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net: hns3: Fix for VF mailbox receiving unknown message
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
2866ccb2 20#include <linux/if_vlan.h>
f2f432f2 21#include <net/rtnetlink.h>
46a3df9f 22#include "hclge_cmd.h"
cacde272 23#include "hclge_dcb.h"
46a3df9f 24#include "hclge_main.h"
dde1a86e 25#include "hclge_mbx.h"
46a3df9f
S		 26#include "hclge_mdio.h"
27#include "hclge_tm.h"
28#include "hnae3.h"
29
30#define HCLGE_NAME "hclge"
31#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35
46a3df9f
S		 36static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
f9fd82a9 39static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 40static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 41static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 42
43static struct hnae3_ae_algo ae_algo;
44
45static const struct pci_device_id ae_algo_pci_tbl[] = {
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 53 /* required last entry */
46a3df9f
S		 54 {0, }
55};
56
2f550a46
YL		 57MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
58
46a3df9f
S		 59static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
60 "Mac Loopback test",
61 "Serdes Loopback test",
62 "Phy Loopback test"
63};
64
65static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
72 {"igu_rx_uni_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
74 {"igu_rx_multi_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
76 {"igu_rx_broad_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
80 {"egu_tx_uni_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
82 {"egu_tx_multi_pkt",
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
84 {"egu_tx_broad_pkt",
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
94 {"ssu_tx_in_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
96 {"ssu_tx_out_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
98 {"ssu_rx_in_num",
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
100 {"ssu_rx_out_num",
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
102};
103
104static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
105 {"igu_rx_err_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
111 {"egu_tx_1588_pkt",
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
117 {"ppp_key_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
119 {"ppp_rlt_drop_num",
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
121 {"ssu_key_drop_num",
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
123 {"pkt_curr_buf_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
125 {"qcn_fb_rcv_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
127 {"qcn_fb_drop_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
211 {"mb_uncopy_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
227};
228
229static const struct hclge_comm_stats_str g_mac_stats_string[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
200a88c6
JS		 286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
91f384f6
JS		 300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
91f384f6
JS		 306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
200a88c6
JS		 336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
91f384f6
JS		 350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
91f384f6
JS		 356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 366
a6c51c26
JS		 367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 391};
392
f5aac71c
FL		 393static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
394 {
395 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
396 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
397 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap = 0x1,
400 },
401};
402
46a3df9f
S		 403static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
404{
405#define HCLGE_64_BIT_CMD_NUM 5
406#define HCLGE_64_BIT_RTN_DATANUM 4
407 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
408 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 409 __le64 *desc_data;
46a3df9f
S		 410 int i, k, n;
411 int ret;
412
413 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
414 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
415 if (ret) {
416 dev_err(&hdev->pdev->dev,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret);
418 return ret;
419 }
420
421 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
422 if (unlikely(i == 0)) {
a90bb9a5 423 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 424 n = HCLGE_64_BIT_RTN_DATANUM - 1;
425 } else {
a90bb9a5 426 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 427 n = HCLGE_64_BIT_RTN_DATANUM;
428 }
429 for (k = 0; k < n; k++) {
a90bb9a5 430 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 431 desc_data++;
432 }
433 }
434
435 return 0;
436}
437
438static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
439{
440 stats->pkt_curr_buf_cnt = 0;
441 stats->pkt_curr_buf_tc0_cnt = 0;
442 stats->pkt_curr_buf_tc1_cnt = 0;
443 stats->pkt_curr_buf_tc2_cnt = 0;
444 stats->pkt_curr_buf_tc3_cnt = 0;
445 stats->pkt_curr_buf_tc4_cnt = 0;
446 stats->pkt_curr_buf_tc5_cnt = 0;
447 stats->pkt_curr_buf_tc6_cnt = 0;
448 stats->pkt_curr_buf_tc7_cnt = 0;
449}
450
451static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
452{
453#define HCLGE_32_BIT_CMD_NUM 8
454#define HCLGE_32_BIT_RTN_DATANUM 8
455
456 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
457 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 458 __le32 *desc_data;
46a3df9f
S		 459 int i, k, n;
460 u64 *data;
461 int ret;
462
463 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
464 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
465
466 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
467 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
468 if (ret) {
469 dev_err(&hdev->pdev->dev,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret);
471
472 return ret;
473 }
474
475 hclge_reset_partial_32bit_counter(all_32_bit_stats);
476 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
477 if (unlikely(i == 0)) {
a90bb9a5
YL		 478 __le16 *desc_data_16bit;
479
46a3df9f 480 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 481 le32_to_cpu(desc[i].data[0]);
482
483 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 484 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 485 le16_to_cpu(*desc_data_16bit);
486
487 desc_data_16bit++;
46a3df9f 488 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 489 le16_to_cpu(*desc_data_16bit);
46a3df9f 490
a90bb9a5 491 desc_data = &desc[i].data[2];
46a3df9f
S		 492 n = HCLGE_32_BIT_RTN_DATANUM - 4;
493 } else {
a90bb9a5 494 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 495 n = HCLGE_32_BIT_RTN_DATANUM;
496 }
497 for (k = 0; k < n; k++) {
a90bb9a5 498 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 499 desc_data++;
500 }
501 }
502
503 return 0;
504}
505
506static int hclge_mac_update_stats(struct hclge_dev *hdev)
507{
91f384f6 508#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 509#define HCLGE_RTN_DATA_NUM 4
510
511 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
512 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 513 __le64 *desc_data;
46a3df9f
S		 514 int i, k, n;
515 int ret;
516
517 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
518 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
519 if (ret) {
520 dev_err(&hdev->pdev->dev,
521 "Get MAC pkt stats fail, status = %d.\n", ret);
522
523 return ret;
524 }
525
526 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
527 if (unlikely(i == 0)) {
a90bb9a5 528 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 529 n = HCLGE_RTN_DATA_NUM - 2;
530 } else {
a90bb9a5 531 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 532 n = HCLGE_RTN_DATA_NUM;
533 }
534 for (k = 0; k < n; k++) {
a90bb9a5 535 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 536 desc_data++;
537 }
538 }
539
540 return 0;
541}
542
543static int hclge_tqps_update_stats(struct hnae3_handle *handle)
544{
545 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
546 struct hclge_vport *vport = hclge_get_vport(handle);
547 struct hclge_dev *hdev = vport->back;
548 struct hnae3_queue *queue;
549 struct hclge_desc desc[1];
550 struct hclge_tqp *tqp;
551 int ret, i;
552
553 for (i = 0; i < kinfo->num_tqps; i++) {
554 queue = handle->kinfo.tqp[i];
555 tqp = container_of(queue, struct hclge_tqp, q);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc[0],
558 HCLGE_OPC_QUERY_RX_STATUS,
559 true);
560
a90bb9a5 561 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 562 ret = hclge_cmd_send(&hdev->hw, desc, 1);
563 if (ret) {
564 dev_err(&hdev->pdev->dev,
565 "Query tqp stat fail, status = %d,queue = %d\n",
566 ret, i);
567 return ret;
568 }
569 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cf72fa63 570 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 571 }
572
573 for (i = 0; i < kinfo->num_tqps; i++) {
574 queue = handle->kinfo.tqp[i];
575 tqp = container_of(queue, struct hclge_tqp, q);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc[0],
578 HCLGE_OPC_QUERY_TX_STATUS,
579 true);
580
a90bb9a5 581 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 582 ret = hclge_cmd_send(&hdev->hw, desc, 1);
583 if (ret) {
584 dev_err(&hdev->pdev->dev,
585 "Query tqp stat fail, status = %d,queue = %d\n",
586 ret, i);
587 return ret;
588 }
589 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cf72fa63 590 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 591 }
592
593 return 0;
594}
595
596static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
597{
598 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
599 struct hclge_tqp *tqp;
600 u64 *buff = data;
601 int i;
602
603 for (i = 0; i < kinfo->num_tqps; i++) {
604 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 605 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 606 }
607
608 for (i = 0; i < kinfo->num_tqps; i++) {
609 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 610 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 611 }
612
613 return buff;
614}
615
616static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
617{
618 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
619
620 return kinfo->num_tqps * (2);
621}
622
623static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
624{
625 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
626 u8 *buff = data;
627 int i = 0;
628
629 for (i = 0; i < kinfo->num_tqps; i++) {
630 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
631 struct hclge_tqp, q);
a6c51c26 632 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 633 tqp->index);
634 buff = buff + ETH_GSTRING_LEN;
635 }
636
637 for (i = 0; i < kinfo->num_tqps; i++) {
638 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
639 struct hclge_tqp, q);
a6c51c26 640 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 641 tqp->index);
642 buff = buff + ETH_GSTRING_LEN;
643 }
644
645 return buff;
646}
647
648static u64 *hclge_comm_get_stats(void *comm_stats,
649 const struct hclge_comm_stats_str strs[],
650 int size, u64 *data)
651{
652 u64 *buf = data;
653 u32 i;
654
655 for (i = 0; i < size; i++)
656 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
657
658 return buf + size;
659}
660
661static u8 *hclge_comm_get_strings(u32 stringset,
662 const struct hclge_comm_stats_str strs[],
663 int size, u8 *data)
664{
665 char *buff = (char *)data;
666 u32 i;
667
668 if (stringset != ETH_SS_STATS)
669 return buff;
670
671 for (i = 0; i < size; i++) {
672 snprintf(buff, ETH_GSTRING_LEN,
673 strs[i].desc);
674 buff = buff + ETH_GSTRING_LEN;
675 }
676
677 return (u8 *)buff;
678}
679
680static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
681 struct net_device_stats *net_stats)
682{
683 net_stats->tx_dropped = 0;
684 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
685 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
686 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
687
200a88c6 688 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 689 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 690 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
691 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
a6c51c26 692 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 693
694 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
695 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
696
a6c51c26 697 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 698 net_stats->rx_length_errors =
699 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
700 net_stats->rx_length_errors +=
200a88c6 701 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 702 net_stats->rx_over_errors =
200a88c6 703 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 704}
705
706static void hclge_update_stats_for_all(struct hclge_dev *hdev)
707{
708 struct hnae3_handle *handle;
709 int status;
710
711 handle = &hdev->vport[0].nic;
712 if (handle->client) {
713 status = hclge_tqps_update_stats(handle);
714 if (status) {
715 dev_err(&hdev->pdev->dev,
716 "Update TQPS stats fail, status = %d.\n",
717 status);
718 }
719 }
720
721 status = hclge_mac_update_stats(hdev);
722 if (status)
723 dev_err(&hdev->pdev->dev,
724 "Update MAC stats fail, status = %d.\n", status);
725
726 status = hclge_32_bit_update_stats(hdev);
727 if (status)
728 dev_err(&hdev->pdev->dev,
729 "Update 32 bit stats fail, status = %d.\n",
730 status);
731
732 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
733}
734
735static void hclge_update_stats(struct hnae3_handle *handle,
736 struct net_device_stats *net_stats)
737{
738 struct hclge_vport *vport = hclge_get_vport(handle);
739 struct hclge_dev *hdev = vport->back;
740 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
741 int status;
742
c5f65480
JS		 743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
744 return;
745
46a3df9f
S		 746 status = hclge_mac_update_stats(hdev);
747 if (status)
748 dev_err(&hdev->pdev->dev,
749 "Update MAC stats fail, status = %d.\n",
750 status);
751
752 status = hclge_32_bit_update_stats(hdev);
753 if (status)
754 dev_err(&hdev->pdev->dev,
755 "Update 32 bit stats fail, status = %d.\n",
756 status);
757
758 status = hclge_64_bit_update_stats(hdev);
759 if (status)
760 dev_err(&hdev->pdev->dev,
761 "Update 64 bit stats fail, status = %d.\n",
762 status);
763
764 status = hclge_tqps_update_stats(handle);
765 if (status)
766 dev_err(&hdev->pdev->dev,
767 "Update TQPS stats fail, status = %d.\n",
768 status);
769
770 hclge_update_netstat(hw_stats, net_stats);
c5f65480
JS		 771
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 773}
774
775static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
776{
777#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
778
779 struct hclge_vport *vport = hclge_get_vport(handle);
780 struct hclge_dev *hdev = vport->back;
781 int count = 0;
782
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
787 */
788 if (stringset == ETH_SS_TEST) {
789 /* clear loopback bit flags at first */
790 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
791 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
792 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
793 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
794 count += 1;
795 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
796 } else {
797 count = -EOPNOTSUPP;
798 }
799 } else if (stringset == ETH_SS_STATS) {
800 count = ARRAY_SIZE(g_mac_stats_string) +
801 ARRAY_SIZE(g_all_32bit_stats_string) +
802 ARRAY_SIZE(g_all_64bit_stats_string) +
803 hclge_tqps_get_sset_count(handle, stringset);
804 }
805
806 return count;
807}
808
809static void hclge_get_strings(struct hnae3_handle *handle,
810 u32 stringset,
811 u8 *data)
812{
813 u8 *p = (char *)data;
814 int size;
815
816 if (stringset == ETH_SS_STATS) {
817 size = ARRAY_SIZE(g_mac_stats_string);
818 p = hclge_comm_get_strings(stringset,
819 g_mac_stats_string,
820 size,
821 p);
822 size = ARRAY_SIZE(g_all_32bit_stats_string);
823 p = hclge_comm_get_strings(stringset,
824 g_all_32bit_stats_string,
825 size,
826 p);
827 size = ARRAY_SIZE(g_all_64bit_stats_string);
828 p = hclge_comm_get_strings(stringset,
829 g_all_64bit_stats_string,
830 size,
831 p);
832 p = hclge_tqps_get_strings(handle, p);
833 } else if (stringset == ETH_SS_TEST) {
834 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
835 memcpy(p,
836 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
837 ETH_GSTRING_LEN);
838 p += ETH_GSTRING_LEN;
839 }
840 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
841 memcpy(p,
842 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
843 ETH_GSTRING_LEN);
844 p += ETH_GSTRING_LEN;
845 }
846 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
847 memcpy(p,
848 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
849 ETH_GSTRING_LEN);
850 p += ETH_GSTRING_LEN;
851 }
852 }
853}
854
855static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
856{
857 struct hclge_vport *vport = hclge_get_vport(handle);
858 struct hclge_dev *hdev = vport->back;
859 u64 *p;
860
861 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
862 g_mac_stats_string,
863 ARRAY_SIZE(g_mac_stats_string),
864 data);
865 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
866 g_all_32bit_stats_string,
867 ARRAY_SIZE(g_all_32bit_stats_string),
868 p);
869 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
870 g_all_64bit_stats_string,
871 ARRAY_SIZE(g_all_64bit_stats_string),
872 p);
873 p = hclge_tqps_get_stats(handle, p);
874}
875
876static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 877 struct hclge_func_status_cmd *status)
46a3df9f
S		 878{
879 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
880 return -EINVAL;
881
882 /* Set the pf to main pf */
883 if (status->pf_state & HCLGE_PF_STATE_MAIN)
884 hdev->flag |= HCLGE_FLAG_MAIN;
885 else
886 hdev->flag &= ~HCLGE_FLAG_MAIN;
887
46a3df9f
S		 888 return 0;
889}
890
891static int hclge_query_function_status(struct hclge_dev *hdev)
892{
d44f9b63 893 struct hclge_func_status_cmd *req;
46a3df9f
S		 894 struct hclge_desc desc;
895 int timeout = 0;
896 int ret;
897
898 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 899 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 900
901 do {
902 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
903 if (ret) {
904 dev_err(&hdev->pdev->dev,
905 "query function status failed %d.\n",
906 ret);
907
908 return ret;
909 }
910
911 /* Check pf reset is done */
912 if (req->pf_state)
913 break;
914 usleep_range(1000, 2000);
915 } while (timeout++ < 5);
916
917 ret = hclge_parse_func_status(hdev, req);
918
919 return ret;
920}
921
922static int hclge_query_pf_resource(struct hclge_dev *hdev)
923{
d44f9b63 924 struct hclge_pf_res_cmd *req;
46a3df9f
S		 925 struct hclge_desc desc;
926 int ret;
927
928 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
929 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930 if (ret) {
931 dev_err(&hdev->pdev->dev,
932 "query pf resource failed %d.\n", ret);
933 return ret;
934 }
935
d44f9b63 936 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 937 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
938 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
939
e92a0843 940 if (hnae3_dev_roce_supported(hdev)) {
887c3820 941 hdev->num_roce_msi =
46a3df9f
S		 942 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
943 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
944
945 /* PF should have NIC vectors and Roce vectors,
946 * NIC vectors are queued before Roce vectors.
947 */
887c3820 948 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 949 } else {
950 hdev->num_msi =
951 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
952 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
953 }
954
955 return 0;
956}
957
958static int hclge_parse_speed(int speed_cmd, int *speed)
959{
960 switch (speed_cmd) {
961 case 6:
962 *speed = HCLGE_MAC_SPEED_10M;
963 break;
964 case 7:
965 *speed = HCLGE_MAC_SPEED_100M;
966 break;
967 case 0:
968 *speed = HCLGE_MAC_SPEED_1G;
969 break;
970 case 1:
971 *speed = HCLGE_MAC_SPEED_10G;
972 break;
973 case 2:
974 *speed = HCLGE_MAC_SPEED_25G;
975 break;
976 case 3:
977 *speed = HCLGE_MAC_SPEED_40G;
978 break;
979 case 4:
980 *speed = HCLGE_MAC_SPEED_50G;
981 break;
982 case 5:
983 *speed = HCLGE_MAC_SPEED_100G;
984 break;
985 default:
986 return -EINVAL;
987 }
988
989 return 0;
990}
991
0979aa0b
FL		 992static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
993 u8 speed_ability)
994{
995 unsigned long *supported = hdev->hw.mac.supported;
996
997 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
998 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
999 supported);
1000
1001 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1002 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1003 supported);
1004
1005 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1006 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1007 supported);
1008
1009 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1010 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1011 supported);
1012
1013 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1014 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1015 supported);
1016
1017 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1018 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1019}
1020
1021static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1022{
1023 u8 media_type = hdev->hw.mac.media_type;
1024
1025 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1026 return;
1027
1028 hclge_parse_fiber_link_mode(hdev, speed_ability);
1029}
1030
46a3df9f
S		 1031static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1032{
d44f9b63 1033 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1034 u64 mac_addr_tmp_high;
1035 u64 mac_addr_tmp;
1036 int i;
1037
d44f9b63 1038 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1039
1040 /* get the configuration */
1041 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1042 HCLGE_CFG_VMDQ_M,
1043 HCLGE_CFG_VMDQ_S);
1044 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1045 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1046 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1047 HCLGE_CFG_TQP_DESC_N_M,
1048 HCLGE_CFG_TQP_DESC_N_S);
1049
1050 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
1051 HCLGE_CFG_PHY_ADDR_M,
1052 HCLGE_CFG_PHY_ADDR_S);
1053 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
1054 HCLGE_CFG_MEDIA_TP_M,
1055 HCLGE_CFG_MEDIA_TP_S);
1056 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
1057 HCLGE_CFG_RX_BUF_LEN_M,
1058 HCLGE_CFG_RX_BUF_LEN_S);
1059 /* get mac_address */
1060 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1061 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
1062 HCLGE_CFG_MAC_ADDR_H_M,
1063 HCLGE_CFG_MAC_ADDR_H_S);
1064
1065 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1066
1067 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
1068 HCLGE_CFG_DEFAULT_SPEED_M,
1069 HCLGE_CFG_DEFAULT_SPEED_S);
0e7a40cd
PL		 1070 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
1071 HCLGE_CFG_RSS_SIZE_M,
1072 HCLGE_CFG_RSS_SIZE_S);
1073
46a3df9f
S		 1074 for (i = 0; i < ETH_ALEN; i++)
1075 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1076
d44f9b63 1077 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 1078 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
0979aa0b
FL		 1079
1080 cfg->speed_ability = hnae_get_field(__le32_to_cpu(req->param[1]),
1081 HCLGE_CFG_SPEED_ABILITY_M,
1082 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 1083}
1084
1085/* hclge_get_cfg: query the static parameter from flash
1086 * @hdev: pointer to struct hclge_dev
1087 * @hcfg: the config structure to be getted
1088 */
1089static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1090{
1091 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1092 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1093 int i, ret;
1094
1095 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1096 u32 offset = 0;
1097
d44f9b63 1098 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1099 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1100 true);
a90bb9a5 1101 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1102 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1103 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1104 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1105 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1106 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1107 }
1108
1109 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1110 if (ret) {
1111 dev_err(&hdev->pdev->dev,
1112 "get config failed %d.\n", ret);
1113 return ret;
1114 }
1115
1116 hclge_parse_cfg(hcfg, desc);
1117 return 0;
1118}
1119
1120static int hclge_get_cap(struct hclge_dev *hdev)
1121{
1122 int ret;
1123
1124 ret = hclge_query_function_status(hdev);
1125 if (ret) {
1126 dev_err(&hdev->pdev->dev,
1127 "query function status error %d.\n", ret);
1128 return ret;
1129 }
1130
1131 /* get pf resource */
1132 ret = hclge_query_pf_resource(hdev);
1133 if (ret) {
1134 dev_err(&hdev->pdev->dev,
1135 "query pf resource error %d.\n", ret);
1136 return ret;
1137 }
1138
1139 return 0;
1140}
1141
1142static int hclge_configure(struct hclge_dev *hdev)
1143{
1144 struct hclge_cfg cfg;
1145 int ret, i;
1146
1147 ret = hclge_get_cfg(hdev, &cfg);
1148 if (ret) {
1149 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1150 return ret;
1151 }
1152
1153 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1154 hdev->base_tqp_pid = 0;
0e7a40cd 1155 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1156 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1157 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1158 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1159 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1160 hdev->num_desc = cfg.tqp_desc_num;
1161 hdev->tm_info.num_pg = 1;
cacde272 1162 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1163 hdev->tm_info.hw_pfc_map = 0;
1164
1165 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1166 if (ret) {
1167 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1168 return ret;
1169 }
1170
0979aa0b
FL		 1171 hclge_parse_link_mode(hdev, cfg.speed_ability);
1172
cacde272
YL		 1173 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1174 (hdev->tc_max < 1)) {
46a3df9f 1175 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1176 hdev->tc_max);
1177 hdev->tc_max = 1;
46a3df9f
S		 1178 }
1179
cacde272
YL		 1180 /* Dev does not support DCB */
1181 if (!hnae3_dev_dcb_supported(hdev)) {
1182 hdev->tc_max = 1;
1183 hdev->pfc_max = 0;
1184 } else {
1185 hdev->pfc_max = hdev->tc_max;
1186 }
1187
1188 hdev->tm_info.num_tc = hdev->tc_max;
1189
46a3df9f 1190 /* Currently not support uncontiuous tc */
cacde272 1191 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1192 hnae_set_bit(hdev->hw_tc_map, i, 1);
1193
71b83869 1194 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1195
1196 return ret;
1197}
1198
1199static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1200 int tso_mss_max)
1201{
d44f9b63 1202 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1203 struct hclge_desc desc;
a90bb9a5 1204 u16 tso_mss;
46a3df9f
S		 1205
1206 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1207
d44f9b63 1208 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1209
1210 tso_mss = 0;
1211 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1212 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1213 req->tso_mss_min = cpu_to_le16(tso_mss);
1214
1215 tso_mss = 0;
1216 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1217 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1218 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1219
1220 return hclge_cmd_send(&hdev->hw, &desc, 1);
1221}
1222
1223static int hclge_alloc_tqps(struct hclge_dev *hdev)
1224{
1225 struct hclge_tqp *tqp;
1226 int i;
1227
1228 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1229 sizeof(struct hclge_tqp), GFP_KERNEL);
1230 if (!hdev->htqp)
1231 return -ENOMEM;
1232
1233 tqp = hdev->htqp;
1234
1235 for (i = 0; i < hdev->num_tqps; i++) {
1236 tqp->dev = &hdev->pdev->dev;
1237 tqp->index = i;
1238
1239 tqp->q.ae_algo = &ae_algo;
1240 tqp->q.buf_size = hdev->rx_buf_len;
1241 tqp->q.desc_num = hdev->num_desc;
1242 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1243 i * HCLGE_TQP_REG_SIZE;
1244
1245 tqp++;
1246 }
1247
1248 return 0;
1249}
1250
1251static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1252 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1253{
d44f9b63 1254 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1255 struct hclge_desc desc;
1256 int ret;
1257
1258 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1259
d44f9b63 1260 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1261 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1262 req->tqp_vf = func_id;
46a3df9f
S		 1263 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1264 1 << HCLGE_TQP_MAP_EN_B;
1265 req->tqp_vid = cpu_to_le16(tqp_vid);
1266
1267 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1268 if (ret) {
1269 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1270 ret);
1271 return ret;
1272 }
1273
1274 return 0;
1275}
1276
1277static int hclge_assign_tqp(struct hclge_vport *vport,
1278 struct hnae3_queue **tqp, u16 num_tqps)
1279{
1280 struct hclge_dev *hdev = vport->back;
7df7dad6 1281 int i, alloced;
46a3df9f
S		 1282
1283 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1284 alloced < num_tqps; i++) {
1285 if (!hdev->htqp[i].alloced) {
1286 hdev->htqp[i].q.handle = &vport->nic;
1287 hdev->htqp[i].q.tqp_index = alloced;
1288 tqp[alloced] = &hdev->htqp[i].q;
1289 hdev->htqp[i].alloced = true;
46a3df9f
S		 1290 alloced++;
1291 }
1292 }
1293 vport->alloc_tqps = num_tqps;
1294
1295 return 0;
1296}
1297
1298static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1299{
1300 struct hnae3_handle *nic = &vport->nic;
1301 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1302 struct hclge_dev *hdev = vport->back;
1303 int i, ret;
1304
1305 kinfo->num_desc = hdev->num_desc;
1306 kinfo->rx_buf_len = hdev->rx_buf_len;
1307 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1308 kinfo->rss_size
1309 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1310 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1311
1312 for (i = 0; i < HNAE3_MAX_TC; i++) {
1313 if (hdev->hw_tc_map & BIT(i)) {
1314 kinfo->tc_info[i].enable = true;
1315 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1316 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1317 kinfo->tc_info[i].tc = i;
1318 } else {
1319 /* Set to default queue if TC is disable */
1320 kinfo->tc_info[i].enable = false;
1321 kinfo->tc_info[i].tqp_offset = 0;
1322 kinfo->tc_info[i].tqp_count = 1;
1323 kinfo->tc_info[i].tc = 0;
1324 }
1325 }
1326
1327 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1328 sizeof(struct hnae3_queue *), GFP_KERNEL);
1329 if (!kinfo->tqp)
1330 return -ENOMEM;
1331
1332 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1333 if (ret) {
1334 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1335 return -EINVAL;
1336 }
1337
1338 return 0;
1339}
1340
7df7dad6
L		 1341static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1342 struct hclge_vport *vport)
1343{
1344 struct hnae3_handle *nic = &vport->nic;
1345 struct hnae3_knic_private_info *kinfo;
1346 u16 i;
1347
1348 kinfo = &nic->kinfo;
1349 for (i = 0; i < kinfo->num_tqps; i++) {
1350 struct hclge_tqp *q =
1351 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1352 bool is_pf;
1353 int ret;
1354
1355 is_pf = !(vport->vport_id);
1356 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1357 i, is_pf);
1358 if (ret)
1359 return ret;
1360 }
1361
1362 return 0;
1363}
1364
1365static int hclge_map_tqp(struct hclge_dev *hdev)
1366{
1367 struct hclge_vport *vport = hdev->vport;
1368 u16 i, num_vport;
1369
1370 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1371 for (i = 0; i < num_vport; i++) {
1372 int ret;
1373
1374 ret = hclge_map_tqp_to_vport(hdev, vport);
1375 if (ret)
1376 return ret;
1377
1378 vport++;
1379 }
1380
1381 return 0;
1382}
1383
46a3df9f
S		 1384static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1385{
1386 /* this would be initialized later */
1387}
1388
1389static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1390{
1391 struct hnae3_handle *nic = &vport->nic;
1392 struct hclge_dev *hdev = vport->back;
1393 int ret;
1394
1395 nic->pdev = hdev->pdev;
1396 nic->ae_algo = &ae_algo;
1397 nic->numa_node_mask = hdev->numa_node_mask;
1398
1399 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1400 ret = hclge_knic_setup(vport, num_tqps);
1401 if (ret) {
1402 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1403 ret);
1404 return ret;
1405 }
1406 } else {
1407 hclge_unic_setup(vport, num_tqps);
1408 }
1409
1410 return 0;
1411}
1412
1413static int hclge_alloc_vport(struct hclge_dev *hdev)
1414{
1415 struct pci_dev *pdev = hdev->pdev;
1416 struct hclge_vport *vport;
1417 u32 tqp_main_vport;
1418 u32 tqp_per_vport;
1419 int num_vport, i;
1420 int ret;
1421
1422 /* We need to alloc a vport for main NIC of PF */
1423 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1424
38e62046
HT		 1425 if (hdev->num_tqps < num_vport) {
1426 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1427 hdev->num_tqps, num_vport);
1428 return -EINVAL;
1429 }
46a3df9f
S		 1430
1431 /* Alloc the same number of TQPs for every vport */
1432 tqp_per_vport = hdev->num_tqps / num_vport;
1433 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1434
1435 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1436 GFP_KERNEL);
1437 if (!vport)
1438 return -ENOMEM;
1439
1440 hdev->vport = vport;
1441 hdev->num_alloc_vport = num_vport;
1442
2312e050
FL		 1443 if (IS_ENABLED(CONFIG_PCI_IOV))
1444 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1445
1446 for (i = 0; i < num_vport; i++) {
1447 vport->back = hdev;
1448 vport->vport_id = i;
1449
1450 if (i == 0)
1451 ret = hclge_vport_setup(vport, tqp_main_vport);
1452 else
1453 ret = hclge_vport_setup(vport, tqp_per_vport);
1454 if (ret) {
1455 dev_err(&pdev->dev,
1456 "vport setup failed for vport %d, %d\n",
1457 i, ret);
1458 return ret;
1459 }
1460
1461 vport++;
1462 }
1463
1464 return 0;
1465}
1466
acf61ecd
YL		 1467static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1468 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1469{
1470/* TX buffer size is unit by 128 byte */
1471#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1472#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1473 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1474 struct hclge_desc desc;
1475 int ret;
1476 u8 i;
1477
d44f9b63 1478 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1479
1480 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1481 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1482 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1483
46a3df9f
S		 1484 req->tx_pkt_buff[i] =
1485 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1486 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1487 }
46a3df9f
S		 1488
1489 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1490 if (ret) {
1491 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1492 ret);
1493 return ret;
1494 }
1495
1496 return 0;
1497}
1498
acf61ecd
YL		 1499static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1500 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1501{
acf61ecd 1502 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1503
1504 if (ret) {
1505 dev_err(&hdev->pdev->dev,
1506 "tx buffer alloc failed %d\n", ret);
1507 return ret;
1508 }
1509
1510 return 0;
1511}
1512
1513static int hclge_get_tc_num(struct hclge_dev *hdev)
1514{
1515 int i, cnt = 0;
1516
1517 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1518 if (hdev->hw_tc_map & BIT(i))
1519 cnt++;
1520 return cnt;
1521}
1522
1523static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1524{
1525 int i, cnt = 0;
1526
1527 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1528 if (hdev->hw_tc_map & BIT(i) &&
1529 hdev->tm_info.hw_pfc_map & BIT(i))
1530 cnt++;
1531 return cnt;
1532}
1533
1534/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1535static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1536 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1537{
1538 struct hclge_priv_buf *priv;
1539 int i, cnt = 0;
1540
1541 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1542 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1543 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1544 priv->enable)
1545 cnt++;
1546 }
1547
1548 return cnt;
1549}
1550
1551/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1552static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1553 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1554{
1555 struct hclge_priv_buf *priv;
1556 int i, cnt = 0;
1557
1558 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1559 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1560 if (hdev->hw_tc_map & BIT(i) &&
1561 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1562 priv->enable)
1563 cnt++;
1564 }
1565
1566 return cnt;
1567}
1568
acf61ecd 1569static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1570{
1571 struct hclge_priv_buf *priv;
1572 u32 rx_priv = 0;
1573 int i;
1574
1575 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1576 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1577 if (priv->enable)
1578 rx_priv += priv->buf_size;
1579 }
1580 return rx_priv;
1581}
1582
acf61ecd 1583static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1584{
1585 u32 i, total_tx_size = 0;
1586
1587 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1588 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1589
1590 return total_tx_size;
1591}
1592
acf61ecd
YL		 1593static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1594 struct hclge_pkt_buf_alloc *buf_alloc,
1595 u32 rx_all)
46a3df9f
S		 1596{
1597 u32 shared_buf_min, shared_buf_tc, shared_std;
1598 int tc_num, pfc_enable_num;
1599 u32 shared_buf;
1600 u32 rx_priv;
1601 int i;
1602
1603 tc_num = hclge_get_tc_num(hdev);
1604 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1605
d221df4e
YL		 1606 if (hnae3_dev_dcb_supported(hdev))
1607 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1608 else
1609 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1610
46a3df9f
S		 1611 shared_buf_tc = pfc_enable_num * hdev->mps +
1612 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1613 hdev->mps;
1614 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1615
acf61ecd 1616 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1617 if (rx_all <= rx_priv + shared_std)
1618 return false;
1619
1620 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1621 buf_alloc->s_buf.buf_size = shared_buf;
1622 buf_alloc->s_buf.self.high = shared_buf;
1623 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1624
1625 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1626 if ((hdev->hw_tc_map & BIT(i)) &&
1627 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1628 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1629 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1630 } else {
acf61ecd
YL		 1631 buf_alloc->s_buf.tc_thrd[i].low = 0;
1632 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1633 }
1634 }
1635
1636 return true;
1637}
1638
acf61ecd
YL		 1639static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1640 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1641{
1642 u32 i, total_size;
1643
1644 total_size = hdev->pkt_buf_size;
1645
1646 /* alloc tx buffer for all enabled tc */
1647 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1648 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1649
1650 if (total_size < HCLGE_DEFAULT_TX_BUF)
1651 return -ENOMEM;
1652
1653 if (hdev->hw_tc_map & BIT(i))
1654 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1655 else
1656 priv->tx_buf_size = 0;
1657
1658 total_size -= priv->tx_buf_size;
1659 }
1660
1661 return 0;
1662}
1663
46a3df9f
S		 1664/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1665 * @hdev: pointer to struct hclge_dev
acf61ecd 1666 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1667 * @return: 0: calculate sucessful, negative: fail
1668 */
1db9b1bf
YL		 1669static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1670 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1671{
9ffe79a9 1672 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1673 int no_pfc_priv_num, pfc_priv_num;
1674 struct hclge_priv_buf *priv;
1675 int i;
1676
acf61ecd 1677 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1678
d602a525
YL		 1679 /* When DCB is not supported, rx private
1680 * buffer is not allocated.
1681 */
1682 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1683 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1684 return -ENOMEM;
1685
1686 return 0;
1687 }
1688
46a3df9f
S		 1689 /* step 1, try to alloc private buffer for all enabled tc */
1690 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1691 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1692 if (hdev->hw_tc_map & BIT(i)) {
1693 priv->enable = 1;
1694 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1695 priv->wl.low = hdev->mps;
1696 priv->wl.high = priv->wl.low + hdev->mps;
1697 priv->buf_size = priv->wl.high +
1698 HCLGE_DEFAULT_DV;
1699 } else {
1700 priv->wl.low = 0;
1701 priv->wl.high = 2 * hdev->mps;
1702 priv->buf_size = priv->wl.high;
1703 }
bb1fe9ea
YL		 1704 } else {
1705 priv->enable = 0;
1706 priv->wl.low = 0;
1707 priv->wl.high = 0;
1708 priv->buf_size = 0;
46a3df9f
S		 1709 }
1710 }
1711
acf61ecd 1712 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1713 return 0;
1714
1715 /* step 2, try to decrease the buffer size of
1716 * no pfc TC's private buffer
1717 */
1718 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1719 priv = &buf_alloc->priv_buf[i];
46a3df9f 1720
bb1fe9ea
YL		 1721 priv->enable = 0;
1722 priv->wl.low = 0;
1723 priv->wl.high = 0;
1724 priv->buf_size = 0;
1725
1726 if (!(hdev->hw_tc_map & BIT(i)))
1727 continue;
1728
1729 priv->enable = 1;
46a3df9f
S		 1730
1731 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1732 priv->wl.low = 128;
1733 priv->wl.high = priv->wl.low + hdev->mps;
1734 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1735 } else {
1736 priv->wl.low = 0;
1737 priv->wl.high = hdev->mps;
1738 priv->buf_size = priv->wl.high;
1739 }
1740 }
1741
acf61ecd 1742 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1743 return 0;
1744
1745 /* step 3, try to reduce the number of pfc disabled TCs,
1746 * which have private buffer
1747 */
1748 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1749 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1750
1751 /* let the last to be cleared first */
1752 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1753 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1754
1755 if (hdev->hw_tc_map & BIT(i) &&
1756 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1757 /* Clear the no pfc TC private buffer */
1758 priv->wl.low = 0;
1759 priv->wl.high = 0;
1760 priv->buf_size = 0;
1761 priv->enable = 0;
1762 no_pfc_priv_num--;
1763 }
1764
acf61ecd 1765 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1766 no_pfc_priv_num == 0)
1767 break;
1768 }
1769
acf61ecd 1770 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1771 return 0;
1772
1773 /* step 4, try to reduce the number of pfc enabled TCs
1774 * which have private buffer.
1775 */
acf61ecd 1776 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1777
1778 /* let the last to be cleared first */
1779 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1780 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1781
1782 if (hdev->hw_tc_map & BIT(i) &&
1783 hdev->tm_info.hw_pfc_map & BIT(i)) {
1784 /* Reduce the number of pfc TC with private buffer */
1785 priv->wl.low = 0;
1786 priv->enable = 0;
1787 priv->wl.high = 0;
1788 priv->buf_size = 0;
1789 pfc_priv_num--;
1790 }
1791
acf61ecd 1792 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1793 pfc_priv_num == 0)
1794 break;
1795 }
acf61ecd 1796 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1797 return 0;
1798
1799 return -ENOMEM;
1800}
1801
acf61ecd
YL		 1802static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1803 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1804{
d44f9b63 1805 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1806 struct hclge_desc desc;
1807 int ret;
1808 int i;
1809
1810 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1811 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1812
1813 /* Alloc private buffer TCs */
1814 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1815 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1816
1817 req->buf_num[i] =
1818 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1819 req->buf_num[i] |=
5bca3b94 1820 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1821 }
1822
b8c8bf47 1823 req->shared_buf =
acf61ecd 1824 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1825 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1826
46a3df9f
S		 1827 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1828 if (ret) {
1829 dev_err(&hdev->pdev->dev,
1830 "rx private buffer alloc cmd failed %d\n", ret);
1831 return ret;
1832 }
1833
1834 return 0;
1835}
1836
1837#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1838
acf61ecd
YL		 1839static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1840 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1841{
1842 struct hclge_rx_priv_wl_buf *req;
1843 struct hclge_priv_buf *priv;
1844 struct hclge_desc desc[2];
1845 int i, j;
1846 int ret;
1847
1848 for (i = 0; i < 2; i++) {
1849 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1850 false);
1851 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1852
1853 /* The first descriptor set the NEXT bit to 1 */
1854 if (i == 0)
1855 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1856 else
1857 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1858
1859 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1860 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1861
1862 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1863 req->tc_wl[j].high =
1864 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1865 req->tc_wl[j].high |=
1866 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1867 HCLGE_RX_PRIV_EN_B);
1868 req->tc_wl[j].low =
1869 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1870 req->tc_wl[j].low |=
1871 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1872 HCLGE_RX_PRIV_EN_B);
1873 }
1874 }
1875
1876 /* Send 2 descriptor at one time */
1877 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1878 if (ret) {
1879 dev_err(&hdev->pdev->dev,
1880 "rx private waterline config cmd failed %d\n",
1881 ret);
1882 return ret;
1883 }
1884 return 0;
1885}
1886
acf61ecd
YL		 1887static int hclge_common_thrd_config(struct hclge_dev *hdev,
1888 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1889{
acf61ecd 1890 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1891 struct hclge_rx_com_thrd *req;
1892 struct hclge_desc desc[2];
1893 struct hclge_tc_thrd *tc;
1894 int i, j;
1895 int ret;
1896
1897 for (i = 0; i < 2; i++) {
1898 hclge_cmd_setup_basic_desc(&desc[i],
1899 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1900 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1901
1902 /* The first descriptor set the NEXT bit to 1 */
1903 if (i == 0)
1904 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1905 else
1906 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1907
1908 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1909 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1910
1911 req->com_thrd[j].high =
1912 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1913 req->com_thrd[j].high |=
1914 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1915 HCLGE_RX_PRIV_EN_B);
1916 req->com_thrd[j].low =
1917 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1918 req->com_thrd[j].low |=
1919 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1920 HCLGE_RX_PRIV_EN_B);
1921 }
1922 }
1923
1924 /* Send 2 descriptors at one time */
1925 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1926 if (ret) {
1927 dev_err(&hdev->pdev->dev,
1928 "common threshold config cmd failed %d\n", ret);
1929 return ret;
1930 }
1931 return 0;
1932}
1933
acf61ecd
YL		 1934static int hclge_common_wl_config(struct hclge_dev *hdev,
1935 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1936{
acf61ecd 1937 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1938 struct hclge_rx_com_wl *req;
1939 struct hclge_desc desc;
1940 int ret;
1941
1942 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1943
1944 req = (struct hclge_rx_com_wl *)desc.data;
1945 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1946 req->com_wl.high |=
1947 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1948 HCLGE_RX_PRIV_EN_B);
1949
1950 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1951 req->com_wl.low |=
1952 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1953 HCLGE_RX_PRIV_EN_B);
1954
1955 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1956 if (ret) {
1957 dev_err(&hdev->pdev->dev,
1958 "common waterline config cmd failed %d\n", ret);
1959 return ret;
1960 }
1961
1962 return 0;
1963}
1964
1965int hclge_buffer_alloc(struct hclge_dev *hdev)
1966{
acf61ecd 1967 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1968 int ret;
1969
acf61ecd
YL		 1970 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1971 if (!pkt_buf)
46a3df9f
S		 1972 return -ENOMEM;
1973
acf61ecd 1974 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1975 if (ret) {
1976 dev_err(&hdev->pdev->dev,
1977 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1978 goto out;
9ffe79a9
YL		 1979 }
1980
acf61ecd 1981 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1982 if (ret) {
1983 dev_err(&hdev->pdev->dev,
1984 "could not alloc tx buffers %d\n", ret);
acf61ecd 1985 goto out;
46a3df9f
S		 1986 }
1987
acf61ecd 1988 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1989 if (ret) {
1990 dev_err(&hdev->pdev->dev,
1991 "could not calc rx priv buffer size for all TCs %d\n",
1992 ret);
acf61ecd 1993 goto out;
46a3df9f
S		 1994 }
1995
acf61ecd 1996 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1997 if (ret) {
1998 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1999 ret);
acf61ecd 2000 goto out;
46a3df9f
S		 2001 }
2002
2daf4a65 2003 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 2004 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 2005 if (ret) {
2006 dev_err(&hdev->pdev->dev,
2007 "could not configure rx private waterline %d\n",
2008 ret);
acf61ecd 2009 goto out;
2daf4a65 2010 }
46a3df9f 2011
acf61ecd 2012 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 2013 if (ret) {
2014 dev_err(&hdev->pdev->dev,
2015 "could not configure common threshold %d\n",
2016 ret);
acf61ecd 2017 goto out;
2daf4a65 2018 }
46a3df9f
S		 2019 }
2020
acf61ecd
YL		 2021 ret = hclge_common_wl_config(hdev, pkt_buf);
2022 if (ret)
46a3df9f
S		 2023 dev_err(&hdev->pdev->dev,
2024 "could not configure common waterline %d\n", ret);
46a3df9f 2025
acf61ecd
YL		 2026out:
2027 kfree(pkt_buf);
2028 return ret;
46a3df9f
S		 2029}
2030
2031static int hclge_init_roce_base_info(struct hclge_vport *vport)
2032{
2033 struct hnae3_handle *roce = &vport->roce;
2034 struct hnae3_handle *nic = &vport->nic;
2035
887c3820 2036 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2037
2038 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2039 vport->back->num_msi_left == 0)
2040 return -EINVAL;
2041
2042 roce->rinfo.base_vector = vport->back->roce_base_vector;
2043
2044 roce->rinfo.netdev = nic->kinfo.netdev;
2045 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2046
2047 roce->pdev = nic->pdev;
2048 roce->ae_algo = nic->ae_algo;
2049 roce->numa_node_mask = nic->numa_node_mask;
2050
2051 return 0;
2052}
2053
887c3820 2054static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2055{
2056 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2057 int vectors;
2058 int i;
46a3df9f 2059
887c3820
SM		 2060 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2061 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2062 if (vectors < 0) {
2063 dev_err(&pdev->dev,
2064 "failed(%d) to allocate MSI/MSI-X vectors\n",
2065 vectors);
2066 return vectors;
46a3df9f 2067 }
887c3820
SM		 2068 if (vectors < hdev->num_msi)
2069 dev_warn(&hdev->pdev->dev,
2070 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2071 hdev->num_msi, vectors);
46a3df9f 2072
887c3820
SM		 2073 hdev->num_msi = vectors;
2074 hdev->num_msi_left = vectors;
2075 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2076 hdev->roce_base_vector = hdev->base_msi_vector +
2077 HCLGE_ROCE_VECTOR_OFFSET;
2078
46a3df9f
S		 2079 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2080 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2081 if (!hdev->vector_status) {
2082 pci_free_irq_vectors(pdev);
46a3df9f 2083 return -ENOMEM;
887c3820 2084 }
46a3df9f
S		 2085
2086 for (i = 0; i < hdev->num_msi; i++)
2087 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2088
887c3820
SM		 2089 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2090 sizeof(int), GFP_KERNEL);
2091 if (!hdev->vector_irq) {
2092 pci_free_irq_vectors(pdev);
2093 return -ENOMEM;
46a3df9f 2094 }
46a3df9f
S		 2095
2096 return 0;
2097}
2098
2099static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2100{
2101 struct hclge_mac *mac = &hdev->hw.mac;
2102
2103 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2104 mac->duplex = (u8)duplex;
2105 else
2106 mac->duplex = HCLGE_MAC_FULL;
2107
2108 mac->speed = speed;
2109}
2110
2111int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2112{
d44f9b63 2113 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2114 struct hclge_desc desc;
2115 int ret;
2116
d44f9b63 2117 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2118
2119 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2120
2121 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2122
2123 switch (speed) {
2124 case HCLGE_MAC_SPEED_10M:
2125 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2126 HCLGE_CFG_SPEED_S, 6);
2127 break;
2128 case HCLGE_MAC_SPEED_100M:
2129 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2130 HCLGE_CFG_SPEED_S, 7);
2131 break;
2132 case HCLGE_MAC_SPEED_1G:
2133 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2134 HCLGE_CFG_SPEED_S, 0);
2135 break;
2136 case HCLGE_MAC_SPEED_10G:
2137 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2138 HCLGE_CFG_SPEED_S, 1);
2139 break;
2140 case HCLGE_MAC_SPEED_25G:
2141 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2142 HCLGE_CFG_SPEED_S, 2);
2143 break;
2144 case HCLGE_MAC_SPEED_40G:
2145 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2146 HCLGE_CFG_SPEED_S, 3);
2147 break;
2148 case HCLGE_MAC_SPEED_50G:
2149 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2150 HCLGE_CFG_SPEED_S, 4);
2151 break;
2152 case HCLGE_MAC_SPEED_100G:
2153 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2154 HCLGE_CFG_SPEED_S, 5);
2155 break;
2156 default:
d7629e74 2157 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2158 return -EINVAL;
2159 }
2160
2161 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2162 1);
2163
2164 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2165 if (ret) {
2166 dev_err(&hdev->pdev->dev,
2167 "mac speed/duplex config cmd failed %d.\n", ret);
2168 return ret;
2169 }
2170
2171 hclge_check_speed_dup(hdev, duplex, speed);
2172
2173 return 0;
2174}
2175
2176static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2177 u8 duplex)
2178{
2179 struct hclge_vport *vport = hclge_get_vport(handle);
2180 struct hclge_dev *hdev = vport->back;
2181
2182 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2183}
2184
2185static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2186 u8 *duplex)
2187{
d44f9b63 2188 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2189 struct hclge_desc desc;
2190 int speed_tmp;
2191 int ret;
2192
d44f9b63 2193 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2194
2195 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2196 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2197 if (ret) {
2198 dev_err(&hdev->pdev->dev,
2199 "mac speed/autoneg/duplex query cmd failed %d\n",
2200 ret);
2201 return ret;
2202 }
2203
2204 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2205 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2206 HCLGE_QUERY_SPEED_S);
2207
2208 ret = hclge_parse_speed(speed_tmp, speed);
2209 if (ret) {
2210 dev_err(&hdev->pdev->dev,
2211 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2212 return -EIO;
2213 }
2214
2215 return 0;
2216}
2217
46a3df9f
S		 2218static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2219{
d44f9b63 2220 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2221 struct hclge_desc desc;
a90bb9a5 2222 u32 flag = 0;
46a3df9f
S		 2223 int ret;
2224
2225 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2226
d44f9b63 2227 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2228 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2229 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2230
2231 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2232 if (ret) {
2233 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2234 ret);
2235 return ret;
2236 }
2237
2238 return 0;
2239}
2240
2241static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2242{
2243 struct hclge_vport *vport = hclge_get_vport(handle);
2244 struct hclge_dev *hdev = vport->back;
2245
2246 return hclge_set_autoneg_en(hdev, enable);
2247}
2248
2249static int hclge_get_autoneg(struct hnae3_handle *handle)
2250{
2251 struct hclge_vport *vport = hclge_get_vport(handle);
2252 struct hclge_dev *hdev = vport->back;
27b5bf49
FL		 2253 struct phy_device *phydev = hdev->hw.mac.phydev;
2254
2255 if (phydev)
2256 return phydev->autoneg;
46a3df9f
S		 2257
2258 return hdev->hw.mac.autoneg;
2259}
2260
7564094c
PL		 2261static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2262 bool mask_vlan,
2263 u8 *mac_mask)
2264{
2265 struct hclge_mac_vlan_mask_entry_cmd *req;
2266 struct hclge_desc desc;
2267 int status;
2268
2269 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2270 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2271
2272 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2273 mask_vlan ? 1 : 0);
2274 ether_addr_copy(req->mac_mask, mac_mask);
2275
2276 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2277 if (status)
2278 dev_err(&hdev->pdev->dev,
2279 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2280 status);
2281
2282 return status;
2283}
2284
46a3df9f
S		 2285static int hclge_mac_init(struct hclge_dev *hdev)
2286{
f9fd82a9
FL		 2287 struct hnae3_handle *handle = &hdev->vport[0].nic;
2288 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2289 struct hclge_mac *mac = &hdev->hw.mac;
7564094c 2290 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
40cca1c5 2291 struct hclge_vport *vport;
f9fd82a9 2292 int mtu;
46a3df9f 2293 int ret;
40cca1c5 2294 int i;
46a3df9f
S		 2295
2296 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2297 if (ret) {
2298 dev_err(&hdev->pdev->dev,
2299 "Config mac speed dup fail ret=%d\n", ret);
2300 return ret;
2301 }
2302
2303 mac->link = 0;
2304
46a3df9f 2305 /* Initialize the MTA table work mode */
46a3df9f
S		 2306 hdev->enable_mta = true;
2307 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2308
2309 ret = hclge_set_mta_filter_mode(hdev,
2310 hdev->mta_mac_sel_type,
2311 hdev->enable_mta);
2312 if (ret) {
2313 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2314 ret);
2315 return ret;
2316 }
2317
40cca1c5
XW		 2318 for (i = 0; i < hdev->num_alloc_vport; i++) {
2319 vport = &hdev->vport[i];
2320 vport->accept_mta_mc = false;
2321
2322 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2323 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2324 if (ret) {
2325 dev_err(&hdev->pdev->dev,
2326 "set mta filter mode fail ret=%d\n", ret);
2327 return ret;
2328 }
7564094c
PL		 2329 }
2330
2331 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
f9fd82a9 2332 if (ret) {
7564094c
PL		 2333 dev_err(&hdev->pdev->dev,
2334 "set default mac_vlan_mask fail ret=%d\n", ret);
f9fd82a9
FL		 2335 return ret;
2336 }
7564094c 2337
f9fd82a9
FL		 2338 if (netdev)
2339 mtu = netdev->mtu;
2340 else
2341 mtu = ETH_DATA_LEN;
2342
2343 ret = hclge_set_mtu(handle, mtu);
2344 if (ret) {
2345 dev_err(&hdev->pdev->dev,
2346 "set mtu failed ret=%d\n", ret);
2347 return ret;
2348 }
2349
2350 return 0;
46a3df9f
S		 2351}
2352
c1a81619
SM		 2353static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2354{
2355 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2356 schedule_work(&hdev->mbx_service_task);
2357}
2358
cb1b9f77
SM		 2359static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2360{
2361 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2362 schedule_work(&hdev->rst_service_task);
2363}
2364
46a3df9f
S		 2365static void hclge_task_schedule(struct hclge_dev *hdev)
2366{
2367 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2368 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2369 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2370 (void)schedule_work(&hdev->service_task);
2371}
2372
2373static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2374{
d44f9b63 2375 struct hclge_link_status_cmd *req;
46a3df9f
S		 2376 struct hclge_desc desc;
2377 int link_status;
2378 int ret;
2379
2380 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2381 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2382 if (ret) {
2383 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2384 ret);
2385 return ret;
2386 }
2387
d44f9b63 2388 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2389 link_status = req->status & HCLGE_LINK_STATUS;
2390
2391 return !!link_status;
2392}
2393
2394static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2395{
2396 int mac_state;
2397 int link_stat;
2398
2399 mac_state = hclge_get_mac_link_status(hdev);
2400
2401 if (hdev->hw.mac.phydev) {
2402 if (!genphy_read_status(hdev->hw.mac.phydev))
2403 link_stat = mac_state &
2404 hdev->hw.mac.phydev->link;
2405 else
2406 link_stat = 0;
2407
2408 } else {
2409 link_stat = mac_state;
2410 }
2411
2412 return !!link_stat;
2413}
2414
2415static void hclge_update_link_status(struct hclge_dev *hdev)
2416{
2417 struct hnae3_client *client = hdev->nic_client;
2418 struct hnae3_handle *handle;
2419 int state;
2420 int i;
2421
2422 if (!client)
2423 return;
2424 state = hclge_get_mac_phy_link(hdev);
2425 if (state != hdev->hw.mac.link) {
2426 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2427 handle = &hdev->vport[i].nic;
2428 client->ops->link_status_change(handle, state);
2429 }
2430 hdev->hw.mac.link = state;
2431 }
2432}
2433
2434static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2435{
2436 struct hclge_mac mac = hdev->hw.mac;
2437 u8 duplex;
2438 int speed;
2439 int ret;
2440
2441 /* get the speed and duplex as autoneg'result from mac cmd when phy
2442 * doesn't exit.
2443 */
c040366b 2444 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2445 return 0;
2446
2447 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2448 if (ret) {
2449 dev_err(&hdev->pdev->dev,
2450 "mac autoneg/speed/duplex query failed %d\n", ret);
2451 return ret;
2452 }
2453
2454 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2455 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2456 if (ret) {
2457 dev_err(&hdev->pdev->dev,
2458 "mac speed/duplex config failed %d\n", ret);
2459 return ret;
2460 }
2461 }
2462
2463 return 0;
2464}
2465
2466static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2467{
2468 struct hclge_vport *vport = hclge_get_vport(handle);
2469 struct hclge_dev *hdev = vport->back;
2470
2471 return hclge_update_speed_duplex(hdev);
2472}
2473
2474static int hclge_get_status(struct hnae3_handle *handle)
2475{
2476 struct hclge_vport *vport = hclge_get_vport(handle);
2477 struct hclge_dev *hdev = vport->back;
2478
2479 hclge_update_link_status(hdev);
2480
2481 return hdev->hw.mac.link;
2482}
2483
d039ef68 2484static void hclge_service_timer(struct timer_list *t)
46a3df9f 2485{
d039ef68 2486 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2487
d039ef68 2488 mod_timer(&hdev->service_timer, jiffies + HZ);
c5f65480 2489 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2490 hclge_task_schedule(hdev);
2491}
2492
2493static void hclge_service_complete(struct hclge_dev *hdev)
2494{
2495 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2496
2497 /* Flush memory before next watchdog */
2498 smp_mb__before_atomic();
2499 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2500}
2501
ca1d7669
SM		 2502static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2503{
2504 u32 rst_src_reg;
c1a81619 2505 u32 cmdq_src_reg;
ca1d7669
SM		 2506
2507 /* fetch the events from their corresponding regs */
2508 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
c1a81619
SM		 2509 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2510
2511 /* Assumption: If by any chance reset and mailbox events are reported
2512 * together then we will only process reset event in this go and will
2513 * defer the processing of the mailbox events. Since, we would have not
2514 * cleared RX CMDQ event this time we would receive again another
2515 * interrupt from H/W just for the mailbox.
2516 */
ca1d7669
SM		 2517
2518 /* check for vector0 reset event sources */
2519 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2520 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2521 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2522 return HCLGE_VECTOR0_EVENT_RST;
2523 }
2524
2525 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2526 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2527 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2528 return HCLGE_VECTOR0_EVENT_RST;
2529 }
2530
2531 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2532 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2533 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2534 return HCLGE_VECTOR0_EVENT_RST;
2535 }
2536
c1a81619
SM		 2537 /* check for vector0 mailbox(=CMDQ RX) event source */
2538 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2539 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2540 *clearval = cmdq_src_reg;
2541 return HCLGE_VECTOR0_EVENT_MBX;
2542 }
ca1d7669
SM		 2543
2544 return HCLGE_VECTOR0_EVENT_OTHER;
2545}
2546
2547static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2548 u32 regclr)
2549{
c1a81619
SM		 2550 switch (event_type) {
2551 case HCLGE_VECTOR0_EVENT_RST:
ca1d7669 2552 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
c1a81619
SM		 2553 break;
2554 case HCLGE_VECTOR0_EVENT_MBX:
2555 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2556 break;
2557 }
ca1d7669
SM		 2558}
2559
466b0c00
L		 2560static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2561{
2562 writel(enable ? 1 : 0, vector->addr);
2563}
2564
2565static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2566{
2567 struct hclge_dev *hdev = data;
ca1d7669
SM		 2568 u32 event_cause;
2569 u32 clearval;
466b0c00
L		 2570
2571 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2572 event_cause = hclge_check_event_cause(hdev, &clearval);
2573
c1a81619 2574 /* vector 0 interrupt is shared with reset and mailbox source events.*/
ca1d7669
SM		 2575 switch (event_cause) {
2576 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2577 hclge_reset_task_schedule(hdev);
ca1d7669 2578 break;
c1a81619
SM		 2579 case HCLGE_VECTOR0_EVENT_MBX:
2580 /* If we are here then,
2581 * 1. Either we are not handling any mbx task and we are not
2582 * scheduled as well
2583 * OR
2584 * 2. We could be handling a mbx task but nothing more is
2585 * scheduled.
2586 * In both cases, we should schedule mbx task as there are more
2587 * mbx messages reported by this interrupt.
2588 */
2589 hclge_mbx_task_schedule(hdev);
f0ad97ac 2590 break;
ca1d7669 2591 default:
f0ad97ac
YL		 2592 dev_warn(&hdev->pdev->dev,
2593 "received unknown or unhandled event of vector0\n");
ca1d7669
SM		 2594 break;
2595 }
2596
cd8c5c26
YL		 2597 /* clear the source of interrupt if it is not cause by reset */
2598 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2599 hclge_clear_event_cause(hdev, event_cause, clearval);
2600 hclge_enable_vector(&hdev->misc_vector, true);
2601 }
466b0c00
L		 2602
2603 return IRQ_HANDLED;
2604}
2605
2606static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2607{
2608 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2609 hdev->num_msi_left += 1;
2610 hdev->num_msi_used -= 1;
2611}
2612
2613static void hclge_get_misc_vector(struct hclge_dev *hdev)
2614{
2615 struct hclge_misc_vector *vector = &hdev->misc_vector;
2616
2617 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2618
2619 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2620 hdev->vector_status[0] = 0;
2621
2622 hdev->num_msi_left -= 1;
2623 hdev->num_msi_used += 1;
2624}
2625
2626static int hclge_misc_irq_init(struct hclge_dev *hdev)
2627{
2628 int ret;
2629
2630 hclge_get_misc_vector(hdev);
2631
ca1d7669
SM		 2632 /* this would be explicitly freed in the end */
2633 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2634 0, "hclge_misc", hdev);
466b0c00
L		 2635 if (ret) {
2636 hclge_free_vector(hdev, 0);
2637 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2638 hdev->misc_vector.vector_irq);
2639 }
2640
2641 return ret;
2642}
2643
ca1d7669
SM		 2644static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2645{
2646 free_irq(hdev->misc_vector.vector_irq, hdev);
2647 hclge_free_vector(hdev, 0);
2648}
2649
4ed340ab
L		 2650static int hclge_notify_client(struct hclge_dev *hdev,
2651 enum hnae3_reset_notify_type type)
2652{
2653 struct hnae3_client *client = hdev->nic_client;
2654 u16 i;
2655
2656 if (!client->ops->reset_notify)
2657 return -EOPNOTSUPP;
2658
2659 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2660 struct hnae3_handle *handle = &hdev->vport[i].nic;
2661 int ret;
2662
2663 ret = client->ops->reset_notify(handle, type);
2664 if (ret)
2665 return ret;
2666 }
2667
2668 return 0;
2669}
2670
2671static int hclge_reset_wait(struct hclge_dev *hdev)
2672{
2673#define HCLGE_RESET_WATI_MS 100
2674#define HCLGE_RESET_WAIT_CNT 5
2675 u32 val, reg, reg_bit;
2676 u32 cnt = 0;
2677
2678 switch (hdev->reset_type) {
2679 case HNAE3_GLOBAL_RESET:
2680 reg = HCLGE_GLOBAL_RESET_REG;
2681 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2682 break;
2683 case HNAE3_CORE_RESET:
2684 reg = HCLGE_GLOBAL_RESET_REG;
2685 reg_bit = HCLGE_CORE_RESET_BIT;
2686 break;
2687 case HNAE3_FUNC_RESET:
2688 reg = HCLGE_FUN_RST_ING;
2689 reg_bit = HCLGE_FUN_RST_ING_B;
2690 break;
2691 default:
2692 dev_err(&hdev->pdev->dev,
2693 "Wait for unsupported reset type: %d\n",
2694 hdev->reset_type);
2695 return -EINVAL;
2696 }
2697
2698 val = hclge_read_dev(&hdev->hw, reg);
2699 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2700 msleep(HCLGE_RESET_WATI_MS);
2701 val = hclge_read_dev(&hdev->hw, reg);
2702 cnt++;
2703 }
2704
4ed340ab
L		 2705 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2706 dev_warn(&hdev->pdev->dev,
2707 "Wait for reset timeout: %d\n", hdev->reset_type);
2708 return -EBUSY;
2709 }
2710
2711 return 0;
2712}
2713
2bfbd35d 2714int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2715{
2716 struct hclge_desc desc;
2717 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2718 int ret;
2719
2720 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2721 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2722 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2723 req->fun_reset_vfid = func_id;
2724
2725 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2726 if (ret)
2727 dev_err(&hdev->pdev->dev,
2728 "send function reset cmd fail, status =%d\n", ret);
2729
2730 return ret;
2731}
2732
f2f432f2 2733static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2734{
2735 struct pci_dev *pdev = hdev->pdev;
2736 u32 val;
2737
f2f432f2 2738 switch (hdev->reset_type) {
4ed340ab
L		 2739 case HNAE3_GLOBAL_RESET:
2740 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2741 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2742 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2743 dev_info(&pdev->dev, "Global Reset requested\n");
2744 break;
2745 case HNAE3_CORE_RESET:
2746 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2747 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2748 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2749 dev_info(&pdev->dev, "Core Reset requested\n");
2750 break;
2751 case HNAE3_FUNC_RESET:
2752 dev_info(&pdev->dev, "PF Reset requested\n");
2753 hclge_func_reset_cmd(hdev, 0);
cb1b9f77
SM		 2754 /* schedule again to check later */
2755 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2756 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2757 break;
2758 default:
2759 dev_warn(&pdev->dev,
f2f432f2 2760 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2761 break;
2762 }
2763}
2764
f2f432f2
SM		 2765static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2766 unsigned long *addr)
2767{
2768 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2769
2770 /* return the highest priority reset level amongst all */
2771 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2772 rst_level = HNAE3_GLOBAL_RESET;
2773 else if (test_bit(HNAE3_CORE_RESET, addr))
2774 rst_level = HNAE3_CORE_RESET;
2775 else if (test_bit(HNAE3_IMP_RESET, addr))
2776 rst_level = HNAE3_IMP_RESET;
2777 else if (test_bit(HNAE3_FUNC_RESET, addr))
2778 rst_level = HNAE3_FUNC_RESET;
2779
2780 /* now, clear all other resets */
2781 clear_bit(HNAE3_GLOBAL_RESET, addr);
2782 clear_bit(HNAE3_CORE_RESET, addr);
2783 clear_bit(HNAE3_IMP_RESET, addr);
2784 clear_bit(HNAE3_FUNC_RESET, addr);
2785
2786 return rst_level;
2787}
2788
cd8c5c26
YL		 2789static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2790{
2791 u32 clearval = 0;
2792
2793 switch (hdev->reset_type) {
2794 case HNAE3_IMP_RESET:
2795 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2796 break;
2797 case HNAE3_GLOBAL_RESET:
2798 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2799 break;
2800 case HNAE3_CORE_RESET:
2801 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2802 break;
2803 default:
2804 dev_warn(&hdev->pdev->dev, "Unsupported reset event to clear:%d",
2805 hdev->reset_type);
2806 break;
2807 }
2808
2809 if (!clearval)
2810 return;
2811
2812 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2813 hclge_enable_vector(&hdev->misc_vector, true);
2814}
2815
f2f432f2
SM		 2816static void hclge_reset(struct hclge_dev *hdev)
2817{
2818 /* perform reset of the stack & ae device for a client */
2819
2820 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2821
2822 if (!hclge_reset_wait(hdev)) {
2823 rtnl_lock();
2824 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2825 hclge_reset_ae_dev(hdev->ae_dev);
2826 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2827 rtnl_unlock();
cd8c5c26
YL		 2828
2829 hclge_clear_reset_cause(hdev);
f2f432f2
SM		 2830 } else {
2831 /* schedule again to check pending resets later */
2832 set_bit(hdev->reset_type, &hdev->reset_pending);
2833 hclge_reset_task_schedule(hdev);
2834 }
2835
2836 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2837}
2838
6d4c3981 2839static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2840{
2841 struct hclge_vport *vport = hclge_get_vport(handle);
2842 struct hclge_dev *hdev = vport->back;
2843
6d4c3981
SM		 2844 /* check if this is a new reset request and we are not here just because
2845 * last reset attempt did not succeed and watchdog hit us again. We will
2846 * know this if last reset request did not occur very recently (watchdog
2847 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2848 * In case of new request we reset the "reset level" to PF reset.
2849 */
2850 if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2851 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2852
6d4c3981
SM		 2853 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2854 handle->reset_level);
2855
2856 /* request reset & schedule reset task */
2857 set_bit(handle->reset_level, &hdev->reset_request);
2858 hclge_reset_task_schedule(hdev);
2859
2860 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2861 handle->reset_level++;
2862
2863 handle->last_reset_time = jiffies;
4ed340ab
L		 2864}
2865
2866static void hclge_reset_subtask(struct hclge_dev *hdev)
2867{
f2f432f2
SM		 2868 /* check if there is any ongoing reset in the hardware. This status can
2869 * be checked from reset_pending. If there is then, we need to wait for
2870 * hardware to complete reset.
2871 * a. If we are able to figure out in reasonable time that hardware
2872 * has fully resetted then, we can proceed with driver, client
2873 * reset.
2874 * b. else, we can come back later to check this status so re-sched
2875 * now.
2876 */
2877 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2878 if (hdev->reset_type != HNAE3_NONE_RESET)
2879 hclge_reset(hdev);
4ed340ab 2880
f2f432f2
SM		 2881 /* check if we got any *new* reset requests to be honored */
2882 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2883 if (hdev->reset_type != HNAE3_NONE_RESET)
2884 hclge_do_reset(hdev);
4ed340ab 2885
4ed340ab
L		 2886 hdev->reset_type = HNAE3_NONE_RESET;
2887}
2888
cb1b9f77 2889static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2890{
cb1b9f77
SM		 2891 struct hclge_dev *hdev =
2892 container_of(work, struct hclge_dev, rst_service_task);
2893
2894 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2895 return;
2896
2897 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2898
4ed340ab 2899 hclge_reset_subtask(hdev);
cb1b9f77
SM		 2900
2901 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2902}
2903
c1a81619
SM		 2904static void hclge_mailbox_service_task(struct work_struct *work)
2905{
2906 struct hclge_dev *hdev =
2907 container_of(work, struct hclge_dev, mbx_service_task);
2908
2909 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2910 return;
2911
2912 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2913
2914 hclge_mbx_handler(hdev);
2915
2916 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2917}
2918
46a3df9f
S		 2919static void hclge_service_task(struct work_struct *work)
2920{
2921 struct hclge_dev *hdev =
2922 container_of(work, struct hclge_dev, service_task);
2923
c5f65480
JS		 2924 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2925 hclge_update_stats_for_all(hdev);
2926 hdev->hw_stats.stats_timer = 0;
2927 }
2928
46a3df9f
S		 2929 hclge_update_speed_duplex(hdev);
2930 hclge_update_link_status(hdev);
46a3df9f
S		 2931 hclge_service_complete(hdev);
2932}
2933
46a3df9f
S		 2934struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2935{
2936 /* VF handle has no client */
2937 if (!handle->client)
2938 return container_of(handle, struct hclge_vport, nic);
2939 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2940 return container_of(handle, struct hclge_vport, roce);
2941 else
2942 return container_of(handle, struct hclge_vport, nic);
2943}
2944
2945static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2946 struct hnae3_vector_info *vector_info)
2947{
2948 struct hclge_vport *vport = hclge_get_vport(handle);
2949 struct hnae3_vector_info *vector = vector_info;
2950 struct hclge_dev *hdev = vport->back;
2951 int alloc = 0;
2952 int i, j;
2953
2954 vector_num = min(hdev->num_msi_left, vector_num);
2955
2956 for (j = 0; j < vector_num; j++) {
2957 for (i = 1; i < hdev->num_msi; i++) {
2958 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2959 vector->vector = pci_irq_vector(hdev->pdev, i);
2960 vector->io_addr = hdev->hw.io_base +
2961 HCLGE_VECTOR_REG_BASE +
2962 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2963 vport->vport_id *
2964 HCLGE_VECTOR_VF_OFFSET;
2965 hdev->vector_status[i] = vport->vport_id;
887c3820 2966 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2967
2968 vector++;
2969 alloc++;
2970
2971 break;
2972 }
2973 }
2974 }
2975 hdev->num_msi_left -= alloc;
2976 hdev->num_msi_used += alloc;
2977
2978 return alloc;
2979}
2980
2981static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2982{
2983 int i;
2984
887c3820
SM		 2985 for (i = 0; i < hdev->num_msi; i++)
2986 if (vector == hdev->vector_irq[i])
2987 return i;
2988
46a3df9f
S		 2989 return -EINVAL;
2990}
2991
0d3e6631
YL		 2992static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2993{
2994 struct hclge_vport *vport = hclge_get_vport(handle);
2995 struct hclge_dev *hdev = vport->back;
2996 int vector_id;
2997
2998 vector_id = hclge_get_vector_index(hdev, vector);
2999 if (vector_id < 0) {
3000 dev_err(&hdev->pdev->dev,
3001 "Get vector index fail. vector_id =%d\n", vector_id);
3002 return vector_id;
3003 }
3004
3005 hclge_free_vector(hdev, vector_id);
3006
3007 return 0;
3008}
3009
46a3df9f
S		 3010static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3011{
3012 return HCLGE_RSS_KEY_SIZE;
3013}
3014
3015static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3016{
3017 return HCLGE_RSS_IND_TBL_SIZE;
3018}
3019
46a3df9f
S		 3020static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3021 const u8 hfunc, const u8 *key)
3022{
d44f9b63 3023 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3024 struct hclge_desc desc;
3025 int key_offset;
3026 int key_size;
3027 int ret;
3028
d44f9b63 3029 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3030
3031 for (key_offset = 0; key_offset < 3; key_offset++) {
3032 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3033 false);
3034
3035 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3036 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3037
3038 if (key_offset == 2)
3039 key_size =
3040 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3041 else
3042 key_size = HCLGE_RSS_HASH_KEY_NUM;
3043
3044 memcpy(req->hash_key,
3045 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3046
3047 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3048 if (ret) {
3049 dev_err(&hdev->pdev->dev,
3050 "Configure RSS config fail, status = %d\n",
3051 ret);
3052 return ret;
3053 }
3054 }
3055 return 0;
3056}
3057
89523cfa 3058static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3059{
d44f9b63 3060 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3061 struct hclge_desc desc;
3062 int i, j;
3063 int ret;
3064
d44f9b63 3065 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3066
3067 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3068 hclge_cmd_setup_basic_desc
3069 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3070
a90bb9a5
YL		 3071 req->start_table_index =
3072 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3073 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3074
3075 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3076 req->rss_result[j] =
3077 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3078
3079 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3080 if (ret) {
3081 dev_err(&hdev->pdev->dev,
3082 "Configure rss indir table fail,status = %d\n",
3083 ret);
3084 return ret;
3085 }
3086 }
3087 return 0;
3088}
3089
3090static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3091 u16 *tc_size, u16 *tc_offset)
3092{
d44f9b63 3093 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3094 struct hclge_desc desc;
3095 int ret;
3096 int i;
3097
3098 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3099 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3100
3101 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3102 u16 mode = 0;
3103
3104 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3105 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 3106 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 3107 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 3108 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3109
3110 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3111 }
3112
3113 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3114 if (ret) {
3115 dev_err(&hdev->pdev->dev,
3116 "Configure rss tc mode fail, status = %d\n", ret);
3117 return ret;
3118 }
3119
3120 return 0;
3121}
3122
3123static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3124{
d44f9b63 3125 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3126 struct hclge_desc desc;
3127 int ret;
3128
3129 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3130
d44f9b63 3131 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429
YL		 3132
3133 /* Get the tuple cfg from pf */
3134 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3135 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3136 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3137 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3138 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3139 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3140 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3141 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f
S		 3142 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3143 if (ret) {
3144 dev_err(&hdev->pdev->dev,
3145 "Configure rss input fail, status = %d\n", ret);
3146 return ret;
3147 }
3148
3149 return 0;
3150}
3151
3152static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3153 u8 *key, u8 *hfunc)
3154{
3155 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3156 int i;
3157
3158 /* Get hash algorithm */
3159 if (hfunc)
89523cfa 3160 *hfunc = vport->rss_algo;
46a3df9f
S		 3161
3162 /* Get the RSS Key required by the user */
3163 if (key)
3164 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3165
3166 /* Get indirect table */
3167 if (indir)
3168 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3169 indir[i] = vport->rss_indirection_tbl[i];
3170
3171 return 0;
3172}
3173
3174static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3175 const u8 *key, const u8 hfunc)
3176{
3177 struct hclge_vport *vport = hclge_get_vport(handle);
3178 struct hclge_dev *hdev = vport->back;
3179 u8 hash_algo;
3180 int ret, i;
3181
3182 /* Set the RSS Hash Key if specififed by the user */
3183 if (key) {
46a3df9f
S		 3184
3185 if (hfunc == ETH_RSS_HASH_TOP ||
3186 hfunc == ETH_RSS_HASH_NO_CHANGE)
3187 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3188 else
3189 return -EINVAL;
3190 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3191 if (ret)
3192 return ret;
89523cfa
YL		 3193
3194 /* Update the shadow RSS key with user specified qids */
3195 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3196 vport->rss_algo = hash_algo;
46a3df9f
S		 3197 }
3198
3199 /* Update the shadow RSS table with user specified qids */
3200 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3201 vport->rss_indirection_tbl[i] = indir[i];
3202
3203 /* Update the hardware */
89523cfa 3204 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3205}
3206
f7db940a
L		 3207static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3208{
3209 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3210
3211 if (nfc->data & RXH_L4_B_2_3)
3212 hash_sets |= HCLGE_D_PORT_BIT;
3213 else
3214 hash_sets &= ~HCLGE_D_PORT_BIT;
3215
3216 if (nfc->data & RXH_IP_SRC)
3217 hash_sets |= HCLGE_S_IP_BIT;
3218 else
3219 hash_sets &= ~HCLGE_S_IP_BIT;
3220
3221 if (nfc->data & RXH_IP_DST)
3222 hash_sets |= HCLGE_D_IP_BIT;
3223 else
3224 hash_sets &= ~HCLGE_D_IP_BIT;
3225
3226 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3227 hash_sets |= HCLGE_V_TAG_BIT;
3228
3229 return hash_sets;
3230}
3231
3232static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3233 struct ethtool_rxnfc *nfc)
3234{
3235 struct hclge_vport *vport = hclge_get_vport(handle);
3236 struct hclge_dev *hdev = vport->back;
3237 struct hclge_rss_input_tuple_cmd *req;
3238 struct hclge_desc desc;
3239 u8 tuple_sets;
3240 int ret;
3241
3242 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3243 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3244 return -EINVAL;
3245
3246 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429 3247 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3248
6f2af429
YL		 3249 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3250 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3251 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3252 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3253 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3254 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3255 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3256 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3257
3258 tuple_sets = hclge_get_rss_hash_bits(nfc);
3259 switch (nfc->flow_type) {
3260 case TCP_V4_FLOW:
3261 req->ipv4_tcp_en = tuple_sets;
3262 break;
3263 case TCP_V6_FLOW:
3264 req->ipv6_tcp_en = tuple_sets;
3265 break;
3266 case UDP_V4_FLOW:
3267 req->ipv4_udp_en = tuple_sets;
3268 break;
3269 case UDP_V6_FLOW:
3270 req->ipv6_udp_en = tuple_sets;
3271 break;
3272 case SCTP_V4_FLOW:
3273 req->ipv4_sctp_en = tuple_sets;
3274 break;
3275 case SCTP_V6_FLOW:
3276 if ((nfc->data & RXH_L4_B_0_1) ||
3277 (nfc->data & RXH_L4_B_2_3))
3278 return -EINVAL;
3279
3280 req->ipv6_sctp_en = tuple_sets;
3281 break;
3282 case IPV4_FLOW:
3283 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3284 break;
3285 case IPV6_FLOW:
3286 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3287 break;
3288 default:
3289 return -EINVAL;
3290 }
3291
3292 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6f2af429 3293 if (ret) {
f7db940a
L		 3294 dev_err(&hdev->pdev->dev,
3295 "Set rss tuple fail, status = %d\n", ret);
6f2af429
YL		 3296 return ret;
3297 }
f7db940a 3298
6f2af429
YL		 3299 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3300 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3301 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3302 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3303 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3304 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3305 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3306 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3307 return 0;
f7db940a
L		 3308}
3309
07d29954
L		 3310static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3311 struct ethtool_rxnfc *nfc)
3312{
3313 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3314 u8 tuple_sets;
07d29954
L		 3315
3316 nfc->data = 0;
3317
07d29954
L		 3318 switch (nfc->flow_type) {
3319 case TCP_V4_FLOW:
6f2af429 3320 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3321 break;
3322 case UDP_V4_FLOW:
6f2af429 3323 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3324 break;
3325 case TCP_V6_FLOW:
6f2af429 3326 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3327 break;
3328 case UDP_V6_FLOW:
6f2af429 3329 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3330 break;
3331 case SCTP_V4_FLOW:
6f2af429 3332 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3333 break;
3334 case SCTP_V6_FLOW:
6f2af429 3335 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3336 break;
3337 case IPV4_FLOW:
3338 case IPV6_FLOW:
3339 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3340 break;
3341 default:
3342 return -EINVAL;
3343 }
3344
3345 if (!tuple_sets)
3346 return 0;
3347
3348 if (tuple_sets & HCLGE_D_PORT_BIT)
3349 nfc->data |= RXH_L4_B_2_3;
3350 if (tuple_sets & HCLGE_S_PORT_BIT)
3351 nfc->data |= RXH_L4_B_0_1;
3352 if (tuple_sets & HCLGE_D_IP_BIT)
3353 nfc->data |= RXH_IP_DST;
3354 if (tuple_sets & HCLGE_S_IP_BIT)
3355 nfc->data |= RXH_IP_SRC;
3356
3357 return 0;
3358}
3359
46a3df9f
S		 3360static int hclge_get_tc_size(struct hnae3_handle *handle)
3361{
3362 struct hclge_vport *vport = hclge_get_vport(handle);
3363 struct hclge_dev *hdev = vport->back;
3364
3365 return hdev->rss_size_max;
3366}
3367
77f255c1 3368int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3369{
46a3df9f 3370 struct hclge_vport *vport = hdev->vport;
268f5dfa
YL		 3371 u8 *rss_indir = vport[0].rss_indirection_tbl;
3372 u16 rss_size = vport[0].alloc_rss_size;
3373 u8 *key = vport[0].rss_hash_key;
3374 u8 hfunc = vport[0].rss_algo;
46a3df9f 3375 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3376 u16 tc_valid[HCLGE_MAX_TC_NUM];
3377 u16 tc_size[HCLGE_MAX_TC_NUM];
268f5dfa
YL		 3378 u16 roundup_size;
3379 int i, ret;
68ece54e 3380
46a3df9f
S		 3381 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3382 if (ret)
268f5dfa 3383 return ret;
46a3df9f 3384
46a3df9f
S		 3385 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3386 if (ret)
268f5dfa 3387 return ret;
46a3df9f
S		 3388
3389 ret = hclge_set_rss_input_tuple(hdev);
3390 if (ret)
268f5dfa 3391 return ret;
46a3df9f 3392
68ece54e
YL		 3393 /* Each TC have the same queue size, and tc_size set to hardware is
3394 * the log2 of roundup power of two of rss_size, the acutal queue
3395 * size is limited by indirection table.
3396 */
3397 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3398 dev_err(&hdev->pdev->dev,
3399 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3400 rss_size);
268f5dfa 3401 return -EINVAL;
68ece54e
YL		 3402 }
3403
3404 roundup_size = roundup_pow_of_two(rss_size);
3405 roundup_size = ilog2(roundup_size);
3406
46a3df9f 3407 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3408 tc_valid[i] = 0;
46a3df9f 3409
68ece54e
YL		 3410 if (!(hdev->hw_tc_map & BIT(i)))
3411 continue;
3412
3413 tc_valid[i] = 1;
3414 tc_size[i] = roundup_size;
3415 tc_offset[i] = rss_size * i;
46a3df9f 3416 }
68ece54e 3417
268f5dfa
YL		 3418 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3419}
46a3df9f 3420
268f5dfa
YL		 3421void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3422{
3423 struct hclge_vport *vport = hdev->vport;
3424 int i, j;
46a3df9f 3425
268f5dfa
YL		 3426 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3427 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3428 vport[j].rss_indirection_tbl[i] =
3429 i % vport[j].alloc_rss_size;
3430 }
3431}
3432
3433static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3434{
3435 struct hclge_vport *vport = hdev->vport;
3436 int i;
3437
268f5dfa
YL		 3438 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3439 vport[i].rss_tuple_sets.ipv4_tcp_en =
3440 HCLGE_RSS_INPUT_TUPLE_OTHER;
3441 vport[i].rss_tuple_sets.ipv4_udp_en =
3442 HCLGE_RSS_INPUT_TUPLE_OTHER;
3443 vport[i].rss_tuple_sets.ipv4_sctp_en =
3444 HCLGE_RSS_INPUT_TUPLE_SCTP;
3445 vport[i].rss_tuple_sets.ipv4_fragment_en =
3446 HCLGE_RSS_INPUT_TUPLE_OTHER;
3447 vport[i].rss_tuple_sets.ipv6_tcp_en =
3448 HCLGE_RSS_INPUT_TUPLE_OTHER;
3449 vport[i].rss_tuple_sets.ipv6_udp_en =
3450 HCLGE_RSS_INPUT_TUPLE_OTHER;
3451 vport[i].rss_tuple_sets.ipv6_sctp_en =
3452 HCLGE_RSS_INPUT_TUPLE_SCTP;
3453 vport[i].rss_tuple_sets.ipv6_fragment_en =
3454 HCLGE_RSS_INPUT_TUPLE_OTHER;
3455
3456 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
ea739c90
FL		 3457
3458 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
268f5dfa
YL		 3459 }
3460
3461 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3462}
3463
84e095d6
SM		 3464int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3465 int vector_id, bool en,
3466 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3467{
3468 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3469 struct hnae3_ring_chain_node *node;
3470 struct hclge_desc desc;
84e095d6
SM		 3471 struct hclge_ctrl_vector_chain_cmd *req
3472 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3473 enum hclge_cmd_status status;
3474 enum hclge_opcode_type op;
3475 u16 tqp_type_and_id;
46a3df9f
S		 3476 int i;
3477
84e095d6
SM		 3478 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3479 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3480 req->int_vector_id = vector_id;
3481
3482 i = 0;
3483 for (node = ring_chain; node; node = node->next) {
84e095d6
SM		 3484 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3485 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3486 HCLGE_INT_TYPE_S,
46a3df9f 3487 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
84e095d6
SM		 3488 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3489 HCLGE_TQP_ID_S, node->tqp_index);
11af96a4
FL		 3490 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3491 HCLGE_INT_GL_IDX_S,
3492 hnae_get_field(node->int_gl_idx,
3493 HNAE3_RING_GL_IDX_M,
3494 HNAE3_RING_GL_IDX_S));
84e095d6 3495 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3496 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3497 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
84e095d6 3498 req->vfid = vport->vport_id;
46a3df9f 3499
84e095d6
SM		 3500 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3501 if (status) {
46a3df9f
S		 3502 dev_err(&hdev->pdev->dev,
3503 "Map TQP fail, status is %d.\n",
84e095d6
SM		 3504 status);
3505 return -EIO;
46a3df9f
S		 3506 }
3507 i = 0;
3508
3509 hclge_cmd_setup_basic_desc(&desc,
84e095d6 3510 op,
46a3df9f
S		 3511 false);
3512 req->int_vector_id = vector_id;
3513 }
3514 }
3515
3516 if (i > 0) {
3517 req->int_cause_num = i;
84e095d6
SM		 3518 req->vfid = vport->vport_id;
3519 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3520 if (status) {
46a3df9f 3521 dev_err(&hdev->pdev->dev,
84e095d6
SM		 3522 "Map TQP fail, status is %d.\n", status);
3523 return -EIO;
46a3df9f
S		 3524 }
3525 }
3526
3527 return 0;
3528}
3529
84e095d6
SM		 3530static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3531 int vector,
3532 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3533{
3534 struct hclge_vport *vport = hclge_get_vport(handle);
3535 struct hclge_dev *hdev = vport->back;
3536 int vector_id;
3537
3538 vector_id = hclge_get_vector_index(hdev, vector);
3539 if (vector_id < 0) {
3540 dev_err(&hdev->pdev->dev,
84e095d6 3541 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3542 return vector_id;
3543 }
3544
84e095d6 3545 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3546}
3547
84e095d6
SM		 3548static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3549 int vector,
3550 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3551{
3552 struct hclge_vport *vport = hclge_get_vport(handle);
3553 struct hclge_dev *hdev = vport->back;
84e095d6 3554 int vector_id, ret;
46a3df9f 3555
b50ae26c
PL		 3556 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3557 return 0;
3558
46a3df9f
S		 3559 vector_id = hclge_get_vector_index(hdev, vector);
3560 if (vector_id < 0) {
3561 dev_err(&handle->pdev->dev,
3562 "Get vector index fail. ret =%d\n", vector_id);
3563 return vector_id;
3564 }
3565
84e095d6 3566 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
0d3e6631 3567 if (ret)
84e095d6
SM		 3568 dev_err(&handle->pdev->dev,
3569 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3570 vector_id,
3571 ret);
46a3df9f 3572
0d3e6631 3573 return ret;
46a3df9f
S		 3574}
3575
3576int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3577 struct hclge_promisc_param *param)
3578{
d44f9b63 3579 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3580 struct hclge_desc desc;
3581 int ret;
3582
3583 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3584
d44f9b63 3585 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3586 req->vf_id = param->vf_id;
96c0e861
PL		 3587
3588 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3589 * pdev revision(0x20), new revision support them. The
3590 * value of this two fields will not return error when driver
3591 * send command to fireware in revision(0x20).
3592 */
3593 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3594 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3595
3596 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3597 if (ret) {
3598 dev_err(&hdev->pdev->dev,
3599 "Set promisc mode fail, status is %d.\n", ret);
3600 return ret;
3601 }
3602 return 0;
3603}
3604
3605void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3606 bool en_mc, bool en_bc, int vport_id)
3607{
3608 if (!param)
3609 return;
3610
3611 memset(param, 0, sizeof(struct hclge_promisc_param));
3612 if (en_uc)
3613 param->enable = HCLGE_PROMISC_EN_UC;
3614 if (en_mc)
3615 param->enable |= HCLGE_PROMISC_EN_MC;
3616 if (en_bc)
3617 param->enable |= HCLGE_PROMISC_EN_BC;
3618 param->vf_id = vport_id;
3619}
3620
3b75c3df
PL		 3621static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3622 bool en_mc_pmc)
46a3df9f
S		 3623{
3624 struct hclge_vport *vport = hclge_get_vport(handle);
3625 struct hclge_dev *hdev = vport->back;
3626 struct hclge_promisc_param param;
3627
3b75c3df
PL		 3628 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3629 vport->vport_id);
46a3df9f
S		 3630 hclge_cmd_set_promisc_mode(hdev, &param);
3631}
3632
3633static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3634{
3635 struct hclge_desc desc;
d44f9b63
YL		 3636 struct hclge_config_mac_mode_cmd *req =
3637 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3638 u32 loop_en = 0;
46a3df9f
S		 3639 int ret;
3640
3641 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3642 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3643 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3644 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3645 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3646 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3647 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3648 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3649 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3650 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3651 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3652 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3653 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3654 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3655 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3656 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3657
3658 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3659 if (ret)
3660 dev_err(&hdev->pdev->dev,
3661 "mac enable fail, ret =%d.\n", ret);
3662}
3663
e4d68dae 3664static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3665{
c39c4d98 3666 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3667 struct hclge_desc desc;
3668 u32 loop_en;
3669 int ret;
3670
e4d68dae
YL		 3671 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3672 /* 1 Read out the MAC mode config at first */
3673 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3674 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3675 if (ret) {
3676 dev_err(&hdev->pdev->dev,
3677 "mac loopback get fail, ret =%d.\n", ret);
3678 return ret;
3679 }
c39c4d98 3680
e4d68dae
YL		 3681 /* 2 Then setup the loopback flag */
3682 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3683 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
3684
3685 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3686
e4d68dae
YL		 3687 /* 3 Config mac work mode with loopback flag
3688 * and its original configure parameters
3689 */
3690 hclge_cmd_reuse_desc(&desc, false);
3691 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3692 if (ret)
3693 dev_err(&hdev->pdev->dev,
3694 "mac loopback set fail, ret =%d.\n", ret);
3695 return ret;
3696}
c39c4d98 3697
e4d68dae
YL		 3698static int hclge_set_loopback(struct hnae3_handle *handle,
3699 enum hnae3_loop loop_mode, bool en)
3700{
3701 struct hclge_vport *vport = hclge_get_vport(handle);
3702 struct hclge_dev *hdev = vport->back;
3703 int ret;
3704
3705 switch (loop_mode) {
3706 case HNAE3_MAC_INTER_LOOP_MAC:
3707 ret = hclge_set_mac_loopback(hdev, en);
c39c4d98
YL		 3708 break;
3709 default:
3710 ret = -ENOTSUPP;
3711 dev_err(&hdev->pdev->dev,
3712 "loop_mode %d is not supported\n", loop_mode);
3713 break;
3714 }
3715
3716 return ret;
3717}
3718
46a3df9f
S		 3719static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3720 int stream_id, bool enable)
3721{
3722 struct hclge_desc desc;
d44f9b63
YL		 3723 struct hclge_cfg_com_tqp_queue_cmd *req =
3724 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3725 int ret;
3726
3727 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3728 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3729 req->stream_id = cpu_to_le16(stream_id);
3730 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3731
3732 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3733 if (ret)
3734 dev_err(&hdev->pdev->dev,
3735 "Tqp enable fail, status =%d.\n", ret);
3736 return ret;
3737}
3738
3739static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3740{
3741 struct hclge_vport *vport = hclge_get_vport(handle);
3742 struct hnae3_queue *queue;
3743 struct hclge_tqp *tqp;
3744 int i;
3745
3746 for (i = 0; i < vport->alloc_tqps; i++) {
3747 queue = handle->kinfo.tqp[i];
3748 tqp = container_of(queue, struct hclge_tqp, q);
3749 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3750 }
3751}
3752
3753static int hclge_ae_start(struct hnae3_handle *handle)
3754{
3755 struct hclge_vport *vport = hclge_get_vport(handle);
3756 struct hclge_dev *hdev = vport->back;
814e0274 3757 int i, ret;
46a3df9f 3758
814e0274
PL		 3759 for (i = 0; i < vport->alloc_tqps; i++)
3760 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3761
46a3df9f
S		 3762 /* mac enable */
3763 hclge_cfg_mac_mode(hdev, true);
3764 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3765 mod_timer(&hdev->service_timer, jiffies + HZ);
be8d8cdb 3766 hdev->hw.mac.link = 0;
46a3df9f 3767
b50ae26c
PL		 3768 /* reset tqp stats */
3769 hclge_reset_tqp_stats(handle);
3770
46a3df9f
S		 3771 ret = hclge_mac_start_phy(hdev);
3772 if (ret)
3773 return ret;
3774
46a3df9f
S		 3775 return 0;
3776}
3777
3778static void hclge_ae_stop(struct hnae3_handle *handle)
3779{
3780 struct hclge_vport *vport = hclge_get_vport(handle);
3781 struct hclge_dev *hdev = vport->back;
814e0274 3782 int i;
46a3df9f 3783
b50ae26c
PL		 3784 del_timer_sync(&hdev->service_timer);
3785 cancel_work_sync(&hdev->service_task);
f5be7967 3786 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
b50ae26c 3787
9617f668
YL		 3788 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3789 hclge_mac_stop_phy(hdev);
b50ae26c 3790 return;
9617f668 3791 }
b50ae26c 3792
814e0274
PL		 3793 for (i = 0; i < vport->alloc_tqps; i++)
3794 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3795
46a3df9f
S		 3796 /* Mac disable */
3797 hclge_cfg_mac_mode(hdev, false);
3798
3799 hclge_mac_stop_phy(hdev);
3800
3801 /* reset tqp stats */
3802 hclge_reset_tqp_stats(handle);
f30dfddc
FL		 3803 del_timer_sync(&hdev->service_timer);
3804 cancel_work_sync(&hdev->service_task);
3805 hclge_update_link_status(hdev);
46a3df9f
S		 3806}
3807
3808static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3809 u16 cmdq_resp, u8 resp_code,
3810 enum hclge_mac_vlan_tbl_opcode op)
3811{
3812 struct hclge_dev *hdev = vport->back;
3813 int return_status = -EIO;
3814
3815 if (cmdq_resp) {
3816 dev_err(&hdev->pdev->dev,
3817 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3818 cmdq_resp);
3819 return -EIO;
3820 }
3821
3822 if (op == HCLGE_MAC_VLAN_ADD) {
3823 if ((!resp_code) || (resp_code == 1)) {
3824 return_status = 0;
3825 } else if (resp_code == 2) {
eefd00a5 3826 return_status = -ENOSPC;
46a3df9f
S		 3827 dev_err(&hdev->pdev->dev,
3828 "add mac addr failed for uc_overflow.\n");
3829 } else if (resp_code == 3) {
eefd00a5 3830 return_status = -ENOSPC;
46a3df9f
S		 3831 dev_err(&hdev->pdev->dev,
3832 "add mac addr failed for mc_overflow.\n");
3833 } else {
3834 dev_err(&hdev->pdev->dev,
3835 "add mac addr failed for undefined, code=%d.\n",
3836 resp_code);
3837 }
3838 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3839 if (!resp_code) {
3840 return_status = 0;
3841 } else if (resp_code == 1) {
eefd00a5 3842 return_status = -ENOENT;
46a3df9f
S		 3843 dev_dbg(&hdev->pdev->dev,
3844 "remove mac addr failed for miss.\n");
3845 } else {
3846 dev_err(&hdev->pdev->dev,
3847 "remove mac addr failed for undefined, code=%d.\n",
3848 resp_code);
3849 }
3850 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3851 if (!resp_code) {
3852 return_status = 0;
3853 } else if (resp_code == 1) {
eefd00a5 3854 return_status = -ENOENT;
46a3df9f
S		 3855 dev_dbg(&hdev->pdev->dev,
3856 "lookup mac addr failed for miss.\n");
3857 } else {
3858 dev_err(&hdev->pdev->dev,
3859 "lookup mac addr failed for undefined, code=%d.\n",
3860 resp_code);
3861 }
3862 } else {
eefd00a5 3863 return_status = -EINVAL;
46a3df9f
S		 3864 dev_err(&hdev->pdev->dev,
3865 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3866 op);
3867 }
3868
3869 return return_status;
3870}
3871
3872static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3873{
3874 int word_num;
3875 int bit_num;
3876
3877 if (vfid > 255 || vfid < 0)
3878 return -EIO;
3879
3880 if (vfid >= 0 && vfid <= 191) {
3881 word_num = vfid / 32;
3882 bit_num = vfid % 32;
3883 if (clr)
a90bb9a5 3884 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3885 else
a90bb9a5 3886 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3887 } else {
3888 word_num = (vfid - 192) / 32;
3889 bit_num = vfid % 32;
3890 if (clr)
a90bb9a5 3891 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3892 else
a90bb9a5 3893 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3894 }
3895
3896 return 0;
3897}
3898
3899static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3900{
3901#define HCLGE_DESC_NUMBER 3
3902#define HCLGE_FUNC_NUMBER_PER_DESC 6
3903 int i, j;
3904
3905 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3906 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3907 if (desc[i].data[j])
3908 return false;
3909
3910 return true;
3911}
3912
d44f9b63 3913static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3914 const u8 *addr)
3915{
3916 const unsigned char *mac_addr = addr;
3917 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3918 (mac_addr[0]) | (mac_addr[1] << 8);
3919 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3920
3921 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3922 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3923}
3924
1db9b1bf
YL		 3925static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3926 const u8 *addr)
46a3df9f
S		 3927{
3928 u16 high_val = addr[1] | (addr[0] << 8);
3929 struct hclge_dev *hdev = vport->back;
3930 u32 rsh = 4 - hdev->mta_mac_sel_type;
3931 u16 ret_val = (high_val >> rsh) & 0xfff;
3932
3933 return ret_val;
3934}
3935
3936static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3937 enum hclge_mta_dmac_sel_type mta_mac_sel,
3938 bool enable)
3939{
d44f9b63 3940 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3941 struct hclge_desc desc;
3942 int ret;
3943
d44f9b63 3944 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3945 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3946
3947 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3948 enable);
3949 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3950 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3951
3952 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3953 if (ret) {
3954 dev_err(&hdev->pdev->dev,
3955 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3956 ret);
3957 return ret;
3958 }
3959
3960 return 0;
3961}
3962
3963int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3964 u8 func_id,
3965 bool enable)
3966{
d44f9b63 3967 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3968 struct hclge_desc desc;
3969 int ret;
3970
d44f9b63 3971 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3972 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3973
3974 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3975 enable);
3976 req->function_id = func_id;
3977
3978 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3979 if (ret) {
3980 dev_err(&hdev->pdev->dev,
3981 "Config func_id enable failed for cmd_send, ret =%d.\n",
3982 ret);
3983 return ret;
3984 }
3985
3986 return 0;
3987}
3988
3989static int hclge_set_mta_table_item(struct hclge_vport *vport,
3990 u16 idx,
3991 bool enable)
3992{
3993 struct hclge_dev *hdev = vport->back;
d44f9b63 3994 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3995 struct hclge_desc desc;
a90bb9a5 3996 u16 item_idx = 0;
46a3df9f
S		 3997 int ret;
3998
d44f9b63 3999 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 4000 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
4001 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
4002
a90bb9a5 4003 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 4004 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 4005 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 4006
4007 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4008 if (ret) {
4009 dev_err(&hdev->pdev->dev,
4010 "Config mta table item failed for cmd_send, ret =%d.\n",
4011 ret);
4012 return ret;
4013 }
4014
40cca1c5
XW		 4015 if (enable)
4016 set_bit(idx, vport->mta_shadow);
4017 else
4018 clear_bit(idx, vport->mta_shadow);
4019
46a3df9f
S		 4020 return 0;
4021}
4022
40cca1c5
XW		 4023static int hclge_update_mta_status(struct hnae3_handle *handle)
4024{
4025 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4026 struct hclge_vport *vport = hclge_get_vport(handle);
4027 struct net_device *netdev = handle->kinfo.netdev;
4028 struct netdev_hw_addr *ha;
4029 u16 tbl_idx;
4030
4031 memset(mta_status, 0, sizeof(mta_status));
4032
4033 /* update mta_status from mc addr list */
4034 netdev_for_each_mc_addr(ha, netdev) {
4035 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4036 set_bit(tbl_idx, mta_status);
4037 }
4038
4039 return hclge_update_mta_status_common(vport, mta_status,
4040 0, HCLGE_MTA_TBL_SIZE, true);
4041}
4042
4043int hclge_update_mta_status_common(struct hclge_vport *vport,
4044 unsigned long *status,
4045 u16 idx,
4046 u16 count,
4047 bool update_filter)
4048{
4049 struct hclge_dev *hdev = vport->back;
4050 u16 update_max = idx + count;
4051 u16 check_max;
4052 int ret = 0;
4053 bool used;
4054 u16 i;
4055
4056 /* setup mta check range */
4057 if (update_filter) {
4058 i = 0;
4059 check_max = HCLGE_MTA_TBL_SIZE;
4060 } else {
4061 i = idx;
4062 check_max = update_max;
4063 }
4064
4065 used = false;
4066 /* check and update all mta item */
4067 for (; i < check_max; i++) {
4068 /* ignore unused item */
4069 if (!test_bit(i, vport->mta_shadow))
4070 continue;
4071
4072 /* if i in update range then update it */
4073 if (i >= idx && i < update_max)
4074 if (!test_bit(i - idx, status))
4075 hclge_set_mta_table_item(vport, i, false);
4076
4077 if (!used && test_bit(i, vport->mta_shadow))
4078 used = true;
4079 }
4080
4081 /* no longer use mta, disable it */
4082 if (vport->accept_mta_mc && update_filter && !used) {
4083 ret = hclge_cfg_func_mta_filter(hdev,
4084 vport->vport_id,
4085 false);
4086 if (ret)
4087 dev_err(&hdev->pdev->dev,
4088 "disable func mta filter fail ret=%d\n",
4089 ret);
4090 else
4091 vport->accept_mta_mc = false;
4092 }
4093
4094 return ret;
4095}
4096
46a3df9f 4097static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4098 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 4099{
4100 struct hclge_dev *hdev = vport->back;
4101 struct hclge_desc desc;
4102 u8 resp_code;
a90bb9a5 4103 u16 retval;
46a3df9f
S		 4104 int ret;
4105
4106 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4107
d44f9b63 4108 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4109
4110 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4111 if (ret) {
4112 dev_err(&hdev->pdev->dev,
4113 "del mac addr failed for cmd_send, ret =%d.\n",
4114 ret);
4115 return ret;
4116 }
a90bb9a5
YL		 4117 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4118 retval = le16_to_cpu(desc.retval);
46a3df9f 4119
a90bb9a5 4120 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4121 HCLGE_MAC_VLAN_REMOVE);
4122}
4123
4124static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4125 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4126 struct hclge_desc *desc,
4127 bool is_mc)
4128{
4129 struct hclge_dev *hdev = vport->back;
4130 u8 resp_code;
a90bb9a5 4131 u16 retval;
46a3df9f
S		 4132 int ret;
4133
4134 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4135 if (is_mc) {
4136 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4137 memcpy(desc[0].data,
4138 req,
d44f9b63 4139 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4140 hclge_cmd_setup_basic_desc(&desc[1],
4141 HCLGE_OPC_MAC_VLAN_ADD,
4142 true);
4143 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4144 hclge_cmd_setup_basic_desc(&desc[2],
4145 HCLGE_OPC_MAC_VLAN_ADD,
4146 true);
4147 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4148 } else {
4149 memcpy(desc[0].data,
4150 req,
d44f9b63 4151 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4152 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4153 }
4154 if (ret) {
4155 dev_err(&hdev->pdev->dev,
4156 "lookup mac addr failed for cmd_send, ret =%d.\n",
4157 ret);
4158 return ret;
4159 }
a90bb9a5
YL		 4160 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4161 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4162
a90bb9a5 4163 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4164 HCLGE_MAC_VLAN_LKUP);
4165}
4166
4167static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4168 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4169 struct hclge_desc *mc_desc)
4170{
4171 struct hclge_dev *hdev = vport->back;
4172 int cfg_status;
4173 u8 resp_code;
a90bb9a5 4174 u16 retval;
46a3df9f
S		 4175 int ret;
4176
4177 if (!mc_desc) {
4178 struct hclge_desc desc;
4179
4180 hclge_cmd_setup_basic_desc(&desc,
4181 HCLGE_OPC_MAC_VLAN_ADD,
4182 false);
d44f9b63
YL		 4183 memcpy(desc.data, req,
4184 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4185 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4186 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4187 retval = le16_to_cpu(desc.retval);
4188
4189 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4190 resp_code,
4191 HCLGE_MAC_VLAN_ADD);
4192 } else {
c3b6f755 4193 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4194 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4195 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4196 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4197 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4198 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4199 memcpy(mc_desc[0].data, req,
d44f9b63 4200 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4201 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4202 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4203 retval = le16_to_cpu(mc_desc[0].retval);
4204
4205 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4206 resp_code,
4207 HCLGE_MAC_VLAN_ADD);
4208 }
4209
4210 if (ret) {
4211 dev_err(&hdev->pdev->dev,
4212 "add mac addr failed for cmd_send, ret =%d.\n",
4213 ret);
4214 return ret;
4215 }
4216
4217 return cfg_status;
4218}
4219
4220static int hclge_add_uc_addr(struct hnae3_handle *handle,
4221 const unsigned char *addr)
4222{
4223 struct hclge_vport *vport = hclge_get_vport(handle);
4224
4225 return hclge_add_uc_addr_common(vport, addr);
4226}
4227
4228int hclge_add_uc_addr_common(struct hclge_vport *vport,
4229 const unsigned char *addr)
4230{
4231 struct hclge_dev *hdev = vport->back;
d44f9b63 4232 struct hclge_mac_vlan_tbl_entry_cmd req;
d07b6bb4 4233 struct hclge_desc desc;
a90bb9a5 4234 u16 egress_port = 0;
aa7a795e 4235 int ret;
46a3df9f
S		 4236
4237 /* mac addr check */
4238 if (is_zero_ether_addr(addr) ||
4239 is_broadcast_ether_addr(addr) ||
4240 is_multicast_ether_addr(addr)) {
4241 dev_err(&hdev->pdev->dev,
4242 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4243 addr,
4244 is_zero_ether_addr(addr),
4245 is_broadcast_ether_addr(addr),
4246 is_multicast_ether_addr(addr));
4247 return -EINVAL;
4248 }
4249
4250 memset(&req, 0, sizeof(req));
4251 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4252 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4253 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4254 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 4255
4256 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4257 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4258 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 4259 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 4260 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 4261 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 4262
4263 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4264
4265 hclge_prepare_mac_addr(&req, addr);
4266
d07b6bb4
JS		 4267 /* Lookup the mac address in the mac_vlan table, and add
4268 * it if the entry is inexistent. Repeated unicast entry
4269 * is not allowed in the mac vlan table.
4270 */
4271 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4272 if (ret == -ENOENT)
4273 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4274
4275 /* check if we just hit the duplicate */
4276 if (!ret)
4277 ret = -EINVAL;
4278
4279 dev_err(&hdev->pdev->dev,
4280 "PF failed to add unicast entry(%pM) in the MAC table\n",
4281 addr);
46a3df9f 4282
aa7a795e 4283 return ret;
46a3df9f
S		 4284}
4285
4286static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4287 const unsigned char *addr)
4288{
4289 struct hclge_vport *vport = hclge_get_vport(handle);
4290
4291 return hclge_rm_uc_addr_common(vport, addr);
4292}
4293
4294int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4295 const unsigned char *addr)
4296{
4297 struct hclge_dev *hdev = vport->back;
d44f9b63 4298 struct hclge_mac_vlan_tbl_entry_cmd req;
aa7a795e 4299 int ret;
46a3df9f
S		 4300
4301 /* mac addr check */
4302 if (is_zero_ether_addr(addr) ||
4303 is_broadcast_ether_addr(addr) ||
4304 is_multicast_ether_addr(addr)) {
4305 dev_dbg(&hdev->pdev->dev,
4306 "Remove mac err! invalid mac:%pM.\n",
4307 addr);
4308 return -EINVAL;
4309 }
4310
4311 memset(&req, 0, sizeof(req));
4312 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4313 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4314 hclge_prepare_mac_addr(&req, addr);
aa7a795e 4315 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4316
aa7a795e 4317 return ret;
46a3df9f
S		 4318}
4319
4320static int hclge_add_mc_addr(struct hnae3_handle *handle,
4321 const unsigned char *addr)
4322{
4323 struct hclge_vport *vport = hclge_get_vport(handle);
4324
4325 return hclge_add_mc_addr_common(vport, addr);
4326}
4327
4328int hclge_add_mc_addr_common(struct hclge_vport *vport,
4329 const unsigned char *addr)
4330{
4331 struct hclge_dev *hdev = vport->back;
d44f9b63 4332 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4333 struct hclge_desc desc[3];
4334 u16 tbl_idx;
4335 int status;
4336
4337 /* mac addr check */
4338 if (!is_multicast_ether_addr(addr)) {
4339 dev_err(&hdev->pdev->dev,
4340 "Add mc mac err! invalid mac:%pM.\n",
4341 addr);
4342 return -EINVAL;
4343 }
4344 memset(&req, 0, sizeof(req));
4345 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4346 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4347 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4348 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4349 hclge_prepare_mac_addr(&req, addr);
4350 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4351 if (!status) {
4352 /* This mac addr exist, update VFID for it */
4353 hclge_update_desc_vfid(desc, vport->vport_id, false);
4354 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4355 } else {
4356 /* This mac addr do not exist, add new entry for it */
4357 memset(desc[0].data, 0, sizeof(desc[0].data));
4358 memset(desc[1].data, 0, sizeof(desc[0].data));
4359 memset(desc[2].data, 0, sizeof(desc[0].data));
4360 hclge_update_desc_vfid(desc, vport->vport_id, false);
4361 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4362 }
4363
40cca1c5
XW		 4364 /* If mc mac vlan table is full, use MTA table */
4365 if (status == -ENOSPC) {
4366 if (!vport->accept_mta_mc) {
4367 status = hclge_cfg_func_mta_filter(hdev,
4368 vport->vport_id,
4369 true);
4370 if (status) {
4371 dev_err(&hdev->pdev->dev,
4372 "set mta filter mode fail ret=%d\n",
4373 status);
4374 return status;
4375 }
4376 vport->accept_mta_mc = true;
4377 }
4378
4379 /* Set MTA table for this MAC address */
4380 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4381 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4382 }
46a3df9f
S		 4383
4384 return status;
4385}
4386
4387static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4388 const unsigned char *addr)
4389{
4390 struct hclge_vport *vport = hclge_get_vport(handle);
4391
4392 return hclge_rm_mc_addr_common(vport, addr);
4393}
4394
4395int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4396 const unsigned char *addr)
4397{
4398 struct hclge_dev *hdev = vport->back;
d44f9b63 4399 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4400 enum hclge_cmd_status status;
4401 struct hclge_desc desc[3];
46a3df9f
S		 4402
4403 /* mac addr check */
4404 if (!is_multicast_ether_addr(addr)) {
4405 dev_dbg(&hdev->pdev->dev,
4406 "Remove mc mac err! invalid mac:%pM.\n",
4407 addr);
4408 return -EINVAL;
4409 }
4410
4411 memset(&req, 0, sizeof(req));
4412 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4413 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4414 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4415 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4416 hclge_prepare_mac_addr(&req, addr);
4417 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4418 if (!status) {
4419 /* This mac addr exist, remove this handle's VFID for it */
4420 hclge_update_desc_vfid(desc, vport->vport_id, true);
4421
4422 if (hclge_is_all_function_id_zero(desc))
4423 /* All the vfid is zero, so need to delete this entry */
4424 status = hclge_remove_mac_vlan_tbl(vport, &req);
4425 else
4426 /* Not all the vfid is zero, update the vfid */
4427 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4428
4429 } else {
40cca1c5
XW		 4430 /* Maybe this mac address is in mta table, but it cannot be
4431 * deleted here because an entry of mta represents an address
4432 * range rather than a specific address. the delete action to
4433 * all entries will take effect in update_mta_status called by
4434 * hns3_nic_set_rx_mode.
4435 */
4436 status = 0;
46a3df9f
S		 4437 }
4438
46a3df9f
S		 4439 return status;
4440}
4441
f5aac71c
FL		 4442static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4443 u16 cmdq_resp, u8 resp_code)
4444{
4445#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4446#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4447#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4448#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4449
4450 int return_status;
4451
4452 if (cmdq_resp) {
4453 dev_err(&hdev->pdev->dev,
4454 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4455 cmdq_resp);
4456 return -EIO;
4457 }
4458
4459 switch (resp_code) {
4460 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4461 case HCLGE_ETHERTYPE_ALREADY_ADD:
4462 return_status = 0;
4463 break;
4464 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4465 dev_err(&hdev->pdev->dev,
4466 "add mac ethertype failed for manager table overflow.\n");
4467 return_status = -EIO;
4468 break;
4469 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4470 dev_err(&hdev->pdev->dev,
4471 "add mac ethertype failed for key conflict.\n");
4472 return_status = -EIO;
4473 break;
4474 default:
4475 dev_err(&hdev->pdev->dev,
4476 "add mac ethertype failed for undefined, code=%d.\n",
4477 resp_code);
4478 return_status = -EIO;
4479 }
4480
4481 return return_status;
4482}
4483
4484static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4485 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4486{
4487 struct hclge_desc desc;
4488 u8 resp_code;
4489 u16 retval;
4490 int ret;
4491
4492 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4493 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4494
4495 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4496 if (ret) {
4497 dev_err(&hdev->pdev->dev,
4498 "add mac ethertype failed for cmd_send, ret =%d.\n",
4499 ret);
4500 return ret;
4501 }
4502
4503 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4504 retval = le16_to_cpu(desc.retval);
4505
4506 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4507}
4508
4509static int init_mgr_tbl(struct hclge_dev *hdev)
4510{
4511 int ret;
4512 int i;
4513
4514 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4515 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4516 if (ret) {
4517 dev_err(&hdev->pdev->dev,
4518 "add mac ethertype failed, ret =%d.\n",
4519 ret);
4520 return ret;
4521 }
4522 }
4523
4524 return 0;
4525}
4526
46a3df9f
S		 4527static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4528{
4529 struct hclge_vport *vport = hclge_get_vport(handle);
4530 struct hclge_dev *hdev = vport->back;
4531
4532 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4533}
4534
59098055
FL		 4535static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4536 bool is_first)
46a3df9f
S		 4537{
4538 const unsigned char *new_addr = (const unsigned char *)p;
4539 struct hclge_vport *vport = hclge_get_vport(handle);
4540 struct hclge_dev *hdev = vport->back;
18838d0c 4541 int ret;
46a3df9f
S		 4542
4543 /* mac addr check */
4544 if (is_zero_ether_addr(new_addr) ||
4545 is_broadcast_ether_addr(new_addr) ||
4546 is_multicast_ether_addr(new_addr)) {
4547 dev_err(&hdev->pdev->dev,
4548 "Change uc mac err! invalid mac:%p.\n",
4549 new_addr);
4550 return -EINVAL;
4551 }
4552
59098055 4553 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4554 dev_warn(&hdev->pdev->dev,
59098055 4555 "remove old uc mac address fail.\n");
46a3df9f 4556
18838d0c
FL		 4557 ret = hclge_add_uc_addr(handle, new_addr);
4558 if (ret) {
4559 dev_err(&hdev->pdev->dev,
4560 "add uc mac address fail, ret =%d.\n",
4561 ret);
4562
59098055
FL		 4563 if (!is_first &&
4564 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4565 dev_err(&hdev->pdev->dev,
59098055 4566 "restore uc mac address fail.\n");
18838d0c
FL		 4567
4568 return -EIO;
46a3df9f
S		 4569 }
4570
e98d7183 4571 ret = hclge_pause_addr_cfg(hdev, new_addr);
18838d0c
FL		 4572 if (ret) {
4573 dev_err(&hdev->pdev->dev,
4574 "configure mac pause address fail, ret =%d.\n",
4575 ret);
4576 return -EIO;
4577 }
4578
4579 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4580
4581 return 0;
46a3df9f
S		 4582}
4583
4584static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4585 bool filter_en)
4586{
d44f9b63 4587 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4588 struct hclge_desc desc;
4589 int ret;
4590
4591 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4592
d44f9b63 4593 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4594 req->vlan_type = vlan_type;
4595 req->vlan_fe = filter_en;
4596
4597 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4598 if (ret) {
4599 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4600 ret);
4601 return ret;
4602 }
4603
4604 return 0;
4605}
4606
391b5e93
JS		 4607#define HCLGE_FILTER_TYPE_VF 0
4608#define HCLGE_FILTER_TYPE_PORT 1
4609
4610static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4611{
4612 struct hclge_vport *vport = hclge_get_vport(handle);
4613 struct hclge_dev *hdev = vport->back;
4614
4615 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4616}
4617
dc8131d8
YL		 4618static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4619 bool is_kill, u16 vlan, u8 qos,
4620 __be16 proto)
46a3df9f
S		 4621{
4622#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4623 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4624 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4625 struct hclge_desc desc[2];
4626 u8 vf_byte_val;
4627 u8 vf_byte_off;
4628 int ret;
4629
4630 hclge_cmd_setup_basic_desc(&desc[0],
4631 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4632 hclge_cmd_setup_basic_desc(&desc[1],
4633 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4634
4635 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4636
4637 vf_byte_off = vfid / 8;
4638 vf_byte_val = 1 << (vfid % 8);
4639
d44f9b63
YL		 4640 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4641 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4642
a90bb9a5 4643 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4644 req0->vlan_cfg = is_kill;
4645
4646 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4647 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4648 else
4649 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4650
4651 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4652 if (ret) {
4653 dev_err(&hdev->pdev->dev,
4654 "Send vf vlan command fail, ret =%d.\n",
4655 ret);
4656 return ret;
4657 }
4658
4659 if (!is_kill) {
6c251711 4660#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4661 if (!req0->resp_code || req0->resp_code == 1)
4662 return 0;
4663
6c251711
YL		 4664 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4665 dev_warn(&hdev->pdev->dev,
4666 "vf vlan table is full, vf vlan filter is disabled\n");
4667 return 0;
4668 }
4669
46a3df9f
S		 4670 dev_err(&hdev->pdev->dev,
4671 "Add vf vlan filter fail, ret =%d.\n",
4672 req0->resp_code);
4673 } else {
4674 if (!req0->resp_code)
4675 return 0;
4676
4677 dev_err(&hdev->pdev->dev,
4678 "Kill vf vlan filter fail, ret =%d.\n",
4679 req0->resp_code);
4680 }
4681
4682 return -EIO;
4683}
4684
dc8131d8
YL		 4685static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4686 u16 vlan_id, bool is_kill)
46a3df9f 4687{
d44f9b63 4688 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4689 struct hclge_desc desc;
4690 u8 vlan_offset_byte_val;
4691 u8 vlan_offset_byte;
4692 u8 vlan_offset_160;
4693 int ret;
4694
4695 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4696
4697 vlan_offset_160 = vlan_id / 160;
4698 vlan_offset_byte = (vlan_id % 160) / 8;
4699 vlan_offset_byte_val = 1 << (vlan_id % 8);
4700
d44f9b63 4701 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4702 req->vlan_offset = vlan_offset_160;
4703 req->vlan_cfg = is_kill;
4704 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4705
4706 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
dc8131d8
YL		 4707 if (ret)
4708 dev_err(&hdev->pdev->dev,
4709 "port vlan command, send fail, ret =%d.\n", ret);
4710 return ret;
4711}
4712
4713static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4714 u16 vport_id, u16 vlan_id, u8 qos,
4715 bool is_kill)
4716{
4717 u16 vport_idx, vport_num = 0;
4718 int ret;
4719
4720 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4721 0, proto);
46a3df9f
S		 4722 if (ret) {
4723 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 4724 "Set %d vport vlan filter config fail, ret =%d.\n",
4725 vport_id, ret);
46a3df9f
S		 4726 return ret;
4727 }
4728
dc8131d8
YL		 4729 /* vlan 0 may be added twice when 8021q module is enabled */
4730 if (!is_kill && !vlan_id &&
4731 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4732 return 0;
4733
4734 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4735 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 4736 "Add port vlan failed, vport %d is already in vlan %d\n",
4737 vport_id, vlan_id);
4738 return -EINVAL;
46a3df9f
S		 4739 }
4740
dc8131d8
YL		 4741 if (is_kill &&
4742 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4743 dev_err(&hdev->pdev->dev,
4744 "Delete port vlan failed, vport %d is not in vlan %d\n",
4745 vport_id, vlan_id);
4746 return -EINVAL;
4747 }
4748
4749 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4750 vport_num++;
4751
4752 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4753 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4754 is_kill);
4755
4756 return ret;
4757}
4758
4759int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4760 u16 vlan_id, bool is_kill)
4761{
4762 struct hclge_vport *vport = hclge_get_vport(handle);
4763 struct hclge_dev *hdev = vport->back;
4764
4765 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4766 0, is_kill);
46a3df9f
S		 4767}
4768
4769static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4770 u16 vlan, u8 qos, __be16 proto)
4771{
4772 struct hclge_vport *vport = hclge_get_vport(handle);
4773 struct hclge_dev *hdev = vport->back;
4774
4775 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4776 return -EINVAL;
4777 if (proto != htons(ETH_P_8021Q))
4778 return -EPROTONOSUPPORT;
4779
dc8131d8 4780 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4781}
4782
5f6ea83f
PL		 4783static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4784{
4785 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4786 struct hclge_vport_vtag_tx_cfg_cmd *req;
4787 struct hclge_dev *hdev = vport->back;
4788 struct hclge_desc desc;
4789 int status;
4790
4791 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4792
4793 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4794 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4795 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
dcb35cce
PL		 4796 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4797 vcfg->accept_tag1 ? 1 : 0);
4798 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4799 vcfg->accept_untag1 ? 1 : 0);
4800 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4801 vcfg->accept_tag2 ? 1 : 0);
4802 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4803 vcfg->accept_untag2 ? 1 : 0);
5f6ea83f
PL		 4804 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4805 vcfg->insert_tag1_en ? 1 : 0);
4806 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4807 vcfg->insert_tag2_en ? 1 : 0);
4808 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4809
4810 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4811 req->vf_bitmap[req->vf_offset] =
4812 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4813
4814 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4815 if (status)
4816 dev_err(&hdev->pdev->dev,
4817 "Send port txvlan cfg command fail, ret =%d\n",
4818 status);
4819
4820 return status;
4821}
4822
4823static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4824{
4825 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4826 struct hclge_vport_vtag_rx_cfg_cmd *req;
4827 struct hclge_dev *hdev = vport->back;
4828 struct hclge_desc desc;
4829 int status;
4830
4831 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4832
4833 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4834 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4835 vcfg->strip_tag1_en ? 1 : 0);
4836 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4837 vcfg->strip_tag2_en ? 1 : 0);
4838 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4839 vcfg->vlan1_vlan_prionly ? 1 : 0);
4840 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4841 vcfg->vlan2_vlan_prionly ? 1 : 0);
4842
4843 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4844 req->vf_bitmap[req->vf_offset] =
4845 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4846
4847 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4848 if (status)
4849 dev_err(&hdev->pdev->dev,
4850 "Send port rxvlan cfg command fail, ret =%d\n",
4851 status);
4852
4853 return status;
4854}
4855
4856static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4857{
4858 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4859 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4860 struct hclge_desc desc;
4861 int status;
4862
4863 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4864 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4865 rx_req->ot_fst_vlan_type =
4866 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4867 rx_req->ot_sec_vlan_type =
4868 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4869 rx_req->in_fst_vlan_type =
4870 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4871 rx_req->in_sec_vlan_type =
4872 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4873
4874 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4875 if (status) {
4876 dev_err(&hdev->pdev->dev,
4877 "Send rxvlan protocol type command fail, ret =%d\n",
4878 status);
4879 return status;
4880 }
4881
4882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4883
4884 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4885 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4886 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4887
4888 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4889 if (status)
4890 dev_err(&hdev->pdev->dev,
4891 "Send txvlan protocol type command fail, ret =%d\n",
4892 status);
4893
4894 return status;
4895}
4896
46a3df9f
S		 4897static int hclge_init_vlan_config(struct hclge_dev *hdev)
4898{
5f6ea83f
PL		 4899#define HCLGE_DEF_VLAN_TYPE 0x8100
4900
5e43aef8 4901 struct hnae3_handle *handle;
5f6ea83f 4902 struct hclge_vport *vport;
46a3df9f 4903 int ret;
5f6ea83f
PL		 4904 int i;
4905
4906 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4907 if (ret)
4908 return ret;
46a3df9f 4909
5f6ea83f 4910 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4911 if (ret)
4912 return ret;
4913
5f6ea83f
PL		 4914 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4915 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4916 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4917 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4918 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4919 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4920
4921 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4922 if (ret)
4923 return ret;
46a3df9f 4924
5f6ea83f
PL		 4925 for (i = 0; i < hdev->num_alloc_vport; i++) {
4926 vport = &hdev->vport[i];
dcb35cce
PL		 4927 vport->txvlan_cfg.accept_tag1 = true;
4928 vport->txvlan_cfg.accept_untag1 = true;
4929
4930 /* accept_tag2 and accept_untag2 are not supported on
4931 * pdev revision(0x20), new revision support them. The
4932 * value of this two fields will not return error when driver
4933 * send command to fireware in revision(0x20).
4934 * This two fields can not configured by user.
4935 */
4936 vport->txvlan_cfg.accept_tag2 = true;
4937 vport->txvlan_cfg.accept_untag2 = true;
4938
5f6ea83f
PL		 4939 vport->txvlan_cfg.insert_tag1_en = false;
4940 vport->txvlan_cfg.insert_tag2_en = false;
4941 vport->txvlan_cfg.default_tag1 = 0;
4942 vport->txvlan_cfg.default_tag2 = 0;
4943
4944 ret = hclge_set_vlan_tx_offload_cfg(vport);
4945 if (ret)
4946 return ret;
4947
4948 vport->rxvlan_cfg.strip_tag1_en = false;
4949 vport->rxvlan_cfg.strip_tag2_en = true;
4950 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4951 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4952
4953 ret = hclge_set_vlan_rx_offload_cfg(vport);
4954 if (ret)
4955 return ret;
4956 }
4957
5e43aef8 4958 handle = &hdev->vport[0].nic;
dc8131d8 4959 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4960}
4961
b2641e2a 4962int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
052ece6d
PL		 4963{
4964 struct hclge_vport *vport = hclge_get_vport(handle);
4965
4966 vport->rxvlan_cfg.strip_tag1_en = false;
4967 vport->rxvlan_cfg.strip_tag2_en = enable;
4968 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4969 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4970
4971 return hclge_set_vlan_rx_offload_cfg(vport);
4972}
4973
dd72140c 4974static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 4975{
d44f9b63 4976 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 4977 struct hclge_desc desc;
2866ccb2 4978 int max_frm_size;
46a3df9f
S		 4979 int ret;
4980
2866ccb2
FL		 4981 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4982
4983 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4984 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4985 return -EINVAL;
4986
2866ccb2
FL		 4987 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4988
46a3df9f
S		 4989 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4990
d44f9b63 4991 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
2866ccb2 4992 req->max_frm_size = cpu_to_le16(max_frm_size);
46a3df9f
S		 4993
4994 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4995 if (ret) {
4996 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4997 return ret;
4998 }
4999
2866ccb2
FL		 5000 hdev->mps = max_frm_size;
5001
46a3df9f
S		 5002 return 0;
5003}
5004
dd72140c
FL		 5005static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5006{
5007 struct hclge_vport *vport = hclge_get_vport(handle);
5008 struct hclge_dev *hdev = vport->back;
5009 int ret;
5010
5011 ret = hclge_set_mac_mtu(hdev, new_mtu);
5012 if (ret) {
5013 dev_err(&hdev->pdev->dev,
5014 "Change mtu fail, ret =%d\n", ret);
5015 return ret;
5016 }
5017
5018 ret = hclge_buffer_alloc(hdev);
5019 if (ret)
5020 dev_err(&hdev->pdev->dev,
5021 "Allocate buffer fail, ret =%d\n", ret);
5022
5023 return ret;
5024}
5025
46a3df9f
S		 5026static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5027 bool enable)
5028{
d44f9b63 5029 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5030 struct hclge_desc desc;
5031 int ret;
5032
5033 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5034
d44f9b63 5035 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 5036 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5037 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
5038
5039 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5040 if (ret) {
5041 dev_err(&hdev->pdev->dev,
5042 "Send tqp reset cmd error, status =%d\n", ret);
5043 return ret;
5044 }
5045
5046 return 0;
5047}
5048
5049static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5050{
d44f9b63 5051 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5052 struct hclge_desc desc;
5053 int ret;
5054
5055 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5056
d44f9b63 5057 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 5058 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5059
5060 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5061 if (ret) {
5062 dev_err(&hdev->pdev->dev,
5063 "Get reset status error, status =%d\n", ret);
5064 return ret;
5065 }
5066
5067 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
5068}
5069
814e0274
PL		 5070static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5071 u16 queue_id)
5072{
5073 struct hnae3_queue *queue;
5074 struct hclge_tqp *tqp;
5075
5076 queue = handle->kinfo.tqp[queue_id];
5077 tqp = container_of(queue, struct hclge_tqp, q);
5078
5079 return tqp->index;
5080}
5081
84e095d6 5082void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 5083{
5084 struct hclge_vport *vport = hclge_get_vport(handle);
5085 struct hclge_dev *hdev = vport->back;
5086 int reset_try_times = 0;
5087 int reset_status;
814e0274 5088 u16 queue_gid;
46a3df9f
S		 5089 int ret;
5090
b50ae26c
PL		 5091 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5092 return;
5093
814e0274
PL		 5094 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5095
46a3df9f
S		 5096 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5097 if (ret) {
5098 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5099 return;
5100 }
5101
814e0274 5102 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 5103 if (ret) {
5104 dev_warn(&hdev->pdev->dev,
5105 "Send reset tqp cmd fail, ret = %d\n", ret);
5106 return;
5107 }
5108
5109 reset_try_times = 0;
5110 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5111 /* Wait for tqp hw reset */
5112 msleep(20);
814e0274 5113 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 5114 if (reset_status)
5115 break;
5116 }
5117
5118 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5119 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5120 return;
5121 }
5122
814e0274 5123 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 5124 if (ret) {
5125 dev_warn(&hdev->pdev->dev,
5126 "Deassert the soft reset fail, ret = %d\n", ret);
5127 return;
5128 }
5129}
5130
1a426f8b
PL		 5131void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5132{
5133 struct hclge_dev *hdev = vport->back;
5134 int reset_try_times = 0;
5135 int reset_status;
5136 u16 queue_gid;
5137 int ret;
5138
5139 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5140
5141 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5142 if (ret) {
5143 dev_warn(&hdev->pdev->dev,
5144 "Send reset tqp cmd fail, ret = %d\n", ret);
5145 return;
5146 }
5147
5148 reset_try_times = 0;
5149 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5150 /* Wait for tqp hw reset */
5151 msleep(20);
5152 reset_status = hclge_get_reset_status(hdev, queue_gid);
5153 if (reset_status)
5154 break;
5155 }
5156
5157 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5158 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5159 return;
5160 }
5161
5162 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5163 if (ret)
5164 dev_warn(&hdev->pdev->dev,
5165 "Deassert the soft reset fail, ret = %d\n", ret);
5166}
5167
46a3df9f
S		 5168static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5169{
5170 struct hclge_vport *vport = hclge_get_vport(handle);
5171 struct hclge_dev *hdev = vport->back;
5172
5173 return hdev->fw_version;
5174}
5175
f34ffffd
PL		 5176static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5177 u32 *flowctrl_adv)
5178{
5179 struct hclge_vport *vport = hclge_get_vport(handle);
5180 struct hclge_dev *hdev = vport->back;
5181 struct phy_device *phydev = hdev->hw.mac.phydev;
5182
5183 if (!phydev)
5184 return;
5185
5186 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5187 (phydev->advertising & ADVERTISED_Asym_Pause);
5188}
5189
61387774
PL		 5190static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5191{
5192 struct phy_device *phydev = hdev->hw.mac.phydev;
5193
5194 if (!phydev)
5195 return;
5196
5197 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5198
5199 if (rx_en)
5200 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5201
5202 if (tx_en)
5203 phydev->advertising ^= ADVERTISED_Asym_Pause;
5204}
5205
5206static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5207{
61387774
PL		 5208 int ret;
5209
5210 if (rx_en && tx_en)
40173a2e 5211 hdev->fc_mode_last_time = HCLGE_FC_FULL;
61387774 5212 else if (rx_en && !tx_en)
40173a2e 5213 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
61387774 5214 else if (!rx_en && tx_en)
40173a2e 5215 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
61387774 5216 else
40173a2e 5217 hdev->fc_mode_last_time = HCLGE_FC_NONE;
61387774 5218
40173a2e 5219 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
61387774 5220 return 0;
61387774
PL		 5221
5222 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5223 if (ret) {
5224 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5225 ret);
5226 return ret;
5227 }
5228
40173a2e 5229 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
61387774
PL		 5230
5231 return 0;
5232}
5233
1770a7a3
PL		 5234int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5235{
5236 struct phy_device *phydev = hdev->hw.mac.phydev;
5237 u16 remote_advertising = 0;
5238 u16 local_advertising = 0;
5239 u32 rx_pause, tx_pause;
5240 u8 flowctl;
5241
5242 if (!phydev->link || !phydev->autoneg)
5243 return 0;
5244
5245 if (phydev->advertising & ADVERTISED_Pause)
5246 local_advertising = ADVERTISE_PAUSE_CAP;
5247
5248 if (phydev->advertising & ADVERTISED_Asym_Pause)
5249 local_advertising |= ADVERTISE_PAUSE_ASYM;
5250
5251 if (phydev->pause)
5252 remote_advertising = LPA_PAUSE_CAP;
5253
5254 if (phydev->asym_pause)
5255 remote_advertising |= LPA_PAUSE_ASYM;
5256
5257 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5258 remote_advertising);
5259 tx_pause = flowctl & FLOW_CTRL_TX;
5260 rx_pause = flowctl & FLOW_CTRL_RX;
5261
5262 if (phydev->duplex == HCLGE_MAC_HALF) {
5263 tx_pause = 0;
5264 rx_pause = 0;
5265 }
5266
5267 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5268}
5269
46a3df9f
S		 5270static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5271 u32 *rx_en, u32 *tx_en)
5272{
5273 struct hclge_vport *vport = hclge_get_vport(handle);
5274 struct hclge_dev *hdev = vport->back;
5275
5276 *auto_neg = hclge_get_autoneg(handle);
5277
5278 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5279 *rx_en = 0;
5280 *tx_en = 0;
5281 return;
5282 }
5283
5284 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5285 *rx_en = 1;
5286 *tx_en = 0;
5287 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5288 *tx_en = 1;
5289 *rx_en = 0;
5290 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5291 *rx_en = 1;
5292 *tx_en = 1;
5293 } else {
5294 *rx_en = 0;
5295 *tx_en = 0;
5296 }
5297}
5298
61387774
PL		 5299static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5300 u32 rx_en, u32 tx_en)
5301{
5302 struct hclge_vport *vport = hclge_get_vport(handle);
5303 struct hclge_dev *hdev = vport->back;
5304 struct phy_device *phydev = hdev->hw.mac.phydev;
5305 u32 fc_autoneg;
5306
61387774
PL		 5307 fc_autoneg = hclge_get_autoneg(handle);
5308 if (auto_neg != fc_autoneg) {
5309 dev_info(&hdev->pdev->dev,
5310 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5311 return -EOPNOTSUPP;
5312 }
5313
5314 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5315 dev_info(&hdev->pdev->dev,
5316 "Priority flow control enabled. Cannot set link flow control.\n");
5317 return -EOPNOTSUPP;
5318 }
5319
5320 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5321
5322 if (!fc_autoneg)
5323 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5324
0c963e8c
FL		 5325 /* Only support flow control negotiation for netdev with
5326 * phy attached for now.
5327 */
5328 if (!phydev)
5329 return -EOPNOTSUPP;
5330
61387774
PL		 5331 return phy_start_aneg(phydev);
5332}
5333
46a3df9f
S		 5334static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5335 u8 *auto_neg, u32 *speed, u8 *duplex)
5336{
5337 struct hclge_vport *vport = hclge_get_vport(handle);
5338 struct hclge_dev *hdev = vport->back;
5339
5340 if (speed)
5341 *speed = hdev->hw.mac.speed;
5342 if (duplex)
5343 *duplex = hdev->hw.mac.duplex;
5344 if (auto_neg)
5345 *auto_neg = hdev->hw.mac.autoneg;
5346}
5347
5348static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5349{
5350 struct hclge_vport *vport = hclge_get_vport(handle);
5351 struct hclge_dev *hdev = vport->back;
5352
5353 if (media_type)
5354 *media_type = hdev->hw.mac.media_type;
5355}
5356
5357static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5358 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5359{
5360 struct hclge_vport *vport = hclge_get_vport(handle);
5361 struct hclge_dev *hdev = vport->back;
5362 struct phy_device *phydev = hdev->hw.mac.phydev;
5363 int mdix_ctrl, mdix, retval, is_resolved;
5364
5365 if (!phydev) {
5366 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5367 *tp_mdix = ETH_TP_MDI_INVALID;
5368 return;
5369 }
5370
5371 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5372
5373 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5374 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5375 HCLGE_PHY_MDIX_CTRL_S);
5376
5377 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5378 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5379 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5380
5381 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5382
5383 switch (mdix_ctrl) {
5384 case 0x0:
5385 *tp_mdix_ctrl = ETH_TP_MDI;
5386 break;
5387 case 0x1:
5388 *tp_mdix_ctrl = ETH_TP_MDI_X;
5389 break;
5390 case 0x3:
5391 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5392 break;
5393 default:
5394 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5395 break;
5396 }
5397
5398 if (!is_resolved)
5399 *tp_mdix = ETH_TP_MDI_INVALID;
5400 else if (mdix)
5401 *tp_mdix = ETH_TP_MDI_X;
5402 else
5403 *tp_mdix = ETH_TP_MDI;
5404}
5405
5406static int hclge_init_client_instance(struct hnae3_client *client,
5407 struct hnae3_ae_dev *ae_dev)
5408{
5409 struct hclge_dev *hdev = ae_dev->priv;
5410 struct hclge_vport *vport;
5411 int i, ret;
5412
5413 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5414 vport = &hdev->vport[i];
5415
5416 switch (client->type) {
5417 case HNAE3_CLIENT_KNIC:
5418
5419 hdev->nic_client = client;
5420 vport->nic.client = client;
5421 ret = client->ops->init_instance(&vport->nic);
5422 if (ret)
99a6993a 5423 return ret;
46a3df9f
S		 5424
5425 if (hdev->roce_client &&
e92a0843 5426 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5427 struct hnae3_client *rc = hdev->roce_client;
5428
5429 ret = hclge_init_roce_base_info(vport);
5430 if (ret)
99a6993a 5431 return ret;
46a3df9f
S		 5432
5433 ret = rc->ops->init_instance(&vport->roce);
5434 if (ret)
99a6993a 5435 return ret;
46a3df9f
S		 5436 }
5437
5438 break;
5439 case HNAE3_CLIENT_UNIC:
5440 hdev->nic_client = client;
5441 vport->nic.client = client;
5442
5443 ret = client->ops->init_instance(&vport->nic);
5444 if (ret)
99a6993a 5445 return ret;
46a3df9f
S		 5446
5447 break;
5448 case HNAE3_CLIENT_ROCE:
e92a0843 5449 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5450 hdev->roce_client = client;
5451 vport->roce.client = client;
5452 }
5453
3a46f34d 5454 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5455 ret = hclge_init_roce_base_info(vport);
5456 if (ret)
99a6993a 5457 return ret;
46a3df9f
S		 5458
5459 ret = client->ops->init_instance(&vport->roce);
5460 if (ret)
99a6993a 5461 return ret;
46a3df9f
S		 5462 }
5463 }
5464 }
5465
5466 return 0;
46a3df9f
S		 5467}
5468
5469static void hclge_uninit_client_instance(struct hnae3_client *client,
5470 struct hnae3_ae_dev *ae_dev)
5471{
5472 struct hclge_dev *hdev = ae_dev->priv;
5473 struct hclge_vport *vport;
5474 int i;
5475
5476 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5477 vport = &hdev->vport[i];
a17dcf3f 5478 if (hdev->roce_client) {
46a3df9f
S		 5479 hdev->roce_client->ops->uninit_instance(&vport->roce,
5480 0);
a17dcf3f
L		 5481 hdev->roce_client = NULL;
5482 vport->roce.client = NULL;
5483 }
46a3df9f
S		 5484 if (client->type == HNAE3_CLIENT_ROCE)
5485 return;
a17dcf3f 5486 if (client->ops->uninit_instance) {
46a3df9f 5487 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5488 hdev->nic_client = NULL;
5489 vport->nic.client = NULL;
5490 }
46a3df9f
S		 5491 }
5492}
5493
5494static int hclge_pci_init(struct hclge_dev *hdev)
5495{
5496 struct pci_dev *pdev = hdev->pdev;
5497 struct hclge_hw *hw;
5498 int ret;
5499
5500 ret = pci_enable_device(pdev);
5501 if (ret) {
5502 dev_err(&pdev->dev, "failed to enable PCI device\n");
3e249d3b 5503 return ret;
46a3df9f
S		 5504 }
5505
5506 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5507 if (ret) {
5508 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5509 if (ret) {
5510 dev_err(&pdev->dev,
5511 "can't set consistent PCI DMA");
5512 goto err_disable_device;
5513 }
5514 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5515 }
5516
5517 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5518 if (ret) {
5519 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5520 goto err_disable_device;
5521 }
5522
5523 pci_set_master(pdev);
5524 hw = &hdev->hw;
5525 hw->back = hdev;
5526 hw->io_base = pcim_iomap(pdev, 2, 0);
5527 if (!hw->io_base) {
5528 dev_err(&pdev->dev, "Can't map configuration register space\n");
5529 ret = -ENOMEM;
5530 goto err_clr_master;
5531 }
5532
709eb41a
L		 5533 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5534
46a3df9f
S		 5535 return 0;
5536err_clr_master:
5537 pci_clear_master(pdev);
5538 pci_release_regions(pdev);
5539err_disable_device:
5540 pci_disable_device(pdev);
46a3df9f
S		 5541
5542 return ret;
5543}
5544
5545static void hclge_pci_uninit(struct hclge_dev *hdev)
5546{
5547 struct pci_dev *pdev = hdev->pdev;
5548
6a814413 5549 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5550 pci_free_irq_vectors(pdev);
46a3df9f
S		 5551 pci_clear_master(pdev);
5552 pci_release_mem_regions(pdev);
5553 pci_disable_device(pdev);
5554}
5555
5556static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5557{
5558 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5559 struct hclge_dev *hdev;
5560 int ret;
5561
5562 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5563 if (!hdev) {
5564 ret = -ENOMEM;
ffd5656e 5565 goto out;
46a3df9f
S		 5566 }
5567
46a3df9f
S		 5568 hdev->pdev = pdev;
5569 hdev->ae_dev = ae_dev;
4ed340ab 5570 hdev->reset_type = HNAE3_NONE_RESET;
cb1b9f77 5571 hdev->reset_request = 0;
ca1d7669 5572 hdev->reset_pending = 0;
46a3df9f
S		 5573 ae_dev->priv = hdev;
5574
46a3df9f
S		 5575 ret = hclge_pci_init(hdev);
5576 if (ret) {
5577 dev_err(&pdev->dev, "PCI init failed\n");
ffd5656e 5578 goto out;
46a3df9f
S		 5579 }
5580
3efb960f
L		 5581 /* Firmware command queue initialize */
5582 ret = hclge_cmd_queue_init(hdev);
5583 if (ret) {
5584 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
ffd5656e 5585 goto err_pci_uninit;
3efb960f
L		 5586 }
5587
5588 /* Firmware command initialize */
46a3df9f
S		 5589 ret = hclge_cmd_init(hdev);
5590 if (ret)
ffd5656e 5591 goto err_cmd_uninit;
46a3df9f
S		 5592
5593 ret = hclge_get_cap(hdev);
5594 if (ret) {
e00e2197
CIK		 5595 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5596 ret);
ffd5656e 5597 goto err_cmd_uninit;
46a3df9f
S		 5598 }
5599
5600 ret = hclge_configure(hdev);
5601 if (ret) {
5602 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
ffd5656e 5603 goto err_cmd_uninit;
46a3df9f
S		 5604 }
5605
887c3820 5606 ret = hclge_init_msi(hdev);
46a3df9f 5607 if (ret) {
887c3820 5608 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
ffd5656e 5609 goto err_cmd_uninit;
46a3df9f
S		 5610 }
5611
466b0c00
L		 5612 ret = hclge_misc_irq_init(hdev);
5613 if (ret) {
5614 dev_err(&pdev->dev,
5615 "Misc IRQ(vector0) init error, ret = %d.\n",
5616 ret);
ffd5656e 5617 goto err_msi_uninit;
466b0c00
L		 5618 }
5619
46a3df9f
S		 5620 ret = hclge_alloc_tqps(hdev);
5621 if (ret) {
5622 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
ffd5656e 5623 goto err_msi_irq_uninit;
46a3df9f
S		 5624 }
5625
5626 ret = hclge_alloc_vport(hdev);
5627 if (ret) {
5628 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
ffd5656e 5629 goto err_msi_irq_uninit;
46a3df9f
S		 5630 }
5631
7df7dad6
L		 5632 ret = hclge_map_tqp(hdev);
5633 if (ret) {
5634 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
2312e050 5635 goto err_msi_irq_uninit;
7df7dad6
L		 5636 }
5637
c5ef83cb
HT		 5638 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5639 ret = hclge_mac_mdio_config(hdev);
5640 if (ret) {
5641 dev_err(&hdev->pdev->dev,
5642 "mdio config fail ret=%d\n", ret);
2312e050 5643 goto err_msi_irq_uninit;
c5ef83cb 5644 }
cf9cca2d 5645 }
5646
46a3df9f
S		 5647 ret = hclge_mac_init(hdev);
5648 if (ret) {
5649 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
ffd5656e 5650 goto err_mdiobus_unreg;
46a3df9f 5651 }
46a3df9f
S		 5652
5653 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5654 if (ret) {
5655 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
ffd5656e 5656 goto err_mdiobus_unreg;
46a3df9f
S		 5657 }
5658
46a3df9f
S		 5659 ret = hclge_init_vlan_config(hdev);
5660 if (ret) {
5661 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
ffd5656e 5662 goto err_mdiobus_unreg;
46a3df9f
S		 5663 }
5664
5665 ret = hclge_tm_schd_init(hdev);
5666 if (ret) {
5667 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
ffd5656e 5668 goto err_mdiobus_unreg;
68ece54e
YL		 5669 }
5670
268f5dfa 5671 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5672 ret = hclge_rss_init_hw(hdev);
5673 if (ret) {
5674 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
ffd5656e 5675 goto err_mdiobus_unreg;
46a3df9f
S		 5676 }
5677
f5aac71c
FL		 5678 ret = init_mgr_tbl(hdev);
5679 if (ret) {
5680 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
ffd5656e 5681 goto err_mdiobus_unreg;
f5aac71c
FL		 5682 }
5683
cacde272
YL		 5684 hclge_dcb_ops_set(hdev);
5685
d039ef68 5686 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5687 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 5688 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
c1a81619 5689 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5690
466b0c00
L		 5691 /* Enable MISC vector(vector0) */
5692 hclge_enable_vector(&hdev->misc_vector, true);
5693
46a3df9f
S		 5694 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5695 set_bit(HCLGE_STATE_DOWN, &hdev->state);
cb1b9f77
SM		 5696 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5697 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
c1a81619
SM		 5698 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5699 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
46a3df9f
S		 5700
5701 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5702 return 0;
5703
ffd5656e
HT		 5704err_mdiobus_unreg:
5705 if (hdev->hw.mac.phydev)
5706 mdiobus_unregister(hdev->hw.mac.mdio_bus);
ffd5656e
HT		 5707err_msi_irq_uninit:
5708 hclge_misc_irq_uninit(hdev);
5709err_msi_uninit:
5710 pci_free_irq_vectors(pdev);
5711err_cmd_uninit:
5712 hclge_destroy_cmd_queue(&hdev->hw);
5713err_pci_uninit:
6a814413 5714 pcim_iounmap(pdev, hdev->hw.io_base);
ffd5656e 5715 pci_clear_master(pdev);
46a3df9f 5716 pci_release_regions(pdev);
ffd5656e 5717 pci_disable_device(pdev);
ffd5656e 5718out:
46a3df9f
S		 5719 return ret;
5720}
5721
c6dc5213 5722static void hclge_stats_clear(struct hclge_dev *hdev)
5723{
5724 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5725}
5726
4ed340ab
L		 5727static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5728{
5729 struct hclge_dev *hdev = ae_dev->priv;
5730 struct pci_dev *pdev = ae_dev->pdev;
5731 int ret;
5732
5733 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5734
c6dc5213 5735 hclge_stats_clear(hdev);
dc8131d8 5736 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5737
4ed340ab
L		 5738 ret = hclge_cmd_init(hdev);
5739 if (ret) {
5740 dev_err(&pdev->dev, "Cmd queue init failed\n");
5741 return ret;
5742 }
5743
5744 ret = hclge_get_cap(hdev);
5745 if (ret) {
5746 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5747 ret);
5748 return ret;
5749 }
5750
5751 ret = hclge_configure(hdev);
5752 if (ret) {
5753 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5754 return ret;
5755 }
5756
5757 ret = hclge_map_tqp(hdev);
5758 if (ret) {
5759 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5760 return ret;
5761 }
5762
5763 ret = hclge_mac_init(hdev);
5764 if (ret) {
5765 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5766 return ret;
5767 }
5768
4ed340ab
L		 5769 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5770 if (ret) {
5771 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5772 return ret;
5773 }
5774
5775 ret = hclge_init_vlan_config(hdev);
5776 if (ret) {
5777 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5778 return ret;
5779 }
5780
f31c1ba6 5781 ret = hclge_tm_init_hw(hdev);
4ed340ab 5782 if (ret) {
f31c1ba6 5783 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5784 return ret;
5785 }
5786
5787 ret = hclge_rss_init_hw(hdev);
5788 if (ret) {
5789 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5790 return ret;
5791 }
5792
4ed340ab
L		 5793 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5794 HCLGE_DRIVER_NAME);
5795
5796 return 0;
5797}
5798
46a3df9f
S		 5799static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5800{
5801 struct hclge_dev *hdev = ae_dev->priv;
5802 struct hclge_mac *mac = &hdev->hw.mac;
5803
5804 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5805
d039ef68 5806 if (hdev->service_timer.function)
46a3df9f
S		 5807 del_timer_sync(&hdev->service_timer);
5808 if (hdev->service_task.func)
5809 cancel_work_sync(&hdev->service_task);
cb1b9f77
SM		 5810 if (hdev->rst_service_task.func)
5811 cancel_work_sync(&hdev->rst_service_task);
c1a81619
SM		 5812 if (hdev->mbx_service_task.func)
5813 cancel_work_sync(&hdev->mbx_service_task);
46a3df9f
S		 5814
5815 if (mac->phydev)
5816 mdiobus_unregister(mac->mdio_bus);
5817
466b0c00
L		 5818 /* Disable MISC vector(vector0) */
5819 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 5820 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 5821 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5822 hclge_pci_uninit(hdev);
5823 ae_dev->priv = NULL;
5824}
5825
482d2e9c
PL		 5826static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5827{
5828 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5829 struct hclge_vport *vport = hclge_get_vport(handle);
5830 struct hclge_dev *hdev = vport->back;
5831
5832 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5833}
5834
5835static void hclge_get_channels(struct hnae3_handle *handle,
5836 struct ethtool_channels *ch)
5837{
5838 struct hclge_vport *vport = hclge_get_vport(handle);
5839
5840 ch->max_combined = hclge_get_max_channels(handle);
5841 ch->other_count = 1;
5842 ch->max_other = 1;
5843 ch->combined_count = vport->alloc_tqps;
5844}
5845
09f2af64
PL		 5846static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5847 u16 *free_tqps, u16 *max_rss_size)
5848{
5849 struct hclge_vport *vport = hclge_get_vport(handle);
5850 struct hclge_dev *hdev = vport->back;
5851 u16 temp_tqps = 0;
5852 int i;
5853
5854 for (i = 0; i < hdev->num_tqps; i++) {
5855 if (!hdev->htqp[i].alloced)
5856 temp_tqps++;
5857 }
5858 *free_tqps = temp_tqps;
5859 *max_rss_size = hdev->rss_size_max;
5860}
5861
5862static void hclge_release_tqp(struct hclge_vport *vport)
5863{
5864 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5865 struct hclge_dev *hdev = vport->back;
5866 int i;
5867
5868 for (i = 0; i < kinfo->num_tqps; i++) {
5869 struct hclge_tqp *tqp =
5870 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5871
5872 tqp->q.handle = NULL;
5873 tqp->q.tqp_index = 0;
5874 tqp->alloced = false;
5875 }
5876
5877 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5878 kinfo->tqp = NULL;
5879}
5880
5881static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5882{
5883 struct hclge_vport *vport = hclge_get_vport(handle);
5884 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5885 struct hclge_dev *hdev = vport->back;
5886 int cur_rss_size = kinfo->rss_size;
5887 int cur_tqps = kinfo->num_tqps;
5888 u16 tc_offset[HCLGE_MAX_TC_NUM];
5889 u16 tc_valid[HCLGE_MAX_TC_NUM];
5890 u16 tc_size[HCLGE_MAX_TC_NUM];
5891 u16 roundup_size;
5892 u32 *rss_indir;
5893 int ret, i;
5894
5895 hclge_release_tqp(vport);
5896
5897 ret = hclge_knic_setup(vport, new_tqps_num);
5898 if (ret) {
5899 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5900 return ret;
5901 }
5902
5903 ret = hclge_map_tqp_to_vport(hdev, vport);
5904 if (ret) {
5905 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5906 return ret;
5907 }
5908
5909 ret = hclge_tm_schd_init(hdev);
5910 if (ret) {
5911 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5912 return ret;
5913 }
5914
5915 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5916 roundup_size = ilog2(roundup_size);
5917 /* Set the RSS TC mode according to the new RSS size */
5918 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5919 tc_valid[i] = 0;
5920
5921 if (!(hdev->hw_tc_map & BIT(i)))
5922 continue;
5923
5924 tc_valid[i] = 1;
5925 tc_size[i] = roundup_size;
5926 tc_offset[i] = kinfo->rss_size * i;
5927 }
5928 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5929 if (ret)
5930 return ret;
5931
5932 /* Reinitializes the rss indirect table according to the new RSS size */
5933 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5934 if (!rss_indir)
5935 return -ENOMEM;
5936
5937 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5938 rss_indir[i] = i % kinfo->rss_size;
5939
5940 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5941 if (ret)
5942 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5943 ret);
5944
5945 kfree(rss_indir);
5946
5947 if (!ret)
5948 dev_info(&hdev->pdev->dev,
5949 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5950 cur_rss_size, kinfo->rss_size,
5951 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5952
5953 return ret;
5954}
5955
77b34110
FL		 5956static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5957 u32 *regs_num_64_bit)
5958{
5959 struct hclge_desc desc;
5960 u32 total_num;
5961 int ret;
5962
5963 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5964 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5965 if (ret) {
5966 dev_err(&hdev->pdev->dev,
5967 "Query register number cmd failed, ret = %d.\n", ret);
5968 return ret;
5969 }
5970
5971 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5972 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5973
5974 total_num = *regs_num_32_bit + *regs_num_64_bit;
5975 if (!total_num)
5976 return -EINVAL;
5977
5978 return 0;
5979}
5980
5981static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5982 void *data)
5983{
5984#define HCLGE_32_BIT_REG_RTN_DATANUM 8
5985
5986 struct hclge_desc *desc;
5987 u32 *reg_val = data;
5988 __le32 *desc_data;
5989 int cmd_num;
5990 int i, k, n;
5991 int ret;
5992
5993 if (regs_num == 0)
5994 return 0;
5995
5996 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
5997 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5998 if (!desc)
5999 return -ENOMEM;
6000
6001 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6002 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6003 if (ret) {
6004 dev_err(&hdev->pdev->dev,
6005 "Query 32 bit register cmd failed, ret = %d.\n", ret);
6006 kfree(desc);
6007 return ret;
6008 }
6009
6010 for (i = 0; i < cmd_num; i++) {
6011 if (i == 0) {
6012 desc_data = (__le32 *)(&desc[i].data[0]);
6013 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6014 } else {
6015 desc_data = (__le32 *)(&desc[i]);
6016 n = HCLGE_32_BIT_REG_RTN_DATANUM;
6017 }
6018 for (k = 0; k < n; k++) {
6019 *reg_val++ = le32_to_cpu(*desc_data++);
6020
6021 regs_num--;
6022 if (!regs_num)
6023 break;
6024 }
6025 }
6026
6027 kfree(desc);
6028 return 0;
6029}
6030
6031static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6032 void *data)
6033{
6034#define HCLGE_64_BIT_REG_RTN_DATANUM 4
6035
6036 struct hclge_desc *desc;
6037 u64 *reg_val = data;
6038 __le64 *desc_data;
6039 int cmd_num;
6040 int i, k, n;
6041 int ret;
6042
6043 if (regs_num == 0)
6044 return 0;
6045
6046 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6047 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6048 if (!desc)
6049 return -ENOMEM;
6050
6051 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6052 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6053 if (ret) {
6054 dev_err(&hdev->pdev->dev,
6055 "Query 64 bit register cmd failed, ret = %d.\n", ret);
6056 kfree(desc);
6057 return ret;
6058 }
6059
6060 for (i = 0; i < cmd_num; i++) {
6061 if (i == 0) {
6062 desc_data = (__le64 *)(&desc[i].data[0]);
6063 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6064 } else {
6065 desc_data = (__le64 *)(&desc[i]);
6066 n = HCLGE_64_BIT_REG_RTN_DATANUM;
6067 }
6068 for (k = 0; k < n; k++) {
6069 *reg_val++ = le64_to_cpu(*desc_data++);
6070
6071 regs_num--;
6072 if (!regs_num)
6073 break;
6074 }
6075 }
6076
6077 kfree(desc);
6078 return 0;
6079}
6080
6081static int hclge_get_regs_len(struct hnae3_handle *handle)
6082{
6083 struct hclge_vport *vport = hclge_get_vport(handle);
6084 struct hclge_dev *hdev = vport->back;
6085 u32 regs_num_32_bit, regs_num_64_bit;
6086 int ret;
6087
6088 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6089 if (ret) {
6090 dev_err(&hdev->pdev->dev,
6091 "Get register number failed, ret = %d.\n", ret);
6092 return -EOPNOTSUPP;
6093 }
6094
6095 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6096}
6097
6098static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6099 void *data)
6100{
6101 struct hclge_vport *vport = hclge_get_vport(handle);
6102 struct hclge_dev *hdev = vport->back;
6103 u32 regs_num_32_bit, regs_num_64_bit;
6104 int ret;
6105
6106 *version = hdev->fw_version;
6107
6108 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6109 if (ret) {
6110 dev_err(&hdev->pdev->dev,
6111 "Get register number failed, ret = %d.\n", ret);
6112 return;
6113 }
6114
6115 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6116 if (ret) {
6117 dev_err(&hdev->pdev->dev,
6118 "Get 32 bit register failed, ret = %d.\n", ret);
6119 return;
6120 }
6121
6122 data = (u32 *)data + regs_num_32_bit;
6123 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6124 data);
6125 if (ret)
6126 dev_err(&hdev->pdev->dev,
6127 "Get 64 bit register failed, ret = %d.\n", ret);
6128}
6129
f6f75abc 6130static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
07f8e940
JS		 6131{
6132 struct hclge_set_led_state_cmd *req;
6133 struct hclge_desc desc;
6134 int ret;
6135
6136 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6137
6138 req = (struct hclge_set_led_state_cmd *)desc.data;
07f8e940
JS		 6139 hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
6140 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6141
6142 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6143 if (ret)
6144 dev_err(&hdev->pdev->dev,
6145 "Send set led state cmd error, ret =%d\n", ret);
6146
6147 return ret;
6148}
6149
6150enum hclge_led_status {
6151 HCLGE_LED_OFF,
6152 HCLGE_LED_ON,
6153 HCLGE_LED_NO_CHANGE = 0xFF,
6154};
6155
6156static int hclge_set_led_id(struct hnae3_handle *handle,
6157 enum ethtool_phys_id_state status)
6158{
07f8e940
JS		 6159 struct hclge_vport *vport = hclge_get_vport(handle);
6160 struct hclge_dev *hdev = vport->back;
07f8e940
JS		 6161
6162 switch (status) {
6163 case ETHTOOL_ID_ACTIVE:
f6f75abc 6164 return hclge_set_led_status(hdev, HCLGE_LED_ON);
07f8e940 6165 case ETHTOOL_ID_INACTIVE:
f6f75abc 6166 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
07f8e940 6167 default:
f6f75abc 6168 return -EINVAL;
07f8e940 6169 }
07f8e940
JS		 6170}
6171
0979aa0b
FL		 6172static void hclge_get_link_mode(struct hnae3_handle *handle,
6173 unsigned long *supported,
6174 unsigned long *advertising)
6175{
6176 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6177 struct hclge_vport *vport = hclge_get_vport(handle);
6178 struct hclge_dev *hdev = vport->back;
6179 unsigned int idx = 0;
6180
6181 for (; idx < size; idx++) {
6182 supported[idx] = hdev->hw.mac.supported[idx];
6183 advertising[idx] = hdev->hw.mac.advertising[idx];
6184 }
6185}
6186
6187static void hclge_get_port_type(struct hnae3_handle *handle,
6188 u8 *port_type)
6189{
6190 struct hclge_vport *vport = hclge_get_vport(handle);
6191 struct hclge_dev *hdev = vport->back;
6192 u8 media_type = hdev->hw.mac.media_type;
6193
6194 switch (media_type) {
6195 case HNAE3_MEDIA_TYPE_FIBER:
6196 *port_type = PORT_FIBRE;
6197 break;
6198 case HNAE3_MEDIA_TYPE_COPPER:
6199 *port_type = PORT_TP;
6200 break;
6201 case HNAE3_MEDIA_TYPE_UNKNOWN:
6202 default:
6203 *port_type = PORT_OTHER;
6204 break;
6205 }
6206}
6207
46a3df9f
S		 6208static const struct hnae3_ae_ops hclge_ops = {
6209 .init_ae_dev = hclge_init_ae_dev,
6210 .uninit_ae_dev = hclge_uninit_ae_dev,
6211 .init_client_instance = hclge_init_client_instance,
6212 .uninit_client_instance = hclge_uninit_client_instance,
84e095d6
SM		 6213 .map_ring_to_vector = hclge_map_ring_to_vector,
6214 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 6215 .get_vector = hclge_get_vector,
0d3e6631 6216 .put_vector = hclge_put_vector,
46a3df9f 6217 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 6218 .set_loopback = hclge_set_loopback,
46a3df9f
S		 6219 .start = hclge_ae_start,
6220 .stop = hclge_ae_stop,
6221 .get_status = hclge_get_status,
6222 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6223 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6224 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6225 .get_media_type = hclge_get_media_type,
6226 .get_rss_key_size = hclge_get_rss_key_size,
6227 .get_rss_indir_size = hclge_get_rss_indir_size,
6228 .get_rss = hclge_get_rss,
6229 .set_rss = hclge_set_rss,
f7db940a 6230 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 6231 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 6232 .get_tc_size = hclge_get_tc_size,
6233 .get_mac_addr = hclge_get_mac_addr,
6234 .set_mac_addr = hclge_set_mac_addr,
6235 .add_uc_addr = hclge_add_uc_addr,
6236 .rm_uc_addr = hclge_rm_uc_addr,
6237 .add_mc_addr = hclge_add_mc_addr,
6238 .rm_mc_addr = hclge_rm_mc_addr,
40cca1c5 6239 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6240 .set_autoneg = hclge_set_autoneg,
6241 .get_autoneg = hclge_get_autoneg,
6242 .get_pauseparam = hclge_get_pauseparam,
61387774 6243 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6244 .set_mtu = hclge_set_mtu,
6245 .reset_queue = hclge_reset_tqp,
6246 .get_stats = hclge_get_stats,
6247 .update_stats = hclge_update_stats,
6248 .get_strings = hclge_get_strings,
6249 .get_sset_count = hclge_get_sset_count,
6250 .get_fw_version = hclge_get_fw_version,
6251 .get_mdix_mode = hclge_get_mdix_mode,
391b5e93 6252 .enable_vlan_filter = hclge_enable_vlan_filter,
dc8131d8 6253 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6254 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
052ece6d 6255 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6256 .reset_event = hclge_reset_event,
09f2af64
PL		 6257 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6258 .set_channels = hclge_set_channels,
482d2e9c 6259 .get_channels = hclge_get_channels,
f34ffffd 6260 .get_flowctrl_adv = hclge_get_flowctrl_adv,
77b34110
FL		 6261 .get_regs_len = hclge_get_regs_len,
6262 .get_regs = hclge_get_regs,
07f8e940 6263 .set_led_id = hclge_set_led_id,
0979aa0b
FL		 6264 .get_link_mode = hclge_get_link_mode,
6265 .get_port_type = hclge_get_port_type,
46a3df9f
S		 6266};
6267
6268static struct hnae3_ae_algo ae_algo = {
6269 .ops = &hclge_ops,
6270 .name = HCLGE_NAME,
6271 .pdev_id_table = ae_algo_pci_tbl,
6272};
6273
6274static int hclge_init(void)
6275{
6276 pr_info("%s is initializing\n", HCLGE_NAME);
6277
854cf33a
FL		 6278 hnae3_register_ae_algo(&ae_algo);
6279
6280 return 0;
46a3df9f
S		 6281}
6282
6283static void hclge_exit(void)
6284{
6285 hnae3_unregister_ae_algo(&ae_algo);
6286}
6287module_init(hclge_init);
6288module_exit(hclge_exit);
6289
6290MODULE_LICENSE("GPL");
6291MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6292MODULE_DESCRIPTION("HCLGE Driver");
6293MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)