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net: hns3: Unified HNS3 {VF|PF} Ethernet Driver for hip08 SoC
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
f2f432f2 20#include <net/rtnetlink.h>
46a3df9f 21#include "hclge_cmd.h"
cacde272 22#include "hclge_dcb.h"
46a3df9f
S		 23#include "hclge_main.h"
24#include "hclge_mdio.h"
25#include "hclge_tm.h"
26#include "hnae3.h"
27
28#define HCLGE_NAME "hclge"
29#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
30#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
31#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
32#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
33
46a3df9f
S		 34static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
35 enum hclge_mta_dmac_sel_type mta_mac_sel,
36 bool enable);
37static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 38static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 39
40static struct hnae3_ae_algo ae_algo;
41
42static const struct pci_device_id ae_algo_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 50 /* required last entry */
46a3df9f
S		 51 {0, }
52};
53
54static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
55 "Mac Loopback test",
56 "Serdes Loopback test",
57 "Phy Loopback test"
58};
59
60static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
61 {"igu_rx_oversize_pkt",
62 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
63 {"igu_rx_undersize_pkt",
64 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
65 {"igu_rx_out_all_pkt",
66 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
67 {"igu_rx_uni_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
69 {"igu_rx_multi_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
71 {"igu_rx_broad_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
73 {"egu_tx_out_all_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
75 {"egu_tx_uni_pkt",
76 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
77 {"egu_tx_multi_pkt",
78 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
79 {"egu_tx_broad_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
81 {"ssu_ppp_mac_key_num",
82 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
83 {"ssu_ppp_host_key_num",
84 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
85 {"ppp_ssu_mac_rlt_num",
86 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
87 {"ppp_ssu_host_rlt_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
89 {"ssu_tx_in_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
91 {"ssu_tx_out_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
93 {"ssu_rx_in_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
95 {"ssu_rx_out_num",
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
97};
98
99static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
100 {"igu_rx_err_pkt",
101 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
102 {"igu_rx_no_eof_pkt",
103 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
104 {"igu_rx_no_sof_pkt",
105 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
106 {"egu_tx_1588_pkt",
107 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
108 {"ssu_full_drop_num",
109 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
110 {"ssu_part_drop_num",
111 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
112 {"ppp_key_drop_num",
113 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
114 {"ppp_rlt_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
116 {"ssu_key_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
118 {"pkt_curr_buf_cnt",
119 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
120 {"qcn_fb_rcv_cnt",
121 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
122 {"qcn_fb_drop_cnt",
123 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
124 {"qcn_fb_invaild_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
126 {"rx_packet_tc0_in_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
128 {"rx_packet_tc1_in_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
130 {"rx_packet_tc2_in_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
132 {"rx_packet_tc3_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
134 {"rx_packet_tc4_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
136 {"rx_packet_tc5_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
138 {"rx_packet_tc6_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
140 {"rx_packet_tc7_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
142 {"rx_packet_tc0_out_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
144 {"rx_packet_tc1_out_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
146 {"rx_packet_tc2_out_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
148 {"rx_packet_tc3_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
150 {"rx_packet_tc4_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
152 {"rx_packet_tc5_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
154 {"rx_packet_tc6_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
156 {"rx_packet_tc7_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
158 {"tx_packet_tc0_in_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
160 {"tx_packet_tc1_in_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
162 {"tx_packet_tc2_in_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
164 {"tx_packet_tc3_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
166 {"tx_packet_tc4_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
168 {"tx_packet_tc5_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
170 {"tx_packet_tc6_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
172 {"tx_packet_tc7_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
174 {"tx_packet_tc0_out_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
176 {"tx_packet_tc1_out_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
178 {"tx_packet_tc2_out_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
180 {"tx_packet_tc3_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
182 {"tx_packet_tc4_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
184 {"tx_packet_tc5_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
186 {"tx_packet_tc6_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
188 {"tx_packet_tc7_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
190 {"pkt_curr_buf_tc0_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
192 {"pkt_curr_buf_tc1_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
194 {"pkt_curr_buf_tc2_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
196 {"pkt_curr_buf_tc3_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
198 {"pkt_curr_buf_tc4_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
200 {"pkt_curr_buf_tc5_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
202 {"pkt_curr_buf_tc6_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
204 {"pkt_curr_buf_tc7_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
206 {"mb_uncopy_num",
207 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
208 {"lo_pri_unicast_rlt_drop_num",
209 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
210 {"hi_pri_multicast_rlt_drop_num",
211 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
212 {"lo_pri_multicast_rlt_drop_num",
213 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
214 {"rx_oq_drop_pkt_cnt",
215 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
216 {"tx_oq_drop_pkt_cnt",
217 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
218 {"nic_l2_err_drop_pkt_cnt",
219 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
220 {"roc_l2_err_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
222};
223
224static const struct hclge_comm_stats_str g_mac_stats_string[] = {
225 {"mac_tx_mac_pause_num",
226 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
227 {"mac_rx_mac_pause_num",
228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
229 {"mac_tx_pfc_pri0_pkt_num",
230 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
231 {"mac_tx_pfc_pri1_pkt_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
233 {"mac_tx_pfc_pri2_pkt_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
235 {"mac_tx_pfc_pri3_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
237 {"mac_tx_pfc_pri4_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
239 {"mac_tx_pfc_pri5_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
241 {"mac_tx_pfc_pri6_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
243 {"mac_tx_pfc_pri7_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
245 {"mac_rx_pfc_pri0_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
247 {"mac_rx_pfc_pri1_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
249 {"mac_rx_pfc_pri2_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
251 {"mac_rx_pfc_pri3_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
253 {"mac_rx_pfc_pri4_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
255 {"mac_rx_pfc_pri5_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
257 {"mac_rx_pfc_pri6_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
259 {"mac_rx_pfc_pri7_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
261 {"mac_tx_total_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
263 {"mac_tx_total_oct_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
265 {"mac_tx_good_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
267 {"mac_tx_bad_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
269 {"mac_tx_good_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
271 {"mac_tx_bad_oct_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
273 {"mac_tx_uni_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
275 {"mac_tx_multi_pkt_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
277 {"mac_tx_broad_pkt_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
279 {"mac_tx_undersize_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
281 {"mac_tx_overrsize_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
283 {"mac_tx_64_oct_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
285 {"mac_tx_65_127_oct_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
287 {"mac_tx_128_255_oct_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
289 {"mac_tx_256_511_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
291 {"mac_tx_512_1023_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
293 {"mac_tx_1024_1518_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
295 {"mac_tx_1519_max_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
297 {"mac_rx_total_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
299 {"mac_rx_total_oct_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
301 {"mac_rx_good_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
303 {"mac_rx_bad_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
305 {"mac_rx_good_oct_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
307 {"mac_rx_bad_oct_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
309 {"mac_rx_uni_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
311 {"mac_rx_multi_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
313 {"mac_rx_broad_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
315 {"mac_rx_undersize_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
317 {"mac_rx_overrsize_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
319 {"mac_rx_64_oct_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
321 {"mac_rx_65_127_oct_pkt_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
323 {"mac_rx_128_255_oct_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
325 {"mac_rx_256_511_oct_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
327 {"mac_rx_512_1023_oct_pkt_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
329 {"mac_rx_1024_1518_oct_pkt_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
331 {"mac_rx_1519_max_oct_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
333
334 {"mac_trans_fragment_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
336 {"mac_trans_undermin_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
338 {"mac_trans_jabber_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
340 {"mac_trans_err_all_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
342 {"mac_trans_from_app_good_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
344 {"mac_trans_from_app_bad_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
346 {"mac_rcv_fragment_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
348 {"mac_rcv_undermin_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
350 {"mac_rcv_jabber_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
352 {"mac_rcv_fcs_err_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
354 {"mac_rcv_send_app_good_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
356 {"mac_rcv_send_app_bad_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
358};
359
360static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
361{
362#define HCLGE_64_BIT_CMD_NUM 5
363#define HCLGE_64_BIT_RTN_DATANUM 4
364 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
365 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 366 __le64 *desc_data;
46a3df9f
S		 367 int i, k, n;
368 int ret;
369
370 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
371 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
372 if (ret) {
373 dev_err(&hdev->pdev->dev,
374 "Get 64 bit pkt stats fail, status = %d.\n", ret);
375 return ret;
376 }
377
378 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
379 if (unlikely(i == 0)) {
a90bb9a5 380 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 381 n = HCLGE_64_BIT_RTN_DATANUM - 1;
382 } else {
a90bb9a5 383 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 384 n = HCLGE_64_BIT_RTN_DATANUM;
385 }
386 for (k = 0; k < n; k++) {
a90bb9a5 387 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 388 desc_data++;
389 }
390 }
391
392 return 0;
393}
394
395static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
396{
397 stats->pkt_curr_buf_cnt = 0;
398 stats->pkt_curr_buf_tc0_cnt = 0;
399 stats->pkt_curr_buf_tc1_cnt = 0;
400 stats->pkt_curr_buf_tc2_cnt = 0;
401 stats->pkt_curr_buf_tc3_cnt = 0;
402 stats->pkt_curr_buf_tc4_cnt = 0;
403 stats->pkt_curr_buf_tc5_cnt = 0;
404 stats->pkt_curr_buf_tc6_cnt = 0;
405 stats->pkt_curr_buf_tc7_cnt = 0;
406}
407
408static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
409{
410#define HCLGE_32_BIT_CMD_NUM 8
411#define HCLGE_32_BIT_RTN_DATANUM 8
412
413 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
414 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 415 __le32 *desc_data;
46a3df9f
S		 416 int i, k, n;
417 u64 *data;
418 int ret;
419
420 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
421 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
422
423 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
424 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
425 if (ret) {
426 dev_err(&hdev->pdev->dev,
427 "Get 32 bit pkt stats fail, status = %d.\n", ret);
428
429 return ret;
430 }
431
432 hclge_reset_partial_32bit_counter(all_32_bit_stats);
433 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
434 if (unlikely(i == 0)) {
a90bb9a5
YL		 435 __le16 *desc_data_16bit;
436
46a3df9f 437 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 438 le32_to_cpu(desc[i].data[0]);
439
440 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 441 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 442 le16_to_cpu(*desc_data_16bit);
443
444 desc_data_16bit++;
46a3df9f 445 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 446 le16_to_cpu(*desc_data_16bit);
46a3df9f 447
a90bb9a5 448 desc_data = &desc[i].data[2];
46a3df9f
S		 449 n = HCLGE_32_BIT_RTN_DATANUM - 4;
450 } else {
a90bb9a5 451 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 452 n = HCLGE_32_BIT_RTN_DATANUM;
453 }
454 for (k = 0; k < n; k++) {
a90bb9a5 455 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 456 desc_data++;
457 }
458 }
459
460 return 0;
461}
462
463static int hclge_mac_update_stats(struct hclge_dev *hdev)
464{
465#define HCLGE_MAC_CMD_NUM 17
466#define HCLGE_RTN_DATA_NUM 4
467
468 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
469 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 470 __le64 *desc_data;
46a3df9f
S		 471 int i, k, n;
472 int ret;
473
474 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
475 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
476 if (ret) {
477 dev_err(&hdev->pdev->dev,
478 "Get MAC pkt stats fail, status = %d.\n", ret);
479
480 return ret;
481 }
482
483 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
484 if (unlikely(i == 0)) {
a90bb9a5 485 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 486 n = HCLGE_RTN_DATA_NUM - 2;
487 } else {
a90bb9a5 488 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 489 n = HCLGE_RTN_DATA_NUM;
490 }
491 for (k = 0; k < n; k++) {
a90bb9a5 492 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 493 desc_data++;
494 }
495 }
496
497 return 0;
498}
499
500static int hclge_tqps_update_stats(struct hnae3_handle *handle)
501{
502 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
503 struct hclge_vport *vport = hclge_get_vport(handle);
504 struct hclge_dev *hdev = vport->back;
505 struct hnae3_queue *queue;
506 struct hclge_desc desc[1];
507 struct hclge_tqp *tqp;
508 int ret, i;
509
510 for (i = 0; i < kinfo->num_tqps; i++) {
511 queue = handle->kinfo.tqp[i];
512 tqp = container_of(queue, struct hclge_tqp, q);
513 /* command : HCLGE_OPC_QUERY_IGU_STAT */
514 hclge_cmd_setup_basic_desc(&desc[0],
515 HCLGE_OPC_QUERY_RX_STATUS,
516 true);
517
a90bb9a5 518 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 519 ret = hclge_cmd_send(&hdev->hw, desc, 1);
520 if (ret) {
521 dev_err(&hdev->pdev->dev,
522 "Query tqp stat fail, status = %d,queue = %d\n",
523 ret, i);
524 return ret;
525 }
526 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
a90bb9a5 527 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 528 }
529
530 for (i = 0; i < kinfo->num_tqps; i++) {
531 queue = handle->kinfo.tqp[i];
532 tqp = container_of(queue, struct hclge_tqp, q);
533 /* command : HCLGE_OPC_QUERY_IGU_STAT */
534 hclge_cmd_setup_basic_desc(&desc[0],
535 HCLGE_OPC_QUERY_TX_STATUS,
536 true);
537
a90bb9a5 538 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 539 ret = hclge_cmd_send(&hdev->hw, desc, 1);
540 if (ret) {
541 dev_err(&hdev->pdev->dev,
542 "Query tqp stat fail, status = %d,queue = %d\n",
543 ret, i);
544 return ret;
545 }
546 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
a90bb9a5 547 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 548 }
549
550 return 0;
551}
552
553static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
554{
555 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
556 struct hclge_tqp *tqp;
557 u64 *buff = data;
558 int i;
559
560 for (i = 0; i < kinfo->num_tqps; i++) {
561 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 562 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 563 }
564
565 for (i = 0; i < kinfo->num_tqps; i++) {
566 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 567 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 568 }
569
570 return buff;
571}
572
573static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
574{
575 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
576
577 return kinfo->num_tqps * (2);
578}
579
580static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
581{
582 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
583 u8 *buff = data;
584 int i = 0;
585
586 for (i = 0; i < kinfo->num_tqps; i++) {
587 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
588 struct hclge_tqp, q);
589 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
590 tqp->index);
591 buff = buff + ETH_GSTRING_LEN;
592 }
593
594 for (i = 0; i < kinfo->num_tqps; i++) {
595 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
596 struct hclge_tqp, q);
597 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
598 tqp->index);
599 buff = buff + ETH_GSTRING_LEN;
600 }
601
602 return buff;
603}
604
605static u64 *hclge_comm_get_stats(void *comm_stats,
606 const struct hclge_comm_stats_str strs[],
607 int size, u64 *data)
608{
609 u64 *buf = data;
610 u32 i;
611
612 for (i = 0; i < size; i++)
613 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
614
615 return buf + size;
616}
617
618static u8 *hclge_comm_get_strings(u32 stringset,
619 const struct hclge_comm_stats_str strs[],
620 int size, u8 *data)
621{
622 char *buff = (char *)data;
623 u32 i;
624
625 if (stringset != ETH_SS_STATS)
626 return buff;
627
628 for (i = 0; i < size; i++) {
629 snprintf(buff, ETH_GSTRING_LEN,
630 strs[i].desc);
631 buff = buff + ETH_GSTRING_LEN;
632 }
633
634 return (u8 *)buff;
635}
636
637static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
638 struct net_device_stats *net_stats)
639{
640 net_stats->tx_dropped = 0;
641 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
642 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
643 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
644
645 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
646 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
647 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
648 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
649 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
650 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
651
652 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
653 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
654
655 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
656 net_stats->rx_length_errors =
657 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
658 net_stats->rx_length_errors +=
659 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
660 net_stats->rx_over_errors =
661 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
662}
663
664static void hclge_update_stats_for_all(struct hclge_dev *hdev)
665{
666 struct hnae3_handle *handle;
667 int status;
668
669 handle = &hdev->vport[0].nic;
670 if (handle->client) {
671 status = hclge_tqps_update_stats(handle);
672 if (status) {
673 dev_err(&hdev->pdev->dev,
674 "Update TQPS stats fail, status = %d.\n",
675 status);
676 }
677 }
678
679 status = hclge_mac_update_stats(hdev);
680 if (status)
681 dev_err(&hdev->pdev->dev,
682 "Update MAC stats fail, status = %d.\n", status);
683
684 status = hclge_32_bit_update_stats(hdev);
685 if (status)
686 dev_err(&hdev->pdev->dev,
687 "Update 32 bit stats fail, status = %d.\n",
688 status);
689
690 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
691}
692
693static void hclge_update_stats(struct hnae3_handle *handle,
694 struct net_device_stats *net_stats)
695{
696 struct hclge_vport *vport = hclge_get_vport(handle);
697 struct hclge_dev *hdev = vport->back;
698 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
699 int status;
700
701 status = hclge_mac_update_stats(hdev);
702 if (status)
703 dev_err(&hdev->pdev->dev,
704 "Update MAC stats fail, status = %d.\n",
705 status);
706
707 status = hclge_32_bit_update_stats(hdev);
708 if (status)
709 dev_err(&hdev->pdev->dev,
710 "Update 32 bit stats fail, status = %d.\n",
711 status);
712
713 status = hclge_64_bit_update_stats(hdev);
714 if (status)
715 dev_err(&hdev->pdev->dev,
716 "Update 64 bit stats fail, status = %d.\n",
717 status);
718
719 status = hclge_tqps_update_stats(handle);
720 if (status)
721 dev_err(&hdev->pdev->dev,
722 "Update TQPS stats fail, status = %d.\n",
723 status);
724
725 hclge_update_netstat(hw_stats, net_stats);
726}
727
728static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
729{
730#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
731
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 int count = 0;
735
736 /* Loopback test support rules:
737 * mac: only GE mode support
738 * serdes: all mac mode will support include GE/XGE/LGE/CGE
739 * phy: only support when phy device exist on board
740 */
741 if (stringset == ETH_SS_TEST) {
742 /* clear loopback bit flags at first */
743 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
744 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
745 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
746 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
747 count += 1;
748 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
749 } else {
750 count = -EOPNOTSUPP;
751 }
752 } else if (stringset == ETH_SS_STATS) {
753 count = ARRAY_SIZE(g_mac_stats_string) +
754 ARRAY_SIZE(g_all_32bit_stats_string) +
755 ARRAY_SIZE(g_all_64bit_stats_string) +
756 hclge_tqps_get_sset_count(handle, stringset);
757 }
758
759 return count;
760}
761
762static void hclge_get_strings(struct hnae3_handle *handle,
763 u32 stringset,
764 u8 *data)
765{
766 u8 *p = (char *)data;
767 int size;
768
769 if (stringset == ETH_SS_STATS) {
770 size = ARRAY_SIZE(g_mac_stats_string);
771 p = hclge_comm_get_strings(stringset,
772 g_mac_stats_string,
773 size,
774 p);
775 size = ARRAY_SIZE(g_all_32bit_stats_string);
776 p = hclge_comm_get_strings(stringset,
777 g_all_32bit_stats_string,
778 size,
779 p);
780 size = ARRAY_SIZE(g_all_64bit_stats_string);
781 p = hclge_comm_get_strings(stringset,
782 g_all_64bit_stats_string,
783 size,
784 p);
785 p = hclge_tqps_get_strings(handle, p);
786 } else if (stringset == ETH_SS_TEST) {
787 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
788 memcpy(p,
789 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
790 ETH_GSTRING_LEN);
791 p += ETH_GSTRING_LEN;
792 }
793 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
794 memcpy(p,
795 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
796 ETH_GSTRING_LEN);
797 p += ETH_GSTRING_LEN;
798 }
799 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
800 memcpy(p,
801 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
802 ETH_GSTRING_LEN);
803 p += ETH_GSTRING_LEN;
804 }
805 }
806}
807
808static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
809{
810 struct hclge_vport *vport = hclge_get_vport(handle);
811 struct hclge_dev *hdev = vport->back;
812 u64 *p;
813
814 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
815 g_mac_stats_string,
816 ARRAY_SIZE(g_mac_stats_string),
817 data);
818 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
819 g_all_32bit_stats_string,
820 ARRAY_SIZE(g_all_32bit_stats_string),
821 p);
822 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
823 g_all_64bit_stats_string,
824 ARRAY_SIZE(g_all_64bit_stats_string),
825 p);
826 p = hclge_tqps_get_stats(handle, p);
827}
828
829static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 830 struct hclge_func_status_cmd *status)
46a3df9f
S		 831{
832 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
833 return -EINVAL;
834
835 /* Set the pf to main pf */
836 if (status->pf_state & HCLGE_PF_STATE_MAIN)
837 hdev->flag |= HCLGE_FLAG_MAIN;
838 else
839 hdev->flag &= ~HCLGE_FLAG_MAIN;
840
46a3df9f
S		 841 return 0;
842}
843
844static int hclge_query_function_status(struct hclge_dev *hdev)
845{
d44f9b63 846 struct hclge_func_status_cmd *req;
46a3df9f
S		 847 struct hclge_desc desc;
848 int timeout = 0;
849 int ret;
850
851 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 852 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 853
854 do {
855 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
856 if (ret) {
857 dev_err(&hdev->pdev->dev,
858 "query function status failed %d.\n",
859 ret);
860
861 return ret;
862 }
863
864 /* Check pf reset is done */
865 if (req->pf_state)
866 break;
867 usleep_range(1000, 2000);
868 } while (timeout++ < 5);
869
870 ret = hclge_parse_func_status(hdev, req);
871
872 return ret;
873}
874
875static int hclge_query_pf_resource(struct hclge_dev *hdev)
876{
d44f9b63 877 struct hclge_pf_res_cmd *req;
46a3df9f
S		 878 struct hclge_desc desc;
879 int ret;
880
881 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
882 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
883 if (ret) {
884 dev_err(&hdev->pdev->dev,
885 "query pf resource failed %d.\n", ret);
886 return ret;
887 }
888
d44f9b63 889 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 890 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
891 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
892
e92a0843 893 if (hnae3_dev_roce_supported(hdev)) {
887c3820 894 hdev->num_roce_msi =
46a3df9f
S		 895 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
896 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
897
898 /* PF should have NIC vectors and Roce vectors,
899 * NIC vectors are queued before Roce vectors.
900 */
887c3820 901 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 902 } else {
903 hdev->num_msi =
904 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
905 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
906 }
907
908 return 0;
909}
910
911static int hclge_parse_speed(int speed_cmd, int *speed)
912{
913 switch (speed_cmd) {
914 case 6:
915 *speed = HCLGE_MAC_SPEED_10M;
916 break;
917 case 7:
918 *speed = HCLGE_MAC_SPEED_100M;
919 break;
920 case 0:
921 *speed = HCLGE_MAC_SPEED_1G;
922 break;
923 case 1:
924 *speed = HCLGE_MAC_SPEED_10G;
925 break;
926 case 2:
927 *speed = HCLGE_MAC_SPEED_25G;
928 break;
929 case 3:
930 *speed = HCLGE_MAC_SPEED_40G;
931 break;
932 case 4:
933 *speed = HCLGE_MAC_SPEED_50G;
934 break;
935 case 5:
936 *speed = HCLGE_MAC_SPEED_100G;
937 break;
938 default:
939 return -EINVAL;
940 }
941
942 return 0;
943}
944
945static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
946{
d44f9b63 947 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 948 u64 mac_addr_tmp_high;
949 u64 mac_addr_tmp;
950 int i;
951
d44f9b63 952 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 953
954 /* get the configuration */
955 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
956 HCLGE_CFG_VMDQ_M,
957 HCLGE_CFG_VMDQ_S);
958 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
959 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
960 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
961 HCLGE_CFG_TQP_DESC_N_M,
962 HCLGE_CFG_TQP_DESC_N_S);
963
964 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
965 HCLGE_CFG_PHY_ADDR_M,
966 HCLGE_CFG_PHY_ADDR_S);
967 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
968 HCLGE_CFG_MEDIA_TP_M,
969 HCLGE_CFG_MEDIA_TP_S);
970 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
971 HCLGE_CFG_RX_BUF_LEN_M,
972 HCLGE_CFG_RX_BUF_LEN_S);
973 /* get mac_address */
974 mac_addr_tmp = __le32_to_cpu(req->param[2]);
975 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
976 HCLGE_CFG_MAC_ADDR_H_M,
977 HCLGE_CFG_MAC_ADDR_H_S);
978
979 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
980
981 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
982 HCLGE_CFG_DEFAULT_SPEED_M,
983 HCLGE_CFG_DEFAULT_SPEED_S);
984 for (i = 0; i < ETH_ALEN; i++)
985 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
986
d44f9b63 987 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f
S		 988 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
989}
990
991/* hclge_get_cfg: query the static parameter from flash
992 * @hdev: pointer to struct hclge_dev
993 * @hcfg: the config structure to be getted
994 */
995static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
996{
997 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 998 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 999 int i, ret;
1000
1001 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1002 u32 offset = 0;
1003
d44f9b63 1004 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1005 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1006 true);
a90bb9a5 1007 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1008 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1009 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1010 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1011 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1012 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1013 }
1014
1015 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1016 if (ret) {
1017 dev_err(&hdev->pdev->dev,
1018 "get config failed %d.\n", ret);
1019 return ret;
1020 }
1021
1022 hclge_parse_cfg(hcfg, desc);
1023 return 0;
1024}
1025
1026static int hclge_get_cap(struct hclge_dev *hdev)
1027{
1028 int ret;
1029
1030 ret = hclge_query_function_status(hdev);
1031 if (ret) {
1032 dev_err(&hdev->pdev->dev,
1033 "query function status error %d.\n", ret);
1034 return ret;
1035 }
1036
1037 /* get pf resource */
1038 ret = hclge_query_pf_resource(hdev);
1039 if (ret) {
1040 dev_err(&hdev->pdev->dev,
1041 "query pf resource error %d.\n", ret);
1042 return ret;
1043 }
1044
1045 return 0;
1046}
1047
1048static int hclge_configure(struct hclge_dev *hdev)
1049{
1050 struct hclge_cfg cfg;
1051 int ret, i;
1052
1053 ret = hclge_get_cfg(hdev, &cfg);
1054 if (ret) {
1055 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1056 return ret;
1057 }
1058
1059 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1060 hdev->base_tqp_pid = 0;
1061 hdev->rss_size_max = 1;
1062 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1063 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1064 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1065 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1066 hdev->num_desc = cfg.tqp_desc_num;
1067 hdev->tm_info.num_pg = 1;
cacde272 1068 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1069 hdev->tm_info.hw_pfc_map = 0;
1070
1071 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1072 if (ret) {
1073 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1074 return ret;
1075 }
1076
cacde272
YL		 1077 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1078 (hdev->tc_max < 1)) {
46a3df9f 1079 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1080 hdev->tc_max);
1081 hdev->tc_max = 1;
46a3df9f
S		 1082 }
1083
cacde272
YL		 1084 /* Dev does not support DCB */
1085 if (!hnae3_dev_dcb_supported(hdev)) {
1086 hdev->tc_max = 1;
1087 hdev->pfc_max = 0;
1088 } else {
1089 hdev->pfc_max = hdev->tc_max;
1090 }
1091
1092 hdev->tm_info.num_tc = hdev->tc_max;
1093
46a3df9f 1094 /* Currently not support uncontiuous tc */
cacde272 1095 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1096 hnae_set_bit(hdev->hw_tc_map, i, 1);
1097
1098 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1099 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1100 else
1101 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1102
1103 return ret;
1104}
1105
1106static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1107 int tso_mss_max)
1108{
d44f9b63 1109 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1110 struct hclge_desc desc;
a90bb9a5 1111 u16 tso_mss;
46a3df9f
S		 1112
1113 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1114
d44f9b63 1115 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1116
1117 tso_mss = 0;
1118 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1119 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1120 req->tso_mss_min = cpu_to_le16(tso_mss);
1121
1122 tso_mss = 0;
1123 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1124 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1125 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1126
1127 return hclge_cmd_send(&hdev->hw, &desc, 1);
1128}
1129
1130static int hclge_alloc_tqps(struct hclge_dev *hdev)
1131{
1132 struct hclge_tqp *tqp;
1133 int i;
1134
1135 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1136 sizeof(struct hclge_tqp), GFP_KERNEL);
1137 if (!hdev->htqp)
1138 return -ENOMEM;
1139
1140 tqp = hdev->htqp;
1141
1142 for (i = 0; i < hdev->num_tqps; i++) {
1143 tqp->dev = &hdev->pdev->dev;
1144 tqp->index = i;
1145
1146 tqp->q.ae_algo = &ae_algo;
1147 tqp->q.buf_size = hdev->rx_buf_len;
1148 tqp->q.desc_num = hdev->num_desc;
1149 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1150 i * HCLGE_TQP_REG_SIZE;
1151
1152 tqp++;
1153 }
1154
1155 return 0;
1156}
1157
1158static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1159 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1160{
d44f9b63 1161 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1162 struct hclge_desc desc;
1163 int ret;
1164
1165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1166
d44f9b63 1167 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1168 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1169 req->tqp_vf = func_id;
46a3df9f
S		 1170 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1171 1 << HCLGE_TQP_MAP_EN_B;
1172 req->tqp_vid = cpu_to_le16(tqp_vid);
1173
1174 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1175 if (ret) {
1176 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1177 ret);
1178 return ret;
1179 }
1180
1181 return 0;
1182}
1183
1184static int hclge_assign_tqp(struct hclge_vport *vport,
1185 struct hnae3_queue **tqp, u16 num_tqps)
1186{
1187 struct hclge_dev *hdev = vport->back;
7df7dad6 1188 int i, alloced;
46a3df9f
S		 1189
1190 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1191 alloced < num_tqps; i++) {
1192 if (!hdev->htqp[i].alloced) {
1193 hdev->htqp[i].q.handle = &vport->nic;
1194 hdev->htqp[i].q.tqp_index = alloced;
1195 tqp[alloced] = &hdev->htqp[i].q;
1196 hdev->htqp[i].alloced = true;
46a3df9f
S		 1197 alloced++;
1198 }
1199 }
1200 vport->alloc_tqps = num_tqps;
1201
1202 return 0;
1203}
1204
1205static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1206{
1207 struct hnae3_handle *nic = &vport->nic;
1208 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1209 struct hclge_dev *hdev = vport->back;
1210 int i, ret;
1211
1212 kinfo->num_desc = hdev->num_desc;
1213 kinfo->rx_buf_len = hdev->rx_buf_len;
1214 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1215 kinfo->rss_size
1216 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1217 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1218
1219 for (i = 0; i < HNAE3_MAX_TC; i++) {
1220 if (hdev->hw_tc_map & BIT(i)) {
1221 kinfo->tc_info[i].enable = true;
1222 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1223 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1224 kinfo->tc_info[i].tc = i;
1225 } else {
1226 /* Set to default queue if TC is disable */
1227 kinfo->tc_info[i].enable = false;
1228 kinfo->tc_info[i].tqp_offset = 0;
1229 kinfo->tc_info[i].tqp_count = 1;
1230 kinfo->tc_info[i].tc = 0;
1231 }
1232 }
1233
1234 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1235 sizeof(struct hnae3_queue *), GFP_KERNEL);
1236 if (!kinfo->tqp)
1237 return -ENOMEM;
1238
1239 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1240 if (ret) {
1241 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1242 return -EINVAL;
1243 }
1244
1245 return 0;
1246}
1247
7df7dad6
L		 1248static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1249 struct hclge_vport *vport)
1250{
1251 struct hnae3_handle *nic = &vport->nic;
1252 struct hnae3_knic_private_info *kinfo;
1253 u16 i;
1254
1255 kinfo = &nic->kinfo;
1256 for (i = 0; i < kinfo->num_tqps; i++) {
1257 struct hclge_tqp *q =
1258 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1259 bool is_pf;
1260 int ret;
1261
1262 is_pf = !(vport->vport_id);
1263 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1264 i, is_pf);
1265 if (ret)
1266 return ret;
1267 }
1268
1269 return 0;
1270}
1271
1272static int hclge_map_tqp(struct hclge_dev *hdev)
1273{
1274 struct hclge_vport *vport = hdev->vport;
1275 u16 i, num_vport;
1276
1277 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1278 for (i = 0; i < num_vport; i++) {
1279 int ret;
1280
1281 ret = hclge_map_tqp_to_vport(hdev, vport);
1282 if (ret)
1283 return ret;
1284
1285 vport++;
1286 }
1287
1288 return 0;
1289}
1290
46a3df9f
S		 1291static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1292{
1293 /* this would be initialized later */
1294}
1295
1296static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1297{
1298 struct hnae3_handle *nic = &vport->nic;
1299 struct hclge_dev *hdev = vport->back;
1300 int ret;
1301
1302 nic->pdev = hdev->pdev;
1303 nic->ae_algo = &ae_algo;
1304 nic->numa_node_mask = hdev->numa_node_mask;
1305
1306 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1307 ret = hclge_knic_setup(vport, num_tqps);
1308 if (ret) {
1309 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1310 ret);
1311 return ret;
1312 }
1313 } else {
1314 hclge_unic_setup(vport, num_tqps);
1315 }
1316
1317 return 0;
1318}
1319
1320static int hclge_alloc_vport(struct hclge_dev *hdev)
1321{
1322 struct pci_dev *pdev = hdev->pdev;
1323 struct hclge_vport *vport;
1324 u32 tqp_main_vport;
1325 u32 tqp_per_vport;
1326 int num_vport, i;
1327 int ret;
1328
1329 /* We need to alloc a vport for main NIC of PF */
1330 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1331
1332 if (hdev->num_tqps < num_vport)
1333 num_vport = hdev->num_tqps;
1334
1335 /* Alloc the same number of TQPs for every vport */
1336 tqp_per_vport = hdev->num_tqps / num_vport;
1337 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1338
1339 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1340 GFP_KERNEL);
1341 if (!vport)
1342 return -ENOMEM;
1343
1344 hdev->vport = vport;
1345 hdev->num_alloc_vport = num_vport;
1346
1347#ifdef CONFIG_PCI_IOV
1348 /* Enable SRIOV */
1349 if (hdev->num_req_vfs) {
1350 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1351 hdev->num_req_vfs);
1352 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1353 if (ret) {
1354 hdev->num_alloc_vfs = 0;
1355 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1356 ret);
1357 return ret;
1358 }
1359 }
1360 hdev->num_alloc_vfs = hdev->num_req_vfs;
1361#endif
1362
1363 for (i = 0; i < num_vport; i++) {
1364 vport->back = hdev;
1365 vport->vport_id = i;
1366
1367 if (i == 0)
1368 ret = hclge_vport_setup(vport, tqp_main_vport);
1369 else
1370 ret = hclge_vport_setup(vport, tqp_per_vport);
1371 if (ret) {
1372 dev_err(&pdev->dev,
1373 "vport setup failed for vport %d, %d\n",
1374 i, ret);
1375 return ret;
1376 }
1377
1378 vport++;
1379 }
1380
1381 return 0;
1382}
1383
acf61ecd
YL		 1384static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1385 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1386{
1387/* TX buffer size is unit by 128 byte */
1388#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1389#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1390 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1391 struct hclge_desc desc;
1392 int ret;
1393 u8 i;
1394
d44f9b63 1395 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1396
1397 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1398 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1399 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1400
46a3df9f
S		 1401 req->tx_pkt_buff[i] =
1402 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1403 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1404 }
46a3df9f
S		 1405
1406 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1407 if (ret) {
1408 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1409 ret);
1410 return ret;
1411 }
1412
1413 return 0;
1414}
1415
acf61ecd
YL		 1416static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1417 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1418{
acf61ecd 1419 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1420
1421 if (ret) {
1422 dev_err(&hdev->pdev->dev,
1423 "tx buffer alloc failed %d\n", ret);
1424 return ret;
1425 }
1426
1427 return 0;
1428}
1429
1430static int hclge_get_tc_num(struct hclge_dev *hdev)
1431{
1432 int i, cnt = 0;
1433
1434 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1435 if (hdev->hw_tc_map & BIT(i))
1436 cnt++;
1437 return cnt;
1438}
1439
1440static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1441{
1442 int i, cnt = 0;
1443
1444 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1445 if (hdev->hw_tc_map & BIT(i) &&
1446 hdev->tm_info.hw_pfc_map & BIT(i))
1447 cnt++;
1448 return cnt;
1449}
1450
1451/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1452static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1453 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1454{
1455 struct hclge_priv_buf *priv;
1456 int i, cnt = 0;
1457
1458 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1459 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1460 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1461 priv->enable)
1462 cnt++;
1463 }
1464
1465 return cnt;
1466}
1467
1468/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1469static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1470 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1471{
1472 struct hclge_priv_buf *priv;
1473 int i, cnt = 0;
1474
1475 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1476 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1477 if (hdev->hw_tc_map & BIT(i) &&
1478 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1479 priv->enable)
1480 cnt++;
1481 }
1482
1483 return cnt;
1484}
1485
acf61ecd 1486static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1487{
1488 struct hclge_priv_buf *priv;
1489 u32 rx_priv = 0;
1490 int i;
1491
1492 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1493 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1494 if (priv->enable)
1495 rx_priv += priv->buf_size;
1496 }
1497 return rx_priv;
1498}
1499
acf61ecd 1500static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1501{
1502 u32 i, total_tx_size = 0;
1503
1504 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1505 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1506
1507 return total_tx_size;
1508}
1509
acf61ecd
YL		 1510static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1511 struct hclge_pkt_buf_alloc *buf_alloc,
1512 u32 rx_all)
46a3df9f
S		 1513{
1514 u32 shared_buf_min, shared_buf_tc, shared_std;
1515 int tc_num, pfc_enable_num;
1516 u32 shared_buf;
1517 u32 rx_priv;
1518 int i;
1519
1520 tc_num = hclge_get_tc_num(hdev);
1521 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1522
d221df4e
YL		 1523 if (hnae3_dev_dcb_supported(hdev))
1524 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1525 else
1526 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1527
46a3df9f
S		 1528 shared_buf_tc = pfc_enable_num * hdev->mps +
1529 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1530 hdev->mps;
1531 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1532
acf61ecd 1533 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1534 if (rx_all <= rx_priv + shared_std)
1535 return false;
1536
1537 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1538 buf_alloc->s_buf.buf_size = shared_buf;
1539 buf_alloc->s_buf.self.high = shared_buf;
1540 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1541
1542 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1543 if ((hdev->hw_tc_map & BIT(i)) &&
1544 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1545 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1546 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1547 } else {
acf61ecd
YL		 1548 buf_alloc->s_buf.tc_thrd[i].low = 0;
1549 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1550 }
1551 }
1552
1553 return true;
1554}
1555
acf61ecd
YL		 1556static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1557 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1558{
1559 u32 i, total_size;
1560
1561 total_size = hdev->pkt_buf_size;
1562
1563 /* alloc tx buffer for all enabled tc */
1564 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1565 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1566
1567 if (total_size < HCLGE_DEFAULT_TX_BUF)
1568 return -ENOMEM;
1569
1570 if (hdev->hw_tc_map & BIT(i))
1571 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1572 else
1573 priv->tx_buf_size = 0;
1574
1575 total_size -= priv->tx_buf_size;
1576 }
1577
1578 return 0;
1579}
1580
46a3df9f
S		 1581/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1582 * @hdev: pointer to struct hclge_dev
acf61ecd 1583 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1584 * @return: 0: calculate sucessful, negative: fail
1585 */
1db9b1bf
YL		 1586static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1587 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1588{
9ffe79a9 1589 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1590 int no_pfc_priv_num, pfc_priv_num;
1591 struct hclge_priv_buf *priv;
1592 int i;
1593
acf61ecd 1594 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1595
d602a525
YL		 1596 /* When DCB is not supported, rx private
1597 * buffer is not allocated.
1598 */
1599 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1600 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1601 return -ENOMEM;
1602
1603 return 0;
1604 }
1605
46a3df9f
S		 1606 /* step 1, try to alloc private buffer for all enabled tc */
1607 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1608 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1609 if (hdev->hw_tc_map & BIT(i)) {
1610 priv->enable = 1;
1611 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1612 priv->wl.low = hdev->mps;
1613 priv->wl.high = priv->wl.low + hdev->mps;
1614 priv->buf_size = priv->wl.high +
1615 HCLGE_DEFAULT_DV;
1616 } else {
1617 priv->wl.low = 0;
1618 priv->wl.high = 2 * hdev->mps;
1619 priv->buf_size = priv->wl.high;
1620 }
bb1fe9ea
YL		 1621 } else {
1622 priv->enable = 0;
1623 priv->wl.low = 0;
1624 priv->wl.high = 0;
1625 priv->buf_size = 0;
46a3df9f
S		 1626 }
1627 }
1628
acf61ecd 1629 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1630 return 0;
1631
1632 /* step 2, try to decrease the buffer size of
1633 * no pfc TC's private buffer
1634 */
1635 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1636 priv = &buf_alloc->priv_buf[i];
46a3df9f 1637
bb1fe9ea
YL		 1638 priv->enable = 0;
1639 priv->wl.low = 0;
1640 priv->wl.high = 0;
1641 priv->buf_size = 0;
1642
1643 if (!(hdev->hw_tc_map & BIT(i)))
1644 continue;
1645
1646 priv->enable = 1;
46a3df9f
S		 1647
1648 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1649 priv->wl.low = 128;
1650 priv->wl.high = priv->wl.low + hdev->mps;
1651 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1652 } else {
1653 priv->wl.low = 0;
1654 priv->wl.high = hdev->mps;
1655 priv->buf_size = priv->wl.high;
1656 }
1657 }
1658
acf61ecd 1659 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1660 return 0;
1661
1662 /* step 3, try to reduce the number of pfc disabled TCs,
1663 * which have private buffer
1664 */
1665 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1666 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1667
1668 /* let the last to be cleared first */
1669 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1670 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1671
1672 if (hdev->hw_tc_map & BIT(i) &&
1673 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1674 /* Clear the no pfc TC private buffer */
1675 priv->wl.low = 0;
1676 priv->wl.high = 0;
1677 priv->buf_size = 0;
1678 priv->enable = 0;
1679 no_pfc_priv_num--;
1680 }
1681
acf61ecd 1682 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1683 no_pfc_priv_num == 0)
1684 break;
1685 }
1686
acf61ecd 1687 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1688 return 0;
1689
1690 /* step 4, try to reduce the number of pfc enabled TCs
1691 * which have private buffer.
1692 */
acf61ecd 1693 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1694
1695 /* let the last to be cleared first */
1696 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1697 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1698
1699 if (hdev->hw_tc_map & BIT(i) &&
1700 hdev->tm_info.hw_pfc_map & BIT(i)) {
1701 /* Reduce the number of pfc TC with private buffer */
1702 priv->wl.low = 0;
1703 priv->enable = 0;
1704 priv->wl.high = 0;
1705 priv->buf_size = 0;
1706 pfc_priv_num--;
1707 }
1708
acf61ecd 1709 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1710 pfc_priv_num == 0)
1711 break;
1712 }
acf61ecd 1713 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1714 return 0;
1715
1716 return -ENOMEM;
1717}
1718
acf61ecd
YL		 1719static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1720 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1721{
d44f9b63 1722 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1723 struct hclge_desc desc;
1724 int ret;
1725 int i;
1726
1727 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1728 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1729
1730 /* Alloc private buffer TCs */
1731 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1732 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1733
1734 req->buf_num[i] =
1735 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1736 req->buf_num[i] |=
5bca3b94 1737 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1738 }
1739
b8c8bf47 1740 req->shared_buf =
acf61ecd 1741 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1742 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1743
46a3df9f
S		 1744 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1745 if (ret) {
1746 dev_err(&hdev->pdev->dev,
1747 "rx private buffer alloc cmd failed %d\n", ret);
1748 return ret;
1749 }
1750
1751 return 0;
1752}
1753
1754#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1755
acf61ecd
YL		 1756static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1757 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1758{
1759 struct hclge_rx_priv_wl_buf *req;
1760 struct hclge_priv_buf *priv;
1761 struct hclge_desc desc[2];
1762 int i, j;
1763 int ret;
1764
1765 for (i = 0; i < 2; i++) {
1766 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1767 false);
1768 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1769
1770 /* The first descriptor set the NEXT bit to 1 */
1771 if (i == 0)
1772 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1773 else
1774 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1775
1776 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1777 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1778
1779 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1780 req->tc_wl[j].high =
1781 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1782 req->tc_wl[j].high |=
1783 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1784 HCLGE_RX_PRIV_EN_B);
1785 req->tc_wl[j].low =
1786 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1787 req->tc_wl[j].low |=
1788 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1789 HCLGE_RX_PRIV_EN_B);
1790 }
1791 }
1792
1793 /* Send 2 descriptor at one time */
1794 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1795 if (ret) {
1796 dev_err(&hdev->pdev->dev,
1797 "rx private waterline config cmd failed %d\n",
1798 ret);
1799 return ret;
1800 }
1801 return 0;
1802}
1803
acf61ecd
YL		 1804static int hclge_common_thrd_config(struct hclge_dev *hdev,
1805 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1806{
acf61ecd 1807 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1808 struct hclge_rx_com_thrd *req;
1809 struct hclge_desc desc[2];
1810 struct hclge_tc_thrd *tc;
1811 int i, j;
1812 int ret;
1813
1814 for (i = 0; i < 2; i++) {
1815 hclge_cmd_setup_basic_desc(&desc[i],
1816 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1817 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1818
1819 /* The first descriptor set the NEXT bit to 1 */
1820 if (i == 0)
1821 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1822 else
1823 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1824
1825 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1826 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1827
1828 req->com_thrd[j].high =
1829 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1830 req->com_thrd[j].high |=
1831 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1832 HCLGE_RX_PRIV_EN_B);
1833 req->com_thrd[j].low =
1834 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1835 req->com_thrd[j].low |=
1836 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1837 HCLGE_RX_PRIV_EN_B);
1838 }
1839 }
1840
1841 /* Send 2 descriptors at one time */
1842 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1843 if (ret) {
1844 dev_err(&hdev->pdev->dev,
1845 "common threshold config cmd failed %d\n", ret);
1846 return ret;
1847 }
1848 return 0;
1849}
1850
acf61ecd
YL		 1851static int hclge_common_wl_config(struct hclge_dev *hdev,
1852 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1853{
acf61ecd 1854 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1855 struct hclge_rx_com_wl *req;
1856 struct hclge_desc desc;
1857 int ret;
1858
1859 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1860
1861 req = (struct hclge_rx_com_wl *)desc.data;
1862 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1863 req->com_wl.high |=
1864 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1865 HCLGE_RX_PRIV_EN_B);
1866
1867 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1868 req->com_wl.low |=
1869 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1870 HCLGE_RX_PRIV_EN_B);
1871
1872 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1873 if (ret) {
1874 dev_err(&hdev->pdev->dev,
1875 "common waterline config cmd failed %d\n", ret);
1876 return ret;
1877 }
1878
1879 return 0;
1880}
1881
1882int hclge_buffer_alloc(struct hclge_dev *hdev)
1883{
acf61ecd 1884 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1885 int ret;
1886
acf61ecd
YL		 1887 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1888 if (!pkt_buf)
46a3df9f
S		 1889 return -ENOMEM;
1890
acf61ecd 1891 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1892 if (ret) {
1893 dev_err(&hdev->pdev->dev,
1894 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1895 goto out;
9ffe79a9
YL		 1896 }
1897
acf61ecd 1898 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1899 if (ret) {
1900 dev_err(&hdev->pdev->dev,
1901 "could not alloc tx buffers %d\n", ret);
acf61ecd 1902 goto out;
46a3df9f
S		 1903 }
1904
acf61ecd 1905 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1906 if (ret) {
1907 dev_err(&hdev->pdev->dev,
1908 "could not calc rx priv buffer size for all TCs %d\n",
1909 ret);
acf61ecd 1910 goto out;
46a3df9f
S		 1911 }
1912
acf61ecd 1913 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1914 if (ret) {
1915 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1916 ret);
acf61ecd 1917 goto out;
46a3df9f
S		 1918 }
1919
2daf4a65 1920 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1921 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1922 if (ret) {
1923 dev_err(&hdev->pdev->dev,
1924 "could not configure rx private waterline %d\n",
1925 ret);
acf61ecd 1926 goto out;
2daf4a65 1927 }
46a3df9f 1928
acf61ecd 1929 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1930 if (ret) {
1931 dev_err(&hdev->pdev->dev,
1932 "could not configure common threshold %d\n",
1933 ret);
acf61ecd 1934 goto out;
2daf4a65 1935 }
46a3df9f
S		 1936 }
1937
acf61ecd
YL		 1938 ret = hclge_common_wl_config(hdev, pkt_buf);
1939 if (ret)
46a3df9f
S		 1940 dev_err(&hdev->pdev->dev,
1941 "could not configure common waterline %d\n", ret);
46a3df9f 1942
acf61ecd
YL		 1943out:
1944 kfree(pkt_buf);
1945 return ret;
46a3df9f
S		 1946}
1947
1948static int hclge_init_roce_base_info(struct hclge_vport *vport)
1949{
1950 struct hnae3_handle *roce = &vport->roce;
1951 struct hnae3_handle *nic = &vport->nic;
1952
887c3820 1953 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1954
1955 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1956 vport->back->num_msi_left == 0)
1957 return -EINVAL;
1958
1959 roce->rinfo.base_vector = vport->back->roce_base_vector;
1960
1961 roce->rinfo.netdev = nic->kinfo.netdev;
1962 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1963
1964 roce->pdev = nic->pdev;
1965 roce->ae_algo = nic->ae_algo;
1966 roce->numa_node_mask = nic->numa_node_mask;
1967
1968 return 0;
1969}
1970
887c3820 1971static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1972{
1973 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1974 int vectors;
1975 int i;
46a3df9f 1976
887c3820
SM		 1977 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1978 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1979 if (vectors < 0) {
1980 dev_err(&pdev->dev,
1981 "failed(%d) to allocate MSI/MSI-X vectors\n",
1982 vectors);
1983 return vectors;
46a3df9f 1984 }
887c3820
SM		 1985 if (vectors < hdev->num_msi)
1986 dev_warn(&hdev->pdev->dev,
1987 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1988 hdev->num_msi, vectors);
46a3df9f 1989
887c3820
SM		 1990 hdev->num_msi = vectors;
1991 hdev->num_msi_left = vectors;
1992 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 1993 hdev->roce_base_vector = hdev->base_msi_vector +
1994 HCLGE_ROCE_VECTOR_OFFSET;
1995
46a3df9f
S		 1996 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1997 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1998 if (!hdev->vector_status) {
1999 pci_free_irq_vectors(pdev);
46a3df9f 2000 return -ENOMEM;
887c3820 2001 }
46a3df9f
S		 2002
2003 for (i = 0; i < hdev->num_msi; i++)
2004 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2005
887c3820
SM		 2006 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2007 sizeof(int), GFP_KERNEL);
2008 if (!hdev->vector_irq) {
2009 pci_free_irq_vectors(pdev);
2010 return -ENOMEM;
46a3df9f 2011 }
46a3df9f
S		 2012
2013 return 0;
2014}
2015
2016static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2017{
2018 struct hclge_mac *mac = &hdev->hw.mac;
2019
2020 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2021 mac->duplex = (u8)duplex;
2022 else
2023 mac->duplex = HCLGE_MAC_FULL;
2024
2025 mac->speed = speed;
2026}
2027
2028int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2029{
d44f9b63 2030 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2031 struct hclge_desc desc;
2032 int ret;
2033
d44f9b63 2034 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2035
2036 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2037
2038 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2039
2040 switch (speed) {
2041 case HCLGE_MAC_SPEED_10M:
2042 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2043 HCLGE_CFG_SPEED_S, 6);
2044 break;
2045 case HCLGE_MAC_SPEED_100M:
2046 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2047 HCLGE_CFG_SPEED_S, 7);
2048 break;
2049 case HCLGE_MAC_SPEED_1G:
2050 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2051 HCLGE_CFG_SPEED_S, 0);
2052 break;
2053 case HCLGE_MAC_SPEED_10G:
2054 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2055 HCLGE_CFG_SPEED_S, 1);
2056 break;
2057 case HCLGE_MAC_SPEED_25G:
2058 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2059 HCLGE_CFG_SPEED_S, 2);
2060 break;
2061 case HCLGE_MAC_SPEED_40G:
2062 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2063 HCLGE_CFG_SPEED_S, 3);
2064 break;
2065 case HCLGE_MAC_SPEED_50G:
2066 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2067 HCLGE_CFG_SPEED_S, 4);
2068 break;
2069 case HCLGE_MAC_SPEED_100G:
2070 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2071 HCLGE_CFG_SPEED_S, 5);
2072 break;
2073 default:
d7629e74 2074 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2075 return -EINVAL;
2076 }
2077
2078 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2079 1);
2080
2081 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2082 if (ret) {
2083 dev_err(&hdev->pdev->dev,
2084 "mac speed/duplex config cmd failed %d.\n", ret);
2085 return ret;
2086 }
2087
2088 hclge_check_speed_dup(hdev, duplex, speed);
2089
2090 return 0;
2091}
2092
2093static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2094 u8 duplex)
2095{
2096 struct hclge_vport *vport = hclge_get_vport(handle);
2097 struct hclge_dev *hdev = vport->back;
2098
2099 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2100}
2101
2102static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2103 u8 *duplex)
2104{
d44f9b63 2105 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2106 struct hclge_desc desc;
2107 int speed_tmp;
2108 int ret;
2109
d44f9b63 2110 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2111
2112 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2113 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2114 if (ret) {
2115 dev_err(&hdev->pdev->dev,
2116 "mac speed/autoneg/duplex query cmd failed %d\n",
2117 ret);
2118 return ret;
2119 }
2120
2121 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2122 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2123 HCLGE_QUERY_SPEED_S);
2124
2125 ret = hclge_parse_speed(speed_tmp, speed);
2126 if (ret) {
2127 dev_err(&hdev->pdev->dev,
2128 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2129 return -EIO;
2130 }
2131
2132 return 0;
2133}
2134
2135static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2136{
2137 struct hclge_mac *mac = &hdev->hw.mac;
d44f9b63 2138 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2139 struct hclge_desc desc;
2140 int ret;
2141
d44f9b63 2142 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2143
2144 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2145 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2146 if (ret) {
2147 dev_err(&hdev->pdev->dev,
2148 "autoneg result query cmd failed %d.\n", ret);
2149 return ret;
2150 }
2151
2152 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2153
2154 return 0;
2155}
2156
2157static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2158{
d44f9b63 2159 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2160 struct hclge_desc desc;
a90bb9a5 2161 u32 flag = 0;
46a3df9f
S		 2162 int ret;
2163
2164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2165
d44f9b63 2166 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2167 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2168 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2169
2170 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2171 if (ret) {
2172 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2173 ret);
2174 return ret;
2175 }
2176
2177 return 0;
2178}
2179
2180static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2181{
2182 struct hclge_vport *vport = hclge_get_vport(handle);
2183 struct hclge_dev *hdev = vport->back;
2184
2185 return hclge_set_autoneg_en(hdev, enable);
2186}
2187
2188static int hclge_get_autoneg(struct hnae3_handle *handle)
2189{
2190 struct hclge_vport *vport = hclge_get_vport(handle);
2191 struct hclge_dev *hdev = vport->back;
2192
2193 hclge_query_autoneg_result(hdev);
2194
2195 return hdev->hw.mac.autoneg;
2196}
2197
2198static int hclge_mac_init(struct hclge_dev *hdev)
2199{
2200 struct hclge_mac *mac = &hdev->hw.mac;
2201 int ret;
2202
2203 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2204 if (ret) {
2205 dev_err(&hdev->pdev->dev,
2206 "Config mac speed dup fail ret=%d\n", ret);
2207 return ret;
2208 }
2209
2210 mac->link = 0;
2211
46a3df9f
S		 2212 /* Initialize the MTA table work mode */
2213 hdev->accept_mta_mc = true;
2214 hdev->enable_mta = true;
2215 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2216
2217 ret = hclge_set_mta_filter_mode(hdev,
2218 hdev->mta_mac_sel_type,
2219 hdev->enable_mta);
2220 if (ret) {
2221 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2222 ret);
2223 return ret;
2224 }
2225
2226 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2227}
2228
cb1b9f77
SM		 2229static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2230{
2231 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2232 schedule_work(&hdev->rst_service_task);
2233}
2234
46a3df9f
S		 2235static void hclge_task_schedule(struct hclge_dev *hdev)
2236{
2237 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2238 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2239 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2240 (void)schedule_work(&hdev->service_task);
2241}
2242
2243static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2244{
d44f9b63 2245 struct hclge_link_status_cmd *req;
46a3df9f
S		 2246 struct hclge_desc desc;
2247 int link_status;
2248 int ret;
2249
2250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2251 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2252 if (ret) {
2253 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2254 ret);
2255 return ret;
2256 }
2257
d44f9b63 2258 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2259 link_status = req->status & HCLGE_LINK_STATUS;
2260
2261 return !!link_status;
2262}
2263
2264static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2265{
2266 int mac_state;
2267 int link_stat;
2268
2269 mac_state = hclge_get_mac_link_status(hdev);
2270
2271 if (hdev->hw.mac.phydev) {
2272 if (!genphy_read_status(hdev->hw.mac.phydev))
2273 link_stat = mac_state &
2274 hdev->hw.mac.phydev->link;
2275 else
2276 link_stat = 0;
2277
2278 } else {
2279 link_stat = mac_state;
2280 }
2281
2282 return !!link_stat;
2283}
2284
2285static void hclge_update_link_status(struct hclge_dev *hdev)
2286{
2287 struct hnae3_client *client = hdev->nic_client;
2288 struct hnae3_handle *handle;
2289 int state;
2290 int i;
2291
2292 if (!client)
2293 return;
2294 state = hclge_get_mac_phy_link(hdev);
2295 if (state != hdev->hw.mac.link) {
2296 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2297 handle = &hdev->vport[i].nic;
2298 client->ops->link_status_change(handle, state);
2299 }
2300 hdev->hw.mac.link = state;
2301 }
2302}
2303
2304static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2305{
2306 struct hclge_mac mac = hdev->hw.mac;
2307 u8 duplex;
2308 int speed;
2309 int ret;
2310
2311 /* get the speed and duplex as autoneg'result from mac cmd when phy
2312 * doesn't exit.
2313 */
c040366b 2314 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2315 return 0;
2316
2317 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2318 if (ret) {
2319 dev_err(&hdev->pdev->dev,
2320 "mac autoneg/speed/duplex query failed %d\n", ret);
2321 return ret;
2322 }
2323
2324 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2325 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2326 if (ret) {
2327 dev_err(&hdev->pdev->dev,
2328 "mac speed/duplex config failed %d\n", ret);
2329 return ret;
2330 }
2331 }
2332
2333 return 0;
2334}
2335
2336static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2337{
2338 struct hclge_vport *vport = hclge_get_vport(handle);
2339 struct hclge_dev *hdev = vport->back;
2340
2341 return hclge_update_speed_duplex(hdev);
2342}
2343
2344static int hclge_get_status(struct hnae3_handle *handle)
2345{
2346 struct hclge_vport *vport = hclge_get_vport(handle);
2347 struct hclge_dev *hdev = vport->back;
2348
2349 hclge_update_link_status(hdev);
2350
2351 return hdev->hw.mac.link;
2352}
2353
d039ef68 2354static void hclge_service_timer(struct timer_list *t)
46a3df9f 2355{
d039ef68 2356 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2357
d039ef68 2358 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 2359 hclge_task_schedule(hdev);
2360}
2361
2362static void hclge_service_complete(struct hclge_dev *hdev)
2363{
2364 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2365
2366 /* Flush memory before next watchdog */
2367 smp_mb__before_atomic();
2368 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2369}
2370
ca1d7669
SM		 2371static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2372{
2373 u32 rst_src_reg;
2374
2375 /* fetch the events from their corresponding regs */
2376 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2377
2378 /* check for vector0 reset event sources */
2379 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2380 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2381 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2382 return HCLGE_VECTOR0_EVENT_RST;
2383 }
2384
2385 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2386 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2387 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2388 return HCLGE_VECTOR0_EVENT_RST;
2389 }
2390
2391 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2392 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2393 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2394 return HCLGE_VECTOR0_EVENT_RST;
2395 }
2396
2397 /* mailbox event sharing vector 0 interrupt would be placed here */
2398
2399 return HCLGE_VECTOR0_EVENT_OTHER;
2400}
2401
2402static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2403 u32 regclr)
2404{
2405 if (event_type == HCLGE_VECTOR0_EVENT_RST)
2406 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2407
2408 /* mailbox event sharing vector 0 interrupt would be placed here */
2409}
2410
466b0c00
L		 2411static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2412{
2413 writel(enable ? 1 : 0, vector->addr);
2414}
2415
2416static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2417{
2418 struct hclge_dev *hdev = data;
ca1d7669
SM		 2419 u32 event_cause;
2420 u32 clearval;
466b0c00
L		 2421
2422 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2423 event_cause = hclge_check_event_cause(hdev, &clearval);
2424
2425 /* vector 0 interrupt is shared with reset and mailbox source events.
2426 * For now, we are not handling mailbox events.
2427 */
2428 switch (event_cause) {
2429 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2430 hclge_reset_task_schedule(hdev);
ca1d7669
SM		 2431 break;
2432 default:
2433 dev_dbg(&hdev->pdev->dev,
2434 "received unknown or unhandled event of vector0\n");
2435 break;
2436 }
2437
2438 /* we should clear the source of interrupt */
2439 hclge_clear_event_cause(hdev, event_cause, clearval);
2440 hclge_enable_vector(&hdev->misc_vector, true);
466b0c00
L		 2441
2442 return IRQ_HANDLED;
2443}
2444
2445static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2446{
2447 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2448 hdev->num_msi_left += 1;
2449 hdev->num_msi_used -= 1;
2450}
2451
2452static void hclge_get_misc_vector(struct hclge_dev *hdev)
2453{
2454 struct hclge_misc_vector *vector = &hdev->misc_vector;
2455
2456 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2457
2458 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2459 hdev->vector_status[0] = 0;
2460
2461 hdev->num_msi_left -= 1;
2462 hdev->num_msi_used += 1;
2463}
2464
2465static int hclge_misc_irq_init(struct hclge_dev *hdev)
2466{
2467 int ret;
2468
2469 hclge_get_misc_vector(hdev);
2470
ca1d7669
SM		 2471 /* this would be explicitly freed in the end */
2472 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2473 0, "hclge_misc", hdev);
466b0c00
L		 2474 if (ret) {
2475 hclge_free_vector(hdev, 0);
2476 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2477 hdev->misc_vector.vector_irq);
2478 }
2479
2480 return ret;
2481}
2482
ca1d7669
SM		 2483static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2484{
2485 free_irq(hdev->misc_vector.vector_irq, hdev);
2486 hclge_free_vector(hdev, 0);
2487}
2488
4ed340ab
L		 2489static int hclge_notify_client(struct hclge_dev *hdev,
2490 enum hnae3_reset_notify_type type)
2491{
2492 struct hnae3_client *client = hdev->nic_client;
2493 u16 i;
2494
2495 if (!client->ops->reset_notify)
2496 return -EOPNOTSUPP;
2497
2498 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2499 struct hnae3_handle *handle = &hdev->vport[i].nic;
2500 int ret;
2501
2502 ret = client->ops->reset_notify(handle, type);
2503 if (ret)
2504 return ret;
2505 }
2506
2507 return 0;
2508}
2509
2510static int hclge_reset_wait(struct hclge_dev *hdev)
2511{
2512#define HCLGE_RESET_WATI_MS 100
2513#define HCLGE_RESET_WAIT_CNT 5
2514 u32 val, reg, reg_bit;
2515 u32 cnt = 0;
2516
2517 switch (hdev->reset_type) {
2518 case HNAE3_GLOBAL_RESET:
2519 reg = HCLGE_GLOBAL_RESET_REG;
2520 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2521 break;
2522 case HNAE3_CORE_RESET:
2523 reg = HCLGE_GLOBAL_RESET_REG;
2524 reg_bit = HCLGE_CORE_RESET_BIT;
2525 break;
2526 case HNAE3_FUNC_RESET:
2527 reg = HCLGE_FUN_RST_ING;
2528 reg_bit = HCLGE_FUN_RST_ING_B;
2529 break;
2530 default:
2531 dev_err(&hdev->pdev->dev,
2532 "Wait for unsupported reset type: %d\n",
2533 hdev->reset_type);
2534 return -EINVAL;
2535 }
2536
2537 val = hclge_read_dev(&hdev->hw, reg);
2538 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2539 msleep(HCLGE_RESET_WATI_MS);
2540 val = hclge_read_dev(&hdev->hw, reg);
2541 cnt++;
2542 }
2543
4ed340ab
L		 2544 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2545 dev_warn(&hdev->pdev->dev,
2546 "Wait for reset timeout: %d\n", hdev->reset_type);
2547 return -EBUSY;
2548 }
2549
2550 return 0;
2551}
2552
2553static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2554{
2555 struct hclge_desc desc;
2556 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2557 int ret;
2558
2559 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2560 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2561 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2562 req->fun_reset_vfid = func_id;
2563
2564 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2565 if (ret)
2566 dev_err(&hdev->pdev->dev,
2567 "send function reset cmd fail, status =%d\n", ret);
2568
2569 return ret;
2570}
2571
f2f432f2 2572static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2573{
2574 struct pci_dev *pdev = hdev->pdev;
2575 u32 val;
2576
f2f432f2 2577 switch (hdev->reset_type) {
4ed340ab
L		 2578 case HNAE3_GLOBAL_RESET:
2579 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2580 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2581 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2582 dev_info(&pdev->dev, "Global Reset requested\n");
2583 break;
2584 case HNAE3_CORE_RESET:
2585 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2586 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2587 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2588 dev_info(&pdev->dev, "Core Reset requested\n");
2589 break;
2590 case HNAE3_FUNC_RESET:
2591 dev_info(&pdev->dev, "PF Reset requested\n");
2592 hclge_func_reset_cmd(hdev, 0);
cb1b9f77
SM		 2593 /* schedule again to check later */
2594 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2595 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2596 break;
2597 default:
2598 dev_warn(&pdev->dev,
f2f432f2 2599 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2600 break;
2601 }
2602}
2603
f2f432f2
SM		 2604static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2605 unsigned long *addr)
2606{
2607 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2608
2609 /* return the highest priority reset level amongst all */
2610 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2611 rst_level = HNAE3_GLOBAL_RESET;
2612 else if (test_bit(HNAE3_CORE_RESET, addr))
2613 rst_level = HNAE3_CORE_RESET;
2614 else if (test_bit(HNAE3_IMP_RESET, addr))
2615 rst_level = HNAE3_IMP_RESET;
2616 else if (test_bit(HNAE3_FUNC_RESET, addr))
2617 rst_level = HNAE3_FUNC_RESET;
2618
2619 /* now, clear all other resets */
2620 clear_bit(HNAE3_GLOBAL_RESET, addr);
2621 clear_bit(HNAE3_CORE_RESET, addr);
2622 clear_bit(HNAE3_IMP_RESET, addr);
2623 clear_bit(HNAE3_FUNC_RESET, addr);
2624
2625 return rst_level;
2626}
2627
2628static void hclge_reset(struct hclge_dev *hdev)
2629{
2630 /* perform reset of the stack & ae device for a client */
2631
2632 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2633
2634 if (!hclge_reset_wait(hdev)) {
2635 rtnl_lock();
2636 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2637 hclge_reset_ae_dev(hdev->ae_dev);
2638 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2639 rtnl_unlock();
2640 } else {
2641 /* schedule again to check pending resets later */
2642 set_bit(hdev->reset_type, &hdev->reset_pending);
2643 hclge_reset_task_schedule(hdev);
2644 }
2645
2646 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2647}
2648
4ed340ab
L		 2649static void hclge_reset_event(struct hnae3_handle *handle,
2650 enum hnae3_reset_type reset)
2651{
2652 struct hclge_vport *vport = hclge_get_vport(handle);
2653 struct hclge_dev *hdev = vport->back;
2654
2655 dev_info(&hdev->pdev->dev,
2656 "Receive reset event , reset_type is %d", reset);
2657
2658 switch (reset) {
2659 case HNAE3_FUNC_RESET:
2660 case HNAE3_CORE_RESET:
2661 case HNAE3_GLOBAL_RESET:
cb1b9f77
SM		 2662 /* request reset & schedule reset task */
2663 set_bit(reset, &hdev->reset_request);
2664 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2665 break;
2666 default:
2667 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2668 break;
2669 }
2670}
2671
2672static void hclge_reset_subtask(struct hclge_dev *hdev)
2673{
f2f432f2
SM		 2674 /* check if there is any ongoing reset in the hardware. This status can
2675 * be checked from reset_pending. If there is then, we need to wait for
2676 * hardware to complete reset.
2677 * a. If we are able to figure out in reasonable time that hardware
2678 * has fully resetted then, we can proceed with driver, client
2679 * reset.
2680 * b. else, we can come back later to check this status so re-sched
2681 * now.
2682 */
2683 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2684 if (hdev->reset_type != HNAE3_NONE_RESET)
2685 hclge_reset(hdev);
4ed340ab 2686
f2f432f2
SM		 2687 /* check if we got any *new* reset requests to be honored */
2688 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2689 if (hdev->reset_type != HNAE3_NONE_RESET)
2690 hclge_do_reset(hdev);
4ed340ab 2691
4ed340ab
L		 2692 hdev->reset_type = HNAE3_NONE_RESET;
2693}
2694
cb1b9f77 2695static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2696{
cb1b9f77
SM		 2697 struct hclge_dev *hdev =
2698 container_of(work, struct hclge_dev, rst_service_task);
2699
2700 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2701 return;
2702
2703 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2704
4ed340ab 2705 hclge_reset_subtask(hdev);
cb1b9f77
SM		 2706
2707 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2708}
2709
46a3df9f
S		 2710static void hclge_service_task(struct work_struct *work)
2711{
2712 struct hclge_dev *hdev =
2713 container_of(work, struct hclge_dev, service_task);
2714
2715 hclge_update_speed_duplex(hdev);
2716 hclge_update_link_status(hdev);
2717 hclge_update_stats_for_all(hdev);
2718 hclge_service_complete(hdev);
2719}
2720
2721static void hclge_disable_sriov(struct hclge_dev *hdev)
2722{
2a32ca13
AB		 2723 /* If our VFs are assigned we cannot shut down SR-IOV
2724 * without causing issues, so just leave the hardware
2725 * available but disabled
2726 */
2727 if (pci_vfs_assigned(hdev->pdev)) {
2728 dev_warn(&hdev->pdev->dev,
2729 "disabling driver while VFs are assigned\n");
2730 return;
2731 }
46a3df9f 2732
2a32ca13 2733 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2734}
2735
2736struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2737{
2738 /* VF handle has no client */
2739 if (!handle->client)
2740 return container_of(handle, struct hclge_vport, nic);
2741 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2742 return container_of(handle, struct hclge_vport, roce);
2743 else
2744 return container_of(handle, struct hclge_vport, nic);
2745}
2746
2747static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2748 struct hnae3_vector_info *vector_info)
2749{
2750 struct hclge_vport *vport = hclge_get_vport(handle);
2751 struct hnae3_vector_info *vector = vector_info;
2752 struct hclge_dev *hdev = vport->back;
2753 int alloc = 0;
2754 int i, j;
2755
2756 vector_num = min(hdev->num_msi_left, vector_num);
2757
2758 for (j = 0; j < vector_num; j++) {
2759 for (i = 1; i < hdev->num_msi; i++) {
2760 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2761 vector->vector = pci_irq_vector(hdev->pdev, i);
2762 vector->io_addr = hdev->hw.io_base +
2763 HCLGE_VECTOR_REG_BASE +
2764 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2765 vport->vport_id *
2766 HCLGE_VECTOR_VF_OFFSET;
2767 hdev->vector_status[i] = vport->vport_id;
887c3820 2768 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2769
2770 vector++;
2771 alloc++;
2772
2773 break;
2774 }
2775 }
2776 }
2777 hdev->num_msi_left -= alloc;
2778 hdev->num_msi_used += alloc;
2779
2780 return alloc;
2781}
2782
2783static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2784{
2785 int i;
2786
887c3820
SM		 2787 for (i = 0; i < hdev->num_msi; i++)
2788 if (vector == hdev->vector_irq[i])
2789 return i;
2790
46a3df9f
S		 2791 return -EINVAL;
2792}
2793
2794static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2795{
2796 return HCLGE_RSS_KEY_SIZE;
2797}
2798
2799static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2800{
2801 return HCLGE_RSS_IND_TBL_SIZE;
2802}
2803
2804static int hclge_get_rss_algo(struct hclge_dev *hdev)
2805{
d44f9b63 2806 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2807 struct hclge_desc desc;
2808 int rss_hash_algo;
2809 int ret;
2810
2811 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2812
2813 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2814 if (ret) {
2815 dev_err(&hdev->pdev->dev,
2816 "Get link status error, status =%d\n", ret);
2817 return ret;
2818 }
2819
d44f9b63 2820 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2821 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2822
2823 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2824 return ETH_RSS_HASH_TOP;
2825
2826 return -EINVAL;
2827}
2828
2829static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2830 const u8 hfunc, const u8 *key)
2831{
d44f9b63 2832 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2833 struct hclge_desc desc;
2834 int key_offset;
2835 int key_size;
2836 int ret;
2837
d44f9b63 2838 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2839
2840 for (key_offset = 0; key_offset < 3; key_offset++) {
2841 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2842 false);
2843
2844 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2845 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2846
2847 if (key_offset == 2)
2848 key_size =
2849 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2850 else
2851 key_size = HCLGE_RSS_HASH_KEY_NUM;
2852
2853 memcpy(req->hash_key,
2854 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2855
2856 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2857 if (ret) {
2858 dev_err(&hdev->pdev->dev,
2859 "Configure RSS config fail, status = %d\n",
2860 ret);
2861 return ret;
2862 }
2863 }
2864 return 0;
2865}
2866
2867static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2868{
d44f9b63 2869 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2870 struct hclge_desc desc;
2871 int i, j;
2872 int ret;
2873
d44f9b63 2874 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2875
2876 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2877 hclge_cmd_setup_basic_desc
2878 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2879
a90bb9a5
YL		 2880 req->start_table_index =
2881 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2882 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2883
2884 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2885 req->rss_result[j] =
2886 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2887
2888 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2889 if (ret) {
2890 dev_err(&hdev->pdev->dev,
2891 "Configure rss indir table fail,status = %d\n",
2892 ret);
2893 return ret;
2894 }
2895 }
2896 return 0;
2897}
2898
2899static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2900 u16 *tc_size, u16 *tc_offset)
2901{
d44f9b63 2902 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2903 struct hclge_desc desc;
2904 int ret;
2905 int i;
2906
2907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2908 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2909
2910 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2911 u16 mode = 0;
2912
2913 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2914 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 2915 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 2916 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 2917 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2918
2919 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2920 }
2921
2922 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2923 if (ret) {
2924 dev_err(&hdev->pdev->dev,
2925 "Configure rss tc mode fail, status = %d\n", ret);
2926 return ret;
2927 }
2928
2929 return 0;
2930}
2931
2932static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2933{
d44f9b63 2934 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2935 struct hclge_desc desc;
2936 int ret;
2937
2938 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2939
d44f9b63 2940 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
46a3df9f
S		 2941 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2942 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2943 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2944 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2945 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2946 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2947 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2948 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2949 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2950 if (ret) {
2951 dev_err(&hdev->pdev->dev,
2952 "Configure rss input fail, status = %d\n", ret);
2953 return ret;
2954 }
2955
2956 return 0;
2957}
2958
2959static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2960 u8 *key, u8 *hfunc)
2961{
2962 struct hclge_vport *vport = hclge_get_vport(handle);
2963 struct hclge_dev *hdev = vport->back;
2964 int i;
2965
2966 /* Get hash algorithm */
2967 if (hfunc)
2968 *hfunc = hclge_get_rss_algo(hdev);
2969
2970 /* Get the RSS Key required by the user */
2971 if (key)
2972 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2973
2974 /* Get indirect table */
2975 if (indir)
2976 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2977 indir[i] = vport->rss_indirection_tbl[i];
2978
2979 return 0;
2980}
2981
2982static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2983 const u8 *key, const u8 hfunc)
2984{
2985 struct hclge_vport *vport = hclge_get_vport(handle);
2986 struct hclge_dev *hdev = vport->back;
2987 u8 hash_algo;
2988 int ret, i;
2989
2990 /* Set the RSS Hash Key if specififed by the user */
2991 if (key) {
2992 /* Update the shadow RSS key with user specified qids */
2993 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2994
2995 if (hfunc == ETH_RSS_HASH_TOP ||
2996 hfunc == ETH_RSS_HASH_NO_CHANGE)
2997 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2998 else
2999 return -EINVAL;
3000 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3001 if (ret)
3002 return ret;
3003 }
3004
3005 /* Update the shadow RSS table with user specified qids */
3006 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3007 vport->rss_indirection_tbl[i] = indir[i];
3008
3009 /* Update the hardware */
3010 ret = hclge_set_rss_indir_table(hdev, indir);
3011 return ret;
3012}
3013
f7db940a
L		 3014static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3015{
3016 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3017
3018 if (nfc->data & RXH_L4_B_2_3)
3019 hash_sets |= HCLGE_D_PORT_BIT;
3020 else
3021 hash_sets &= ~HCLGE_D_PORT_BIT;
3022
3023 if (nfc->data & RXH_IP_SRC)
3024 hash_sets |= HCLGE_S_IP_BIT;
3025 else
3026 hash_sets &= ~HCLGE_S_IP_BIT;
3027
3028 if (nfc->data & RXH_IP_DST)
3029 hash_sets |= HCLGE_D_IP_BIT;
3030 else
3031 hash_sets &= ~HCLGE_D_IP_BIT;
3032
3033 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3034 hash_sets |= HCLGE_V_TAG_BIT;
3035
3036 return hash_sets;
3037}
3038
3039static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3040 struct ethtool_rxnfc *nfc)
3041{
3042 struct hclge_vport *vport = hclge_get_vport(handle);
3043 struct hclge_dev *hdev = vport->back;
3044 struct hclge_rss_input_tuple_cmd *req;
3045 struct hclge_desc desc;
3046 u8 tuple_sets;
3047 int ret;
3048
3049 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3050 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3051 return -EINVAL;
3052
3053 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3054 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3055 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3056 if (ret) {
3057 dev_err(&hdev->pdev->dev,
3058 "Read rss tuple fail, status = %d\n", ret);
3059 return ret;
3060 }
3061
3062 hclge_cmd_reuse_desc(&desc, false);
3063
3064 tuple_sets = hclge_get_rss_hash_bits(nfc);
3065 switch (nfc->flow_type) {
3066 case TCP_V4_FLOW:
3067 req->ipv4_tcp_en = tuple_sets;
3068 break;
3069 case TCP_V6_FLOW:
3070 req->ipv6_tcp_en = tuple_sets;
3071 break;
3072 case UDP_V4_FLOW:
3073 req->ipv4_udp_en = tuple_sets;
3074 break;
3075 case UDP_V6_FLOW:
3076 req->ipv6_udp_en = tuple_sets;
3077 break;
3078 case SCTP_V4_FLOW:
3079 req->ipv4_sctp_en = tuple_sets;
3080 break;
3081 case SCTP_V6_FLOW:
3082 if ((nfc->data & RXH_L4_B_0_1) ||
3083 (nfc->data & RXH_L4_B_2_3))
3084 return -EINVAL;
3085
3086 req->ipv6_sctp_en = tuple_sets;
3087 break;
3088 case IPV4_FLOW:
3089 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3090 break;
3091 case IPV6_FLOW:
3092 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3093 break;
3094 default:
3095 return -EINVAL;
3096 }
3097
3098 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3099 if (ret)
3100 dev_err(&hdev->pdev->dev,
3101 "Set rss tuple fail, status = %d\n", ret);
3102
3103 return ret;
3104}
3105
07d29954
L		 3106static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3107 struct ethtool_rxnfc *nfc)
3108{
3109 struct hclge_vport *vport = hclge_get_vport(handle);
3110 struct hclge_dev *hdev = vport->back;
3111 struct hclge_rss_input_tuple_cmd *req;
3112 struct hclge_desc desc;
3113 u8 tuple_sets;
3114 int ret;
3115
3116 nfc->data = 0;
3117
3118 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3119 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3120 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3121 if (ret) {
3122 dev_err(&hdev->pdev->dev,
3123 "Read rss tuple fail, status = %d\n", ret);
3124 return ret;
3125 }
3126
3127 switch (nfc->flow_type) {
3128 case TCP_V4_FLOW:
3129 tuple_sets = req->ipv4_tcp_en;
3130 break;
3131 case UDP_V4_FLOW:
3132 tuple_sets = req->ipv4_udp_en;
3133 break;
3134 case TCP_V6_FLOW:
3135 tuple_sets = req->ipv6_tcp_en;
3136 break;
3137 case UDP_V6_FLOW:
3138 tuple_sets = req->ipv6_udp_en;
3139 break;
3140 case SCTP_V4_FLOW:
3141 tuple_sets = req->ipv4_sctp_en;
3142 break;
3143 case SCTP_V6_FLOW:
3144 tuple_sets = req->ipv6_sctp_en;
3145 break;
3146 case IPV4_FLOW:
3147 case IPV6_FLOW:
3148 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3149 break;
3150 default:
3151 return -EINVAL;
3152 }
3153
3154 if (!tuple_sets)
3155 return 0;
3156
3157 if (tuple_sets & HCLGE_D_PORT_BIT)
3158 nfc->data |= RXH_L4_B_2_3;
3159 if (tuple_sets & HCLGE_S_PORT_BIT)
3160 nfc->data |= RXH_L4_B_0_1;
3161 if (tuple_sets & HCLGE_D_IP_BIT)
3162 nfc->data |= RXH_IP_DST;
3163 if (tuple_sets & HCLGE_S_IP_BIT)
3164 nfc->data |= RXH_IP_SRC;
3165
3166 return 0;
3167}
3168
46a3df9f
S		 3169static int hclge_get_tc_size(struct hnae3_handle *handle)
3170{
3171 struct hclge_vport *vport = hclge_get_vport(handle);
3172 struct hclge_dev *hdev = vport->back;
3173
3174 return hdev->rss_size_max;
3175}
3176
77f255c1 3177int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f
S		 3178{
3179 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3180 struct hclge_vport *vport = hdev->vport;
3181 u16 tc_offset[HCLGE_MAX_TC_NUM];
3182 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3183 u16 tc_valid[HCLGE_MAX_TC_NUM];
3184 u16 tc_size[HCLGE_MAX_TC_NUM];
3185 u32 *rss_indir = NULL;
68ece54e 3186 u16 rss_size = 0, roundup_size;
46a3df9f
S		 3187 const u8 *key;
3188 int i, ret, j;
3189
3190 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3191 if (!rss_indir)
3192 return -ENOMEM;
3193
3194 /* Get default RSS key */
3195 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3196
3197 /* Initialize RSS indirect table for each vport */
3198 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3199 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3200 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 3201 i % vport[j].alloc_rss_size;
3202
3203 /* vport 0 is for PF */
3204 if (j != 0)
3205 continue;
3206
3207 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 3208 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3209 }
3210 }
3211 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3212 if (ret)
3213 goto err;
3214
3215 key = rss_key;
3216 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3217 if (ret)
3218 goto err;
3219
3220 ret = hclge_set_rss_input_tuple(hdev);
3221 if (ret)
3222 goto err;
3223
68ece54e
YL		 3224 /* Each TC have the same queue size, and tc_size set to hardware is
3225 * the log2 of roundup power of two of rss_size, the acutal queue
3226 * size is limited by indirection table.
3227 */
3228 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3229 dev_err(&hdev->pdev->dev,
3230 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3231 rss_size);
81359617
CJ		 3232 ret = -EINVAL;
3233 goto err;
68ece54e
YL		 3234 }
3235
3236 roundup_size = roundup_pow_of_two(rss_size);
3237 roundup_size = ilog2(roundup_size);
3238
46a3df9f 3239 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3240 tc_valid[i] = 0;
46a3df9f 3241
68ece54e
YL		 3242 if (!(hdev->hw_tc_map & BIT(i)))
3243 continue;
3244
3245 tc_valid[i] = 1;
3246 tc_size[i] = roundup_size;
3247 tc_offset[i] = rss_size * i;
46a3df9f 3248 }
68ece54e 3249
46a3df9f
S		 3250 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3251
3252err:
3253 kfree(rss_indir);
3254
3255 return ret;
3256}
3257
3258int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
3259 struct hnae3_ring_chain_node *ring_chain)
3260{
3261 struct hclge_dev *hdev = vport->back;
d44f9b63 3262 struct hclge_ctrl_vector_chain_cmd *req;
46a3df9f
S		 3263 struct hnae3_ring_chain_node *node;
3264 struct hclge_desc desc;
3265 int ret;
3266 int i;
3267
3268 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
3269
d44f9b63 3270 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
46a3df9f
S		 3271 req->int_vector_id = vector_id;
3272
3273 i = 0;
3274 for (node = ring_chain; node; node = node->next) {
a90bb9a5
YL		 3275 u16 type_and_id = 0;
3276
3277 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
46a3df9f 3278 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5
YL		 3279 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3280 node->tqp_index);
3281 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
0305b443
L		 3282 HCLGE_INT_GL_IDX_S,
3283 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5 3284 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
0305b443 3285 req->vfid = vport->vport_id;
46a3df9f
S		 3286
3287 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3288 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3289
3290 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3291 if (ret) {
3292 dev_err(&hdev->pdev->dev,
3293 "Map TQP fail, status is %d.\n",
3294 ret);
3295 return ret;
3296 }
3297 i = 0;
3298
3299 hclge_cmd_setup_basic_desc(&desc,
3300 HCLGE_OPC_ADD_RING_TO_VECTOR,
3301 false);
3302 req->int_vector_id = vector_id;
3303 }
3304 }
3305
3306 if (i > 0) {
3307 req->int_cause_num = i;
3308
3309 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3310 if (ret) {
3311 dev_err(&hdev->pdev->dev,
3312 "Map TQP fail, status is %d.\n", ret);
3313 return ret;
3314 }
3315 }
3316
3317 return 0;
3318}
3319
1db9b1bf
YL		 3320static int hclge_map_handle_ring_to_vector(
3321 struct hnae3_handle *handle, int vector,
3322 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3323{
3324 struct hclge_vport *vport = hclge_get_vport(handle);
3325 struct hclge_dev *hdev = vport->back;
3326 int vector_id;
3327
3328 vector_id = hclge_get_vector_index(hdev, vector);
3329 if (vector_id < 0) {
3330 dev_err(&hdev->pdev->dev,
3331 "Get vector index fail. ret =%d\n", vector_id);
3332 return vector_id;
3333 }
3334
3335 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
3336}
3337
3338static int hclge_unmap_ring_from_vector(
3339 struct hnae3_handle *handle, int vector,
3340 struct hnae3_ring_chain_node *ring_chain)
3341{
3342 struct hclge_vport *vport = hclge_get_vport(handle);
3343 struct hclge_dev *hdev = vport->back;
d44f9b63 3344 struct hclge_ctrl_vector_chain_cmd *req;
46a3df9f
S		 3345 struct hnae3_ring_chain_node *node;
3346 struct hclge_desc desc;
3347 int i, vector_id;
3348 int ret;
3349
3350 vector_id = hclge_get_vector_index(hdev, vector);
3351 if (vector_id < 0) {
3352 dev_err(&handle->pdev->dev,
3353 "Get vector index fail. ret =%d\n", vector_id);
3354 return vector_id;
3355 }
3356
3357 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
3358
d44f9b63 3359 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
46a3df9f
S		 3360 req->int_vector_id = vector_id;
3361
3362 i = 0;
3363 for (node = ring_chain; node; node = node->next) {
a90bb9a5
YL		 3364 u16 type_and_id = 0;
3365
3366 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
46a3df9f 3367 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5
YL		 3368 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3369 node->tqp_index);
3370 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
0305b443
L		 3371 HCLGE_INT_GL_IDX_S,
3372 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f 3373
a90bb9a5 3374 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
0305b443 3375 req->vfid = vport->vport_id;
46a3df9f
S		 3376
3377 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3378 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3379
3380 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3381 if (ret) {
3382 dev_err(&hdev->pdev->dev,
3383 "Unmap TQP fail, status is %d.\n",
3384 ret);
3385 return ret;
3386 }
3387 i = 0;
3388 hclge_cmd_setup_basic_desc(&desc,
c5b1b975 3389 HCLGE_OPC_DEL_RING_TO_VECTOR,
46a3df9f
S		 3390 false);
3391 req->int_vector_id = vector_id;
3392 }
3393 }
3394
3395 if (i > 0) {
3396 req->int_cause_num = i;
3397
3398 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3399 if (ret) {
3400 dev_err(&hdev->pdev->dev,
3401 "Unmap TQP fail, status is %d.\n", ret);
3402 return ret;
3403 }
3404 }
3405
3406 return 0;
3407}
3408
3409int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3410 struct hclge_promisc_param *param)
3411{
d44f9b63 3412 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3413 struct hclge_desc desc;
3414 int ret;
3415
3416 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3417
d44f9b63 3418 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f
S		 3419 req->vf_id = param->vf_id;
3420 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3421
3422 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3423 if (ret) {
3424 dev_err(&hdev->pdev->dev,
3425 "Set promisc mode fail, status is %d.\n", ret);
3426 return ret;
3427 }
3428 return 0;
3429}
3430
3431void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3432 bool en_mc, bool en_bc, int vport_id)
3433{
3434 if (!param)
3435 return;
3436
3437 memset(param, 0, sizeof(struct hclge_promisc_param));
3438 if (en_uc)
3439 param->enable = HCLGE_PROMISC_EN_UC;
3440 if (en_mc)
3441 param->enable |= HCLGE_PROMISC_EN_MC;
3442 if (en_bc)
3443 param->enable |= HCLGE_PROMISC_EN_BC;
3444 param->vf_id = vport_id;
3445}
3446
3447static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3448{
3449 struct hclge_vport *vport = hclge_get_vport(handle);
3450 struct hclge_dev *hdev = vport->back;
3451 struct hclge_promisc_param param;
3452
3453 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3454 hclge_cmd_set_promisc_mode(hdev, &param);
3455}
3456
3457static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3458{
3459 struct hclge_desc desc;
d44f9b63
YL		 3460 struct hclge_config_mac_mode_cmd *req =
3461 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3462 u32 loop_en = 0;
46a3df9f
S		 3463 int ret;
3464
3465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3466 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3467 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3468 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3469 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3470 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3471 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3472 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3473 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3474 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3475 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3476 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3477 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3478 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3479 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3480 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3481
3482 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3483 if (ret)
3484 dev_err(&hdev->pdev->dev,
3485 "mac enable fail, ret =%d.\n", ret);
3486}
3487
c39c4d98
YL		 3488static int hclge_set_loopback(struct hnae3_handle *handle,
3489 enum hnae3_loop loop_mode, bool en)
3490{
3491 struct hclge_vport *vport = hclge_get_vport(handle);
3492 struct hclge_config_mac_mode_cmd *req;
3493 struct hclge_dev *hdev = vport->back;
3494 struct hclge_desc desc;
3495 u32 loop_en;
3496 int ret;
3497
3498 switch (loop_mode) {
3499 case HNAE3_MAC_INTER_LOOP_MAC:
3500 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3501 /* 1 Read out the MAC mode config at first */
3502 hclge_cmd_setup_basic_desc(&desc,
3503 HCLGE_OPC_CONFIG_MAC_MODE,
3504 true);
3505 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3506 if (ret) {
3507 dev_err(&hdev->pdev->dev,
3508 "mac loopback get fail, ret =%d.\n",
3509 ret);
3510 return ret;
3511 }
3512
3513 /* 2 Then setup the loopback flag */
3514 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3515 if (en)
3516 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3517 else
3518 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3519
3520 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3521
3522 /* 3 Config mac work mode with loopback flag
3523 * and its original configure parameters
3524 */
3525 hclge_cmd_reuse_desc(&desc, false);
3526 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3527 if (ret)
3528 dev_err(&hdev->pdev->dev,
3529 "mac loopback set fail, ret =%d.\n", ret);
3530 break;
3531 default:
3532 ret = -ENOTSUPP;
3533 dev_err(&hdev->pdev->dev,
3534 "loop_mode %d is not supported\n", loop_mode);
3535 break;
3536 }
3537
3538 return ret;
3539}
3540
46a3df9f
S		 3541static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3542 int stream_id, bool enable)
3543{
3544 struct hclge_desc desc;
d44f9b63
YL		 3545 struct hclge_cfg_com_tqp_queue_cmd *req =
3546 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3547 int ret;
3548
3549 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3550 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3551 req->stream_id = cpu_to_le16(stream_id);
3552 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3553
3554 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3555 if (ret)
3556 dev_err(&hdev->pdev->dev,
3557 "Tqp enable fail, status =%d.\n", ret);
3558 return ret;
3559}
3560
3561static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3562{
3563 struct hclge_vport *vport = hclge_get_vport(handle);
3564 struct hnae3_queue *queue;
3565 struct hclge_tqp *tqp;
3566 int i;
3567
3568 for (i = 0; i < vport->alloc_tqps; i++) {
3569 queue = handle->kinfo.tqp[i];
3570 tqp = container_of(queue, struct hclge_tqp, q);
3571 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3572 }
3573}
3574
3575static int hclge_ae_start(struct hnae3_handle *handle)
3576{
3577 struct hclge_vport *vport = hclge_get_vport(handle);
3578 struct hclge_dev *hdev = vport->back;
3579 int i, queue_id, ret;
3580
3581 for (i = 0; i < vport->alloc_tqps; i++) {
3582 /* todo clear interrupt */
3583 /* ring enable */
3584 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3585 if (queue_id < 0) {
3586 dev_warn(&hdev->pdev->dev,
3587 "Get invalid queue id, ignore it\n");
3588 continue;
3589 }
3590
3591 hclge_tqp_enable(hdev, queue_id, 0, true);
3592 }
3593 /* mac enable */
3594 hclge_cfg_mac_mode(hdev, true);
3595 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3596 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 3597
3598 ret = hclge_mac_start_phy(hdev);
3599 if (ret)
3600 return ret;
3601
3602 /* reset tqp stats */
3603 hclge_reset_tqp_stats(handle);
3604
3605 return 0;
3606}
3607
3608static void hclge_ae_stop(struct hnae3_handle *handle)
3609{
3610 struct hclge_vport *vport = hclge_get_vport(handle);
3611 struct hclge_dev *hdev = vport->back;
3612 int i, queue_id;
3613
3614 for (i = 0; i < vport->alloc_tqps; i++) {
3615 /* Ring disable */
3616 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3617 if (queue_id < 0) {
3618 dev_warn(&hdev->pdev->dev,
3619 "Get invalid queue id, ignore it\n");
3620 continue;
3621 }
3622
3623 hclge_tqp_enable(hdev, queue_id, 0, false);
3624 }
3625 /* Mac disable */
3626 hclge_cfg_mac_mode(hdev, false);
3627
3628 hclge_mac_stop_phy(hdev);
3629
3630 /* reset tqp stats */
3631 hclge_reset_tqp_stats(handle);
3632}
3633
3634static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3635 u16 cmdq_resp, u8 resp_code,
3636 enum hclge_mac_vlan_tbl_opcode op)
3637{
3638 struct hclge_dev *hdev = vport->back;
3639 int return_status = -EIO;
3640
3641 if (cmdq_resp) {
3642 dev_err(&hdev->pdev->dev,
3643 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3644 cmdq_resp);
3645 return -EIO;
3646 }
3647
3648 if (op == HCLGE_MAC_VLAN_ADD) {
3649 if ((!resp_code) || (resp_code == 1)) {
3650 return_status = 0;
3651 } else if (resp_code == 2) {
3652 return_status = -EIO;
3653 dev_err(&hdev->pdev->dev,
3654 "add mac addr failed for uc_overflow.\n");
3655 } else if (resp_code == 3) {
3656 return_status = -EIO;
3657 dev_err(&hdev->pdev->dev,
3658 "add mac addr failed for mc_overflow.\n");
3659 } else {
3660 dev_err(&hdev->pdev->dev,
3661 "add mac addr failed for undefined, code=%d.\n",
3662 resp_code);
3663 }
3664 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3665 if (!resp_code) {
3666 return_status = 0;
3667 } else if (resp_code == 1) {
3668 return_status = -EIO;
3669 dev_dbg(&hdev->pdev->dev,
3670 "remove mac addr failed for miss.\n");
3671 } else {
3672 dev_err(&hdev->pdev->dev,
3673 "remove mac addr failed for undefined, code=%d.\n",
3674 resp_code);
3675 }
3676 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3677 if (!resp_code) {
3678 return_status = 0;
3679 } else if (resp_code == 1) {
3680 return_status = -EIO;
3681 dev_dbg(&hdev->pdev->dev,
3682 "lookup mac addr failed for miss.\n");
3683 } else {
3684 dev_err(&hdev->pdev->dev,
3685 "lookup mac addr failed for undefined, code=%d.\n",
3686 resp_code);
3687 }
3688 } else {
3689 return_status = -EIO;
3690 dev_err(&hdev->pdev->dev,
3691 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3692 op);
3693 }
3694
3695 return return_status;
3696}
3697
3698static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3699{
3700 int word_num;
3701 int bit_num;
3702
3703 if (vfid > 255 || vfid < 0)
3704 return -EIO;
3705
3706 if (vfid >= 0 && vfid <= 191) {
3707 word_num = vfid / 32;
3708 bit_num = vfid % 32;
3709 if (clr)
a90bb9a5 3710 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3711 else
a90bb9a5 3712 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3713 } else {
3714 word_num = (vfid - 192) / 32;
3715 bit_num = vfid % 32;
3716 if (clr)
a90bb9a5 3717 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3718 else
a90bb9a5 3719 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3720 }
3721
3722 return 0;
3723}
3724
3725static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3726{
3727#define HCLGE_DESC_NUMBER 3
3728#define HCLGE_FUNC_NUMBER_PER_DESC 6
3729 int i, j;
3730
3731 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3732 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3733 if (desc[i].data[j])
3734 return false;
3735
3736 return true;
3737}
3738
d44f9b63 3739static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3740 const u8 *addr)
3741{
3742 const unsigned char *mac_addr = addr;
3743 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3744 (mac_addr[0]) | (mac_addr[1] << 8);
3745 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3746
3747 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3748 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3749}
3750
1db9b1bf
YL		 3751static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3752 const u8 *addr)
46a3df9f
S		 3753{
3754 u16 high_val = addr[1] | (addr[0] << 8);
3755 struct hclge_dev *hdev = vport->back;
3756 u32 rsh = 4 - hdev->mta_mac_sel_type;
3757 u16 ret_val = (high_val >> rsh) & 0xfff;
3758
3759 return ret_val;
3760}
3761
3762static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3763 enum hclge_mta_dmac_sel_type mta_mac_sel,
3764 bool enable)
3765{
d44f9b63 3766 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3767 struct hclge_desc desc;
3768 int ret;
3769
d44f9b63 3770 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3771 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3772
3773 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3774 enable);
3775 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3776 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3777
3778 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3779 if (ret) {
3780 dev_err(&hdev->pdev->dev,
3781 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3782 ret);
3783 return ret;
3784 }
3785
3786 return 0;
3787}
3788
3789int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3790 u8 func_id,
3791 bool enable)
3792{
d44f9b63 3793 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3794 struct hclge_desc desc;
3795 int ret;
3796
d44f9b63 3797 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3798 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3799
3800 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3801 enable);
3802 req->function_id = func_id;
3803
3804 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3805 if (ret) {
3806 dev_err(&hdev->pdev->dev,
3807 "Config func_id enable failed for cmd_send, ret =%d.\n",
3808 ret);
3809 return ret;
3810 }
3811
3812 return 0;
3813}
3814
3815static int hclge_set_mta_table_item(struct hclge_vport *vport,
3816 u16 idx,
3817 bool enable)
3818{
3819 struct hclge_dev *hdev = vport->back;
d44f9b63 3820 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3821 struct hclge_desc desc;
a90bb9a5 3822 u16 item_idx = 0;
46a3df9f
S		 3823 int ret;
3824
d44f9b63 3825 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 3826 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3827 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3828
a90bb9a5 3829 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 3830 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3831 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3832
3833 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3834 if (ret) {
3835 dev_err(&hdev->pdev->dev,
3836 "Config mta table item failed for cmd_send, ret =%d.\n",
3837 ret);
3838 return ret;
3839 }
3840
3841 return 0;
3842}
3843
3844static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3845 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3846{
3847 struct hclge_dev *hdev = vport->back;
3848 struct hclge_desc desc;
3849 u8 resp_code;
a90bb9a5 3850 u16 retval;
46a3df9f
S		 3851 int ret;
3852
3853 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3854
d44f9b63 3855 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3856
3857 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3858 if (ret) {
3859 dev_err(&hdev->pdev->dev,
3860 "del mac addr failed for cmd_send, ret =%d.\n",
3861 ret);
3862 return ret;
3863 }
a90bb9a5
YL		 3864 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3865 retval = le16_to_cpu(desc.retval);
46a3df9f 3866
a90bb9a5 3867 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3868 HCLGE_MAC_VLAN_REMOVE);
3869}
3870
3871static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3872 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3873 struct hclge_desc *desc,
3874 bool is_mc)
3875{
3876 struct hclge_dev *hdev = vport->back;
3877 u8 resp_code;
a90bb9a5 3878 u16 retval;
46a3df9f
S		 3879 int ret;
3880
3881 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3882 if (is_mc) {
3883 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3884 memcpy(desc[0].data,
3885 req,
d44f9b63 3886 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3887 hclge_cmd_setup_basic_desc(&desc[1],
3888 HCLGE_OPC_MAC_VLAN_ADD,
3889 true);
3890 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3891 hclge_cmd_setup_basic_desc(&desc[2],
3892 HCLGE_OPC_MAC_VLAN_ADD,
3893 true);
3894 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3895 } else {
3896 memcpy(desc[0].data,
3897 req,
d44f9b63 3898 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3899 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3900 }
3901 if (ret) {
3902 dev_err(&hdev->pdev->dev,
3903 "lookup mac addr failed for cmd_send, ret =%d.\n",
3904 ret);
3905 return ret;
3906 }
a90bb9a5
YL		 3907 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3908 retval = le16_to_cpu(desc[0].retval);
46a3df9f 3909
a90bb9a5 3910 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3911 HCLGE_MAC_VLAN_LKUP);
3912}
3913
3914static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3915 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3916 struct hclge_desc *mc_desc)
3917{
3918 struct hclge_dev *hdev = vport->back;
3919 int cfg_status;
3920 u8 resp_code;
a90bb9a5 3921 u16 retval;
46a3df9f
S		 3922 int ret;
3923
3924 if (!mc_desc) {
3925 struct hclge_desc desc;
3926
3927 hclge_cmd_setup_basic_desc(&desc,
3928 HCLGE_OPC_MAC_VLAN_ADD,
3929 false);
d44f9b63
YL		 3930 memcpy(desc.data, req,
3931 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3932 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 3933 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3934 retval = le16_to_cpu(desc.retval);
3935
3936 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3937 resp_code,
3938 HCLGE_MAC_VLAN_ADD);
3939 } else {
c3b6f755 3940 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 3941 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3942 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 3943 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3944 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 3945 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3946 memcpy(mc_desc[0].data, req,
d44f9b63 3947 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3948 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 3949 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3950 retval = le16_to_cpu(mc_desc[0].retval);
3951
3952 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3953 resp_code,
3954 HCLGE_MAC_VLAN_ADD);
3955 }
3956
3957 if (ret) {
3958 dev_err(&hdev->pdev->dev,
3959 "add mac addr failed for cmd_send, ret =%d.\n",
3960 ret);
3961 return ret;
3962 }
3963
3964 return cfg_status;
3965}
3966
3967static int hclge_add_uc_addr(struct hnae3_handle *handle,
3968 const unsigned char *addr)
3969{
3970 struct hclge_vport *vport = hclge_get_vport(handle);
3971
3972 return hclge_add_uc_addr_common(vport, addr);
3973}
3974
3975int hclge_add_uc_addr_common(struct hclge_vport *vport,
3976 const unsigned char *addr)
3977{
3978 struct hclge_dev *hdev = vport->back;
d44f9b63 3979 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 3980 enum hclge_cmd_status status;
a90bb9a5 3981 u16 egress_port = 0;
46a3df9f
S		 3982
3983 /* mac addr check */
3984 if (is_zero_ether_addr(addr) ||
3985 is_broadcast_ether_addr(addr) ||
3986 is_multicast_ether_addr(addr)) {
3987 dev_err(&hdev->pdev->dev,
3988 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3989 addr,
3990 is_zero_ether_addr(addr),
3991 is_broadcast_ether_addr(addr),
3992 is_multicast_ether_addr(addr));
3993 return -EINVAL;
3994 }
3995
3996 memset(&req, 0, sizeof(req));
3997 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3998 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3999 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4000 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 4001
4002 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4003 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4004 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 4005 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 4006 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 4007 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 4008
4009 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4010
4011 hclge_prepare_mac_addr(&req, addr);
4012
4013 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4014
4015 return status;
4016}
4017
4018static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4019 const unsigned char *addr)
4020{
4021 struct hclge_vport *vport = hclge_get_vport(handle);
4022
4023 return hclge_rm_uc_addr_common(vport, addr);
4024}
4025
4026int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4027 const unsigned char *addr)
4028{
4029 struct hclge_dev *hdev = vport->back;
d44f9b63 4030 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4031 enum hclge_cmd_status status;
4032
4033 /* mac addr check */
4034 if (is_zero_ether_addr(addr) ||
4035 is_broadcast_ether_addr(addr) ||
4036 is_multicast_ether_addr(addr)) {
4037 dev_dbg(&hdev->pdev->dev,
4038 "Remove mac err! invalid mac:%pM.\n",
4039 addr);
4040 return -EINVAL;
4041 }
4042
4043 memset(&req, 0, sizeof(req));
4044 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4045 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4046 hclge_prepare_mac_addr(&req, addr);
4047 status = hclge_remove_mac_vlan_tbl(vport, &req);
4048
4049 return status;
4050}
4051
4052static int hclge_add_mc_addr(struct hnae3_handle *handle,
4053 const unsigned char *addr)
4054{
4055 struct hclge_vport *vport = hclge_get_vport(handle);
4056
4057 return hclge_add_mc_addr_common(vport, addr);
4058}
4059
4060int hclge_add_mc_addr_common(struct hclge_vport *vport,
4061 const unsigned char *addr)
4062{
4063 struct hclge_dev *hdev = vport->back;
d44f9b63 4064 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4065 struct hclge_desc desc[3];
4066 u16 tbl_idx;
4067 int status;
4068
4069 /* mac addr check */
4070 if (!is_multicast_ether_addr(addr)) {
4071 dev_err(&hdev->pdev->dev,
4072 "Add mc mac err! invalid mac:%pM.\n",
4073 addr);
4074 return -EINVAL;
4075 }
4076 memset(&req, 0, sizeof(req));
4077 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4078 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4079 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4080 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4081 hclge_prepare_mac_addr(&req, addr);
4082 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4083 if (!status) {
4084 /* This mac addr exist, update VFID for it */
4085 hclge_update_desc_vfid(desc, vport->vport_id, false);
4086 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4087 } else {
4088 /* This mac addr do not exist, add new entry for it */
4089 memset(desc[0].data, 0, sizeof(desc[0].data));
4090 memset(desc[1].data, 0, sizeof(desc[0].data));
4091 memset(desc[2].data, 0, sizeof(desc[0].data));
4092 hclge_update_desc_vfid(desc, vport->vport_id, false);
4093 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4094 }
4095
4096 /* Set MTA table for this MAC address */
4097 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4098 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4099
4100 return status;
4101}
4102
4103static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4104 const unsigned char *addr)
4105{
4106 struct hclge_vport *vport = hclge_get_vport(handle);
4107
4108 return hclge_rm_mc_addr_common(vport, addr);
4109}
4110
4111int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4112 const unsigned char *addr)
4113{
4114 struct hclge_dev *hdev = vport->back;
d44f9b63 4115 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4116 enum hclge_cmd_status status;
4117 struct hclge_desc desc[3];
4118 u16 tbl_idx;
4119
4120 /* mac addr check */
4121 if (!is_multicast_ether_addr(addr)) {
4122 dev_dbg(&hdev->pdev->dev,
4123 "Remove mc mac err! invalid mac:%pM.\n",
4124 addr);
4125 return -EINVAL;
4126 }
4127
4128 memset(&req, 0, sizeof(req));
4129 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4130 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4131 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4132 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4133 hclge_prepare_mac_addr(&req, addr);
4134 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4135 if (!status) {
4136 /* This mac addr exist, remove this handle's VFID for it */
4137 hclge_update_desc_vfid(desc, vport->vport_id, true);
4138
4139 if (hclge_is_all_function_id_zero(desc))
4140 /* All the vfid is zero, so need to delete this entry */
4141 status = hclge_remove_mac_vlan_tbl(vport, &req);
4142 else
4143 /* Not all the vfid is zero, update the vfid */
4144 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4145
4146 } else {
4147 /* This mac addr do not exist, can't delete it */
4148 dev_err(&hdev->pdev->dev,
d7629e74 4149 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 4150 status);
4151 return -EIO;
4152 }
4153
4154 /* Set MTB table for this MAC address */
4155 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4156 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4157
4158 return status;
4159}
4160
4161static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4162{
4163 struct hclge_vport *vport = hclge_get_vport(handle);
4164 struct hclge_dev *hdev = vport->back;
4165
4166 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4167}
4168
4169static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4170{
4171 const unsigned char *new_addr = (const unsigned char *)p;
4172 struct hclge_vport *vport = hclge_get_vport(handle);
4173 struct hclge_dev *hdev = vport->back;
4174
4175 /* mac addr check */
4176 if (is_zero_ether_addr(new_addr) ||
4177 is_broadcast_ether_addr(new_addr) ||
4178 is_multicast_ether_addr(new_addr)) {
4179 dev_err(&hdev->pdev->dev,
4180 "Change uc mac err! invalid mac:%p.\n",
4181 new_addr);
4182 return -EINVAL;
4183 }
4184
4185 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4186
4187 if (!hclge_add_uc_addr(handle, new_addr)) {
4188 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4189 return 0;
4190 }
4191
4192 return -EIO;
4193}
4194
4195static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4196 bool filter_en)
4197{
d44f9b63 4198 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4199 struct hclge_desc desc;
4200 int ret;
4201
4202 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4203
d44f9b63 4204 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4205 req->vlan_type = vlan_type;
4206 req->vlan_fe = filter_en;
4207
4208 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4209 if (ret) {
4210 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4211 ret);
4212 return ret;
4213 }
4214
4215 return 0;
4216}
4217
4218int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4219 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4220{
4221#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4222 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4223 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4224 struct hclge_desc desc[2];
4225 u8 vf_byte_val;
4226 u8 vf_byte_off;
4227 int ret;
4228
4229 hclge_cmd_setup_basic_desc(&desc[0],
4230 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4231 hclge_cmd_setup_basic_desc(&desc[1],
4232 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4233
4234 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4235
4236 vf_byte_off = vfid / 8;
4237 vf_byte_val = 1 << (vfid % 8);
4238
d44f9b63
YL		 4239 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4240 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4241
a90bb9a5 4242 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4243 req0->vlan_cfg = is_kill;
4244
4245 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4246 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4247 else
4248 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4249
4250 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4251 if (ret) {
4252 dev_err(&hdev->pdev->dev,
4253 "Send vf vlan command fail, ret =%d.\n",
4254 ret);
4255 return ret;
4256 }
4257
4258 if (!is_kill) {
4259 if (!req0->resp_code || req0->resp_code == 1)
4260 return 0;
4261
4262 dev_err(&hdev->pdev->dev,
4263 "Add vf vlan filter fail, ret =%d.\n",
4264 req0->resp_code);
4265 } else {
4266 if (!req0->resp_code)
4267 return 0;
4268
4269 dev_err(&hdev->pdev->dev,
4270 "Kill vf vlan filter fail, ret =%d.\n",
4271 req0->resp_code);
4272 }
4273
4274 return -EIO;
4275}
4276
4277static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4278 __be16 proto, u16 vlan_id,
4279 bool is_kill)
4280{
4281 struct hclge_vport *vport = hclge_get_vport(handle);
4282 struct hclge_dev *hdev = vport->back;
d44f9b63 4283 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4284 struct hclge_desc desc;
4285 u8 vlan_offset_byte_val;
4286 u8 vlan_offset_byte;
4287 u8 vlan_offset_160;
4288 int ret;
4289
4290 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4291
4292 vlan_offset_160 = vlan_id / 160;
4293 vlan_offset_byte = (vlan_id % 160) / 8;
4294 vlan_offset_byte_val = 1 << (vlan_id % 8);
4295
d44f9b63 4296 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4297 req->vlan_offset = vlan_offset_160;
4298 req->vlan_cfg = is_kill;
4299 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4300
4301 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4302 if (ret) {
4303 dev_err(&hdev->pdev->dev,
4304 "port vlan command, send fail, ret =%d.\n",
4305 ret);
4306 return ret;
4307 }
4308
4309 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4310 if (ret) {
4311 dev_err(&hdev->pdev->dev,
4312 "Set pf vlan filter config fail, ret =%d.\n",
4313 ret);
4314 return -EIO;
4315 }
4316
4317 return 0;
4318}
4319
4320static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4321 u16 vlan, u8 qos, __be16 proto)
4322{
4323 struct hclge_vport *vport = hclge_get_vport(handle);
4324 struct hclge_dev *hdev = vport->back;
4325
4326 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4327 return -EINVAL;
4328 if (proto != htons(ETH_P_8021Q))
4329 return -EPROTONOSUPPORT;
4330
4331 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4332}
4333
4334static int hclge_init_vlan_config(struct hclge_dev *hdev)
4335{
4336#define HCLGE_VLAN_TYPE_VF_TABLE 0
4337#define HCLGE_VLAN_TYPE_PORT_TABLE 1
5e43aef8 4338 struct hnae3_handle *handle;
46a3df9f
S		 4339 int ret;
4340
4341 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
4342 true);
4343 if (ret)
4344 return ret;
4345
4346 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
4347 true);
5e43aef8
L		 4348 if (ret)
4349 return ret;
46a3df9f 4350
5e43aef8
L		 4351 handle = &hdev->vport[0].nic;
4352 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4353}
4354
4355static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4356{
4357 struct hclge_vport *vport = hclge_get_vport(handle);
d44f9b63 4358 struct hclge_config_max_frm_size_cmd *req;
46a3df9f
S		 4359 struct hclge_dev *hdev = vport->back;
4360 struct hclge_desc desc;
4361 int ret;
4362
4363 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
4364 return -EINVAL;
4365
4366 hdev->mps = new_mtu;
4367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4368
d44f9b63 4369 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
46a3df9f
S		 4370 req->max_frm_size = cpu_to_le16(new_mtu);
4371
4372 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4373 if (ret) {
4374 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4375 return ret;
4376 }
4377
4378 return 0;
4379}
4380
4381static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4382 bool enable)
4383{
d44f9b63 4384 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4385 struct hclge_desc desc;
4386 int ret;
4387
4388 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4389
d44f9b63 4390 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4391 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4392 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4393
4394 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4395 if (ret) {
4396 dev_err(&hdev->pdev->dev,
4397 "Send tqp reset cmd error, status =%d\n", ret);
4398 return ret;
4399 }
4400
4401 return 0;
4402}
4403
4404static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4405{
d44f9b63 4406 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4407 struct hclge_desc desc;
4408 int ret;
4409
4410 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4411
d44f9b63 4412 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4413 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4414
4415 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4416 if (ret) {
4417 dev_err(&hdev->pdev->dev,
4418 "Get reset status error, status =%d\n", ret);
4419 return ret;
4420 }
4421
4422 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4423}
4424
4425static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4426{
4427 struct hclge_vport *vport = hclge_get_vport(handle);
4428 struct hclge_dev *hdev = vport->back;
4429 int reset_try_times = 0;
4430 int reset_status;
4431 int ret;
4432
4433 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4434 if (ret) {
4435 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4436 return;
4437 }
4438
4439 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4440 if (ret) {
4441 dev_warn(&hdev->pdev->dev,
4442 "Send reset tqp cmd fail, ret = %d\n", ret);
4443 return;
4444 }
4445
4446 reset_try_times = 0;
4447 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4448 /* Wait for tqp hw reset */
4449 msleep(20);
4450 reset_status = hclge_get_reset_status(hdev, queue_id);
4451 if (reset_status)
4452 break;
4453 }
4454
4455 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4456 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4457 return;
4458 }
4459
4460 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4461 if (ret) {
4462 dev_warn(&hdev->pdev->dev,
4463 "Deassert the soft reset fail, ret = %d\n", ret);
4464 return;
4465 }
4466}
4467
4468static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4469{
4470 struct hclge_vport *vport = hclge_get_vport(handle);
4471 struct hclge_dev *hdev = vport->back;
4472
4473 return hdev->fw_version;
4474}
4475
4476static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4477 u32 *rx_en, u32 *tx_en)
4478{
4479 struct hclge_vport *vport = hclge_get_vport(handle);
4480 struct hclge_dev *hdev = vport->back;
4481
4482 *auto_neg = hclge_get_autoneg(handle);
4483
4484 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4485 *rx_en = 0;
4486 *tx_en = 0;
4487 return;
4488 }
4489
4490 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4491 *rx_en = 1;
4492 *tx_en = 0;
4493 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4494 *tx_en = 1;
4495 *rx_en = 0;
4496 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4497 *rx_en = 1;
4498 *tx_en = 1;
4499 } else {
4500 *rx_en = 0;
4501 *tx_en = 0;
4502 }
4503}
4504
4505static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4506 u8 *auto_neg, u32 *speed, u8 *duplex)
4507{
4508 struct hclge_vport *vport = hclge_get_vport(handle);
4509 struct hclge_dev *hdev = vport->back;
4510
4511 if (speed)
4512 *speed = hdev->hw.mac.speed;
4513 if (duplex)
4514 *duplex = hdev->hw.mac.duplex;
4515 if (auto_neg)
4516 *auto_neg = hdev->hw.mac.autoneg;
4517}
4518
4519static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4520{
4521 struct hclge_vport *vport = hclge_get_vport(handle);
4522 struct hclge_dev *hdev = vport->back;
4523
4524 if (media_type)
4525 *media_type = hdev->hw.mac.media_type;
4526}
4527
4528static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4529 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4530{
4531 struct hclge_vport *vport = hclge_get_vport(handle);
4532 struct hclge_dev *hdev = vport->back;
4533 struct phy_device *phydev = hdev->hw.mac.phydev;
4534 int mdix_ctrl, mdix, retval, is_resolved;
4535
4536 if (!phydev) {
4537 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4538 *tp_mdix = ETH_TP_MDI_INVALID;
4539 return;
4540 }
4541
4542 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4543
4544 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4545 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4546 HCLGE_PHY_MDIX_CTRL_S);
4547
4548 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4549 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4550 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4551
4552 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4553
4554 switch (mdix_ctrl) {
4555 case 0x0:
4556 *tp_mdix_ctrl = ETH_TP_MDI;
4557 break;
4558 case 0x1:
4559 *tp_mdix_ctrl = ETH_TP_MDI_X;
4560 break;
4561 case 0x3:
4562 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4563 break;
4564 default:
4565 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4566 break;
4567 }
4568
4569 if (!is_resolved)
4570 *tp_mdix = ETH_TP_MDI_INVALID;
4571 else if (mdix)
4572 *tp_mdix = ETH_TP_MDI_X;
4573 else
4574 *tp_mdix = ETH_TP_MDI;
4575}
4576
4577static int hclge_init_client_instance(struct hnae3_client *client,
4578 struct hnae3_ae_dev *ae_dev)
4579{
4580 struct hclge_dev *hdev = ae_dev->priv;
4581 struct hclge_vport *vport;
4582 int i, ret;
4583
4584 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4585 vport = &hdev->vport[i];
4586
4587 switch (client->type) {
4588 case HNAE3_CLIENT_KNIC:
4589
4590 hdev->nic_client = client;
4591 vport->nic.client = client;
4592 ret = client->ops->init_instance(&vport->nic);
4593 if (ret)
4594 goto err;
4595
4596 if (hdev->roce_client &&
e92a0843 4597 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4598 struct hnae3_client *rc = hdev->roce_client;
4599
4600 ret = hclge_init_roce_base_info(vport);
4601 if (ret)
4602 goto err;
4603
4604 ret = rc->ops->init_instance(&vport->roce);
4605 if (ret)
4606 goto err;
4607 }
4608
4609 break;
4610 case HNAE3_CLIENT_UNIC:
4611 hdev->nic_client = client;
4612 vport->nic.client = client;
4613
4614 ret = client->ops->init_instance(&vport->nic);
4615 if (ret)
4616 goto err;
4617
4618 break;
4619 case HNAE3_CLIENT_ROCE:
e92a0843 4620 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4621 hdev->roce_client = client;
4622 vport->roce.client = client;
4623 }
4624
3a46f34d 4625 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 4626 ret = hclge_init_roce_base_info(vport);
4627 if (ret)
4628 goto err;
4629
4630 ret = client->ops->init_instance(&vport->roce);
4631 if (ret)
4632 goto err;
4633 }
4634 }
4635 }
4636
4637 return 0;
4638err:
4639 return ret;
4640}
4641
4642static void hclge_uninit_client_instance(struct hnae3_client *client,
4643 struct hnae3_ae_dev *ae_dev)
4644{
4645 struct hclge_dev *hdev = ae_dev->priv;
4646 struct hclge_vport *vport;
4647 int i;
4648
4649 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4650 vport = &hdev->vport[i];
a17dcf3f 4651 if (hdev->roce_client) {
46a3df9f
S		 4652 hdev->roce_client->ops->uninit_instance(&vport->roce,
4653 0);
a17dcf3f
L		 4654 hdev->roce_client = NULL;
4655 vport->roce.client = NULL;
4656 }
46a3df9f
S		 4657 if (client->type == HNAE3_CLIENT_ROCE)
4658 return;
a17dcf3f 4659 if (client->ops->uninit_instance) {
46a3df9f 4660 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 4661 hdev->nic_client = NULL;
4662 vport->nic.client = NULL;
4663 }
46a3df9f
S		 4664 }
4665}
4666
4667static int hclge_pci_init(struct hclge_dev *hdev)
4668{
4669 struct pci_dev *pdev = hdev->pdev;
4670 struct hclge_hw *hw;
4671 int ret;
4672
4673 ret = pci_enable_device(pdev);
4674 if (ret) {
4675 dev_err(&pdev->dev, "failed to enable PCI device\n");
4676 goto err_no_drvdata;
4677 }
4678
4679 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4680 if (ret) {
4681 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4682 if (ret) {
4683 dev_err(&pdev->dev,
4684 "can't set consistent PCI DMA");
4685 goto err_disable_device;
4686 }
4687 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4688 }
4689
4690 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4691 if (ret) {
4692 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4693 goto err_disable_device;
4694 }
4695
4696 pci_set_master(pdev);
4697 hw = &hdev->hw;
4698 hw->back = hdev;
4699 hw->io_base = pcim_iomap(pdev, 2, 0);
4700 if (!hw->io_base) {
4701 dev_err(&pdev->dev, "Can't map configuration register space\n");
4702 ret = -ENOMEM;
4703 goto err_clr_master;
4704 }
4705
709eb41a
L		 4706 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
4707
46a3df9f
S		 4708 return 0;
4709err_clr_master:
4710 pci_clear_master(pdev);
4711 pci_release_regions(pdev);
4712err_disable_device:
4713 pci_disable_device(pdev);
4714err_no_drvdata:
4715 pci_set_drvdata(pdev, NULL);
4716
4717 return ret;
4718}
4719
4720static void hclge_pci_uninit(struct hclge_dev *hdev)
4721{
4722 struct pci_dev *pdev = hdev->pdev;
4723
887c3820 4724 pci_free_irq_vectors(pdev);
46a3df9f
S		 4725 pci_clear_master(pdev);
4726 pci_release_mem_regions(pdev);
4727 pci_disable_device(pdev);
4728}
4729
4730static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4731{
4732 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 4733 struct hclge_dev *hdev;
4734 int ret;
4735
4736 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4737 if (!hdev) {
4738 ret = -ENOMEM;
4739 goto err_hclge_dev;
4740 }
4741
46a3df9f
S		 4742 hdev->pdev = pdev;
4743 hdev->ae_dev = ae_dev;
4ed340ab 4744 hdev->reset_type = HNAE3_NONE_RESET;
cb1b9f77 4745 hdev->reset_request = 0;
ca1d7669 4746 hdev->reset_pending = 0;
46a3df9f
S		 4747 ae_dev->priv = hdev;
4748
46a3df9f
S		 4749 ret = hclge_pci_init(hdev);
4750 if (ret) {
4751 dev_err(&pdev->dev, "PCI init failed\n");
4752 goto err_pci_init;
4753 }
4754
3efb960f
L		 4755 /* Firmware command queue initialize */
4756 ret = hclge_cmd_queue_init(hdev);
4757 if (ret) {
4758 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
4759 return ret;
4760 }
4761
4762 /* Firmware command initialize */
46a3df9f
S		 4763 ret = hclge_cmd_init(hdev);
4764 if (ret)
4765 goto err_cmd_init;
4766
4767 ret = hclge_get_cap(hdev);
4768 if (ret) {
e00e2197
CIK		 4769 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4770 ret);
46a3df9f
S		 4771 return ret;
4772 }
4773
4774 ret = hclge_configure(hdev);
4775 if (ret) {
4776 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4777 return ret;
4778 }
4779
887c3820 4780 ret = hclge_init_msi(hdev);
46a3df9f 4781 if (ret) {
887c3820 4782 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
46a3df9f
S		 4783 return ret;
4784 }
4785
466b0c00
L		 4786 ret = hclge_misc_irq_init(hdev);
4787 if (ret) {
4788 dev_err(&pdev->dev,
4789 "Misc IRQ(vector0) init error, ret = %d.\n",
4790 ret);
4791 return ret;
4792 }
4793
46a3df9f
S		 4794 ret = hclge_alloc_tqps(hdev);
4795 if (ret) {
4796 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4797 return ret;
4798 }
4799
4800 ret = hclge_alloc_vport(hdev);
4801 if (ret) {
4802 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4803 return ret;
4804 }
4805
7df7dad6
L		 4806 ret = hclge_map_tqp(hdev);
4807 if (ret) {
4808 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4809 return ret;
4810 }
4811
cf9cca2d 4812 ret = hclge_mac_mdio_config(hdev);
4813 if (ret) {
4814 dev_warn(&hdev->pdev->dev,
4815 "mdio config fail ret=%d\n", ret);
4816 return ret;
4817 }
4818
46a3df9f
S		 4819 ret = hclge_mac_init(hdev);
4820 if (ret) {
4821 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4822 return ret;
4823 }
4824 ret = hclge_buffer_alloc(hdev);
4825 if (ret) {
4826 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4827 return ret;
4828 }
4829
4830 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4831 if (ret) {
4832 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4833 return ret;
4834 }
4835
46a3df9f
S		 4836 ret = hclge_init_vlan_config(hdev);
4837 if (ret) {
4838 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4839 return ret;
4840 }
4841
4842 ret = hclge_tm_schd_init(hdev);
4843 if (ret) {
4844 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4845 return ret;
68ece54e
YL		 4846 }
4847
4848 ret = hclge_rss_init_hw(hdev);
4849 if (ret) {
4850 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4851 return ret;
46a3df9f
S		 4852 }
4853
cacde272
YL		 4854 hclge_dcb_ops_set(hdev);
4855
d039ef68 4856 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 4857 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 4858 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
46a3df9f 4859
466b0c00
L		 4860 /* Enable MISC vector(vector0) */
4861 hclge_enable_vector(&hdev->misc_vector, true);
4862
46a3df9f
S		 4863 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4864 set_bit(HCLGE_STATE_DOWN, &hdev->state);
cb1b9f77
SM		 4865 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
4866 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
46a3df9f
S		 4867
4868 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4869 return 0;
4870
4871err_cmd_init:
4872 pci_release_regions(pdev);
4873err_pci_init:
4874 pci_set_drvdata(pdev, NULL);
4875err_hclge_dev:
4876 return ret;
4877}
4878
c6dc5213 4879static void hclge_stats_clear(struct hclge_dev *hdev)
4880{
4881 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
4882}
4883
4ed340ab
L		 4884static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
4885{
4886 struct hclge_dev *hdev = ae_dev->priv;
4887 struct pci_dev *pdev = ae_dev->pdev;
4888 int ret;
4889
4890 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4891
c6dc5213 4892 hclge_stats_clear(hdev);
4893
4ed340ab
L		 4894 ret = hclge_cmd_init(hdev);
4895 if (ret) {
4896 dev_err(&pdev->dev, "Cmd queue init failed\n");
4897 return ret;
4898 }
4899
4900 ret = hclge_get_cap(hdev);
4901 if (ret) {
4902 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4903 ret);
4904 return ret;
4905 }
4906
4907 ret = hclge_configure(hdev);
4908 if (ret) {
4909 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4910 return ret;
4911 }
4912
4913 ret = hclge_map_tqp(hdev);
4914 if (ret) {
4915 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4916 return ret;
4917 }
4918
4919 ret = hclge_mac_init(hdev);
4920 if (ret) {
4921 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4922 return ret;
4923 }
4924
4925 ret = hclge_buffer_alloc(hdev);
4926 if (ret) {
4927 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4928 return ret;
4929 }
4930
4931 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4932 if (ret) {
4933 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4934 return ret;
4935 }
4936
4937 ret = hclge_init_vlan_config(hdev);
4938 if (ret) {
4939 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4940 return ret;
4941 }
4942
4943 ret = hclge_tm_schd_init(hdev);
4944 if (ret) {
4945 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4946 return ret;
4947 }
4948
4949 ret = hclge_rss_init_hw(hdev);
4950 if (ret) {
4951 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4952 return ret;
4953 }
4954
4955 /* Enable MISC vector(vector0) */
4956 hclge_enable_vector(&hdev->misc_vector, true);
4957
4958 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
4959 HCLGE_DRIVER_NAME);
4960
4961 return 0;
4962}
4963
46a3df9f
S		 4964static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4965{
4966 struct hclge_dev *hdev = ae_dev->priv;
4967 struct hclge_mac *mac = &hdev->hw.mac;
4968
4969 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4970
2a32ca13
AB		 4971 if (IS_ENABLED(CONFIG_PCI_IOV))
4972 hclge_disable_sriov(hdev);
46a3df9f 4973
d039ef68 4974 if (hdev->service_timer.function)
46a3df9f
S		 4975 del_timer_sync(&hdev->service_timer);
4976 if (hdev->service_task.func)
4977 cancel_work_sync(&hdev->service_task);
cb1b9f77
SM		 4978 if (hdev->rst_service_task.func)
4979 cancel_work_sync(&hdev->rst_service_task);
46a3df9f
S		 4980
4981 if (mac->phydev)
4982 mdiobus_unregister(mac->mdio_bus);
4983
466b0c00
L		 4984 /* Disable MISC vector(vector0) */
4985 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 4986 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 4987 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 4988 hclge_pci_uninit(hdev);
4989 ae_dev->priv = NULL;
4990}
4991
4992static const struct hnae3_ae_ops hclge_ops = {
4993 .init_ae_dev = hclge_init_ae_dev,
4994 .uninit_ae_dev = hclge_uninit_ae_dev,
4995 .init_client_instance = hclge_init_client_instance,
4996 .uninit_client_instance = hclge_uninit_client_instance,
4997 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4998 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4999 .get_vector = hclge_get_vector,
5000 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 5001 .set_loopback = hclge_set_loopback,
46a3df9f
S		 5002 .start = hclge_ae_start,
5003 .stop = hclge_ae_stop,
5004 .get_status = hclge_get_status,
5005 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5006 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5007 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5008 .get_media_type = hclge_get_media_type,
5009 .get_rss_key_size = hclge_get_rss_key_size,
5010 .get_rss_indir_size = hclge_get_rss_indir_size,
5011 .get_rss = hclge_get_rss,
5012 .set_rss = hclge_set_rss,
f7db940a 5013 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 5014 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 5015 .get_tc_size = hclge_get_tc_size,
5016 .get_mac_addr = hclge_get_mac_addr,
5017 .set_mac_addr = hclge_set_mac_addr,
5018 .add_uc_addr = hclge_add_uc_addr,
5019 .rm_uc_addr = hclge_rm_uc_addr,
5020 .add_mc_addr = hclge_add_mc_addr,
5021 .rm_mc_addr = hclge_rm_mc_addr,
5022 .set_autoneg = hclge_set_autoneg,
5023 .get_autoneg = hclge_get_autoneg,
5024 .get_pauseparam = hclge_get_pauseparam,
5025 .set_mtu = hclge_set_mtu,
5026 .reset_queue = hclge_reset_tqp,
5027 .get_stats = hclge_get_stats,
5028 .update_stats = hclge_update_stats,
5029 .get_strings = hclge_get_strings,
5030 .get_sset_count = hclge_get_sset_count,
5031 .get_fw_version = hclge_get_fw_version,
5032 .get_mdix_mode = hclge_get_mdix_mode,
5033 .set_vlan_filter = hclge_set_port_vlan_filter,
5034 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4ed340ab 5035 .reset_event = hclge_reset_event,
46a3df9f
S		 5036};
5037
5038static struct hnae3_ae_algo ae_algo = {
5039 .ops = &hclge_ops,
5040 .name = HCLGE_NAME,
5041 .pdev_id_table = ae_algo_pci_tbl,
5042};
5043
5044static int hclge_init(void)
5045{
5046 pr_info("%s is initializing\n", HCLGE_NAME);
5047
5048 return hnae3_register_ae_algo(&ae_algo);
5049}
5050
5051static void hclge_exit(void)
5052{
5053 hnae3_unregister_ae_algo(&ae_algo);
5054}
5055module_init(hclge_init);
5056module_exit(hclge_exit);
5057
5058MODULE_LICENSE("GPL");
5059MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5060MODULE_DESCRIPTION("HCLGE Driver");
5061MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)