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d71d8381 JS |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // Copyright (c) 2016-2017 Hisilicon Limited. | |
46a3df9f S |
3 | |
4 | #include <linux/acpi.h> | |
5 | #include <linux/device.h> | |
6 | #include <linux/etherdevice.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/interrupt.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/netdevice.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/platform_device.h> | |
2866ccb2 | 14 | #include <linux/if_vlan.h> |
f2f432f2 | 15 | #include <net/rtnetlink.h> |
46a3df9f | 16 | #include "hclge_cmd.h" |
cacde272 | 17 | #include "hclge_dcb.h" |
46a3df9f | 18 | #include "hclge_main.h" |
dde1a86e | 19 | #include "hclge_mbx.h" |
46a3df9f S |
20 | #include "hclge_mdio.h" |
21 | #include "hclge_tm.h" | |
22 | #include "hnae3.h" | |
23 | ||
24 | #define HCLGE_NAME "hclge" | |
25 | #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) | |
26 | #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) | |
27 | #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f)) | |
28 | #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f)) | |
29 | ||
46a3df9f S |
30 | static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, |
31 | enum hclge_mta_dmac_sel_type mta_mac_sel, | |
32 | bool enable); | |
f9fd82a9 | 33 | static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); |
46a3df9f | 34 | static int hclge_init_vlan_config(struct hclge_dev *hdev); |
4ed340ab | 35 | static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); |
46a3df9f S |
36 | |
37 | static struct hnae3_ae_algo ae_algo; | |
38 | ||
39 | static const struct pci_device_id ae_algo_pci_tbl[] = { | |
40 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, | |
41 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, | |
42 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, | |
43 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, | |
44 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, | |
45 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, | |
46 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, | |
e92a0843 | 47 | /* required last entry */ |
46a3df9f S |
48 | {0, } |
49 | }; | |
50 | ||
2f550a46 YL |
51 | MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); |
52 | ||
46a3df9f S |
53 | static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { |
54 | "Mac Loopback test", | |
55 | "Serdes Loopback test", | |
56 | "Phy Loopback test" | |
57 | }; | |
58 | ||
59 | static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = { | |
60 | {"igu_rx_oversize_pkt", | |
61 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)}, | |
62 | {"igu_rx_undersize_pkt", | |
63 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)}, | |
64 | {"igu_rx_out_all_pkt", | |
65 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)}, | |
66 | {"igu_rx_uni_pkt", | |
67 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)}, | |
68 | {"igu_rx_multi_pkt", | |
69 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)}, | |
70 | {"igu_rx_broad_pkt", | |
71 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)}, | |
72 | {"egu_tx_out_all_pkt", | |
73 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)}, | |
74 | {"egu_tx_uni_pkt", | |
75 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)}, | |
76 | {"egu_tx_multi_pkt", | |
77 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)}, | |
78 | {"egu_tx_broad_pkt", | |
79 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)}, | |
80 | {"ssu_ppp_mac_key_num", | |
81 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)}, | |
82 | {"ssu_ppp_host_key_num", | |
83 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)}, | |
84 | {"ppp_ssu_mac_rlt_num", | |
85 | HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)}, | |
86 | {"ppp_ssu_host_rlt_num", | |
87 | HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)}, | |
88 | {"ssu_tx_in_num", | |
89 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)}, | |
90 | {"ssu_tx_out_num", | |
91 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)}, | |
92 | {"ssu_rx_in_num", | |
93 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)}, | |
94 | {"ssu_rx_out_num", | |
95 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)} | |
96 | }; | |
97 | ||
98 | static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = { | |
99 | {"igu_rx_err_pkt", | |
100 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)}, | |
101 | {"igu_rx_no_eof_pkt", | |
102 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)}, | |
103 | {"igu_rx_no_sof_pkt", | |
104 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)}, | |
105 | {"egu_tx_1588_pkt", | |
106 | HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)}, | |
107 | {"ssu_full_drop_num", | |
108 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)}, | |
109 | {"ssu_part_drop_num", | |
110 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)}, | |
111 | {"ppp_key_drop_num", | |
112 | HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)}, | |
113 | {"ppp_rlt_drop_num", | |
114 | HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)}, | |
115 | {"ssu_key_drop_num", | |
116 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)}, | |
117 | {"pkt_curr_buf_cnt", | |
118 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)}, | |
119 | {"qcn_fb_rcv_cnt", | |
120 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)}, | |
121 | {"qcn_fb_drop_cnt", | |
122 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)}, | |
123 | {"qcn_fb_invaild_cnt", | |
124 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)}, | |
125 | {"rx_packet_tc0_in_cnt", | |
126 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)}, | |
127 | {"rx_packet_tc1_in_cnt", | |
128 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)}, | |
129 | {"rx_packet_tc2_in_cnt", | |
130 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)}, | |
131 | {"rx_packet_tc3_in_cnt", | |
132 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)}, | |
133 | {"rx_packet_tc4_in_cnt", | |
134 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)}, | |
135 | {"rx_packet_tc5_in_cnt", | |
136 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)}, | |
137 | {"rx_packet_tc6_in_cnt", | |
138 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)}, | |
139 | {"rx_packet_tc7_in_cnt", | |
140 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)}, | |
141 | {"rx_packet_tc0_out_cnt", | |
142 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)}, | |
143 | {"rx_packet_tc1_out_cnt", | |
144 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)}, | |
145 | {"rx_packet_tc2_out_cnt", | |
146 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)}, | |
147 | {"rx_packet_tc3_out_cnt", | |
148 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)}, | |
149 | {"rx_packet_tc4_out_cnt", | |
150 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)}, | |
151 | {"rx_packet_tc5_out_cnt", | |
152 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)}, | |
153 | {"rx_packet_tc6_out_cnt", | |
154 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)}, | |
155 | {"rx_packet_tc7_out_cnt", | |
156 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)}, | |
157 | {"tx_packet_tc0_in_cnt", | |
158 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)}, | |
159 | {"tx_packet_tc1_in_cnt", | |
160 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)}, | |
161 | {"tx_packet_tc2_in_cnt", | |
162 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)}, | |
163 | {"tx_packet_tc3_in_cnt", | |
164 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)}, | |
165 | {"tx_packet_tc4_in_cnt", | |
166 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)}, | |
167 | {"tx_packet_tc5_in_cnt", | |
168 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)}, | |
169 | {"tx_packet_tc6_in_cnt", | |
170 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)}, | |
171 | {"tx_packet_tc7_in_cnt", | |
172 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)}, | |
173 | {"tx_packet_tc0_out_cnt", | |
174 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)}, | |
175 | {"tx_packet_tc1_out_cnt", | |
176 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)}, | |
177 | {"tx_packet_tc2_out_cnt", | |
178 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)}, | |
179 | {"tx_packet_tc3_out_cnt", | |
180 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)}, | |
181 | {"tx_packet_tc4_out_cnt", | |
182 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)}, | |
183 | {"tx_packet_tc5_out_cnt", | |
184 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)}, | |
185 | {"tx_packet_tc6_out_cnt", | |
186 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)}, | |
187 | {"tx_packet_tc7_out_cnt", | |
188 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)}, | |
189 | {"pkt_curr_buf_tc0_cnt", | |
190 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)}, | |
191 | {"pkt_curr_buf_tc1_cnt", | |
192 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)}, | |
193 | {"pkt_curr_buf_tc2_cnt", | |
194 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)}, | |
195 | {"pkt_curr_buf_tc3_cnt", | |
196 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)}, | |
197 | {"pkt_curr_buf_tc4_cnt", | |
198 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)}, | |
199 | {"pkt_curr_buf_tc5_cnt", | |
200 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)}, | |
201 | {"pkt_curr_buf_tc6_cnt", | |
202 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)}, | |
203 | {"pkt_curr_buf_tc7_cnt", | |
204 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)}, | |
205 | {"mb_uncopy_num", | |
206 | HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)}, | |
207 | {"lo_pri_unicast_rlt_drop_num", | |
208 | HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)}, | |
209 | {"hi_pri_multicast_rlt_drop_num", | |
210 | HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)}, | |
211 | {"lo_pri_multicast_rlt_drop_num", | |
212 | HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)}, | |
213 | {"rx_oq_drop_pkt_cnt", | |
214 | HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)}, | |
215 | {"tx_oq_drop_pkt_cnt", | |
216 | HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)}, | |
217 | {"nic_l2_err_drop_pkt_cnt", | |
218 | HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)}, | |
219 | {"roc_l2_err_drop_pkt_cnt", | |
220 | HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)} | |
221 | }; | |
222 | ||
223 | static const struct hclge_comm_stats_str g_mac_stats_string[] = { | |
224 | {"mac_tx_mac_pause_num", | |
225 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, | |
226 | {"mac_rx_mac_pause_num", | |
227 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, | |
228 | {"mac_tx_pfc_pri0_pkt_num", | |
229 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, | |
230 | {"mac_tx_pfc_pri1_pkt_num", | |
231 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, | |
232 | {"mac_tx_pfc_pri2_pkt_num", | |
233 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, | |
234 | {"mac_tx_pfc_pri3_pkt_num", | |
235 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, | |
236 | {"mac_tx_pfc_pri4_pkt_num", | |
237 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, | |
238 | {"mac_tx_pfc_pri5_pkt_num", | |
239 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, | |
240 | {"mac_tx_pfc_pri6_pkt_num", | |
241 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, | |
242 | {"mac_tx_pfc_pri7_pkt_num", | |
243 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, | |
244 | {"mac_rx_pfc_pri0_pkt_num", | |
245 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, | |
246 | {"mac_rx_pfc_pri1_pkt_num", | |
247 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, | |
248 | {"mac_rx_pfc_pri2_pkt_num", | |
249 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, | |
250 | {"mac_rx_pfc_pri3_pkt_num", | |
251 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, | |
252 | {"mac_rx_pfc_pri4_pkt_num", | |
253 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, | |
254 | {"mac_rx_pfc_pri5_pkt_num", | |
255 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, | |
256 | {"mac_rx_pfc_pri6_pkt_num", | |
257 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, | |
258 | {"mac_rx_pfc_pri7_pkt_num", | |
259 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, | |
260 | {"mac_tx_total_pkt_num", | |
261 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, | |
262 | {"mac_tx_total_oct_num", | |
263 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, | |
264 | {"mac_tx_good_pkt_num", | |
265 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, | |
266 | {"mac_tx_bad_pkt_num", | |
267 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, | |
268 | {"mac_tx_good_oct_num", | |
269 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, | |
270 | {"mac_tx_bad_oct_num", | |
271 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, | |
272 | {"mac_tx_uni_pkt_num", | |
273 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, | |
274 | {"mac_tx_multi_pkt_num", | |
275 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, | |
276 | {"mac_tx_broad_pkt_num", | |
277 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, | |
278 | {"mac_tx_undersize_pkt_num", | |
279 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, | |
200a88c6 JS |
280 | {"mac_tx_oversize_pkt_num", |
281 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, | |
46a3df9f S |
282 | {"mac_tx_64_oct_pkt_num", |
283 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, | |
284 | {"mac_tx_65_127_oct_pkt_num", | |
285 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, | |
286 | {"mac_tx_128_255_oct_pkt_num", | |
287 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, | |
288 | {"mac_tx_256_511_oct_pkt_num", | |
289 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, | |
290 | {"mac_tx_512_1023_oct_pkt_num", | |
291 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, | |
292 | {"mac_tx_1024_1518_oct_pkt_num", | |
293 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, | |
91f384f6 JS |
294 | {"mac_tx_1519_2047_oct_pkt_num", |
295 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, | |
296 | {"mac_tx_2048_4095_oct_pkt_num", | |
297 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, | |
298 | {"mac_tx_4096_8191_oct_pkt_num", | |
299 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, | |
91f384f6 JS |
300 | {"mac_tx_8192_9216_oct_pkt_num", |
301 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, | |
302 | {"mac_tx_9217_12287_oct_pkt_num", | |
303 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, | |
304 | {"mac_tx_12288_16383_oct_pkt_num", | |
305 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, | |
306 | {"mac_tx_1519_max_good_pkt_num", | |
307 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, | |
308 | {"mac_tx_1519_max_bad_pkt_num", | |
309 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, | |
46a3df9f S |
310 | {"mac_rx_total_pkt_num", |
311 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, | |
312 | {"mac_rx_total_oct_num", | |
313 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, | |
314 | {"mac_rx_good_pkt_num", | |
315 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, | |
316 | {"mac_rx_bad_pkt_num", | |
317 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, | |
318 | {"mac_rx_good_oct_num", | |
319 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, | |
320 | {"mac_rx_bad_oct_num", | |
321 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, | |
322 | {"mac_rx_uni_pkt_num", | |
323 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, | |
324 | {"mac_rx_multi_pkt_num", | |
325 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, | |
326 | {"mac_rx_broad_pkt_num", | |
327 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, | |
328 | {"mac_rx_undersize_pkt_num", | |
329 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, | |
200a88c6 JS |
330 | {"mac_rx_oversize_pkt_num", |
331 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, | |
46a3df9f S |
332 | {"mac_rx_64_oct_pkt_num", |
333 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, | |
334 | {"mac_rx_65_127_oct_pkt_num", | |
335 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, | |
336 | {"mac_rx_128_255_oct_pkt_num", | |
337 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, | |
338 | {"mac_rx_256_511_oct_pkt_num", | |
339 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, | |
340 | {"mac_rx_512_1023_oct_pkt_num", | |
341 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, | |
342 | {"mac_rx_1024_1518_oct_pkt_num", | |
343 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, | |
91f384f6 JS |
344 | {"mac_rx_1519_2047_oct_pkt_num", |
345 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, | |
346 | {"mac_rx_2048_4095_oct_pkt_num", | |
347 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, | |
348 | {"mac_rx_4096_8191_oct_pkt_num", | |
349 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, | |
91f384f6 JS |
350 | {"mac_rx_8192_9216_oct_pkt_num", |
351 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, | |
352 | {"mac_rx_9217_12287_oct_pkt_num", | |
353 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, | |
354 | {"mac_rx_12288_16383_oct_pkt_num", | |
355 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, | |
356 | {"mac_rx_1519_max_good_pkt_num", | |
357 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, | |
358 | {"mac_rx_1519_max_bad_pkt_num", | |
359 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, | |
46a3df9f | 360 | |
a6c51c26 JS |
361 | {"mac_tx_fragment_pkt_num", |
362 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, | |
363 | {"mac_tx_undermin_pkt_num", | |
364 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, | |
365 | {"mac_tx_jabber_pkt_num", | |
366 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, | |
367 | {"mac_tx_err_all_pkt_num", | |
368 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, | |
369 | {"mac_tx_from_app_good_pkt_num", | |
370 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, | |
371 | {"mac_tx_from_app_bad_pkt_num", | |
372 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, | |
373 | {"mac_rx_fragment_pkt_num", | |
374 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, | |
375 | {"mac_rx_undermin_pkt_num", | |
376 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, | |
377 | {"mac_rx_jabber_pkt_num", | |
378 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, | |
379 | {"mac_rx_fcs_err_pkt_num", | |
380 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, | |
381 | {"mac_rx_send_app_good_pkt_num", | |
382 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, | |
383 | {"mac_rx_send_app_bad_pkt_num", | |
384 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} | |
46a3df9f S |
385 | }; |
386 | ||
f5aac71c FL |
387 | static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { |
388 | { | |
389 | .flags = HCLGE_MAC_MGR_MASK_VLAN_B, | |
390 | .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), | |
391 | .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), | |
392 | .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), | |
393 | .i_port_bitmap = 0x1, | |
394 | }, | |
395 | }; | |
396 | ||
46a3df9f S |
397 | static int hclge_64_bit_update_stats(struct hclge_dev *hdev) |
398 | { | |
399 | #define HCLGE_64_BIT_CMD_NUM 5 | |
400 | #define HCLGE_64_BIT_RTN_DATANUM 4 | |
401 | u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats); | |
402 | struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM]; | |
a90bb9a5 | 403 | __le64 *desc_data; |
46a3df9f S |
404 | int i, k, n; |
405 | int ret; | |
406 | ||
407 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true); | |
408 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM); | |
409 | if (ret) { | |
410 | dev_err(&hdev->pdev->dev, | |
411 | "Get 64 bit pkt stats fail, status = %d.\n", ret); | |
412 | return ret; | |
413 | } | |
414 | ||
415 | for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) { | |
416 | if (unlikely(i == 0)) { | |
a90bb9a5 | 417 | desc_data = (__le64 *)(&desc[i].data[0]); |
46a3df9f S |
418 | n = HCLGE_64_BIT_RTN_DATANUM - 1; |
419 | } else { | |
a90bb9a5 | 420 | desc_data = (__le64 *)(&desc[i]); |
46a3df9f S |
421 | n = HCLGE_64_BIT_RTN_DATANUM; |
422 | } | |
423 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 424 | *data++ += le64_to_cpu(*desc_data); |
46a3df9f S |
425 | desc_data++; |
426 | } | |
427 | } | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
432 | static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats) | |
433 | { | |
434 | stats->pkt_curr_buf_cnt = 0; | |
435 | stats->pkt_curr_buf_tc0_cnt = 0; | |
436 | stats->pkt_curr_buf_tc1_cnt = 0; | |
437 | stats->pkt_curr_buf_tc2_cnt = 0; | |
438 | stats->pkt_curr_buf_tc3_cnt = 0; | |
439 | stats->pkt_curr_buf_tc4_cnt = 0; | |
440 | stats->pkt_curr_buf_tc5_cnt = 0; | |
441 | stats->pkt_curr_buf_tc6_cnt = 0; | |
442 | stats->pkt_curr_buf_tc7_cnt = 0; | |
443 | } | |
444 | ||
445 | static int hclge_32_bit_update_stats(struct hclge_dev *hdev) | |
446 | { | |
447 | #define HCLGE_32_BIT_CMD_NUM 8 | |
448 | #define HCLGE_32_BIT_RTN_DATANUM 8 | |
449 | ||
450 | struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM]; | |
451 | struct hclge_32_bit_stats *all_32_bit_stats; | |
a90bb9a5 | 452 | __le32 *desc_data; |
46a3df9f S |
453 | int i, k, n; |
454 | u64 *data; | |
455 | int ret; | |
456 | ||
457 | all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats; | |
458 | data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt); | |
459 | ||
460 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true); | |
461 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM); | |
462 | if (ret) { | |
463 | dev_err(&hdev->pdev->dev, | |
464 | "Get 32 bit pkt stats fail, status = %d.\n", ret); | |
465 | ||
466 | return ret; | |
467 | } | |
468 | ||
469 | hclge_reset_partial_32bit_counter(all_32_bit_stats); | |
470 | for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) { | |
471 | if (unlikely(i == 0)) { | |
a90bb9a5 YL |
472 | __le16 *desc_data_16bit; |
473 | ||
46a3df9f | 474 | all_32_bit_stats->igu_rx_err_pkt += |
a90bb9a5 YL |
475 | le32_to_cpu(desc[i].data[0]); |
476 | ||
477 | desc_data_16bit = (__le16 *)&desc[i].data[1]; | |
46a3df9f | 478 | all_32_bit_stats->igu_rx_no_eof_pkt += |
a90bb9a5 YL |
479 | le16_to_cpu(*desc_data_16bit); |
480 | ||
481 | desc_data_16bit++; | |
46a3df9f | 482 | all_32_bit_stats->igu_rx_no_sof_pkt += |
a90bb9a5 | 483 | le16_to_cpu(*desc_data_16bit); |
46a3df9f | 484 | |
a90bb9a5 | 485 | desc_data = &desc[i].data[2]; |
46a3df9f S |
486 | n = HCLGE_32_BIT_RTN_DATANUM - 4; |
487 | } else { | |
a90bb9a5 | 488 | desc_data = (__le32 *)&desc[i]; |
46a3df9f S |
489 | n = HCLGE_32_BIT_RTN_DATANUM; |
490 | } | |
491 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 492 | *data++ += le32_to_cpu(*desc_data); |
46a3df9f S |
493 | desc_data++; |
494 | } | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static int hclge_mac_update_stats(struct hclge_dev *hdev) | |
501 | { | |
91f384f6 | 502 | #define HCLGE_MAC_CMD_NUM 21 |
46a3df9f S |
503 | #define HCLGE_RTN_DATA_NUM 4 |
504 | ||
505 | u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); | |
506 | struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; | |
a90bb9a5 | 507 | __le64 *desc_data; |
46a3df9f S |
508 | int i, k, n; |
509 | int ret; | |
510 | ||
511 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); | |
512 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); | |
513 | if (ret) { | |
514 | dev_err(&hdev->pdev->dev, | |
515 | "Get MAC pkt stats fail, status = %d.\n", ret); | |
516 | ||
517 | return ret; | |
518 | } | |
519 | ||
520 | for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { | |
521 | if (unlikely(i == 0)) { | |
a90bb9a5 | 522 | desc_data = (__le64 *)(&desc[i].data[0]); |
46a3df9f S |
523 | n = HCLGE_RTN_DATA_NUM - 2; |
524 | } else { | |
a90bb9a5 | 525 | desc_data = (__le64 *)(&desc[i]); |
46a3df9f S |
526 | n = HCLGE_RTN_DATA_NUM; |
527 | } | |
528 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 529 | *data++ += le64_to_cpu(*desc_data); |
46a3df9f S |
530 | desc_data++; |
531 | } | |
532 | } | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | static int hclge_tqps_update_stats(struct hnae3_handle *handle) | |
538 | { | |
539 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
540 | struct hclge_vport *vport = hclge_get_vport(handle); | |
541 | struct hclge_dev *hdev = vport->back; | |
542 | struct hnae3_queue *queue; | |
543 | struct hclge_desc desc[1]; | |
544 | struct hclge_tqp *tqp; | |
545 | int ret, i; | |
546 | ||
547 | for (i = 0; i < kinfo->num_tqps; i++) { | |
548 | queue = handle->kinfo.tqp[i]; | |
549 | tqp = container_of(queue, struct hclge_tqp, q); | |
550 | /* command : HCLGE_OPC_QUERY_IGU_STAT */ | |
551 | hclge_cmd_setup_basic_desc(&desc[0], | |
552 | HCLGE_OPC_QUERY_RX_STATUS, | |
553 | true); | |
554 | ||
a90bb9a5 | 555 | desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); |
46a3df9f S |
556 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
557 | if (ret) { | |
558 | dev_err(&hdev->pdev->dev, | |
559 | "Query tqp stat fail, status = %d,queue = %d\n", | |
560 | ret, i); | |
561 | return ret; | |
562 | } | |
563 | tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += | |
cf72fa63 | 564 | le32_to_cpu(desc[0].data[1]); |
46a3df9f S |
565 | } |
566 | ||
567 | for (i = 0; i < kinfo->num_tqps; i++) { | |
568 | queue = handle->kinfo.tqp[i]; | |
569 | tqp = container_of(queue, struct hclge_tqp, q); | |
570 | /* command : HCLGE_OPC_QUERY_IGU_STAT */ | |
571 | hclge_cmd_setup_basic_desc(&desc[0], | |
572 | HCLGE_OPC_QUERY_TX_STATUS, | |
573 | true); | |
574 | ||
a90bb9a5 | 575 | desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); |
46a3df9f S |
576 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
577 | if (ret) { | |
578 | dev_err(&hdev->pdev->dev, | |
579 | "Query tqp stat fail, status = %d,queue = %d\n", | |
580 | ret, i); | |
581 | return ret; | |
582 | } | |
583 | tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += | |
cf72fa63 | 584 | le32_to_cpu(desc[0].data[1]); |
46a3df9f S |
585 | } |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) | |
591 | { | |
592 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
593 | struct hclge_tqp *tqp; | |
594 | u64 *buff = data; | |
595 | int i; | |
596 | ||
597 | for (i = 0; i < kinfo->num_tqps; i++) { | |
598 | tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
a90bb9a5 | 599 | *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; |
46a3df9f S |
600 | } |
601 | ||
602 | for (i = 0; i < kinfo->num_tqps; i++) { | |
603 | tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
a90bb9a5 | 604 | *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; |
46a3df9f S |
605 | } |
606 | ||
607 | return buff; | |
608 | } | |
609 | ||
610 | static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) | |
611 | { | |
612 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
613 | ||
614 | return kinfo->num_tqps * (2); | |
615 | } | |
616 | ||
617 | static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) | |
618 | { | |
619 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
620 | u8 *buff = data; | |
621 | int i = 0; | |
622 | ||
623 | for (i = 0; i < kinfo->num_tqps; i++) { | |
624 | struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], | |
625 | struct hclge_tqp, q); | |
a6c51c26 | 626 | snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", |
46a3df9f S |
627 | tqp->index); |
628 | buff = buff + ETH_GSTRING_LEN; | |
629 | } | |
630 | ||
631 | for (i = 0; i < kinfo->num_tqps; i++) { | |
632 | struct hclge_tqp *tqp = container_of(kinfo->tqp[i], | |
633 | struct hclge_tqp, q); | |
a6c51c26 | 634 | snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", |
46a3df9f S |
635 | tqp->index); |
636 | buff = buff + ETH_GSTRING_LEN; | |
637 | } | |
638 | ||
639 | return buff; | |
640 | } | |
641 | ||
642 | static u64 *hclge_comm_get_stats(void *comm_stats, | |
643 | const struct hclge_comm_stats_str strs[], | |
644 | int size, u64 *data) | |
645 | { | |
646 | u64 *buf = data; | |
647 | u32 i; | |
648 | ||
649 | for (i = 0; i < size; i++) | |
650 | buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); | |
651 | ||
652 | return buf + size; | |
653 | } | |
654 | ||
655 | static u8 *hclge_comm_get_strings(u32 stringset, | |
656 | const struct hclge_comm_stats_str strs[], | |
657 | int size, u8 *data) | |
658 | { | |
659 | char *buff = (char *)data; | |
660 | u32 i; | |
661 | ||
662 | if (stringset != ETH_SS_STATS) | |
663 | return buff; | |
664 | ||
665 | for (i = 0; i < size; i++) { | |
666 | snprintf(buff, ETH_GSTRING_LEN, | |
667 | strs[i].desc); | |
668 | buff = buff + ETH_GSTRING_LEN; | |
669 | } | |
670 | ||
671 | return (u8 *)buff; | |
672 | } | |
673 | ||
674 | static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, | |
675 | struct net_device_stats *net_stats) | |
676 | { | |
677 | net_stats->tx_dropped = 0; | |
678 | net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num; | |
679 | net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num; | |
680 | net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num; | |
681 | ||
200a88c6 | 682 | net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f | 683 | net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; |
46a3df9f S |
684 | net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt; |
685 | net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt; | |
a6c51c26 | 686 | net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; |
46a3df9f S |
687 | |
688 | net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; | |
689 | net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; | |
690 | ||
a6c51c26 | 691 | net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; |
46a3df9f S |
692 | net_stats->rx_length_errors = |
693 | hw_stats->mac_stats.mac_rx_undersize_pkt_num; | |
694 | net_stats->rx_length_errors += | |
200a88c6 | 695 | hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f | 696 | net_stats->rx_over_errors = |
200a88c6 | 697 | hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f S |
698 | } |
699 | ||
700 | static void hclge_update_stats_for_all(struct hclge_dev *hdev) | |
701 | { | |
702 | struct hnae3_handle *handle; | |
703 | int status; | |
704 | ||
705 | handle = &hdev->vport[0].nic; | |
706 | if (handle->client) { | |
707 | status = hclge_tqps_update_stats(handle); | |
708 | if (status) { | |
709 | dev_err(&hdev->pdev->dev, | |
710 | "Update TQPS stats fail, status = %d.\n", | |
711 | status); | |
712 | } | |
713 | } | |
714 | ||
715 | status = hclge_mac_update_stats(hdev); | |
716 | if (status) | |
717 | dev_err(&hdev->pdev->dev, | |
718 | "Update MAC stats fail, status = %d.\n", status); | |
719 | ||
720 | status = hclge_32_bit_update_stats(hdev); | |
721 | if (status) | |
722 | dev_err(&hdev->pdev->dev, | |
723 | "Update 32 bit stats fail, status = %d.\n", | |
724 | status); | |
725 | ||
726 | hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); | |
727 | } | |
728 | ||
729 | static void hclge_update_stats(struct hnae3_handle *handle, | |
730 | struct net_device_stats *net_stats) | |
731 | { | |
732 | struct hclge_vport *vport = hclge_get_vport(handle); | |
733 | struct hclge_dev *hdev = vport->back; | |
734 | struct hclge_hw_stats *hw_stats = &hdev->hw_stats; | |
735 | int status; | |
736 | ||
c5f65480 JS |
737 | if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) |
738 | return; | |
739 | ||
46a3df9f S |
740 | status = hclge_mac_update_stats(hdev); |
741 | if (status) | |
742 | dev_err(&hdev->pdev->dev, | |
743 | "Update MAC stats fail, status = %d.\n", | |
744 | status); | |
745 | ||
746 | status = hclge_32_bit_update_stats(hdev); | |
747 | if (status) | |
748 | dev_err(&hdev->pdev->dev, | |
749 | "Update 32 bit stats fail, status = %d.\n", | |
750 | status); | |
751 | ||
752 | status = hclge_64_bit_update_stats(hdev); | |
753 | if (status) | |
754 | dev_err(&hdev->pdev->dev, | |
755 | "Update 64 bit stats fail, status = %d.\n", | |
756 | status); | |
757 | ||
758 | status = hclge_tqps_update_stats(handle); | |
759 | if (status) | |
760 | dev_err(&hdev->pdev->dev, | |
761 | "Update TQPS stats fail, status = %d.\n", | |
762 | status); | |
763 | ||
764 | hclge_update_netstat(hw_stats, net_stats); | |
c5f65480 JS |
765 | |
766 | clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); | |
46a3df9f S |
767 | } |
768 | ||
769 | static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) | |
770 | { | |
771 | #define HCLGE_LOOPBACK_TEST_FLAGS 0x7 | |
772 | ||
773 | struct hclge_vport *vport = hclge_get_vport(handle); | |
774 | struct hclge_dev *hdev = vport->back; | |
775 | int count = 0; | |
776 | ||
777 | /* Loopback test support rules: | |
778 | * mac: only GE mode support | |
779 | * serdes: all mac mode will support include GE/XGE/LGE/CGE | |
780 | * phy: only support when phy device exist on board | |
781 | */ | |
782 | if (stringset == ETH_SS_TEST) { | |
783 | /* clear loopback bit flags at first */ | |
784 | handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); | |
785 | if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || | |
786 | hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || | |
787 | hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { | |
788 | count += 1; | |
789 | handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; | |
46a3df9f | 790 | } |
5fd50ac3 PL |
791 | |
792 | count++; | |
793 | handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK; | |
46a3df9f S |
794 | } else if (stringset == ETH_SS_STATS) { |
795 | count = ARRAY_SIZE(g_mac_stats_string) + | |
796 | ARRAY_SIZE(g_all_32bit_stats_string) + | |
797 | ARRAY_SIZE(g_all_64bit_stats_string) + | |
798 | hclge_tqps_get_sset_count(handle, stringset); | |
799 | } | |
800 | ||
801 | return count; | |
802 | } | |
803 | ||
804 | static void hclge_get_strings(struct hnae3_handle *handle, | |
805 | u32 stringset, | |
806 | u8 *data) | |
807 | { | |
808 | u8 *p = (char *)data; | |
809 | int size; | |
810 | ||
811 | if (stringset == ETH_SS_STATS) { | |
812 | size = ARRAY_SIZE(g_mac_stats_string); | |
813 | p = hclge_comm_get_strings(stringset, | |
814 | g_mac_stats_string, | |
815 | size, | |
816 | p); | |
817 | size = ARRAY_SIZE(g_all_32bit_stats_string); | |
818 | p = hclge_comm_get_strings(stringset, | |
819 | g_all_32bit_stats_string, | |
820 | size, | |
821 | p); | |
822 | size = ARRAY_SIZE(g_all_64bit_stats_string); | |
823 | p = hclge_comm_get_strings(stringset, | |
824 | g_all_64bit_stats_string, | |
825 | size, | |
826 | p); | |
827 | p = hclge_tqps_get_strings(handle, p); | |
828 | } else if (stringset == ETH_SS_TEST) { | |
829 | if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { | |
830 | memcpy(p, | |
831 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], | |
832 | ETH_GSTRING_LEN); | |
833 | p += ETH_GSTRING_LEN; | |
834 | } | |
835 | if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { | |
836 | memcpy(p, | |
837 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], | |
838 | ETH_GSTRING_LEN); | |
839 | p += ETH_GSTRING_LEN; | |
840 | } | |
841 | if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { | |
842 | memcpy(p, | |
843 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], | |
844 | ETH_GSTRING_LEN); | |
845 | p += ETH_GSTRING_LEN; | |
846 | } | |
847 | } | |
848 | } | |
849 | ||
850 | static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) | |
851 | { | |
852 | struct hclge_vport *vport = hclge_get_vport(handle); | |
853 | struct hclge_dev *hdev = vport->back; | |
854 | u64 *p; | |
855 | ||
856 | p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, | |
857 | g_mac_stats_string, | |
858 | ARRAY_SIZE(g_mac_stats_string), | |
859 | data); | |
860 | p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats, | |
861 | g_all_32bit_stats_string, | |
862 | ARRAY_SIZE(g_all_32bit_stats_string), | |
863 | p); | |
864 | p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats, | |
865 | g_all_64bit_stats_string, | |
866 | ARRAY_SIZE(g_all_64bit_stats_string), | |
867 | p); | |
868 | p = hclge_tqps_get_stats(handle, p); | |
869 | } | |
870 | ||
871 | static int hclge_parse_func_status(struct hclge_dev *hdev, | |
d44f9b63 | 872 | struct hclge_func_status_cmd *status) |
46a3df9f S |
873 | { |
874 | if (!(status->pf_state & HCLGE_PF_STATE_DONE)) | |
875 | return -EINVAL; | |
876 | ||
877 | /* Set the pf to main pf */ | |
878 | if (status->pf_state & HCLGE_PF_STATE_MAIN) | |
879 | hdev->flag |= HCLGE_FLAG_MAIN; | |
880 | else | |
881 | hdev->flag &= ~HCLGE_FLAG_MAIN; | |
882 | ||
46a3df9f S |
883 | return 0; |
884 | } | |
885 | ||
886 | static int hclge_query_function_status(struct hclge_dev *hdev) | |
887 | { | |
d44f9b63 | 888 | struct hclge_func_status_cmd *req; |
46a3df9f S |
889 | struct hclge_desc desc; |
890 | int timeout = 0; | |
891 | int ret; | |
892 | ||
893 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); | |
d44f9b63 | 894 | req = (struct hclge_func_status_cmd *)desc.data; |
46a3df9f S |
895 | |
896 | do { | |
897 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
898 | if (ret) { | |
899 | dev_err(&hdev->pdev->dev, | |
900 | "query function status failed %d.\n", | |
901 | ret); | |
902 | ||
903 | return ret; | |
904 | } | |
905 | ||
906 | /* Check pf reset is done */ | |
907 | if (req->pf_state) | |
908 | break; | |
909 | usleep_range(1000, 2000); | |
910 | } while (timeout++ < 5); | |
911 | ||
912 | ret = hclge_parse_func_status(hdev, req); | |
913 | ||
914 | return ret; | |
915 | } | |
916 | ||
917 | static int hclge_query_pf_resource(struct hclge_dev *hdev) | |
918 | { | |
d44f9b63 | 919 | struct hclge_pf_res_cmd *req; |
46a3df9f S |
920 | struct hclge_desc desc; |
921 | int ret; | |
922 | ||
923 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); | |
924 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
925 | if (ret) { | |
926 | dev_err(&hdev->pdev->dev, | |
927 | "query pf resource failed %d.\n", ret); | |
928 | return ret; | |
929 | } | |
930 | ||
d44f9b63 | 931 | req = (struct hclge_pf_res_cmd *)desc.data; |
46a3df9f S |
932 | hdev->num_tqps = __le16_to_cpu(req->tqp_num); |
933 | hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; | |
934 | ||
e92a0843 | 935 | if (hnae3_dev_roce_supported(hdev)) { |
375dd5e4 JS |
936 | hdev->roce_base_msix_offset = |
937 | hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), | |
938 | HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S); | |
887c3820 | 939 | hdev->num_roce_msi = |
e4e87715 PL |
940 | hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), |
941 | HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); | |
46a3df9f S |
942 | |
943 | /* PF should have NIC vectors and Roce vectors, | |
944 | * NIC vectors are queued before Roce vectors. | |
945 | */ | |
375dd5e4 JS |
946 | hdev->num_msi = hdev->num_roce_msi + |
947 | hdev->roce_base_msix_offset; | |
46a3df9f S |
948 | } else { |
949 | hdev->num_msi = | |
e4e87715 PL |
950 | hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), |
951 | HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); | |
46a3df9f S |
952 | } |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
957 | static int hclge_parse_speed(int speed_cmd, int *speed) | |
958 | { | |
959 | switch (speed_cmd) { | |
960 | case 6: | |
961 | *speed = HCLGE_MAC_SPEED_10M; | |
962 | break; | |
963 | case 7: | |
964 | *speed = HCLGE_MAC_SPEED_100M; | |
965 | break; | |
966 | case 0: | |
967 | *speed = HCLGE_MAC_SPEED_1G; | |
968 | break; | |
969 | case 1: | |
970 | *speed = HCLGE_MAC_SPEED_10G; | |
971 | break; | |
972 | case 2: | |
973 | *speed = HCLGE_MAC_SPEED_25G; | |
974 | break; | |
975 | case 3: | |
976 | *speed = HCLGE_MAC_SPEED_40G; | |
977 | break; | |
978 | case 4: | |
979 | *speed = HCLGE_MAC_SPEED_50G; | |
980 | break; | |
981 | case 5: | |
982 | *speed = HCLGE_MAC_SPEED_100G; | |
983 | break; | |
984 | default: | |
985 | return -EINVAL; | |
986 | } | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
0979aa0b FL |
991 | static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, |
992 | u8 speed_ability) | |
993 | { | |
994 | unsigned long *supported = hdev->hw.mac.supported; | |
995 | ||
996 | if (speed_ability & HCLGE_SUPPORT_1G_BIT) | |
997 | set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, | |
998 | supported); | |
999 | ||
1000 | if (speed_ability & HCLGE_SUPPORT_10G_BIT) | |
1001 | set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, | |
1002 | supported); | |
1003 | ||
1004 | if (speed_ability & HCLGE_SUPPORT_25G_BIT) | |
1005 | set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, | |
1006 | supported); | |
1007 | ||
1008 | if (speed_ability & HCLGE_SUPPORT_50G_BIT) | |
1009 | set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, | |
1010 | supported); | |
1011 | ||
1012 | if (speed_ability & HCLGE_SUPPORT_100G_BIT) | |
1013 | set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, | |
1014 | supported); | |
1015 | ||
1016 | set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); | |
1017 | set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); | |
1018 | } | |
1019 | ||
1020 | static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability) | |
1021 | { | |
1022 | u8 media_type = hdev->hw.mac.media_type; | |
1023 | ||
1024 | if (media_type != HNAE3_MEDIA_TYPE_FIBER) | |
1025 | return; | |
1026 | ||
1027 | hclge_parse_fiber_link_mode(hdev, speed_ability); | |
1028 | } | |
1029 | ||
46a3df9f S |
1030 | static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) |
1031 | { | |
d44f9b63 | 1032 | struct hclge_cfg_param_cmd *req; |
46a3df9f S |
1033 | u64 mac_addr_tmp_high; |
1034 | u64 mac_addr_tmp; | |
1035 | int i; | |
1036 | ||
d44f9b63 | 1037 | req = (struct hclge_cfg_param_cmd *)desc[0].data; |
46a3df9f S |
1038 | |
1039 | /* get the configuration */ | |
e4e87715 PL |
1040 | cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]), |
1041 | HCLGE_CFG_VMDQ_M, | |
1042 | HCLGE_CFG_VMDQ_S); | |
1043 | cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), | |
1044 | HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); | |
1045 | cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), | |
1046 | HCLGE_CFG_TQP_DESC_N_M, | |
1047 | HCLGE_CFG_TQP_DESC_N_S); | |
1048 | ||
1049 | cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), | |
1050 | HCLGE_CFG_PHY_ADDR_M, | |
1051 | HCLGE_CFG_PHY_ADDR_S); | |
1052 | cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), | |
1053 | HCLGE_CFG_MEDIA_TP_M, | |
1054 | HCLGE_CFG_MEDIA_TP_S); | |
1055 | cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), | |
1056 | HCLGE_CFG_RX_BUF_LEN_M, | |
1057 | HCLGE_CFG_RX_BUF_LEN_S); | |
46a3df9f S |
1058 | /* get mac_address */ |
1059 | mac_addr_tmp = __le32_to_cpu(req->param[2]); | |
e4e87715 PL |
1060 | mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), |
1061 | HCLGE_CFG_MAC_ADDR_H_M, | |
1062 | HCLGE_CFG_MAC_ADDR_H_S); | |
46a3df9f S |
1063 | |
1064 | mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; | |
1065 | ||
e4e87715 PL |
1066 | cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), |
1067 | HCLGE_CFG_DEFAULT_SPEED_M, | |
1068 | HCLGE_CFG_DEFAULT_SPEED_S); | |
1069 | cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), | |
1070 | HCLGE_CFG_RSS_SIZE_M, | |
1071 | HCLGE_CFG_RSS_SIZE_S); | |
0e7a40cd | 1072 | |
46a3df9f S |
1073 | for (i = 0; i < ETH_ALEN; i++) |
1074 | cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; | |
1075 | ||
d44f9b63 | 1076 | req = (struct hclge_cfg_param_cmd *)desc[1].data; |
46a3df9f | 1077 | cfg->numa_node_map = __le32_to_cpu(req->param[0]); |
0979aa0b | 1078 | |
e4e87715 PL |
1079 | cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), |
1080 | HCLGE_CFG_SPEED_ABILITY_M, | |
1081 | HCLGE_CFG_SPEED_ABILITY_S); | |
46a3df9f S |
1082 | } |
1083 | ||
1084 | /* hclge_get_cfg: query the static parameter from flash | |
1085 | * @hdev: pointer to struct hclge_dev | |
1086 | * @hcfg: the config structure to be getted | |
1087 | */ | |
1088 | static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) | |
1089 | { | |
1090 | struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; | |
d44f9b63 | 1091 | struct hclge_cfg_param_cmd *req; |
46a3df9f S |
1092 | int i, ret; |
1093 | ||
1094 | for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { | |
a90bb9a5 YL |
1095 | u32 offset = 0; |
1096 | ||
d44f9b63 | 1097 | req = (struct hclge_cfg_param_cmd *)desc[i].data; |
46a3df9f S |
1098 | hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, |
1099 | true); | |
e4e87715 PL |
1100 | hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, |
1101 | HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); | |
46a3df9f | 1102 | /* Len should be united by 4 bytes when send to hardware */ |
e4e87715 PL |
1103 | hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, |
1104 | HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); | |
a90bb9a5 | 1105 | req->offset = cpu_to_le32(offset); |
46a3df9f S |
1106 | } |
1107 | ||
1108 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); | |
1109 | if (ret) { | |
3f639907 | 1110 | dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); |
46a3df9f S |
1111 | return ret; |
1112 | } | |
1113 | ||
1114 | hclge_parse_cfg(hcfg, desc); | |
3f639907 | 1115 | |
46a3df9f S |
1116 | return 0; |
1117 | } | |
1118 | ||
1119 | static int hclge_get_cap(struct hclge_dev *hdev) | |
1120 | { | |
1121 | int ret; | |
1122 | ||
1123 | ret = hclge_query_function_status(hdev); | |
1124 | if (ret) { | |
1125 | dev_err(&hdev->pdev->dev, | |
1126 | "query function status error %d.\n", ret); | |
1127 | return ret; | |
1128 | } | |
1129 | ||
1130 | /* get pf resource */ | |
1131 | ret = hclge_query_pf_resource(hdev); | |
3f639907 JS |
1132 | if (ret) |
1133 | dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret); | |
46a3df9f | 1134 | |
3f639907 | 1135 | return ret; |
46a3df9f S |
1136 | } |
1137 | ||
1138 | static int hclge_configure(struct hclge_dev *hdev) | |
1139 | { | |
1140 | struct hclge_cfg cfg; | |
1141 | int ret, i; | |
1142 | ||
1143 | ret = hclge_get_cfg(hdev, &cfg); | |
1144 | if (ret) { | |
1145 | dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); | |
1146 | return ret; | |
1147 | } | |
1148 | ||
1149 | hdev->num_vmdq_vport = cfg.vmdq_vport_num; | |
1150 | hdev->base_tqp_pid = 0; | |
0e7a40cd | 1151 | hdev->rss_size_max = cfg.rss_size_max; |
46a3df9f | 1152 | hdev->rx_buf_len = cfg.rx_buf_len; |
fbbb1536 | 1153 | ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); |
46a3df9f | 1154 | hdev->hw.mac.media_type = cfg.media_type; |
2a4776e1 | 1155 | hdev->hw.mac.phy_addr = cfg.phy_addr; |
46a3df9f S |
1156 | hdev->num_desc = cfg.tqp_desc_num; |
1157 | hdev->tm_info.num_pg = 1; | |
cacde272 | 1158 | hdev->tc_max = cfg.tc_num; |
46a3df9f S |
1159 | hdev->tm_info.hw_pfc_map = 0; |
1160 | ||
1161 | ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); | |
1162 | if (ret) { | |
1163 | dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); | |
1164 | return ret; | |
1165 | } | |
1166 | ||
0979aa0b FL |
1167 | hclge_parse_link_mode(hdev, cfg.speed_ability); |
1168 | ||
cacde272 YL |
1169 | if ((hdev->tc_max > HNAE3_MAX_TC) || |
1170 | (hdev->tc_max < 1)) { | |
46a3df9f | 1171 | dev_warn(&hdev->pdev->dev, "TC num = %d.\n", |
cacde272 YL |
1172 | hdev->tc_max); |
1173 | hdev->tc_max = 1; | |
46a3df9f S |
1174 | } |
1175 | ||
cacde272 YL |
1176 | /* Dev does not support DCB */ |
1177 | if (!hnae3_dev_dcb_supported(hdev)) { | |
1178 | hdev->tc_max = 1; | |
1179 | hdev->pfc_max = 0; | |
1180 | } else { | |
1181 | hdev->pfc_max = hdev->tc_max; | |
1182 | } | |
1183 | ||
1184 | hdev->tm_info.num_tc = hdev->tc_max; | |
1185 | ||
46a3df9f | 1186 | /* Currently not support uncontiuous tc */ |
cacde272 | 1187 | for (i = 0; i < hdev->tm_info.num_tc; i++) |
e4e87715 | 1188 | hnae3_set_bit(hdev->hw_tc_map, i, 1); |
46a3df9f | 1189 | |
71b83869 | 1190 | hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; |
46a3df9f S |
1191 | |
1192 | return ret; | |
1193 | } | |
1194 | ||
1195 | static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, | |
1196 | int tso_mss_max) | |
1197 | { | |
d44f9b63 | 1198 | struct hclge_cfg_tso_status_cmd *req; |
46a3df9f | 1199 | struct hclge_desc desc; |
a90bb9a5 | 1200 | u16 tso_mss; |
46a3df9f S |
1201 | |
1202 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); | |
1203 | ||
d44f9b63 | 1204 | req = (struct hclge_cfg_tso_status_cmd *)desc.data; |
a90bb9a5 YL |
1205 | |
1206 | tso_mss = 0; | |
e4e87715 PL |
1207 | hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, |
1208 | HCLGE_TSO_MSS_MIN_S, tso_mss_min); | |
a90bb9a5 YL |
1209 | req->tso_mss_min = cpu_to_le16(tso_mss); |
1210 | ||
1211 | tso_mss = 0; | |
e4e87715 PL |
1212 | hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, |
1213 | HCLGE_TSO_MSS_MIN_S, tso_mss_max); | |
a90bb9a5 | 1214 | req->tso_mss_max = cpu_to_le16(tso_mss); |
46a3df9f S |
1215 | |
1216 | return hclge_cmd_send(&hdev->hw, &desc, 1); | |
1217 | } | |
1218 | ||
1219 | static int hclge_alloc_tqps(struct hclge_dev *hdev) | |
1220 | { | |
1221 | struct hclge_tqp *tqp; | |
1222 | int i; | |
1223 | ||
1224 | hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, | |
1225 | sizeof(struct hclge_tqp), GFP_KERNEL); | |
1226 | if (!hdev->htqp) | |
1227 | return -ENOMEM; | |
1228 | ||
1229 | tqp = hdev->htqp; | |
1230 | ||
1231 | for (i = 0; i < hdev->num_tqps; i++) { | |
1232 | tqp->dev = &hdev->pdev->dev; | |
1233 | tqp->index = i; | |
1234 | ||
1235 | tqp->q.ae_algo = &ae_algo; | |
1236 | tqp->q.buf_size = hdev->rx_buf_len; | |
1237 | tqp->q.desc_num = hdev->num_desc; | |
1238 | tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + | |
1239 | i * HCLGE_TQP_REG_SIZE; | |
1240 | ||
1241 | tqp++; | |
1242 | } | |
1243 | ||
1244 | return 0; | |
1245 | } | |
1246 | ||
1247 | static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, | |
1248 | u16 tqp_pid, u16 tqp_vid, bool is_pf) | |
1249 | { | |
d44f9b63 | 1250 | struct hclge_tqp_map_cmd *req; |
46a3df9f S |
1251 | struct hclge_desc desc; |
1252 | int ret; | |
1253 | ||
1254 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); | |
1255 | ||
d44f9b63 | 1256 | req = (struct hclge_tqp_map_cmd *)desc.data; |
46a3df9f | 1257 | req->tqp_id = cpu_to_le16(tqp_pid); |
a90bb9a5 | 1258 | req->tqp_vf = func_id; |
46a3df9f S |
1259 | req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | |
1260 | 1 << HCLGE_TQP_MAP_EN_B; | |
1261 | req->tqp_vid = cpu_to_le16(tqp_vid); | |
1262 | ||
1263 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 JS |
1264 | if (ret) |
1265 | dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); | |
46a3df9f | 1266 | |
3f639907 | 1267 | return ret; |
46a3df9f S |
1268 | } |
1269 | ||
128b900d | 1270 | static int hclge_assign_tqp(struct hclge_vport *vport) |
46a3df9f | 1271 | { |
128b900d | 1272 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; |
46a3df9f | 1273 | struct hclge_dev *hdev = vport->back; |
7df7dad6 | 1274 | int i, alloced; |
46a3df9f S |
1275 | |
1276 | for (i = 0, alloced = 0; i < hdev->num_tqps && | |
128b900d | 1277 | alloced < kinfo->num_tqps; i++) { |
46a3df9f S |
1278 | if (!hdev->htqp[i].alloced) { |
1279 | hdev->htqp[i].q.handle = &vport->nic; | |
1280 | hdev->htqp[i].q.tqp_index = alloced; | |
128b900d YL |
1281 | hdev->htqp[i].q.desc_num = kinfo->num_desc; |
1282 | kinfo->tqp[alloced] = &hdev->htqp[i].q; | |
46a3df9f | 1283 | hdev->htqp[i].alloced = true; |
46a3df9f S |
1284 | alloced++; |
1285 | } | |
1286 | } | |
128b900d | 1287 | vport->alloc_tqps = kinfo->num_tqps; |
46a3df9f S |
1288 | |
1289 | return 0; | |
1290 | } | |
1291 | ||
128b900d YL |
1292 | static int hclge_knic_setup(struct hclge_vport *vport, |
1293 | u16 num_tqps, u16 num_desc) | |
46a3df9f S |
1294 | { |
1295 | struct hnae3_handle *nic = &vport->nic; | |
1296 | struct hnae3_knic_private_info *kinfo = &nic->kinfo; | |
1297 | struct hclge_dev *hdev = vport->back; | |
1298 | int i, ret; | |
1299 | ||
128b900d | 1300 | kinfo->num_desc = num_desc; |
46a3df9f S |
1301 | kinfo->rx_buf_len = hdev->rx_buf_len; |
1302 | kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); | |
1303 | kinfo->rss_size | |
1304 | = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); | |
1305 | kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; | |
1306 | ||
1307 | for (i = 0; i < HNAE3_MAX_TC; i++) { | |
1308 | if (hdev->hw_tc_map & BIT(i)) { | |
1309 | kinfo->tc_info[i].enable = true; | |
1310 | kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; | |
1311 | kinfo->tc_info[i].tqp_count = kinfo->rss_size; | |
1312 | kinfo->tc_info[i].tc = i; | |
1313 | } else { | |
1314 | /* Set to default queue if TC is disable */ | |
1315 | kinfo->tc_info[i].enable = false; | |
1316 | kinfo->tc_info[i].tqp_offset = 0; | |
1317 | kinfo->tc_info[i].tqp_count = 1; | |
1318 | kinfo->tc_info[i].tc = 0; | |
1319 | } | |
1320 | } | |
1321 | ||
1322 | kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, | |
1323 | sizeof(struct hnae3_queue *), GFP_KERNEL); | |
1324 | if (!kinfo->tqp) | |
1325 | return -ENOMEM; | |
1326 | ||
128b900d | 1327 | ret = hclge_assign_tqp(vport); |
3f639907 | 1328 | if (ret) |
46a3df9f | 1329 | dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); |
46a3df9f | 1330 | |
3f639907 | 1331 | return ret; |
46a3df9f S |
1332 | } |
1333 | ||
7df7dad6 L |
1334 | static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, |
1335 | struct hclge_vport *vport) | |
1336 | { | |
1337 | struct hnae3_handle *nic = &vport->nic; | |
1338 | struct hnae3_knic_private_info *kinfo; | |
1339 | u16 i; | |
1340 | ||
1341 | kinfo = &nic->kinfo; | |
1342 | for (i = 0; i < kinfo->num_tqps; i++) { | |
1343 | struct hclge_tqp *q = | |
1344 | container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
1345 | bool is_pf; | |
1346 | int ret; | |
1347 | ||
1348 | is_pf = !(vport->vport_id); | |
1349 | ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, | |
1350 | i, is_pf); | |
1351 | if (ret) | |
1352 | return ret; | |
1353 | } | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int hclge_map_tqp(struct hclge_dev *hdev) | |
1359 | { | |
1360 | struct hclge_vport *vport = hdev->vport; | |
1361 | u16 i, num_vport; | |
1362 | ||
1363 | num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; | |
1364 | for (i = 0; i < num_vport; i++) { | |
1365 | int ret; | |
1366 | ||
1367 | ret = hclge_map_tqp_to_vport(hdev, vport); | |
1368 | if (ret) | |
1369 | return ret; | |
1370 | ||
1371 | vport++; | |
1372 | } | |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
46a3df9f S |
1377 | static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) |
1378 | { | |
1379 | /* this would be initialized later */ | |
1380 | } | |
1381 | ||
1382 | static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) | |
1383 | { | |
1384 | struct hnae3_handle *nic = &vport->nic; | |
1385 | struct hclge_dev *hdev = vport->back; | |
1386 | int ret; | |
1387 | ||
1388 | nic->pdev = hdev->pdev; | |
1389 | nic->ae_algo = &ae_algo; | |
1390 | nic->numa_node_mask = hdev->numa_node_mask; | |
1391 | ||
1392 | if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { | |
128b900d | 1393 | ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc); |
46a3df9f S |
1394 | if (ret) { |
1395 | dev_err(&hdev->pdev->dev, "knic setup failed %d\n", | |
1396 | ret); | |
1397 | return ret; | |
1398 | } | |
1399 | } else { | |
1400 | hclge_unic_setup(vport, num_tqps); | |
1401 | } | |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | static int hclge_alloc_vport(struct hclge_dev *hdev) | |
1407 | { | |
1408 | struct pci_dev *pdev = hdev->pdev; | |
1409 | struct hclge_vport *vport; | |
1410 | u32 tqp_main_vport; | |
1411 | u32 tqp_per_vport; | |
1412 | int num_vport, i; | |
1413 | int ret; | |
1414 | ||
1415 | /* We need to alloc a vport for main NIC of PF */ | |
1416 | num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; | |
1417 | ||
38e62046 HT |
1418 | if (hdev->num_tqps < num_vport) { |
1419 | dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)", | |
1420 | hdev->num_tqps, num_vport); | |
1421 | return -EINVAL; | |
1422 | } | |
46a3df9f S |
1423 | |
1424 | /* Alloc the same number of TQPs for every vport */ | |
1425 | tqp_per_vport = hdev->num_tqps / num_vport; | |
1426 | tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; | |
1427 | ||
1428 | vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), | |
1429 | GFP_KERNEL); | |
1430 | if (!vport) | |
1431 | return -ENOMEM; | |
1432 | ||
1433 | hdev->vport = vport; | |
1434 | hdev->num_alloc_vport = num_vport; | |
1435 | ||
2312e050 FL |
1436 | if (IS_ENABLED(CONFIG_PCI_IOV)) |
1437 | hdev->num_alloc_vfs = hdev->num_req_vfs; | |
46a3df9f S |
1438 | |
1439 | for (i = 0; i < num_vport; i++) { | |
1440 | vport->back = hdev; | |
1441 | vport->vport_id = i; | |
1442 | ||
1443 | if (i == 0) | |
1444 | ret = hclge_vport_setup(vport, tqp_main_vport); | |
1445 | else | |
1446 | ret = hclge_vport_setup(vport, tqp_per_vport); | |
1447 | if (ret) { | |
1448 | dev_err(&pdev->dev, | |
1449 | "vport setup failed for vport %d, %d\n", | |
1450 | i, ret); | |
1451 | return ret; | |
1452 | } | |
1453 | ||
1454 | vport++; | |
1455 | } | |
1456 | ||
1457 | return 0; | |
1458 | } | |
1459 | ||
acf61ecd YL |
1460 | static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, |
1461 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1462 | { |
1463 | /* TX buffer size is unit by 128 byte */ | |
1464 | #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 | |
1465 | #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) | |
d44f9b63 | 1466 | struct hclge_tx_buff_alloc_cmd *req; |
46a3df9f S |
1467 | struct hclge_desc desc; |
1468 | int ret; | |
1469 | u8 i; | |
1470 | ||
d44f9b63 | 1471 | req = (struct hclge_tx_buff_alloc_cmd *)desc.data; |
46a3df9f S |
1472 | |
1473 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); | |
9ffe79a9 | 1474 | for (i = 0; i < HCLGE_TC_NUM; i++) { |
acf61ecd | 1475 | u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; |
9ffe79a9 | 1476 | |
46a3df9f S |
1477 | req->tx_pkt_buff[i] = |
1478 | cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | | |
1479 | HCLGE_BUF_SIZE_UPDATE_EN_MSK); | |
9ffe79a9 | 1480 | } |
46a3df9f S |
1481 | |
1482 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 1483 | if (ret) |
46a3df9f S |
1484 | dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", |
1485 | ret); | |
46a3df9f | 1486 | |
3f639907 | 1487 | return ret; |
46a3df9f S |
1488 | } |
1489 | ||
acf61ecd YL |
1490 | static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, |
1491 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1492 | { |
acf61ecd | 1493 | int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); |
46a3df9f | 1494 | |
3f639907 JS |
1495 | if (ret) |
1496 | dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); | |
46a3df9f | 1497 | |
3f639907 | 1498 | return ret; |
46a3df9f S |
1499 | } |
1500 | ||
1501 | static int hclge_get_tc_num(struct hclge_dev *hdev) | |
1502 | { | |
1503 | int i, cnt = 0; | |
1504 | ||
1505 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
1506 | if (hdev->hw_tc_map & BIT(i)) | |
1507 | cnt++; | |
1508 | return cnt; | |
1509 | } | |
1510 | ||
1511 | static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) | |
1512 | { | |
1513 | int i, cnt = 0; | |
1514 | ||
1515 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
1516 | if (hdev->hw_tc_map & BIT(i) && | |
1517 | hdev->tm_info.hw_pfc_map & BIT(i)) | |
1518 | cnt++; | |
1519 | return cnt; | |
1520 | } | |
1521 | ||
1522 | /* Get the number of pfc enabled TCs, which have private buffer */ | |
acf61ecd YL |
1523 | static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, |
1524 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1525 | { |
1526 | struct hclge_priv_buf *priv; | |
1527 | int i, cnt = 0; | |
1528 | ||
1529 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1530 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1531 | if ((hdev->tm_info.hw_pfc_map & BIT(i)) && |
1532 | priv->enable) | |
1533 | cnt++; | |
1534 | } | |
1535 | ||
1536 | return cnt; | |
1537 | } | |
1538 | ||
1539 | /* Get the number of pfc disabled TCs, which have private buffer */ | |
acf61ecd YL |
1540 | static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, |
1541 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1542 | { |
1543 | struct hclge_priv_buf *priv; | |
1544 | int i, cnt = 0; | |
1545 | ||
1546 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1547 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1548 | if (hdev->hw_tc_map & BIT(i) && |
1549 | !(hdev->tm_info.hw_pfc_map & BIT(i)) && | |
1550 | priv->enable) | |
1551 | cnt++; | |
1552 | } | |
1553 | ||
1554 | return cnt; | |
1555 | } | |
1556 | ||
acf61ecd | 1557 | static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) |
46a3df9f S |
1558 | { |
1559 | struct hclge_priv_buf *priv; | |
1560 | u32 rx_priv = 0; | |
1561 | int i; | |
1562 | ||
1563 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1564 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1565 | if (priv->enable) |
1566 | rx_priv += priv->buf_size; | |
1567 | } | |
1568 | return rx_priv; | |
1569 | } | |
1570 | ||
acf61ecd | 1571 | static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) |
9ffe79a9 YL |
1572 | { |
1573 | u32 i, total_tx_size = 0; | |
1574 | ||
1575 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
acf61ecd | 1576 | total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; |
9ffe79a9 YL |
1577 | |
1578 | return total_tx_size; | |
1579 | } | |
1580 | ||
acf61ecd YL |
1581 | static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, |
1582 | struct hclge_pkt_buf_alloc *buf_alloc, | |
1583 | u32 rx_all) | |
46a3df9f S |
1584 | { |
1585 | u32 shared_buf_min, shared_buf_tc, shared_std; | |
1586 | int tc_num, pfc_enable_num; | |
1587 | u32 shared_buf; | |
1588 | u32 rx_priv; | |
1589 | int i; | |
1590 | ||
1591 | tc_num = hclge_get_tc_num(hdev); | |
1592 | pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); | |
1593 | ||
d221df4e YL |
1594 | if (hnae3_dev_dcb_supported(hdev)) |
1595 | shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; | |
1596 | else | |
1597 | shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; | |
1598 | ||
46a3df9f S |
1599 | shared_buf_tc = pfc_enable_num * hdev->mps + |
1600 | (tc_num - pfc_enable_num) * hdev->mps / 2 + | |
1601 | hdev->mps; | |
1602 | shared_std = max_t(u32, shared_buf_min, shared_buf_tc); | |
1603 | ||
acf61ecd | 1604 | rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); |
46a3df9f S |
1605 | if (rx_all <= rx_priv + shared_std) |
1606 | return false; | |
1607 | ||
1608 | shared_buf = rx_all - rx_priv; | |
acf61ecd YL |
1609 | buf_alloc->s_buf.buf_size = shared_buf; |
1610 | buf_alloc->s_buf.self.high = shared_buf; | |
1611 | buf_alloc->s_buf.self.low = 2 * hdev->mps; | |
46a3df9f S |
1612 | |
1613 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
1614 | if ((hdev->hw_tc_map & BIT(i)) && | |
1615 | (hdev->tm_info.hw_pfc_map & BIT(i))) { | |
acf61ecd YL |
1616 | buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; |
1617 | buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; | |
46a3df9f | 1618 | } else { |
acf61ecd YL |
1619 | buf_alloc->s_buf.tc_thrd[i].low = 0; |
1620 | buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; | |
46a3df9f S |
1621 | } |
1622 | } | |
1623 | ||
1624 | return true; | |
1625 | } | |
1626 | ||
acf61ecd YL |
1627 | static int hclge_tx_buffer_calc(struct hclge_dev *hdev, |
1628 | struct hclge_pkt_buf_alloc *buf_alloc) | |
9ffe79a9 YL |
1629 | { |
1630 | u32 i, total_size; | |
1631 | ||
1632 | total_size = hdev->pkt_buf_size; | |
1633 | ||
1634 | /* alloc tx buffer for all enabled tc */ | |
1635 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1636 | struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; |
9ffe79a9 YL |
1637 | |
1638 | if (total_size < HCLGE_DEFAULT_TX_BUF) | |
1639 | return -ENOMEM; | |
1640 | ||
1641 | if (hdev->hw_tc_map & BIT(i)) | |
1642 | priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; | |
1643 | else | |
1644 | priv->tx_buf_size = 0; | |
1645 | ||
1646 | total_size -= priv->tx_buf_size; | |
1647 | } | |
1648 | ||
1649 | return 0; | |
1650 | } | |
1651 | ||
46a3df9f S |
1652 | /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs |
1653 | * @hdev: pointer to struct hclge_dev | |
acf61ecd | 1654 | * @buf_alloc: pointer to buffer calculation data |
46a3df9f S |
1655 | * @return: 0: calculate sucessful, negative: fail |
1656 | */ | |
1db9b1bf YL |
1657 | static int hclge_rx_buffer_calc(struct hclge_dev *hdev, |
1658 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1659 | { |
9ffe79a9 | 1660 | u32 rx_all = hdev->pkt_buf_size; |
46a3df9f S |
1661 | int no_pfc_priv_num, pfc_priv_num; |
1662 | struct hclge_priv_buf *priv; | |
1663 | int i; | |
1664 | ||
acf61ecd | 1665 | rx_all -= hclge_get_tx_buff_alloced(buf_alloc); |
9ffe79a9 | 1666 | |
d602a525 YL |
1667 | /* When DCB is not supported, rx private |
1668 | * buffer is not allocated. | |
1669 | */ | |
1670 | if (!hnae3_dev_dcb_supported(hdev)) { | |
acf61ecd | 1671 | if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
d602a525 YL |
1672 | return -ENOMEM; |
1673 | ||
1674 | return 0; | |
1675 | } | |
1676 | ||
46a3df9f S |
1677 | /* step 1, try to alloc private buffer for all enabled tc */ |
1678 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1679 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1680 | if (hdev->hw_tc_map & BIT(i)) { |
1681 | priv->enable = 1; | |
1682 | if (hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1683 | priv->wl.low = hdev->mps; | |
1684 | priv->wl.high = priv->wl.low + hdev->mps; | |
1685 | priv->buf_size = priv->wl.high + | |
1686 | HCLGE_DEFAULT_DV; | |
1687 | } else { | |
1688 | priv->wl.low = 0; | |
1689 | priv->wl.high = 2 * hdev->mps; | |
1690 | priv->buf_size = priv->wl.high; | |
1691 | } | |
bb1fe9ea YL |
1692 | } else { |
1693 | priv->enable = 0; | |
1694 | priv->wl.low = 0; | |
1695 | priv->wl.high = 0; | |
1696 | priv->buf_size = 0; | |
46a3df9f S |
1697 | } |
1698 | } | |
1699 | ||
acf61ecd | 1700 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1701 | return 0; |
1702 | ||
1703 | /* step 2, try to decrease the buffer size of | |
1704 | * no pfc TC's private buffer | |
1705 | */ | |
1706 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1707 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f | 1708 | |
bb1fe9ea YL |
1709 | priv->enable = 0; |
1710 | priv->wl.low = 0; | |
1711 | priv->wl.high = 0; | |
1712 | priv->buf_size = 0; | |
1713 | ||
1714 | if (!(hdev->hw_tc_map & BIT(i))) | |
1715 | continue; | |
1716 | ||
1717 | priv->enable = 1; | |
46a3df9f S |
1718 | |
1719 | if (hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1720 | priv->wl.low = 128; | |
1721 | priv->wl.high = priv->wl.low + hdev->mps; | |
1722 | priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; | |
1723 | } else { | |
1724 | priv->wl.low = 0; | |
1725 | priv->wl.high = hdev->mps; | |
1726 | priv->buf_size = priv->wl.high; | |
1727 | } | |
1728 | } | |
1729 | ||
acf61ecd | 1730 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1731 | return 0; |
1732 | ||
1733 | /* step 3, try to reduce the number of pfc disabled TCs, | |
1734 | * which have private buffer | |
1735 | */ | |
1736 | /* get the total no pfc enable TC number, which have private buffer */ | |
acf61ecd | 1737 | no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); |
46a3df9f S |
1738 | |
1739 | /* let the last to be cleared first */ | |
1740 | for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { | |
acf61ecd | 1741 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1742 | |
1743 | if (hdev->hw_tc_map & BIT(i) && | |
1744 | !(hdev->tm_info.hw_pfc_map & BIT(i))) { | |
1745 | /* Clear the no pfc TC private buffer */ | |
1746 | priv->wl.low = 0; | |
1747 | priv->wl.high = 0; | |
1748 | priv->buf_size = 0; | |
1749 | priv->enable = 0; | |
1750 | no_pfc_priv_num--; | |
1751 | } | |
1752 | ||
acf61ecd | 1753 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || |
46a3df9f S |
1754 | no_pfc_priv_num == 0) |
1755 | break; | |
1756 | } | |
1757 | ||
acf61ecd | 1758 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1759 | return 0; |
1760 | ||
1761 | /* step 4, try to reduce the number of pfc enabled TCs | |
1762 | * which have private buffer. | |
1763 | */ | |
acf61ecd | 1764 | pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); |
46a3df9f S |
1765 | |
1766 | /* let the last to be cleared first */ | |
1767 | for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { | |
acf61ecd | 1768 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1769 | |
1770 | if (hdev->hw_tc_map & BIT(i) && | |
1771 | hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1772 | /* Reduce the number of pfc TC with private buffer */ | |
1773 | priv->wl.low = 0; | |
1774 | priv->enable = 0; | |
1775 | priv->wl.high = 0; | |
1776 | priv->buf_size = 0; | |
1777 | pfc_priv_num--; | |
1778 | } | |
1779 | ||
acf61ecd | 1780 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || |
46a3df9f S |
1781 | pfc_priv_num == 0) |
1782 | break; | |
1783 | } | |
acf61ecd | 1784 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1785 | return 0; |
1786 | ||
1787 | return -ENOMEM; | |
1788 | } | |
1789 | ||
acf61ecd YL |
1790 | static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, |
1791 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1792 | { |
d44f9b63 | 1793 | struct hclge_rx_priv_buff_cmd *req; |
46a3df9f S |
1794 | struct hclge_desc desc; |
1795 | int ret; | |
1796 | int i; | |
1797 | ||
1798 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); | |
d44f9b63 | 1799 | req = (struct hclge_rx_priv_buff_cmd *)desc.data; |
46a3df9f S |
1800 | |
1801 | /* Alloc private buffer TCs */ | |
1802 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1803 | struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1804 | |
1805 | req->buf_num[i] = | |
1806 | cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); | |
1807 | req->buf_num[i] |= | |
5bca3b94 | 1808 | cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); |
46a3df9f S |
1809 | } |
1810 | ||
b8c8bf47 | 1811 | req->shared_buf = |
acf61ecd | 1812 | cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | |
b8c8bf47 YL |
1813 | (1 << HCLGE_TC0_PRI_BUF_EN_B)); |
1814 | ||
46a3df9f | 1815 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
3f639907 | 1816 | if (ret) |
46a3df9f S |
1817 | dev_err(&hdev->pdev->dev, |
1818 | "rx private buffer alloc cmd failed %d\n", ret); | |
46a3df9f | 1819 | |
3f639907 | 1820 | return ret; |
46a3df9f S |
1821 | } |
1822 | ||
acf61ecd YL |
1823 | static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, |
1824 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1825 | { |
1826 | struct hclge_rx_priv_wl_buf *req; | |
1827 | struct hclge_priv_buf *priv; | |
1828 | struct hclge_desc desc[2]; | |
1829 | int i, j; | |
1830 | int ret; | |
1831 | ||
1832 | for (i = 0; i < 2; i++) { | |
1833 | hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, | |
1834 | false); | |
1835 | req = (struct hclge_rx_priv_wl_buf *)desc[i].data; | |
1836 | ||
1837 | /* The first descriptor set the NEXT bit to 1 */ | |
1838 | if (i == 0) | |
1839 | desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1840 | else | |
1841 | desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1842 | ||
1843 | for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { | |
acf61ecd YL |
1844 | u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; |
1845 | ||
1846 | priv = &buf_alloc->priv_buf[idx]; | |
46a3df9f S |
1847 | req->tc_wl[j].high = |
1848 | cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); | |
1849 | req->tc_wl[j].high |= | |
3738287c | 1850 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1851 | req->tc_wl[j].low = |
1852 | cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); | |
1853 | req->tc_wl[j].low |= | |
3738287c | 1854 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1855 | } |
1856 | } | |
1857 | ||
1858 | /* Send 2 descriptor at one time */ | |
1859 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
3f639907 | 1860 | if (ret) |
46a3df9f S |
1861 | dev_err(&hdev->pdev->dev, |
1862 | "rx private waterline config cmd failed %d\n", | |
1863 | ret); | |
3f639907 | 1864 | return ret; |
46a3df9f S |
1865 | } |
1866 | ||
acf61ecd YL |
1867 | static int hclge_common_thrd_config(struct hclge_dev *hdev, |
1868 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1869 | { |
acf61ecd | 1870 | struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; |
46a3df9f S |
1871 | struct hclge_rx_com_thrd *req; |
1872 | struct hclge_desc desc[2]; | |
1873 | struct hclge_tc_thrd *tc; | |
1874 | int i, j; | |
1875 | int ret; | |
1876 | ||
1877 | for (i = 0; i < 2; i++) { | |
1878 | hclge_cmd_setup_basic_desc(&desc[i], | |
1879 | HCLGE_OPC_RX_COM_THRD_ALLOC, false); | |
1880 | req = (struct hclge_rx_com_thrd *)&desc[i].data; | |
1881 | ||
1882 | /* The first descriptor set the NEXT bit to 1 */ | |
1883 | if (i == 0) | |
1884 | desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1885 | else | |
1886 | desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1887 | ||
1888 | for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { | |
1889 | tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; | |
1890 | ||
1891 | req->com_thrd[j].high = | |
1892 | cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); | |
1893 | req->com_thrd[j].high |= | |
3738287c | 1894 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1895 | req->com_thrd[j].low = |
1896 | cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); | |
1897 | req->com_thrd[j].low |= | |
3738287c | 1898 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1899 | } |
1900 | } | |
1901 | ||
1902 | /* Send 2 descriptors at one time */ | |
1903 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
3f639907 | 1904 | if (ret) |
46a3df9f S |
1905 | dev_err(&hdev->pdev->dev, |
1906 | "common threshold config cmd failed %d\n", ret); | |
3f639907 | 1907 | return ret; |
46a3df9f S |
1908 | } |
1909 | ||
acf61ecd YL |
1910 | static int hclge_common_wl_config(struct hclge_dev *hdev, |
1911 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1912 | { |
acf61ecd | 1913 | struct hclge_shared_buf *buf = &buf_alloc->s_buf; |
46a3df9f S |
1914 | struct hclge_rx_com_wl *req; |
1915 | struct hclge_desc desc; | |
1916 | int ret; | |
1917 | ||
1918 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); | |
1919 | ||
1920 | req = (struct hclge_rx_com_wl *)desc.data; | |
1921 | req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); | |
3738287c | 1922 | req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1923 | |
1924 | req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); | |
3738287c | 1925 | req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1926 | |
1927 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 1928 | if (ret) |
46a3df9f S |
1929 | dev_err(&hdev->pdev->dev, |
1930 | "common waterline config cmd failed %d\n", ret); | |
46a3df9f | 1931 | |
3f639907 | 1932 | return ret; |
46a3df9f S |
1933 | } |
1934 | ||
1935 | int hclge_buffer_alloc(struct hclge_dev *hdev) | |
1936 | { | |
acf61ecd | 1937 | struct hclge_pkt_buf_alloc *pkt_buf; |
46a3df9f S |
1938 | int ret; |
1939 | ||
acf61ecd YL |
1940 | pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); |
1941 | if (!pkt_buf) | |
46a3df9f S |
1942 | return -ENOMEM; |
1943 | ||
acf61ecd | 1944 | ret = hclge_tx_buffer_calc(hdev, pkt_buf); |
9ffe79a9 YL |
1945 | if (ret) { |
1946 | dev_err(&hdev->pdev->dev, | |
1947 | "could not calc tx buffer size for all TCs %d\n", ret); | |
acf61ecd | 1948 | goto out; |
9ffe79a9 YL |
1949 | } |
1950 | ||
acf61ecd | 1951 | ret = hclge_tx_buffer_alloc(hdev, pkt_buf); |
46a3df9f S |
1952 | if (ret) { |
1953 | dev_err(&hdev->pdev->dev, | |
1954 | "could not alloc tx buffers %d\n", ret); | |
acf61ecd | 1955 | goto out; |
46a3df9f S |
1956 | } |
1957 | ||
acf61ecd | 1958 | ret = hclge_rx_buffer_calc(hdev, pkt_buf); |
46a3df9f S |
1959 | if (ret) { |
1960 | dev_err(&hdev->pdev->dev, | |
1961 | "could not calc rx priv buffer size for all TCs %d\n", | |
1962 | ret); | |
acf61ecd | 1963 | goto out; |
46a3df9f S |
1964 | } |
1965 | ||
acf61ecd | 1966 | ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); |
46a3df9f S |
1967 | if (ret) { |
1968 | dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", | |
1969 | ret); | |
acf61ecd | 1970 | goto out; |
46a3df9f S |
1971 | } |
1972 | ||
2daf4a65 | 1973 | if (hnae3_dev_dcb_supported(hdev)) { |
acf61ecd | 1974 | ret = hclge_rx_priv_wl_config(hdev, pkt_buf); |
2daf4a65 YL |
1975 | if (ret) { |
1976 | dev_err(&hdev->pdev->dev, | |
1977 | "could not configure rx private waterline %d\n", | |
1978 | ret); | |
acf61ecd | 1979 | goto out; |
2daf4a65 | 1980 | } |
46a3df9f | 1981 | |
acf61ecd | 1982 | ret = hclge_common_thrd_config(hdev, pkt_buf); |
2daf4a65 YL |
1983 | if (ret) { |
1984 | dev_err(&hdev->pdev->dev, | |
1985 | "could not configure common threshold %d\n", | |
1986 | ret); | |
acf61ecd | 1987 | goto out; |
2daf4a65 | 1988 | } |
46a3df9f S |
1989 | } |
1990 | ||
acf61ecd YL |
1991 | ret = hclge_common_wl_config(hdev, pkt_buf); |
1992 | if (ret) | |
46a3df9f S |
1993 | dev_err(&hdev->pdev->dev, |
1994 | "could not configure common waterline %d\n", ret); | |
46a3df9f | 1995 | |
acf61ecd YL |
1996 | out: |
1997 | kfree(pkt_buf); | |
1998 | return ret; | |
46a3df9f S |
1999 | } |
2000 | ||
2001 | static int hclge_init_roce_base_info(struct hclge_vport *vport) | |
2002 | { | |
2003 | struct hnae3_handle *roce = &vport->roce; | |
2004 | struct hnae3_handle *nic = &vport->nic; | |
2005 | ||
887c3820 | 2006 | roce->rinfo.num_vectors = vport->back->num_roce_msi; |
46a3df9f S |
2007 | |
2008 | if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || | |
2009 | vport->back->num_msi_left == 0) | |
2010 | return -EINVAL; | |
2011 | ||
2012 | roce->rinfo.base_vector = vport->back->roce_base_vector; | |
2013 | ||
2014 | roce->rinfo.netdev = nic->kinfo.netdev; | |
2015 | roce->rinfo.roce_io_base = vport->back->hw.io_base; | |
2016 | ||
2017 | roce->pdev = nic->pdev; | |
2018 | roce->ae_algo = nic->ae_algo; | |
2019 | roce->numa_node_mask = nic->numa_node_mask; | |
2020 | ||
2021 | return 0; | |
2022 | } | |
2023 | ||
887c3820 | 2024 | static int hclge_init_msi(struct hclge_dev *hdev) |
46a3df9f S |
2025 | { |
2026 | struct pci_dev *pdev = hdev->pdev; | |
887c3820 SM |
2027 | int vectors; |
2028 | int i; | |
46a3df9f | 2029 | |
887c3820 SM |
2030 | vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, |
2031 | PCI_IRQ_MSI | PCI_IRQ_MSIX); | |
2032 | if (vectors < 0) { | |
2033 | dev_err(&pdev->dev, | |
2034 | "failed(%d) to allocate MSI/MSI-X vectors\n", | |
2035 | vectors); | |
2036 | return vectors; | |
46a3df9f | 2037 | } |
887c3820 SM |
2038 | if (vectors < hdev->num_msi) |
2039 | dev_warn(&hdev->pdev->dev, | |
2040 | "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", | |
2041 | hdev->num_msi, vectors); | |
46a3df9f | 2042 | |
887c3820 SM |
2043 | hdev->num_msi = vectors; |
2044 | hdev->num_msi_left = vectors; | |
2045 | hdev->base_msi_vector = pdev->irq; | |
46a3df9f | 2046 | hdev->roce_base_vector = hdev->base_msi_vector + |
375dd5e4 | 2047 | hdev->roce_base_msix_offset; |
46a3df9f | 2048 | |
46a3df9f S |
2049 | hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, |
2050 | sizeof(u16), GFP_KERNEL); | |
887c3820 SM |
2051 | if (!hdev->vector_status) { |
2052 | pci_free_irq_vectors(pdev); | |
46a3df9f | 2053 | return -ENOMEM; |
887c3820 | 2054 | } |
46a3df9f S |
2055 | |
2056 | for (i = 0; i < hdev->num_msi; i++) | |
2057 | hdev->vector_status[i] = HCLGE_INVALID_VPORT; | |
2058 | ||
887c3820 SM |
2059 | hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, |
2060 | sizeof(int), GFP_KERNEL); | |
2061 | if (!hdev->vector_irq) { | |
2062 | pci_free_irq_vectors(pdev); | |
2063 | return -ENOMEM; | |
46a3df9f | 2064 | } |
46a3df9f S |
2065 | |
2066 | return 0; | |
2067 | } | |
2068 | ||
2069 | static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed) | |
2070 | { | |
2071 | struct hclge_mac *mac = &hdev->hw.mac; | |
2072 | ||
2073 | if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M)) | |
2074 | mac->duplex = (u8)duplex; | |
2075 | else | |
2076 | mac->duplex = HCLGE_MAC_FULL; | |
2077 | ||
2078 | mac->speed = speed; | |
2079 | } | |
2080 | ||
2081 | int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) | |
2082 | { | |
d44f9b63 | 2083 | struct hclge_config_mac_speed_dup_cmd *req; |
46a3df9f S |
2084 | struct hclge_desc desc; |
2085 | int ret; | |
2086 | ||
d44f9b63 | 2087 | req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; |
46a3df9f S |
2088 | |
2089 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); | |
2090 | ||
e4e87715 | 2091 | hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); |
46a3df9f S |
2092 | |
2093 | switch (speed) { | |
2094 | case HCLGE_MAC_SPEED_10M: | |
e4e87715 PL |
2095 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2096 | HCLGE_CFG_SPEED_S, 6); | |
46a3df9f S |
2097 | break; |
2098 | case HCLGE_MAC_SPEED_100M: | |
e4e87715 PL |
2099 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2100 | HCLGE_CFG_SPEED_S, 7); | |
46a3df9f S |
2101 | break; |
2102 | case HCLGE_MAC_SPEED_1G: | |
e4e87715 PL |
2103 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2104 | HCLGE_CFG_SPEED_S, 0); | |
46a3df9f S |
2105 | break; |
2106 | case HCLGE_MAC_SPEED_10G: | |
e4e87715 PL |
2107 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2108 | HCLGE_CFG_SPEED_S, 1); | |
46a3df9f S |
2109 | break; |
2110 | case HCLGE_MAC_SPEED_25G: | |
e4e87715 PL |
2111 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2112 | HCLGE_CFG_SPEED_S, 2); | |
46a3df9f S |
2113 | break; |
2114 | case HCLGE_MAC_SPEED_40G: | |
e4e87715 PL |
2115 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2116 | HCLGE_CFG_SPEED_S, 3); | |
46a3df9f S |
2117 | break; |
2118 | case HCLGE_MAC_SPEED_50G: | |
e4e87715 PL |
2119 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2120 | HCLGE_CFG_SPEED_S, 4); | |
46a3df9f S |
2121 | break; |
2122 | case HCLGE_MAC_SPEED_100G: | |
e4e87715 PL |
2123 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2124 | HCLGE_CFG_SPEED_S, 5); | |
46a3df9f S |
2125 | break; |
2126 | default: | |
d7629e74 | 2127 | dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); |
46a3df9f S |
2128 | return -EINVAL; |
2129 | } | |
2130 | ||
e4e87715 PL |
2131 | hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, |
2132 | 1); | |
46a3df9f S |
2133 | |
2134 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2135 | if (ret) { | |
2136 | dev_err(&hdev->pdev->dev, | |
2137 | "mac speed/duplex config cmd failed %d.\n", ret); | |
2138 | return ret; | |
2139 | } | |
2140 | ||
2141 | hclge_check_speed_dup(hdev, duplex, speed); | |
2142 | ||
2143 | return 0; | |
2144 | } | |
2145 | ||
2146 | static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, | |
2147 | u8 duplex) | |
2148 | { | |
2149 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2150 | struct hclge_dev *hdev = vport->back; | |
2151 | ||
2152 | return hclge_cfg_mac_speed_dup(hdev, speed, duplex); | |
2153 | } | |
2154 | ||
2155 | static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, | |
2156 | u8 *duplex) | |
2157 | { | |
d44f9b63 | 2158 | struct hclge_query_an_speed_dup_cmd *req; |
46a3df9f S |
2159 | struct hclge_desc desc; |
2160 | int speed_tmp; | |
2161 | int ret; | |
2162 | ||
d44f9b63 | 2163 | req = (struct hclge_query_an_speed_dup_cmd *)desc.data; |
46a3df9f S |
2164 | |
2165 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); | |
2166 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2167 | if (ret) { | |
2168 | dev_err(&hdev->pdev->dev, | |
2169 | "mac speed/autoneg/duplex query cmd failed %d\n", | |
2170 | ret); | |
2171 | return ret; | |
2172 | } | |
2173 | ||
e4e87715 PL |
2174 | *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); |
2175 | speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, | |
2176 | HCLGE_QUERY_SPEED_S); | |
46a3df9f S |
2177 | |
2178 | ret = hclge_parse_speed(speed_tmp, speed); | |
3f639907 | 2179 | if (ret) |
46a3df9f S |
2180 | dev_err(&hdev->pdev->dev, |
2181 | "could not parse speed(=%d), %d\n", speed_tmp, ret); | |
46a3df9f | 2182 | |
3f639907 | 2183 | return ret; |
46a3df9f S |
2184 | } |
2185 | ||
46a3df9f S |
2186 | static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) |
2187 | { | |
d44f9b63 | 2188 | struct hclge_config_auto_neg_cmd *req; |
46a3df9f | 2189 | struct hclge_desc desc; |
a90bb9a5 | 2190 | u32 flag = 0; |
46a3df9f S |
2191 | int ret; |
2192 | ||
2193 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); | |
2194 | ||
d44f9b63 | 2195 | req = (struct hclge_config_auto_neg_cmd *)desc.data; |
e4e87715 | 2196 | hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); |
a90bb9a5 | 2197 | req->cfg_an_cmd_flag = cpu_to_le32(flag); |
46a3df9f S |
2198 | |
2199 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 2200 | if (ret) |
46a3df9f S |
2201 | dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", |
2202 | ret); | |
46a3df9f | 2203 | |
3f639907 | 2204 | return ret; |
46a3df9f S |
2205 | } |
2206 | ||
2207 | static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) | |
2208 | { | |
2209 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2210 | struct hclge_dev *hdev = vport->back; | |
2211 | ||
2212 | return hclge_set_autoneg_en(hdev, enable); | |
2213 | } | |
2214 | ||
2215 | static int hclge_get_autoneg(struct hnae3_handle *handle) | |
2216 | { | |
2217 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2218 | struct hclge_dev *hdev = vport->back; | |
27b5bf49 FL |
2219 | struct phy_device *phydev = hdev->hw.mac.phydev; |
2220 | ||
2221 | if (phydev) | |
2222 | return phydev->autoneg; | |
46a3df9f S |
2223 | |
2224 | return hdev->hw.mac.autoneg; | |
2225 | } | |
2226 | ||
7564094c PL |
2227 | static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev, |
2228 | bool mask_vlan, | |
2229 | u8 *mac_mask) | |
2230 | { | |
2231 | struct hclge_mac_vlan_mask_entry_cmd *req; | |
2232 | struct hclge_desc desc; | |
2233 | int status; | |
2234 | ||
2235 | req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data; | |
2236 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false); | |
2237 | ||
e4e87715 PL |
2238 | hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B, |
2239 | mask_vlan ? 1 : 0); | |
7564094c PL |
2240 | ether_addr_copy(req->mac_mask, mac_mask); |
2241 | ||
2242 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2243 | if (status) | |
2244 | dev_err(&hdev->pdev->dev, | |
2245 | "Config mac_vlan_mask failed for cmd_send, ret =%d\n", | |
2246 | status); | |
2247 | ||
2248 | return status; | |
2249 | } | |
2250 | ||
46a3df9f S |
2251 | static int hclge_mac_init(struct hclge_dev *hdev) |
2252 | { | |
f9fd82a9 FL |
2253 | struct hnae3_handle *handle = &hdev->vport[0].nic; |
2254 | struct net_device *netdev = handle->kinfo.netdev; | |
46a3df9f | 2255 | struct hclge_mac *mac = &hdev->hw.mac; |
7564094c | 2256 | u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; |
40cca1c5 | 2257 | struct hclge_vport *vport; |
f9fd82a9 | 2258 | int mtu; |
46a3df9f | 2259 | int ret; |
40cca1c5 | 2260 | int i; |
46a3df9f S |
2261 | |
2262 | ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL); | |
2263 | if (ret) { | |
2264 | dev_err(&hdev->pdev->dev, | |
2265 | "Config mac speed dup fail ret=%d\n", ret); | |
2266 | return ret; | |
2267 | } | |
2268 | ||
2269 | mac->link = 0; | |
2270 | ||
46a3df9f | 2271 | /* Initialize the MTA table work mode */ |
46a3df9f S |
2272 | hdev->enable_mta = true; |
2273 | hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36; | |
2274 | ||
2275 | ret = hclge_set_mta_filter_mode(hdev, | |
2276 | hdev->mta_mac_sel_type, | |
2277 | hdev->enable_mta); | |
2278 | if (ret) { | |
2279 | dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n", | |
2280 | ret); | |
2281 | return ret; | |
2282 | } | |
2283 | ||
40cca1c5 XW |
2284 | for (i = 0; i < hdev->num_alloc_vport; i++) { |
2285 | vport = &hdev->vport[i]; | |
2286 | vport->accept_mta_mc = false; | |
2287 | ||
2288 | memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow)); | |
2289 | ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false); | |
2290 | if (ret) { | |
2291 | dev_err(&hdev->pdev->dev, | |
2292 | "set mta filter mode fail ret=%d\n", ret); | |
2293 | return ret; | |
2294 | } | |
7564094c PL |
2295 | } |
2296 | ||
2297 | ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask); | |
f9fd82a9 | 2298 | if (ret) { |
7564094c PL |
2299 | dev_err(&hdev->pdev->dev, |
2300 | "set default mac_vlan_mask fail ret=%d\n", ret); | |
f9fd82a9 FL |
2301 | return ret; |
2302 | } | |
7564094c | 2303 | |
f9fd82a9 FL |
2304 | if (netdev) |
2305 | mtu = netdev->mtu; | |
2306 | else | |
2307 | mtu = ETH_DATA_LEN; | |
2308 | ||
2309 | ret = hclge_set_mtu(handle, mtu); | |
3f639907 | 2310 | if (ret) |
f9fd82a9 FL |
2311 | dev_err(&hdev->pdev->dev, |
2312 | "set mtu failed ret=%d\n", ret); | |
f9fd82a9 | 2313 | |
3f639907 | 2314 | return ret; |
46a3df9f S |
2315 | } |
2316 | ||
c1a81619 SM |
2317 | static void hclge_mbx_task_schedule(struct hclge_dev *hdev) |
2318 | { | |
2319 | if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) | |
2320 | schedule_work(&hdev->mbx_service_task); | |
2321 | } | |
2322 | ||
cb1b9f77 SM |
2323 | static void hclge_reset_task_schedule(struct hclge_dev *hdev) |
2324 | { | |
2325 | if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) | |
2326 | schedule_work(&hdev->rst_service_task); | |
2327 | } | |
2328 | ||
46a3df9f S |
2329 | static void hclge_task_schedule(struct hclge_dev *hdev) |
2330 | { | |
2331 | if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && | |
2332 | !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && | |
2333 | !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) | |
2334 | (void)schedule_work(&hdev->service_task); | |
2335 | } | |
2336 | ||
2337 | static int hclge_get_mac_link_status(struct hclge_dev *hdev) | |
2338 | { | |
d44f9b63 | 2339 | struct hclge_link_status_cmd *req; |
46a3df9f S |
2340 | struct hclge_desc desc; |
2341 | int link_status; | |
2342 | int ret; | |
2343 | ||
2344 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); | |
2345 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2346 | if (ret) { | |
2347 | dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", | |
2348 | ret); | |
2349 | return ret; | |
2350 | } | |
2351 | ||
d44f9b63 | 2352 | req = (struct hclge_link_status_cmd *)desc.data; |
c79301d8 | 2353 | link_status = req->status & HCLGE_LINK_STATUS_UP_M; |
46a3df9f S |
2354 | |
2355 | return !!link_status; | |
2356 | } | |
2357 | ||
2358 | static int hclge_get_mac_phy_link(struct hclge_dev *hdev) | |
2359 | { | |
2360 | int mac_state; | |
2361 | int link_stat; | |
2362 | ||
2363 | mac_state = hclge_get_mac_link_status(hdev); | |
2364 | ||
2365 | if (hdev->hw.mac.phydev) { | |
2366 | if (!genphy_read_status(hdev->hw.mac.phydev)) | |
2367 | link_stat = mac_state & | |
2368 | hdev->hw.mac.phydev->link; | |
2369 | else | |
2370 | link_stat = 0; | |
2371 | ||
2372 | } else { | |
2373 | link_stat = mac_state; | |
2374 | } | |
2375 | ||
2376 | return !!link_stat; | |
2377 | } | |
2378 | ||
2379 | static void hclge_update_link_status(struct hclge_dev *hdev) | |
2380 | { | |
2381 | struct hnae3_client *client = hdev->nic_client; | |
2382 | struct hnae3_handle *handle; | |
2383 | int state; | |
2384 | int i; | |
2385 | ||
2386 | if (!client) | |
2387 | return; | |
2388 | state = hclge_get_mac_phy_link(hdev); | |
2389 | if (state != hdev->hw.mac.link) { | |
2390 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
2391 | handle = &hdev->vport[i].nic; | |
2392 | client->ops->link_status_change(handle, state); | |
2393 | } | |
2394 | hdev->hw.mac.link = state; | |
2395 | } | |
2396 | } | |
2397 | ||
2398 | static int hclge_update_speed_duplex(struct hclge_dev *hdev) | |
2399 | { | |
2400 | struct hclge_mac mac = hdev->hw.mac; | |
2401 | u8 duplex; | |
2402 | int speed; | |
2403 | int ret; | |
2404 | ||
2405 | /* get the speed and duplex as autoneg'result from mac cmd when phy | |
2406 | * doesn't exit. | |
2407 | */ | |
c040366b | 2408 | if (mac.phydev || !mac.autoneg) |
46a3df9f S |
2409 | return 0; |
2410 | ||
2411 | ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); | |
2412 | if (ret) { | |
2413 | dev_err(&hdev->pdev->dev, | |
2414 | "mac autoneg/speed/duplex query failed %d\n", ret); | |
2415 | return ret; | |
2416 | } | |
2417 | ||
2418 | if ((mac.speed != speed) || (mac.duplex != duplex)) { | |
2419 | ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); | |
2420 | if (ret) { | |
2421 | dev_err(&hdev->pdev->dev, | |
2422 | "mac speed/duplex config failed %d\n", ret); | |
2423 | return ret; | |
2424 | } | |
2425 | } | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) | |
2431 | { | |
2432 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2433 | struct hclge_dev *hdev = vport->back; | |
2434 | ||
2435 | return hclge_update_speed_duplex(hdev); | |
2436 | } | |
2437 | ||
2438 | static int hclge_get_status(struct hnae3_handle *handle) | |
2439 | { | |
2440 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2441 | struct hclge_dev *hdev = vport->back; | |
2442 | ||
2443 | hclge_update_link_status(hdev); | |
2444 | ||
2445 | return hdev->hw.mac.link; | |
2446 | } | |
2447 | ||
d039ef68 | 2448 | static void hclge_service_timer(struct timer_list *t) |
46a3df9f | 2449 | { |
d039ef68 | 2450 | struct hclge_dev *hdev = from_timer(hdev, t, service_timer); |
46a3df9f | 2451 | |
d039ef68 | 2452 | mod_timer(&hdev->service_timer, jiffies + HZ); |
c5f65480 | 2453 | hdev->hw_stats.stats_timer++; |
46a3df9f S |
2454 | hclge_task_schedule(hdev); |
2455 | } | |
2456 | ||
2457 | static void hclge_service_complete(struct hclge_dev *hdev) | |
2458 | { | |
2459 | WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); | |
2460 | ||
2461 | /* Flush memory before next watchdog */ | |
2462 | smp_mb__before_atomic(); | |
2463 | clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); | |
2464 | } | |
2465 | ||
ca1d7669 SM |
2466 | static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) |
2467 | { | |
2468 | u32 rst_src_reg; | |
c1a81619 | 2469 | u32 cmdq_src_reg; |
ca1d7669 SM |
2470 | |
2471 | /* fetch the events from their corresponding regs */ | |
9ca8d1a7 | 2472 | rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); |
c1a81619 SM |
2473 | cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); |
2474 | ||
2475 | /* Assumption: If by any chance reset and mailbox events are reported | |
2476 | * together then we will only process reset event in this go and will | |
2477 | * defer the processing of the mailbox events. Since, we would have not | |
2478 | * cleared RX CMDQ event this time we would receive again another | |
2479 | * interrupt from H/W just for the mailbox. | |
2480 | */ | |
ca1d7669 SM |
2481 | |
2482 | /* check for vector0 reset event sources */ | |
2483 | if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { | |
8d40854f | 2484 | set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); |
ca1d7669 SM |
2485 | set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); |
2486 | *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); | |
2487 | return HCLGE_VECTOR0_EVENT_RST; | |
2488 | } | |
2489 | ||
2490 | if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { | |
8d40854f | 2491 | set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); |
ca1d7669 SM |
2492 | set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); |
2493 | *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); | |
2494 | return HCLGE_VECTOR0_EVENT_RST; | |
2495 | } | |
2496 | ||
2497 | if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { | |
2498 | set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); | |
2499 | *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); | |
2500 | return HCLGE_VECTOR0_EVENT_RST; | |
2501 | } | |
2502 | ||
c1a81619 SM |
2503 | /* check for vector0 mailbox(=CMDQ RX) event source */ |
2504 | if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { | |
2505 | cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); | |
2506 | *clearval = cmdq_src_reg; | |
2507 | return HCLGE_VECTOR0_EVENT_MBX; | |
2508 | } | |
ca1d7669 SM |
2509 | |
2510 | return HCLGE_VECTOR0_EVENT_OTHER; | |
2511 | } | |
2512 | ||
2513 | static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, | |
2514 | u32 regclr) | |
2515 | { | |
c1a81619 SM |
2516 | switch (event_type) { |
2517 | case HCLGE_VECTOR0_EVENT_RST: | |
ca1d7669 | 2518 | hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); |
c1a81619 SM |
2519 | break; |
2520 | case HCLGE_VECTOR0_EVENT_MBX: | |
2521 | hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); | |
2522 | break; | |
2523 | } | |
ca1d7669 SM |
2524 | } |
2525 | ||
8e52a602 XW |
2526 | static void hclge_clear_all_event_cause(struct hclge_dev *hdev) |
2527 | { | |
2528 | hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, | |
2529 | BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | | |
2530 | BIT(HCLGE_VECTOR0_CORERESET_INT_B) | | |
2531 | BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); | |
2532 | hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); | |
2533 | } | |
2534 | ||
466b0c00 L |
2535 | static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) |
2536 | { | |
2537 | writel(enable ? 1 : 0, vector->addr); | |
2538 | } | |
2539 | ||
2540 | static irqreturn_t hclge_misc_irq_handle(int irq, void *data) | |
2541 | { | |
2542 | struct hclge_dev *hdev = data; | |
ca1d7669 SM |
2543 | u32 event_cause; |
2544 | u32 clearval; | |
466b0c00 L |
2545 | |
2546 | hclge_enable_vector(&hdev->misc_vector, false); | |
ca1d7669 SM |
2547 | event_cause = hclge_check_event_cause(hdev, &clearval); |
2548 | ||
c1a81619 | 2549 | /* vector 0 interrupt is shared with reset and mailbox source events.*/ |
ca1d7669 SM |
2550 | switch (event_cause) { |
2551 | case HCLGE_VECTOR0_EVENT_RST: | |
cb1b9f77 | 2552 | hclge_reset_task_schedule(hdev); |
ca1d7669 | 2553 | break; |
c1a81619 SM |
2554 | case HCLGE_VECTOR0_EVENT_MBX: |
2555 | /* If we are here then, | |
2556 | * 1. Either we are not handling any mbx task and we are not | |
2557 | * scheduled as well | |
2558 | * OR | |
2559 | * 2. We could be handling a mbx task but nothing more is | |
2560 | * scheduled. | |
2561 | * In both cases, we should schedule mbx task as there are more | |
2562 | * mbx messages reported by this interrupt. | |
2563 | */ | |
2564 | hclge_mbx_task_schedule(hdev); | |
f0ad97ac | 2565 | break; |
ca1d7669 | 2566 | default: |
f0ad97ac YL |
2567 | dev_warn(&hdev->pdev->dev, |
2568 | "received unknown or unhandled event of vector0\n"); | |
ca1d7669 SM |
2569 | break; |
2570 | } | |
2571 | ||
cd8c5c26 YL |
2572 | /* clear the source of interrupt if it is not cause by reset */ |
2573 | if (event_cause != HCLGE_VECTOR0_EVENT_RST) { | |
2574 | hclge_clear_event_cause(hdev, event_cause, clearval); | |
2575 | hclge_enable_vector(&hdev->misc_vector, true); | |
2576 | } | |
466b0c00 L |
2577 | |
2578 | return IRQ_HANDLED; | |
2579 | } | |
2580 | ||
2581 | static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) | |
2582 | { | |
36cbbdf6 PL |
2583 | if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { |
2584 | dev_warn(&hdev->pdev->dev, | |
2585 | "vector(vector_id %d) has been freed.\n", vector_id); | |
2586 | return; | |
2587 | } | |
2588 | ||
466b0c00 L |
2589 | hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; |
2590 | hdev->num_msi_left += 1; | |
2591 | hdev->num_msi_used -= 1; | |
2592 | } | |
2593 | ||
2594 | static void hclge_get_misc_vector(struct hclge_dev *hdev) | |
2595 | { | |
2596 | struct hclge_misc_vector *vector = &hdev->misc_vector; | |
2597 | ||
2598 | vector->vector_irq = pci_irq_vector(hdev->pdev, 0); | |
2599 | ||
2600 | vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; | |
2601 | hdev->vector_status[0] = 0; | |
2602 | ||
2603 | hdev->num_msi_left -= 1; | |
2604 | hdev->num_msi_used += 1; | |
2605 | } | |
2606 | ||
2607 | static int hclge_misc_irq_init(struct hclge_dev *hdev) | |
2608 | { | |
2609 | int ret; | |
2610 | ||
2611 | hclge_get_misc_vector(hdev); | |
2612 | ||
ca1d7669 SM |
2613 | /* this would be explicitly freed in the end */ |
2614 | ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, | |
2615 | 0, "hclge_misc", hdev); | |
466b0c00 L |
2616 | if (ret) { |
2617 | hclge_free_vector(hdev, 0); | |
2618 | dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", | |
2619 | hdev->misc_vector.vector_irq); | |
2620 | } | |
2621 | ||
2622 | return ret; | |
2623 | } | |
2624 | ||
ca1d7669 SM |
2625 | static void hclge_misc_irq_uninit(struct hclge_dev *hdev) |
2626 | { | |
2627 | free_irq(hdev->misc_vector.vector_irq, hdev); | |
2628 | hclge_free_vector(hdev, 0); | |
2629 | } | |
2630 | ||
4ed340ab L |
2631 | static int hclge_notify_client(struct hclge_dev *hdev, |
2632 | enum hnae3_reset_notify_type type) | |
2633 | { | |
2634 | struct hnae3_client *client = hdev->nic_client; | |
2635 | u16 i; | |
2636 | ||
2637 | if (!client->ops->reset_notify) | |
2638 | return -EOPNOTSUPP; | |
2639 | ||
2640 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
2641 | struct hnae3_handle *handle = &hdev->vport[i].nic; | |
2642 | int ret; | |
2643 | ||
2644 | ret = client->ops->reset_notify(handle, type); | |
2645 | if (ret) | |
2646 | return ret; | |
2647 | } | |
2648 | ||
2649 | return 0; | |
2650 | } | |
2651 | ||
2652 | static int hclge_reset_wait(struct hclge_dev *hdev) | |
2653 | { | |
2654 | #define HCLGE_RESET_WATI_MS 100 | |
2655 | #define HCLGE_RESET_WAIT_CNT 5 | |
2656 | u32 val, reg, reg_bit; | |
2657 | u32 cnt = 0; | |
2658 | ||
2659 | switch (hdev->reset_type) { | |
2660 | case HNAE3_GLOBAL_RESET: | |
2661 | reg = HCLGE_GLOBAL_RESET_REG; | |
2662 | reg_bit = HCLGE_GLOBAL_RESET_BIT; | |
2663 | break; | |
2664 | case HNAE3_CORE_RESET: | |
2665 | reg = HCLGE_GLOBAL_RESET_REG; | |
2666 | reg_bit = HCLGE_CORE_RESET_BIT; | |
2667 | break; | |
2668 | case HNAE3_FUNC_RESET: | |
2669 | reg = HCLGE_FUN_RST_ING; | |
2670 | reg_bit = HCLGE_FUN_RST_ING_B; | |
2671 | break; | |
2672 | default: | |
2673 | dev_err(&hdev->pdev->dev, | |
2674 | "Wait for unsupported reset type: %d\n", | |
2675 | hdev->reset_type); | |
2676 | return -EINVAL; | |
2677 | } | |
2678 | ||
2679 | val = hclge_read_dev(&hdev->hw, reg); | |
e4e87715 | 2680 | while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { |
4ed340ab L |
2681 | msleep(HCLGE_RESET_WATI_MS); |
2682 | val = hclge_read_dev(&hdev->hw, reg); | |
2683 | cnt++; | |
2684 | } | |
2685 | ||
4ed340ab L |
2686 | if (cnt >= HCLGE_RESET_WAIT_CNT) { |
2687 | dev_warn(&hdev->pdev->dev, | |
2688 | "Wait for reset timeout: %d\n", hdev->reset_type); | |
2689 | return -EBUSY; | |
2690 | } | |
2691 | ||
2692 | return 0; | |
2693 | } | |
2694 | ||
2bfbd35d | 2695 | int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) |
4ed340ab L |
2696 | { |
2697 | struct hclge_desc desc; | |
2698 | struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; | |
2699 | int ret; | |
2700 | ||
2701 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); | |
e4e87715 | 2702 | hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); |
4ed340ab L |
2703 | req->fun_reset_vfid = func_id; |
2704 | ||
2705 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2706 | if (ret) | |
2707 | dev_err(&hdev->pdev->dev, | |
2708 | "send function reset cmd fail, status =%d\n", ret); | |
2709 | ||
2710 | return ret; | |
2711 | } | |
2712 | ||
f2f432f2 | 2713 | static void hclge_do_reset(struct hclge_dev *hdev) |
4ed340ab L |
2714 | { |
2715 | struct pci_dev *pdev = hdev->pdev; | |
2716 | u32 val; | |
2717 | ||
f2f432f2 | 2718 | switch (hdev->reset_type) { |
4ed340ab L |
2719 | case HNAE3_GLOBAL_RESET: |
2720 | val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); | |
e4e87715 | 2721 | hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); |
4ed340ab L |
2722 | hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); |
2723 | dev_info(&pdev->dev, "Global Reset requested\n"); | |
2724 | break; | |
2725 | case HNAE3_CORE_RESET: | |
2726 | val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); | |
e4e87715 | 2727 | hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1); |
4ed340ab L |
2728 | hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); |
2729 | dev_info(&pdev->dev, "Core Reset requested\n"); | |
2730 | break; | |
2731 | case HNAE3_FUNC_RESET: | |
2732 | dev_info(&pdev->dev, "PF Reset requested\n"); | |
2733 | hclge_func_reset_cmd(hdev, 0); | |
cb1b9f77 SM |
2734 | /* schedule again to check later */ |
2735 | set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); | |
2736 | hclge_reset_task_schedule(hdev); | |
4ed340ab L |
2737 | break; |
2738 | default: | |
2739 | dev_warn(&pdev->dev, | |
f2f432f2 | 2740 | "Unsupported reset type: %d\n", hdev->reset_type); |
4ed340ab L |
2741 | break; |
2742 | } | |
2743 | } | |
2744 | ||
f2f432f2 SM |
2745 | static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, |
2746 | unsigned long *addr) | |
2747 | { | |
2748 | enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; | |
2749 | ||
2750 | /* return the highest priority reset level amongst all */ | |
2751 | if (test_bit(HNAE3_GLOBAL_RESET, addr)) | |
2752 | rst_level = HNAE3_GLOBAL_RESET; | |
2753 | else if (test_bit(HNAE3_CORE_RESET, addr)) | |
2754 | rst_level = HNAE3_CORE_RESET; | |
2755 | else if (test_bit(HNAE3_IMP_RESET, addr)) | |
2756 | rst_level = HNAE3_IMP_RESET; | |
2757 | else if (test_bit(HNAE3_FUNC_RESET, addr)) | |
2758 | rst_level = HNAE3_FUNC_RESET; | |
2759 | ||
2760 | /* now, clear all other resets */ | |
2761 | clear_bit(HNAE3_GLOBAL_RESET, addr); | |
2762 | clear_bit(HNAE3_CORE_RESET, addr); | |
2763 | clear_bit(HNAE3_IMP_RESET, addr); | |
2764 | clear_bit(HNAE3_FUNC_RESET, addr); | |
2765 | ||
2766 | return rst_level; | |
2767 | } | |
2768 | ||
cd8c5c26 YL |
2769 | static void hclge_clear_reset_cause(struct hclge_dev *hdev) |
2770 | { | |
2771 | u32 clearval = 0; | |
2772 | ||
2773 | switch (hdev->reset_type) { | |
2774 | case HNAE3_IMP_RESET: | |
2775 | clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); | |
2776 | break; | |
2777 | case HNAE3_GLOBAL_RESET: | |
2778 | clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); | |
2779 | break; | |
2780 | case HNAE3_CORE_RESET: | |
2781 | clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); | |
2782 | break; | |
2783 | default: | |
cd8c5c26 YL |
2784 | break; |
2785 | } | |
2786 | ||
2787 | if (!clearval) | |
2788 | return; | |
2789 | ||
2790 | hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval); | |
2791 | hclge_enable_vector(&hdev->misc_vector, true); | |
2792 | } | |
2793 | ||
f2f432f2 SM |
2794 | static void hclge_reset(struct hclge_dev *hdev) |
2795 | { | |
9de0b86f HT |
2796 | struct hnae3_handle *handle; |
2797 | ||
f2f432f2 | 2798 | /* perform reset of the stack & ae device for a client */ |
9de0b86f | 2799 | handle = &hdev->vport[0].nic; |
6d4fab39 | 2800 | rtnl_lock(); |
f2f432f2 SM |
2801 | hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); |
2802 | ||
2803 | if (!hclge_reset_wait(hdev)) { | |
f2f432f2 SM |
2804 | hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); |
2805 | hclge_reset_ae_dev(hdev->ae_dev); | |
2806 | hclge_notify_client(hdev, HNAE3_INIT_CLIENT); | |
cd8c5c26 YL |
2807 | |
2808 | hclge_clear_reset_cause(hdev); | |
f2f432f2 SM |
2809 | } else { |
2810 | /* schedule again to check pending resets later */ | |
2811 | set_bit(hdev->reset_type, &hdev->reset_pending); | |
2812 | hclge_reset_task_schedule(hdev); | |
2813 | } | |
2814 | ||
2815 | hclge_notify_client(hdev, HNAE3_UP_CLIENT); | |
9de0b86f | 2816 | handle->last_reset_time = jiffies; |
6d4fab39 | 2817 | rtnl_unlock(); |
f2f432f2 SM |
2818 | } |
2819 | ||
6d4c3981 | 2820 | static void hclge_reset_event(struct hnae3_handle *handle) |
4ed340ab L |
2821 | { |
2822 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2823 | struct hclge_dev *hdev = vport->back; | |
2824 | ||
6d4c3981 SM |
2825 | /* check if this is a new reset request and we are not here just because |
2826 | * last reset attempt did not succeed and watchdog hit us again. We will | |
2827 | * know this if last reset request did not occur very recently (watchdog | |
2828 | * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) | |
2829 | * In case of new request we reset the "reset level" to PF reset. | |
9de0b86f HT |
2830 | * And if it is a repeat reset request of the most recent one then we |
2831 | * want to make sure we throttle the reset request. Therefore, we will | |
2832 | * not allow it again before 3*HZ times. | |
6d4c3981 | 2833 | */ |
9de0b86f HT |
2834 | if (time_before(jiffies, (handle->last_reset_time + 3 * HZ))) |
2835 | return; | |
2836 | else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) | |
6d4c3981 | 2837 | handle->reset_level = HNAE3_FUNC_RESET; |
4ed340ab | 2838 | |
6d4c3981 SM |
2839 | dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", |
2840 | handle->reset_level); | |
2841 | ||
2842 | /* request reset & schedule reset task */ | |
2843 | set_bit(handle->reset_level, &hdev->reset_request); | |
2844 | hclge_reset_task_schedule(hdev); | |
2845 | ||
2846 | if (handle->reset_level < HNAE3_GLOBAL_RESET) | |
2847 | handle->reset_level++; | |
4ed340ab L |
2848 | } |
2849 | ||
2850 | static void hclge_reset_subtask(struct hclge_dev *hdev) | |
2851 | { | |
f2f432f2 SM |
2852 | /* check if there is any ongoing reset in the hardware. This status can |
2853 | * be checked from reset_pending. If there is then, we need to wait for | |
2854 | * hardware to complete reset. | |
2855 | * a. If we are able to figure out in reasonable time that hardware | |
2856 | * has fully resetted then, we can proceed with driver, client | |
2857 | * reset. | |
2858 | * b. else, we can come back later to check this status so re-sched | |
2859 | * now. | |
2860 | */ | |
2861 | hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); | |
2862 | if (hdev->reset_type != HNAE3_NONE_RESET) | |
2863 | hclge_reset(hdev); | |
4ed340ab | 2864 | |
f2f432f2 SM |
2865 | /* check if we got any *new* reset requests to be honored */ |
2866 | hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); | |
2867 | if (hdev->reset_type != HNAE3_NONE_RESET) | |
2868 | hclge_do_reset(hdev); | |
4ed340ab | 2869 | |
4ed340ab L |
2870 | hdev->reset_type = HNAE3_NONE_RESET; |
2871 | } | |
2872 | ||
cb1b9f77 | 2873 | static void hclge_reset_service_task(struct work_struct *work) |
466b0c00 | 2874 | { |
cb1b9f77 SM |
2875 | struct hclge_dev *hdev = |
2876 | container_of(work, struct hclge_dev, rst_service_task); | |
2877 | ||
2878 | if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) | |
2879 | return; | |
2880 | ||
2881 | clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); | |
2882 | ||
4ed340ab | 2883 | hclge_reset_subtask(hdev); |
cb1b9f77 SM |
2884 | |
2885 | clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); | |
466b0c00 L |
2886 | } |
2887 | ||
c1a81619 SM |
2888 | static void hclge_mailbox_service_task(struct work_struct *work) |
2889 | { | |
2890 | struct hclge_dev *hdev = | |
2891 | container_of(work, struct hclge_dev, mbx_service_task); | |
2892 | ||
2893 | if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) | |
2894 | return; | |
2895 | ||
2896 | clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); | |
2897 | ||
2898 | hclge_mbx_handler(hdev); | |
2899 | ||
2900 | clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); | |
2901 | } | |
2902 | ||
46a3df9f S |
2903 | static void hclge_service_task(struct work_struct *work) |
2904 | { | |
2905 | struct hclge_dev *hdev = | |
2906 | container_of(work, struct hclge_dev, service_task); | |
2907 | ||
c5f65480 JS |
2908 | if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { |
2909 | hclge_update_stats_for_all(hdev); | |
2910 | hdev->hw_stats.stats_timer = 0; | |
2911 | } | |
2912 | ||
46a3df9f S |
2913 | hclge_update_speed_duplex(hdev); |
2914 | hclge_update_link_status(hdev); | |
46a3df9f S |
2915 | hclge_service_complete(hdev); |
2916 | } | |
2917 | ||
46a3df9f S |
2918 | struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) |
2919 | { | |
2920 | /* VF handle has no client */ | |
2921 | if (!handle->client) | |
2922 | return container_of(handle, struct hclge_vport, nic); | |
2923 | else if (handle->client->type == HNAE3_CLIENT_ROCE) | |
2924 | return container_of(handle, struct hclge_vport, roce); | |
2925 | else | |
2926 | return container_of(handle, struct hclge_vport, nic); | |
2927 | } | |
2928 | ||
2929 | static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, | |
2930 | struct hnae3_vector_info *vector_info) | |
2931 | { | |
2932 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2933 | struct hnae3_vector_info *vector = vector_info; | |
2934 | struct hclge_dev *hdev = vport->back; | |
2935 | int alloc = 0; | |
2936 | int i, j; | |
2937 | ||
2938 | vector_num = min(hdev->num_msi_left, vector_num); | |
2939 | ||
2940 | for (j = 0; j < vector_num; j++) { | |
2941 | for (i = 1; i < hdev->num_msi; i++) { | |
2942 | if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { | |
2943 | vector->vector = pci_irq_vector(hdev->pdev, i); | |
2944 | vector->io_addr = hdev->hw.io_base + | |
2945 | HCLGE_VECTOR_REG_BASE + | |
2946 | (i - 1) * HCLGE_VECTOR_REG_OFFSET + | |
2947 | vport->vport_id * | |
2948 | HCLGE_VECTOR_VF_OFFSET; | |
2949 | hdev->vector_status[i] = vport->vport_id; | |
887c3820 | 2950 | hdev->vector_irq[i] = vector->vector; |
46a3df9f S |
2951 | |
2952 | vector++; | |
2953 | alloc++; | |
2954 | ||
2955 | break; | |
2956 | } | |
2957 | } | |
2958 | } | |
2959 | hdev->num_msi_left -= alloc; | |
2960 | hdev->num_msi_used += alloc; | |
2961 | ||
2962 | return alloc; | |
2963 | } | |
2964 | ||
2965 | static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) | |
2966 | { | |
2967 | int i; | |
2968 | ||
887c3820 SM |
2969 | for (i = 0; i < hdev->num_msi; i++) |
2970 | if (vector == hdev->vector_irq[i]) | |
2971 | return i; | |
2972 | ||
46a3df9f S |
2973 | return -EINVAL; |
2974 | } | |
2975 | ||
0d3e6631 YL |
2976 | static int hclge_put_vector(struct hnae3_handle *handle, int vector) |
2977 | { | |
2978 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2979 | struct hclge_dev *hdev = vport->back; | |
2980 | int vector_id; | |
2981 | ||
2982 | vector_id = hclge_get_vector_index(hdev, vector); | |
2983 | if (vector_id < 0) { | |
2984 | dev_err(&hdev->pdev->dev, | |
2985 | "Get vector index fail. vector_id =%d\n", vector_id); | |
2986 | return vector_id; | |
2987 | } | |
2988 | ||
2989 | hclge_free_vector(hdev, vector_id); | |
2990 | ||
2991 | return 0; | |
2992 | } | |
2993 | ||
46a3df9f S |
2994 | static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) |
2995 | { | |
2996 | return HCLGE_RSS_KEY_SIZE; | |
2997 | } | |
2998 | ||
2999 | static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) | |
3000 | { | |
3001 | return HCLGE_RSS_IND_TBL_SIZE; | |
3002 | } | |
3003 | ||
46a3df9f S |
3004 | static int hclge_set_rss_algo_key(struct hclge_dev *hdev, |
3005 | const u8 hfunc, const u8 *key) | |
3006 | { | |
d44f9b63 | 3007 | struct hclge_rss_config_cmd *req; |
46a3df9f S |
3008 | struct hclge_desc desc; |
3009 | int key_offset; | |
3010 | int key_size; | |
3011 | int ret; | |
3012 | ||
d44f9b63 | 3013 | req = (struct hclge_rss_config_cmd *)desc.data; |
46a3df9f S |
3014 | |
3015 | for (key_offset = 0; key_offset < 3; key_offset++) { | |
3016 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, | |
3017 | false); | |
3018 | ||
3019 | req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); | |
3020 | req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); | |
3021 | ||
3022 | if (key_offset == 2) | |
3023 | key_size = | |
3024 | HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; | |
3025 | else | |
3026 | key_size = HCLGE_RSS_HASH_KEY_NUM; | |
3027 | ||
3028 | memcpy(req->hash_key, | |
3029 | key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); | |
3030 | ||
3031 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3032 | if (ret) { | |
3033 | dev_err(&hdev->pdev->dev, | |
3034 | "Configure RSS config fail, status = %d\n", | |
3035 | ret); | |
3036 | return ret; | |
3037 | } | |
3038 | } | |
3039 | return 0; | |
3040 | } | |
3041 | ||
89523cfa | 3042 | static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir) |
46a3df9f | 3043 | { |
d44f9b63 | 3044 | struct hclge_rss_indirection_table_cmd *req; |
46a3df9f S |
3045 | struct hclge_desc desc; |
3046 | int i, j; | |
3047 | int ret; | |
3048 | ||
d44f9b63 | 3049 | req = (struct hclge_rss_indirection_table_cmd *)desc.data; |
46a3df9f S |
3050 | |
3051 | for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { | |
3052 | hclge_cmd_setup_basic_desc | |
3053 | (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); | |
3054 | ||
a90bb9a5 YL |
3055 | req->start_table_index = |
3056 | cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); | |
3057 | req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); | |
46a3df9f S |
3058 | |
3059 | for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) | |
3060 | req->rss_result[j] = | |
3061 | indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; | |
3062 | ||
3063 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3064 | if (ret) { | |
3065 | dev_err(&hdev->pdev->dev, | |
3066 | "Configure rss indir table fail,status = %d\n", | |
3067 | ret); | |
3068 | return ret; | |
3069 | } | |
3070 | } | |
3071 | return 0; | |
3072 | } | |
3073 | ||
3074 | static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, | |
3075 | u16 *tc_size, u16 *tc_offset) | |
3076 | { | |
d44f9b63 | 3077 | struct hclge_rss_tc_mode_cmd *req; |
46a3df9f S |
3078 | struct hclge_desc desc; |
3079 | int ret; | |
3080 | int i; | |
3081 | ||
3082 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); | |
d44f9b63 | 3083 | req = (struct hclge_rss_tc_mode_cmd *)desc.data; |
46a3df9f S |
3084 | |
3085 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
a90bb9a5 YL |
3086 | u16 mode = 0; |
3087 | ||
e4e87715 PL |
3088 | hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); |
3089 | hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M, | |
3090 | HCLGE_RSS_TC_SIZE_S, tc_size[i]); | |
3091 | hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M, | |
3092 | HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); | |
a90bb9a5 YL |
3093 | |
3094 | req->rss_tc_mode[i] = cpu_to_le16(mode); | |
46a3df9f S |
3095 | } |
3096 | ||
3097 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 3098 | if (ret) |
46a3df9f S |
3099 | dev_err(&hdev->pdev->dev, |
3100 | "Configure rss tc mode fail, status = %d\n", ret); | |
46a3df9f | 3101 | |
3f639907 | 3102 | return ret; |
46a3df9f S |
3103 | } |
3104 | ||
3105 | static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) | |
3106 | { | |
d44f9b63 | 3107 | struct hclge_rss_input_tuple_cmd *req; |
46a3df9f S |
3108 | struct hclge_desc desc; |
3109 | int ret; | |
3110 | ||
3111 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); | |
3112 | ||
d44f9b63 | 3113 | req = (struct hclge_rss_input_tuple_cmd *)desc.data; |
6f2af429 YL |
3114 | |
3115 | /* Get the tuple cfg from pf */ | |
3116 | req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en; | |
3117 | req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en; | |
3118 | req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en; | |
3119 | req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en; | |
3120 | req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en; | |
3121 | req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; | |
3122 | req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; | |
3123 | req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; | |
46a3df9f | 3124 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
3f639907 | 3125 | if (ret) |
46a3df9f S |
3126 | dev_err(&hdev->pdev->dev, |
3127 | "Configure rss input fail, status = %d\n", ret); | |
3f639907 | 3128 | return ret; |
46a3df9f S |
3129 | } |
3130 | ||
3131 | static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, | |
3132 | u8 *key, u8 *hfunc) | |
3133 | { | |
3134 | struct hclge_vport *vport = hclge_get_vport(handle); | |
46a3df9f S |
3135 | int i; |
3136 | ||
3137 | /* Get hash algorithm */ | |
3138 | if (hfunc) | |
89523cfa | 3139 | *hfunc = vport->rss_algo; |
46a3df9f S |
3140 | |
3141 | /* Get the RSS Key required by the user */ | |
3142 | if (key) | |
3143 | memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); | |
3144 | ||
3145 | /* Get indirect table */ | |
3146 | if (indir) | |
3147 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3148 | indir[i] = vport->rss_indirection_tbl[i]; | |
3149 | ||
3150 | return 0; | |
3151 | } | |
3152 | ||
3153 | static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, | |
3154 | const u8 *key, const u8 hfunc) | |
3155 | { | |
3156 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3157 | struct hclge_dev *hdev = vport->back; | |
3158 | u8 hash_algo; | |
3159 | int ret, i; | |
3160 | ||
3161 | /* Set the RSS Hash Key if specififed by the user */ | |
3162 | if (key) { | |
46a3df9f S |
3163 | |
3164 | if (hfunc == ETH_RSS_HASH_TOP || | |
3165 | hfunc == ETH_RSS_HASH_NO_CHANGE) | |
3166 | hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; | |
3167 | else | |
3168 | return -EINVAL; | |
3169 | ret = hclge_set_rss_algo_key(hdev, hash_algo, key); | |
3170 | if (ret) | |
3171 | return ret; | |
89523cfa YL |
3172 | |
3173 | /* Update the shadow RSS key with user specified qids */ | |
3174 | memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); | |
3175 | vport->rss_algo = hash_algo; | |
46a3df9f S |
3176 | } |
3177 | ||
3178 | /* Update the shadow RSS table with user specified qids */ | |
3179 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3180 | vport->rss_indirection_tbl[i] = indir[i]; | |
3181 | ||
3182 | /* Update the hardware */ | |
89523cfa | 3183 | return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl); |
46a3df9f S |
3184 | } |
3185 | ||
f7db940a L |
3186 | static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) |
3187 | { | |
3188 | u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; | |
3189 | ||
3190 | if (nfc->data & RXH_L4_B_2_3) | |
3191 | hash_sets |= HCLGE_D_PORT_BIT; | |
3192 | else | |
3193 | hash_sets &= ~HCLGE_D_PORT_BIT; | |
3194 | ||
3195 | if (nfc->data & RXH_IP_SRC) | |
3196 | hash_sets |= HCLGE_S_IP_BIT; | |
3197 | else | |
3198 | hash_sets &= ~HCLGE_S_IP_BIT; | |
3199 | ||
3200 | if (nfc->data & RXH_IP_DST) | |
3201 | hash_sets |= HCLGE_D_IP_BIT; | |
3202 | else | |
3203 | hash_sets &= ~HCLGE_D_IP_BIT; | |
3204 | ||
3205 | if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) | |
3206 | hash_sets |= HCLGE_V_TAG_BIT; | |
3207 | ||
3208 | return hash_sets; | |
3209 | } | |
3210 | ||
3211 | static int hclge_set_rss_tuple(struct hnae3_handle *handle, | |
3212 | struct ethtool_rxnfc *nfc) | |
3213 | { | |
3214 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3215 | struct hclge_dev *hdev = vport->back; | |
3216 | struct hclge_rss_input_tuple_cmd *req; | |
3217 | struct hclge_desc desc; | |
3218 | u8 tuple_sets; | |
3219 | int ret; | |
3220 | ||
3221 | if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | | |
3222 | RXH_L4_B_0_1 | RXH_L4_B_2_3)) | |
3223 | return -EINVAL; | |
3224 | ||
3225 | req = (struct hclge_rss_input_tuple_cmd *)desc.data; | |
6f2af429 | 3226 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); |
f7db940a | 3227 | |
6f2af429 YL |
3228 | req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en; |
3229 | req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en; | |
3230 | req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en; | |
3231 | req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en; | |
3232 | req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en; | |
3233 | req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en; | |
3234 | req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en; | |
3235 | req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en; | |
f7db940a L |
3236 | |
3237 | tuple_sets = hclge_get_rss_hash_bits(nfc); | |
3238 | switch (nfc->flow_type) { | |
3239 | case TCP_V4_FLOW: | |
3240 | req->ipv4_tcp_en = tuple_sets; | |
3241 | break; | |
3242 | case TCP_V6_FLOW: | |
3243 | req->ipv6_tcp_en = tuple_sets; | |
3244 | break; | |
3245 | case UDP_V4_FLOW: | |
3246 | req->ipv4_udp_en = tuple_sets; | |
3247 | break; | |
3248 | case UDP_V6_FLOW: | |
3249 | req->ipv6_udp_en = tuple_sets; | |
3250 | break; | |
3251 | case SCTP_V4_FLOW: | |
3252 | req->ipv4_sctp_en = tuple_sets; | |
3253 | break; | |
3254 | case SCTP_V6_FLOW: | |
3255 | if ((nfc->data & RXH_L4_B_0_1) || | |
3256 | (nfc->data & RXH_L4_B_2_3)) | |
3257 | return -EINVAL; | |
3258 | ||
3259 | req->ipv6_sctp_en = tuple_sets; | |
3260 | break; | |
3261 | case IPV4_FLOW: | |
3262 | req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3263 | break; | |
3264 | case IPV6_FLOW: | |
3265 | req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3266 | break; | |
3267 | default: | |
3268 | return -EINVAL; | |
3269 | } | |
3270 | ||
3271 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
6f2af429 | 3272 | if (ret) { |
f7db940a L |
3273 | dev_err(&hdev->pdev->dev, |
3274 | "Set rss tuple fail, status = %d\n", ret); | |
6f2af429 YL |
3275 | return ret; |
3276 | } | |
f7db940a | 3277 | |
6f2af429 YL |
3278 | vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; |
3279 | vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; | |
3280 | vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; | |
3281 | vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; | |
3282 | vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; | |
3283 | vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; | |
3284 | vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; | |
3285 | vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; | |
3286 | return 0; | |
f7db940a L |
3287 | } |
3288 | ||
07d29954 L |
3289 | static int hclge_get_rss_tuple(struct hnae3_handle *handle, |
3290 | struct ethtool_rxnfc *nfc) | |
3291 | { | |
3292 | struct hclge_vport *vport = hclge_get_vport(handle); | |
07d29954 | 3293 | u8 tuple_sets; |
07d29954 L |
3294 | |
3295 | nfc->data = 0; | |
3296 | ||
07d29954 L |
3297 | switch (nfc->flow_type) { |
3298 | case TCP_V4_FLOW: | |
6f2af429 | 3299 | tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en; |
07d29954 L |
3300 | break; |
3301 | case UDP_V4_FLOW: | |
6f2af429 | 3302 | tuple_sets = vport->rss_tuple_sets.ipv4_udp_en; |
07d29954 L |
3303 | break; |
3304 | case TCP_V6_FLOW: | |
6f2af429 | 3305 | tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en; |
07d29954 L |
3306 | break; |
3307 | case UDP_V6_FLOW: | |
6f2af429 | 3308 | tuple_sets = vport->rss_tuple_sets.ipv6_udp_en; |
07d29954 L |
3309 | break; |
3310 | case SCTP_V4_FLOW: | |
6f2af429 | 3311 | tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en; |
07d29954 L |
3312 | break; |
3313 | case SCTP_V6_FLOW: | |
6f2af429 | 3314 | tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en; |
07d29954 L |
3315 | break; |
3316 | case IPV4_FLOW: | |
3317 | case IPV6_FLOW: | |
3318 | tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; | |
3319 | break; | |
3320 | default: | |
3321 | return -EINVAL; | |
3322 | } | |
3323 | ||
3324 | if (!tuple_sets) | |
3325 | return 0; | |
3326 | ||
3327 | if (tuple_sets & HCLGE_D_PORT_BIT) | |
3328 | nfc->data |= RXH_L4_B_2_3; | |
3329 | if (tuple_sets & HCLGE_S_PORT_BIT) | |
3330 | nfc->data |= RXH_L4_B_0_1; | |
3331 | if (tuple_sets & HCLGE_D_IP_BIT) | |
3332 | nfc->data |= RXH_IP_DST; | |
3333 | if (tuple_sets & HCLGE_S_IP_BIT) | |
3334 | nfc->data |= RXH_IP_SRC; | |
3335 | ||
3336 | return 0; | |
3337 | } | |
3338 | ||
46a3df9f S |
3339 | static int hclge_get_tc_size(struct hnae3_handle *handle) |
3340 | { | |
3341 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3342 | struct hclge_dev *hdev = vport->back; | |
3343 | ||
3344 | return hdev->rss_size_max; | |
3345 | } | |
3346 | ||
77f255c1 | 3347 | int hclge_rss_init_hw(struct hclge_dev *hdev) |
46a3df9f | 3348 | { |
46a3df9f | 3349 | struct hclge_vport *vport = hdev->vport; |
268f5dfa YL |
3350 | u8 *rss_indir = vport[0].rss_indirection_tbl; |
3351 | u16 rss_size = vport[0].alloc_rss_size; | |
3352 | u8 *key = vport[0].rss_hash_key; | |
3353 | u8 hfunc = vport[0].rss_algo; | |
46a3df9f | 3354 | u16 tc_offset[HCLGE_MAX_TC_NUM]; |
46a3df9f S |
3355 | u16 tc_valid[HCLGE_MAX_TC_NUM]; |
3356 | u16 tc_size[HCLGE_MAX_TC_NUM]; | |
268f5dfa YL |
3357 | u16 roundup_size; |
3358 | int i, ret; | |
68ece54e | 3359 | |
46a3df9f S |
3360 | ret = hclge_set_rss_indir_table(hdev, rss_indir); |
3361 | if (ret) | |
268f5dfa | 3362 | return ret; |
46a3df9f | 3363 | |
46a3df9f S |
3364 | ret = hclge_set_rss_algo_key(hdev, hfunc, key); |
3365 | if (ret) | |
268f5dfa | 3366 | return ret; |
46a3df9f S |
3367 | |
3368 | ret = hclge_set_rss_input_tuple(hdev); | |
3369 | if (ret) | |
268f5dfa | 3370 | return ret; |
46a3df9f | 3371 | |
68ece54e YL |
3372 | /* Each TC have the same queue size, and tc_size set to hardware is |
3373 | * the log2 of roundup power of two of rss_size, the acutal queue | |
3374 | * size is limited by indirection table. | |
3375 | */ | |
3376 | if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { | |
3377 | dev_err(&hdev->pdev->dev, | |
3378 | "Configure rss tc size failed, invalid TC_SIZE = %d\n", | |
3379 | rss_size); | |
268f5dfa | 3380 | return -EINVAL; |
68ece54e YL |
3381 | } |
3382 | ||
3383 | roundup_size = roundup_pow_of_two(rss_size); | |
3384 | roundup_size = ilog2(roundup_size); | |
3385 | ||
46a3df9f | 3386 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
68ece54e | 3387 | tc_valid[i] = 0; |
46a3df9f | 3388 | |
68ece54e YL |
3389 | if (!(hdev->hw_tc_map & BIT(i))) |
3390 | continue; | |
3391 | ||
3392 | tc_valid[i] = 1; | |
3393 | tc_size[i] = roundup_size; | |
3394 | tc_offset[i] = rss_size * i; | |
46a3df9f | 3395 | } |
68ece54e | 3396 | |
268f5dfa YL |
3397 | return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); |
3398 | } | |
46a3df9f | 3399 | |
268f5dfa YL |
3400 | void hclge_rss_indir_init_cfg(struct hclge_dev *hdev) |
3401 | { | |
3402 | struct hclge_vport *vport = hdev->vport; | |
3403 | int i, j; | |
46a3df9f | 3404 | |
268f5dfa YL |
3405 | for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { |
3406 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3407 | vport[j].rss_indirection_tbl[i] = | |
3408 | i % vport[j].alloc_rss_size; | |
3409 | } | |
3410 | } | |
3411 | ||
3412 | static void hclge_rss_init_cfg(struct hclge_dev *hdev) | |
3413 | { | |
3414 | struct hclge_vport *vport = hdev->vport; | |
3415 | int i; | |
3416 | ||
268f5dfa YL |
3417 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { |
3418 | vport[i].rss_tuple_sets.ipv4_tcp_en = | |
3419 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3420 | vport[i].rss_tuple_sets.ipv4_udp_en = | |
3421 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3422 | vport[i].rss_tuple_sets.ipv4_sctp_en = | |
3423 | HCLGE_RSS_INPUT_TUPLE_SCTP; | |
3424 | vport[i].rss_tuple_sets.ipv4_fragment_en = | |
3425 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3426 | vport[i].rss_tuple_sets.ipv6_tcp_en = | |
3427 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3428 | vport[i].rss_tuple_sets.ipv6_udp_en = | |
3429 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3430 | vport[i].rss_tuple_sets.ipv6_sctp_en = | |
3431 | HCLGE_RSS_INPUT_TUPLE_SCTP; | |
3432 | vport[i].rss_tuple_sets.ipv6_fragment_en = | |
3433 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3434 | ||
3435 | vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; | |
ea739c90 FL |
3436 | |
3437 | netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE); | |
268f5dfa YL |
3438 | } |
3439 | ||
3440 | hclge_rss_indir_init_cfg(hdev); | |
46a3df9f S |
3441 | } |
3442 | ||
84e095d6 SM |
3443 | int hclge_bind_ring_with_vector(struct hclge_vport *vport, |
3444 | int vector_id, bool en, | |
3445 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3446 | { |
3447 | struct hclge_dev *hdev = vport->back; | |
46a3df9f S |
3448 | struct hnae3_ring_chain_node *node; |
3449 | struct hclge_desc desc; | |
84e095d6 SM |
3450 | struct hclge_ctrl_vector_chain_cmd *req |
3451 | = (struct hclge_ctrl_vector_chain_cmd *)desc.data; | |
3452 | enum hclge_cmd_status status; | |
3453 | enum hclge_opcode_type op; | |
3454 | u16 tqp_type_and_id; | |
46a3df9f S |
3455 | int i; |
3456 | ||
84e095d6 SM |
3457 | op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; |
3458 | hclge_cmd_setup_basic_desc(&desc, op, false); | |
46a3df9f S |
3459 | req->int_vector_id = vector_id; |
3460 | ||
3461 | i = 0; | |
3462 | for (node = ring_chain; node; node = node->next) { | |
84e095d6 | 3463 | tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); |
e4e87715 PL |
3464 | hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, |
3465 | HCLGE_INT_TYPE_S, | |
3466 | hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); | |
3467 | hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, | |
3468 | HCLGE_TQP_ID_S, node->tqp_index); | |
3469 | hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, | |
3470 | HCLGE_INT_GL_IDX_S, | |
3471 | hnae3_get_field(node->int_gl_idx, | |
3472 | HNAE3_RING_GL_IDX_M, | |
3473 | HNAE3_RING_GL_IDX_S)); | |
84e095d6 | 3474 | req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); |
46a3df9f S |
3475 | if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { |
3476 | req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; | |
84e095d6 | 3477 | req->vfid = vport->vport_id; |
46a3df9f | 3478 | |
84e095d6 SM |
3479 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
3480 | if (status) { | |
46a3df9f S |
3481 | dev_err(&hdev->pdev->dev, |
3482 | "Map TQP fail, status is %d.\n", | |
84e095d6 SM |
3483 | status); |
3484 | return -EIO; | |
46a3df9f S |
3485 | } |
3486 | i = 0; | |
3487 | ||
3488 | hclge_cmd_setup_basic_desc(&desc, | |
84e095d6 | 3489 | op, |
46a3df9f S |
3490 | false); |
3491 | req->int_vector_id = vector_id; | |
3492 | } | |
3493 | } | |
3494 | ||
3495 | if (i > 0) { | |
3496 | req->int_cause_num = i; | |
84e095d6 SM |
3497 | req->vfid = vport->vport_id; |
3498 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3499 | if (status) { | |
46a3df9f | 3500 | dev_err(&hdev->pdev->dev, |
84e095d6 SM |
3501 | "Map TQP fail, status is %d.\n", status); |
3502 | return -EIO; | |
46a3df9f S |
3503 | } |
3504 | } | |
3505 | ||
3506 | return 0; | |
3507 | } | |
3508 | ||
84e095d6 SM |
3509 | static int hclge_map_ring_to_vector(struct hnae3_handle *handle, |
3510 | int vector, | |
3511 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3512 | { |
3513 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3514 | struct hclge_dev *hdev = vport->back; | |
3515 | int vector_id; | |
3516 | ||
3517 | vector_id = hclge_get_vector_index(hdev, vector); | |
3518 | if (vector_id < 0) { | |
3519 | dev_err(&hdev->pdev->dev, | |
84e095d6 | 3520 | "Get vector index fail. vector_id =%d\n", vector_id); |
46a3df9f S |
3521 | return vector_id; |
3522 | } | |
3523 | ||
84e095d6 | 3524 | return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); |
46a3df9f S |
3525 | } |
3526 | ||
84e095d6 SM |
3527 | static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, |
3528 | int vector, | |
3529 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3530 | { |
3531 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3532 | struct hclge_dev *hdev = vport->back; | |
84e095d6 | 3533 | int vector_id, ret; |
46a3df9f | 3534 | |
b50ae26c PL |
3535 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
3536 | return 0; | |
3537 | ||
46a3df9f S |
3538 | vector_id = hclge_get_vector_index(hdev, vector); |
3539 | if (vector_id < 0) { | |
3540 | dev_err(&handle->pdev->dev, | |
3541 | "Get vector index fail. ret =%d\n", vector_id); | |
3542 | return vector_id; | |
3543 | } | |
3544 | ||
84e095d6 | 3545 | ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); |
0d3e6631 | 3546 | if (ret) |
84e095d6 SM |
3547 | dev_err(&handle->pdev->dev, |
3548 | "Unmap ring from vector fail. vectorid=%d, ret =%d\n", | |
3549 | vector_id, | |
3550 | ret); | |
46a3df9f | 3551 | |
0d3e6631 | 3552 | return ret; |
46a3df9f S |
3553 | } |
3554 | ||
3555 | int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, | |
3556 | struct hclge_promisc_param *param) | |
3557 | { | |
d44f9b63 | 3558 | struct hclge_promisc_cfg_cmd *req; |
46a3df9f S |
3559 | struct hclge_desc desc; |
3560 | int ret; | |
3561 | ||
3562 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); | |
3563 | ||
d44f9b63 | 3564 | req = (struct hclge_promisc_cfg_cmd *)desc.data; |
46a3df9f | 3565 | req->vf_id = param->vf_id; |
96c0e861 PL |
3566 | |
3567 | /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on | |
3568 | * pdev revision(0x20), new revision support them. The | |
3569 | * value of this two fields will not return error when driver | |
3570 | * send command to fireware in revision(0x20). | |
3571 | */ | |
3572 | req->flag = (param->enable << HCLGE_PROMISC_EN_B) | | |
3573 | HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B; | |
46a3df9f S |
3574 | |
3575 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 3576 | if (ret) |
46a3df9f S |
3577 | dev_err(&hdev->pdev->dev, |
3578 | "Set promisc mode fail, status is %d.\n", ret); | |
3f639907 JS |
3579 | |
3580 | return ret; | |
46a3df9f S |
3581 | } |
3582 | ||
3583 | void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, | |
3584 | bool en_mc, bool en_bc, int vport_id) | |
3585 | { | |
3586 | if (!param) | |
3587 | return; | |
3588 | ||
3589 | memset(param, 0, sizeof(struct hclge_promisc_param)); | |
3590 | if (en_uc) | |
3591 | param->enable = HCLGE_PROMISC_EN_UC; | |
3592 | if (en_mc) | |
3593 | param->enable |= HCLGE_PROMISC_EN_MC; | |
3594 | if (en_bc) | |
3595 | param->enable |= HCLGE_PROMISC_EN_BC; | |
3596 | param->vf_id = vport_id; | |
3597 | } | |
3598 | ||
3b75c3df PL |
3599 | static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, |
3600 | bool en_mc_pmc) | |
46a3df9f S |
3601 | { |
3602 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3603 | struct hclge_dev *hdev = vport->back; | |
3604 | struct hclge_promisc_param param; | |
3605 | ||
3b75c3df PL |
3606 | hclge_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, true, |
3607 | vport->vport_id); | |
46a3df9f S |
3608 | hclge_cmd_set_promisc_mode(hdev, ¶m); |
3609 | } | |
3610 | ||
3611 | static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) | |
3612 | { | |
3613 | struct hclge_desc desc; | |
d44f9b63 YL |
3614 | struct hclge_config_mac_mode_cmd *req = |
3615 | (struct hclge_config_mac_mode_cmd *)desc.data; | |
a90bb9a5 | 3616 | u32 loop_en = 0; |
46a3df9f S |
3617 | int ret; |
3618 | ||
3619 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); | |
e4e87715 PL |
3620 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); |
3621 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); | |
3622 | hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); | |
3623 | hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); | |
3624 | hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); | |
3625 | hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); | |
3626 | hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); | |
3627 | hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); | |
3628 | hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); | |
3629 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); | |
3630 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); | |
3631 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); | |
3632 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); | |
3633 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); | |
a90bb9a5 | 3634 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); |
46a3df9f S |
3635 | |
3636 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3637 | if (ret) | |
3638 | dev_err(&hdev->pdev->dev, | |
3639 | "mac enable fail, ret =%d.\n", ret); | |
3640 | } | |
3641 | ||
e4d68dae | 3642 | static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en) |
c39c4d98 | 3643 | { |
c39c4d98 | 3644 | struct hclge_config_mac_mode_cmd *req; |
c39c4d98 YL |
3645 | struct hclge_desc desc; |
3646 | u32 loop_en; | |
3647 | int ret; | |
3648 | ||
e4d68dae YL |
3649 | req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; |
3650 | /* 1 Read out the MAC mode config at first */ | |
3651 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); | |
3652 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3653 | if (ret) { | |
3654 | dev_err(&hdev->pdev->dev, | |
3655 | "mac loopback get fail, ret =%d.\n", ret); | |
3656 | return ret; | |
3657 | } | |
c39c4d98 | 3658 | |
e4d68dae YL |
3659 | /* 2 Then setup the loopback flag */ |
3660 | loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); | |
e4e87715 | 3661 | hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); |
e4d68dae YL |
3662 | |
3663 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); | |
c39c4d98 | 3664 | |
e4d68dae YL |
3665 | /* 3 Config mac work mode with loopback flag |
3666 | * and its original configure parameters | |
3667 | */ | |
3668 | hclge_cmd_reuse_desc(&desc, false); | |
3669 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3670 | if (ret) | |
3671 | dev_err(&hdev->pdev->dev, | |
3672 | "mac loopback set fail, ret =%d.\n", ret); | |
3673 | return ret; | |
3674 | } | |
c39c4d98 | 3675 | |
5fd50ac3 PL |
3676 | static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en) |
3677 | { | |
3678 | #define HCLGE_SERDES_RETRY_MS 10 | |
3679 | #define HCLGE_SERDES_RETRY_NUM 100 | |
3680 | struct hclge_serdes_lb_cmd *req; | |
3681 | struct hclge_desc desc; | |
3682 | int ret, i = 0; | |
3683 | ||
3684 | req = (struct hclge_serdes_lb_cmd *)&desc.data[0]; | |
3685 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false); | |
3686 | ||
3687 | if (en) { | |
3688 | req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; | |
3689 | req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; | |
3690 | } else { | |
3691 | req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; | |
3692 | } | |
3693 | ||
3694 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3695 | if (ret) { | |
3696 | dev_err(&hdev->pdev->dev, | |
3697 | "serdes loopback set fail, ret = %d\n", ret); | |
3698 | return ret; | |
3699 | } | |
3700 | ||
3701 | do { | |
3702 | msleep(HCLGE_SERDES_RETRY_MS); | |
3703 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, | |
3704 | true); | |
3705 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3706 | if (ret) { | |
3707 | dev_err(&hdev->pdev->dev, | |
3708 | "serdes loopback get, ret = %d\n", ret); | |
3709 | return ret; | |
3710 | } | |
3711 | } while (++i < HCLGE_SERDES_RETRY_NUM && | |
3712 | !(req->result & HCLGE_CMD_SERDES_DONE_B)); | |
3713 | ||
3714 | if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) { | |
3715 | dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n"); | |
3716 | return -EBUSY; | |
3717 | } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) { | |
3718 | dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n"); | |
3719 | return -EIO; | |
3720 | } | |
3721 | ||
3722 | return 0; | |
3723 | } | |
3724 | ||
e4d68dae YL |
3725 | static int hclge_set_loopback(struct hnae3_handle *handle, |
3726 | enum hnae3_loop loop_mode, bool en) | |
3727 | { | |
3728 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3729 | struct hclge_dev *hdev = vport->back; | |
3730 | int ret; | |
3731 | ||
3732 | switch (loop_mode) { | |
3733 | case HNAE3_MAC_INTER_LOOP_MAC: | |
3734 | ret = hclge_set_mac_loopback(hdev, en); | |
c39c4d98 | 3735 | break; |
5fd50ac3 PL |
3736 | case HNAE3_MAC_INTER_LOOP_SERDES: |
3737 | ret = hclge_set_serdes_loopback(hdev, en); | |
3738 | break; | |
c39c4d98 YL |
3739 | default: |
3740 | ret = -ENOTSUPP; | |
3741 | dev_err(&hdev->pdev->dev, | |
3742 | "loop_mode %d is not supported\n", loop_mode); | |
3743 | break; | |
3744 | } | |
3745 | ||
3746 | return ret; | |
3747 | } | |
3748 | ||
46a3df9f S |
3749 | static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, |
3750 | int stream_id, bool enable) | |
3751 | { | |
3752 | struct hclge_desc desc; | |
d44f9b63 YL |
3753 | struct hclge_cfg_com_tqp_queue_cmd *req = |
3754 | (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; | |
46a3df9f S |
3755 | int ret; |
3756 | ||
3757 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); | |
3758 | req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); | |
3759 | req->stream_id = cpu_to_le16(stream_id); | |
3760 | req->enable |= enable << HCLGE_TQP_ENABLE_B; | |
3761 | ||
3762 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3763 | if (ret) | |
3764 | dev_err(&hdev->pdev->dev, | |
3765 | "Tqp enable fail, status =%d.\n", ret); | |
3766 | return ret; | |
3767 | } | |
3768 | ||
3769 | static void hclge_reset_tqp_stats(struct hnae3_handle *handle) | |
3770 | { | |
3771 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3772 | struct hnae3_queue *queue; | |
3773 | struct hclge_tqp *tqp; | |
3774 | int i; | |
3775 | ||
3776 | for (i = 0; i < vport->alloc_tqps; i++) { | |
3777 | queue = handle->kinfo.tqp[i]; | |
3778 | tqp = container_of(queue, struct hclge_tqp, q); | |
3779 | memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); | |
3780 | } | |
3781 | } | |
3782 | ||
3783 | static int hclge_ae_start(struct hnae3_handle *handle) | |
3784 | { | |
3785 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3786 | struct hclge_dev *hdev = vport->back; | |
b01b7cf1 | 3787 | int i; |
46a3df9f | 3788 | |
814e0274 PL |
3789 | for (i = 0; i < vport->alloc_tqps; i++) |
3790 | hclge_tqp_enable(hdev, i, 0, true); | |
46a3df9f | 3791 | |
46a3df9f S |
3792 | /* mac enable */ |
3793 | hclge_cfg_mac_mode(hdev, true); | |
3794 | clear_bit(HCLGE_STATE_DOWN, &hdev->state); | |
d039ef68 | 3795 | mod_timer(&hdev->service_timer, jiffies + HZ); |
be8d8cdb | 3796 | hdev->hw.mac.link = 0; |
46a3df9f | 3797 | |
b50ae26c PL |
3798 | /* reset tqp stats */ |
3799 | hclge_reset_tqp_stats(handle); | |
3800 | ||
b01b7cf1 | 3801 | hclge_mac_start_phy(hdev); |
46a3df9f | 3802 | |
46a3df9f S |
3803 | return 0; |
3804 | } | |
3805 | ||
3806 | static void hclge_ae_stop(struct hnae3_handle *handle) | |
3807 | { | |
3808 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3809 | struct hclge_dev *hdev = vport->back; | |
814e0274 | 3810 | int i; |
46a3df9f | 3811 | |
b50ae26c PL |
3812 | del_timer_sync(&hdev->service_timer); |
3813 | cancel_work_sync(&hdev->service_task); | |
f5be7967 | 3814 | clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); |
b50ae26c | 3815 | |
9617f668 YL |
3816 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { |
3817 | hclge_mac_stop_phy(hdev); | |
b50ae26c | 3818 | return; |
9617f668 | 3819 | } |
b50ae26c | 3820 | |
814e0274 PL |
3821 | for (i = 0; i < vport->alloc_tqps; i++) |
3822 | hclge_tqp_enable(hdev, i, 0, false); | |
46a3df9f | 3823 | |
46a3df9f S |
3824 | /* Mac disable */ |
3825 | hclge_cfg_mac_mode(hdev, false); | |
3826 | ||
3827 | hclge_mac_stop_phy(hdev); | |
3828 | ||
3829 | /* reset tqp stats */ | |
3830 | hclge_reset_tqp_stats(handle); | |
f30dfddc FL |
3831 | del_timer_sync(&hdev->service_timer); |
3832 | cancel_work_sync(&hdev->service_task); | |
3833 | hclge_update_link_status(hdev); | |
46a3df9f S |
3834 | } |
3835 | ||
3836 | static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, | |
3837 | u16 cmdq_resp, u8 resp_code, | |
3838 | enum hclge_mac_vlan_tbl_opcode op) | |
3839 | { | |
3840 | struct hclge_dev *hdev = vport->back; | |
3841 | int return_status = -EIO; | |
3842 | ||
3843 | if (cmdq_resp) { | |
3844 | dev_err(&hdev->pdev->dev, | |
3845 | "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", | |
3846 | cmdq_resp); | |
3847 | return -EIO; | |
3848 | } | |
3849 | ||
3850 | if (op == HCLGE_MAC_VLAN_ADD) { | |
3851 | if ((!resp_code) || (resp_code == 1)) { | |
3852 | return_status = 0; | |
3853 | } else if (resp_code == 2) { | |
eefd00a5 | 3854 | return_status = -ENOSPC; |
46a3df9f S |
3855 | dev_err(&hdev->pdev->dev, |
3856 | "add mac addr failed for uc_overflow.\n"); | |
3857 | } else if (resp_code == 3) { | |
eefd00a5 | 3858 | return_status = -ENOSPC; |
46a3df9f S |
3859 | dev_err(&hdev->pdev->dev, |
3860 | "add mac addr failed for mc_overflow.\n"); | |
3861 | } else { | |
3862 | dev_err(&hdev->pdev->dev, | |
3863 | "add mac addr failed for undefined, code=%d.\n", | |
3864 | resp_code); | |
3865 | } | |
3866 | } else if (op == HCLGE_MAC_VLAN_REMOVE) { | |
3867 | if (!resp_code) { | |
3868 | return_status = 0; | |
3869 | } else if (resp_code == 1) { | |
eefd00a5 | 3870 | return_status = -ENOENT; |
46a3df9f S |
3871 | dev_dbg(&hdev->pdev->dev, |
3872 | "remove mac addr failed for miss.\n"); | |
3873 | } else { | |
3874 | dev_err(&hdev->pdev->dev, | |
3875 | "remove mac addr failed for undefined, code=%d.\n", | |
3876 | resp_code); | |
3877 | } | |
3878 | } else if (op == HCLGE_MAC_VLAN_LKUP) { | |
3879 | if (!resp_code) { | |
3880 | return_status = 0; | |
3881 | } else if (resp_code == 1) { | |
eefd00a5 | 3882 | return_status = -ENOENT; |
46a3df9f S |
3883 | dev_dbg(&hdev->pdev->dev, |
3884 | "lookup mac addr failed for miss.\n"); | |
3885 | } else { | |
3886 | dev_err(&hdev->pdev->dev, | |
3887 | "lookup mac addr failed for undefined, code=%d.\n", | |
3888 | resp_code); | |
3889 | } | |
3890 | } else { | |
eefd00a5 | 3891 | return_status = -EINVAL; |
46a3df9f S |
3892 | dev_err(&hdev->pdev->dev, |
3893 | "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", | |
3894 | op); | |
3895 | } | |
3896 | ||
3897 | return return_status; | |
3898 | } | |
3899 | ||
3900 | static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) | |
3901 | { | |
3902 | int word_num; | |
3903 | int bit_num; | |
3904 | ||
3905 | if (vfid > 255 || vfid < 0) | |
3906 | return -EIO; | |
3907 | ||
3908 | if (vfid >= 0 && vfid <= 191) { | |
3909 | word_num = vfid / 32; | |
3910 | bit_num = vfid % 32; | |
3911 | if (clr) | |
a90bb9a5 | 3912 | desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); |
46a3df9f | 3913 | else |
a90bb9a5 | 3914 | desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); |
46a3df9f S |
3915 | } else { |
3916 | word_num = (vfid - 192) / 32; | |
3917 | bit_num = vfid % 32; | |
3918 | if (clr) | |
a90bb9a5 | 3919 | desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); |
46a3df9f | 3920 | else |
a90bb9a5 | 3921 | desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); |
46a3df9f S |
3922 | } |
3923 | ||
3924 | return 0; | |
3925 | } | |
3926 | ||
3927 | static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) | |
3928 | { | |
3929 | #define HCLGE_DESC_NUMBER 3 | |
3930 | #define HCLGE_FUNC_NUMBER_PER_DESC 6 | |
3931 | int i, j; | |
3932 | ||
6c39d527 | 3933 | for (i = 1; i < HCLGE_DESC_NUMBER; i++) |
46a3df9f S |
3934 | for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) |
3935 | if (desc[i].data[j]) | |
3936 | return false; | |
3937 | ||
3938 | return true; | |
3939 | } | |
3940 | ||
d44f9b63 | 3941 | static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, |
46a3df9f S |
3942 | const u8 *addr) |
3943 | { | |
3944 | const unsigned char *mac_addr = addr; | |
3945 | u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | | |
3946 | (mac_addr[0]) | (mac_addr[1] << 8); | |
3947 | u32 low_val = mac_addr[4] | (mac_addr[5] << 8); | |
3948 | ||
3949 | new_req->mac_addr_hi32 = cpu_to_le32(high_val); | |
3950 | new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); | |
3951 | } | |
3952 | ||
1db9b1bf YL |
3953 | static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport, |
3954 | const u8 *addr) | |
46a3df9f S |
3955 | { |
3956 | u16 high_val = addr[1] | (addr[0] << 8); | |
3957 | struct hclge_dev *hdev = vport->back; | |
3958 | u32 rsh = 4 - hdev->mta_mac_sel_type; | |
3959 | u16 ret_val = (high_val >> rsh) & 0xfff; | |
3960 | ||
3961 | return ret_val; | |
3962 | } | |
3963 | ||
3964 | static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, | |
3965 | enum hclge_mta_dmac_sel_type mta_mac_sel, | |
3966 | bool enable) | |
3967 | { | |
d44f9b63 | 3968 | struct hclge_mta_filter_mode_cmd *req; |
46a3df9f S |
3969 | struct hclge_desc desc; |
3970 | int ret; | |
3971 | ||
d44f9b63 | 3972 | req = (struct hclge_mta_filter_mode_cmd *)desc.data; |
46a3df9f S |
3973 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false); |
3974 | ||
e4e87715 PL |
3975 | hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B, |
3976 | enable); | |
3977 | hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M, | |
3978 | HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel); | |
46a3df9f S |
3979 | |
3980 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 3981 | if (ret) |
46a3df9f S |
3982 | dev_err(&hdev->pdev->dev, |
3983 | "Config mat filter mode failed for cmd_send, ret =%d.\n", | |
3984 | ret); | |
46a3df9f | 3985 | |
3f639907 | 3986 | return ret; |
46a3df9f S |
3987 | } |
3988 | ||
3989 | int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, | |
3990 | u8 func_id, | |
3991 | bool enable) | |
3992 | { | |
d44f9b63 | 3993 | struct hclge_cfg_func_mta_filter_cmd *req; |
46a3df9f S |
3994 | struct hclge_desc desc; |
3995 | int ret; | |
3996 | ||
d44f9b63 | 3997 | req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data; |
46a3df9f S |
3998 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false); |
3999 | ||
e4e87715 PL |
4000 | hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B, |
4001 | enable); | |
46a3df9f S |
4002 | req->function_id = func_id; |
4003 | ||
4004 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 4005 | if (ret) |
46a3df9f S |
4006 | dev_err(&hdev->pdev->dev, |
4007 | "Config func_id enable failed for cmd_send, ret =%d.\n", | |
4008 | ret); | |
46a3df9f | 4009 | |
3f639907 | 4010 | return ret; |
46a3df9f S |
4011 | } |
4012 | ||
4013 | static int hclge_set_mta_table_item(struct hclge_vport *vport, | |
4014 | u16 idx, | |
4015 | bool enable) | |
4016 | { | |
4017 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4018 | struct hclge_cfg_func_mta_item_cmd *req; |
46a3df9f | 4019 | struct hclge_desc desc; |
a90bb9a5 | 4020 | u16 item_idx = 0; |
46a3df9f S |
4021 | int ret; |
4022 | ||
d44f9b63 | 4023 | req = (struct hclge_cfg_func_mta_item_cmd *)desc.data; |
46a3df9f | 4024 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false); |
e4e87715 | 4025 | hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable); |
46a3df9f | 4026 | |
e4e87715 PL |
4027 | hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M, |
4028 | HCLGE_CFG_MTA_ITEM_IDX_S, idx); | |
a90bb9a5 | 4029 | req->item_idx = cpu_to_le16(item_idx); |
46a3df9f S |
4030 | |
4031 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4032 | if (ret) { | |
4033 | dev_err(&hdev->pdev->dev, | |
4034 | "Config mta table item failed for cmd_send, ret =%d.\n", | |
4035 | ret); | |
4036 | return ret; | |
4037 | } | |
4038 | ||
40cca1c5 XW |
4039 | if (enable) |
4040 | set_bit(idx, vport->mta_shadow); | |
4041 | else | |
4042 | clear_bit(idx, vport->mta_shadow); | |
4043 | ||
46a3df9f S |
4044 | return 0; |
4045 | } | |
4046 | ||
40cca1c5 XW |
4047 | static int hclge_update_mta_status(struct hnae3_handle *handle) |
4048 | { | |
4049 | unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)]; | |
4050 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4051 | struct net_device *netdev = handle->kinfo.netdev; | |
4052 | struct netdev_hw_addr *ha; | |
4053 | u16 tbl_idx; | |
4054 | ||
4055 | memset(mta_status, 0, sizeof(mta_status)); | |
4056 | ||
4057 | /* update mta_status from mc addr list */ | |
4058 | netdev_for_each_mc_addr(ha, netdev) { | |
4059 | tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr); | |
4060 | set_bit(tbl_idx, mta_status); | |
4061 | } | |
4062 | ||
4063 | return hclge_update_mta_status_common(vport, mta_status, | |
4064 | 0, HCLGE_MTA_TBL_SIZE, true); | |
4065 | } | |
4066 | ||
4067 | int hclge_update_mta_status_common(struct hclge_vport *vport, | |
4068 | unsigned long *status, | |
4069 | u16 idx, | |
4070 | u16 count, | |
4071 | bool update_filter) | |
4072 | { | |
4073 | struct hclge_dev *hdev = vport->back; | |
4074 | u16 update_max = idx + count; | |
4075 | u16 check_max; | |
4076 | int ret = 0; | |
4077 | bool used; | |
4078 | u16 i; | |
4079 | ||
4080 | /* setup mta check range */ | |
4081 | if (update_filter) { | |
4082 | i = 0; | |
4083 | check_max = HCLGE_MTA_TBL_SIZE; | |
4084 | } else { | |
4085 | i = idx; | |
4086 | check_max = update_max; | |
4087 | } | |
4088 | ||
4089 | used = false; | |
4090 | /* check and update all mta item */ | |
4091 | for (; i < check_max; i++) { | |
4092 | /* ignore unused item */ | |
4093 | if (!test_bit(i, vport->mta_shadow)) | |
4094 | continue; | |
4095 | ||
4096 | /* if i in update range then update it */ | |
4097 | if (i >= idx && i < update_max) | |
4098 | if (!test_bit(i - idx, status)) | |
4099 | hclge_set_mta_table_item(vport, i, false); | |
4100 | ||
4101 | if (!used && test_bit(i, vport->mta_shadow)) | |
4102 | used = true; | |
4103 | } | |
4104 | ||
4105 | /* no longer use mta, disable it */ | |
4106 | if (vport->accept_mta_mc && update_filter && !used) { | |
4107 | ret = hclge_cfg_func_mta_filter(hdev, | |
4108 | vport->vport_id, | |
4109 | false); | |
4110 | if (ret) | |
4111 | dev_err(&hdev->pdev->dev, | |
4112 | "disable func mta filter fail ret=%d\n", | |
4113 | ret); | |
4114 | else | |
4115 | vport->accept_mta_mc = false; | |
4116 | } | |
4117 | ||
4118 | return ret; | |
4119 | } | |
4120 | ||
46a3df9f | 4121 | static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, |
d44f9b63 | 4122 | struct hclge_mac_vlan_tbl_entry_cmd *req) |
46a3df9f S |
4123 | { |
4124 | struct hclge_dev *hdev = vport->back; | |
4125 | struct hclge_desc desc; | |
4126 | u8 resp_code; | |
a90bb9a5 | 4127 | u16 retval; |
46a3df9f S |
4128 | int ret; |
4129 | ||
4130 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); | |
4131 | ||
d44f9b63 | 4132 | memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4133 | |
4134 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4135 | if (ret) { | |
4136 | dev_err(&hdev->pdev->dev, | |
4137 | "del mac addr failed for cmd_send, ret =%d.\n", | |
4138 | ret); | |
4139 | return ret; | |
4140 | } | |
a90bb9a5 YL |
4141 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
4142 | retval = le16_to_cpu(desc.retval); | |
46a3df9f | 4143 | |
a90bb9a5 | 4144 | return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, |
46a3df9f S |
4145 | HCLGE_MAC_VLAN_REMOVE); |
4146 | } | |
4147 | ||
4148 | static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, | |
d44f9b63 | 4149 | struct hclge_mac_vlan_tbl_entry_cmd *req, |
46a3df9f S |
4150 | struct hclge_desc *desc, |
4151 | bool is_mc) | |
4152 | { | |
4153 | struct hclge_dev *hdev = vport->back; | |
4154 | u8 resp_code; | |
a90bb9a5 | 4155 | u16 retval; |
46a3df9f S |
4156 | int ret; |
4157 | ||
4158 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); | |
4159 | if (is_mc) { | |
4160 | desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4161 | memcpy(desc[0].data, | |
4162 | req, | |
d44f9b63 | 4163 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4164 | hclge_cmd_setup_basic_desc(&desc[1], |
4165 | HCLGE_OPC_MAC_VLAN_ADD, | |
4166 | true); | |
4167 | desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4168 | hclge_cmd_setup_basic_desc(&desc[2], | |
4169 | HCLGE_OPC_MAC_VLAN_ADD, | |
4170 | true); | |
4171 | ret = hclge_cmd_send(&hdev->hw, desc, 3); | |
4172 | } else { | |
4173 | memcpy(desc[0].data, | |
4174 | req, | |
d44f9b63 | 4175 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4176 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
4177 | } | |
4178 | if (ret) { | |
4179 | dev_err(&hdev->pdev->dev, | |
4180 | "lookup mac addr failed for cmd_send, ret =%d.\n", | |
4181 | ret); | |
4182 | return ret; | |
4183 | } | |
a90bb9a5 YL |
4184 | resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; |
4185 | retval = le16_to_cpu(desc[0].retval); | |
46a3df9f | 4186 | |
a90bb9a5 | 4187 | return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, |
46a3df9f S |
4188 | HCLGE_MAC_VLAN_LKUP); |
4189 | } | |
4190 | ||
4191 | static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, | |
d44f9b63 | 4192 | struct hclge_mac_vlan_tbl_entry_cmd *req, |
46a3df9f S |
4193 | struct hclge_desc *mc_desc) |
4194 | { | |
4195 | struct hclge_dev *hdev = vport->back; | |
4196 | int cfg_status; | |
4197 | u8 resp_code; | |
a90bb9a5 | 4198 | u16 retval; |
46a3df9f S |
4199 | int ret; |
4200 | ||
4201 | if (!mc_desc) { | |
4202 | struct hclge_desc desc; | |
4203 | ||
4204 | hclge_cmd_setup_basic_desc(&desc, | |
4205 | HCLGE_OPC_MAC_VLAN_ADD, | |
4206 | false); | |
d44f9b63 YL |
4207 | memcpy(desc.data, req, |
4208 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); | |
46a3df9f | 4209 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
a90bb9a5 YL |
4210 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
4211 | retval = le16_to_cpu(desc.retval); | |
4212 | ||
4213 | cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, | |
46a3df9f S |
4214 | resp_code, |
4215 | HCLGE_MAC_VLAN_ADD); | |
4216 | } else { | |
c3b6f755 | 4217 | hclge_cmd_reuse_desc(&mc_desc[0], false); |
46a3df9f | 4218 | mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
c3b6f755 | 4219 | hclge_cmd_reuse_desc(&mc_desc[1], false); |
46a3df9f | 4220 | mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
c3b6f755 | 4221 | hclge_cmd_reuse_desc(&mc_desc[2], false); |
46a3df9f S |
4222 | mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); |
4223 | memcpy(mc_desc[0].data, req, | |
d44f9b63 | 4224 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f | 4225 | ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); |
a90bb9a5 YL |
4226 | resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; |
4227 | retval = le16_to_cpu(mc_desc[0].retval); | |
4228 | ||
4229 | cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, | |
46a3df9f S |
4230 | resp_code, |
4231 | HCLGE_MAC_VLAN_ADD); | |
4232 | } | |
4233 | ||
4234 | if (ret) { | |
4235 | dev_err(&hdev->pdev->dev, | |
4236 | "add mac addr failed for cmd_send, ret =%d.\n", | |
4237 | ret); | |
4238 | return ret; | |
4239 | } | |
4240 | ||
4241 | return cfg_status; | |
4242 | } | |
4243 | ||
4244 | static int hclge_add_uc_addr(struct hnae3_handle *handle, | |
4245 | const unsigned char *addr) | |
4246 | { | |
4247 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4248 | ||
4249 | return hclge_add_uc_addr_common(vport, addr); | |
4250 | } | |
4251 | ||
4252 | int hclge_add_uc_addr_common(struct hclge_vport *vport, | |
4253 | const unsigned char *addr) | |
4254 | { | |
4255 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4256 | struct hclge_mac_vlan_tbl_entry_cmd req; |
d07b6bb4 | 4257 | struct hclge_desc desc; |
a90bb9a5 | 4258 | u16 egress_port = 0; |
aa7a795e | 4259 | int ret; |
46a3df9f S |
4260 | |
4261 | /* mac addr check */ | |
4262 | if (is_zero_ether_addr(addr) || | |
4263 | is_broadcast_ether_addr(addr) || | |
4264 | is_multicast_ether_addr(addr)) { | |
4265 | dev_err(&hdev->pdev->dev, | |
4266 | "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", | |
4267 | addr, | |
4268 | is_zero_ether_addr(addr), | |
4269 | is_broadcast_ether_addr(addr), | |
4270 | is_multicast_ether_addr(addr)); | |
4271 | return -EINVAL; | |
4272 | } | |
4273 | ||
4274 | memset(&req, 0, sizeof(req)); | |
e4e87715 | 4275 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
a90bb9a5 | 4276 | |
e4e87715 PL |
4277 | hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, |
4278 | HCLGE_MAC_EPORT_VFID_S, vport->vport_id); | |
a90bb9a5 YL |
4279 | |
4280 | req.egress_port = cpu_to_le16(egress_port); | |
46a3df9f S |
4281 | |
4282 | hclge_prepare_mac_addr(&req, addr); | |
4283 | ||
d07b6bb4 JS |
4284 | /* Lookup the mac address in the mac_vlan table, and add |
4285 | * it if the entry is inexistent. Repeated unicast entry | |
4286 | * is not allowed in the mac vlan table. | |
4287 | */ | |
4288 | ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); | |
4289 | if (ret == -ENOENT) | |
4290 | return hclge_add_mac_vlan_tbl(vport, &req, NULL); | |
4291 | ||
4292 | /* check if we just hit the duplicate */ | |
4293 | if (!ret) | |
4294 | ret = -EINVAL; | |
4295 | ||
4296 | dev_err(&hdev->pdev->dev, | |
4297 | "PF failed to add unicast entry(%pM) in the MAC table\n", | |
4298 | addr); | |
46a3df9f | 4299 | |
aa7a795e | 4300 | return ret; |
46a3df9f S |
4301 | } |
4302 | ||
4303 | static int hclge_rm_uc_addr(struct hnae3_handle *handle, | |
4304 | const unsigned char *addr) | |
4305 | { | |
4306 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4307 | ||
4308 | return hclge_rm_uc_addr_common(vport, addr); | |
4309 | } | |
4310 | ||
4311 | int hclge_rm_uc_addr_common(struct hclge_vport *vport, | |
4312 | const unsigned char *addr) | |
4313 | { | |
4314 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4315 | struct hclge_mac_vlan_tbl_entry_cmd req; |
aa7a795e | 4316 | int ret; |
46a3df9f S |
4317 | |
4318 | /* mac addr check */ | |
4319 | if (is_zero_ether_addr(addr) || | |
4320 | is_broadcast_ether_addr(addr) || | |
4321 | is_multicast_ether_addr(addr)) { | |
4322 | dev_dbg(&hdev->pdev->dev, | |
4323 | "Remove mac err! invalid mac:%pM.\n", | |
4324 | addr); | |
4325 | return -EINVAL; | |
4326 | } | |
4327 | ||
4328 | memset(&req, 0, sizeof(req)); | |
e4e87715 PL |
4329 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
4330 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
46a3df9f | 4331 | hclge_prepare_mac_addr(&req, addr); |
aa7a795e | 4332 | ret = hclge_remove_mac_vlan_tbl(vport, &req); |
46a3df9f | 4333 | |
aa7a795e | 4334 | return ret; |
46a3df9f S |
4335 | } |
4336 | ||
4337 | static int hclge_add_mc_addr(struct hnae3_handle *handle, | |
4338 | const unsigned char *addr) | |
4339 | { | |
4340 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4341 | ||
a10829c4 | 4342 | return hclge_add_mc_addr_common(vport, addr); |
46a3df9f S |
4343 | } |
4344 | ||
4345 | int hclge_add_mc_addr_common(struct hclge_vport *vport, | |
4346 | const unsigned char *addr) | |
4347 | { | |
4348 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4349 | struct hclge_mac_vlan_tbl_entry_cmd req; |
46a3df9f S |
4350 | struct hclge_desc desc[3]; |
4351 | u16 tbl_idx; | |
4352 | int status; | |
4353 | ||
4354 | /* mac addr check */ | |
4355 | if (!is_multicast_ether_addr(addr)) { | |
4356 | dev_err(&hdev->pdev->dev, | |
4357 | "Add mc mac err! invalid mac:%pM.\n", | |
4358 | addr); | |
4359 | return -EINVAL; | |
4360 | } | |
4361 | memset(&req, 0, sizeof(req)); | |
e4e87715 PL |
4362 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
4363 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4364 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); | |
4365 | hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
46a3df9f S |
4366 | hclge_prepare_mac_addr(&req, addr); |
4367 | status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); | |
4368 | if (!status) { | |
4369 | /* This mac addr exist, update VFID for it */ | |
4370 | hclge_update_desc_vfid(desc, vport->vport_id, false); | |
4371 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4372 | } else { | |
4373 | /* This mac addr do not exist, add new entry for it */ | |
4374 | memset(desc[0].data, 0, sizeof(desc[0].data)); | |
4375 | memset(desc[1].data, 0, sizeof(desc[0].data)); | |
4376 | memset(desc[2].data, 0, sizeof(desc[0].data)); | |
4377 | hclge_update_desc_vfid(desc, vport->vport_id, false); | |
4378 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4379 | } | |
4380 | ||
40cca1c5 XW |
4381 | /* If mc mac vlan table is full, use MTA table */ |
4382 | if (status == -ENOSPC) { | |
4383 | if (!vport->accept_mta_mc) { | |
4384 | status = hclge_cfg_func_mta_filter(hdev, | |
4385 | vport->vport_id, | |
4386 | true); | |
4387 | if (status) { | |
4388 | dev_err(&hdev->pdev->dev, | |
4389 | "set mta filter mode fail ret=%d\n", | |
4390 | status); | |
4391 | return status; | |
4392 | } | |
4393 | vport->accept_mta_mc = true; | |
4394 | } | |
4395 | ||
4396 | /* Set MTA table for this MAC address */ | |
4397 | tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); | |
4398 | status = hclge_set_mta_table_item(vport, tbl_idx, true); | |
4399 | } | |
46a3df9f S |
4400 | |
4401 | return status; | |
4402 | } | |
4403 | ||
4404 | static int hclge_rm_mc_addr(struct hnae3_handle *handle, | |
4405 | const unsigned char *addr) | |
4406 | { | |
4407 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4408 | ||
4409 | return hclge_rm_mc_addr_common(vport, addr); | |
4410 | } | |
4411 | ||
4412 | int hclge_rm_mc_addr_common(struct hclge_vport *vport, | |
4413 | const unsigned char *addr) | |
4414 | { | |
4415 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4416 | struct hclge_mac_vlan_tbl_entry_cmd req; |
46a3df9f S |
4417 | enum hclge_cmd_status status; |
4418 | struct hclge_desc desc[3]; | |
46a3df9f S |
4419 | |
4420 | /* mac addr check */ | |
4421 | if (!is_multicast_ether_addr(addr)) { | |
4422 | dev_dbg(&hdev->pdev->dev, | |
4423 | "Remove mc mac err! invalid mac:%pM.\n", | |
4424 | addr); | |
4425 | return -EINVAL; | |
4426 | } | |
4427 | ||
4428 | memset(&req, 0, sizeof(req)); | |
e4e87715 PL |
4429 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
4430 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4431 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); | |
4432 | hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
46a3df9f S |
4433 | hclge_prepare_mac_addr(&req, addr); |
4434 | status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); | |
4435 | if (!status) { | |
4436 | /* This mac addr exist, remove this handle's VFID for it */ | |
4437 | hclge_update_desc_vfid(desc, vport->vport_id, true); | |
4438 | ||
4439 | if (hclge_is_all_function_id_zero(desc)) | |
4440 | /* All the vfid is zero, so need to delete this entry */ | |
4441 | status = hclge_remove_mac_vlan_tbl(vport, &req); | |
4442 | else | |
4443 | /* Not all the vfid is zero, update the vfid */ | |
4444 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4445 | ||
4446 | } else { | |
40cca1c5 XW |
4447 | /* Maybe this mac address is in mta table, but it cannot be |
4448 | * deleted here because an entry of mta represents an address | |
4449 | * range rather than a specific address. the delete action to | |
4450 | * all entries will take effect in update_mta_status called by | |
4451 | * hns3_nic_set_rx_mode. | |
4452 | */ | |
4453 | status = 0; | |
46a3df9f S |
4454 | } |
4455 | ||
46a3df9f S |
4456 | return status; |
4457 | } | |
4458 | ||
f5aac71c FL |
4459 | static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, |
4460 | u16 cmdq_resp, u8 resp_code) | |
4461 | { | |
4462 | #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 | |
4463 | #define HCLGE_ETHERTYPE_ALREADY_ADD 1 | |
4464 | #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 | |
4465 | #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 | |
4466 | ||
4467 | int return_status; | |
4468 | ||
4469 | if (cmdq_resp) { | |
4470 | dev_err(&hdev->pdev->dev, | |
4471 | "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", | |
4472 | cmdq_resp); | |
4473 | return -EIO; | |
4474 | } | |
4475 | ||
4476 | switch (resp_code) { | |
4477 | case HCLGE_ETHERTYPE_SUCCESS_ADD: | |
4478 | case HCLGE_ETHERTYPE_ALREADY_ADD: | |
4479 | return_status = 0; | |
4480 | break; | |
4481 | case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: | |
4482 | dev_err(&hdev->pdev->dev, | |
4483 | "add mac ethertype failed for manager table overflow.\n"); | |
4484 | return_status = -EIO; | |
4485 | break; | |
4486 | case HCLGE_ETHERTYPE_KEY_CONFLICT: | |
4487 | dev_err(&hdev->pdev->dev, | |
4488 | "add mac ethertype failed for key conflict.\n"); | |
4489 | return_status = -EIO; | |
4490 | break; | |
4491 | default: | |
4492 | dev_err(&hdev->pdev->dev, | |
4493 | "add mac ethertype failed for undefined, code=%d.\n", | |
4494 | resp_code); | |
4495 | return_status = -EIO; | |
4496 | } | |
4497 | ||
4498 | return return_status; | |
4499 | } | |
4500 | ||
4501 | static int hclge_add_mgr_tbl(struct hclge_dev *hdev, | |
4502 | const struct hclge_mac_mgr_tbl_entry_cmd *req) | |
4503 | { | |
4504 | struct hclge_desc desc; | |
4505 | u8 resp_code; | |
4506 | u16 retval; | |
4507 | int ret; | |
4508 | ||
4509 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); | |
4510 | memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); | |
4511 | ||
4512 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4513 | if (ret) { | |
4514 | dev_err(&hdev->pdev->dev, | |
4515 | "add mac ethertype failed for cmd_send, ret =%d.\n", | |
4516 | ret); | |
4517 | return ret; | |
4518 | } | |
4519 | ||
4520 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; | |
4521 | retval = le16_to_cpu(desc.retval); | |
4522 | ||
4523 | return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); | |
4524 | } | |
4525 | ||
4526 | static int init_mgr_tbl(struct hclge_dev *hdev) | |
4527 | { | |
4528 | int ret; | |
4529 | int i; | |
4530 | ||
4531 | for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { | |
4532 | ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); | |
4533 | if (ret) { | |
4534 | dev_err(&hdev->pdev->dev, | |
4535 | "add mac ethertype failed, ret =%d.\n", | |
4536 | ret); | |
4537 | return ret; | |
4538 | } | |
4539 | } | |
4540 | ||
4541 | return 0; | |
4542 | } | |
4543 | ||
46a3df9f S |
4544 | static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) |
4545 | { | |
4546 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4547 | struct hclge_dev *hdev = vport->back; | |
4548 | ||
4549 | ether_addr_copy(p, hdev->hw.mac.mac_addr); | |
4550 | } | |
4551 | ||
59098055 FL |
4552 | static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p, |
4553 | bool is_first) | |
46a3df9f S |
4554 | { |
4555 | const unsigned char *new_addr = (const unsigned char *)p; | |
4556 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4557 | struct hclge_dev *hdev = vport->back; | |
18838d0c | 4558 | int ret; |
46a3df9f S |
4559 | |
4560 | /* mac addr check */ | |
4561 | if (is_zero_ether_addr(new_addr) || | |
4562 | is_broadcast_ether_addr(new_addr) || | |
4563 | is_multicast_ether_addr(new_addr)) { | |
4564 | dev_err(&hdev->pdev->dev, | |
4565 | "Change uc mac err! invalid mac:%p.\n", | |
4566 | new_addr); | |
4567 | return -EINVAL; | |
4568 | } | |
4569 | ||
59098055 | 4570 | if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr)) |
18838d0c | 4571 | dev_warn(&hdev->pdev->dev, |
59098055 | 4572 | "remove old uc mac address fail.\n"); |
46a3df9f | 4573 | |
18838d0c FL |
4574 | ret = hclge_add_uc_addr(handle, new_addr); |
4575 | if (ret) { | |
4576 | dev_err(&hdev->pdev->dev, | |
4577 | "add uc mac address fail, ret =%d.\n", | |
4578 | ret); | |
4579 | ||
59098055 FL |
4580 | if (!is_first && |
4581 | hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr)) | |
18838d0c | 4582 | dev_err(&hdev->pdev->dev, |
59098055 | 4583 | "restore uc mac address fail.\n"); |
18838d0c FL |
4584 | |
4585 | return -EIO; | |
46a3df9f S |
4586 | } |
4587 | ||
e98d7183 | 4588 | ret = hclge_pause_addr_cfg(hdev, new_addr); |
18838d0c FL |
4589 | if (ret) { |
4590 | dev_err(&hdev->pdev->dev, | |
4591 | "configure mac pause address fail, ret =%d.\n", | |
4592 | ret); | |
4593 | return -EIO; | |
4594 | } | |
4595 | ||
4596 | ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); | |
4597 | ||
4598 | return 0; | |
46a3df9f S |
4599 | } |
4600 | ||
4601 | static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, | |
4602 | bool filter_en) | |
4603 | { | |
d44f9b63 | 4604 | struct hclge_vlan_filter_ctrl_cmd *req; |
46a3df9f S |
4605 | struct hclge_desc desc; |
4606 | int ret; | |
4607 | ||
4608 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); | |
4609 | ||
d44f9b63 | 4610 | req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; |
46a3df9f S |
4611 | req->vlan_type = vlan_type; |
4612 | req->vlan_fe = filter_en; | |
4613 | ||
4614 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 4615 | if (ret) |
46a3df9f S |
4616 | dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", |
4617 | ret); | |
46a3df9f | 4618 | |
3f639907 | 4619 | return ret; |
46a3df9f S |
4620 | } |
4621 | ||
391b5e93 JS |
4622 | #define HCLGE_FILTER_TYPE_VF 0 |
4623 | #define HCLGE_FILTER_TYPE_PORT 1 | |
4624 | ||
4625 | static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) | |
4626 | { | |
4627 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4628 | struct hclge_dev *hdev = vport->back; | |
4629 | ||
4630 | hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); | |
4631 | } | |
4632 | ||
dc8131d8 YL |
4633 | static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, |
4634 | bool is_kill, u16 vlan, u8 qos, | |
4635 | __be16 proto) | |
46a3df9f S |
4636 | { |
4637 | #define HCLGE_MAX_VF_BYTES 16 | |
d44f9b63 YL |
4638 | struct hclge_vlan_filter_vf_cfg_cmd *req0; |
4639 | struct hclge_vlan_filter_vf_cfg_cmd *req1; | |
46a3df9f S |
4640 | struct hclge_desc desc[2]; |
4641 | u8 vf_byte_val; | |
4642 | u8 vf_byte_off; | |
4643 | int ret; | |
4644 | ||
4645 | hclge_cmd_setup_basic_desc(&desc[0], | |
4646 | HCLGE_OPC_VLAN_FILTER_VF_CFG, false); | |
4647 | hclge_cmd_setup_basic_desc(&desc[1], | |
4648 | HCLGE_OPC_VLAN_FILTER_VF_CFG, false); | |
4649 | ||
4650 | desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4651 | ||
4652 | vf_byte_off = vfid / 8; | |
4653 | vf_byte_val = 1 << (vfid % 8); | |
4654 | ||
d44f9b63 YL |
4655 | req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; |
4656 | req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; | |
46a3df9f | 4657 | |
a90bb9a5 | 4658 | req0->vlan_id = cpu_to_le16(vlan); |
46a3df9f S |
4659 | req0->vlan_cfg = is_kill; |
4660 | ||
4661 | if (vf_byte_off < HCLGE_MAX_VF_BYTES) | |
4662 | req0->vf_bitmap[vf_byte_off] = vf_byte_val; | |
4663 | else | |
4664 | req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; | |
4665 | ||
4666 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
4667 | if (ret) { | |
4668 | dev_err(&hdev->pdev->dev, | |
4669 | "Send vf vlan command fail, ret =%d.\n", | |
4670 | ret); | |
4671 | return ret; | |
4672 | } | |
4673 | ||
4674 | if (!is_kill) { | |
6c251711 | 4675 | #define HCLGE_VF_VLAN_NO_ENTRY 2 |
46a3df9f S |
4676 | if (!req0->resp_code || req0->resp_code == 1) |
4677 | return 0; | |
4678 | ||
6c251711 YL |
4679 | if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { |
4680 | dev_warn(&hdev->pdev->dev, | |
4681 | "vf vlan table is full, vf vlan filter is disabled\n"); | |
4682 | return 0; | |
4683 | } | |
4684 | ||
46a3df9f S |
4685 | dev_err(&hdev->pdev->dev, |
4686 | "Add vf vlan filter fail, ret =%d.\n", | |
4687 | req0->resp_code); | |
4688 | } else { | |
41dafea2 | 4689 | #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 |
46a3df9f S |
4690 | if (!req0->resp_code) |
4691 | return 0; | |
4692 | ||
41dafea2 YL |
4693 | if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) { |
4694 | dev_warn(&hdev->pdev->dev, | |
4695 | "vlan %d filter is not in vf vlan table\n", | |
4696 | vlan); | |
4697 | return 0; | |
4698 | } | |
4699 | ||
46a3df9f S |
4700 | dev_err(&hdev->pdev->dev, |
4701 | "Kill vf vlan filter fail, ret =%d.\n", | |
4702 | req0->resp_code); | |
4703 | } | |
4704 | ||
4705 | return -EIO; | |
4706 | } | |
4707 | ||
dc8131d8 YL |
4708 | static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, |
4709 | u16 vlan_id, bool is_kill) | |
46a3df9f | 4710 | { |
d44f9b63 | 4711 | struct hclge_vlan_filter_pf_cfg_cmd *req; |
46a3df9f S |
4712 | struct hclge_desc desc; |
4713 | u8 vlan_offset_byte_val; | |
4714 | u8 vlan_offset_byte; | |
4715 | u8 vlan_offset_160; | |
4716 | int ret; | |
4717 | ||
4718 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); | |
4719 | ||
4720 | vlan_offset_160 = vlan_id / 160; | |
4721 | vlan_offset_byte = (vlan_id % 160) / 8; | |
4722 | vlan_offset_byte_val = 1 << (vlan_id % 8); | |
4723 | ||
d44f9b63 | 4724 | req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; |
46a3df9f S |
4725 | req->vlan_offset = vlan_offset_160; |
4726 | req->vlan_cfg = is_kill; | |
4727 | req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; | |
4728 | ||
4729 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
dc8131d8 YL |
4730 | if (ret) |
4731 | dev_err(&hdev->pdev->dev, | |
4732 | "port vlan command, send fail, ret =%d.\n", ret); | |
4733 | return ret; | |
4734 | } | |
4735 | ||
4736 | static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, | |
4737 | u16 vport_id, u16 vlan_id, u8 qos, | |
4738 | bool is_kill) | |
4739 | { | |
4740 | u16 vport_idx, vport_num = 0; | |
4741 | int ret; | |
4742 | ||
4743 | ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id, | |
4744 | 0, proto); | |
46a3df9f S |
4745 | if (ret) { |
4746 | dev_err(&hdev->pdev->dev, | |
dc8131d8 YL |
4747 | "Set %d vport vlan filter config fail, ret =%d.\n", |
4748 | vport_id, ret); | |
46a3df9f S |
4749 | return ret; |
4750 | } | |
4751 | ||
dc8131d8 YL |
4752 | /* vlan 0 may be added twice when 8021q module is enabled */ |
4753 | if (!is_kill && !vlan_id && | |
4754 | test_bit(vport_id, hdev->vlan_table[vlan_id])) | |
4755 | return 0; | |
4756 | ||
4757 | if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { | |
46a3df9f | 4758 | dev_err(&hdev->pdev->dev, |
dc8131d8 YL |
4759 | "Add port vlan failed, vport %d is already in vlan %d\n", |
4760 | vport_id, vlan_id); | |
4761 | return -EINVAL; | |
46a3df9f S |
4762 | } |
4763 | ||
dc8131d8 YL |
4764 | if (is_kill && |
4765 | !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { | |
4766 | dev_err(&hdev->pdev->dev, | |
4767 | "Delete port vlan failed, vport %d is not in vlan %d\n", | |
4768 | vport_id, vlan_id); | |
4769 | return -EINVAL; | |
4770 | } | |
4771 | ||
4772 | for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID) | |
4773 | vport_num++; | |
4774 | ||
4775 | if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) | |
4776 | ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, | |
4777 | is_kill); | |
4778 | ||
4779 | return ret; | |
4780 | } | |
4781 | ||
4782 | int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, | |
4783 | u16 vlan_id, bool is_kill) | |
4784 | { | |
4785 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4786 | struct hclge_dev *hdev = vport->back; | |
4787 | ||
4788 | return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id, | |
4789 | 0, is_kill); | |
46a3df9f S |
4790 | } |
4791 | ||
4792 | static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, | |
4793 | u16 vlan, u8 qos, __be16 proto) | |
4794 | { | |
4795 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4796 | struct hclge_dev *hdev = vport->back; | |
4797 | ||
4798 | if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) | |
4799 | return -EINVAL; | |
4800 | if (proto != htons(ETH_P_8021Q)) | |
4801 | return -EPROTONOSUPPORT; | |
4802 | ||
dc8131d8 | 4803 | return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false); |
46a3df9f S |
4804 | } |
4805 | ||
5f6ea83f PL |
4806 | static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) |
4807 | { | |
4808 | struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; | |
4809 | struct hclge_vport_vtag_tx_cfg_cmd *req; | |
4810 | struct hclge_dev *hdev = vport->back; | |
4811 | struct hclge_desc desc; | |
4812 | int status; | |
4813 | ||
4814 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); | |
4815 | ||
4816 | req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; | |
4817 | req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); | |
4818 | req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); | |
e4e87715 PL |
4819 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, |
4820 | vcfg->accept_tag1 ? 1 : 0); | |
4821 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, | |
4822 | vcfg->accept_untag1 ? 1 : 0); | |
4823 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, | |
4824 | vcfg->accept_tag2 ? 1 : 0); | |
4825 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, | |
4826 | vcfg->accept_untag2 ? 1 : 0); | |
4827 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, | |
4828 | vcfg->insert_tag1_en ? 1 : 0); | |
4829 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, | |
4830 | vcfg->insert_tag2_en ? 1 : 0); | |
4831 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); | |
5f6ea83f PL |
4832 | |
4833 | req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; | |
4834 | req->vf_bitmap[req->vf_offset] = | |
4835 | 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); | |
4836 | ||
4837 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4838 | if (status) | |
4839 | dev_err(&hdev->pdev->dev, | |
4840 | "Send port txvlan cfg command fail, ret =%d\n", | |
4841 | status); | |
4842 | ||
4843 | return status; | |
4844 | } | |
4845 | ||
4846 | static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) | |
4847 | { | |
4848 | struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; | |
4849 | struct hclge_vport_vtag_rx_cfg_cmd *req; | |
4850 | struct hclge_dev *hdev = vport->back; | |
4851 | struct hclge_desc desc; | |
4852 | int status; | |
4853 | ||
4854 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); | |
4855 | ||
4856 | req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; | |
e4e87715 PL |
4857 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, |
4858 | vcfg->strip_tag1_en ? 1 : 0); | |
4859 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, | |
4860 | vcfg->strip_tag2_en ? 1 : 0); | |
4861 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, | |
4862 | vcfg->vlan1_vlan_prionly ? 1 : 0); | |
4863 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, | |
4864 | vcfg->vlan2_vlan_prionly ? 1 : 0); | |
5f6ea83f PL |
4865 | |
4866 | req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; | |
4867 | req->vf_bitmap[req->vf_offset] = | |
4868 | 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); | |
4869 | ||
4870 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4871 | if (status) | |
4872 | dev_err(&hdev->pdev->dev, | |
4873 | "Send port rxvlan cfg command fail, ret =%d\n", | |
4874 | status); | |
4875 | ||
4876 | return status; | |
4877 | } | |
4878 | ||
4879 | static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) | |
4880 | { | |
4881 | struct hclge_rx_vlan_type_cfg_cmd *rx_req; | |
4882 | struct hclge_tx_vlan_type_cfg_cmd *tx_req; | |
4883 | struct hclge_desc desc; | |
4884 | int status; | |
4885 | ||
4886 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); | |
4887 | rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; | |
4888 | rx_req->ot_fst_vlan_type = | |
4889 | cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); | |
4890 | rx_req->ot_sec_vlan_type = | |
4891 | cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); | |
4892 | rx_req->in_fst_vlan_type = | |
4893 | cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); | |
4894 | rx_req->in_sec_vlan_type = | |
4895 | cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); | |
4896 | ||
4897 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4898 | if (status) { | |
4899 | dev_err(&hdev->pdev->dev, | |
4900 | "Send rxvlan protocol type command fail, ret =%d\n", | |
4901 | status); | |
4902 | return status; | |
4903 | } | |
4904 | ||
4905 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); | |
4906 | ||
4907 | tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; | |
4908 | tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); | |
4909 | tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); | |
4910 | ||
4911 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4912 | if (status) | |
4913 | dev_err(&hdev->pdev->dev, | |
4914 | "Send txvlan protocol type command fail, ret =%d\n", | |
4915 | status); | |
4916 | ||
4917 | return status; | |
4918 | } | |
4919 | ||
46a3df9f S |
4920 | static int hclge_init_vlan_config(struct hclge_dev *hdev) |
4921 | { | |
5f6ea83f PL |
4922 | #define HCLGE_DEF_VLAN_TYPE 0x8100 |
4923 | ||
5e43aef8 | 4924 | struct hnae3_handle *handle; |
5f6ea83f | 4925 | struct hclge_vport *vport; |
46a3df9f | 4926 | int ret; |
5f6ea83f PL |
4927 | int i; |
4928 | ||
4929 | ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); | |
4930 | if (ret) | |
4931 | return ret; | |
46a3df9f | 4932 | |
5f6ea83f | 4933 | ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); |
46a3df9f S |
4934 | if (ret) |
4935 | return ret; | |
4936 | ||
5f6ea83f PL |
4937 | hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; |
4938 | hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4939 | hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4940 | hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4941 | hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4942 | hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4943 | ||
4944 | ret = hclge_set_vlan_protocol_type(hdev); | |
5e43aef8 L |
4945 | if (ret) |
4946 | return ret; | |
46a3df9f | 4947 | |
5f6ea83f PL |
4948 | for (i = 0; i < hdev->num_alloc_vport; i++) { |
4949 | vport = &hdev->vport[i]; | |
dcb35cce PL |
4950 | vport->txvlan_cfg.accept_tag1 = true; |
4951 | vport->txvlan_cfg.accept_untag1 = true; | |
4952 | ||
4953 | /* accept_tag2 and accept_untag2 are not supported on | |
4954 | * pdev revision(0x20), new revision support them. The | |
4955 | * value of this two fields will not return error when driver | |
4956 | * send command to fireware in revision(0x20). | |
4957 | * This two fields can not configured by user. | |
4958 | */ | |
4959 | vport->txvlan_cfg.accept_tag2 = true; | |
4960 | vport->txvlan_cfg.accept_untag2 = true; | |
4961 | ||
5f6ea83f PL |
4962 | vport->txvlan_cfg.insert_tag1_en = false; |
4963 | vport->txvlan_cfg.insert_tag2_en = false; | |
4964 | vport->txvlan_cfg.default_tag1 = 0; | |
4965 | vport->txvlan_cfg.default_tag2 = 0; | |
4966 | ||
4967 | ret = hclge_set_vlan_tx_offload_cfg(vport); | |
4968 | if (ret) | |
4969 | return ret; | |
4970 | ||
4971 | vport->rxvlan_cfg.strip_tag1_en = false; | |
4972 | vport->rxvlan_cfg.strip_tag2_en = true; | |
4973 | vport->rxvlan_cfg.vlan1_vlan_prionly = false; | |
4974 | vport->rxvlan_cfg.vlan2_vlan_prionly = false; | |
4975 | ||
4976 | ret = hclge_set_vlan_rx_offload_cfg(vport); | |
4977 | if (ret) | |
4978 | return ret; | |
4979 | } | |
4980 | ||
5e43aef8 | 4981 | handle = &hdev->vport[0].nic; |
dc8131d8 | 4982 | return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); |
46a3df9f S |
4983 | } |
4984 | ||
b2641e2a | 4985 | int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) |
052ece6d PL |
4986 | { |
4987 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4988 | ||
4989 | vport->rxvlan_cfg.strip_tag1_en = false; | |
4990 | vport->rxvlan_cfg.strip_tag2_en = enable; | |
4991 | vport->rxvlan_cfg.vlan1_vlan_prionly = false; | |
4992 | vport->rxvlan_cfg.vlan2_vlan_prionly = false; | |
4993 | ||
4994 | return hclge_set_vlan_rx_offload_cfg(vport); | |
4995 | } | |
4996 | ||
dd72140c | 4997 | static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu) |
46a3df9f | 4998 | { |
d44f9b63 | 4999 | struct hclge_config_max_frm_size_cmd *req; |
46a3df9f | 5000 | struct hclge_desc desc; |
2866ccb2 | 5001 | int max_frm_size; |
46a3df9f S |
5002 | int ret; |
5003 | ||
2866ccb2 FL |
5004 | max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
5005 | ||
5006 | if (max_frm_size < HCLGE_MAC_MIN_FRAME || | |
5007 | max_frm_size > HCLGE_MAC_MAX_FRAME) | |
46a3df9f S |
5008 | return -EINVAL; |
5009 | ||
2866ccb2 FL |
5010 | max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); |
5011 | ||
46a3df9f S |
5012 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); |
5013 | ||
d44f9b63 | 5014 | req = (struct hclge_config_max_frm_size_cmd *)desc.data; |
2866ccb2 | 5015 | req->max_frm_size = cpu_to_le16(max_frm_size); |
8fc7346c | 5016 | req->min_frm_size = HCLGE_MAC_MIN_FRAME; |
46a3df9f S |
5017 | |
5018 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3f639907 | 5019 | if (ret) |
46a3df9f | 5020 | dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); |
3f639907 JS |
5021 | else |
5022 | hdev->mps = max_frm_size; | |
2866ccb2 | 5023 | |
3f639907 | 5024 | return ret; |
46a3df9f S |
5025 | } |
5026 | ||
dd72140c FL |
5027 | static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) |
5028 | { | |
5029 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5030 | struct hclge_dev *hdev = vport->back; | |
5031 | int ret; | |
5032 | ||
5033 | ret = hclge_set_mac_mtu(hdev, new_mtu); | |
5034 | if (ret) { | |
5035 | dev_err(&hdev->pdev->dev, | |
5036 | "Change mtu fail, ret =%d\n", ret); | |
5037 | return ret; | |
5038 | } | |
5039 | ||
5040 | ret = hclge_buffer_alloc(hdev); | |
5041 | if (ret) | |
5042 | dev_err(&hdev->pdev->dev, | |
5043 | "Allocate buffer fail, ret =%d\n", ret); | |
5044 | ||
5045 | return ret; | |
5046 | } | |
5047 | ||
46a3df9f S |
5048 | static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, |
5049 | bool enable) | |
5050 | { | |
d44f9b63 | 5051 | struct hclge_reset_tqp_queue_cmd *req; |
46a3df9f S |
5052 | struct hclge_desc desc; |
5053 | int ret; | |
5054 | ||
5055 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); | |
5056 | ||
d44f9b63 | 5057 | req = (struct hclge_reset_tqp_queue_cmd *)desc.data; |
46a3df9f | 5058 | req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); |
e4e87715 | 5059 | hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); |
46a3df9f S |
5060 | |
5061 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
5062 | if (ret) { | |
5063 | dev_err(&hdev->pdev->dev, | |
5064 | "Send tqp reset cmd error, status =%d\n", ret); | |
5065 | return ret; | |
5066 | } | |
5067 | ||
5068 | return 0; | |
5069 | } | |
5070 | ||
5071 | static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) | |
5072 | { | |
d44f9b63 | 5073 | struct hclge_reset_tqp_queue_cmd *req; |
46a3df9f S |
5074 | struct hclge_desc desc; |
5075 | int ret; | |
5076 | ||
5077 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); | |
5078 | ||
d44f9b63 | 5079 | req = (struct hclge_reset_tqp_queue_cmd *)desc.data; |
46a3df9f S |
5080 | req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); |
5081 | ||
5082 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
5083 | if (ret) { | |
5084 | dev_err(&hdev->pdev->dev, | |
5085 | "Get reset status error, status =%d\n", ret); | |
5086 | return ret; | |
5087 | } | |
5088 | ||
e4e87715 | 5089 | return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); |
46a3df9f S |
5090 | } |
5091 | ||
814e0274 PL |
5092 | static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, |
5093 | u16 queue_id) | |
5094 | { | |
5095 | struct hnae3_queue *queue; | |
5096 | struct hclge_tqp *tqp; | |
5097 | ||
5098 | queue = handle->kinfo.tqp[queue_id]; | |
5099 | tqp = container_of(queue, struct hclge_tqp, q); | |
5100 | ||
5101 | return tqp->index; | |
5102 | } | |
5103 | ||
84e095d6 | 5104 | void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) |
46a3df9f S |
5105 | { |
5106 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5107 | struct hclge_dev *hdev = vport->back; | |
5108 | int reset_try_times = 0; | |
5109 | int reset_status; | |
814e0274 | 5110 | u16 queue_gid; |
46a3df9f S |
5111 | int ret; |
5112 | ||
b50ae26c PL |
5113 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
5114 | return; | |
5115 | ||
814e0274 PL |
5116 | queue_gid = hclge_covert_handle_qid_global(handle, queue_id); |
5117 | ||
46a3df9f S |
5118 | ret = hclge_tqp_enable(hdev, queue_id, 0, false); |
5119 | if (ret) { | |
5120 | dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); | |
5121 | return; | |
5122 | } | |
5123 | ||
814e0274 | 5124 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); |
46a3df9f S |
5125 | if (ret) { |
5126 | dev_warn(&hdev->pdev->dev, | |
5127 | "Send reset tqp cmd fail, ret = %d\n", ret); | |
5128 | return; | |
5129 | } | |
5130 | ||
5131 | reset_try_times = 0; | |
5132 | while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { | |
5133 | /* Wait for tqp hw reset */ | |
5134 | msleep(20); | |
814e0274 | 5135 | reset_status = hclge_get_reset_status(hdev, queue_gid); |
46a3df9f S |
5136 | if (reset_status) |
5137 | break; | |
5138 | } | |
5139 | ||
5140 | if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { | |
5141 | dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); | |
5142 | return; | |
5143 | } | |
5144 | ||
814e0274 | 5145 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); |
46a3df9f S |
5146 | if (ret) { |
5147 | dev_warn(&hdev->pdev->dev, | |
5148 | "Deassert the soft reset fail, ret = %d\n", ret); | |
5149 | return; | |
5150 | } | |
5151 | } | |
5152 | ||
1a426f8b PL |
5153 | void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) |
5154 | { | |
5155 | struct hclge_dev *hdev = vport->back; | |
5156 | int reset_try_times = 0; | |
5157 | int reset_status; | |
5158 | u16 queue_gid; | |
5159 | int ret; | |
5160 | ||
5161 | queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id); | |
5162 | ||
5163 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); | |
5164 | if (ret) { | |
5165 | dev_warn(&hdev->pdev->dev, | |
5166 | "Send reset tqp cmd fail, ret = %d\n", ret); | |
5167 | return; | |
5168 | } | |
5169 | ||
5170 | reset_try_times = 0; | |
5171 | while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { | |
5172 | /* Wait for tqp hw reset */ | |
5173 | msleep(20); | |
5174 | reset_status = hclge_get_reset_status(hdev, queue_gid); | |
5175 | if (reset_status) | |
5176 | break; | |
5177 | } | |
5178 | ||
5179 | if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { | |
5180 | dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); | |
5181 | return; | |
5182 | } | |
5183 | ||
5184 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); | |
5185 | if (ret) | |
5186 | dev_warn(&hdev->pdev->dev, | |
5187 | "Deassert the soft reset fail, ret = %d\n", ret); | |
5188 | } | |
5189 | ||
46a3df9f S |
5190 | static u32 hclge_get_fw_version(struct hnae3_handle *handle) |
5191 | { | |
5192 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5193 | struct hclge_dev *hdev = vport->back; | |
5194 | ||
5195 | return hdev->fw_version; | |
5196 | } | |
5197 | ||
f34ffffd PL |
5198 | static void hclge_get_flowctrl_adv(struct hnae3_handle *handle, |
5199 | u32 *flowctrl_adv) | |
5200 | { | |
5201 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5202 | struct hclge_dev *hdev = vport->back; | |
5203 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5204 | ||
5205 | if (!phydev) | |
5206 | return; | |
5207 | ||
5208 | *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) | | |
5209 | (phydev->advertising & ADVERTISED_Asym_Pause); | |
5210 | } | |
5211 | ||
61387774 PL |
5212 | static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) |
5213 | { | |
5214 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5215 | ||
5216 | if (!phydev) | |
5217 | return; | |
5218 | ||
5219 | phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
5220 | ||
5221 | if (rx_en) | |
5222 | phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; | |
5223 | ||
5224 | if (tx_en) | |
5225 | phydev->advertising ^= ADVERTISED_Asym_Pause; | |
5226 | } | |
5227 | ||
5228 | static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) | |
5229 | { | |
61387774 PL |
5230 | int ret; |
5231 | ||
5232 | if (rx_en && tx_en) | |
40173a2e | 5233 | hdev->fc_mode_last_time = HCLGE_FC_FULL; |
61387774 | 5234 | else if (rx_en && !tx_en) |
40173a2e | 5235 | hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; |
61387774 | 5236 | else if (!rx_en && tx_en) |
40173a2e | 5237 | hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; |
61387774 | 5238 | else |
40173a2e | 5239 | hdev->fc_mode_last_time = HCLGE_FC_NONE; |
61387774 | 5240 | |
40173a2e | 5241 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) |
61387774 | 5242 | return 0; |
61387774 PL |
5243 | |
5244 | ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); | |
5245 | if (ret) { | |
5246 | dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", | |
5247 | ret); | |
5248 | return ret; | |
5249 | } | |
5250 | ||
40173a2e | 5251 | hdev->tm_info.fc_mode = hdev->fc_mode_last_time; |
61387774 PL |
5252 | |
5253 | return 0; | |
5254 | } | |
5255 | ||
1770a7a3 PL |
5256 | int hclge_cfg_flowctrl(struct hclge_dev *hdev) |
5257 | { | |
5258 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5259 | u16 remote_advertising = 0; | |
5260 | u16 local_advertising = 0; | |
5261 | u32 rx_pause, tx_pause; | |
5262 | u8 flowctl; | |
5263 | ||
5264 | if (!phydev->link || !phydev->autoneg) | |
5265 | return 0; | |
5266 | ||
5267 | if (phydev->advertising & ADVERTISED_Pause) | |
5268 | local_advertising = ADVERTISE_PAUSE_CAP; | |
5269 | ||
5270 | if (phydev->advertising & ADVERTISED_Asym_Pause) | |
5271 | local_advertising |= ADVERTISE_PAUSE_ASYM; | |
5272 | ||
5273 | if (phydev->pause) | |
5274 | remote_advertising = LPA_PAUSE_CAP; | |
5275 | ||
5276 | if (phydev->asym_pause) | |
5277 | remote_advertising |= LPA_PAUSE_ASYM; | |
5278 | ||
5279 | flowctl = mii_resolve_flowctrl_fdx(local_advertising, | |
5280 | remote_advertising); | |
5281 | tx_pause = flowctl & FLOW_CTRL_TX; | |
5282 | rx_pause = flowctl & FLOW_CTRL_RX; | |
5283 | ||
5284 | if (phydev->duplex == HCLGE_MAC_HALF) { | |
5285 | tx_pause = 0; | |
5286 | rx_pause = 0; | |
5287 | } | |
5288 | ||
5289 | return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); | |
5290 | } | |
5291 | ||
46a3df9f S |
5292 | static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, |
5293 | u32 *rx_en, u32 *tx_en) | |
5294 | { | |
5295 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5296 | struct hclge_dev *hdev = vport->back; | |
5297 | ||
5298 | *auto_neg = hclge_get_autoneg(handle); | |
5299 | ||
5300 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { | |
5301 | *rx_en = 0; | |
5302 | *tx_en = 0; | |
5303 | return; | |
5304 | } | |
5305 | ||
5306 | if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { | |
5307 | *rx_en = 1; | |
5308 | *tx_en = 0; | |
5309 | } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { | |
5310 | *tx_en = 1; | |
5311 | *rx_en = 0; | |
5312 | } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { | |
5313 | *rx_en = 1; | |
5314 | *tx_en = 1; | |
5315 | } else { | |
5316 | *rx_en = 0; | |
5317 | *tx_en = 0; | |
5318 | } | |
5319 | } | |
5320 | ||
61387774 PL |
5321 | static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, |
5322 | u32 rx_en, u32 tx_en) | |
5323 | { | |
5324 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5325 | struct hclge_dev *hdev = vport->back; | |
5326 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5327 | u32 fc_autoneg; | |
5328 | ||
61387774 PL |
5329 | fc_autoneg = hclge_get_autoneg(handle); |
5330 | if (auto_neg != fc_autoneg) { | |
5331 | dev_info(&hdev->pdev->dev, | |
5332 | "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); | |
5333 | return -EOPNOTSUPP; | |
5334 | } | |
5335 | ||
5336 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { | |
5337 | dev_info(&hdev->pdev->dev, | |
5338 | "Priority flow control enabled. Cannot set link flow control.\n"); | |
5339 | return -EOPNOTSUPP; | |
5340 | } | |
5341 | ||
5342 | hclge_set_flowctrl_adv(hdev, rx_en, tx_en); | |
5343 | ||
5344 | if (!fc_autoneg) | |
5345 | return hclge_cfg_pauseparam(hdev, rx_en, tx_en); | |
5346 | ||
0c963e8c FL |
5347 | /* Only support flow control negotiation for netdev with |
5348 | * phy attached for now. | |
5349 | */ | |
5350 | if (!phydev) | |
5351 | return -EOPNOTSUPP; | |
5352 | ||
61387774 PL |
5353 | return phy_start_aneg(phydev); |
5354 | } | |
5355 | ||
46a3df9f S |
5356 | static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, |
5357 | u8 *auto_neg, u32 *speed, u8 *duplex) | |
5358 | { | |
5359 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5360 | struct hclge_dev *hdev = vport->back; | |
5361 | ||
5362 | if (speed) | |
5363 | *speed = hdev->hw.mac.speed; | |
5364 | if (duplex) | |
5365 | *duplex = hdev->hw.mac.duplex; | |
5366 | if (auto_neg) | |
5367 | *auto_neg = hdev->hw.mac.autoneg; | |
5368 | } | |
5369 | ||
5370 | static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) | |
5371 | { | |
5372 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5373 | struct hclge_dev *hdev = vport->back; | |
5374 | ||
5375 | if (media_type) | |
5376 | *media_type = hdev->hw.mac.media_type; | |
5377 | } | |
5378 | ||
5379 | static void hclge_get_mdix_mode(struct hnae3_handle *handle, | |
5380 | u8 *tp_mdix_ctrl, u8 *tp_mdix) | |
5381 | { | |
5382 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5383 | struct hclge_dev *hdev = vport->back; | |
5384 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5385 | int mdix_ctrl, mdix, retval, is_resolved; | |
5386 | ||
5387 | if (!phydev) { | |
5388 | *tp_mdix_ctrl = ETH_TP_MDI_INVALID; | |
5389 | *tp_mdix = ETH_TP_MDI_INVALID; | |
5390 | return; | |
5391 | } | |
5392 | ||
5393 | phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); | |
5394 | ||
5395 | retval = phy_read(phydev, HCLGE_PHY_CSC_REG); | |
e4e87715 PL |
5396 | mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, |
5397 | HCLGE_PHY_MDIX_CTRL_S); | |
46a3df9f S |
5398 | |
5399 | retval = phy_read(phydev, HCLGE_PHY_CSS_REG); | |
e4e87715 PL |
5400 | mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); |
5401 | is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); | |
46a3df9f S |
5402 | |
5403 | phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); | |
5404 | ||
5405 | switch (mdix_ctrl) { | |
5406 | case 0x0: | |
5407 | *tp_mdix_ctrl = ETH_TP_MDI; | |
5408 | break; | |
5409 | case 0x1: | |
5410 | *tp_mdix_ctrl = ETH_TP_MDI_X; | |
5411 | break; | |
5412 | case 0x3: | |
5413 | *tp_mdix_ctrl = ETH_TP_MDI_AUTO; | |
5414 | break; | |
5415 | default: | |
5416 | *tp_mdix_ctrl = ETH_TP_MDI_INVALID; | |
5417 | break; | |
5418 | } | |
5419 | ||
5420 | if (!is_resolved) | |
5421 | *tp_mdix = ETH_TP_MDI_INVALID; | |
5422 | else if (mdix) | |
5423 | *tp_mdix = ETH_TP_MDI_X; | |
5424 | else | |
5425 | *tp_mdix = ETH_TP_MDI; | |
5426 | } | |
5427 | ||
b01b7cf1 FL |
5428 | static int hclge_init_instance_hw(struct hclge_dev *hdev) |
5429 | { | |
5430 | return hclge_mac_connect_phy(hdev); | |
5431 | } | |
5432 | ||
5433 | static void hclge_uninit_instance_hw(struct hclge_dev *hdev) | |
5434 | { | |
5435 | hclge_mac_disconnect_phy(hdev); | |
5436 | } | |
5437 | ||
46a3df9f S |
5438 | static int hclge_init_client_instance(struct hnae3_client *client, |
5439 | struct hnae3_ae_dev *ae_dev) | |
5440 | { | |
5441 | struct hclge_dev *hdev = ae_dev->priv; | |
5442 | struct hclge_vport *vport; | |
5443 | int i, ret; | |
5444 | ||
5445 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
5446 | vport = &hdev->vport[i]; | |
5447 | ||
5448 | switch (client->type) { | |
5449 | case HNAE3_CLIENT_KNIC: | |
5450 | ||
5451 | hdev->nic_client = client; | |
5452 | vport->nic.client = client; | |
5453 | ret = client->ops->init_instance(&vport->nic); | |
5454 | if (ret) | |
99a6993a | 5455 | return ret; |
46a3df9f | 5456 | |
b01b7cf1 FL |
5457 | ret = hclge_init_instance_hw(hdev); |
5458 | if (ret) { | |
5459 | client->ops->uninit_instance(&vport->nic, | |
5460 | 0); | |
5461 | return ret; | |
5462 | } | |
5463 | ||
46a3df9f | 5464 | if (hdev->roce_client && |
e92a0843 | 5465 | hnae3_dev_roce_supported(hdev)) { |
46a3df9f S |
5466 | struct hnae3_client *rc = hdev->roce_client; |
5467 | ||
5468 | ret = hclge_init_roce_base_info(vport); | |
5469 | if (ret) | |
99a6993a | 5470 | return ret; |
46a3df9f S |
5471 | |
5472 | ret = rc->ops->init_instance(&vport->roce); | |
5473 | if (ret) | |
99a6993a | 5474 | return ret; |
46a3df9f S |
5475 | } |
5476 | ||
5477 | break; | |
5478 | case HNAE3_CLIENT_UNIC: | |
5479 | hdev->nic_client = client; | |
5480 | vport->nic.client = client; | |
5481 | ||
5482 | ret = client->ops->init_instance(&vport->nic); | |
5483 | if (ret) | |
99a6993a | 5484 | return ret; |
46a3df9f S |
5485 | |
5486 | break; | |
5487 | case HNAE3_CLIENT_ROCE: | |
e92a0843 | 5488 | if (hnae3_dev_roce_supported(hdev)) { |
46a3df9f S |
5489 | hdev->roce_client = client; |
5490 | vport->roce.client = client; | |
5491 | } | |
5492 | ||
3a46f34d | 5493 | if (hdev->roce_client && hdev->nic_client) { |
46a3df9f S |
5494 | ret = hclge_init_roce_base_info(vport); |
5495 | if (ret) | |
99a6993a | 5496 | return ret; |
46a3df9f S |
5497 | |
5498 | ret = client->ops->init_instance(&vport->roce); | |
5499 | if (ret) | |
99a6993a | 5500 | return ret; |
46a3df9f S |
5501 | } |
5502 | } | |
5503 | } | |
5504 | ||
5505 | return 0; | |
46a3df9f S |
5506 | } |
5507 | ||
5508 | static void hclge_uninit_client_instance(struct hnae3_client *client, | |
5509 | struct hnae3_ae_dev *ae_dev) | |
5510 | { | |
5511 | struct hclge_dev *hdev = ae_dev->priv; | |
5512 | struct hclge_vport *vport; | |
5513 | int i; | |
5514 | ||
5515 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
5516 | vport = &hdev->vport[i]; | |
a17dcf3f | 5517 | if (hdev->roce_client) { |
46a3df9f S |
5518 | hdev->roce_client->ops->uninit_instance(&vport->roce, |
5519 | 0); | |
a17dcf3f L |
5520 | hdev->roce_client = NULL; |
5521 | vport->roce.client = NULL; | |
5522 | } | |
46a3df9f S |
5523 | if (client->type == HNAE3_CLIENT_ROCE) |
5524 | return; | |
a17dcf3f | 5525 | if (client->ops->uninit_instance) { |
b01b7cf1 | 5526 | hclge_uninit_instance_hw(hdev); |
46a3df9f | 5527 | client->ops->uninit_instance(&vport->nic, 0); |
a17dcf3f L |
5528 | hdev->nic_client = NULL; |
5529 | vport->nic.client = NULL; | |
5530 | } | |
46a3df9f S |
5531 | } |
5532 | } | |
5533 | ||
5534 | static int hclge_pci_init(struct hclge_dev *hdev) | |
5535 | { | |
5536 | struct pci_dev *pdev = hdev->pdev; | |
5537 | struct hclge_hw *hw; | |
5538 | int ret; | |
5539 | ||
5540 | ret = pci_enable_device(pdev); | |
5541 | if (ret) { | |
5542 | dev_err(&pdev->dev, "failed to enable PCI device\n"); | |
3e249d3b | 5543 | return ret; |
46a3df9f S |
5544 | } |
5545 | ||
5546 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); | |
5547 | if (ret) { | |
5548 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
5549 | if (ret) { | |
5550 | dev_err(&pdev->dev, | |
5551 | "can't set consistent PCI DMA"); | |
5552 | goto err_disable_device; | |
5553 | } | |
5554 | dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); | |
5555 | } | |
5556 | ||
5557 | ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); | |
5558 | if (ret) { | |
5559 | dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); | |
5560 | goto err_disable_device; | |
5561 | } | |
5562 | ||
5563 | pci_set_master(pdev); | |
5564 | hw = &hdev->hw; | |
46a3df9f S |
5565 | hw->io_base = pcim_iomap(pdev, 2, 0); |
5566 | if (!hw->io_base) { | |
5567 | dev_err(&pdev->dev, "Can't map configuration register space\n"); | |
5568 | ret = -ENOMEM; | |
5569 | goto err_clr_master; | |
5570 | } | |
5571 | ||
709eb41a L |
5572 | hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); |
5573 | ||
46a3df9f S |
5574 | return 0; |
5575 | err_clr_master: | |
5576 | pci_clear_master(pdev); | |
5577 | pci_release_regions(pdev); | |
5578 | err_disable_device: | |
5579 | pci_disable_device(pdev); | |
46a3df9f S |
5580 | |
5581 | return ret; | |
5582 | } | |
5583 | ||
5584 | static void hclge_pci_uninit(struct hclge_dev *hdev) | |
5585 | { | |
5586 | struct pci_dev *pdev = hdev->pdev; | |
5587 | ||
6a814413 | 5588 | pcim_iounmap(pdev, hdev->hw.io_base); |
887c3820 | 5589 | pci_free_irq_vectors(pdev); |
46a3df9f S |
5590 | pci_clear_master(pdev); |
5591 | pci_release_mem_regions(pdev); | |
5592 | pci_disable_device(pdev); | |
5593 | } | |
5594 | ||
48569cda PL |
5595 | static void hclge_state_init(struct hclge_dev *hdev) |
5596 | { | |
5597 | set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); | |
5598 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
5599 | clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); | |
5600 | clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); | |
5601 | clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); | |
5602 | clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); | |
5603 | } | |
5604 | ||
5605 | static void hclge_state_uninit(struct hclge_dev *hdev) | |
5606 | { | |
5607 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
5608 | ||
5609 | if (hdev->service_timer.function) | |
5610 | del_timer_sync(&hdev->service_timer); | |
5611 | if (hdev->service_task.func) | |
5612 | cancel_work_sync(&hdev->service_task); | |
5613 | if (hdev->rst_service_task.func) | |
5614 | cancel_work_sync(&hdev->rst_service_task); | |
5615 | if (hdev->mbx_service_task.func) | |
5616 | cancel_work_sync(&hdev->mbx_service_task); | |
5617 | } | |
5618 | ||
46a3df9f S |
5619 | static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) |
5620 | { | |
5621 | struct pci_dev *pdev = ae_dev->pdev; | |
46a3df9f S |
5622 | struct hclge_dev *hdev; |
5623 | int ret; | |
5624 | ||
5625 | hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); | |
5626 | if (!hdev) { | |
5627 | ret = -ENOMEM; | |
ffd5656e | 5628 | goto out; |
46a3df9f S |
5629 | } |
5630 | ||
46a3df9f S |
5631 | hdev->pdev = pdev; |
5632 | hdev->ae_dev = ae_dev; | |
4ed340ab | 5633 | hdev->reset_type = HNAE3_NONE_RESET; |
46a3df9f S |
5634 | ae_dev->priv = hdev; |
5635 | ||
46a3df9f S |
5636 | ret = hclge_pci_init(hdev); |
5637 | if (ret) { | |
5638 | dev_err(&pdev->dev, "PCI init failed\n"); | |
ffd5656e | 5639 | goto out; |
46a3df9f S |
5640 | } |
5641 | ||
3efb960f L |
5642 | /* Firmware command queue initialize */ |
5643 | ret = hclge_cmd_queue_init(hdev); | |
5644 | if (ret) { | |
5645 | dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); | |
ffd5656e | 5646 | goto err_pci_uninit; |
3efb960f L |
5647 | } |
5648 | ||
5649 | /* Firmware command initialize */ | |
46a3df9f S |
5650 | ret = hclge_cmd_init(hdev); |
5651 | if (ret) | |
ffd5656e | 5652 | goto err_cmd_uninit; |
46a3df9f S |
5653 | |
5654 | ret = hclge_get_cap(hdev); | |
5655 | if (ret) { | |
e00e2197 CIK |
5656 | dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", |
5657 | ret); | |
ffd5656e | 5658 | goto err_cmd_uninit; |
46a3df9f S |
5659 | } |
5660 | ||
5661 | ret = hclge_configure(hdev); | |
5662 | if (ret) { | |
5663 | dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); | |
ffd5656e | 5664 | goto err_cmd_uninit; |
46a3df9f S |
5665 | } |
5666 | ||
887c3820 | 5667 | ret = hclge_init_msi(hdev); |
46a3df9f | 5668 | if (ret) { |
887c3820 | 5669 | dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); |
ffd5656e | 5670 | goto err_cmd_uninit; |
46a3df9f S |
5671 | } |
5672 | ||
466b0c00 L |
5673 | ret = hclge_misc_irq_init(hdev); |
5674 | if (ret) { | |
5675 | dev_err(&pdev->dev, | |
5676 | "Misc IRQ(vector0) init error, ret = %d.\n", | |
5677 | ret); | |
ffd5656e | 5678 | goto err_msi_uninit; |
466b0c00 L |
5679 | } |
5680 | ||
46a3df9f S |
5681 | ret = hclge_alloc_tqps(hdev); |
5682 | if (ret) { | |
5683 | dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); | |
ffd5656e | 5684 | goto err_msi_irq_uninit; |
46a3df9f S |
5685 | } |
5686 | ||
5687 | ret = hclge_alloc_vport(hdev); | |
5688 | if (ret) { | |
5689 | dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); | |
ffd5656e | 5690 | goto err_msi_irq_uninit; |
46a3df9f S |
5691 | } |
5692 | ||
7df7dad6 L |
5693 | ret = hclge_map_tqp(hdev); |
5694 | if (ret) { | |
5695 | dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); | |
2312e050 | 5696 | goto err_msi_irq_uninit; |
7df7dad6 L |
5697 | } |
5698 | ||
c5ef83cb HT |
5699 | if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { |
5700 | ret = hclge_mac_mdio_config(hdev); | |
5701 | if (ret) { | |
5702 | dev_err(&hdev->pdev->dev, | |
5703 | "mdio config fail ret=%d\n", ret); | |
2312e050 | 5704 | goto err_msi_irq_uninit; |
c5ef83cb | 5705 | } |
cf9cca2d | 5706 | } |
5707 | ||
46a3df9f S |
5708 | ret = hclge_mac_init(hdev); |
5709 | if (ret) { | |
5710 | dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); | |
ffd5656e | 5711 | goto err_mdiobus_unreg; |
46a3df9f | 5712 | } |
46a3df9f S |
5713 | |
5714 | ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); | |
5715 | if (ret) { | |
5716 | dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); | |
ffd5656e | 5717 | goto err_mdiobus_unreg; |
46a3df9f S |
5718 | } |
5719 | ||
46a3df9f S |
5720 | ret = hclge_init_vlan_config(hdev); |
5721 | if (ret) { | |
5722 | dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); | |
ffd5656e | 5723 | goto err_mdiobus_unreg; |
46a3df9f S |
5724 | } |
5725 | ||
5726 | ret = hclge_tm_schd_init(hdev); | |
5727 | if (ret) { | |
5728 | dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); | |
ffd5656e | 5729 | goto err_mdiobus_unreg; |
68ece54e YL |
5730 | } |
5731 | ||
268f5dfa | 5732 | hclge_rss_init_cfg(hdev); |
68ece54e YL |
5733 | ret = hclge_rss_init_hw(hdev); |
5734 | if (ret) { | |
5735 | dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); | |
ffd5656e | 5736 | goto err_mdiobus_unreg; |
46a3df9f S |
5737 | } |
5738 | ||
f5aac71c FL |
5739 | ret = init_mgr_tbl(hdev); |
5740 | if (ret) { | |
5741 | dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); | |
ffd5656e | 5742 | goto err_mdiobus_unreg; |
f5aac71c FL |
5743 | } |
5744 | ||
cacde272 YL |
5745 | hclge_dcb_ops_set(hdev); |
5746 | ||
d039ef68 | 5747 | timer_setup(&hdev->service_timer, hclge_service_timer, 0); |
46a3df9f | 5748 | INIT_WORK(&hdev->service_task, hclge_service_task); |
cb1b9f77 | 5749 | INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); |
c1a81619 | 5750 | INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); |
46a3df9f | 5751 | |
8e52a602 XW |
5752 | hclge_clear_all_event_cause(hdev); |
5753 | ||
466b0c00 L |
5754 | /* Enable MISC vector(vector0) */ |
5755 | hclge_enable_vector(&hdev->misc_vector, true); | |
5756 | ||
48569cda | 5757 | hclge_state_init(hdev); |
46a3df9f S |
5758 | |
5759 | pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); | |
5760 | return 0; | |
5761 | ||
ffd5656e HT |
5762 | err_mdiobus_unreg: |
5763 | if (hdev->hw.mac.phydev) | |
5764 | mdiobus_unregister(hdev->hw.mac.mdio_bus); | |
ffd5656e HT |
5765 | err_msi_irq_uninit: |
5766 | hclge_misc_irq_uninit(hdev); | |
5767 | err_msi_uninit: | |
5768 | pci_free_irq_vectors(pdev); | |
5769 | err_cmd_uninit: | |
5770 | hclge_destroy_cmd_queue(&hdev->hw); | |
5771 | err_pci_uninit: | |
6a814413 | 5772 | pcim_iounmap(pdev, hdev->hw.io_base); |
ffd5656e | 5773 | pci_clear_master(pdev); |
46a3df9f | 5774 | pci_release_regions(pdev); |
ffd5656e | 5775 | pci_disable_device(pdev); |
ffd5656e | 5776 | out: |
46a3df9f S |
5777 | return ret; |
5778 | } | |
5779 | ||
c6dc5213 | 5780 | static void hclge_stats_clear(struct hclge_dev *hdev) |
5781 | { | |
5782 | memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); | |
5783 | } | |
5784 | ||
4ed340ab L |
5785 | static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) |
5786 | { | |
5787 | struct hclge_dev *hdev = ae_dev->priv; | |
5788 | struct pci_dev *pdev = ae_dev->pdev; | |
5789 | int ret; | |
5790 | ||
5791 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
5792 | ||
c6dc5213 | 5793 | hclge_stats_clear(hdev); |
dc8131d8 | 5794 | memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); |
c6dc5213 | 5795 | |
4ed340ab L |
5796 | ret = hclge_cmd_init(hdev); |
5797 | if (ret) { | |
5798 | dev_err(&pdev->dev, "Cmd queue init failed\n"); | |
5799 | return ret; | |
5800 | } | |
5801 | ||
5802 | ret = hclge_get_cap(hdev); | |
5803 | if (ret) { | |
5804 | dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", | |
5805 | ret); | |
5806 | return ret; | |
5807 | } | |
5808 | ||
5809 | ret = hclge_configure(hdev); | |
5810 | if (ret) { | |
5811 | dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); | |
5812 | return ret; | |
5813 | } | |
5814 | ||
5815 | ret = hclge_map_tqp(hdev); | |
5816 | if (ret) { | |
5817 | dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); | |
5818 | return ret; | |
5819 | } | |
5820 | ||
5821 | ret = hclge_mac_init(hdev); | |
5822 | if (ret) { | |
5823 | dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); | |
5824 | return ret; | |
5825 | } | |
5826 | ||
4ed340ab L |
5827 | ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); |
5828 | if (ret) { | |
5829 | dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); | |
5830 | return ret; | |
5831 | } | |
5832 | ||
5833 | ret = hclge_init_vlan_config(hdev); | |
5834 | if (ret) { | |
5835 | dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); | |
5836 | return ret; | |
5837 | } | |
5838 | ||
f31c1ba6 | 5839 | ret = hclge_tm_init_hw(hdev); |
4ed340ab | 5840 | if (ret) { |
f31c1ba6 | 5841 | dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); |
4ed340ab L |
5842 | return ret; |
5843 | } | |
5844 | ||
5845 | ret = hclge_rss_init_hw(hdev); | |
5846 | if (ret) { | |
5847 | dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); | |
5848 | return ret; | |
5849 | } | |
5850 | ||
4ed340ab L |
5851 | dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", |
5852 | HCLGE_DRIVER_NAME); | |
5853 | ||
5854 | return 0; | |
5855 | } | |
5856 | ||
46a3df9f S |
5857 | static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) |
5858 | { | |
5859 | struct hclge_dev *hdev = ae_dev->priv; | |
5860 | struct hclge_mac *mac = &hdev->hw.mac; | |
5861 | ||
48569cda | 5862 | hclge_state_uninit(hdev); |
46a3df9f S |
5863 | |
5864 | if (mac->phydev) | |
5865 | mdiobus_unregister(mac->mdio_bus); | |
5866 | ||
466b0c00 L |
5867 | /* Disable MISC vector(vector0) */ |
5868 | hclge_enable_vector(&hdev->misc_vector, false); | |
8e52a602 XW |
5869 | synchronize_irq(hdev->misc_vector.vector_irq); |
5870 | ||
46a3df9f | 5871 | hclge_destroy_cmd_queue(&hdev->hw); |
ca1d7669 | 5872 | hclge_misc_irq_uninit(hdev); |
46a3df9f S |
5873 | hclge_pci_uninit(hdev); |
5874 | ae_dev->priv = NULL; | |
5875 | } | |
5876 | ||
482d2e9c PL |
5877 | static u32 hclge_get_max_channels(struct hnae3_handle *handle) |
5878 | { | |
5879 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
5880 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5881 | struct hclge_dev *hdev = vport->back; | |
5882 | ||
5883 | return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); | |
5884 | } | |
5885 | ||
5886 | static void hclge_get_channels(struct hnae3_handle *handle, | |
5887 | struct ethtool_channels *ch) | |
5888 | { | |
5889 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5890 | ||
5891 | ch->max_combined = hclge_get_max_channels(handle); | |
5892 | ch->other_count = 1; | |
5893 | ch->max_other = 1; | |
5894 | ch->combined_count = vport->alloc_tqps; | |
5895 | } | |
5896 | ||
09f2af64 PL |
5897 | static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, |
5898 | u16 *free_tqps, u16 *max_rss_size) | |
5899 | { | |
5900 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5901 | struct hclge_dev *hdev = vport->back; | |
5902 | u16 temp_tqps = 0; | |
5903 | int i; | |
5904 | ||
5905 | for (i = 0; i < hdev->num_tqps; i++) { | |
5906 | if (!hdev->htqp[i].alloced) | |
5907 | temp_tqps++; | |
5908 | } | |
5909 | *free_tqps = temp_tqps; | |
5910 | *max_rss_size = hdev->rss_size_max; | |
5911 | } | |
5912 | ||
5913 | static void hclge_release_tqp(struct hclge_vport *vport) | |
5914 | { | |
5915 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; | |
5916 | struct hclge_dev *hdev = vport->back; | |
5917 | int i; | |
5918 | ||
5919 | for (i = 0; i < kinfo->num_tqps; i++) { | |
5920 | struct hclge_tqp *tqp = | |
5921 | container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
5922 | ||
5923 | tqp->q.handle = NULL; | |
5924 | tqp->q.tqp_index = 0; | |
5925 | tqp->alloced = false; | |
5926 | } | |
5927 | ||
5928 | devm_kfree(&hdev->pdev->dev, kinfo->tqp); | |
5929 | kinfo->tqp = NULL; | |
5930 | } | |
5931 | ||
5932 | static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) | |
5933 | { | |
5934 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5935 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; | |
5936 | struct hclge_dev *hdev = vport->back; | |
5937 | int cur_rss_size = kinfo->rss_size; | |
5938 | int cur_tqps = kinfo->num_tqps; | |
5939 | u16 tc_offset[HCLGE_MAX_TC_NUM]; | |
5940 | u16 tc_valid[HCLGE_MAX_TC_NUM]; | |
5941 | u16 tc_size[HCLGE_MAX_TC_NUM]; | |
5942 | u16 roundup_size; | |
5943 | u32 *rss_indir; | |
5944 | int ret, i; | |
5945 | ||
fdace1bc | 5946 | /* Free old tqps, and reallocate with new tqp number when nic setup */ |
09f2af64 PL |
5947 | hclge_release_tqp(vport); |
5948 | ||
128b900d | 5949 | ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc); |
09f2af64 PL |
5950 | if (ret) { |
5951 | dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); | |
5952 | return ret; | |
5953 | } | |
5954 | ||
5955 | ret = hclge_map_tqp_to_vport(hdev, vport); | |
5956 | if (ret) { | |
5957 | dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); | |
5958 | return ret; | |
5959 | } | |
5960 | ||
5961 | ret = hclge_tm_schd_init(hdev); | |
5962 | if (ret) { | |
5963 | dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); | |
5964 | return ret; | |
5965 | } | |
5966 | ||
5967 | roundup_size = roundup_pow_of_two(kinfo->rss_size); | |
5968 | roundup_size = ilog2(roundup_size); | |
5969 | /* Set the RSS TC mode according to the new RSS size */ | |
5970 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
5971 | tc_valid[i] = 0; | |
5972 | ||
5973 | if (!(hdev->hw_tc_map & BIT(i))) | |
5974 | continue; | |
5975 | ||
5976 | tc_valid[i] = 1; | |
5977 | tc_size[i] = roundup_size; | |
5978 | tc_offset[i] = kinfo->rss_size * i; | |
5979 | } | |
5980 | ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); | |
5981 | if (ret) | |
5982 | return ret; | |
5983 | ||
5984 | /* Reinitializes the rss indirect table according to the new RSS size */ | |
5985 | rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); | |
5986 | if (!rss_indir) | |
5987 | return -ENOMEM; | |
5988 | ||
5989 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
5990 | rss_indir[i] = i % kinfo->rss_size; | |
5991 | ||
5992 | ret = hclge_set_rss(handle, rss_indir, NULL, 0); | |
5993 | if (ret) | |
5994 | dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", | |
5995 | ret); | |
5996 | ||
5997 | kfree(rss_indir); | |
5998 | ||
5999 | if (!ret) | |
6000 | dev_info(&hdev->pdev->dev, | |
6001 | "Channels changed, rss_size from %d to %d, tqps from %d to %d", | |
6002 | cur_rss_size, kinfo->rss_size, | |
6003 | cur_tqps, kinfo->rss_size * kinfo->num_tc); | |
6004 | ||
6005 | return ret; | |
6006 | } | |
6007 | ||
77b34110 FL |
6008 | static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, |
6009 | u32 *regs_num_64_bit) | |
6010 | { | |
6011 | struct hclge_desc desc; | |
6012 | u32 total_num; | |
6013 | int ret; | |
6014 | ||
6015 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); | |
6016 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
6017 | if (ret) { | |
6018 | dev_err(&hdev->pdev->dev, | |
6019 | "Query register number cmd failed, ret = %d.\n", ret); | |
6020 | return ret; | |
6021 | } | |
6022 | ||
6023 | *regs_num_32_bit = le32_to_cpu(desc.data[0]); | |
6024 | *regs_num_64_bit = le32_to_cpu(desc.data[1]); | |
6025 | ||
6026 | total_num = *regs_num_32_bit + *regs_num_64_bit; | |
6027 | if (!total_num) | |
6028 | return -EINVAL; | |
6029 | ||
6030 | return 0; | |
6031 | } | |
6032 | ||
6033 | static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, | |
6034 | void *data) | |
6035 | { | |
6036 | #define HCLGE_32_BIT_REG_RTN_DATANUM 8 | |
6037 | ||
6038 | struct hclge_desc *desc; | |
6039 | u32 *reg_val = data; | |
6040 | __le32 *desc_data; | |
6041 | int cmd_num; | |
6042 | int i, k, n; | |
6043 | int ret; | |
6044 | ||
6045 | if (regs_num == 0) | |
6046 | return 0; | |
6047 | ||
6048 | cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); | |
6049 | desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); | |
6050 | if (!desc) | |
6051 | return -ENOMEM; | |
6052 | ||
6053 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); | |
6054 | ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); | |
6055 | if (ret) { | |
6056 | dev_err(&hdev->pdev->dev, | |
6057 | "Query 32 bit register cmd failed, ret = %d.\n", ret); | |
6058 | kfree(desc); | |
6059 | return ret; | |
6060 | } | |
6061 | ||
6062 | for (i = 0; i < cmd_num; i++) { | |
6063 | if (i == 0) { | |
6064 | desc_data = (__le32 *)(&desc[i].data[0]); | |
6065 | n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; | |
6066 | } else { | |
6067 | desc_data = (__le32 *)(&desc[i]); | |
6068 | n = HCLGE_32_BIT_REG_RTN_DATANUM; | |
6069 | } | |
6070 | for (k = 0; k < n; k++) { | |
6071 | *reg_val++ = le32_to_cpu(*desc_data++); | |
6072 | ||
6073 | regs_num--; | |
6074 | if (!regs_num) | |
6075 | break; | |
6076 | } | |
6077 | } | |
6078 | ||
6079 | kfree(desc); | |
6080 | return 0; | |
6081 | } | |
6082 | ||
6083 | static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, | |
6084 | void *data) | |
6085 | { | |
6086 | #define HCLGE_64_BIT_REG_RTN_DATANUM 4 | |
6087 | ||
6088 | struct hclge_desc *desc; | |
6089 | u64 *reg_val = data; | |
6090 | __le64 *desc_data; | |
6091 | int cmd_num; | |
6092 | int i, k, n; | |
6093 | int ret; | |
6094 | ||
6095 | if (regs_num == 0) | |
6096 | return 0; | |
6097 | ||
6098 | cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); | |
6099 | desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); | |
6100 | if (!desc) | |
6101 | return -ENOMEM; | |
6102 | ||
6103 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); | |
6104 | ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); | |
6105 | if (ret) { | |
6106 | dev_err(&hdev->pdev->dev, | |
6107 | "Query 64 bit register cmd failed, ret = %d.\n", ret); | |
6108 | kfree(desc); | |
6109 | return ret; | |
6110 | } | |
6111 | ||
6112 | for (i = 0; i < cmd_num; i++) { | |
6113 | if (i == 0) { | |
6114 | desc_data = (__le64 *)(&desc[i].data[0]); | |
6115 | n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; | |
6116 | } else { | |
6117 | desc_data = (__le64 *)(&desc[i]); | |
6118 | n = HCLGE_64_BIT_REG_RTN_DATANUM; | |
6119 | } | |
6120 | for (k = 0; k < n; k++) { | |
6121 | *reg_val++ = le64_to_cpu(*desc_data++); | |
6122 | ||
6123 | regs_num--; | |
6124 | if (!regs_num) | |
6125 | break; | |
6126 | } | |
6127 | } | |
6128 | ||
6129 | kfree(desc); | |
6130 | return 0; | |
6131 | } | |
6132 | ||
6133 | static int hclge_get_regs_len(struct hnae3_handle *handle) | |
6134 | { | |
6135 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6136 | struct hclge_dev *hdev = vport->back; | |
6137 | u32 regs_num_32_bit, regs_num_64_bit; | |
6138 | int ret; | |
6139 | ||
6140 | ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); | |
6141 | if (ret) { | |
6142 | dev_err(&hdev->pdev->dev, | |
6143 | "Get register number failed, ret = %d.\n", ret); | |
6144 | return -EOPNOTSUPP; | |
6145 | } | |
6146 | ||
6147 | return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); | |
6148 | } | |
6149 | ||
6150 | static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, | |
6151 | void *data) | |
6152 | { | |
6153 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6154 | struct hclge_dev *hdev = vport->back; | |
6155 | u32 regs_num_32_bit, regs_num_64_bit; | |
6156 | int ret; | |
6157 | ||
6158 | *version = hdev->fw_version; | |
6159 | ||
6160 | ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); | |
6161 | if (ret) { | |
6162 | dev_err(&hdev->pdev->dev, | |
6163 | "Get register number failed, ret = %d.\n", ret); | |
6164 | return; | |
6165 | } | |
6166 | ||
6167 | ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); | |
6168 | if (ret) { | |
6169 | dev_err(&hdev->pdev->dev, | |
6170 | "Get 32 bit register failed, ret = %d.\n", ret); | |
6171 | return; | |
6172 | } | |
6173 | ||
6174 | data = (u32 *)data + regs_num_32_bit; | |
6175 | ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, | |
6176 | data); | |
6177 | if (ret) | |
6178 | dev_err(&hdev->pdev->dev, | |
6179 | "Get 64 bit register failed, ret = %d.\n", ret); | |
6180 | } | |
6181 | ||
f6f75abc | 6182 | static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) |
07f8e940 JS |
6183 | { |
6184 | struct hclge_set_led_state_cmd *req; | |
6185 | struct hclge_desc desc; | |
6186 | int ret; | |
6187 | ||
6188 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); | |
6189 | ||
6190 | req = (struct hclge_set_led_state_cmd *)desc.data; | |
e4e87715 PL |
6191 | hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, |
6192 | HCLGE_LED_LOCATE_STATE_S, locate_led_status); | |
07f8e940 JS |
6193 | |
6194 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
6195 | if (ret) | |
6196 | dev_err(&hdev->pdev->dev, | |
6197 | "Send set led state cmd error, ret =%d\n", ret); | |
6198 | ||
6199 | return ret; | |
6200 | } | |
6201 | ||
6202 | enum hclge_led_status { | |
6203 | HCLGE_LED_OFF, | |
6204 | HCLGE_LED_ON, | |
6205 | HCLGE_LED_NO_CHANGE = 0xFF, | |
6206 | }; | |
6207 | ||
6208 | static int hclge_set_led_id(struct hnae3_handle *handle, | |
6209 | enum ethtool_phys_id_state status) | |
6210 | { | |
07f8e940 JS |
6211 | struct hclge_vport *vport = hclge_get_vport(handle); |
6212 | struct hclge_dev *hdev = vport->back; | |
07f8e940 JS |
6213 | |
6214 | switch (status) { | |
6215 | case ETHTOOL_ID_ACTIVE: | |
f6f75abc | 6216 | return hclge_set_led_status(hdev, HCLGE_LED_ON); |
07f8e940 | 6217 | case ETHTOOL_ID_INACTIVE: |
f6f75abc | 6218 | return hclge_set_led_status(hdev, HCLGE_LED_OFF); |
07f8e940 | 6219 | default: |
f6f75abc | 6220 | return -EINVAL; |
07f8e940 | 6221 | } |
07f8e940 JS |
6222 | } |
6223 | ||
0979aa0b FL |
6224 | static void hclge_get_link_mode(struct hnae3_handle *handle, |
6225 | unsigned long *supported, | |
6226 | unsigned long *advertising) | |
6227 | { | |
6228 | unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); | |
6229 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6230 | struct hclge_dev *hdev = vport->back; | |
6231 | unsigned int idx = 0; | |
6232 | ||
6233 | for (; idx < size; idx++) { | |
6234 | supported[idx] = hdev->hw.mac.supported[idx]; | |
6235 | advertising[idx] = hdev->hw.mac.advertising[idx]; | |
6236 | } | |
6237 | } | |
6238 | ||
6239 | static void hclge_get_port_type(struct hnae3_handle *handle, | |
6240 | u8 *port_type) | |
6241 | { | |
6242 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6243 | struct hclge_dev *hdev = vport->back; | |
6244 | u8 media_type = hdev->hw.mac.media_type; | |
6245 | ||
6246 | switch (media_type) { | |
6247 | case HNAE3_MEDIA_TYPE_FIBER: | |
6248 | *port_type = PORT_FIBRE; | |
6249 | break; | |
6250 | case HNAE3_MEDIA_TYPE_COPPER: | |
6251 | *port_type = PORT_TP; | |
6252 | break; | |
6253 | case HNAE3_MEDIA_TYPE_UNKNOWN: | |
6254 | default: | |
6255 | *port_type = PORT_OTHER; | |
6256 | break; | |
6257 | } | |
6258 | } | |
6259 | ||
46a3df9f S |
6260 | static const struct hnae3_ae_ops hclge_ops = { |
6261 | .init_ae_dev = hclge_init_ae_dev, | |
6262 | .uninit_ae_dev = hclge_uninit_ae_dev, | |
6263 | .init_client_instance = hclge_init_client_instance, | |
6264 | .uninit_client_instance = hclge_uninit_client_instance, | |
84e095d6 SM |
6265 | .map_ring_to_vector = hclge_map_ring_to_vector, |
6266 | .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, | |
46a3df9f | 6267 | .get_vector = hclge_get_vector, |
0d3e6631 | 6268 | .put_vector = hclge_put_vector, |
46a3df9f | 6269 | .set_promisc_mode = hclge_set_promisc_mode, |
c39c4d98 | 6270 | .set_loopback = hclge_set_loopback, |
46a3df9f S |
6271 | .start = hclge_ae_start, |
6272 | .stop = hclge_ae_stop, | |
6273 | .get_status = hclge_get_status, | |
6274 | .get_ksettings_an_result = hclge_get_ksettings_an_result, | |
6275 | .update_speed_duplex_h = hclge_update_speed_duplex_h, | |
6276 | .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, | |
6277 | .get_media_type = hclge_get_media_type, | |
6278 | .get_rss_key_size = hclge_get_rss_key_size, | |
6279 | .get_rss_indir_size = hclge_get_rss_indir_size, | |
6280 | .get_rss = hclge_get_rss, | |
6281 | .set_rss = hclge_set_rss, | |
f7db940a | 6282 | .set_rss_tuple = hclge_set_rss_tuple, |
07d29954 | 6283 | .get_rss_tuple = hclge_get_rss_tuple, |
46a3df9f S |
6284 | .get_tc_size = hclge_get_tc_size, |
6285 | .get_mac_addr = hclge_get_mac_addr, | |
6286 | .set_mac_addr = hclge_set_mac_addr, | |
6287 | .add_uc_addr = hclge_add_uc_addr, | |
6288 | .rm_uc_addr = hclge_rm_uc_addr, | |
6289 | .add_mc_addr = hclge_add_mc_addr, | |
6290 | .rm_mc_addr = hclge_rm_mc_addr, | |
40cca1c5 | 6291 | .update_mta_status = hclge_update_mta_status, |
46a3df9f S |
6292 | .set_autoneg = hclge_set_autoneg, |
6293 | .get_autoneg = hclge_get_autoneg, | |
6294 | .get_pauseparam = hclge_get_pauseparam, | |
61387774 | 6295 | .set_pauseparam = hclge_set_pauseparam, |
46a3df9f S |
6296 | .set_mtu = hclge_set_mtu, |
6297 | .reset_queue = hclge_reset_tqp, | |
6298 | .get_stats = hclge_get_stats, | |
6299 | .update_stats = hclge_update_stats, | |
6300 | .get_strings = hclge_get_strings, | |
6301 | .get_sset_count = hclge_get_sset_count, | |
6302 | .get_fw_version = hclge_get_fw_version, | |
6303 | .get_mdix_mode = hclge_get_mdix_mode, | |
391b5e93 | 6304 | .enable_vlan_filter = hclge_enable_vlan_filter, |
dc8131d8 | 6305 | .set_vlan_filter = hclge_set_vlan_filter, |
46a3df9f | 6306 | .set_vf_vlan_filter = hclge_set_vf_vlan_filter, |
052ece6d | 6307 | .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, |
4ed340ab | 6308 | .reset_event = hclge_reset_event, |
09f2af64 PL |
6309 | .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, |
6310 | .set_channels = hclge_set_channels, | |
482d2e9c | 6311 | .get_channels = hclge_get_channels, |
f34ffffd | 6312 | .get_flowctrl_adv = hclge_get_flowctrl_adv, |
77b34110 FL |
6313 | .get_regs_len = hclge_get_regs_len, |
6314 | .get_regs = hclge_get_regs, | |
07f8e940 | 6315 | .set_led_id = hclge_set_led_id, |
0979aa0b FL |
6316 | .get_link_mode = hclge_get_link_mode, |
6317 | .get_port_type = hclge_get_port_type, | |
46a3df9f S |
6318 | }; |
6319 | ||
6320 | static struct hnae3_ae_algo ae_algo = { | |
6321 | .ops = &hclge_ops, | |
46a3df9f S |
6322 | .pdev_id_table = ae_algo_pci_tbl, |
6323 | }; | |
6324 | ||
6325 | static int hclge_init(void) | |
6326 | { | |
6327 | pr_info("%s is initializing\n", HCLGE_NAME); | |
6328 | ||
854cf33a FL |
6329 | hnae3_register_ae_algo(&ae_algo); |
6330 | ||
6331 | return 0; | |
46a3df9f S |
6332 | } |
6333 | ||
6334 | static void hclge_exit(void) | |
6335 | { | |
6336 | hnae3_unregister_ae_algo(&ae_algo); | |
6337 | } | |
6338 | module_init(hclge_init); | |
6339 | module_exit(hclge_exit); | |
6340 | ||
6341 | MODULE_LICENSE("GPL"); | |
6342 | MODULE_AUTHOR("Huawei Tech. Co., Ltd."); | |
6343 | MODULE_DESCRIPTION("HCLGE Driver"); | |
6344 | MODULE_VERSION(HCLGE_MOD_VERSION); |