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net: hns3: fix a bug when getting phy address from NCL_config file
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20
21#include "hclge_cmd.h"
cacde272 22#include "hclge_dcb.h"
46a3df9f
S		 23#include "hclge_main.h"
24#include "hclge_mdio.h"
25#include "hclge_tm.h"
26#include "hnae3.h"
27
28#define HCLGE_NAME "hclge"
29#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
30#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
31#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
32#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
33
46a3df9f
S		 34static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
35 enum hclge_mta_dmac_sel_type mta_mac_sel,
36 bool enable);
37static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 38static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 39
40static struct hnae3_ae_algo ae_algo;
41
42static const struct pci_device_id ae_algo_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 50 /* required last entry */
46a3df9f
S		 51 {0, }
52};
53
54static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
55 "Mac Loopback test",
56 "Serdes Loopback test",
57 "Phy Loopback test"
58};
59
60static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
61 {"igu_rx_oversize_pkt",
62 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
63 {"igu_rx_undersize_pkt",
64 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
65 {"igu_rx_out_all_pkt",
66 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
67 {"igu_rx_uni_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
69 {"igu_rx_multi_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
71 {"igu_rx_broad_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
73 {"egu_tx_out_all_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
75 {"egu_tx_uni_pkt",
76 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
77 {"egu_tx_multi_pkt",
78 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
79 {"egu_tx_broad_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
81 {"ssu_ppp_mac_key_num",
82 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
83 {"ssu_ppp_host_key_num",
84 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
85 {"ppp_ssu_mac_rlt_num",
86 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
87 {"ppp_ssu_host_rlt_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
89 {"ssu_tx_in_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
91 {"ssu_tx_out_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
93 {"ssu_rx_in_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
95 {"ssu_rx_out_num",
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
97};
98
99static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
100 {"igu_rx_err_pkt",
101 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
102 {"igu_rx_no_eof_pkt",
103 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
104 {"igu_rx_no_sof_pkt",
105 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
106 {"egu_tx_1588_pkt",
107 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
108 {"ssu_full_drop_num",
109 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
110 {"ssu_part_drop_num",
111 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
112 {"ppp_key_drop_num",
113 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
114 {"ppp_rlt_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
116 {"ssu_key_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
118 {"pkt_curr_buf_cnt",
119 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
120 {"qcn_fb_rcv_cnt",
121 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
122 {"qcn_fb_drop_cnt",
123 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
124 {"qcn_fb_invaild_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
126 {"rx_packet_tc0_in_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
128 {"rx_packet_tc1_in_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
130 {"rx_packet_tc2_in_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
132 {"rx_packet_tc3_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
134 {"rx_packet_tc4_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
136 {"rx_packet_tc5_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
138 {"rx_packet_tc6_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
140 {"rx_packet_tc7_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
142 {"rx_packet_tc0_out_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
144 {"rx_packet_tc1_out_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
146 {"rx_packet_tc2_out_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
148 {"rx_packet_tc3_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
150 {"rx_packet_tc4_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
152 {"rx_packet_tc5_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
154 {"rx_packet_tc6_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
156 {"rx_packet_tc7_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
158 {"tx_packet_tc0_in_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
160 {"tx_packet_tc1_in_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
162 {"tx_packet_tc2_in_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
164 {"tx_packet_tc3_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
166 {"tx_packet_tc4_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
168 {"tx_packet_tc5_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
170 {"tx_packet_tc6_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
172 {"tx_packet_tc7_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
174 {"tx_packet_tc0_out_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
176 {"tx_packet_tc1_out_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
178 {"tx_packet_tc2_out_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
180 {"tx_packet_tc3_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
182 {"tx_packet_tc4_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
184 {"tx_packet_tc5_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
186 {"tx_packet_tc6_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
188 {"tx_packet_tc7_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
190 {"pkt_curr_buf_tc0_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
192 {"pkt_curr_buf_tc1_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
194 {"pkt_curr_buf_tc2_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
196 {"pkt_curr_buf_tc3_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
198 {"pkt_curr_buf_tc4_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
200 {"pkt_curr_buf_tc5_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
202 {"pkt_curr_buf_tc6_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
204 {"pkt_curr_buf_tc7_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
206 {"mb_uncopy_num",
207 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
208 {"lo_pri_unicast_rlt_drop_num",
209 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
210 {"hi_pri_multicast_rlt_drop_num",
211 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
212 {"lo_pri_multicast_rlt_drop_num",
213 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
214 {"rx_oq_drop_pkt_cnt",
215 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
216 {"tx_oq_drop_pkt_cnt",
217 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
218 {"nic_l2_err_drop_pkt_cnt",
219 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
220 {"roc_l2_err_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
222};
223
224static const struct hclge_comm_stats_str g_mac_stats_string[] = {
225 {"mac_tx_mac_pause_num",
226 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
227 {"mac_rx_mac_pause_num",
228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
229 {"mac_tx_pfc_pri0_pkt_num",
230 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
231 {"mac_tx_pfc_pri1_pkt_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
233 {"mac_tx_pfc_pri2_pkt_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
235 {"mac_tx_pfc_pri3_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
237 {"mac_tx_pfc_pri4_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
239 {"mac_tx_pfc_pri5_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
241 {"mac_tx_pfc_pri6_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
243 {"mac_tx_pfc_pri7_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
245 {"mac_rx_pfc_pri0_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
247 {"mac_rx_pfc_pri1_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
249 {"mac_rx_pfc_pri2_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
251 {"mac_rx_pfc_pri3_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
253 {"mac_rx_pfc_pri4_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
255 {"mac_rx_pfc_pri5_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
257 {"mac_rx_pfc_pri6_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
259 {"mac_rx_pfc_pri7_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
261 {"mac_tx_total_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
263 {"mac_tx_total_oct_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
265 {"mac_tx_good_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
267 {"mac_tx_bad_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
269 {"mac_tx_good_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
271 {"mac_tx_bad_oct_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
273 {"mac_tx_uni_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
275 {"mac_tx_multi_pkt_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
277 {"mac_tx_broad_pkt_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
279 {"mac_tx_undersize_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
281 {"mac_tx_overrsize_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
283 {"mac_tx_64_oct_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
285 {"mac_tx_65_127_oct_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
287 {"mac_tx_128_255_oct_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
289 {"mac_tx_256_511_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
291 {"mac_tx_512_1023_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
293 {"mac_tx_1024_1518_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
295 {"mac_tx_1519_max_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
297 {"mac_rx_total_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
299 {"mac_rx_total_oct_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
301 {"mac_rx_good_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
303 {"mac_rx_bad_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
305 {"mac_rx_good_oct_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
307 {"mac_rx_bad_oct_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
309 {"mac_rx_uni_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
311 {"mac_rx_multi_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
313 {"mac_rx_broad_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
315 {"mac_rx_undersize_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
317 {"mac_rx_overrsize_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
319 {"mac_rx_64_oct_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
321 {"mac_rx_65_127_oct_pkt_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
323 {"mac_rx_128_255_oct_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
325 {"mac_rx_256_511_oct_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
327 {"mac_rx_512_1023_oct_pkt_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
329 {"mac_rx_1024_1518_oct_pkt_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
331 {"mac_rx_1519_max_oct_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
333
334 {"mac_trans_fragment_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
336 {"mac_trans_undermin_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
338 {"mac_trans_jabber_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
340 {"mac_trans_err_all_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
342 {"mac_trans_from_app_good_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
344 {"mac_trans_from_app_bad_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
346 {"mac_rcv_fragment_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
348 {"mac_rcv_undermin_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
350 {"mac_rcv_jabber_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
352 {"mac_rcv_fcs_err_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
354 {"mac_rcv_send_app_good_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
356 {"mac_rcv_send_app_bad_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
358};
359
360static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
361{
362#define HCLGE_64_BIT_CMD_NUM 5
363#define HCLGE_64_BIT_RTN_DATANUM 4
364 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
365 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 366 __le64 *desc_data;
46a3df9f
S		 367 int i, k, n;
368 int ret;
369
370 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
371 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
372 if (ret) {
373 dev_err(&hdev->pdev->dev,
374 "Get 64 bit pkt stats fail, status = %d.\n", ret);
375 return ret;
376 }
377
378 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
379 if (unlikely(i == 0)) {
a90bb9a5 380 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 381 n = HCLGE_64_BIT_RTN_DATANUM - 1;
382 } else {
a90bb9a5 383 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 384 n = HCLGE_64_BIT_RTN_DATANUM;
385 }
386 for (k = 0; k < n; k++) {
a90bb9a5 387 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 388 desc_data++;
389 }
390 }
391
392 return 0;
393}
394
395static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
396{
397 stats->pkt_curr_buf_cnt = 0;
398 stats->pkt_curr_buf_tc0_cnt = 0;
399 stats->pkt_curr_buf_tc1_cnt = 0;
400 stats->pkt_curr_buf_tc2_cnt = 0;
401 stats->pkt_curr_buf_tc3_cnt = 0;
402 stats->pkt_curr_buf_tc4_cnt = 0;
403 stats->pkt_curr_buf_tc5_cnt = 0;
404 stats->pkt_curr_buf_tc6_cnt = 0;
405 stats->pkt_curr_buf_tc7_cnt = 0;
406}
407
408static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
409{
410#define HCLGE_32_BIT_CMD_NUM 8
411#define HCLGE_32_BIT_RTN_DATANUM 8
412
413 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
414 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 415 __le32 *desc_data;
46a3df9f
S		 416 int i, k, n;
417 u64 *data;
418 int ret;
419
420 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
421 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
422
423 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
424 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
425 if (ret) {
426 dev_err(&hdev->pdev->dev,
427 "Get 32 bit pkt stats fail, status = %d.\n", ret);
428
429 return ret;
430 }
431
432 hclge_reset_partial_32bit_counter(all_32_bit_stats);
433 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
434 if (unlikely(i == 0)) {
a90bb9a5
YL		 435 __le16 *desc_data_16bit;
436
46a3df9f 437 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 438 le32_to_cpu(desc[i].data[0]);
439
440 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 441 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 442 le16_to_cpu(*desc_data_16bit);
443
444 desc_data_16bit++;
46a3df9f 445 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 446 le16_to_cpu(*desc_data_16bit);
46a3df9f 447
a90bb9a5 448 desc_data = &desc[i].data[2];
46a3df9f
S		 449 n = HCLGE_32_BIT_RTN_DATANUM - 4;
450 } else {
a90bb9a5 451 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 452 n = HCLGE_32_BIT_RTN_DATANUM;
453 }
454 for (k = 0; k < n; k++) {
a90bb9a5 455 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 456 desc_data++;
457 }
458 }
459
460 return 0;
461}
462
463static int hclge_mac_update_stats(struct hclge_dev *hdev)
464{
465#define HCLGE_MAC_CMD_NUM 17
466#define HCLGE_RTN_DATA_NUM 4
467
468 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
469 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 470 __le64 *desc_data;
46a3df9f
S		 471 int i, k, n;
472 int ret;
473
474 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
475 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
476 if (ret) {
477 dev_err(&hdev->pdev->dev,
478 "Get MAC pkt stats fail, status = %d.\n", ret);
479
480 return ret;
481 }
482
483 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
484 if (unlikely(i == 0)) {
a90bb9a5 485 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 486 n = HCLGE_RTN_DATA_NUM - 2;
487 } else {
a90bb9a5 488 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 489 n = HCLGE_RTN_DATA_NUM;
490 }
491 for (k = 0; k < n; k++) {
a90bb9a5 492 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 493 desc_data++;
494 }
495 }
496
497 return 0;
498}
499
500static int hclge_tqps_update_stats(struct hnae3_handle *handle)
501{
502 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
503 struct hclge_vport *vport = hclge_get_vport(handle);
504 struct hclge_dev *hdev = vport->back;
505 struct hnae3_queue *queue;
506 struct hclge_desc desc[1];
507 struct hclge_tqp *tqp;
508 int ret, i;
509
510 for (i = 0; i < kinfo->num_tqps; i++) {
511 queue = handle->kinfo.tqp[i];
512 tqp = container_of(queue, struct hclge_tqp, q);
513 /* command : HCLGE_OPC_QUERY_IGU_STAT */
514 hclge_cmd_setup_basic_desc(&desc[0],
515 HCLGE_OPC_QUERY_RX_STATUS,
516 true);
517
a90bb9a5 518 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 519 ret = hclge_cmd_send(&hdev->hw, desc, 1);
520 if (ret) {
521 dev_err(&hdev->pdev->dev,
522 "Query tqp stat fail, status = %d,queue = %d\n",
523 ret, i);
524 return ret;
525 }
526 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
a90bb9a5 527 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 528 }
529
530 for (i = 0; i < kinfo->num_tqps; i++) {
531 queue = handle->kinfo.tqp[i];
532 tqp = container_of(queue, struct hclge_tqp, q);
533 /* command : HCLGE_OPC_QUERY_IGU_STAT */
534 hclge_cmd_setup_basic_desc(&desc[0],
535 HCLGE_OPC_QUERY_TX_STATUS,
536 true);
537
a90bb9a5 538 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 539 ret = hclge_cmd_send(&hdev->hw, desc, 1);
540 if (ret) {
541 dev_err(&hdev->pdev->dev,
542 "Query tqp stat fail, status = %d,queue = %d\n",
543 ret, i);
544 return ret;
545 }
546 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
a90bb9a5 547 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 548 }
549
550 return 0;
551}
552
553static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
554{
555 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
556 struct hclge_tqp *tqp;
557 u64 *buff = data;
558 int i;
559
560 for (i = 0; i < kinfo->num_tqps; i++) {
561 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 562 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 563 }
564
565 for (i = 0; i < kinfo->num_tqps; i++) {
566 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 567 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 568 }
569
570 return buff;
571}
572
573static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
574{
575 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
576
577 return kinfo->num_tqps * (2);
578}
579
580static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
581{
582 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
583 u8 *buff = data;
584 int i = 0;
585
586 for (i = 0; i < kinfo->num_tqps; i++) {
587 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
588 struct hclge_tqp, q);
589 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
590 tqp->index);
591 buff = buff + ETH_GSTRING_LEN;
592 }
593
594 for (i = 0; i < kinfo->num_tqps; i++) {
595 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
596 struct hclge_tqp, q);
597 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
598 tqp->index);
599 buff = buff + ETH_GSTRING_LEN;
600 }
601
602 return buff;
603}
604
605static u64 *hclge_comm_get_stats(void *comm_stats,
606 const struct hclge_comm_stats_str strs[],
607 int size, u64 *data)
608{
609 u64 *buf = data;
610 u32 i;
611
612 for (i = 0; i < size; i++)
613 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
614
615 return buf + size;
616}
617
618static u8 *hclge_comm_get_strings(u32 stringset,
619 const struct hclge_comm_stats_str strs[],
620 int size, u8 *data)
621{
622 char *buff = (char *)data;
623 u32 i;
624
625 if (stringset != ETH_SS_STATS)
626 return buff;
627
628 for (i = 0; i < size; i++) {
629 snprintf(buff, ETH_GSTRING_LEN,
630 strs[i].desc);
631 buff = buff + ETH_GSTRING_LEN;
632 }
633
634 return (u8 *)buff;
635}
636
637static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
638 struct net_device_stats *net_stats)
639{
640 net_stats->tx_dropped = 0;
641 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
642 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
643 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
644
645 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
646 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
647 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
648 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
649 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
650 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
651
652 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
653 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
654
655 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
656 net_stats->rx_length_errors =
657 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
658 net_stats->rx_length_errors +=
659 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
660 net_stats->rx_over_errors =
661 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
662}
663
664static void hclge_update_stats_for_all(struct hclge_dev *hdev)
665{
666 struct hnae3_handle *handle;
667 int status;
668
669 handle = &hdev->vport[0].nic;
670 if (handle->client) {
671 status = hclge_tqps_update_stats(handle);
672 if (status) {
673 dev_err(&hdev->pdev->dev,
674 "Update TQPS stats fail, status = %d.\n",
675 status);
676 }
677 }
678
679 status = hclge_mac_update_stats(hdev);
680 if (status)
681 dev_err(&hdev->pdev->dev,
682 "Update MAC stats fail, status = %d.\n", status);
683
684 status = hclge_32_bit_update_stats(hdev);
685 if (status)
686 dev_err(&hdev->pdev->dev,
687 "Update 32 bit stats fail, status = %d.\n",
688 status);
689
690 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
691}
692
693static void hclge_update_stats(struct hnae3_handle *handle,
694 struct net_device_stats *net_stats)
695{
696 struct hclge_vport *vport = hclge_get_vport(handle);
697 struct hclge_dev *hdev = vport->back;
698 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
699 int status;
700
701 status = hclge_mac_update_stats(hdev);
702 if (status)
703 dev_err(&hdev->pdev->dev,
704 "Update MAC stats fail, status = %d.\n",
705 status);
706
707 status = hclge_32_bit_update_stats(hdev);
708 if (status)
709 dev_err(&hdev->pdev->dev,
710 "Update 32 bit stats fail, status = %d.\n",
711 status);
712
713 status = hclge_64_bit_update_stats(hdev);
714 if (status)
715 dev_err(&hdev->pdev->dev,
716 "Update 64 bit stats fail, status = %d.\n",
717 status);
718
719 status = hclge_tqps_update_stats(handle);
720 if (status)
721 dev_err(&hdev->pdev->dev,
722 "Update TQPS stats fail, status = %d.\n",
723 status);
724
725 hclge_update_netstat(hw_stats, net_stats);
726}
727
728static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
729{
730#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
731
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 int count = 0;
735
736 /* Loopback test support rules:
737 * mac: only GE mode support
738 * serdes: all mac mode will support include GE/XGE/LGE/CGE
739 * phy: only support when phy device exist on board
740 */
741 if (stringset == ETH_SS_TEST) {
742 /* clear loopback bit flags at first */
743 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
744 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
745 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
746 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
747 count += 1;
748 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
749 } else {
750 count = -EOPNOTSUPP;
751 }
752 } else if (stringset == ETH_SS_STATS) {
753 count = ARRAY_SIZE(g_mac_stats_string) +
754 ARRAY_SIZE(g_all_32bit_stats_string) +
755 ARRAY_SIZE(g_all_64bit_stats_string) +
756 hclge_tqps_get_sset_count(handle, stringset);
757 }
758
759 return count;
760}
761
762static void hclge_get_strings(struct hnae3_handle *handle,
763 u32 stringset,
764 u8 *data)
765{
766 u8 *p = (char *)data;
767 int size;
768
769 if (stringset == ETH_SS_STATS) {
770 size = ARRAY_SIZE(g_mac_stats_string);
771 p = hclge_comm_get_strings(stringset,
772 g_mac_stats_string,
773 size,
774 p);
775 size = ARRAY_SIZE(g_all_32bit_stats_string);
776 p = hclge_comm_get_strings(stringset,
777 g_all_32bit_stats_string,
778 size,
779 p);
780 size = ARRAY_SIZE(g_all_64bit_stats_string);
781 p = hclge_comm_get_strings(stringset,
782 g_all_64bit_stats_string,
783 size,
784 p);
785 p = hclge_tqps_get_strings(handle, p);
786 } else if (stringset == ETH_SS_TEST) {
787 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
788 memcpy(p,
789 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
790 ETH_GSTRING_LEN);
791 p += ETH_GSTRING_LEN;
792 }
793 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
794 memcpy(p,
795 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
796 ETH_GSTRING_LEN);
797 p += ETH_GSTRING_LEN;
798 }
799 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
800 memcpy(p,
801 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
802 ETH_GSTRING_LEN);
803 p += ETH_GSTRING_LEN;
804 }
805 }
806}
807
808static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
809{
810 struct hclge_vport *vport = hclge_get_vport(handle);
811 struct hclge_dev *hdev = vport->back;
812 u64 *p;
813
814 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
815 g_mac_stats_string,
816 ARRAY_SIZE(g_mac_stats_string),
817 data);
818 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
819 g_all_32bit_stats_string,
820 ARRAY_SIZE(g_all_32bit_stats_string),
821 p);
822 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
823 g_all_64bit_stats_string,
824 ARRAY_SIZE(g_all_64bit_stats_string),
825 p);
826 p = hclge_tqps_get_stats(handle, p);
827}
828
829static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 830 struct hclge_func_status_cmd *status)
46a3df9f
S		 831{
832 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
833 return -EINVAL;
834
835 /* Set the pf to main pf */
836 if (status->pf_state & HCLGE_PF_STATE_MAIN)
837 hdev->flag |= HCLGE_FLAG_MAIN;
838 else
839 hdev->flag &= ~HCLGE_FLAG_MAIN;
840
46a3df9f
S		 841 return 0;
842}
843
844static int hclge_query_function_status(struct hclge_dev *hdev)
845{
d44f9b63 846 struct hclge_func_status_cmd *req;
46a3df9f
S		 847 struct hclge_desc desc;
848 int timeout = 0;
849 int ret;
850
851 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 852 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 853
854 do {
855 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
856 if (ret) {
857 dev_err(&hdev->pdev->dev,
858 "query function status failed %d.\n",
859 ret);
860
861 return ret;
862 }
863
864 /* Check pf reset is done */
865 if (req->pf_state)
866 break;
867 usleep_range(1000, 2000);
868 } while (timeout++ < 5);
869
870 ret = hclge_parse_func_status(hdev, req);
871
872 return ret;
873}
874
875static int hclge_query_pf_resource(struct hclge_dev *hdev)
876{
d44f9b63 877 struct hclge_pf_res_cmd *req;
46a3df9f
S		 878 struct hclge_desc desc;
879 int ret;
880
881 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
882 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
883 if (ret) {
884 dev_err(&hdev->pdev->dev,
885 "query pf resource failed %d.\n", ret);
886 return ret;
887 }
888
d44f9b63 889 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 890 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
891 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
892
e92a0843 893 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 894 hdev->num_roce_msix =
895 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
896 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
897
898 /* PF should have NIC vectors and Roce vectors,
899 * NIC vectors are queued before Roce vectors.
900 */
901 hdev->num_msi = hdev->num_roce_msix + HCLGE_ROCE_VECTOR_OFFSET;
902 } else {
903 hdev->num_msi =
904 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
905 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
906 }
907
908 return 0;
909}
910
911static int hclge_parse_speed(int speed_cmd, int *speed)
912{
913 switch (speed_cmd) {
914 case 6:
915 *speed = HCLGE_MAC_SPEED_10M;
916 break;
917 case 7:
918 *speed = HCLGE_MAC_SPEED_100M;
919 break;
920 case 0:
921 *speed = HCLGE_MAC_SPEED_1G;
922 break;
923 case 1:
924 *speed = HCLGE_MAC_SPEED_10G;
925 break;
926 case 2:
927 *speed = HCLGE_MAC_SPEED_25G;
928 break;
929 case 3:
930 *speed = HCLGE_MAC_SPEED_40G;
931 break;
932 case 4:
933 *speed = HCLGE_MAC_SPEED_50G;
934 break;
935 case 5:
936 *speed = HCLGE_MAC_SPEED_100G;
937 break;
938 default:
939 return -EINVAL;
940 }
941
942 return 0;
943}
944
945static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
946{
d44f9b63 947 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 948 u64 mac_addr_tmp_high;
949 u64 mac_addr_tmp;
950 int i;
951
d44f9b63 952 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 953
954 /* get the configuration */
955 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
956 HCLGE_CFG_VMDQ_M,
957 HCLGE_CFG_VMDQ_S);
958 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
959 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
960 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
961 HCLGE_CFG_TQP_DESC_N_M,
962 HCLGE_CFG_TQP_DESC_N_S);
963
964 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
965 HCLGE_CFG_PHY_ADDR_M,
966 HCLGE_CFG_PHY_ADDR_S);
967 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
968 HCLGE_CFG_MEDIA_TP_M,
969 HCLGE_CFG_MEDIA_TP_S);
970 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
971 HCLGE_CFG_RX_BUF_LEN_M,
972 HCLGE_CFG_RX_BUF_LEN_S);
973 /* get mac_address */
974 mac_addr_tmp = __le32_to_cpu(req->param[2]);
975 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
976 HCLGE_CFG_MAC_ADDR_H_M,
977 HCLGE_CFG_MAC_ADDR_H_S);
978
979 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
980
981 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
982 HCLGE_CFG_DEFAULT_SPEED_M,
983 HCLGE_CFG_DEFAULT_SPEED_S);
984 for (i = 0; i < ETH_ALEN; i++)
985 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
986
d44f9b63 987 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f
S		 988 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
989}
990
991/* hclge_get_cfg: query the static parameter from flash
992 * @hdev: pointer to struct hclge_dev
993 * @hcfg: the config structure to be getted
994 */
995static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
996{
997 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 998 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 999 int i, ret;
1000
1001 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1002 u32 offset = 0;
1003
d44f9b63 1004 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1005 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1006 true);
a90bb9a5 1007 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1008 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1009 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1010 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1011 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1012 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1013 }
1014
1015 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1016 if (ret) {
1017 dev_err(&hdev->pdev->dev,
1018 "get config failed %d.\n", ret);
1019 return ret;
1020 }
1021
1022 hclge_parse_cfg(hcfg, desc);
1023 return 0;
1024}
1025
1026static int hclge_get_cap(struct hclge_dev *hdev)
1027{
1028 int ret;
1029
1030 ret = hclge_query_function_status(hdev);
1031 if (ret) {
1032 dev_err(&hdev->pdev->dev,
1033 "query function status error %d.\n", ret);
1034 return ret;
1035 }
1036
1037 /* get pf resource */
1038 ret = hclge_query_pf_resource(hdev);
1039 if (ret) {
1040 dev_err(&hdev->pdev->dev,
1041 "query pf resource error %d.\n", ret);
1042 return ret;
1043 }
1044
1045 return 0;
1046}
1047
1048static int hclge_configure(struct hclge_dev *hdev)
1049{
1050 struct hclge_cfg cfg;
1051 int ret, i;
1052
1053 ret = hclge_get_cfg(hdev, &cfg);
1054 if (ret) {
1055 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1056 return ret;
1057 }
1058
1059 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1060 hdev->base_tqp_pid = 0;
1061 hdev->rss_size_max = 1;
1062 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1063 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1064 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1065 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1066 hdev->num_desc = cfg.tqp_desc_num;
1067 hdev->tm_info.num_pg = 1;
cacde272 1068 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1069 hdev->tm_info.hw_pfc_map = 0;
1070
1071 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1072 if (ret) {
1073 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1074 return ret;
1075 }
1076
cacde272
YL		 1077 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1078 (hdev->tc_max < 1)) {
46a3df9f 1079 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1080 hdev->tc_max);
1081 hdev->tc_max = 1;
46a3df9f
S		 1082 }
1083
cacde272
YL		 1084 /* Dev does not support DCB */
1085 if (!hnae3_dev_dcb_supported(hdev)) {
1086 hdev->tc_max = 1;
1087 hdev->pfc_max = 0;
1088 } else {
1089 hdev->pfc_max = hdev->tc_max;
1090 }
1091
1092 hdev->tm_info.num_tc = hdev->tc_max;
1093
46a3df9f 1094 /* Currently not support uncontiuous tc */
cacde272 1095 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1096 hnae_set_bit(hdev->hw_tc_map, i, 1);
1097
1098 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1099 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1100 else
1101 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1102
1103 return ret;
1104}
1105
1106static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1107 int tso_mss_max)
1108{
d44f9b63 1109 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1110 struct hclge_desc desc;
a90bb9a5 1111 u16 tso_mss;
46a3df9f
S		 1112
1113 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1114
d44f9b63 1115 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1116
1117 tso_mss = 0;
1118 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1119 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1120 req->tso_mss_min = cpu_to_le16(tso_mss);
1121
1122 tso_mss = 0;
1123 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1124 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1125 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1126
1127 return hclge_cmd_send(&hdev->hw, &desc, 1);
1128}
1129
1130static int hclge_alloc_tqps(struct hclge_dev *hdev)
1131{
1132 struct hclge_tqp *tqp;
1133 int i;
1134
1135 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1136 sizeof(struct hclge_tqp), GFP_KERNEL);
1137 if (!hdev->htqp)
1138 return -ENOMEM;
1139
1140 tqp = hdev->htqp;
1141
1142 for (i = 0; i < hdev->num_tqps; i++) {
1143 tqp->dev = &hdev->pdev->dev;
1144 tqp->index = i;
1145
1146 tqp->q.ae_algo = &ae_algo;
1147 tqp->q.buf_size = hdev->rx_buf_len;
1148 tqp->q.desc_num = hdev->num_desc;
1149 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1150 i * HCLGE_TQP_REG_SIZE;
1151
1152 tqp++;
1153 }
1154
1155 return 0;
1156}
1157
1158static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1159 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1160{
d44f9b63 1161 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1162 struct hclge_desc desc;
1163 int ret;
1164
1165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1166
d44f9b63 1167 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1168 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1169 req->tqp_vf = func_id;
46a3df9f
S		 1170 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1171 1 << HCLGE_TQP_MAP_EN_B;
1172 req->tqp_vid = cpu_to_le16(tqp_vid);
1173
1174 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1175 if (ret) {
1176 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1177 ret);
1178 return ret;
1179 }
1180
1181 return 0;
1182}
1183
1184static int hclge_assign_tqp(struct hclge_vport *vport,
1185 struct hnae3_queue **tqp, u16 num_tqps)
1186{
1187 struct hclge_dev *hdev = vport->back;
7df7dad6 1188 int i, alloced;
46a3df9f
S		 1189
1190 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1191 alloced < num_tqps; i++) {
1192 if (!hdev->htqp[i].alloced) {
1193 hdev->htqp[i].q.handle = &vport->nic;
1194 hdev->htqp[i].q.tqp_index = alloced;
1195 tqp[alloced] = &hdev->htqp[i].q;
1196 hdev->htqp[i].alloced = true;
46a3df9f
S		 1197 alloced++;
1198 }
1199 }
1200 vport->alloc_tqps = num_tqps;
1201
1202 return 0;
1203}
1204
1205static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1206{
1207 struct hnae3_handle *nic = &vport->nic;
1208 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1209 struct hclge_dev *hdev = vport->back;
1210 int i, ret;
1211
1212 kinfo->num_desc = hdev->num_desc;
1213 kinfo->rx_buf_len = hdev->rx_buf_len;
1214 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1215 kinfo->rss_size
1216 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1217 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1218
1219 for (i = 0; i < HNAE3_MAX_TC; i++) {
1220 if (hdev->hw_tc_map & BIT(i)) {
1221 kinfo->tc_info[i].enable = true;
1222 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1223 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1224 kinfo->tc_info[i].tc = i;
1225 } else {
1226 /* Set to default queue if TC is disable */
1227 kinfo->tc_info[i].enable = false;
1228 kinfo->tc_info[i].tqp_offset = 0;
1229 kinfo->tc_info[i].tqp_count = 1;
1230 kinfo->tc_info[i].tc = 0;
1231 }
1232 }
1233
1234 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1235 sizeof(struct hnae3_queue *), GFP_KERNEL);
1236 if (!kinfo->tqp)
1237 return -ENOMEM;
1238
1239 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1240 if (ret) {
1241 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1242 return -EINVAL;
1243 }
1244
1245 return 0;
1246}
1247
7df7dad6
L		 1248static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1249 struct hclge_vport *vport)
1250{
1251 struct hnae3_handle *nic = &vport->nic;
1252 struct hnae3_knic_private_info *kinfo;
1253 u16 i;
1254
1255 kinfo = &nic->kinfo;
1256 for (i = 0; i < kinfo->num_tqps; i++) {
1257 struct hclge_tqp *q =
1258 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1259 bool is_pf;
1260 int ret;
1261
1262 is_pf = !(vport->vport_id);
1263 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1264 i, is_pf);
1265 if (ret)
1266 return ret;
1267 }
1268
1269 return 0;
1270}
1271
1272static int hclge_map_tqp(struct hclge_dev *hdev)
1273{
1274 struct hclge_vport *vport = hdev->vport;
1275 u16 i, num_vport;
1276
1277 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1278 for (i = 0; i < num_vport; i++) {
1279 int ret;
1280
1281 ret = hclge_map_tqp_to_vport(hdev, vport);
1282 if (ret)
1283 return ret;
1284
1285 vport++;
1286 }
1287
1288 return 0;
1289}
1290
46a3df9f
S		 1291static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1292{
1293 /* this would be initialized later */
1294}
1295
1296static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1297{
1298 struct hnae3_handle *nic = &vport->nic;
1299 struct hclge_dev *hdev = vport->back;
1300 int ret;
1301
1302 nic->pdev = hdev->pdev;
1303 nic->ae_algo = &ae_algo;
1304 nic->numa_node_mask = hdev->numa_node_mask;
1305
1306 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1307 ret = hclge_knic_setup(vport, num_tqps);
1308 if (ret) {
1309 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1310 ret);
1311 return ret;
1312 }
1313 } else {
1314 hclge_unic_setup(vport, num_tqps);
1315 }
1316
1317 return 0;
1318}
1319
1320static int hclge_alloc_vport(struct hclge_dev *hdev)
1321{
1322 struct pci_dev *pdev = hdev->pdev;
1323 struct hclge_vport *vport;
1324 u32 tqp_main_vport;
1325 u32 tqp_per_vport;
1326 int num_vport, i;
1327 int ret;
1328
1329 /* We need to alloc a vport for main NIC of PF */
1330 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1331
1332 if (hdev->num_tqps < num_vport)
1333 num_vport = hdev->num_tqps;
1334
1335 /* Alloc the same number of TQPs for every vport */
1336 tqp_per_vport = hdev->num_tqps / num_vport;
1337 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1338
1339 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1340 GFP_KERNEL);
1341 if (!vport)
1342 return -ENOMEM;
1343
1344 hdev->vport = vport;
1345 hdev->num_alloc_vport = num_vport;
1346
1347#ifdef CONFIG_PCI_IOV
1348 /* Enable SRIOV */
1349 if (hdev->num_req_vfs) {
1350 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1351 hdev->num_req_vfs);
1352 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1353 if (ret) {
1354 hdev->num_alloc_vfs = 0;
1355 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1356 ret);
1357 return ret;
1358 }
1359 }
1360 hdev->num_alloc_vfs = hdev->num_req_vfs;
1361#endif
1362
1363 for (i = 0; i < num_vport; i++) {
1364 vport->back = hdev;
1365 vport->vport_id = i;
1366
1367 if (i == 0)
1368 ret = hclge_vport_setup(vport, tqp_main_vport);
1369 else
1370 ret = hclge_vport_setup(vport, tqp_per_vport);
1371 if (ret) {
1372 dev_err(&pdev->dev,
1373 "vport setup failed for vport %d, %d\n",
1374 i, ret);
1375 return ret;
1376 }
1377
1378 vport++;
1379 }
1380
1381 return 0;
1382}
1383
acf61ecd
YL		 1384static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1385 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1386{
1387/* TX buffer size is unit by 128 byte */
1388#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1389#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1390 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1391 struct hclge_desc desc;
1392 int ret;
1393 u8 i;
1394
d44f9b63 1395 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1396
1397 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1398 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1399 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1400
46a3df9f
S		 1401 req->tx_pkt_buff[i] =
1402 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1403 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1404 }
46a3df9f
S		 1405
1406 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1407 if (ret) {
1408 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1409 ret);
1410 return ret;
1411 }
1412
1413 return 0;
1414}
1415
acf61ecd
YL		 1416static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1417 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1418{
acf61ecd 1419 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1420
1421 if (ret) {
1422 dev_err(&hdev->pdev->dev,
1423 "tx buffer alloc failed %d\n", ret);
1424 return ret;
1425 }
1426
1427 return 0;
1428}
1429
1430static int hclge_get_tc_num(struct hclge_dev *hdev)
1431{
1432 int i, cnt = 0;
1433
1434 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1435 if (hdev->hw_tc_map & BIT(i))
1436 cnt++;
1437 return cnt;
1438}
1439
1440static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1441{
1442 int i, cnt = 0;
1443
1444 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1445 if (hdev->hw_tc_map & BIT(i) &&
1446 hdev->tm_info.hw_pfc_map & BIT(i))
1447 cnt++;
1448 return cnt;
1449}
1450
1451/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1452static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1453 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1454{
1455 struct hclge_priv_buf *priv;
1456 int i, cnt = 0;
1457
1458 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1459 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1460 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1461 priv->enable)
1462 cnt++;
1463 }
1464
1465 return cnt;
1466}
1467
1468/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1469static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1470 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1471{
1472 struct hclge_priv_buf *priv;
1473 int i, cnt = 0;
1474
1475 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1476 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1477 if (hdev->hw_tc_map & BIT(i) &&
1478 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1479 priv->enable)
1480 cnt++;
1481 }
1482
1483 return cnt;
1484}
1485
acf61ecd 1486static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1487{
1488 struct hclge_priv_buf *priv;
1489 u32 rx_priv = 0;
1490 int i;
1491
1492 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1493 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1494 if (priv->enable)
1495 rx_priv += priv->buf_size;
1496 }
1497 return rx_priv;
1498}
1499
acf61ecd 1500static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1501{
1502 u32 i, total_tx_size = 0;
1503
1504 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1505 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1506
1507 return total_tx_size;
1508}
1509
acf61ecd
YL		 1510static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1511 struct hclge_pkt_buf_alloc *buf_alloc,
1512 u32 rx_all)
46a3df9f
S		 1513{
1514 u32 shared_buf_min, shared_buf_tc, shared_std;
1515 int tc_num, pfc_enable_num;
1516 u32 shared_buf;
1517 u32 rx_priv;
1518 int i;
1519
1520 tc_num = hclge_get_tc_num(hdev);
1521 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1522
d221df4e
YL		 1523 if (hnae3_dev_dcb_supported(hdev))
1524 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1525 else
1526 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1527
46a3df9f
S		 1528 shared_buf_tc = pfc_enable_num * hdev->mps +
1529 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1530 hdev->mps;
1531 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1532
acf61ecd 1533 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1534 if (rx_all <= rx_priv + shared_std)
1535 return false;
1536
1537 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1538 buf_alloc->s_buf.buf_size = shared_buf;
1539 buf_alloc->s_buf.self.high = shared_buf;
1540 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1541
1542 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1543 if ((hdev->hw_tc_map & BIT(i)) &&
1544 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1545 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1546 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1547 } else {
acf61ecd
YL		 1548 buf_alloc->s_buf.tc_thrd[i].low = 0;
1549 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1550 }
1551 }
1552
1553 return true;
1554}
1555
acf61ecd
YL		 1556static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1557 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1558{
1559 u32 i, total_size;
1560
1561 total_size = hdev->pkt_buf_size;
1562
1563 /* alloc tx buffer for all enabled tc */
1564 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1565 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1566
1567 if (total_size < HCLGE_DEFAULT_TX_BUF)
1568 return -ENOMEM;
1569
1570 if (hdev->hw_tc_map & BIT(i))
1571 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1572 else
1573 priv->tx_buf_size = 0;
1574
1575 total_size -= priv->tx_buf_size;
1576 }
1577
1578 return 0;
1579}
1580
46a3df9f
S		 1581/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1582 * @hdev: pointer to struct hclge_dev
acf61ecd 1583 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1584 * @return: 0: calculate sucessful, negative: fail
1585 */
1db9b1bf
YL		 1586static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1587 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1588{
9ffe79a9 1589 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1590 int no_pfc_priv_num, pfc_priv_num;
1591 struct hclge_priv_buf *priv;
1592 int i;
1593
acf61ecd 1594 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1595
d602a525
YL		 1596 /* When DCB is not supported, rx private
1597 * buffer is not allocated.
1598 */
1599 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1600 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1601 return -ENOMEM;
1602
1603 return 0;
1604 }
1605
46a3df9f
S		 1606 /* step 1, try to alloc private buffer for all enabled tc */
1607 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1608 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1609 if (hdev->hw_tc_map & BIT(i)) {
1610 priv->enable = 1;
1611 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1612 priv->wl.low = hdev->mps;
1613 priv->wl.high = priv->wl.low + hdev->mps;
1614 priv->buf_size = priv->wl.high +
1615 HCLGE_DEFAULT_DV;
1616 } else {
1617 priv->wl.low = 0;
1618 priv->wl.high = 2 * hdev->mps;
1619 priv->buf_size = priv->wl.high;
1620 }
bb1fe9ea
YL		 1621 } else {
1622 priv->enable = 0;
1623 priv->wl.low = 0;
1624 priv->wl.high = 0;
1625 priv->buf_size = 0;
46a3df9f
S		 1626 }
1627 }
1628
acf61ecd 1629 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1630 return 0;
1631
1632 /* step 2, try to decrease the buffer size of
1633 * no pfc TC's private buffer
1634 */
1635 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1636 priv = &buf_alloc->priv_buf[i];
46a3df9f 1637
bb1fe9ea
YL		 1638 priv->enable = 0;
1639 priv->wl.low = 0;
1640 priv->wl.high = 0;
1641 priv->buf_size = 0;
1642
1643 if (!(hdev->hw_tc_map & BIT(i)))
1644 continue;
1645
1646 priv->enable = 1;
46a3df9f
S		 1647
1648 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1649 priv->wl.low = 128;
1650 priv->wl.high = priv->wl.low + hdev->mps;
1651 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1652 } else {
1653 priv->wl.low = 0;
1654 priv->wl.high = hdev->mps;
1655 priv->buf_size = priv->wl.high;
1656 }
1657 }
1658
acf61ecd 1659 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1660 return 0;
1661
1662 /* step 3, try to reduce the number of pfc disabled TCs,
1663 * which have private buffer
1664 */
1665 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1666 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1667
1668 /* let the last to be cleared first */
1669 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1670 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1671
1672 if (hdev->hw_tc_map & BIT(i) &&
1673 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1674 /* Clear the no pfc TC private buffer */
1675 priv->wl.low = 0;
1676 priv->wl.high = 0;
1677 priv->buf_size = 0;
1678 priv->enable = 0;
1679 no_pfc_priv_num--;
1680 }
1681
acf61ecd 1682 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1683 no_pfc_priv_num == 0)
1684 break;
1685 }
1686
acf61ecd 1687 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1688 return 0;
1689
1690 /* step 4, try to reduce the number of pfc enabled TCs
1691 * which have private buffer.
1692 */
acf61ecd 1693 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1694
1695 /* let the last to be cleared first */
1696 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1697 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1698
1699 if (hdev->hw_tc_map & BIT(i) &&
1700 hdev->tm_info.hw_pfc_map & BIT(i)) {
1701 /* Reduce the number of pfc TC with private buffer */
1702 priv->wl.low = 0;
1703 priv->enable = 0;
1704 priv->wl.high = 0;
1705 priv->buf_size = 0;
1706 pfc_priv_num--;
1707 }
1708
acf61ecd 1709 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1710 pfc_priv_num == 0)
1711 break;
1712 }
acf61ecd 1713 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1714 return 0;
1715
1716 return -ENOMEM;
1717}
1718
acf61ecd
YL		 1719static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1720 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1721{
d44f9b63 1722 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1723 struct hclge_desc desc;
1724 int ret;
1725 int i;
1726
1727 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1728 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1729
1730 /* Alloc private buffer TCs */
1731 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1732 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1733
1734 req->buf_num[i] =
1735 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1736 req->buf_num[i] |=
5bca3b94 1737 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1738 }
1739
b8c8bf47 1740 req->shared_buf =
acf61ecd 1741 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1742 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1743
46a3df9f
S		 1744 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1745 if (ret) {
1746 dev_err(&hdev->pdev->dev,
1747 "rx private buffer alloc cmd failed %d\n", ret);
1748 return ret;
1749 }
1750
1751 return 0;
1752}
1753
1754#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1755
acf61ecd
YL		 1756static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1757 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1758{
1759 struct hclge_rx_priv_wl_buf *req;
1760 struct hclge_priv_buf *priv;
1761 struct hclge_desc desc[2];
1762 int i, j;
1763 int ret;
1764
1765 for (i = 0; i < 2; i++) {
1766 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1767 false);
1768 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1769
1770 /* The first descriptor set the NEXT bit to 1 */
1771 if (i == 0)
1772 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1773 else
1774 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1775
1776 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1777 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1778
1779 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1780 req->tc_wl[j].high =
1781 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1782 req->tc_wl[j].high |=
1783 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1784 HCLGE_RX_PRIV_EN_B);
1785 req->tc_wl[j].low =
1786 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1787 req->tc_wl[j].low |=
1788 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1789 HCLGE_RX_PRIV_EN_B);
1790 }
1791 }
1792
1793 /* Send 2 descriptor at one time */
1794 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1795 if (ret) {
1796 dev_err(&hdev->pdev->dev,
1797 "rx private waterline config cmd failed %d\n",
1798 ret);
1799 return ret;
1800 }
1801 return 0;
1802}
1803
acf61ecd
YL		 1804static int hclge_common_thrd_config(struct hclge_dev *hdev,
1805 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1806{
acf61ecd 1807 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1808 struct hclge_rx_com_thrd *req;
1809 struct hclge_desc desc[2];
1810 struct hclge_tc_thrd *tc;
1811 int i, j;
1812 int ret;
1813
1814 for (i = 0; i < 2; i++) {
1815 hclge_cmd_setup_basic_desc(&desc[i],
1816 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1817 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1818
1819 /* The first descriptor set the NEXT bit to 1 */
1820 if (i == 0)
1821 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1822 else
1823 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1824
1825 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1826 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1827
1828 req->com_thrd[j].high =
1829 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1830 req->com_thrd[j].high |=
1831 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1832 HCLGE_RX_PRIV_EN_B);
1833 req->com_thrd[j].low =
1834 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1835 req->com_thrd[j].low |=
1836 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1837 HCLGE_RX_PRIV_EN_B);
1838 }
1839 }
1840
1841 /* Send 2 descriptors at one time */
1842 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1843 if (ret) {
1844 dev_err(&hdev->pdev->dev,
1845 "common threshold config cmd failed %d\n", ret);
1846 return ret;
1847 }
1848 return 0;
1849}
1850
acf61ecd
YL		 1851static int hclge_common_wl_config(struct hclge_dev *hdev,
1852 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1853{
acf61ecd 1854 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1855 struct hclge_rx_com_wl *req;
1856 struct hclge_desc desc;
1857 int ret;
1858
1859 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1860
1861 req = (struct hclge_rx_com_wl *)desc.data;
1862 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1863 req->com_wl.high |=
1864 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1865 HCLGE_RX_PRIV_EN_B);
1866
1867 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1868 req->com_wl.low |=
1869 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1870 HCLGE_RX_PRIV_EN_B);
1871
1872 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1873 if (ret) {
1874 dev_err(&hdev->pdev->dev,
1875 "common waterline config cmd failed %d\n", ret);
1876 return ret;
1877 }
1878
1879 return 0;
1880}
1881
1882int hclge_buffer_alloc(struct hclge_dev *hdev)
1883{
acf61ecd 1884 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1885 int ret;
1886
acf61ecd
YL		 1887 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1888 if (!pkt_buf)
46a3df9f
S		 1889 return -ENOMEM;
1890
acf61ecd 1891 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1892 if (ret) {
1893 dev_err(&hdev->pdev->dev,
1894 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1895 goto out;
9ffe79a9
YL		 1896 }
1897
acf61ecd 1898 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1899 if (ret) {
1900 dev_err(&hdev->pdev->dev,
1901 "could not alloc tx buffers %d\n", ret);
acf61ecd 1902 goto out;
46a3df9f
S		 1903 }
1904
acf61ecd 1905 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1906 if (ret) {
1907 dev_err(&hdev->pdev->dev,
1908 "could not calc rx priv buffer size for all TCs %d\n",
1909 ret);
acf61ecd 1910 goto out;
46a3df9f
S		 1911 }
1912
acf61ecd 1913 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1914 if (ret) {
1915 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1916 ret);
acf61ecd 1917 goto out;
46a3df9f
S		 1918 }
1919
2daf4a65 1920 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1921 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1922 if (ret) {
1923 dev_err(&hdev->pdev->dev,
1924 "could not configure rx private waterline %d\n",
1925 ret);
acf61ecd 1926 goto out;
2daf4a65 1927 }
46a3df9f 1928
acf61ecd 1929 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1930 if (ret) {
1931 dev_err(&hdev->pdev->dev,
1932 "could not configure common threshold %d\n",
1933 ret);
acf61ecd 1934 goto out;
2daf4a65 1935 }
46a3df9f
S		 1936 }
1937
acf61ecd
YL		 1938 ret = hclge_common_wl_config(hdev, pkt_buf);
1939 if (ret)
46a3df9f
S		 1940 dev_err(&hdev->pdev->dev,
1941 "could not configure common waterline %d\n", ret);
46a3df9f 1942
acf61ecd
YL		 1943out:
1944 kfree(pkt_buf);
1945 return ret;
46a3df9f
S		 1946}
1947
1948static int hclge_init_roce_base_info(struct hclge_vport *vport)
1949{
1950 struct hnae3_handle *roce = &vport->roce;
1951 struct hnae3_handle *nic = &vport->nic;
1952
1953 roce->rinfo.num_vectors = vport->back->num_roce_msix;
1954
1955 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1956 vport->back->num_msi_left == 0)
1957 return -EINVAL;
1958
1959 roce->rinfo.base_vector = vport->back->roce_base_vector;
1960
1961 roce->rinfo.netdev = nic->kinfo.netdev;
1962 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1963
1964 roce->pdev = nic->pdev;
1965 roce->ae_algo = nic->ae_algo;
1966 roce->numa_node_mask = nic->numa_node_mask;
1967
1968 return 0;
1969}
1970
1971static int hclge_init_msix(struct hclge_dev *hdev)
1972{
1973 struct pci_dev *pdev = hdev->pdev;
1974 int ret, i;
1975
1976 hdev->msix_entries = devm_kcalloc(&pdev->dev, hdev->num_msi,
1977 sizeof(struct msix_entry),
1978 GFP_KERNEL);
1979 if (!hdev->msix_entries)
1980 return -ENOMEM;
1981
1982 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1983 sizeof(u16), GFP_KERNEL);
1984 if (!hdev->vector_status)
1985 return -ENOMEM;
1986
1987 for (i = 0; i < hdev->num_msi; i++) {
1988 hdev->msix_entries[i].entry = i;
1989 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1990 }
1991
1992 hdev->num_msi_left = hdev->num_msi;
1993 hdev->base_msi_vector = hdev->pdev->irq;
1994 hdev->roce_base_vector = hdev->base_msi_vector +
1995 HCLGE_ROCE_VECTOR_OFFSET;
1996
1997 ret = pci_enable_msix_range(hdev->pdev, hdev->msix_entries,
1998 hdev->num_msi, hdev->num_msi);
1999 if (ret < 0) {
2000 dev_info(&hdev->pdev->dev,
2001 "MSI-X vector alloc failed: %d\n", ret);
2002 return ret;
2003 }
2004
2005 return 0;
2006}
2007
2008static int hclge_init_msi(struct hclge_dev *hdev)
2009{
2010 struct pci_dev *pdev = hdev->pdev;
2011 int vectors;
2012 int i;
2013
2014 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2015 sizeof(u16), GFP_KERNEL);
2016 if (!hdev->vector_status)
2017 return -ENOMEM;
2018
2019 for (i = 0; i < hdev->num_msi; i++)
2020 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2021
2022 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, PCI_IRQ_MSI);
2023 if (vectors < 0) {
2024 dev_err(&pdev->dev, "MSI vectors enable failed %d\n", vectors);
2025 return -EINVAL;
2026 }
2027 hdev->num_msi = vectors;
2028 hdev->num_msi_left = vectors;
2029 hdev->base_msi_vector = pdev->irq;
2030 hdev->roce_base_vector = hdev->base_msi_vector +
2031 HCLGE_ROCE_VECTOR_OFFSET;
2032
2033 return 0;
2034}
2035
2036static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2037{
2038 struct hclge_mac *mac = &hdev->hw.mac;
2039
2040 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2041 mac->duplex = (u8)duplex;
2042 else
2043 mac->duplex = HCLGE_MAC_FULL;
2044
2045 mac->speed = speed;
2046}
2047
2048int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2049{
d44f9b63 2050 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2051 struct hclge_desc desc;
2052 int ret;
2053
d44f9b63 2054 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2055
2056 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2057
2058 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2059
2060 switch (speed) {
2061 case HCLGE_MAC_SPEED_10M:
2062 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2063 HCLGE_CFG_SPEED_S, 6);
2064 break;
2065 case HCLGE_MAC_SPEED_100M:
2066 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2067 HCLGE_CFG_SPEED_S, 7);
2068 break;
2069 case HCLGE_MAC_SPEED_1G:
2070 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2071 HCLGE_CFG_SPEED_S, 0);
2072 break;
2073 case HCLGE_MAC_SPEED_10G:
2074 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2075 HCLGE_CFG_SPEED_S, 1);
2076 break;
2077 case HCLGE_MAC_SPEED_25G:
2078 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2079 HCLGE_CFG_SPEED_S, 2);
2080 break;
2081 case HCLGE_MAC_SPEED_40G:
2082 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2083 HCLGE_CFG_SPEED_S, 3);
2084 break;
2085 case HCLGE_MAC_SPEED_50G:
2086 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2087 HCLGE_CFG_SPEED_S, 4);
2088 break;
2089 case HCLGE_MAC_SPEED_100G:
2090 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2091 HCLGE_CFG_SPEED_S, 5);
2092 break;
2093 default:
d7629e74 2094 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2095 return -EINVAL;
2096 }
2097
2098 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2099 1);
2100
2101 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2102 if (ret) {
2103 dev_err(&hdev->pdev->dev,
2104 "mac speed/duplex config cmd failed %d.\n", ret);
2105 return ret;
2106 }
2107
2108 hclge_check_speed_dup(hdev, duplex, speed);
2109
2110 return 0;
2111}
2112
2113static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2114 u8 duplex)
2115{
2116 struct hclge_vport *vport = hclge_get_vport(handle);
2117 struct hclge_dev *hdev = vport->back;
2118
2119 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2120}
2121
2122static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2123 u8 *duplex)
2124{
d44f9b63 2125 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2126 struct hclge_desc desc;
2127 int speed_tmp;
2128 int ret;
2129
d44f9b63 2130 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2131
2132 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2133 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2134 if (ret) {
2135 dev_err(&hdev->pdev->dev,
2136 "mac speed/autoneg/duplex query cmd failed %d\n",
2137 ret);
2138 return ret;
2139 }
2140
2141 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2142 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2143 HCLGE_QUERY_SPEED_S);
2144
2145 ret = hclge_parse_speed(speed_tmp, speed);
2146 if (ret) {
2147 dev_err(&hdev->pdev->dev,
2148 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2149 return -EIO;
2150 }
2151
2152 return 0;
2153}
2154
2155static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2156{
2157 struct hclge_mac *mac = &hdev->hw.mac;
d44f9b63 2158 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2159 struct hclge_desc desc;
2160 int ret;
2161
d44f9b63 2162 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2163
2164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2165 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2166 if (ret) {
2167 dev_err(&hdev->pdev->dev,
2168 "autoneg result query cmd failed %d.\n", ret);
2169 return ret;
2170 }
2171
2172 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2173
2174 return 0;
2175}
2176
2177static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2178{
d44f9b63 2179 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2180 struct hclge_desc desc;
a90bb9a5 2181 u32 flag = 0;
46a3df9f
S		 2182 int ret;
2183
2184 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2185
d44f9b63 2186 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2187 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2188 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2189
2190 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2191 if (ret) {
2192 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2193 ret);
2194 return ret;
2195 }
2196
2197 return 0;
2198}
2199
2200static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2201{
2202 struct hclge_vport *vport = hclge_get_vport(handle);
2203 struct hclge_dev *hdev = vport->back;
2204
2205 return hclge_set_autoneg_en(hdev, enable);
2206}
2207
2208static int hclge_get_autoneg(struct hnae3_handle *handle)
2209{
2210 struct hclge_vport *vport = hclge_get_vport(handle);
2211 struct hclge_dev *hdev = vport->back;
2212
2213 hclge_query_autoneg_result(hdev);
2214
2215 return hdev->hw.mac.autoneg;
2216}
2217
2218static int hclge_mac_init(struct hclge_dev *hdev)
2219{
2220 struct hclge_mac *mac = &hdev->hw.mac;
2221 int ret;
2222
2223 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2224 if (ret) {
2225 dev_err(&hdev->pdev->dev,
2226 "Config mac speed dup fail ret=%d\n", ret);
2227 return ret;
2228 }
2229
2230 mac->link = 0;
2231
46a3df9f
S		 2232 /* Initialize the MTA table work mode */
2233 hdev->accept_mta_mc = true;
2234 hdev->enable_mta = true;
2235 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2236
2237 ret = hclge_set_mta_filter_mode(hdev,
2238 hdev->mta_mac_sel_type,
2239 hdev->enable_mta);
2240 if (ret) {
2241 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2242 ret);
2243 return ret;
2244 }
2245
2246 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2247}
2248
2249static void hclge_task_schedule(struct hclge_dev *hdev)
2250{
2251 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2252 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2253 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2254 (void)schedule_work(&hdev->service_task);
2255}
2256
2257static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2258{
d44f9b63 2259 struct hclge_link_status_cmd *req;
46a3df9f
S		 2260 struct hclge_desc desc;
2261 int link_status;
2262 int ret;
2263
2264 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2265 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2266 if (ret) {
2267 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2268 ret);
2269 return ret;
2270 }
2271
d44f9b63 2272 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2273 link_status = req->status & HCLGE_LINK_STATUS;
2274
2275 return !!link_status;
2276}
2277
2278static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2279{
2280 int mac_state;
2281 int link_stat;
2282
2283 mac_state = hclge_get_mac_link_status(hdev);
2284
2285 if (hdev->hw.mac.phydev) {
2286 if (!genphy_read_status(hdev->hw.mac.phydev))
2287 link_stat = mac_state &
2288 hdev->hw.mac.phydev->link;
2289 else
2290 link_stat = 0;
2291
2292 } else {
2293 link_stat = mac_state;
2294 }
2295
2296 return !!link_stat;
2297}
2298
2299static void hclge_update_link_status(struct hclge_dev *hdev)
2300{
2301 struct hnae3_client *client = hdev->nic_client;
2302 struct hnae3_handle *handle;
2303 int state;
2304 int i;
2305
2306 if (!client)
2307 return;
2308 state = hclge_get_mac_phy_link(hdev);
2309 if (state != hdev->hw.mac.link) {
2310 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2311 handle = &hdev->vport[i].nic;
2312 client->ops->link_status_change(handle, state);
2313 }
2314 hdev->hw.mac.link = state;
2315 }
2316}
2317
2318static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2319{
2320 struct hclge_mac mac = hdev->hw.mac;
2321 u8 duplex;
2322 int speed;
2323 int ret;
2324
2325 /* get the speed and duplex as autoneg'result from mac cmd when phy
2326 * doesn't exit.
2327 */
2328 if (mac.phydev)
2329 return 0;
2330
2331 /* update mac->antoneg. */
2332 ret = hclge_query_autoneg_result(hdev);
2333 if (ret) {
2334 dev_err(&hdev->pdev->dev,
2335 "autoneg result query failed %d\n", ret);
2336 return ret;
2337 }
2338
2339 if (!mac.autoneg)
2340 return 0;
2341
2342 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2343 if (ret) {
2344 dev_err(&hdev->pdev->dev,
2345 "mac autoneg/speed/duplex query failed %d\n", ret);
2346 return ret;
2347 }
2348
2349 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2350 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2351 if (ret) {
2352 dev_err(&hdev->pdev->dev,
2353 "mac speed/duplex config failed %d\n", ret);
2354 return ret;
2355 }
2356 }
2357
2358 return 0;
2359}
2360
2361static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2362{
2363 struct hclge_vport *vport = hclge_get_vport(handle);
2364 struct hclge_dev *hdev = vport->back;
2365
2366 return hclge_update_speed_duplex(hdev);
2367}
2368
2369static int hclge_get_status(struct hnae3_handle *handle)
2370{
2371 struct hclge_vport *vport = hclge_get_vport(handle);
2372 struct hclge_dev *hdev = vport->back;
2373
2374 hclge_update_link_status(hdev);
2375
2376 return hdev->hw.mac.link;
2377}
2378
d039ef68 2379static void hclge_service_timer(struct timer_list *t)
46a3df9f 2380{
d039ef68 2381 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2382
d039ef68 2383 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 2384 hclge_task_schedule(hdev);
2385}
2386
2387static void hclge_service_complete(struct hclge_dev *hdev)
2388{
2389 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2390
2391 /* Flush memory before next watchdog */
2392 smp_mb__before_atomic();
2393 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2394}
2395
466b0c00
L		 2396static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2397{
2398 writel(enable ? 1 : 0, vector->addr);
2399}
2400
2401static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2402{
2403 struct hclge_dev *hdev = data;
2404
2405 hclge_enable_vector(&hdev->misc_vector, false);
2406 if (!test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2407 schedule_work(&hdev->service_task);
2408
2409 return IRQ_HANDLED;
2410}
2411
2412static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2413{
2414 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2415 hdev->num_msi_left += 1;
2416 hdev->num_msi_used -= 1;
2417}
2418
2419static void hclge_get_misc_vector(struct hclge_dev *hdev)
2420{
2421 struct hclge_misc_vector *vector = &hdev->misc_vector;
2422
2423 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2424
2425 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2426 hdev->vector_status[0] = 0;
2427
2428 hdev->num_msi_left -= 1;
2429 hdev->num_msi_used += 1;
2430}
2431
2432static int hclge_misc_irq_init(struct hclge_dev *hdev)
2433{
2434 int ret;
2435
2436 hclge_get_misc_vector(hdev);
2437
2438 ret = devm_request_irq(&hdev->pdev->dev,
2439 hdev->misc_vector.vector_irq,
2440 hclge_misc_irq_handle, 0, "hclge_misc", hdev);
2441 if (ret) {
2442 hclge_free_vector(hdev, 0);
2443 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2444 hdev->misc_vector.vector_irq);
2445 }
2446
2447 return ret;
2448}
2449
4ed340ab
L		 2450static int hclge_notify_client(struct hclge_dev *hdev,
2451 enum hnae3_reset_notify_type type)
2452{
2453 struct hnae3_client *client = hdev->nic_client;
2454 u16 i;
2455
2456 if (!client->ops->reset_notify)
2457 return -EOPNOTSUPP;
2458
2459 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2460 struct hnae3_handle *handle = &hdev->vport[i].nic;
2461 int ret;
2462
2463 ret = client->ops->reset_notify(handle, type);
2464 if (ret)
2465 return ret;
2466 }
2467
2468 return 0;
2469}
2470
2471static int hclge_reset_wait(struct hclge_dev *hdev)
2472{
2473#define HCLGE_RESET_WATI_MS 100
2474#define HCLGE_RESET_WAIT_CNT 5
2475 u32 val, reg, reg_bit;
2476 u32 cnt = 0;
2477
2478 switch (hdev->reset_type) {
2479 case HNAE3_GLOBAL_RESET:
2480 reg = HCLGE_GLOBAL_RESET_REG;
2481 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2482 break;
2483 case HNAE3_CORE_RESET:
2484 reg = HCLGE_GLOBAL_RESET_REG;
2485 reg_bit = HCLGE_CORE_RESET_BIT;
2486 break;
2487 case HNAE3_FUNC_RESET:
2488 reg = HCLGE_FUN_RST_ING;
2489 reg_bit = HCLGE_FUN_RST_ING_B;
2490 break;
2491 default:
2492 dev_err(&hdev->pdev->dev,
2493 "Wait for unsupported reset type: %d\n",
2494 hdev->reset_type);
2495 return -EINVAL;
2496 }
2497
2498 val = hclge_read_dev(&hdev->hw, reg);
2499 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2500 msleep(HCLGE_RESET_WATI_MS);
2501 val = hclge_read_dev(&hdev->hw, reg);
2502 cnt++;
2503 }
2504
2505 /* must clear reset status register to
2506 * prevent driver detect reset interrupt again
2507 */
2508 reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2509 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, reg);
2510
2511 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2512 dev_warn(&hdev->pdev->dev,
2513 "Wait for reset timeout: %d\n", hdev->reset_type);
2514 return -EBUSY;
2515 }
2516
2517 return 0;
2518}
2519
2520static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2521{
2522 struct hclge_desc desc;
2523 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2524 int ret;
2525
2526 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2527 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2528 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2529 req->fun_reset_vfid = func_id;
2530
2531 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2532 if (ret)
2533 dev_err(&hdev->pdev->dev,
2534 "send function reset cmd fail, status =%d\n", ret);
2535
2536 return ret;
2537}
2538
2539static void hclge_do_reset(struct hclge_dev *hdev, enum hnae3_reset_type type)
2540{
2541 struct pci_dev *pdev = hdev->pdev;
2542 u32 val;
2543
2544 switch (type) {
2545 case HNAE3_GLOBAL_RESET:
2546 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2547 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2548 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2549 dev_info(&pdev->dev, "Global Reset requested\n");
2550 break;
2551 case HNAE3_CORE_RESET:
2552 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2553 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2554 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2555 dev_info(&pdev->dev, "Core Reset requested\n");
2556 break;
2557 case HNAE3_FUNC_RESET:
2558 dev_info(&pdev->dev, "PF Reset requested\n");
2559 hclge_func_reset_cmd(hdev, 0);
2560 break;
2561 default:
2562 dev_warn(&pdev->dev,
2563 "Unsupported reset type: %d\n", type);
2564 break;
2565 }
2566}
2567
2568static enum hnae3_reset_type hclge_detected_reset_event(struct hclge_dev *hdev)
2569{
2570 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2571 u32 rst_reg_val;
2572
2573 rst_reg_val = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2574 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_reg_val)
2575 rst_level = HNAE3_GLOBAL_RESET;
2576 else if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_reg_val)
2577 rst_level = HNAE3_CORE_RESET;
2578 else if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_reg_val)
2579 rst_level = HNAE3_IMP_RESET;
2580
2581 return rst_level;
2582}
2583
2584static void hclge_reset_event(struct hnae3_handle *handle,
2585 enum hnae3_reset_type reset)
2586{
2587 struct hclge_vport *vport = hclge_get_vport(handle);
2588 struct hclge_dev *hdev = vport->back;
2589
2590 dev_info(&hdev->pdev->dev,
2591 "Receive reset event , reset_type is %d", reset);
2592
2593 switch (reset) {
2594 case HNAE3_FUNC_RESET:
2595 case HNAE3_CORE_RESET:
2596 case HNAE3_GLOBAL_RESET:
2597 if (test_bit(HCLGE_STATE_RESET_INT, &hdev->state)) {
2598 dev_err(&hdev->pdev->dev, "Already in reset state");
2599 return;
2600 }
2601 hdev->reset_type = reset;
2602 set_bit(HCLGE_STATE_RESET_INT, &hdev->state);
2603 set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2604 schedule_work(&hdev->service_task);
2605 break;
2606 default:
2607 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2608 break;
2609 }
2610}
2611
2612static void hclge_reset_subtask(struct hclge_dev *hdev)
2613{
2614 bool do_reset;
2615
2616 do_reset = hdev->reset_type != HNAE3_NONE_RESET;
2617
2618 /* Reset is detected by interrupt */
2619 if (hdev->reset_type == HNAE3_NONE_RESET)
2620 hdev->reset_type = hclge_detected_reset_event(hdev);
2621
2622 if (hdev->reset_type == HNAE3_NONE_RESET)
2623 return;
2624
2625 switch (hdev->reset_type) {
2626 case HNAE3_FUNC_RESET:
2627 case HNAE3_CORE_RESET:
2628 case HNAE3_GLOBAL_RESET:
2629 case HNAE3_IMP_RESET:
2630 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2631
2632 if (do_reset)
2633 hclge_do_reset(hdev, hdev->reset_type);
2634 else
2635 set_bit(HCLGE_STATE_RESET_INT, &hdev->state);
2636
2637 if (!hclge_reset_wait(hdev)) {
2638 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2639 hclge_reset_ae_dev(hdev->ae_dev);
2640 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2641 clear_bit(HCLGE_STATE_RESET_INT, &hdev->state);
2642 }
2643 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2644 break;
2645 default:
2646 dev_err(&hdev->pdev->dev, "Unsupported reset type:%d\n",
2647 hdev->reset_type);
2648 break;
2649 }
2650 hdev->reset_type = HNAE3_NONE_RESET;
2651}
2652
466b0c00
L		 2653static void hclge_misc_irq_service_task(struct hclge_dev *hdev)
2654{
4ed340ab 2655 hclge_reset_subtask(hdev);
466b0c00
L		 2656 hclge_enable_vector(&hdev->misc_vector, true);
2657}
2658
46a3df9f
S		 2659static void hclge_service_task(struct work_struct *work)
2660{
2661 struct hclge_dev *hdev =
2662 container_of(work, struct hclge_dev, service_task);
2663
466b0c00 2664 hclge_misc_irq_service_task(hdev);
46a3df9f
S		 2665 hclge_update_speed_duplex(hdev);
2666 hclge_update_link_status(hdev);
2667 hclge_update_stats_for_all(hdev);
2668 hclge_service_complete(hdev);
2669}
2670
2671static void hclge_disable_sriov(struct hclge_dev *hdev)
2672{
2a32ca13
AB		 2673 /* If our VFs are assigned we cannot shut down SR-IOV
2674 * without causing issues, so just leave the hardware
2675 * available but disabled
2676 */
2677 if (pci_vfs_assigned(hdev->pdev)) {
2678 dev_warn(&hdev->pdev->dev,
2679 "disabling driver while VFs are assigned\n");
2680 return;
2681 }
46a3df9f 2682
2a32ca13 2683 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2684}
2685
2686struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2687{
2688 /* VF handle has no client */
2689 if (!handle->client)
2690 return container_of(handle, struct hclge_vport, nic);
2691 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2692 return container_of(handle, struct hclge_vport, roce);
2693 else
2694 return container_of(handle, struct hclge_vport, nic);
2695}
2696
2697static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2698 struct hnae3_vector_info *vector_info)
2699{
2700 struct hclge_vport *vport = hclge_get_vport(handle);
2701 struct hnae3_vector_info *vector = vector_info;
2702 struct hclge_dev *hdev = vport->back;
2703 int alloc = 0;
2704 int i, j;
2705
2706 vector_num = min(hdev->num_msi_left, vector_num);
2707
2708 for (j = 0; j < vector_num; j++) {
2709 for (i = 1; i < hdev->num_msi; i++) {
2710 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2711 vector->vector = pci_irq_vector(hdev->pdev, i);
2712 vector->io_addr = hdev->hw.io_base +
2713 HCLGE_VECTOR_REG_BASE +
2714 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2715 vport->vport_id *
2716 HCLGE_VECTOR_VF_OFFSET;
2717 hdev->vector_status[i] = vport->vport_id;
2718
2719 vector++;
2720 alloc++;
2721
2722 break;
2723 }
2724 }
2725 }
2726 hdev->num_msi_left -= alloc;
2727 hdev->num_msi_used += alloc;
2728
2729 return alloc;
2730}
2731
2732static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2733{
2734 int i;
2735
2736 for (i = 0; i < hdev->num_msi; i++) {
2737 if (hdev->msix_entries) {
2738 if (vector == hdev->msix_entries[i].vector)
2739 return i;
2740 } else {
2741 if (vector == (hdev->base_msi_vector + i))
2742 return i;
2743 }
2744 }
2745 return -EINVAL;
2746}
2747
2748static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2749{
2750 return HCLGE_RSS_KEY_SIZE;
2751}
2752
2753static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2754{
2755 return HCLGE_RSS_IND_TBL_SIZE;
2756}
2757
2758static int hclge_get_rss_algo(struct hclge_dev *hdev)
2759{
d44f9b63 2760 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2761 struct hclge_desc desc;
2762 int rss_hash_algo;
2763 int ret;
2764
2765 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2766
2767 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2768 if (ret) {
2769 dev_err(&hdev->pdev->dev,
2770 "Get link status error, status =%d\n", ret);
2771 return ret;
2772 }
2773
d44f9b63 2774 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2775 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2776
2777 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2778 return ETH_RSS_HASH_TOP;
2779
2780 return -EINVAL;
2781}
2782
2783static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2784 const u8 hfunc, const u8 *key)
2785{
d44f9b63 2786 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2787 struct hclge_desc desc;
2788 int key_offset;
2789 int key_size;
2790 int ret;
2791
d44f9b63 2792 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2793
2794 for (key_offset = 0; key_offset < 3; key_offset++) {
2795 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2796 false);
2797
2798 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2799 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2800
2801 if (key_offset == 2)
2802 key_size =
2803 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2804 else
2805 key_size = HCLGE_RSS_HASH_KEY_NUM;
2806
2807 memcpy(req->hash_key,
2808 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2809
2810 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2811 if (ret) {
2812 dev_err(&hdev->pdev->dev,
2813 "Configure RSS config fail, status = %d\n",
2814 ret);
2815 return ret;
2816 }
2817 }
2818 return 0;
2819}
2820
2821static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2822{
d44f9b63 2823 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2824 struct hclge_desc desc;
2825 int i, j;
2826 int ret;
2827
d44f9b63 2828 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2829
2830 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2831 hclge_cmd_setup_basic_desc
2832 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2833
a90bb9a5
YL		 2834 req->start_table_index =
2835 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2836 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2837
2838 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2839 req->rss_result[j] =
2840 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2841
2842 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2843 if (ret) {
2844 dev_err(&hdev->pdev->dev,
2845 "Configure rss indir table fail,status = %d\n",
2846 ret);
2847 return ret;
2848 }
2849 }
2850 return 0;
2851}
2852
2853static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2854 u16 *tc_size, u16 *tc_offset)
2855{
d44f9b63 2856 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2857 struct hclge_desc desc;
2858 int ret;
2859 int i;
2860
2861 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2862 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2863
2864 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2865 u16 mode = 0;
2866
2867 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2868 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 2869 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 2870 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 2871 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2872
2873 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2874 }
2875
2876 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2877 if (ret) {
2878 dev_err(&hdev->pdev->dev,
2879 "Configure rss tc mode fail, status = %d\n", ret);
2880 return ret;
2881 }
2882
2883 return 0;
2884}
2885
2886static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2887{
d44f9b63 2888 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2889 struct hclge_desc desc;
2890 int ret;
2891
2892 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2893
d44f9b63 2894 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
46a3df9f
S		 2895 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2896 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2897 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2898 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2899 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2900 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2901 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2902 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2903 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2904 if (ret) {
2905 dev_err(&hdev->pdev->dev,
2906 "Configure rss input fail, status = %d\n", ret);
2907 return ret;
2908 }
2909
2910 return 0;
2911}
2912
2913static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2914 u8 *key, u8 *hfunc)
2915{
2916 struct hclge_vport *vport = hclge_get_vport(handle);
2917 struct hclge_dev *hdev = vport->back;
2918 int i;
2919
2920 /* Get hash algorithm */
2921 if (hfunc)
2922 *hfunc = hclge_get_rss_algo(hdev);
2923
2924 /* Get the RSS Key required by the user */
2925 if (key)
2926 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2927
2928 /* Get indirect table */
2929 if (indir)
2930 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2931 indir[i] = vport->rss_indirection_tbl[i];
2932
2933 return 0;
2934}
2935
2936static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2937 const u8 *key, const u8 hfunc)
2938{
2939 struct hclge_vport *vport = hclge_get_vport(handle);
2940 struct hclge_dev *hdev = vport->back;
2941 u8 hash_algo;
2942 int ret, i;
2943
2944 /* Set the RSS Hash Key if specififed by the user */
2945 if (key) {
2946 /* Update the shadow RSS key with user specified qids */
2947 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2948
2949 if (hfunc == ETH_RSS_HASH_TOP ||
2950 hfunc == ETH_RSS_HASH_NO_CHANGE)
2951 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2952 else
2953 return -EINVAL;
2954 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2955 if (ret)
2956 return ret;
2957 }
2958
2959 /* Update the shadow RSS table with user specified qids */
2960 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2961 vport->rss_indirection_tbl[i] = indir[i];
2962
2963 /* Update the hardware */
2964 ret = hclge_set_rss_indir_table(hdev, indir);
2965 return ret;
2966}
2967
f7db940a
L		 2968static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2969{
2970 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2971
2972 if (nfc->data & RXH_L4_B_2_3)
2973 hash_sets |= HCLGE_D_PORT_BIT;
2974 else
2975 hash_sets &= ~HCLGE_D_PORT_BIT;
2976
2977 if (nfc->data & RXH_IP_SRC)
2978 hash_sets |= HCLGE_S_IP_BIT;
2979 else
2980 hash_sets &= ~HCLGE_S_IP_BIT;
2981
2982 if (nfc->data & RXH_IP_DST)
2983 hash_sets |= HCLGE_D_IP_BIT;
2984 else
2985 hash_sets &= ~HCLGE_D_IP_BIT;
2986
2987 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
2988 hash_sets |= HCLGE_V_TAG_BIT;
2989
2990 return hash_sets;
2991}
2992
2993static int hclge_set_rss_tuple(struct hnae3_handle *handle,
2994 struct ethtool_rxnfc *nfc)
2995{
2996 struct hclge_vport *vport = hclge_get_vport(handle);
2997 struct hclge_dev *hdev = vport->back;
2998 struct hclge_rss_input_tuple_cmd *req;
2999 struct hclge_desc desc;
3000 u8 tuple_sets;
3001 int ret;
3002
3003 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3004 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3005 return -EINVAL;
3006
3007 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3008 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3009 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3010 if (ret) {
3011 dev_err(&hdev->pdev->dev,
3012 "Read rss tuple fail, status = %d\n", ret);
3013 return ret;
3014 }
3015
3016 hclge_cmd_reuse_desc(&desc, false);
3017
3018 tuple_sets = hclge_get_rss_hash_bits(nfc);
3019 switch (nfc->flow_type) {
3020 case TCP_V4_FLOW:
3021 req->ipv4_tcp_en = tuple_sets;
3022 break;
3023 case TCP_V6_FLOW:
3024 req->ipv6_tcp_en = tuple_sets;
3025 break;
3026 case UDP_V4_FLOW:
3027 req->ipv4_udp_en = tuple_sets;
3028 break;
3029 case UDP_V6_FLOW:
3030 req->ipv6_udp_en = tuple_sets;
3031 break;
3032 case SCTP_V4_FLOW:
3033 req->ipv4_sctp_en = tuple_sets;
3034 break;
3035 case SCTP_V6_FLOW:
3036 if ((nfc->data & RXH_L4_B_0_1) ||
3037 (nfc->data & RXH_L4_B_2_3))
3038 return -EINVAL;
3039
3040 req->ipv6_sctp_en = tuple_sets;
3041 break;
3042 case IPV4_FLOW:
3043 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3044 break;
3045 case IPV6_FLOW:
3046 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3047 break;
3048 default:
3049 return -EINVAL;
3050 }
3051
3052 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3053 if (ret)
3054 dev_err(&hdev->pdev->dev,
3055 "Set rss tuple fail, status = %d\n", ret);
3056
3057 return ret;
3058}
3059
07d29954
L		 3060static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3061 struct ethtool_rxnfc *nfc)
3062{
3063 struct hclge_vport *vport = hclge_get_vport(handle);
3064 struct hclge_dev *hdev = vport->back;
3065 struct hclge_rss_input_tuple_cmd *req;
3066 struct hclge_desc desc;
3067 u8 tuple_sets;
3068 int ret;
3069
3070 nfc->data = 0;
3071
3072 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3073 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3074 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3075 if (ret) {
3076 dev_err(&hdev->pdev->dev,
3077 "Read rss tuple fail, status = %d\n", ret);
3078 return ret;
3079 }
3080
3081 switch (nfc->flow_type) {
3082 case TCP_V4_FLOW:
3083 tuple_sets = req->ipv4_tcp_en;
3084 break;
3085 case UDP_V4_FLOW:
3086 tuple_sets = req->ipv4_udp_en;
3087 break;
3088 case TCP_V6_FLOW:
3089 tuple_sets = req->ipv6_tcp_en;
3090 break;
3091 case UDP_V6_FLOW:
3092 tuple_sets = req->ipv6_udp_en;
3093 break;
3094 case SCTP_V4_FLOW:
3095 tuple_sets = req->ipv4_sctp_en;
3096 break;
3097 case SCTP_V6_FLOW:
3098 tuple_sets = req->ipv6_sctp_en;
3099 break;
3100 case IPV4_FLOW:
3101 case IPV6_FLOW:
3102 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3103 break;
3104 default:
3105 return -EINVAL;
3106 }
3107
3108 if (!tuple_sets)
3109 return 0;
3110
3111 if (tuple_sets & HCLGE_D_PORT_BIT)
3112 nfc->data |= RXH_L4_B_2_3;
3113 if (tuple_sets & HCLGE_S_PORT_BIT)
3114 nfc->data |= RXH_L4_B_0_1;
3115 if (tuple_sets & HCLGE_D_IP_BIT)
3116 nfc->data |= RXH_IP_DST;
3117 if (tuple_sets & HCLGE_S_IP_BIT)
3118 nfc->data |= RXH_IP_SRC;
3119
3120 return 0;
3121}
3122
46a3df9f
S		 3123static int hclge_get_tc_size(struct hnae3_handle *handle)
3124{
3125 struct hclge_vport *vport = hclge_get_vport(handle);
3126 struct hclge_dev *hdev = vport->back;
3127
3128 return hdev->rss_size_max;
3129}
3130
77f255c1 3131int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f
S		 3132{
3133 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3134 struct hclge_vport *vport = hdev->vport;
3135 u16 tc_offset[HCLGE_MAX_TC_NUM];
3136 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3137 u16 tc_valid[HCLGE_MAX_TC_NUM];
3138 u16 tc_size[HCLGE_MAX_TC_NUM];
3139 u32 *rss_indir = NULL;
68ece54e 3140 u16 rss_size = 0, roundup_size;
46a3df9f
S		 3141 const u8 *key;
3142 int i, ret, j;
3143
3144 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3145 if (!rss_indir)
3146 return -ENOMEM;
3147
3148 /* Get default RSS key */
3149 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3150
3151 /* Initialize RSS indirect table for each vport */
3152 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3153 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3154 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 3155 i % vport[j].alloc_rss_size;
3156
3157 /* vport 0 is for PF */
3158 if (j != 0)
3159 continue;
3160
3161 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 3162 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3163 }
3164 }
3165 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3166 if (ret)
3167 goto err;
3168
3169 key = rss_key;
3170 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3171 if (ret)
3172 goto err;
3173
3174 ret = hclge_set_rss_input_tuple(hdev);
3175 if (ret)
3176 goto err;
3177
68ece54e
YL		 3178 /* Each TC have the same queue size, and tc_size set to hardware is
3179 * the log2 of roundup power of two of rss_size, the acutal queue
3180 * size is limited by indirection table.
3181 */
3182 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3183 dev_err(&hdev->pdev->dev,
3184 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3185 rss_size);
81359617
CJ		 3186 ret = -EINVAL;
3187 goto err;
68ece54e
YL		 3188 }
3189
3190 roundup_size = roundup_pow_of_two(rss_size);
3191 roundup_size = ilog2(roundup_size);
3192
46a3df9f 3193 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3194 tc_valid[i] = 0;
46a3df9f 3195
68ece54e
YL		 3196 if (!(hdev->hw_tc_map & BIT(i)))
3197 continue;
3198
3199 tc_valid[i] = 1;
3200 tc_size[i] = roundup_size;
3201 tc_offset[i] = rss_size * i;
46a3df9f 3202 }
68ece54e 3203
46a3df9f
S		 3204 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3205
3206err:
3207 kfree(rss_indir);
3208
3209 return ret;
3210}
3211
3212int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
3213 struct hnae3_ring_chain_node *ring_chain)
3214{
3215 struct hclge_dev *hdev = vport->back;
d44f9b63 3216 struct hclge_ctrl_vector_chain_cmd *req;
46a3df9f
S		 3217 struct hnae3_ring_chain_node *node;
3218 struct hclge_desc desc;
3219 int ret;
3220 int i;
3221
3222 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
3223
d44f9b63 3224 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
46a3df9f
S		 3225 req->int_vector_id = vector_id;
3226
3227 i = 0;
3228 for (node = ring_chain; node; node = node->next) {
a90bb9a5
YL		 3229 u16 type_and_id = 0;
3230
3231 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
46a3df9f 3232 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5
YL		 3233 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3234 node->tqp_index);
3235 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
0305b443
L		 3236 HCLGE_INT_GL_IDX_S,
3237 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5 3238 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
0305b443 3239 req->vfid = vport->vport_id;
46a3df9f
S		 3240
3241 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3242 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3243
3244 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3245 if (ret) {
3246 dev_err(&hdev->pdev->dev,
3247 "Map TQP fail, status is %d.\n",
3248 ret);
3249 return ret;
3250 }
3251 i = 0;
3252
3253 hclge_cmd_setup_basic_desc(&desc,
3254 HCLGE_OPC_ADD_RING_TO_VECTOR,
3255 false);
3256 req->int_vector_id = vector_id;
3257 }
3258 }
3259
3260 if (i > 0) {
3261 req->int_cause_num = i;
3262
3263 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3264 if (ret) {
3265 dev_err(&hdev->pdev->dev,
3266 "Map TQP fail, status is %d.\n", ret);
3267 return ret;
3268 }
3269 }
3270
3271 return 0;
3272}
3273
1db9b1bf
YL		 3274static int hclge_map_handle_ring_to_vector(
3275 struct hnae3_handle *handle, int vector,
3276 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3277{
3278 struct hclge_vport *vport = hclge_get_vport(handle);
3279 struct hclge_dev *hdev = vport->back;
3280 int vector_id;
3281
3282 vector_id = hclge_get_vector_index(hdev, vector);
3283 if (vector_id < 0) {
3284 dev_err(&hdev->pdev->dev,
3285 "Get vector index fail. ret =%d\n", vector_id);
3286 return vector_id;
3287 }
3288
3289 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
3290}
3291
3292static int hclge_unmap_ring_from_vector(
3293 struct hnae3_handle *handle, int vector,
3294 struct hnae3_ring_chain_node *ring_chain)
3295{
3296 struct hclge_vport *vport = hclge_get_vport(handle);
3297 struct hclge_dev *hdev = vport->back;
d44f9b63 3298 struct hclge_ctrl_vector_chain_cmd *req;
46a3df9f
S		 3299 struct hnae3_ring_chain_node *node;
3300 struct hclge_desc desc;
3301 int i, vector_id;
3302 int ret;
3303
3304 vector_id = hclge_get_vector_index(hdev, vector);
3305 if (vector_id < 0) {
3306 dev_err(&handle->pdev->dev,
3307 "Get vector index fail. ret =%d\n", vector_id);
3308 return vector_id;
3309 }
3310
3311 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
3312
d44f9b63 3313 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
46a3df9f
S		 3314 req->int_vector_id = vector_id;
3315
3316 i = 0;
3317 for (node = ring_chain; node; node = node->next) {
a90bb9a5
YL		 3318 u16 type_and_id = 0;
3319
3320 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
46a3df9f 3321 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5
YL		 3322 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3323 node->tqp_index);
3324 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
0305b443
L		 3325 HCLGE_INT_GL_IDX_S,
3326 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f 3327
a90bb9a5 3328 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
0305b443 3329 req->vfid = vport->vport_id;
46a3df9f
S		 3330
3331 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3332 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3333
3334 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3335 if (ret) {
3336 dev_err(&hdev->pdev->dev,
3337 "Unmap TQP fail, status is %d.\n",
3338 ret);
3339 return ret;
3340 }
3341 i = 0;
3342 hclge_cmd_setup_basic_desc(&desc,
c5b1b975 3343 HCLGE_OPC_DEL_RING_TO_VECTOR,
46a3df9f
S		 3344 false);
3345 req->int_vector_id = vector_id;
3346 }
3347 }
3348
3349 if (i > 0) {
3350 req->int_cause_num = i;
3351
3352 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3353 if (ret) {
3354 dev_err(&hdev->pdev->dev,
3355 "Unmap TQP fail, status is %d.\n", ret);
3356 return ret;
3357 }
3358 }
3359
3360 return 0;
3361}
3362
3363int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3364 struct hclge_promisc_param *param)
3365{
d44f9b63 3366 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3367 struct hclge_desc desc;
3368 int ret;
3369
3370 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3371
d44f9b63 3372 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f
S		 3373 req->vf_id = param->vf_id;
3374 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3375
3376 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3377 if (ret) {
3378 dev_err(&hdev->pdev->dev,
3379 "Set promisc mode fail, status is %d.\n", ret);
3380 return ret;
3381 }
3382 return 0;
3383}
3384
3385void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3386 bool en_mc, bool en_bc, int vport_id)
3387{
3388 if (!param)
3389 return;
3390
3391 memset(param, 0, sizeof(struct hclge_promisc_param));
3392 if (en_uc)
3393 param->enable = HCLGE_PROMISC_EN_UC;
3394 if (en_mc)
3395 param->enable |= HCLGE_PROMISC_EN_MC;
3396 if (en_bc)
3397 param->enable |= HCLGE_PROMISC_EN_BC;
3398 param->vf_id = vport_id;
3399}
3400
3401static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3402{
3403 struct hclge_vport *vport = hclge_get_vport(handle);
3404 struct hclge_dev *hdev = vport->back;
3405 struct hclge_promisc_param param;
3406
3407 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3408 hclge_cmd_set_promisc_mode(hdev, &param);
3409}
3410
3411static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3412{
3413 struct hclge_desc desc;
d44f9b63
YL		 3414 struct hclge_config_mac_mode_cmd *req =
3415 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3416 u32 loop_en = 0;
46a3df9f
S		 3417 int ret;
3418
3419 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3420 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3421 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3422 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3423 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3424 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3425 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3426 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3427 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3428 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3429 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3430 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3431 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3432 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3433 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3434 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3435
3436 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3437 if (ret)
3438 dev_err(&hdev->pdev->dev,
3439 "mac enable fail, ret =%d.\n", ret);
3440}
3441
c39c4d98
YL		 3442static int hclge_set_loopback(struct hnae3_handle *handle,
3443 enum hnae3_loop loop_mode, bool en)
3444{
3445 struct hclge_vport *vport = hclge_get_vport(handle);
3446 struct hclge_config_mac_mode_cmd *req;
3447 struct hclge_dev *hdev = vport->back;
3448 struct hclge_desc desc;
3449 u32 loop_en;
3450 int ret;
3451
3452 switch (loop_mode) {
3453 case HNAE3_MAC_INTER_LOOP_MAC:
3454 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3455 /* 1 Read out the MAC mode config at first */
3456 hclge_cmd_setup_basic_desc(&desc,
3457 HCLGE_OPC_CONFIG_MAC_MODE,
3458 true);
3459 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3460 if (ret) {
3461 dev_err(&hdev->pdev->dev,
3462 "mac loopback get fail, ret =%d.\n",
3463 ret);
3464 return ret;
3465 }
3466
3467 /* 2 Then setup the loopback flag */
3468 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3469 if (en)
3470 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3471 else
3472 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3473
3474 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3475
3476 /* 3 Config mac work mode with loopback flag
3477 * and its original configure parameters
3478 */
3479 hclge_cmd_reuse_desc(&desc, false);
3480 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3481 if (ret)
3482 dev_err(&hdev->pdev->dev,
3483 "mac loopback set fail, ret =%d.\n", ret);
3484 break;
3485 default:
3486 ret = -ENOTSUPP;
3487 dev_err(&hdev->pdev->dev,
3488 "loop_mode %d is not supported\n", loop_mode);
3489 break;
3490 }
3491
3492 return ret;
3493}
3494
46a3df9f
S		 3495static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3496 int stream_id, bool enable)
3497{
3498 struct hclge_desc desc;
d44f9b63
YL		 3499 struct hclge_cfg_com_tqp_queue_cmd *req =
3500 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3501 int ret;
3502
3503 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3504 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3505 req->stream_id = cpu_to_le16(stream_id);
3506 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3507
3508 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3509 if (ret)
3510 dev_err(&hdev->pdev->dev,
3511 "Tqp enable fail, status =%d.\n", ret);
3512 return ret;
3513}
3514
3515static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3516{
3517 struct hclge_vport *vport = hclge_get_vport(handle);
3518 struct hnae3_queue *queue;
3519 struct hclge_tqp *tqp;
3520 int i;
3521
3522 for (i = 0; i < vport->alloc_tqps; i++) {
3523 queue = handle->kinfo.tqp[i];
3524 tqp = container_of(queue, struct hclge_tqp, q);
3525 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3526 }
3527}
3528
3529static int hclge_ae_start(struct hnae3_handle *handle)
3530{
3531 struct hclge_vport *vport = hclge_get_vport(handle);
3532 struct hclge_dev *hdev = vport->back;
3533 int i, queue_id, ret;
3534
3535 for (i = 0; i < vport->alloc_tqps; i++) {
3536 /* todo clear interrupt */
3537 /* ring enable */
3538 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3539 if (queue_id < 0) {
3540 dev_warn(&hdev->pdev->dev,
3541 "Get invalid queue id, ignore it\n");
3542 continue;
3543 }
3544
3545 hclge_tqp_enable(hdev, queue_id, 0, true);
3546 }
3547 /* mac enable */
3548 hclge_cfg_mac_mode(hdev, true);
3549 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3550 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 3551
3552 ret = hclge_mac_start_phy(hdev);
3553 if (ret)
3554 return ret;
3555
3556 /* reset tqp stats */
3557 hclge_reset_tqp_stats(handle);
3558
3559 return 0;
3560}
3561
3562static void hclge_ae_stop(struct hnae3_handle *handle)
3563{
3564 struct hclge_vport *vport = hclge_get_vport(handle);
3565 struct hclge_dev *hdev = vport->back;
3566 int i, queue_id;
3567
3568 for (i = 0; i < vport->alloc_tqps; i++) {
3569 /* Ring disable */
3570 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3571 if (queue_id < 0) {
3572 dev_warn(&hdev->pdev->dev,
3573 "Get invalid queue id, ignore it\n");
3574 continue;
3575 }
3576
3577 hclge_tqp_enable(hdev, queue_id, 0, false);
3578 }
3579 /* Mac disable */
3580 hclge_cfg_mac_mode(hdev, false);
3581
3582 hclge_mac_stop_phy(hdev);
3583
3584 /* reset tqp stats */
3585 hclge_reset_tqp_stats(handle);
3586}
3587
3588static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3589 u16 cmdq_resp, u8 resp_code,
3590 enum hclge_mac_vlan_tbl_opcode op)
3591{
3592 struct hclge_dev *hdev = vport->back;
3593 int return_status = -EIO;
3594
3595 if (cmdq_resp) {
3596 dev_err(&hdev->pdev->dev,
3597 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3598 cmdq_resp);
3599 return -EIO;
3600 }
3601
3602 if (op == HCLGE_MAC_VLAN_ADD) {
3603 if ((!resp_code) || (resp_code == 1)) {
3604 return_status = 0;
3605 } else if (resp_code == 2) {
3606 return_status = -EIO;
3607 dev_err(&hdev->pdev->dev,
3608 "add mac addr failed for uc_overflow.\n");
3609 } else if (resp_code == 3) {
3610 return_status = -EIO;
3611 dev_err(&hdev->pdev->dev,
3612 "add mac addr failed for mc_overflow.\n");
3613 } else {
3614 dev_err(&hdev->pdev->dev,
3615 "add mac addr failed for undefined, code=%d.\n",
3616 resp_code);
3617 }
3618 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3619 if (!resp_code) {
3620 return_status = 0;
3621 } else if (resp_code == 1) {
3622 return_status = -EIO;
3623 dev_dbg(&hdev->pdev->dev,
3624 "remove mac addr failed for miss.\n");
3625 } else {
3626 dev_err(&hdev->pdev->dev,
3627 "remove mac addr failed for undefined, code=%d.\n",
3628 resp_code);
3629 }
3630 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3631 if (!resp_code) {
3632 return_status = 0;
3633 } else if (resp_code == 1) {
3634 return_status = -EIO;
3635 dev_dbg(&hdev->pdev->dev,
3636 "lookup mac addr failed for miss.\n");
3637 } else {
3638 dev_err(&hdev->pdev->dev,
3639 "lookup mac addr failed for undefined, code=%d.\n",
3640 resp_code);
3641 }
3642 } else {
3643 return_status = -EIO;
3644 dev_err(&hdev->pdev->dev,
3645 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3646 op);
3647 }
3648
3649 return return_status;
3650}
3651
3652static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3653{
3654 int word_num;
3655 int bit_num;
3656
3657 if (vfid > 255 || vfid < 0)
3658 return -EIO;
3659
3660 if (vfid >= 0 && vfid <= 191) {
3661 word_num = vfid / 32;
3662 bit_num = vfid % 32;
3663 if (clr)
a90bb9a5 3664 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3665 else
a90bb9a5 3666 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3667 } else {
3668 word_num = (vfid - 192) / 32;
3669 bit_num = vfid % 32;
3670 if (clr)
a90bb9a5 3671 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3672 else
a90bb9a5 3673 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3674 }
3675
3676 return 0;
3677}
3678
3679static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3680{
3681#define HCLGE_DESC_NUMBER 3
3682#define HCLGE_FUNC_NUMBER_PER_DESC 6
3683 int i, j;
3684
3685 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3686 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3687 if (desc[i].data[j])
3688 return false;
3689
3690 return true;
3691}
3692
d44f9b63 3693static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3694 const u8 *addr)
3695{
3696 const unsigned char *mac_addr = addr;
3697 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3698 (mac_addr[0]) | (mac_addr[1] << 8);
3699 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3700
3701 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3702 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3703}
3704
1db9b1bf
YL		 3705static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3706 const u8 *addr)
46a3df9f
S		 3707{
3708 u16 high_val = addr[1] | (addr[0] << 8);
3709 struct hclge_dev *hdev = vport->back;
3710 u32 rsh = 4 - hdev->mta_mac_sel_type;
3711 u16 ret_val = (high_val >> rsh) & 0xfff;
3712
3713 return ret_val;
3714}
3715
3716static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3717 enum hclge_mta_dmac_sel_type mta_mac_sel,
3718 bool enable)
3719{
d44f9b63 3720 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3721 struct hclge_desc desc;
3722 int ret;
3723
d44f9b63 3724 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3725 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3726
3727 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3728 enable);
3729 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3730 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3731
3732 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3733 if (ret) {
3734 dev_err(&hdev->pdev->dev,
3735 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3736 ret);
3737 return ret;
3738 }
3739
3740 return 0;
3741}
3742
3743int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3744 u8 func_id,
3745 bool enable)
3746{
d44f9b63 3747 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3748 struct hclge_desc desc;
3749 int ret;
3750
d44f9b63 3751 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3752 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3753
3754 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3755 enable);
3756 req->function_id = func_id;
3757
3758 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3759 if (ret) {
3760 dev_err(&hdev->pdev->dev,
3761 "Config func_id enable failed for cmd_send, ret =%d.\n",
3762 ret);
3763 return ret;
3764 }
3765
3766 return 0;
3767}
3768
3769static int hclge_set_mta_table_item(struct hclge_vport *vport,
3770 u16 idx,
3771 bool enable)
3772{
3773 struct hclge_dev *hdev = vport->back;
d44f9b63 3774 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3775 struct hclge_desc desc;
a90bb9a5 3776 u16 item_idx = 0;
46a3df9f
S		 3777 int ret;
3778
d44f9b63 3779 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 3780 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3781 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3782
a90bb9a5 3783 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 3784 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3785 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3786
3787 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3788 if (ret) {
3789 dev_err(&hdev->pdev->dev,
3790 "Config mta table item failed for cmd_send, ret =%d.\n",
3791 ret);
3792 return ret;
3793 }
3794
3795 return 0;
3796}
3797
3798static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3799 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3800{
3801 struct hclge_dev *hdev = vport->back;
3802 struct hclge_desc desc;
3803 u8 resp_code;
a90bb9a5 3804 u16 retval;
46a3df9f
S		 3805 int ret;
3806
3807 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3808
d44f9b63 3809 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3810
3811 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3812 if (ret) {
3813 dev_err(&hdev->pdev->dev,
3814 "del mac addr failed for cmd_send, ret =%d.\n",
3815 ret);
3816 return ret;
3817 }
a90bb9a5
YL		 3818 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3819 retval = le16_to_cpu(desc.retval);
46a3df9f 3820
a90bb9a5 3821 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3822 HCLGE_MAC_VLAN_REMOVE);
3823}
3824
3825static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3826 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3827 struct hclge_desc *desc,
3828 bool is_mc)
3829{
3830 struct hclge_dev *hdev = vport->back;
3831 u8 resp_code;
a90bb9a5 3832 u16 retval;
46a3df9f
S		 3833 int ret;
3834
3835 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3836 if (is_mc) {
3837 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3838 memcpy(desc[0].data,
3839 req,
d44f9b63 3840 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3841 hclge_cmd_setup_basic_desc(&desc[1],
3842 HCLGE_OPC_MAC_VLAN_ADD,
3843 true);
3844 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3845 hclge_cmd_setup_basic_desc(&desc[2],
3846 HCLGE_OPC_MAC_VLAN_ADD,
3847 true);
3848 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3849 } else {
3850 memcpy(desc[0].data,
3851 req,
d44f9b63 3852 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3853 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3854 }
3855 if (ret) {
3856 dev_err(&hdev->pdev->dev,
3857 "lookup mac addr failed for cmd_send, ret =%d.\n",
3858 ret);
3859 return ret;
3860 }
a90bb9a5
YL		 3861 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3862 retval = le16_to_cpu(desc[0].retval);
46a3df9f 3863
a90bb9a5 3864 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3865 HCLGE_MAC_VLAN_LKUP);
3866}
3867
3868static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3869 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3870 struct hclge_desc *mc_desc)
3871{
3872 struct hclge_dev *hdev = vport->back;
3873 int cfg_status;
3874 u8 resp_code;
a90bb9a5 3875 u16 retval;
46a3df9f
S		 3876 int ret;
3877
3878 if (!mc_desc) {
3879 struct hclge_desc desc;
3880
3881 hclge_cmd_setup_basic_desc(&desc,
3882 HCLGE_OPC_MAC_VLAN_ADD,
3883 false);
d44f9b63
YL		 3884 memcpy(desc.data, req,
3885 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3886 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 3887 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3888 retval = le16_to_cpu(desc.retval);
3889
3890 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3891 resp_code,
3892 HCLGE_MAC_VLAN_ADD);
3893 } else {
c3b6f755 3894 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 3895 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3896 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 3897 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3898 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 3899 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3900 memcpy(mc_desc[0].data, req,
d44f9b63 3901 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3902 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 3903 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3904 retval = le16_to_cpu(mc_desc[0].retval);
3905
3906 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3907 resp_code,
3908 HCLGE_MAC_VLAN_ADD);
3909 }
3910
3911 if (ret) {
3912 dev_err(&hdev->pdev->dev,
3913 "add mac addr failed for cmd_send, ret =%d.\n",
3914 ret);
3915 return ret;
3916 }
3917
3918 return cfg_status;
3919}
3920
3921static int hclge_add_uc_addr(struct hnae3_handle *handle,
3922 const unsigned char *addr)
3923{
3924 struct hclge_vport *vport = hclge_get_vport(handle);
3925
3926 return hclge_add_uc_addr_common(vport, addr);
3927}
3928
3929int hclge_add_uc_addr_common(struct hclge_vport *vport,
3930 const unsigned char *addr)
3931{
3932 struct hclge_dev *hdev = vport->back;
d44f9b63 3933 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 3934 enum hclge_cmd_status status;
a90bb9a5 3935 u16 egress_port = 0;
46a3df9f
S		 3936
3937 /* mac addr check */
3938 if (is_zero_ether_addr(addr) ||
3939 is_broadcast_ether_addr(addr) ||
3940 is_multicast_ether_addr(addr)) {
3941 dev_err(&hdev->pdev->dev,
3942 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3943 addr,
3944 is_zero_ether_addr(addr),
3945 is_broadcast_ether_addr(addr),
3946 is_multicast_ether_addr(addr));
3947 return -EINVAL;
3948 }
3949
3950 memset(&req, 0, sizeof(req));
3951 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3952 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3953 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
3954 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 3955
3956 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
3957 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
3958 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 3959 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 3960 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 3961 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 3962
3963 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 3964
3965 hclge_prepare_mac_addr(&req, addr);
3966
3967 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
3968
3969 return status;
3970}
3971
3972static int hclge_rm_uc_addr(struct hnae3_handle *handle,
3973 const unsigned char *addr)
3974{
3975 struct hclge_vport *vport = hclge_get_vport(handle);
3976
3977 return hclge_rm_uc_addr_common(vport, addr);
3978}
3979
3980int hclge_rm_uc_addr_common(struct hclge_vport *vport,
3981 const unsigned char *addr)
3982{
3983 struct hclge_dev *hdev = vport->back;
d44f9b63 3984 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 3985 enum hclge_cmd_status status;
3986
3987 /* mac addr check */
3988 if (is_zero_ether_addr(addr) ||
3989 is_broadcast_ether_addr(addr) ||
3990 is_multicast_ether_addr(addr)) {
3991 dev_dbg(&hdev->pdev->dev,
3992 "Remove mac err! invalid mac:%pM.\n",
3993 addr);
3994 return -EINVAL;
3995 }
3996
3997 memset(&req, 0, sizeof(req));
3998 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3999 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4000 hclge_prepare_mac_addr(&req, addr);
4001 status = hclge_remove_mac_vlan_tbl(vport, &req);
4002
4003 return status;
4004}
4005
4006static int hclge_add_mc_addr(struct hnae3_handle *handle,
4007 const unsigned char *addr)
4008{
4009 struct hclge_vport *vport = hclge_get_vport(handle);
4010
4011 return hclge_add_mc_addr_common(vport, addr);
4012}
4013
4014int hclge_add_mc_addr_common(struct hclge_vport *vport,
4015 const unsigned char *addr)
4016{
4017 struct hclge_dev *hdev = vport->back;
d44f9b63 4018 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4019 struct hclge_desc desc[3];
4020 u16 tbl_idx;
4021 int status;
4022
4023 /* mac addr check */
4024 if (!is_multicast_ether_addr(addr)) {
4025 dev_err(&hdev->pdev->dev,
4026 "Add mc mac err! invalid mac:%pM.\n",
4027 addr);
4028 return -EINVAL;
4029 }
4030 memset(&req, 0, sizeof(req));
4031 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4032 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4033 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4034 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4035 hclge_prepare_mac_addr(&req, addr);
4036 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4037 if (!status) {
4038 /* This mac addr exist, update VFID for it */
4039 hclge_update_desc_vfid(desc, vport->vport_id, false);
4040 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4041 } else {
4042 /* This mac addr do not exist, add new entry for it */
4043 memset(desc[0].data, 0, sizeof(desc[0].data));
4044 memset(desc[1].data, 0, sizeof(desc[0].data));
4045 memset(desc[2].data, 0, sizeof(desc[0].data));
4046 hclge_update_desc_vfid(desc, vport->vport_id, false);
4047 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4048 }
4049
4050 /* Set MTA table for this MAC address */
4051 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4052 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4053
4054 return status;
4055}
4056
4057static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4058 const unsigned char *addr)
4059{
4060 struct hclge_vport *vport = hclge_get_vport(handle);
4061
4062 return hclge_rm_mc_addr_common(vport, addr);
4063}
4064
4065int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4066 const unsigned char *addr)
4067{
4068 struct hclge_dev *hdev = vport->back;
d44f9b63 4069 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4070 enum hclge_cmd_status status;
4071 struct hclge_desc desc[3];
4072 u16 tbl_idx;
4073
4074 /* mac addr check */
4075 if (!is_multicast_ether_addr(addr)) {
4076 dev_dbg(&hdev->pdev->dev,
4077 "Remove mc mac err! invalid mac:%pM.\n",
4078 addr);
4079 return -EINVAL;
4080 }
4081
4082 memset(&req, 0, sizeof(req));
4083 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4084 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4085 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4086 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4087 hclge_prepare_mac_addr(&req, addr);
4088 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4089 if (!status) {
4090 /* This mac addr exist, remove this handle's VFID for it */
4091 hclge_update_desc_vfid(desc, vport->vport_id, true);
4092
4093 if (hclge_is_all_function_id_zero(desc))
4094 /* All the vfid is zero, so need to delete this entry */
4095 status = hclge_remove_mac_vlan_tbl(vport, &req);
4096 else
4097 /* Not all the vfid is zero, update the vfid */
4098 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4099
4100 } else {
4101 /* This mac addr do not exist, can't delete it */
4102 dev_err(&hdev->pdev->dev,
d7629e74 4103 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 4104 status);
4105 return -EIO;
4106 }
4107
4108 /* Set MTB table for this MAC address */
4109 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4110 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4111
4112 return status;
4113}
4114
4115static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4116{
4117 struct hclge_vport *vport = hclge_get_vport(handle);
4118 struct hclge_dev *hdev = vport->back;
4119
4120 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4121}
4122
4123static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4124{
4125 const unsigned char *new_addr = (const unsigned char *)p;
4126 struct hclge_vport *vport = hclge_get_vport(handle);
4127 struct hclge_dev *hdev = vport->back;
4128
4129 /* mac addr check */
4130 if (is_zero_ether_addr(new_addr) ||
4131 is_broadcast_ether_addr(new_addr) ||
4132 is_multicast_ether_addr(new_addr)) {
4133 dev_err(&hdev->pdev->dev,
4134 "Change uc mac err! invalid mac:%p.\n",
4135 new_addr);
4136 return -EINVAL;
4137 }
4138
4139 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4140
4141 if (!hclge_add_uc_addr(handle, new_addr)) {
4142 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4143 return 0;
4144 }
4145
4146 return -EIO;
4147}
4148
4149static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4150 bool filter_en)
4151{
d44f9b63 4152 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4153 struct hclge_desc desc;
4154 int ret;
4155
4156 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4157
d44f9b63 4158 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4159 req->vlan_type = vlan_type;
4160 req->vlan_fe = filter_en;
4161
4162 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4163 if (ret) {
4164 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4165 ret);
4166 return ret;
4167 }
4168
4169 return 0;
4170}
4171
4172int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4173 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4174{
4175#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4176 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4177 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4178 struct hclge_desc desc[2];
4179 u8 vf_byte_val;
4180 u8 vf_byte_off;
4181 int ret;
4182
4183 hclge_cmd_setup_basic_desc(&desc[0],
4184 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4185 hclge_cmd_setup_basic_desc(&desc[1],
4186 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4187
4188 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4189
4190 vf_byte_off = vfid / 8;
4191 vf_byte_val = 1 << (vfid % 8);
4192
d44f9b63
YL		 4193 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4194 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4195
a90bb9a5 4196 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4197 req0->vlan_cfg = is_kill;
4198
4199 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4200 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4201 else
4202 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4203
4204 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4205 if (ret) {
4206 dev_err(&hdev->pdev->dev,
4207 "Send vf vlan command fail, ret =%d.\n",
4208 ret);
4209 return ret;
4210 }
4211
4212 if (!is_kill) {
4213 if (!req0->resp_code || req0->resp_code == 1)
4214 return 0;
4215
4216 dev_err(&hdev->pdev->dev,
4217 "Add vf vlan filter fail, ret =%d.\n",
4218 req0->resp_code);
4219 } else {
4220 if (!req0->resp_code)
4221 return 0;
4222
4223 dev_err(&hdev->pdev->dev,
4224 "Kill vf vlan filter fail, ret =%d.\n",
4225 req0->resp_code);
4226 }
4227
4228 return -EIO;
4229}
4230
4231static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4232 __be16 proto, u16 vlan_id,
4233 bool is_kill)
4234{
4235 struct hclge_vport *vport = hclge_get_vport(handle);
4236 struct hclge_dev *hdev = vport->back;
d44f9b63 4237 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4238 struct hclge_desc desc;
4239 u8 vlan_offset_byte_val;
4240 u8 vlan_offset_byte;
4241 u8 vlan_offset_160;
4242 int ret;
4243
4244 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4245
4246 vlan_offset_160 = vlan_id / 160;
4247 vlan_offset_byte = (vlan_id % 160) / 8;
4248 vlan_offset_byte_val = 1 << (vlan_id % 8);
4249
d44f9b63 4250 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4251 req->vlan_offset = vlan_offset_160;
4252 req->vlan_cfg = is_kill;
4253 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4254
4255 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4256 if (ret) {
4257 dev_err(&hdev->pdev->dev,
4258 "port vlan command, send fail, ret =%d.\n",
4259 ret);
4260 return ret;
4261 }
4262
4263 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4264 if (ret) {
4265 dev_err(&hdev->pdev->dev,
4266 "Set pf vlan filter config fail, ret =%d.\n",
4267 ret);
4268 return -EIO;
4269 }
4270
4271 return 0;
4272}
4273
4274static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4275 u16 vlan, u8 qos, __be16 proto)
4276{
4277 struct hclge_vport *vport = hclge_get_vport(handle);
4278 struct hclge_dev *hdev = vport->back;
4279
4280 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4281 return -EINVAL;
4282 if (proto != htons(ETH_P_8021Q))
4283 return -EPROTONOSUPPORT;
4284
4285 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4286}
4287
4288static int hclge_init_vlan_config(struct hclge_dev *hdev)
4289{
4290#define HCLGE_VLAN_TYPE_VF_TABLE 0
4291#define HCLGE_VLAN_TYPE_PORT_TABLE 1
5e43aef8 4292 struct hnae3_handle *handle;
46a3df9f
S		 4293 int ret;
4294
4295 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
4296 true);
4297 if (ret)
4298 return ret;
4299
4300 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
4301 true);
5e43aef8
L		 4302 if (ret)
4303 return ret;
46a3df9f 4304
5e43aef8
L		 4305 handle = &hdev->vport[0].nic;
4306 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4307}
4308
4309static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4310{
4311 struct hclge_vport *vport = hclge_get_vport(handle);
d44f9b63 4312 struct hclge_config_max_frm_size_cmd *req;
46a3df9f
S		 4313 struct hclge_dev *hdev = vport->back;
4314 struct hclge_desc desc;
4315 int ret;
4316
4317 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
4318 return -EINVAL;
4319
4320 hdev->mps = new_mtu;
4321 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4322
d44f9b63 4323 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
46a3df9f
S		 4324 req->max_frm_size = cpu_to_le16(new_mtu);
4325
4326 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4327 if (ret) {
4328 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4329 return ret;
4330 }
4331
4332 return 0;
4333}
4334
4335static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4336 bool enable)
4337{
d44f9b63 4338 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4339 struct hclge_desc desc;
4340 int ret;
4341
4342 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4343
d44f9b63 4344 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4345 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4346 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4347
4348 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4349 if (ret) {
4350 dev_err(&hdev->pdev->dev,
4351 "Send tqp reset cmd error, status =%d\n", ret);
4352 return ret;
4353 }
4354
4355 return 0;
4356}
4357
4358static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4359{
d44f9b63 4360 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4361 struct hclge_desc desc;
4362 int ret;
4363
4364 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4365
d44f9b63 4366 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4367 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4368
4369 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4370 if (ret) {
4371 dev_err(&hdev->pdev->dev,
4372 "Get reset status error, status =%d\n", ret);
4373 return ret;
4374 }
4375
4376 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4377}
4378
4379static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4380{
4381 struct hclge_vport *vport = hclge_get_vport(handle);
4382 struct hclge_dev *hdev = vport->back;
4383 int reset_try_times = 0;
4384 int reset_status;
4385 int ret;
4386
4387 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4388 if (ret) {
4389 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4390 return;
4391 }
4392
4393 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4394 if (ret) {
4395 dev_warn(&hdev->pdev->dev,
4396 "Send reset tqp cmd fail, ret = %d\n", ret);
4397 return;
4398 }
4399
4400 reset_try_times = 0;
4401 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4402 /* Wait for tqp hw reset */
4403 msleep(20);
4404 reset_status = hclge_get_reset_status(hdev, queue_id);
4405 if (reset_status)
4406 break;
4407 }
4408
4409 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4410 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4411 return;
4412 }
4413
4414 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4415 if (ret) {
4416 dev_warn(&hdev->pdev->dev,
4417 "Deassert the soft reset fail, ret = %d\n", ret);
4418 return;
4419 }
4420}
4421
4422static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4423{
4424 struct hclge_vport *vport = hclge_get_vport(handle);
4425 struct hclge_dev *hdev = vport->back;
4426
4427 return hdev->fw_version;
4428}
4429
4430static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4431 u32 *rx_en, u32 *tx_en)
4432{
4433 struct hclge_vport *vport = hclge_get_vport(handle);
4434 struct hclge_dev *hdev = vport->back;
4435
4436 *auto_neg = hclge_get_autoneg(handle);
4437
4438 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4439 *rx_en = 0;
4440 *tx_en = 0;
4441 return;
4442 }
4443
4444 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4445 *rx_en = 1;
4446 *tx_en = 0;
4447 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4448 *tx_en = 1;
4449 *rx_en = 0;
4450 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4451 *rx_en = 1;
4452 *tx_en = 1;
4453 } else {
4454 *rx_en = 0;
4455 *tx_en = 0;
4456 }
4457}
4458
4459static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4460 u8 *auto_neg, u32 *speed, u8 *duplex)
4461{
4462 struct hclge_vport *vport = hclge_get_vport(handle);
4463 struct hclge_dev *hdev = vport->back;
4464
4465 if (speed)
4466 *speed = hdev->hw.mac.speed;
4467 if (duplex)
4468 *duplex = hdev->hw.mac.duplex;
4469 if (auto_neg)
4470 *auto_neg = hdev->hw.mac.autoneg;
4471}
4472
4473static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4474{
4475 struct hclge_vport *vport = hclge_get_vport(handle);
4476 struct hclge_dev *hdev = vport->back;
4477
4478 if (media_type)
4479 *media_type = hdev->hw.mac.media_type;
4480}
4481
4482static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4483 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4484{
4485 struct hclge_vport *vport = hclge_get_vport(handle);
4486 struct hclge_dev *hdev = vport->back;
4487 struct phy_device *phydev = hdev->hw.mac.phydev;
4488 int mdix_ctrl, mdix, retval, is_resolved;
4489
4490 if (!phydev) {
4491 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4492 *tp_mdix = ETH_TP_MDI_INVALID;
4493 return;
4494 }
4495
4496 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4497
4498 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4499 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4500 HCLGE_PHY_MDIX_CTRL_S);
4501
4502 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4503 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4504 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4505
4506 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4507
4508 switch (mdix_ctrl) {
4509 case 0x0:
4510 *tp_mdix_ctrl = ETH_TP_MDI;
4511 break;
4512 case 0x1:
4513 *tp_mdix_ctrl = ETH_TP_MDI_X;
4514 break;
4515 case 0x3:
4516 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4517 break;
4518 default:
4519 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4520 break;
4521 }
4522
4523 if (!is_resolved)
4524 *tp_mdix = ETH_TP_MDI_INVALID;
4525 else if (mdix)
4526 *tp_mdix = ETH_TP_MDI_X;
4527 else
4528 *tp_mdix = ETH_TP_MDI;
4529}
4530
4531static int hclge_init_client_instance(struct hnae3_client *client,
4532 struct hnae3_ae_dev *ae_dev)
4533{
4534 struct hclge_dev *hdev = ae_dev->priv;
4535 struct hclge_vport *vport;
4536 int i, ret;
4537
4538 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4539 vport = &hdev->vport[i];
4540
4541 switch (client->type) {
4542 case HNAE3_CLIENT_KNIC:
4543
4544 hdev->nic_client = client;
4545 vport->nic.client = client;
4546 ret = client->ops->init_instance(&vport->nic);
4547 if (ret)
4548 goto err;
4549
4550 if (hdev->roce_client &&
e92a0843 4551 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4552 struct hnae3_client *rc = hdev->roce_client;
4553
4554 ret = hclge_init_roce_base_info(vport);
4555 if (ret)
4556 goto err;
4557
4558 ret = rc->ops->init_instance(&vport->roce);
4559 if (ret)
4560 goto err;
4561 }
4562
4563 break;
4564 case HNAE3_CLIENT_UNIC:
4565 hdev->nic_client = client;
4566 vport->nic.client = client;
4567
4568 ret = client->ops->init_instance(&vport->nic);
4569 if (ret)
4570 goto err;
4571
4572 break;
4573 case HNAE3_CLIENT_ROCE:
e92a0843 4574 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4575 hdev->roce_client = client;
4576 vport->roce.client = client;
4577 }
4578
3a46f34d 4579 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 4580 ret = hclge_init_roce_base_info(vport);
4581 if (ret)
4582 goto err;
4583
4584 ret = client->ops->init_instance(&vport->roce);
4585 if (ret)
4586 goto err;
4587 }
4588 }
4589 }
4590
4591 return 0;
4592err:
4593 return ret;
4594}
4595
4596static void hclge_uninit_client_instance(struct hnae3_client *client,
4597 struct hnae3_ae_dev *ae_dev)
4598{
4599 struct hclge_dev *hdev = ae_dev->priv;
4600 struct hclge_vport *vport;
4601 int i;
4602
4603 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4604 vport = &hdev->vport[i];
a17dcf3f 4605 if (hdev->roce_client) {
46a3df9f
S		 4606 hdev->roce_client->ops->uninit_instance(&vport->roce,
4607 0);
a17dcf3f
L		 4608 hdev->roce_client = NULL;
4609 vport->roce.client = NULL;
4610 }
46a3df9f
S		 4611 if (client->type == HNAE3_CLIENT_ROCE)
4612 return;
a17dcf3f 4613 if (client->ops->uninit_instance) {
46a3df9f 4614 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 4615 hdev->nic_client = NULL;
4616 vport->nic.client = NULL;
4617 }
46a3df9f
S		 4618 }
4619}
4620
4621static int hclge_pci_init(struct hclge_dev *hdev)
4622{
4623 struct pci_dev *pdev = hdev->pdev;
4624 struct hclge_hw *hw;
4625 int ret;
4626
4627 ret = pci_enable_device(pdev);
4628 if (ret) {
4629 dev_err(&pdev->dev, "failed to enable PCI device\n");
4630 goto err_no_drvdata;
4631 }
4632
4633 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4634 if (ret) {
4635 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4636 if (ret) {
4637 dev_err(&pdev->dev,
4638 "can't set consistent PCI DMA");
4639 goto err_disable_device;
4640 }
4641 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4642 }
4643
4644 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4645 if (ret) {
4646 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4647 goto err_disable_device;
4648 }
4649
4650 pci_set_master(pdev);
4651 hw = &hdev->hw;
4652 hw->back = hdev;
4653 hw->io_base = pcim_iomap(pdev, 2, 0);
4654 if (!hw->io_base) {
4655 dev_err(&pdev->dev, "Can't map configuration register space\n");
4656 ret = -ENOMEM;
4657 goto err_clr_master;
4658 }
4659
709eb41a
L		 4660 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
4661
46a3df9f
S		 4662 return 0;
4663err_clr_master:
4664 pci_clear_master(pdev);
4665 pci_release_regions(pdev);
4666err_disable_device:
4667 pci_disable_device(pdev);
4668err_no_drvdata:
4669 pci_set_drvdata(pdev, NULL);
4670
4671 return ret;
4672}
4673
4674static void hclge_pci_uninit(struct hclge_dev *hdev)
4675{
4676 struct pci_dev *pdev = hdev->pdev;
4677
4678 if (hdev->flag & HCLGE_FLAG_USE_MSIX) {
4679 pci_disable_msix(pdev);
4680 devm_kfree(&pdev->dev, hdev->msix_entries);
4681 hdev->msix_entries = NULL;
4682 } else {
4683 pci_disable_msi(pdev);
4684 }
4685
4686 pci_clear_master(pdev);
4687 pci_release_mem_regions(pdev);
4688 pci_disable_device(pdev);
4689}
4690
4691static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4692{
4693 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 4694 struct hclge_dev *hdev;
4695 int ret;
4696
4697 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4698 if (!hdev) {
4699 ret = -ENOMEM;
4700 goto err_hclge_dev;
4701 }
4702
4703 hdev->flag |= HCLGE_FLAG_USE_MSIX;
4704 hdev->pdev = pdev;
4705 hdev->ae_dev = ae_dev;
4ed340ab 4706 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 4707 ae_dev->priv = hdev;
4708
46a3df9f
S		 4709 ret = hclge_pci_init(hdev);
4710 if (ret) {
4711 dev_err(&pdev->dev, "PCI init failed\n");
4712 goto err_pci_init;
4713 }
4714
3efb960f
L		 4715 /* Firmware command queue initialize */
4716 ret = hclge_cmd_queue_init(hdev);
4717 if (ret) {
4718 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
4719 return ret;
4720 }
4721
4722 /* Firmware command initialize */
46a3df9f
S		 4723 ret = hclge_cmd_init(hdev);
4724 if (ret)
4725 goto err_cmd_init;
4726
4727 ret = hclge_get_cap(hdev);
4728 if (ret) {
e00e2197
CIK		 4729 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4730 ret);
46a3df9f
S		 4731 return ret;
4732 }
4733
4734 ret = hclge_configure(hdev);
4735 if (ret) {
4736 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4737 return ret;
4738 }
4739
4740 if (hdev->flag & HCLGE_FLAG_USE_MSIX)
4741 ret = hclge_init_msix(hdev);
4742 else
4743 ret = hclge_init_msi(hdev);
4744 if (ret) {
4745 dev_err(&pdev->dev, "Init msix/msi error, ret = %d.\n", ret);
4746 return ret;
4747 }
4748
466b0c00
L		 4749 ret = hclge_misc_irq_init(hdev);
4750 if (ret) {
4751 dev_err(&pdev->dev,
4752 "Misc IRQ(vector0) init error, ret = %d.\n",
4753 ret);
4754 return ret;
4755 }
4756
46a3df9f
S		 4757 ret = hclge_alloc_tqps(hdev);
4758 if (ret) {
4759 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4760 return ret;
4761 }
4762
4763 ret = hclge_alloc_vport(hdev);
4764 if (ret) {
4765 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4766 return ret;
4767 }
4768
7df7dad6
L		 4769 ret = hclge_map_tqp(hdev);
4770 if (ret) {
4771 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4772 return ret;
4773 }
4774
cf9cca2d 4775 ret = hclge_mac_mdio_config(hdev);
4776 if (ret) {
4777 dev_warn(&hdev->pdev->dev,
4778 "mdio config fail ret=%d\n", ret);
4779 return ret;
4780 }
4781
46a3df9f
S		 4782 ret = hclge_mac_init(hdev);
4783 if (ret) {
4784 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4785 return ret;
4786 }
4787 ret = hclge_buffer_alloc(hdev);
4788 if (ret) {
4789 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4790 return ret;
4791 }
4792
4793 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4794 if (ret) {
4795 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4796 return ret;
4797 }
4798
46a3df9f
S		 4799 ret = hclge_init_vlan_config(hdev);
4800 if (ret) {
4801 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4802 return ret;
4803 }
4804
4805 ret = hclge_tm_schd_init(hdev);
4806 if (ret) {
4807 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4808 return ret;
68ece54e
YL		 4809 }
4810
4811 ret = hclge_rss_init_hw(hdev);
4812 if (ret) {
4813 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4814 return ret;
46a3df9f
S		 4815 }
4816
cacde272
YL		 4817 hclge_dcb_ops_set(hdev);
4818
d039ef68 4819 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f
S		 4820 INIT_WORK(&hdev->service_task, hclge_service_task);
4821
466b0c00
L		 4822 /* Enable MISC vector(vector0) */
4823 hclge_enable_vector(&hdev->misc_vector, true);
4824
46a3df9f
S		 4825 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4826 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4827
4828 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4829 return 0;
4830
4831err_cmd_init:
4832 pci_release_regions(pdev);
4833err_pci_init:
4834 pci_set_drvdata(pdev, NULL);
4835err_hclge_dev:
4836 return ret;
4837}
4838
c6dc5213 4839static void hclge_stats_clear(struct hclge_dev *hdev)
4840{
4841 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
4842}
4843
4ed340ab
L		 4844static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
4845{
4846 struct hclge_dev *hdev = ae_dev->priv;
4847 struct pci_dev *pdev = ae_dev->pdev;
4848 int ret;
4849
4850 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4851
c6dc5213 4852 hclge_stats_clear(hdev);
4853
4ed340ab
L		 4854 ret = hclge_cmd_init(hdev);
4855 if (ret) {
4856 dev_err(&pdev->dev, "Cmd queue init failed\n");
4857 return ret;
4858 }
4859
4860 ret = hclge_get_cap(hdev);
4861 if (ret) {
4862 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4863 ret);
4864 return ret;
4865 }
4866
4867 ret = hclge_configure(hdev);
4868 if (ret) {
4869 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4870 return ret;
4871 }
4872
4873 ret = hclge_map_tqp(hdev);
4874 if (ret) {
4875 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4876 return ret;
4877 }
4878
4879 ret = hclge_mac_init(hdev);
4880 if (ret) {
4881 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4882 return ret;
4883 }
4884
4885 ret = hclge_buffer_alloc(hdev);
4886 if (ret) {
4887 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4888 return ret;
4889 }
4890
4891 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4892 if (ret) {
4893 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4894 return ret;
4895 }
4896
4897 ret = hclge_init_vlan_config(hdev);
4898 if (ret) {
4899 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4900 return ret;
4901 }
4902
4903 ret = hclge_tm_schd_init(hdev);
4904 if (ret) {
4905 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4906 return ret;
4907 }
4908
4909 ret = hclge_rss_init_hw(hdev);
4910 if (ret) {
4911 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4912 return ret;
4913 }
4914
4915 /* Enable MISC vector(vector0) */
4916 hclge_enable_vector(&hdev->misc_vector, true);
4917
4918 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
4919 HCLGE_DRIVER_NAME);
4920
4921 return 0;
4922}
4923
46a3df9f
S		 4924static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4925{
4926 struct hclge_dev *hdev = ae_dev->priv;
4927 struct hclge_mac *mac = &hdev->hw.mac;
4928
4929 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4930
2a32ca13
AB		 4931 if (IS_ENABLED(CONFIG_PCI_IOV))
4932 hclge_disable_sriov(hdev);
46a3df9f 4933
d039ef68 4934 if (hdev->service_timer.function)
46a3df9f
S		 4935 del_timer_sync(&hdev->service_timer);
4936 if (hdev->service_task.func)
4937 cancel_work_sync(&hdev->service_task);
4938
4939 if (mac->phydev)
4940 mdiobus_unregister(mac->mdio_bus);
4941
466b0c00
L		 4942 /* Disable MISC vector(vector0) */
4943 hclge_enable_vector(&hdev->misc_vector, false);
4944 hclge_free_vector(hdev, 0);
46a3df9f
S		 4945 hclge_destroy_cmd_queue(&hdev->hw);
4946 hclge_pci_uninit(hdev);
4947 ae_dev->priv = NULL;
4948}
4949
4950static const struct hnae3_ae_ops hclge_ops = {
4951 .init_ae_dev = hclge_init_ae_dev,
4952 .uninit_ae_dev = hclge_uninit_ae_dev,
4953 .init_client_instance = hclge_init_client_instance,
4954 .uninit_client_instance = hclge_uninit_client_instance,
4955 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4956 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4957 .get_vector = hclge_get_vector,
4958 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 4959 .set_loopback = hclge_set_loopback,
46a3df9f
S		 4960 .start = hclge_ae_start,
4961 .stop = hclge_ae_stop,
4962 .get_status = hclge_get_status,
4963 .get_ksettings_an_result = hclge_get_ksettings_an_result,
4964 .update_speed_duplex_h = hclge_update_speed_duplex_h,
4965 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
4966 .get_media_type = hclge_get_media_type,
4967 .get_rss_key_size = hclge_get_rss_key_size,
4968 .get_rss_indir_size = hclge_get_rss_indir_size,
4969 .get_rss = hclge_get_rss,
4970 .set_rss = hclge_set_rss,
f7db940a 4971 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 4972 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 4973 .get_tc_size = hclge_get_tc_size,
4974 .get_mac_addr = hclge_get_mac_addr,
4975 .set_mac_addr = hclge_set_mac_addr,
4976 .add_uc_addr = hclge_add_uc_addr,
4977 .rm_uc_addr = hclge_rm_uc_addr,
4978 .add_mc_addr = hclge_add_mc_addr,
4979 .rm_mc_addr = hclge_rm_mc_addr,
4980 .set_autoneg = hclge_set_autoneg,
4981 .get_autoneg = hclge_get_autoneg,
4982 .get_pauseparam = hclge_get_pauseparam,
4983 .set_mtu = hclge_set_mtu,
4984 .reset_queue = hclge_reset_tqp,
4985 .get_stats = hclge_get_stats,
4986 .update_stats = hclge_update_stats,
4987 .get_strings = hclge_get_strings,
4988 .get_sset_count = hclge_get_sset_count,
4989 .get_fw_version = hclge_get_fw_version,
4990 .get_mdix_mode = hclge_get_mdix_mode,
4991 .set_vlan_filter = hclge_set_port_vlan_filter,
4992 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4ed340ab 4993 .reset_event = hclge_reset_event,
46a3df9f
S		 4994};
4995
4996static struct hnae3_ae_algo ae_algo = {
4997 .ops = &hclge_ops,
4998 .name = HCLGE_NAME,
4999 .pdev_id_table = ae_algo_pci_tbl,
5000};
5001
5002static int hclge_init(void)
5003{
5004 pr_info("%s is initializing\n", HCLGE_NAME);
5005
5006 return hnae3_register_ae_algo(&ae_algo);
5007}
5008
5009static void hclge_exit(void)
5010{
5011 hnae3_unregister_ae_algo(&ae_algo);
5012}
5013module_init(hclge_init);
5014module_exit(hclge_exit);
5015
5016MODULE_LICENSE("GPL");
5017MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5018MODULE_DESCRIPTION("HCLGE Driver");
5019MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)