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net: hns3: Set STATE_DOWN bit of hdev state when stopping net
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
2866ccb2 14#include <linux/if_vlan.h>
f2f432f2 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
dde1a86e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
22#include "hnae3.h"
23
24#define HCLGE_NAME "hclge"
25#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
46a3df9f 27
46a3df9f
S		 28static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
29 enum hclge_mta_dmac_sel_type mta_mac_sel,
30 bool enable);
f9fd82a9 31static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 32static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 33static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 34
35static struct hnae3_ae_algo ae_algo;
36
37static const struct pci_device_id ae_algo_pci_tbl[] = {
38 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
39 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 45 /* required last entry */
46a3df9f
S		 46 {0, }
47};
48
2f550a46
YL		 49MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
50
46a3df9f
S		 51static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
52 "Mac Loopback test",
53 "Serdes Loopback test",
54 "Phy Loopback test"
55};
56
46a3df9f
S		 57static const struct hclge_comm_stats_str g_mac_stats_string[] = {
58 {"mac_tx_mac_pause_num",
59 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
60 {"mac_rx_mac_pause_num",
61 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
62 {"mac_tx_pfc_pri0_pkt_num",
63 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
64 {"mac_tx_pfc_pri1_pkt_num",
65 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
66 {"mac_tx_pfc_pri2_pkt_num",
67 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
68 {"mac_tx_pfc_pri3_pkt_num",
69 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
70 {"mac_tx_pfc_pri4_pkt_num",
71 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
72 {"mac_tx_pfc_pri5_pkt_num",
73 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
74 {"mac_tx_pfc_pri6_pkt_num",
75 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
76 {"mac_tx_pfc_pri7_pkt_num",
77 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
78 {"mac_rx_pfc_pri0_pkt_num",
79 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
80 {"mac_rx_pfc_pri1_pkt_num",
81 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
82 {"mac_rx_pfc_pri2_pkt_num",
83 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
84 {"mac_rx_pfc_pri3_pkt_num",
85 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
86 {"mac_rx_pfc_pri4_pkt_num",
87 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
88 {"mac_rx_pfc_pri5_pkt_num",
89 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
90 {"mac_rx_pfc_pri6_pkt_num",
91 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
92 {"mac_rx_pfc_pri7_pkt_num",
93 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
94 {"mac_tx_total_pkt_num",
95 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
96 {"mac_tx_total_oct_num",
97 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
98 {"mac_tx_good_pkt_num",
99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
100 {"mac_tx_bad_pkt_num",
101 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
102 {"mac_tx_good_oct_num",
103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
104 {"mac_tx_bad_oct_num",
105 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
106 {"mac_tx_uni_pkt_num",
107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
108 {"mac_tx_multi_pkt_num",
109 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
110 {"mac_tx_broad_pkt_num",
111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
112 {"mac_tx_undersize_pkt_num",
113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
200a88c6
JS		 114 {"mac_tx_oversize_pkt_num",
115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 116 {"mac_tx_64_oct_pkt_num",
117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
118 {"mac_tx_65_127_oct_pkt_num",
119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
120 {"mac_tx_128_255_oct_pkt_num",
121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
122 {"mac_tx_256_511_oct_pkt_num",
123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
124 {"mac_tx_512_1023_oct_pkt_num",
125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
126 {"mac_tx_1024_1518_oct_pkt_num",
127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
91f384f6
JS		 128 {"mac_tx_1519_2047_oct_pkt_num",
129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
130 {"mac_tx_2048_4095_oct_pkt_num",
131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
132 {"mac_tx_4096_8191_oct_pkt_num",
133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
91f384f6
JS		 134 {"mac_tx_8192_9216_oct_pkt_num",
135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
136 {"mac_tx_9217_12287_oct_pkt_num",
137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
138 {"mac_tx_12288_16383_oct_pkt_num",
139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
140 {"mac_tx_1519_max_good_pkt_num",
141 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
142 {"mac_tx_1519_max_bad_pkt_num",
143 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 144 {"mac_rx_total_pkt_num",
145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
146 {"mac_rx_total_oct_num",
147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
148 {"mac_rx_good_pkt_num",
149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
150 {"mac_rx_bad_pkt_num",
151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
152 {"mac_rx_good_oct_num",
153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
154 {"mac_rx_bad_oct_num",
155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
156 {"mac_rx_uni_pkt_num",
157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
158 {"mac_rx_multi_pkt_num",
159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
160 {"mac_rx_broad_pkt_num",
161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
162 {"mac_rx_undersize_pkt_num",
163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
200a88c6
JS		 164 {"mac_rx_oversize_pkt_num",
165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 166 {"mac_rx_64_oct_pkt_num",
167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
168 {"mac_rx_65_127_oct_pkt_num",
169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
170 {"mac_rx_128_255_oct_pkt_num",
171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
172 {"mac_rx_256_511_oct_pkt_num",
173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
174 {"mac_rx_512_1023_oct_pkt_num",
175 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
176 {"mac_rx_1024_1518_oct_pkt_num",
177 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
91f384f6
JS		 178 {"mac_rx_1519_2047_oct_pkt_num",
179 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
180 {"mac_rx_2048_4095_oct_pkt_num",
181 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
182 {"mac_rx_4096_8191_oct_pkt_num",
183 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
91f384f6
JS		 184 {"mac_rx_8192_9216_oct_pkt_num",
185 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
186 {"mac_rx_9217_12287_oct_pkt_num",
187 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
188 {"mac_rx_12288_16383_oct_pkt_num",
189 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
190 {"mac_rx_1519_max_good_pkt_num",
191 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
192 {"mac_rx_1519_max_bad_pkt_num",
193 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 194
a6c51c26
JS		 195 {"mac_tx_fragment_pkt_num",
196 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
197 {"mac_tx_undermin_pkt_num",
198 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
199 {"mac_tx_jabber_pkt_num",
200 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
201 {"mac_tx_err_all_pkt_num",
202 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
203 {"mac_tx_from_app_good_pkt_num",
204 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
205 {"mac_tx_from_app_bad_pkt_num",
206 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
207 {"mac_rx_fragment_pkt_num",
208 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
209 {"mac_rx_undermin_pkt_num",
210 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
211 {"mac_rx_jabber_pkt_num",
212 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
213 {"mac_rx_fcs_err_pkt_num",
214 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
215 {"mac_rx_send_app_good_pkt_num",
216 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
217 {"mac_rx_send_app_bad_pkt_num",
218 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 219};
220
f5aac71c
FL		 221static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
222 {
223 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
224 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
225 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
226 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
227 .i_port_bitmap = 0x1,
228 },
229};
230
46a3df9f
S		 231static int hclge_mac_update_stats(struct hclge_dev *hdev)
232{
91f384f6 233#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 234#define HCLGE_RTN_DATA_NUM 4
235
236 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
237 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 238 __le64 *desc_data;
46a3df9f
S		 239 int i, k, n;
240 int ret;
241
242 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
243 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
244 if (ret) {
245 dev_err(&hdev->pdev->dev,
246 "Get MAC pkt stats fail, status = %d.\n", ret);
247
248 return ret;
249 }
250
251 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
252 if (unlikely(i == 0)) {
a90bb9a5 253 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 254 n = HCLGE_RTN_DATA_NUM - 2;
255 } else {
a90bb9a5 256 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 257 n = HCLGE_RTN_DATA_NUM;
258 }
259 for (k = 0; k < n; k++) {
a90bb9a5 260 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 261 desc_data++;
262 }
263 }
264
265 return 0;
266}
267
268static int hclge_tqps_update_stats(struct hnae3_handle *handle)
269{
270 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
271 struct hclge_vport *vport = hclge_get_vport(handle);
272 struct hclge_dev *hdev = vport->back;
273 struct hnae3_queue *queue;
274 struct hclge_desc desc[1];
275 struct hclge_tqp *tqp;
276 int ret, i;
277
278 for (i = 0; i < kinfo->num_tqps; i++) {
279 queue = handle->kinfo.tqp[i];
280 tqp = container_of(queue, struct hclge_tqp, q);
281 /* command : HCLGE_OPC_QUERY_IGU_STAT */
282 hclge_cmd_setup_basic_desc(&desc[0],
283 HCLGE_OPC_QUERY_RX_STATUS,
284 true);
285
a90bb9a5 286 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 287 ret = hclge_cmd_send(&hdev->hw, desc, 1);
288 if (ret) {
289 dev_err(&hdev->pdev->dev,
290 "Query tqp stat fail, status = %d,queue = %d\n",
291 ret, i);
292 return ret;
293 }
294 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cf72fa63 295 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 296 }
297
298 for (i = 0; i < kinfo->num_tqps; i++) {
299 queue = handle->kinfo.tqp[i];
300 tqp = container_of(queue, struct hclge_tqp, q);
301 /* command : HCLGE_OPC_QUERY_IGU_STAT */
302 hclge_cmd_setup_basic_desc(&desc[0],
303 HCLGE_OPC_QUERY_TX_STATUS,
304 true);
305
a90bb9a5 306 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 307 ret = hclge_cmd_send(&hdev->hw, desc, 1);
308 if (ret) {
309 dev_err(&hdev->pdev->dev,
310 "Query tqp stat fail, status = %d,queue = %d\n",
311 ret, i);
312 return ret;
313 }
314 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cf72fa63 315 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 316 }
317
318 return 0;
319}
320
321static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
322{
323 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
324 struct hclge_tqp *tqp;
325 u64 *buff = data;
326 int i;
327
328 for (i = 0; i < kinfo->num_tqps; i++) {
329 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 330 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 331 }
332
333 for (i = 0; i < kinfo->num_tqps; i++) {
334 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 335 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 336 }
337
338 return buff;
339}
340
341static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
342{
343 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
344
345 return kinfo->num_tqps * (2);
346}
347
348static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
349{
350 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
351 u8 *buff = data;
352 int i = 0;
353
354 for (i = 0; i < kinfo->num_tqps; i++) {
355 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
356 struct hclge_tqp, q);
a6c51c26 357 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 358 tqp->index);
359 buff = buff + ETH_GSTRING_LEN;
360 }
361
362 for (i = 0; i < kinfo->num_tqps; i++) {
363 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
364 struct hclge_tqp, q);
a6c51c26 365 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 366 tqp->index);
367 buff = buff + ETH_GSTRING_LEN;
368 }
369
370 return buff;
371}
372
373static u64 *hclge_comm_get_stats(void *comm_stats,
374 const struct hclge_comm_stats_str strs[],
375 int size, u64 *data)
376{
377 u64 *buf = data;
378 u32 i;
379
380 for (i = 0; i < size; i++)
381 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
382
383 return buf + size;
384}
385
386static u8 *hclge_comm_get_strings(u32 stringset,
387 const struct hclge_comm_stats_str strs[],
388 int size, u8 *data)
389{
390 char *buff = (char *)data;
391 u32 i;
392
393 if (stringset != ETH_SS_STATS)
394 return buff;
395
396 for (i = 0; i < size; i++) {
397 snprintf(buff, ETH_GSTRING_LEN,
398 strs[i].desc);
399 buff = buff + ETH_GSTRING_LEN;
400 }
401
402 return (u8 *)buff;
403}
404
405static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
406 struct net_device_stats *net_stats)
407{
408 net_stats->tx_dropped = 0;
200a88c6 409 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 410 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
a6c51c26 411 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 412
413 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
414 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
415
a6c51c26 416 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 417 net_stats->rx_length_errors =
418 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
419 net_stats->rx_length_errors +=
200a88c6 420 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 421 net_stats->rx_over_errors =
200a88c6 422 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 423}
424
425static void hclge_update_stats_for_all(struct hclge_dev *hdev)
426{
427 struct hnae3_handle *handle;
428 int status;
429
430 handle = &hdev->vport[0].nic;
431 if (handle->client) {
432 status = hclge_tqps_update_stats(handle);
433 if (status) {
434 dev_err(&hdev->pdev->dev,
435 "Update TQPS stats fail, status = %d.\n",
436 status);
437 }
438 }
439
440 status = hclge_mac_update_stats(hdev);
441 if (status)
442 dev_err(&hdev->pdev->dev,
443 "Update MAC stats fail, status = %d.\n", status);
444
46a3df9f
S		 445 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
446}
447
448static void hclge_update_stats(struct hnae3_handle *handle,
449 struct net_device_stats *net_stats)
450{
451 struct hclge_vport *vport = hclge_get_vport(handle);
452 struct hclge_dev *hdev = vport->back;
453 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
454 int status;
455
c5f65480
JS		 456 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
457 return;
458
46a3df9f
S		 459 status = hclge_mac_update_stats(hdev);
460 if (status)
461 dev_err(&hdev->pdev->dev,
462 "Update MAC stats fail, status = %d.\n",
463 status);
464
46a3df9f
S		 465 status = hclge_tqps_update_stats(handle);
466 if (status)
467 dev_err(&hdev->pdev->dev,
468 "Update TQPS stats fail, status = %d.\n",
469 status);
470
471 hclge_update_netstat(hw_stats, net_stats);
c5f65480
JS		 472
473 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 474}
475
476static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
477{
478#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
479
480 struct hclge_vport *vport = hclge_get_vport(handle);
481 struct hclge_dev *hdev = vport->back;
482 int count = 0;
483
484 /* Loopback test support rules:
485 * mac: only GE mode support
486 * serdes: all mac mode will support include GE/XGE/LGE/CGE
487 * phy: only support when phy device exist on board
488 */
489 if (stringset == ETH_SS_TEST) {
490 /* clear loopback bit flags at first */
491 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
492 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
493 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
494 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
495 count += 1;
496 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
46a3df9f 497 }
5fd50ac3
PL		 498
499 count++;
500 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
46a3df9f
S		 501 } else if (stringset == ETH_SS_STATS) {
502 count = ARRAY_SIZE(g_mac_stats_string) +
46a3df9f
S		 503 hclge_tqps_get_sset_count(handle, stringset);
504 }
505
506 return count;
507}
508
509static void hclge_get_strings(struct hnae3_handle *handle,
510 u32 stringset,
511 u8 *data)
512{
513 u8 *p = (char *)data;
514 int size;
515
516 if (stringset == ETH_SS_STATS) {
517 size = ARRAY_SIZE(g_mac_stats_string);
518 p = hclge_comm_get_strings(stringset,
519 g_mac_stats_string,
520 size,
521 p);
46a3df9f
S		 522 p = hclge_tqps_get_strings(handle, p);
523 } else if (stringset == ETH_SS_TEST) {
524 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
525 memcpy(p,
526 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
527 ETH_GSTRING_LEN);
528 p += ETH_GSTRING_LEN;
529 }
530 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
531 memcpy(p,
532 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
533 ETH_GSTRING_LEN);
534 p += ETH_GSTRING_LEN;
535 }
536 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
537 memcpy(p,
538 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
539 ETH_GSTRING_LEN);
540 p += ETH_GSTRING_LEN;
541 }
542 }
543}
544
545static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
546{
547 struct hclge_vport *vport = hclge_get_vport(handle);
548 struct hclge_dev *hdev = vport->back;
549 u64 *p;
550
551 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
552 g_mac_stats_string,
553 ARRAY_SIZE(g_mac_stats_string),
554 data);
46a3df9f
S		 555 p = hclge_tqps_get_stats(handle, p);
556}
557
558static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 559 struct hclge_func_status_cmd *status)
46a3df9f
S		 560{
561 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
562 return -EINVAL;
563
564 /* Set the pf to main pf */
565 if (status->pf_state & HCLGE_PF_STATE_MAIN)
566 hdev->flag |= HCLGE_FLAG_MAIN;
567 else
568 hdev->flag &= ~HCLGE_FLAG_MAIN;
569
46a3df9f
S		 570 return 0;
571}
572
573static int hclge_query_function_status(struct hclge_dev *hdev)
574{
d44f9b63 575 struct hclge_func_status_cmd *req;
46a3df9f
S		 576 struct hclge_desc desc;
577 int timeout = 0;
578 int ret;
579
580 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 581 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 582
583 do {
584 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
585 if (ret) {
586 dev_err(&hdev->pdev->dev,
587 "query function status failed %d.\n",
588 ret);
589
590 return ret;
591 }
592
593 /* Check pf reset is done */
594 if (req->pf_state)
595 break;
596 usleep_range(1000, 2000);
597 } while (timeout++ < 5);
598
599 ret = hclge_parse_func_status(hdev, req);
600
601 return ret;
602}
603
604static int hclge_query_pf_resource(struct hclge_dev *hdev)
605{
d44f9b63 606 struct hclge_pf_res_cmd *req;
46a3df9f
S		 607 struct hclge_desc desc;
608 int ret;
609
610 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
611 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
612 if (ret) {
613 dev_err(&hdev->pdev->dev,
614 "query pf resource failed %d.\n", ret);
615 return ret;
616 }
617
d44f9b63 618 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 619 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
620 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
621
e92a0843 622 if (hnae3_dev_roce_supported(hdev)) {
375dd5e4
JS		 623 hdev->roce_base_msix_offset =
624 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
625 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
887c3820 626 hdev->num_roce_msi =
e4e87715
PL		 627 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
628 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 629
630 /* PF should have NIC vectors and Roce vectors,
631 * NIC vectors are queued before Roce vectors.
632 */
375dd5e4
JS		 633 hdev->num_msi = hdev->num_roce_msi +
634 hdev->roce_base_msix_offset;
46a3df9f
S		 635 } else {
636 hdev->num_msi =
e4e87715
PL		 637 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
638 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 639 }
640
641 return 0;
642}
643
644static int hclge_parse_speed(int speed_cmd, int *speed)
645{
646 switch (speed_cmd) {
647 case 6:
648 *speed = HCLGE_MAC_SPEED_10M;
649 break;
650 case 7:
651 *speed = HCLGE_MAC_SPEED_100M;
652 break;
653 case 0:
654 *speed = HCLGE_MAC_SPEED_1G;
655 break;
656 case 1:
657 *speed = HCLGE_MAC_SPEED_10G;
658 break;
659 case 2:
660 *speed = HCLGE_MAC_SPEED_25G;
661 break;
662 case 3:
663 *speed = HCLGE_MAC_SPEED_40G;
664 break;
665 case 4:
666 *speed = HCLGE_MAC_SPEED_50G;
667 break;
668 case 5:
669 *speed = HCLGE_MAC_SPEED_100G;
670 break;
671 default:
672 return -EINVAL;
673 }
674
675 return 0;
676}
677
0979aa0b
FL		 678static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
679 u8 speed_ability)
680{
681 unsigned long *supported = hdev->hw.mac.supported;
682
683 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
684 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
685 supported);
686
687 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
688 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
689 supported);
690
691 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
692 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
693 supported);
694
695 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
696 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
697 supported);
698
699 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
700 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
701 supported);
702
703 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
704 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
705}
706
707static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
708{
709 u8 media_type = hdev->hw.mac.media_type;
710
711 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
712 return;
713
714 hclge_parse_fiber_link_mode(hdev, speed_ability);
715}
716
46a3df9f
S		 717static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
718{
d44f9b63 719 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 720 u64 mac_addr_tmp_high;
721 u64 mac_addr_tmp;
722 int i;
723
d44f9b63 724 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 725
726 /* get the configuration */
e4e87715
PL		 727 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
728 HCLGE_CFG_VMDQ_M,
729 HCLGE_CFG_VMDQ_S);
730 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
731 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
732 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
733 HCLGE_CFG_TQP_DESC_N_M,
734 HCLGE_CFG_TQP_DESC_N_S);
735
736 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
737 HCLGE_CFG_PHY_ADDR_M,
738 HCLGE_CFG_PHY_ADDR_S);
739 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
740 HCLGE_CFG_MEDIA_TP_M,
741 HCLGE_CFG_MEDIA_TP_S);
742 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
743 HCLGE_CFG_RX_BUF_LEN_M,
744 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 745 /* get mac_address */
746 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e4e87715
PL		 747 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
748 HCLGE_CFG_MAC_ADDR_H_M,
749 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 750
751 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
752
e4e87715
PL		 753 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
754 HCLGE_CFG_DEFAULT_SPEED_M,
755 HCLGE_CFG_DEFAULT_SPEED_S);
756 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
757 HCLGE_CFG_RSS_SIZE_M,
758 HCLGE_CFG_RSS_SIZE_S);
0e7a40cd 759
46a3df9f
S		 760 for (i = 0; i < ETH_ALEN; i++)
761 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
762
d44f9b63 763 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 764 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
0979aa0b 765
e4e87715
PL		 766 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
767 HCLGE_CFG_SPEED_ABILITY_M,
768 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 769}
770
771/* hclge_get_cfg: query the static parameter from flash
772 * @hdev: pointer to struct hclge_dev
773 * @hcfg: the config structure to be getted
774 */
775static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
776{
777 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 778 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 779 int i, ret;
780
781 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 782 u32 offset = 0;
783
d44f9b63 784 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 785 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
786 true);
e4e87715
PL		 787 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
788 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 789 /* Len should be united by 4 bytes when send to hardware */
e4e87715
PL		 790 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
791 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 792 req->offset = cpu_to_le32(offset);
46a3df9f
S		 793 }
794
795 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
796 if (ret) {
3f639907 797 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 798 return ret;
799 }
800
801 hclge_parse_cfg(hcfg, desc);
3f639907 802
46a3df9f
S		 803 return 0;
804}
805
806static int hclge_get_cap(struct hclge_dev *hdev)
807{
808 int ret;
809
810 ret = hclge_query_function_status(hdev);
811 if (ret) {
812 dev_err(&hdev->pdev->dev,
813 "query function status error %d.\n", ret);
814 return ret;
815 }
816
817 /* get pf resource */
818 ret = hclge_query_pf_resource(hdev);
3f639907
JS		 819 if (ret)
820 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 821
3f639907 822 return ret;
46a3df9f
S		 823}
824
825static int hclge_configure(struct hclge_dev *hdev)
826{
827 struct hclge_cfg cfg;
828 int ret, i;
829
830 ret = hclge_get_cfg(hdev, &cfg);
831 if (ret) {
832 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
833 return ret;
834 }
835
836 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
837 hdev->base_tqp_pid = 0;
0e7a40cd 838 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 839 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 840 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 841 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 842 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 843 hdev->num_desc = cfg.tqp_desc_num;
844 hdev->tm_info.num_pg = 1;
cacde272 845 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 846 hdev->tm_info.hw_pfc_map = 0;
847
848 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
849 if (ret) {
850 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
851 return ret;
852 }
853
0979aa0b
FL		 854 hclge_parse_link_mode(hdev, cfg.speed_ability);
855
cacde272
YL		 856 if ((hdev->tc_max > HNAE3_MAX_TC) ||
857 (hdev->tc_max < 1)) {
46a3df9f 858 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 859 hdev->tc_max);
860 hdev->tc_max = 1;
46a3df9f
S		 861 }
862
cacde272
YL		 863 /* Dev does not support DCB */
864 if (!hnae3_dev_dcb_supported(hdev)) {
865 hdev->tc_max = 1;
866 hdev->pfc_max = 0;
867 } else {
868 hdev->pfc_max = hdev->tc_max;
869 }
870
871 hdev->tm_info.num_tc = hdev->tc_max;
872
46a3df9f 873 /* Currently not support uncontiuous tc */
cacde272 874 for (i = 0; i < hdev->tm_info.num_tc; i++)
e4e87715 875 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 876
71b83869 877 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 878
879 return ret;
880}
881
882static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
883 int tso_mss_max)
884{
d44f9b63 885 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 886 struct hclge_desc desc;
a90bb9a5 887 u16 tso_mss;
46a3df9f
S		 888
889 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
890
d44f9b63 891 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 892
893 tso_mss = 0;
e4e87715
PL		 894 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
895 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 896 req->tso_mss_min = cpu_to_le16(tso_mss);
897
898 tso_mss = 0;
e4e87715
PL		 899 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
900 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 901 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 902
903 return hclge_cmd_send(&hdev->hw, &desc, 1);
904}
905
906static int hclge_alloc_tqps(struct hclge_dev *hdev)
907{
908 struct hclge_tqp *tqp;
909 int i;
910
911 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
912 sizeof(struct hclge_tqp), GFP_KERNEL);
913 if (!hdev->htqp)
914 return -ENOMEM;
915
916 tqp = hdev->htqp;
917
918 for (i = 0; i < hdev->num_tqps; i++) {
919 tqp->dev = &hdev->pdev->dev;
920 tqp->index = i;
921
922 tqp->q.ae_algo = &ae_algo;
923 tqp->q.buf_size = hdev->rx_buf_len;
924 tqp->q.desc_num = hdev->num_desc;
925 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
926 i * HCLGE_TQP_REG_SIZE;
927
928 tqp++;
929 }
930
931 return 0;
932}
933
934static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
935 u16 tqp_pid, u16 tqp_vid, bool is_pf)
936{
d44f9b63 937 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 938 struct hclge_desc desc;
939 int ret;
940
941 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
942
d44f9b63 943 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 944 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 945 req->tqp_vf = func_id;
46a3df9f
S		 946 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
947 1 << HCLGE_TQP_MAP_EN_B;
948 req->tqp_vid = cpu_to_le16(tqp_vid);
949
950 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907
JS		 951 if (ret)
952 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 953
3f639907 954 return ret;
46a3df9f
S		 955}
956
128b900d 957static int hclge_assign_tqp(struct hclge_vport *vport)
46a3df9f 958{
128b900d 959 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
46a3df9f 960 struct hclge_dev *hdev = vport->back;
7df7dad6 961 int i, alloced;
46a3df9f
S		 962
963 for (i = 0, alloced = 0; i < hdev->num_tqps &&
128b900d 964 alloced < kinfo->num_tqps; i++) {
46a3df9f
S		 965 if (!hdev->htqp[i].alloced) {
966 hdev->htqp[i].q.handle = &vport->nic;
967 hdev->htqp[i].q.tqp_index = alloced;
128b900d
YL		 968 hdev->htqp[i].q.desc_num = kinfo->num_desc;
969 kinfo->tqp[alloced] = &hdev->htqp[i].q;
46a3df9f 970 hdev->htqp[i].alloced = true;
46a3df9f
S		 971 alloced++;
972 }
973 }
128b900d 974 vport->alloc_tqps = kinfo->num_tqps;
46a3df9f
S		 975
976 return 0;
977}
978
128b900d
YL		 979static int hclge_knic_setup(struct hclge_vport *vport,
980 u16 num_tqps, u16 num_desc)
46a3df9f
S		 981{
982 struct hnae3_handle *nic = &vport->nic;
983 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
984 struct hclge_dev *hdev = vport->back;
985 int i, ret;
986
128b900d 987 kinfo->num_desc = num_desc;
46a3df9f
S		 988 kinfo->rx_buf_len = hdev->rx_buf_len;
989 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
990 kinfo->rss_size
991 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
992 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
993
994 for (i = 0; i < HNAE3_MAX_TC; i++) {
995 if (hdev->hw_tc_map & BIT(i)) {
996 kinfo->tc_info[i].enable = true;
997 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
998 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
999 kinfo->tc_info[i].tc = i;
1000 } else {
1001 /* Set to default queue if TC is disable */
1002 kinfo->tc_info[i].enable = false;
1003 kinfo->tc_info[i].tqp_offset = 0;
1004 kinfo->tc_info[i].tqp_count = 1;
1005 kinfo->tc_info[i].tc = 0;
1006 }
1007 }
1008
1009 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1010 sizeof(struct hnae3_queue *), GFP_KERNEL);
1011 if (!kinfo->tqp)
1012 return -ENOMEM;
1013
128b900d 1014 ret = hclge_assign_tqp(vport);
3f639907 1015 if (ret)
46a3df9f 1016 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1017
3f639907 1018 return ret;
46a3df9f
S		 1019}
1020
7df7dad6
L		 1021static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1022 struct hclge_vport *vport)
1023{
1024 struct hnae3_handle *nic = &vport->nic;
1025 struct hnae3_knic_private_info *kinfo;
1026 u16 i;
1027
1028 kinfo = &nic->kinfo;
1029 for (i = 0; i < kinfo->num_tqps; i++) {
1030 struct hclge_tqp *q =
1031 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1032 bool is_pf;
1033 int ret;
1034
1035 is_pf = !(vport->vport_id);
1036 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1037 i, is_pf);
1038 if (ret)
1039 return ret;
1040 }
1041
1042 return 0;
1043}
1044
1045static int hclge_map_tqp(struct hclge_dev *hdev)
1046{
1047 struct hclge_vport *vport = hdev->vport;
1048 u16 i, num_vport;
1049
1050 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1051 for (i = 0; i < num_vport; i++) {
1052 int ret;
1053
1054 ret = hclge_map_tqp_to_vport(hdev, vport);
1055 if (ret)
1056 return ret;
1057
1058 vport++;
1059 }
1060
1061 return 0;
1062}
1063
46a3df9f
S		 1064static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1065{
1066 /* this would be initialized later */
1067}
1068
1069static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1070{
1071 struct hnae3_handle *nic = &vport->nic;
1072 struct hclge_dev *hdev = vport->back;
1073 int ret;
1074
1075 nic->pdev = hdev->pdev;
1076 nic->ae_algo = &ae_algo;
1077 nic->numa_node_mask = hdev->numa_node_mask;
1078
1079 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
128b900d 1080 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
46a3df9f
S		 1081 if (ret) {
1082 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1083 ret);
1084 return ret;
1085 }
1086 } else {
1087 hclge_unic_setup(vport, num_tqps);
1088 }
1089
1090 return 0;
1091}
1092
1093static int hclge_alloc_vport(struct hclge_dev *hdev)
1094{
1095 struct pci_dev *pdev = hdev->pdev;
1096 struct hclge_vport *vport;
1097 u32 tqp_main_vport;
1098 u32 tqp_per_vport;
1099 int num_vport, i;
1100 int ret;
1101
1102 /* We need to alloc a vport for main NIC of PF */
1103 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1104
38e62046
HT		 1105 if (hdev->num_tqps < num_vport) {
1106 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1107 hdev->num_tqps, num_vport);
1108 return -EINVAL;
1109 }
46a3df9f
S		 1110
1111 /* Alloc the same number of TQPs for every vport */
1112 tqp_per_vport = hdev->num_tqps / num_vport;
1113 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1114
1115 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1116 GFP_KERNEL);
1117 if (!vport)
1118 return -ENOMEM;
1119
1120 hdev->vport = vport;
1121 hdev->num_alloc_vport = num_vport;
1122
2312e050
FL		 1123 if (IS_ENABLED(CONFIG_PCI_IOV))
1124 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1125
1126 for (i = 0; i < num_vport; i++) {
1127 vport->back = hdev;
1128 vport->vport_id = i;
1129
1130 if (i == 0)
1131 ret = hclge_vport_setup(vport, tqp_main_vport);
1132 else
1133 ret = hclge_vport_setup(vport, tqp_per_vport);
1134 if (ret) {
1135 dev_err(&pdev->dev,
1136 "vport setup failed for vport %d, %d\n",
1137 i, ret);
1138 return ret;
1139 }
1140
1141 vport++;
1142 }
1143
1144 return 0;
1145}
1146
acf61ecd
YL		 1147static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1148 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1149{
1150/* TX buffer size is unit by 128 byte */
1151#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1152#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1153 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1154 struct hclge_desc desc;
1155 int ret;
1156 u8 i;
1157
d44f9b63 1158 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1159
1160 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1161 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1162 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1163
46a3df9f
S		 1164 req->tx_pkt_buff[i] =
1165 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1166 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1167 }
46a3df9f
S		 1168
1169 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1170 if (ret)
46a3df9f
S		 1171 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1172 ret);
46a3df9f 1173
3f639907 1174 return ret;
46a3df9f
S		 1175}
1176
acf61ecd
YL		 1177static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1178 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1179{
acf61ecd 1180 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1181
3f639907
JS		 1182 if (ret)
1183 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1184
3f639907 1185 return ret;
46a3df9f
S		 1186}
1187
1188static int hclge_get_tc_num(struct hclge_dev *hdev)
1189{
1190 int i, cnt = 0;
1191
1192 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1193 if (hdev->hw_tc_map & BIT(i))
1194 cnt++;
1195 return cnt;
1196}
1197
1198static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1199{
1200 int i, cnt = 0;
1201
1202 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1203 if (hdev->hw_tc_map & BIT(i) &&
1204 hdev->tm_info.hw_pfc_map & BIT(i))
1205 cnt++;
1206 return cnt;
1207}
1208
1209/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1210static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1211 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1212{
1213 struct hclge_priv_buf *priv;
1214 int i, cnt = 0;
1215
1216 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1217 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1218 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1219 priv->enable)
1220 cnt++;
1221 }
1222
1223 return cnt;
1224}
1225
1226/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1227static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1228 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1229{
1230 struct hclge_priv_buf *priv;
1231 int i, cnt = 0;
1232
1233 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1234 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1235 if (hdev->hw_tc_map & BIT(i) &&
1236 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1237 priv->enable)
1238 cnt++;
1239 }
1240
1241 return cnt;
1242}
1243
acf61ecd 1244static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1245{
1246 struct hclge_priv_buf *priv;
1247 u32 rx_priv = 0;
1248 int i;
1249
1250 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1251 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1252 if (priv->enable)
1253 rx_priv += priv->buf_size;
1254 }
1255 return rx_priv;
1256}
1257
acf61ecd 1258static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1259{
1260 u32 i, total_tx_size = 0;
1261
1262 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1263 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1264
1265 return total_tx_size;
1266}
1267
acf61ecd
YL		 1268static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1269 struct hclge_pkt_buf_alloc *buf_alloc,
1270 u32 rx_all)
46a3df9f
S		 1271{
1272 u32 shared_buf_min, shared_buf_tc, shared_std;
1273 int tc_num, pfc_enable_num;
1274 u32 shared_buf;
1275 u32 rx_priv;
1276 int i;
1277
1278 tc_num = hclge_get_tc_num(hdev);
1279 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1280
d221df4e
YL		 1281 if (hnae3_dev_dcb_supported(hdev))
1282 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1283 else
1284 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1285
46a3df9f
S		 1286 shared_buf_tc = pfc_enable_num * hdev->mps +
1287 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1288 hdev->mps;
1289 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1290
acf61ecd 1291 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1292 if (rx_all <= rx_priv + shared_std)
1293 return false;
1294
1295 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1296 buf_alloc->s_buf.buf_size = shared_buf;
1297 buf_alloc->s_buf.self.high = shared_buf;
1298 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1299
1300 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1301 if ((hdev->hw_tc_map & BIT(i)) &&
1302 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1303 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1304 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1305 } else {
acf61ecd
YL		 1306 buf_alloc->s_buf.tc_thrd[i].low = 0;
1307 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1308 }
1309 }
1310
1311 return true;
1312}
1313
acf61ecd
YL		 1314static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1315 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1316{
1317 u32 i, total_size;
1318
1319 total_size = hdev->pkt_buf_size;
1320
1321 /* alloc tx buffer for all enabled tc */
1322 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1323 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1324
1325 if (total_size < HCLGE_DEFAULT_TX_BUF)
1326 return -ENOMEM;
1327
1328 if (hdev->hw_tc_map & BIT(i))
1329 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1330 else
1331 priv->tx_buf_size = 0;
1332
1333 total_size -= priv->tx_buf_size;
1334 }
1335
1336 return 0;
1337}
1338
46a3df9f
S		 1339/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1340 * @hdev: pointer to struct hclge_dev
acf61ecd 1341 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1342 * @return: 0: calculate sucessful, negative: fail
1343 */
1db9b1bf
YL		 1344static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1345 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1346{
9ffe79a9 1347 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1348 int no_pfc_priv_num, pfc_priv_num;
1349 struct hclge_priv_buf *priv;
1350 int i;
1351
acf61ecd 1352 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1353
d602a525
YL		 1354 /* When DCB is not supported, rx private
1355 * buffer is not allocated.
1356 */
1357 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1358 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1359 return -ENOMEM;
1360
1361 return 0;
1362 }
1363
46a3df9f
S		 1364 /* step 1, try to alloc private buffer for all enabled tc */
1365 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1366 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1367 if (hdev->hw_tc_map & BIT(i)) {
1368 priv->enable = 1;
1369 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1370 priv->wl.low = hdev->mps;
1371 priv->wl.high = priv->wl.low + hdev->mps;
1372 priv->buf_size = priv->wl.high +
1373 HCLGE_DEFAULT_DV;
1374 } else {
1375 priv->wl.low = 0;
1376 priv->wl.high = 2 * hdev->mps;
1377 priv->buf_size = priv->wl.high;
1378 }
bb1fe9ea
YL		 1379 } else {
1380 priv->enable = 0;
1381 priv->wl.low = 0;
1382 priv->wl.high = 0;
1383 priv->buf_size = 0;
46a3df9f
S		 1384 }
1385 }
1386
acf61ecd 1387 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1388 return 0;
1389
1390 /* step 2, try to decrease the buffer size of
1391 * no pfc TC's private buffer
1392 */
1393 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1394 priv = &buf_alloc->priv_buf[i];
46a3df9f 1395
bb1fe9ea
YL		 1396 priv->enable = 0;
1397 priv->wl.low = 0;
1398 priv->wl.high = 0;
1399 priv->buf_size = 0;
1400
1401 if (!(hdev->hw_tc_map & BIT(i)))
1402 continue;
1403
1404 priv->enable = 1;
46a3df9f
S		 1405
1406 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1407 priv->wl.low = 128;
1408 priv->wl.high = priv->wl.low + hdev->mps;
1409 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1410 } else {
1411 priv->wl.low = 0;
1412 priv->wl.high = hdev->mps;
1413 priv->buf_size = priv->wl.high;
1414 }
1415 }
1416
acf61ecd 1417 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1418 return 0;
1419
1420 /* step 3, try to reduce the number of pfc disabled TCs,
1421 * which have private buffer
1422 */
1423 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1424 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1425
1426 /* let the last to be cleared first */
1427 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1428 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1429
1430 if (hdev->hw_tc_map & BIT(i) &&
1431 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1432 /* Clear the no pfc TC private buffer */
1433 priv->wl.low = 0;
1434 priv->wl.high = 0;
1435 priv->buf_size = 0;
1436 priv->enable = 0;
1437 no_pfc_priv_num--;
1438 }
1439
acf61ecd 1440 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1441 no_pfc_priv_num == 0)
1442 break;
1443 }
1444
acf61ecd 1445 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1446 return 0;
1447
1448 /* step 4, try to reduce the number of pfc enabled TCs
1449 * which have private buffer.
1450 */
acf61ecd 1451 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1452
1453 /* let the last to be cleared first */
1454 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1455 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1456
1457 if (hdev->hw_tc_map & BIT(i) &&
1458 hdev->tm_info.hw_pfc_map & BIT(i)) {
1459 /* Reduce the number of pfc TC with private buffer */
1460 priv->wl.low = 0;
1461 priv->enable = 0;
1462 priv->wl.high = 0;
1463 priv->buf_size = 0;
1464 pfc_priv_num--;
1465 }
1466
acf61ecd 1467 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1468 pfc_priv_num == 0)
1469 break;
1470 }
acf61ecd 1471 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1472 return 0;
1473
1474 return -ENOMEM;
1475}
1476
acf61ecd
YL		 1477static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1478 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1479{
d44f9b63 1480 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1481 struct hclge_desc desc;
1482 int ret;
1483 int i;
1484
1485 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1486 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1487
1488 /* Alloc private buffer TCs */
1489 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1490 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1491
1492 req->buf_num[i] =
1493 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1494 req->buf_num[i] |=
5bca3b94 1495 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1496 }
1497
b8c8bf47 1498 req->shared_buf =
acf61ecd 1499 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1500 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1501
46a3df9f 1502 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1503 if (ret)
46a3df9f
S		 1504 dev_err(&hdev->pdev->dev,
1505 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1506
3f639907 1507 return ret;
46a3df9f
S		 1508}
1509
acf61ecd
YL		 1510static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1511 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1512{
1513 struct hclge_rx_priv_wl_buf *req;
1514 struct hclge_priv_buf *priv;
1515 struct hclge_desc desc[2];
1516 int i, j;
1517 int ret;
1518
1519 for (i = 0; i < 2; i++) {
1520 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1521 false);
1522 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1523
1524 /* The first descriptor set the NEXT bit to 1 */
1525 if (i == 0)
1526 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1527 else
1528 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1529
1530 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1531 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1532
1533 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1534 req->tc_wl[j].high =
1535 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1536 req->tc_wl[j].high |=
3738287c 1537 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1538 req->tc_wl[j].low =
1539 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1540 req->tc_wl[j].low |=
3738287c 1541 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1542 }
1543 }
1544
1545 /* Send 2 descriptor at one time */
1546 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1547 if (ret)
46a3df9f
S		 1548 dev_err(&hdev->pdev->dev,
1549 "rx private waterline config cmd failed %d\n",
1550 ret);
3f639907 1551 return ret;
46a3df9f
S		 1552}
1553
acf61ecd
YL		 1554static int hclge_common_thrd_config(struct hclge_dev *hdev,
1555 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1556{
acf61ecd 1557 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1558 struct hclge_rx_com_thrd *req;
1559 struct hclge_desc desc[2];
1560 struct hclge_tc_thrd *tc;
1561 int i, j;
1562 int ret;
1563
1564 for (i = 0; i < 2; i++) {
1565 hclge_cmd_setup_basic_desc(&desc[i],
1566 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1567 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1568
1569 /* The first descriptor set the NEXT bit to 1 */
1570 if (i == 0)
1571 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1572 else
1573 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1574
1575 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1576 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1577
1578 req->com_thrd[j].high =
1579 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1580 req->com_thrd[j].high |=
3738287c 1581 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1582 req->com_thrd[j].low =
1583 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1584 req->com_thrd[j].low |=
3738287c 1585 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1586 }
1587 }
1588
1589 /* Send 2 descriptors at one time */
1590 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1591 if (ret)
46a3df9f
S		 1592 dev_err(&hdev->pdev->dev,
1593 "common threshold config cmd failed %d\n", ret);
3f639907 1594 return ret;
46a3df9f
S		 1595}
1596
acf61ecd
YL		 1597static int hclge_common_wl_config(struct hclge_dev *hdev,
1598 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1599{
acf61ecd 1600 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1601 struct hclge_rx_com_wl *req;
1602 struct hclge_desc desc;
1603 int ret;
1604
1605 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1606
1607 req = (struct hclge_rx_com_wl *)desc.data;
1608 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
3738287c 1609 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1610
1611 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
3738287c 1612 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1613
1614 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1615 if (ret)
46a3df9f
S		 1616 dev_err(&hdev->pdev->dev,
1617 "common waterline config cmd failed %d\n", ret);
46a3df9f 1618
3f639907 1619 return ret;
46a3df9f
S		 1620}
1621
1622int hclge_buffer_alloc(struct hclge_dev *hdev)
1623{
acf61ecd 1624 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1625 int ret;
1626
acf61ecd
YL		 1627 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1628 if (!pkt_buf)
46a3df9f
S		 1629 return -ENOMEM;
1630
acf61ecd 1631 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1632 if (ret) {
1633 dev_err(&hdev->pdev->dev,
1634 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1635 goto out;
9ffe79a9
YL		 1636 }
1637
acf61ecd 1638 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1639 if (ret) {
1640 dev_err(&hdev->pdev->dev,
1641 "could not alloc tx buffers %d\n", ret);
acf61ecd 1642 goto out;
46a3df9f
S		 1643 }
1644
acf61ecd 1645 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1646 if (ret) {
1647 dev_err(&hdev->pdev->dev,
1648 "could not calc rx priv buffer size for all TCs %d\n",
1649 ret);
acf61ecd 1650 goto out;
46a3df9f
S		 1651 }
1652
acf61ecd 1653 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1654 if (ret) {
1655 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1656 ret);
acf61ecd 1657 goto out;
46a3df9f
S		 1658 }
1659
2daf4a65 1660 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1661 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1662 if (ret) {
1663 dev_err(&hdev->pdev->dev,
1664 "could not configure rx private waterline %d\n",
1665 ret);
acf61ecd 1666 goto out;
2daf4a65 1667 }
46a3df9f 1668
acf61ecd 1669 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1670 if (ret) {
1671 dev_err(&hdev->pdev->dev,
1672 "could not configure common threshold %d\n",
1673 ret);
acf61ecd 1674 goto out;
2daf4a65 1675 }
46a3df9f
S		 1676 }
1677
acf61ecd
YL		 1678 ret = hclge_common_wl_config(hdev, pkt_buf);
1679 if (ret)
46a3df9f
S		 1680 dev_err(&hdev->pdev->dev,
1681 "could not configure common waterline %d\n", ret);
46a3df9f 1682
acf61ecd
YL		 1683out:
1684 kfree(pkt_buf);
1685 return ret;
46a3df9f
S		 1686}
1687
1688static int hclge_init_roce_base_info(struct hclge_vport *vport)
1689{
1690 struct hnae3_handle *roce = &vport->roce;
1691 struct hnae3_handle *nic = &vport->nic;
1692
887c3820 1693 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1694
1695 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1696 vport->back->num_msi_left == 0)
1697 return -EINVAL;
1698
1699 roce->rinfo.base_vector = vport->back->roce_base_vector;
1700
1701 roce->rinfo.netdev = nic->kinfo.netdev;
1702 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1703
1704 roce->pdev = nic->pdev;
1705 roce->ae_algo = nic->ae_algo;
1706 roce->numa_node_mask = nic->numa_node_mask;
1707
1708 return 0;
1709}
1710
887c3820 1711static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1712{
1713 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1714 int vectors;
1715 int i;
46a3df9f 1716
887c3820
SM		 1717 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1718 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1719 if (vectors < 0) {
1720 dev_err(&pdev->dev,
1721 "failed(%d) to allocate MSI/MSI-X vectors\n",
1722 vectors);
1723 return vectors;
46a3df9f 1724 }
887c3820
SM		 1725 if (vectors < hdev->num_msi)
1726 dev_warn(&hdev->pdev->dev,
1727 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1728 hdev->num_msi, vectors);
46a3df9f 1729
887c3820
SM		 1730 hdev->num_msi = vectors;
1731 hdev->num_msi_left = vectors;
1732 hdev->base_msi_vector = pdev->irq;
46a3df9f 1733 hdev->roce_base_vector = hdev->base_msi_vector +
375dd5e4 1734 hdev->roce_base_msix_offset;
46a3df9f 1735
46a3df9f
S		 1736 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1737 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1738 if (!hdev->vector_status) {
1739 pci_free_irq_vectors(pdev);
46a3df9f 1740 return -ENOMEM;
887c3820 1741 }
46a3df9f
S		 1742
1743 for (i = 0; i < hdev->num_msi; i++)
1744 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1745
887c3820
SM		 1746 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1747 sizeof(int), GFP_KERNEL);
1748 if (!hdev->vector_irq) {
1749 pci_free_irq_vectors(pdev);
1750 return -ENOMEM;
46a3df9f 1751 }
46a3df9f
S		 1752
1753 return 0;
1754}
1755
2d03eacc 1756static u8 hclge_check_speed_dup(u8 duplex, int speed)
46a3df9f 1757{
46a3df9f 1758
2d03eacc
YL		 1759 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1760 duplex = HCLGE_MAC_FULL;
46a3df9f 1761
2d03eacc 1762 return duplex;
46a3df9f
S		 1763}
1764
2d03eacc
YL		 1765static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1766 u8 duplex)
46a3df9f 1767{
d44f9b63 1768 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 1769 struct hclge_desc desc;
1770 int ret;
1771
d44f9b63 1772 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 1773
1774 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1775
e4e87715 1776 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 1777
1778 switch (speed) {
1779 case HCLGE_MAC_SPEED_10M:
e4e87715
PL		 1780 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1781 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 1782 break;
1783 case HCLGE_MAC_SPEED_100M:
e4e87715
PL		 1784 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1785 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 1786 break;
1787 case HCLGE_MAC_SPEED_1G:
e4e87715
PL		 1788 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1789 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 1790 break;
1791 case HCLGE_MAC_SPEED_10G:
e4e87715
PL		 1792 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1793 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 1794 break;
1795 case HCLGE_MAC_SPEED_25G:
e4e87715
PL		 1796 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1797 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 1798 break;
1799 case HCLGE_MAC_SPEED_40G:
e4e87715
PL		 1800 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1801 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 1802 break;
1803 case HCLGE_MAC_SPEED_50G:
e4e87715
PL		 1804 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1805 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 1806 break;
1807 case HCLGE_MAC_SPEED_100G:
e4e87715
PL		 1808 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1809 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 1810 break;
1811 default:
d7629e74 1812 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1813 return -EINVAL;
1814 }
1815
e4e87715
PL		 1816 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1817 1);
46a3df9f
S		 1818
1819 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1820 if (ret) {
1821 dev_err(&hdev->pdev->dev,
1822 "mac speed/duplex config cmd failed %d.\n", ret);
1823 return ret;
1824 }
1825
2d03eacc
YL		 1826 return 0;
1827}
1828
1829int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1830{
1831 int ret;
1832
1833 duplex = hclge_check_speed_dup(duplex, speed);
1834 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1835 return 0;
1836
1837 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1838 if (ret)
1839 return ret;
1840
1841 hdev->hw.mac.speed = speed;
1842 hdev->hw.mac.duplex = duplex;
46a3df9f
S		 1843
1844 return 0;
1845}
1846
1847static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1848 u8 duplex)
1849{
1850 struct hclge_vport *vport = hclge_get_vport(handle);
1851 struct hclge_dev *hdev = vport->back;
1852
1853 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1854}
1855
1856static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1857 u8 *duplex)
1858{
d44f9b63 1859 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 1860 struct hclge_desc desc;
1861 int speed_tmp;
1862 int ret;
1863
d44f9b63 1864 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 1865
1866 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1867 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1868 if (ret) {
1869 dev_err(&hdev->pdev->dev,
1870 "mac speed/autoneg/duplex query cmd failed %d\n",
1871 ret);
1872 return ret;
1873 }
1874
e4e87715
PL		 1875 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1876 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1877 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 1878
1879 ret = hclge_parse_speed(speed_tmp, speed);
3f639907 1880 if (ret)
46a3df9f
S		 1881 dev_err(&hdev->pdev->dev,
1882 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 1883
3f639907 1884 return ret;
46a3df9f
S		 1885}
1886
46a3df9f
S		 1887static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1888{
d44f9b63 1889 struct hclge_config_auto_neg_cmd *req;
46a3df9f 1890 struct hclge_desc desc;
a90bb9a5 1891 u32 flag = 0;
46a3df9f
S		 1892 int ret;
1893
1894 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1895
d44f9b63 1896 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e4e87715 1897 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 1898 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 1899
1900 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1901 if (ret)
46a3df9f
S		 1902 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1903 ret);
46a3df9f 1904
3f639907 1905 return ret;
46a3df9f
S		 1906}
1907
1908static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1909{
1910 struct hclge_vport *vport = hclge_get_vport(handle);
1911 struct hclge_dev *hdev = vport->back;
1912
1913 return hclge_set_autoneg_en(hdev, enable);
1914}
1915
1916static int hclge_get_autoneg(struct hnae3_handle *handle)
1917{
1918 struct hclge_vport *vport = hclge_get_vport(handle);
1919 struct hclge_dev *hdev = vport->back;
27b5bf49
FL		 1920 struct phy_device *phydev = hdev->hw.mac.phydev;
1921
1922 if (phydev)
1923 return phydev->autoneg;
46a3df9f
S		 1924
1925 return hdev->hw.mac.autoneg;
1926}
1927
7564094c
PL		 1928static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
1929 bool mask_vlan,
1930 u8 *mac_mask)
1931{
1932 struct hclge_mac_vlan_mask_entry_cmd *req;
1933 struct hclge_desc desc;
1934 int status;
1935
1936 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
1937 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
1938
e4e87715
PL		 1939 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
1940 mask_vlan ? 1 : 0);
7564094c
PL		 1941 ether_addr_copy(req->mac_mask, mac_mask);
1942
1943 status = hclge_cmd_send(&hdev->hw, &desc, 1);
1944 if (status)
1945 dev_err(&hdev->pdev->dev,
1946 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
1947 status);
1948
1949 return status;
1950}
1951
46a3df9f
S		 1952static int hclge_mac_init(struct hclge_dev *hdev)
1953{
f9fd82a9
FL		 1954 struct hnae3_handle *handle = &hdev->vport[0].nic;
1955 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 1956 struct hclge_mac *mac = &hdev->hw.mac;
7564094c 1957 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
40cca1c5 1958 struct hclge_vport *vport;
f9fd82a9 1959 int mtu;
46a3df9f 1960 int ret;
40cca1c5 1961 int i;
46a3df9f 1962
2d03eacc
YL		 1963 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1964 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1965 hdev->hw.mac.duplex);
46a3df9f
S		 1966 if (ret) {
1967 dev_err(&hdev->pdev->dev,
1968 "Config mac speed dup fail ret=%d\n", ret);
1969 return ret;
1970 }
1971
1972 mac->link = 0;
1973
46a3df9f 1974 /* Initialize the MTA table work mode */
46a3df9f
S		 1975 hdev->enable_mta = true;
1976 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
1977
1978 ret = hclge_set_mta_filter_mode(hdev,
1979 hdev->mta_mac_sel_type,
1980 hdev->enable_mta);
1981 if (ret) {
1982 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
1983 ret);
1984 return ret;
1985 }
1986
40cca1c5
XW		 1987 for (i = 0; i < hdev->num_alloc_vport; i++) {
1988 vport = &hdev->vport[i];
1989 vport->accept_mta_mc = false;
1990
1991 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
1992 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
1993 if (ret) {
1994 dev_err(&hdev->pdev->dev,
1995 "set mta filter mode fail ret=%d\n", ret);
1996 return ret;
1997 }
7564094c
PL		 1998 }
1999
2000 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
f9fd82a9 2001 if (ret) {
7564094c
PL		 2002 dev_err(&hdev->pdev->dev,
2003 "set default mac_vlan_mask fail ret=%d\n", ret);
f9fd82a9
FL		 2004 return ret;
2005 }
7564094c 2006
f9fd82a9
FL		 2007 if (netdev)
2008 mtu = netdev->mtu;
2009 else
2010 mtu = ETH_DATA_LEN;
2011
2012 ret = hclge_set_mtu(handle, mtu);
3f639907 2013 if (ret)
f9fd82a9
FL		 2014 dev_err(&hdev->pdev->dev,
2015 "set mtu failed ret=%d\n", ret);
f9fd82a9 2016
3f639907 2017 return ret;
46a3df9f
S		 2018}
2019
c1a81619
SM		 2020static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2021{
2022 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2023 schedule_work(&hdev->mbx_service_task);
2024}
2025
cb1b9f77
SM		 2026static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2027{
2028 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2029 schedule_work(&hdev->rst_service_task);
2030}
2031
46a3df9f
S		 2032static void hclge_task_schedule(struct hclge_dev *hdev)
2033{
2034 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2035 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2036 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2037 (void)schedule_work(&hdev->service_task);
2038}
2039
2040static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2041{
d44f9b63 2042 struct hclge_link_status_cmd *req;
46a3df9f
S		 2043 struct hclge_desc desc;
2044 int link_status;
2045 int ret;
2046
2047 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2048 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2049 if (ret) {
2050 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2051 ret);
2052 return ret;
2053 }
2054
d44f9b63 2055 req = (struct hclge_link_status_cmd *)desc.data;
c79301d8 2056 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2057
2058 return !!link_status;
2059}
2060
2061static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2062{
2063 int mac_state;
2064 int link_stat;
2065
2066 mac_state = hclge_get_mac_link_status(hdev);
2067
2068 if (hdev->hw.mac.phydev) {
2069 if (!genphy_read_status(hdev->hw.mac.phydev))
2070 link_stat = mac_state &
2071 hdev->hw.mac.phydev->link;
2072 else
2073 link_stat = 0;
2074
2075 } else {
2076 link_stat = mac_state;
2077 }
2078
2079 return !!link_stat;
2080}
2081
2082static void hclge_update_link_status(struct hclge_dev *hdev)
2083{
2084 struct hnae3_client *client = hdev->nic_client;
2085 struct hnae3_handle *handle;
2086 int state;
2087 int i;
2088
2089 if (!client)
2090 return;
2091 state = hclge_get_mac_phy_link(hdev);
2092 if (state != hdev->hw.mac.link) {
2093 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2094 handle = &hdev->vport[i].nic;
2095 client->ops->link_status_change(handle, state);
2096 }
2097 hdev->hw.mac.link = state;
2098 }
2099}
2100
2101static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2102{
2103 struct hclge_mac mac = hdev->hw.mac;
2104 u8 duplex;
2105 int speed;
2106 int ret;
2107
2108 /* get the speed and duplex as autoneg'result from mac cmd when phy
2109 * doesn't exit.
2110 */
c040366b 2111 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2112 return 0;
2113
2114 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2115 if (ret) {
2116 dev_err(&hdev->pdev->dev,
2117 "mac autoneg/speed/duplex query failed %d\n", ret);
2118 return ret;
2119 }
2120
2d03eacc
YL		 2121 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2122 if (ret) {
2123 dev_err(&hdev->pdev->dev,
2124 "mac speed/duplex config failed %d\n", ret);
2125 return ret;
46a3df9f
S		 2126 }
2127
2128 return 0;
2129}
2130
2131static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2132{
2133 struct hclge_vport *vport = hclge_get_vport(handle);
2134 struct hclge_dev *hdev = vport->back;
2135
2136 return hclge_update_speed_duplex(hdev);
2137}
2138
2139static int hclge_get_status(struct hnae3_handle *handle)
2140{
2141 struct hclge_vport *vport = hclge_get_vport(handle);
2142 struct hclge_dev *hdev = vport->back;
2143
2144 hclge_update_link_status(hdev);
2145
2146 return hdev->hw.mac.link;
2147}
2148
d039ef68 2149static void hclge_service_timer(struct timer_list *t)
46a3df9f 2150{
d039ef68 2151 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2152
d039ef68 2153 mod_timer(&hdev->service_timer, jiffies + HZ);
c5f65480 2154 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2155 hclge_task_schedule(hdev);
2156}
2157
2158static void hclge_service_complete(struct hclge_dev *hdev)
2159{
2160 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2161
2162 /* Flush memory before next watchdog */
2163 smp_mb__before_atomic();
2164 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2165}
2166
ca1d7669
SM		 2167static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2168{
2169 u32 rst_src_reg;
c1a81619 2170 u32 cmdq_src_reg;
ca1d7669
SM		 2171
2172 /* fetch the events from their corresponding regs */
9ca8d1a7 2173 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
c1a81619
SM		 2174 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2175
2176 /* Assumption: If by any chance reset and mailbox events are reported
2177 * together then we will only process reset event in this go and will
2178 * defer the processing of the mailbox events. Since, we would have not
2179 * cleared RX CMDQ event this time we would receive again another
2180 * interrupt from H/W just for the mailbox.
2181 */
ca1d7669
SM		 2182
2183 /* check for vector0 reset event sources */
2184 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
8d40854f 2185 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2186 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2187 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2188 return HCLGE_VECTOR0_EVENT_RST;
2189 }
2190
2191 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
8d40854f 2192 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2193 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2194 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2195 return HCLGE_VECTOR0_EVENT_RST;
2196 }
2197
2198 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2199 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2200 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2201 return HCLGE_VECTOR0_EVENT_RST;
2202 }
2203
c1a81619
SM		 2204 /* check for vector0 mailbox(=CMDQ RX) event source */
2205 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2206 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2207 *clearval = cmdq_src_reg;
2208 return HCLGE_VECTOR0_EVENT_MBX;
2209 }
ca1d7669
SM		 2210
2211 return HCLGE_VECTOR0_EVENT_OTHER;
2212}
2213
2214static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2215 u32 regclr)
2216{
c1a81619
SM		 2217 switch (event_type) {
2218 case HCLGE_VECTOR0_EVENT_RST:
ca1d7669 2219 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
c1a81619
SM		 2220 break;
2221 case HCLGE_VECTOR0_EVENT_MBX:
2222 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2223 break;
2224 }
ca1d7669
SM		 2225}
2226
8e52a602
XW		 2227static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2228{
2229 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2230 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2231 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2232 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2233 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2234}
2235
466b0c00
L		 2236static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2237{
2238 writel(enable ? 1 : 0, vector->addr);
2239}
2240
2241static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2242{
2243 struct hclge_dev *hdev = data;
ca1d7669
SM		 2244 u32 event_cause;
2245 u32 clearval;
466b0c00
L		 2246
2247 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2248 event_cause = hclge_check_event_cause(hdev, &clearval);
2249
c1a81619 2250 /* vector 0 interrupt is shared with reset and mailbox source events.*/
ca1d7669
SM		 2251 switch (event_cause) {
2252 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2253 hclge_reset_task_schedule(hdev);
ca1d7669 2254 break;
c1a81619
SM		 2255 case HCLGE_VECTOR0_EVENT_MBX:
2256 /* If we are here then,
2257 * 1. Either we are not handling any mbx task and we are not
2258 * scheduled as well
2259 * OR
2260 * 2. We could be handling a mbx task but nothing more is
2261 * scheduled.
2262 * In both cases, we should schedule mbx task as there are more
2263 * mbx messages reported by this interrupt.
2264 */
2265 hclge_mbx_task_schedule(hdev);
f0ad97ac 2266 break;
ca1d7669 2267 default:
f0ad97ac
YL		 2268 dev_warn(&hdev->pdev->dev,
2269 "received unknown or unhandled event of vector0\n");
ca1d7669
SM		 2270 break;
2271 }
2272
cd8c5c26
YL		 2273 /* clear the source of interrupt if it is not cause by reset */
2274 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2275 hclge_clear_event_cause(hdev, event_cause, clearval);
2276 hclge_enable_vector(&hdev->misc_vector, true);
2277 }
466b0c00
L		 2278
2279 return IRQ_HANDLED;
2280}
2281
2282static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2283{
36cbbdf6
PL		 2284 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2285 dev_warn(&hdev->pdev->dev,
2286 "vector(vector_id %d) has been freed.\n", vector_id);
2287 return;
2288 }
2289
466b0c00
L		 2290 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2291 hdev->num_msi_left += 1;
2292 hdev->num_msi_used -= 1;
2293}
2294
2295static void hclge_get_misc_vector(struct hclge_dev *hdev)
2296{
2297 struct hclge_misc_vector *vector = &hdev->misc_vector;
2298
2299 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2300
2301 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2302 hdev->vector_status[0] = 0;
2303
2304 hdev->num_msi_left -= 1;
2305 hdev->num_msi_used += 1;
2306}
2307
2308static int hclge_misc_irq_init(struct hclge_dev *hdev)
2309{
2310 int ret;
2311
2312 hclge_get_misc_vector(hdev);
2313
ca1d7669
SM		 2314 /* this would be explicitly freed in the end */
2315 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2316 0, "hclge_misc", hdev);
466b0c00
L		 2317 if (ret) {
2318 hclge_free_vector(hdev, 0);
2319 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2320 hdev->misc_vector.vector_irq);
2321 }
2322
2323 return ret;
2324}
2325
ca1d7669
SM		 2326static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2327{
2328 free_irq(hdev->misc_vector.vector_irq, hdev);
2329 hclge_free_vector(hdev, 0);
2330}
2331
4ed340ab
L		 2332static int hclge_notify_client(struct hclge_dev *hdev,
2333 enum hnae3_reset_notify_type type)
2334{
2335 struct hnae3_client *client = hdev->nic_client;
2336 u16 i;
2337
2338 if (!client->ops->reset_notify)
2339 return -EOPNOTSUPP;
2340
2341 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2342 struct hnae3_handle *handle = &hdev->vport[i].nic;
2343 int ret;
2344
2345 ret = client->ops->reset_notify(handle, type);
2346 if (ret)
2347 return ret;
2348 }
2349
2350 return 0;
2351}
2352
2353static int hclge_reset_wait(struct hclge_dev *hdev)
2354{
2355#define HCLGE_RESET_WATI_MS 100
2356#define HCLGE_RESET_WAIT_CNT 5
2357 u32 val, reg, reg_bit;
2358 u32 cnt = 0;
2359
2360 switch (hdev->reset_type) {
2361 case HNAE3_GLOBAL_RESET:
2362 reg = HCLGE_GLOBAL_RESET_REG;
2363 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2364 break;
2365 case HNAE3_CORE_RESET:
2366 reg = HCLGE_GLOBAL_RESET_REG;
2367 reg_bit = HCLGE_CORE_RESET_BIT;
2368 break;
2369 case HNAE3_FUNC_RESET:
2370 reg = HCLGE_FUN_RST_ING;
2371 reg_bit = HCLGE_FUN_RST_ING_B;
2372 break;
2373 default:
2374 dev_err(&hdev->pdev->dev,
2375 "Wait for unsupported reset type: %d\n",
2376 hdev->reset_type);
2377 return -EINVAL;
2378 }
2379
2380 val = hclge_read_dev(&hdev->hw, reg);
e4e87715 2381 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
4ed340ab
L		 2382 msleep(HCLGE_RESET_WATI_MS);
2383 val = hclge_read_dev(&hdev->hw, reg);
2384 cnt++;
2385 }
2386
4ed340ab
L		 2387 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2388 dev_warn(&hdev->pdev->dev,
2389 "Wait for reset timeout: %d\n", hdev->reset_type);
2390 return -EBUSY;
2391 }
2392
2393 return 0;
2394}
2395
2bfbd35d 2396int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2397{
2398 struct hclge_desc desc;
2399 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2400 int ret;
2401
2402 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e4e87715 2403 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2404 req->fun_reset_vfid = func_id;
2405
2406 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2407 if (ret)
2408 dev_err(&hdev->pdev->dev,
2409 "send function reset cmd fail, status =%d\n", ret);
2410
2411 return ret;
2412}
2413
f2f432f2 2414static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2415{
2416 struct pci_dev *pdev = hdev->pdev;
2417 u32 val;
2418
f2f432f2 2419 switch (hdev->reset_type) {
4ed340ab
L		 2420 case HNAE3_GLOBAL_RESET:
2421 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2422 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2423 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2424 dev_info(&pdev->dev, "Global Reset requested\n");
2425 break;
2426 case HNAE3_CORE_RESET:
2427 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2428 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2429 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2430 dev_info(&pdev->dev, "Core Reset requested\n");
2431 break;
2432 case HNAE3_FUNC_RESET:
2433 dev_info(&pdev->dev, "PF Reset requested\n");
2434 hclge_func_reset_cmd(hdev, 0);
cb1b9f77
SM		 2435 /* schedule again to check later */
2436 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2437 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2438 break;
2439 default:
2440 dev_warn(&pdev->dev,
f2f432f2 2441 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2442 break;
2443 }
2444}
2445
f2f432f2
SM		 2446static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2447 unsigned long *addr)
2448{
2449 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2450
2451 /* return the highest priority reset level amongst all */
2452 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2453 rst_level = HNAE3_GLOBAL_RESET;
2454 else if (test_bit(HNAE3_CORE_RESET, addr))
2455 rst_level = HNAE3_CORE_RESET;
2456 else if (test_bit(HNAE3_IMP_RESET, addr))
2457 rst_level = HNAE3_IMP_RESET;
2458 else if (test_bit(HNAE3_FUNC_RESET, addr))
2459 rst_level = HNAE3_FUNC_RESET;
2460
2461 /* now, clear all other resets */
2462 clear_bit(HNAE3_GLOBAL_RESET, addr);
2463 clear_bit(HNAE3_CORE_RESET, addr);
2464 clear_bit(HNAE3_IMP_RESET, addr);
2465 clear_bit(HNAE3_FUNC_RESET, addr);
2466
2467 return rst_level;
2468}
2469
cd8c5c26
YL		 2470static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2471{
2472 u32 clearval = 0;
2473
2474 switch (hdev->reset_type) {
2475 case HNAE3_IMP_RESET:
2476 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2477 break;
2478 case HNAE3_GLOBAL_RESET:
2479 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2480 break;
2481 case HNAE3_CORE_RESET:
2482 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2483 break;
2484 default:
cd8c5c26
YL		 2485 break;
2486 }
2487
2488 if (!clearval)
2489 return;
2490
2491 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2492 hclge_enable_vector(&hdev->misc_vector, true);
2493}
2494
f2f432f2
SM		 2495static void hclge_reset(struct hclge_dev *hdev)
2496{
9de0b86f
HT		 2497 struct hnae3_handle *handle;
2498
f2f432f2 2499 /* perform reset of the stack & ae device for a client */
9de0b86f 2500 handle = &hdev->vport[0].nic;
6d4fab39 2501 rtnl_lock();
f2f432f2
SM		 2502 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2503
2504 if (!hclge_reset_wait(hdev)) {
f2f432f2
SM		 2505 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2506 hclge_reset_ae_dev(hdev->ae_dev);
2507 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
cd8c5c26
YL		 2508
2509 hclge_clear_reset_cause(hdev);
f2f432f2
SM		 2510 } else {
2511 /* schedule again to check pending resets later */
2512 set_bit(hdev->reset_type, &hdev->reset_pending);
2513 hclge_reset_task_schedule(hdev);
2514 }
2515
2516 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
9de0b86f 2517 handle->last_reset_time = jiffies;
6d4fab39 2518 rtnl_unlock();
f2f432f2
SM		 2519}
2520
6d4c3981 2521static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2522{
2523 struct hclge_vport *vport = hclge_get_vport(handle);
2524 struct hclge_dev *hdev = vport->back;
2525
6d4c3981
SM		 2526 /* check if this is a new reset request and we are not here just because
2527 * last reset attempt did not succeed and watchdog hit us again. We will
2528 * know this if last reset request did not occur very recently (watchdog
2529 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2530 * In case of new request we reset the "reset level" to PF reset.
9de0b86f
HT		 2531 * And if it is a repeat reset request of the most recent one then we
2532 * want to make sure we throttle the reset request. Therefore, we will
2533 * not allow it again before 3*HZ times.
6d4c3981 2534 */
9de0b86f
HT		 2535 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2536 return;
2537 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
6d4c3981 2538 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2539
6d4c3981
SM		 2540 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2541 handle->reset_level);
2542
2543 /* request reset & schedule reset task */
2544 set_bit(handle->reset_level, &hdev->reset_request);
2545 hclge_reset_task_schedule(hdev);
2546
2547 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2548 handle->reset_level++;
4ed340ab
L		 2549}
2550
2551static void hclge_reset_subtask(struct hclge_dev *hdev)
2552{
f2f432f2
SM		 2553 /* check if there is any ongoing reset in the hardware. This status can
2554 * be checked from reset_pending. If there is then, we need to wait for
2555 * hardware to complete reset.
2556 * a. If we are able to figure out in reasonable time that hardware
2557 * has fully resetted then, we can proceed with driver, client
2558 * reset.
2559 * b. else, we can come back later to check this status so re-sched
2560 * now.
2561 */
2562 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2563 if (hdev->reset_type != HNAE3_NONE_RESET)
2564 hclge_reset(hdev);
4ed340ab 2565
f2f432f2
SM		 2566 /* check if we got any *new* reset requests to be honored */
2567 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2568 if (hdev->reset_type != HNAE3_NONE_RESET)
2569 hclge_do_reset(hdev);
4ed340ab 2570
4ed340ab
L		 2571 hdev->reset_type = HNAE3_NONE_RESET;
2572}
2573
cb1b9f77 2574static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2575{
cb1b9f77
SM		 2576 struct hclge_dev *hdev =
2577 container_of(work, struct hclge_dev, rst_service_task);
2578
2579 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2580 return;
2581
2582 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2583
4ed340ab 2584 hclge_reset_subtask(hdev);
cb1b9f77
SM		 2585
2586 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2587}
2588
c1a81619
SM		 2589static void hclge_mailbox_service_task(struct work_struct *work)
2590{
2591 struct hclge_dev *hdev =
2592 container_of(work, struct hclge_dev, mbx_service_task);
2593
2594 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2595 return;
2596
2597 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2598
2599 hclge_mbx_handler(hdev);
2600
2601 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2602}
2603
46a3df9f
S		 2604static void hclge_service_task(struct work_struct *work)
2605{
2606 struct hclge_dev *hdev =
2607 container_of(work, struct hclge_dev, service_task);
2608
c5f65480
JS		 2609 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2610 hclge_update_stats_for_all(hdev);
2611 hdev->hw_stats.stats_timer = 0;
2612 }
2613
46a3df9f
S		 2614 hclge_update_speed_duplex(hdev);
2615 hclge_update_link_status(hdev);
46a3df9f
S		 2616 hclge_service_complete(hdev);
2617}
2618
46a3df9f
S		 2619struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2620{
2621 /* VF handle has no client */
2622 if (!handle->client)
2623 return container_of(handle, struct hclge_vport, nic);
2624 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2625 return container_of(handle, struct hclge_vport, roce);
2626 else
2627 return container_of(handle, struct hclge_vport, nic);
2628}
2629
2630static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2631 struct hnae3_vector_info *vector_info)
2632{
2633 struct hclge_vport *vport = hclge_get_vport(handle);
2634 struct hnae3_vector_info *vector = vector_info;
2635 struct hclge_dev *hdev = vport->back;
2636 int alloc = 0;
2637 int i, j;
2638
2639 vector_num = min(hdev->num_msi_left, vector_num);
2640
2641 for (j = 0; j < vector_num; j++) {
2642 for (i = 1; i < hdev->num_msi; i++) {
2643 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2644 vector->vector = pci_irq_vector(hdev->pdev, i);
2645 vector->io_addr = hdev->hw.io_base +
2646 HCLGE_VECTOR_REG_BASE +
2647 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2648 vport->vport_id *
2649 HCLGE_VECTOR_VF_OFFSET;
2650 hdev->vector_status[i] = vport->vport_id;
887c3820 2651 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2652
2653 vector++;
2654 alloc++;
2655
2656 break;
2657 }
2658 }
2659 }
2660 hdev->num_msi_left -= alloc;
2661 hdev->num_msi_used += alloc;
2662
2663 return alloc;
2664}
2665
2666static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2667{
2668 int i;
2669
887c3820
SM		 2670 for (i = 0; i < hdev->num_msi; i++)
2671 if (vector == hdev->vector_irq[i])
2672 return i;
2673
46a3df9f
S		 2674 return -EINVAL;
2675}
2676
0d3e6631
YL		 2677static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2678{
2679 struct hclge_vport *vport = hclge_get_vport(handle);
2680 struct hclge_dev *hdev = vport->back;
2681 int vector_id;
2682
2683 vector_id = hclge_get_vector_index(hdev, vector);
2684 if (vector_id < 0) {
2685 dev_err(&hdev->pdev->dev,
2686 "Get vector index fail. vector_id =%d\n", vector_id);
2687 return vector_id;
2688 }
2689
2690 hclge_free_vector(hdev, vector_id);
2691
2692 return 0;
2693}
2694
46a3df9f
S		 2695static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2696{
2697 return HCLGE_RSS_KEY_SIZE;
2698}
2699
2700static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2701{
2702 return HCLGE_RSS_IND_TBL_SIZE;
2703}
2704
46a3df9f
S		 2705static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2706 const u8 hfunc, const u8 *key)
2707{
d44f9b63 2708 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2709 struct hclge_desc desc;
2710 int key_offset;
2711 int key_size;
2712 int ret;
2713
d44f9b63 2714 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2715
2716 for (key_offset = 0; key_offset < 3; key_offset++) {
2717 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2718 false);
2719
2720 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2721 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2722
2723 if (key_offset == 2)
2724 key_size =
2725 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2726 else
2727 key_size = HCLGE_RSS_HASH_KEY_NUM;
2728
2729 memcpy(req->hash_key,
2730 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2731
2732 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2733 if (ret) {
2734 dev_err(&hdev->pdev->dev,
2735 "Configure RSS config fail, status = %d\n",
2736 ret);
2737 return ret;
2738 }
2739 }
2740 return 0;
2741}
2742
89523cfa 2743static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 2744{
d44f9b63 2745 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2746 struct hclge_desc desc;
2747 int i, j;
2748 int ret;
2749
d44f9b63 2750 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2751
2752 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2753 hclge_cmd_setup_basic_desc
2754 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2755
a90bb9a5
YL		 2756 req->start_table_index =
2757 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2758 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2759
2760 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2761 req->rss_result[j] =
2762 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2763
2764 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2765 if (ret) {
2766 dev_err(&hdev->pdev->dev,
2767 "Configure rss indir table fail,status = %d\n",
2768 ret);
2769 return ret;
2770 }
2771 }
2772 return 0;
2773}
2774
2775static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2776 u16 *tc_size, u16 *tc_offset)
2777{
d44f9b63 2778 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2779 struct hclge_desc desc;
2780 int ret;
2781 int i;
2782
2783 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2784 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2785
2786 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2787 u16 mode = 0;
2788
e4e87715
PL		 2789 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2790 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
2791 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2792 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
2793 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2794
2795 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2796 }
2797
2798 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 2799 if (ret)
46a3df9f
S		 2800 dev_err(&hdev->pdev->dev,
2801 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 2802
3f639907 2803 return ret;
46a3df9f
S		 2804}
2805
2806static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2807{
d44f9b63 2808 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2809 struct hclge_desc desc;
2810 int ret;
2811
2812 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2813
d44f9b63 2814 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429
YL		 2815
2816 /* Get the tuple cfg from pf */
2817 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
2818 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
2819 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
2820 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
2821 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
2822 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
2823 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
2824 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f 2825 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 2826 if (ret)
46a3df9f
S		 2827 dev_err(&hdev->pdev->dev,
2828 "Configure rss input fail, status = %d\n", ret);
3f639907 2829 return ret;
46a3df9f
S		 2830}
2831
2832static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2833 u8 *key, u8 *hfunc)
2834{
2835 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 2836 int i;
2837
2838 /* Get hash algorithm */
2839 if (hfunc)
89523cfa 2840 *hfunc = vport->rss_algo;
46a3df9f
S		 2841
2842 /* Get the RSS Key required by the user */
2843 if (key)
2844 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2845
2846 /* Get indirect table */
2847 if (indir)
2848 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2849 indir[i] = vport->rss_indirection_tbl[i];
2850
2851 return 0;
2852}
2853
2854static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2855 const u8 *key, const u8 hfunc)
2856{
2857 struct hclge_vport *vport = hclge_get_vport(handle);
2858 struct hclge_dev *hdev = vport->back;
2859 u8 hash_algo;
2860 int ret, i;
2861
2862 /* Set the RSS Hash Key if specififed by the user */
2863 if (key) {
46a3df9f
S		 2864
2865 if (hfunc == ETH_RSS_HASH_TOP ||
2866 hfunc == ETH_RSS_HASH_NO_CHANGE)
2867 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2868 else
2869 return -EINVAL;
2870 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2871 if (ret)
2872 return ret;
89523cfa
YL		 2873
2874 /* Update the shadow RSS key with user specified qids */
2875 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2876 vport->rss_algo = hash_algo;
46a3df9f
S		 2877 }
2878
2879 /* Update the shadow RSS table with user specified qids */
2880 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2881 vport->rss_indirection_tbl[i] = indir[i];
2882
2883 /* Update the hardware */
89523cfa 2884 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 2885}
2886
f7db940a
L		 2887static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2888{
2889 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2890
2891 if (nfc->data & RXH_L4_B_2_3)
2892 hash_sets |= HCLGE_D_PORT_BIT;
2893 else
2894 hash_sets &= ~HCLGE_D_PORT_BIT;
2895
2896 if (nfc->data & RXH_IP_SRC)
2897 hash_sets |= HCLGE_S_IP_BIT;
2898 else
2899 hash_sets &= ~HCLGE_S_IP_BIT;
2900
2901 if (nfc->data & RXH_IP_DST)
2902 hash_sets |= HCLGE_D_IP_BIT;
2903 else
2904 hash_sets &= ~HCLGE_D_IP_BIT;
2905
2906 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
2907 hash_sets |= HCLGE_V_TAG_BIT;
2908
2909 return hash_sets;
2910}
2911
2912static int hclge_set_rss_tuple(struct hnae3_handle *handle,
2913 struct ethtool_rxnfc *nfc)
2914{
2915 struct hclge_vport *vport = hclge_get_vport(handle);
2916 struct hclge_dev *hdev = vport->back;
2917 struct hclge_rss_input_tuple_cmd *req;
2918 struct hclge_desc desc;
2919 u8 tuple_sets;
2920 int ret;
2921
2922 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2923 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2924 return -EINVAL;
2925
2926 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429 2927 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 2928
6f2af429
YL		 2929 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
2930 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
2931 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
2932 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
2933 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
2934 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
2935 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
2936 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 2937
2938 tuple_sets = hclge_get_rss_hash_bits(nfc);
2939 switch (nfc->flow_type) {
2940 case TCP_V4_FLOW:
2941 req->ipv4_tcp_en = tuple_sets;
2942 break;
2943 case TCP_V6_FLOW:
2944 req->ipv6_tcp_en = tuple_sets;
2945 break;
2946 case UDP_V4_FLOW:
2947 req->ipv4_udp_en = tuple_sets;
2948 break;
2949 case UDP_V6_FLOW:
2950 req->ipv6_udp_en = tuple_sets;
2951 break;
2952 case SCTP_V4_FLOW:
2953 req->ipv4_sctp_en = tuple_sets;
2954 break;
2955 case SCTP_V6_FLOW:
2956 if ((nfc->data & RXH_L4_B_0_1) ||
2957 (nfc->data & RXH_L4_B_2_3))
2958 return -EINVAL;
2959
2960 req->ipv6_sctp_en = tuple_sets;
2961 break;
2962 case IPV4_FLOW:
2963 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2964 break;
2965 case IPV6_FLOW:
2966 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2967 break;
2968 default:
2969 return -EINVAL;
2970 }
2971
2972 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6f2af429 2973 if (ret) {
f7db940a
L		 2974 dev_err(&hdev->pdev->dev,
2975 "Set rss tuple fail, status = %d\n", ret);
6f2af429
YL		 2976 return ret;
2977 }
f7db940a 2978
6f2af429
YL		 2979 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
2980 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
2981 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
2982 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
2983 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
2984 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
2985 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
2986 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
2987 return 0;
f7db940a
L		 2988}
2989
07d29954
L		 2990static int hclge_get_rss_tuple(struct hnae3_handle *handle,
2991 struct ethtool_rxnfc *nfc)
2992{
2993 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 2994 u8 tuple_sets;
07d29954
L		 2995
2996 nfc->data = 0;
2997
07d29954
L		 2998 switch (nfc->flow_type) {
2999 case TCP_V4_FLOW:
6f2af429 3000 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3001 break;
3002 case UDP_V4_FLOW:
6f2af429 3003 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3004 break;
3005 case TCP_V6_FLOW:
6f2af429 3006 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3007 break;
3008 case UDP_V6_FLOW:
6f2af429 3009 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3010 break;
3011 case SCTP_V4_FLOW:
6f2af429 3012 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3013 break;
3014 case SCTP_V6_FLOW:
6f2af429 3015 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3016 break;
3017 case IPV4_FLOW:
3018 case IPV6_FLOW:
3019 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3020 break;
3021 default:
3022 return -EINVAL;
3023 }
3024
3025 if (!tuple_sets)
3026 return 0;
3027
3028 if (tuple_sets & HCLGE_D_PORT_BIT)
3029 nfc->data |= RXH_L4_B_2_3;
3030 if (tuple_sets & HCLGE_S_PORT_BIT)
3031 nfc->data |= RXH_L4_B_0_1;
3032 if (tuple_sets & HCLGE_D_IP_BIT)
3033 nfc->data |= RXH_IP_DST;
3034 if (tuple_sets & HCLGE_S_IP_BIT)
3035 nfc->data |= RXH_IP_SRC;
3036
3037 return 0;
3038}
3039
46a3df9f
S		 3040static int hclge_get_tc_size(struct hnae3_handle *handle)
3041{
3042 struct hclge_vport *vport = hclge_get_vport(handle);
3043 struct hclge_dev *hdev = vport->back;
3044
3045 return hdev->rss_size_max;
3046}
3047
77f255c1 3048int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3049{
46a3df9f 3050 struct hclge_vport *vport = hdev->vport;
268f5dfa
YL		 3051 u8 *rss_indir = vport[0].rss_indirection_tbl;
3052 u16 rss_size = vport[0].alloc_rss_size;
3053 u8 *key = vport[0].rss_hash_key;
3054 u8 hfunc = vport[0].rss_algo;
46a3df9f 3055 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3056 u16 tc_valid[HCLGE_MAX_TC_NUM];
3057 u16 tc_size[HCLGE_MAX_TC_NUM];
268f5dfa
YL		 3058 u16 roundup_size;
3059 int i, ret;
68ece54e 3060
46a3df9f
S		 3061 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3062 if (ret)
268f5dfa 3063 return ret;
46a3df9f 3064
46a3df9f
S		 3065 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3066 if (ret)
268f5dfa 3067 return ret;
46a3df9f
S		 3068
3069 ret = hclge_set_rss_input_tuple(hdev);
3070 if (ret)
268f5dfa 3071 return ret;
46a3df9f 3072
68ece54e
YL		 3073 /* Each TC have the same queue size, and tc_size set to hardware is
3074 * the log2 of roundup power of two of rss_size, the acutal queue
3075 * size is limited by indirection table.
3076 */
3077 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3078 dev_err(&hdev->pdev->dev,
3079 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3080 rss_size);
268f5dfa 3081 return -EINVAL;
68ece54e
YL		 3082 }
3083
3084 roundup_size = roundup_pow_of_two(rss_size);
3085 roundup_size = ilog2(roundup_size);
3086
46a3df9f 3087 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3088 tc_valid[i] = 0;
46a3df9f 3089
68ece54e
YL		 3090 if (!(hdev->hw_tc_map & BIT(i)))
3091 continue;
3092
3093 tc_valid[i] = 1;
3094 tc_size[i] = roundup_size;
3095 tc_offset[i] = rss_size * i;
46a3df9f 3096 }
68ece54e 3097
268f5dfa
YL		 3098 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3099}
46a3df9f 3100
268f5dfa
YL		 3101void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3102{
3103 struct hclge_vport *vport = hdev->vport;
3104 int i, j;
46a3df9f 3105
268f5dfa
YL		 3106 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3107 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3108 vport[j].rss_indirection_tbl[i] =
3109 i % vport[j].alloc_rss_size;
3110 }
3111}
3112
3113static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3114{
3115 struct hclge_vport *vport = hdev->vport;
3116 int i;
3117
268f5dfa
YL		 3118 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3119 vport[i].rss_tuple_sets.ipv4_tcp_en =
3120 HCLGE_RSS_INPUT_TUPLE_OTHER;
3121 vport[i].rss_tuple_sets.ipv4_udp_en =
3122 HCLGE_RSS_INPUT_TUPLE_OTHER;
3123 vport[i].rss_tuple_sets.ipv4_sctp_en =
3124 HCLGE_RSS_INPUT_TUPLE_SCTP;
3125 vport[i].rss_tuple_sets.ipv4_fragment_en =
3126 HCLGE_RSS_INPUT_TUPLE_OTHER;
3127 vport[i].rss_tuple_sets.ipv6_tcp_en =
3128 HCLGE_RSS_INPUT_TUPLE_OTHER;
3129 vport[i].rss_tuple_sets.ipv6_udp_en =
3130 HCLGE_RSS_INPUT_TUPLE_OTHER;
3131 vport[i].rss_tuple_sets.ipv6_sctp_en =
3132 HCLGE_RSS_INPUT_TUPLE_SCTP;
3133 vport[i].rss_tuple_sets.ipv6_fragment_en =
3134 HCLGE_RSS_INPUT_TUPLE_OTHER;
3135
3136 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
ea739c90
FL		 3137
3138 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
268f5dfa
YL		 3139 }
3140
3141 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3142}
3143
84e095d6
SM		 3144int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3145 int vector_id, bool en,
3146 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3147{
3148 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3149 struct hnae3_ring_chain_node *node;
3150 struct hclge_desc desc;
84e095d6
SM		 3151 struct hclge_ctrl_vector_chain_cmd *req
3152 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3153 enum hclge_cmd_status status;
3154 enum hclge_opcode_type op;
3155 u16 tqp_type_and_id;
46a3df9f
S		 3156 int i;
3157
84e095d6
SM		 3158 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3159 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3160 req->int_vector_id = vector_id;
3161
3162 i = 0;
3163 for (node = ring_chain; node; node = node->next) {
84e095d6 3164 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e4e87715
PL		 3165 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3166 HCLGE_INT_TYPE_S,
3167 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3168 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3169 HCLGE_TQP_ID_S, node->tqp_index);
3170 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3171 HCLGE_INT_GL_IDX_S,
3172 hnae3_get_field(node->int_gl_idx,
3173 HNAE3_RING_GL_IDX_M,
3174 HNAE3_RING_GL_IDX_S));
84e095d6 3175 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3176 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3177 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
84e095d6 3178 req->vfid = vport->vport_id;
46a3df9f 3179
84e095d6
SM		 3180 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3181 if (status) {
46a3df9f
S		 3182 dev_err(&hdev->pdev->dev,
3183 "Map TQP fail, status is %d.\n",
84e095d6
SM		 3184 status);
3185 return -EIO;
46a3df9f
S		 3186 }
3187 i = 0;
3188
3189 hclge_cmd_setup_basic_desc(&desc,
84e095d6 3190 op,
46a3df9f
S		 3191 false);
3192 req->int_vector_id = vector_id;
3193 }
3194 }
3195
3196 if (i > 0) {
3197 req->int_cause_num = i;
84e095d6
SM		 3198 req->vfid = vport->vport_id;
3199 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3200 if (status) {
46a3df9f 3201 dev_err(&hdev->pdev->dev,
84e095d6
SM		 3202 "Map TQP fail, status is %d.\n", status);
3203 return -EIO;
46a3df9f
S		 3204 }
3205 }
3206
3207 return 0;
3208}
3209
84e095d6
SM		 3210static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3211 int vector,
3212 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3213{
3214 struct hclge_vport *vport = hclge_get_vport(handle);
3215 struct hclge_dev *hdev = vport->back;
3216 int vector_id;
3217
3218 vector_id = hclge_get_vector_index(hdev, vector);
3219 if (vector_id < 0) {
3220 dev_err(&hdev->pdev->dev,
84e095d6 3221 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3222 return vector_id;
3223 }
3224
84e095d6 3225 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3226}
3227
84e095d6
SM		 3228static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3229 int vector,
3230 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3231{
3232 struct hclge_vport *vport = hclge_get_vport(handle);
3233 struct hclge_dev *hdev = vport->back;
84e095d6 3234 int vector_id, ret;
46a3df9f 3235
b50ae26c
PL		 3236 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3237 return 0;
3238
46a3df9f
S		 3239 vector_id = hclge_get_vector_index(hdev, vector);
3240 if (vector_id < 0) {
3241 dev_err(&handle->pdev->dev,
3242 "Get vector index fail. ret =%d\n", vector_id);
3243 return vector_id;
3244 }
3245
84e095d6 3246 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
0d3e6631 3247 if (ret)
84e095d6
SM		 3248 dev_err(&handle->pdev->dev,
3249 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3250 vector_id,
3251 ret);
46a3df9f 3252
0d3e6631 3253 return ret;
46a3df9f
S		 3254}
3255
3256int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3257 struct hclge_promisc_param *param)
3258{
d44f9b63 3259 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3260 struct hclge_desc desc;
3261 int ret;
3262
3263 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3264
d44f9b63 3265 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3266 req->vf_id = param->vf_id;
96c0e861
PL		 3267
3268 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3269 * pdev revision(0x20), new revision support them. The
3270 * value of this two fields will not return error when driver
3271 * send command to fireware in revision(0x20).
3272 */
3273 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3274 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3275
3276 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3277 if (ret)
46a3df9f
S		 3278 dev_err(&hdev->pdev->dev,
3279 "Set promisc mode fail, status is %d.\n", ret);
3f639907
JS		 3280
3281 return ret;
46a3df9f
S		 3282}
3283
3284void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3285 bool en_mc, bool en_bc, int vport_id)
3286{
3287 if (!param)
3288 return;
3289
3290 memset(param, 0, sizeof(struct hclge_promisc_param));
3291 if (en_uc)
3292 param->enable = HCLGE_PROMISC_EN_UC;
3293 if (en_mc)
3294 param->enable |= HCLGE_PROMISC_EN_MC;
3295 if (en_bc)
3296 param->enable |= HCLGE_PROMISC_EN_BC;
3297 param->vf_id = vport_id;
3298}
3299
3b75c3df
PL		 3300static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3301 bool en_mc_pmc)
46a3df9f
S		 3302{
3303 struct hclge_vport *vport = hclge_get_vport(handle);
3304 struct hclge_dev *hdev = vport->back;
3305 struct hclge_promisc_param param;
3306
3b75c3df
PL		 3307 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3308 vport->vport_id);
46a3df9f
S		 3309 hclge_cmd_set_promisc_mode(hdev, &param);
3310}
3311
3312static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3313{
3314 struct hclge_desc desc;
d44f9b63
YL		 3315 struct hclge_config_mac_mode_cmd *req =
3316 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3317 u32 loop_en = 0;
46a3df9f
S		 3318 int ret;
3319
3320 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e4e87715
PL		 3321 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3322 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3323 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3324 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3325 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3326 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3327 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3328 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3329 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3330 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3331 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3332 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3333 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3334 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 3335 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3336
3337 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3338 if (ret)
3339 dev_err(&hdev->pdev->dev,
3340 "mac enable fail, ret =%d.\n", ret);
3341}
3342
e4d68dae 3343static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3344{
c39c4d98 3345 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3346 struct hclge_desc desc;
3347 u32 loop_en;
3348 int ret;
3349
e4d68dae
YL		 3350 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3351 /* 1 Read out the MAC mode config at first */
3352 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3353 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3354 if (ret) {
3355 dev_err(&hdev->pdev->dev,
3356 "mac loopback get fail, ret =%d.\n", ret);
3357 return ret;
3358 }
c39c4d98 3359
e4d68dae
YL		 3360 /* 2 Then setup the loopback flag */
3361 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e4e87715 3362 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
0f29fc23
YL		 3363 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
3364 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
e4d68dae
YL		 3365
3366 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3367
e4d68dae
YL		 3368 /* 3 Config mac work mode with loopback flag
3369 * and its original configure parameters
3370 */
3371 hclge_cmd_reuse_desc(&desc, false);
3372 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3373 if (ret)
3374 dev_err(&hdev->pdev->dev,
3375 "mac loopback set fail, ret =%d.\n", ret);
3376 return ret;
3377}
c39c4d98 3378
5fd50ac3
PL		 3379static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3380{
3381#define HCLGE_SERDES_RETRY_MS 10
3382#define HCLGE_SERDES_RETRY_NUM 100
3383 struct hclge_serdes_lb_cmd *req;
3384 struct hclge_desc desc;
3385 int ret, i = 0;
3386
3387 req = (struct hclge_serdes_lb_cmd *)&desc.data[0];
3388 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3389
3390 if (en) {
3391 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3392 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3393 } else {
3394 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3395 }
3396
3397 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3398 if (ret) {
3399 dev_err(&hdev->pdev->dev,
3400 "serdes loopback set fail, ret = %d\n", ret);
3401 return ret;
3402 }
3403
3404 do {
3405 msleep(HCLGE_SERDES_RETRY_MS);
3406 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3407 true);
3408 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3409 if (ret) {
3410 dev_err(&hdev->pdev->dev,
3411 "serdes loopback get, ret = %d\n", ret);
3412 return ret;
3413 }
3414 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3415 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3416
3417 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3418 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3419 return -EBUSY;
3420 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3421 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3422 return -EIO;
3423 }
3424
0f29fc23 3425 hclge_cfg_mac_mode(hdev, en);
5fd50ac3
PL		 3426 return 0;
3427}
3428
0f29fc23
YL		 3429static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3430 int stream_id, bool enable)
3431{
3432 struct hclge_desc desc;
3433 struct hclge_cfg_com_tqp_queue_cmd *req =
3434 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3435 int ret;
3436
3437 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3438 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3439 req->stream_id = cpu_to_le16(stream_id);
3440 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3441
3442 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3443 if (ret)
3444 dev_err(&hdev->pdev->dev,
3445 "Tqp enable fail, status =%d.\n", ret);
3446 return ret;
3447}
3448
e4d68dae
YL		 3449static int hclge_set_loopback(struct hnae3_handle *handle,
3450 enum hnae3_loop loop_mode, bool en)
3451{
3452 struct hclge_vport *vport = hclge_get_vport(handle);
3453 struct hclge_dev *hdev = vport->back;
0f29fc23 3454 int i, ret;
e4d68dae
YL		 3455
3456 switch (loop_mode) {
3457 case HNAE3_MAC_INTER_LOOP_MAC:
3458 ret = hclge_set_mac_loopback(hdev, en);
c39c4d98 3459 break;
5fd50ac3
PL		 3460 case HNAE3_MAC_INTER_LOOP_SERDES:
3461 ret = hclge_set_serdes_loopback(hdev, en);
3462 break;
c39c4d98
YL		 3463 default:
3464 ret = -ENOTSUPP;
3465 dev_err(&hdev->pdev->dev,
3466 "loop_mode %d is not supported\n", loop_mode);
3467 break;
3468 }
3469
0f29fc23
YL		 3470 for (i = 0; i < vport->alloc_tqps; i++) {
3471 ret = hclge_tqp_enable(hdev, i, 0, en);
3472 if (ret)
3473 return ret;
3474 }
46a3df9f 3475
0f29fc23 3476 return 0;
46a3df9f
S		 3477}
3478
3479static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3480{
3481 struct hclge_vport *vport = hclge_get_vport(handle);
3482 struct hnae3_queue *queue;
3483 struct hclge_tqp *tqp;
3484 int i;
3485
3486 for (i = 0; i < vport->alloc_tqps; i++) {
3487 queue = handle->kinfo.tqp[i];
3488 tqp = container_of(queue, struct hclge_tqp, q);
3489 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3490 }
3491}
3492
3493static int hclge_ae_start(struct hnae3_handle *handle)
3494{
3495 struct hclge_vport *vport = hclge_get_vport(handle);
3496 struct hclge_dev *hdev = vport->back;
b01b7cf1 3497 int i;
46a3df9f 3498
814e0274
PL		 3499 for (i = 0; i < vport->alloc_tqps; i++)
3500 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3501
46a3df9f
S		 3502 /* mac enable */
3503 hclge_cfg_mac_mode(hdev, true);
3504 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3505 mod_timer(&hdev->service_timer, jiffies + HZ);
be8d8cdb 3506 hdev->hw.mac.link = 0;
46a3df9f 3507
b50ae26c
PL		 3508 /* reset tqp stats */
3509 hclge_reset_tqp_stats(handle);
3510
b01b7cf1 3511 hclge_mac_start_phy(hdev);
46a3df9f 3512
46a3df9f
S		 3513 return 0;
3514}
3515
3516static void hclge_ae_stop(struct hnae3_handle *handle)
3517{
3518 struct hclge_vport *vport = hclge_get_vport(handle);
3519 struct hclge_dev *hdev = vport->back;
814e0274 3520 int i;
46a3df9f 3521
2f7e4896
FL		 3522 set_bit(HCLGE_STATE_DOWN, &hdev->state);
3523
b50ae26c
PL		 3524 del_timer_sync(&hdev->service_timer);
3525 cancel_work_sync(&hdev->service_task);
f5be7967 3526 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
b50ae26c 3527
9617f668
YL		 3528 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3529 hclge_mac_stop_phy(hdev);
b50ae26c 3530 return;
9617f668 3531 }
b50ae26c 3532
814e0274
PL		 3533 for (i = 0; i < vport->alloc_tqps; i++)
3534 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3535
46a3df9f
S		 3536 /* Mac disable */
3537 hclge_cfg_mac_mode(hdev, false);
3538
3539 hclge_mac_stop_phy(hdev);
3540
3541 /* reset tqp stats */
3542 hclge_reset_tqp_stats(handle);
f30dfddc
FL		 3543 del_timer_sync(&hdev->service_timer);
3544 cancel_work_sync(&hdev->service_task);
3545 hclge_update_link_status(hdev);
46a3df9f
S		 3546}
3547
3548static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3549 u16 cmdq_resp, u8 resp_code,
3550 enum hclge_mac_vlan_tbl_opcode op)
3551{
3552 struct hclge_dev *hdev = vport->back;
3553 int return_status = -EIO;
3554
3555 if (cmdq_resp) {
3556 dev_err(&hdev->pdev->dev,
3557 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3558 cmdq_resp);
3559 return -EIO;
3560 }
3561
3562 if (op == HCLGE_MAC_VLAN_ADD) {
3563 if ((!resp_code) || (resp_code == 1)) {
3564 return_status = 0;
3565 } else if (resp_code == 2) {
eefd00a5 3566 return_status = -ENOSPC;
46a3df9f
S		 3567 dev_err(&hdev->pdev->dev,
3568 "add mac addr failed for uc_overflow.\n");
3569 } else if (resp_code == 3) {
eefd00a5 3570 return_status = -ENOSPC;
46a3df9f
S		 3571 dev_err(&hdev->pdev->dev,
3572 "add mac addr failed for mc_overflow.\n");
3573 } else {
3574 dev_err(&hdev->pdev->dev,
3575 "add mac addr failed for undefined, code=%d.\n",
3576 resp_code);
3577 }
3578 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3579 if (!resp_code) {
3580 return_status = 0;
3581 } else if (resp_code == 1) {
eefd00a5 3582 return_status = -ENOENT;
46a3df9f
S		 3583 dev_dbg(&hdev->pdev->dev,
3584 "remove mac addr failed for miss.\n");
3585 } else {
3586 dev_err(&hdev->pdev->dev,
3587 "remove mac addr failed for undefined, code=%d.\n",
3588 resp_code);
3589 }
3590 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3591 if (!resp_code) {
3592 return_status = 0;
3593 } else if (resp_code == 1) {
eefd00a5 3594 return_status = -ENOENT;
46a3df9f
S		 3595 dev_dbg(&hdev->pdev->dev,
3596 "lookup mac addr failed for miss.\n");
3597 } else {
3598 dev_err(&hdev->pdev->dev,
3599 "lookup mac addr failed for undefined, code=%d.\n",
3600 resp_code);
3601 }
3602 } else {
eefd00a5 3603 return_status = -EINVAL;
46a3df9f
S		 3604 dev_err(&hdev->pdev->dev,
3605 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3606 op);
3607 }
3608
3609 return return_status;
3610}
3611
3612static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3613{
3614 int word_num;
3615 int bit_num;
3616
3617 if (vfid > 255 || vfid < 0)
3618 return -EIO;
3619
3620 if (vfid >= 0 && vfid <= 191) {
3621 word_num = vfid / 32;
3622 bit_num = vfid % 32;
3623 if (clr)
a90bb9a5 3624 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3625 else
a90bb9a5 3626 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3627 } else {
3628 word_num = (vfid - 192) / 32;
3629 bit_num = vfid % 32;
3630 if (clr)
a90bb9a5 3631 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3632 else
a90bb9a5 3633 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3634 }
3635
3636 return 0;
3637}
3638
3639static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3640{
3641#define HCLGE_DESC_NUMBER 3
3642#define HCLGE_FUNC_NUMBER_PER_DESC 6
3643 int i, j;
3644
6c39d527 3645 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
46a3df9f
S		 3646 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3647 if (desc[i].data[j])
3648 return false;
3649
3650 return true;
3651}
3652
d44f9b63 3653static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3654 const u8 *addr)
3655{
3656 const unsigned char *mac_addr = addr;
3657 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3658 (mac_addr[0]) | (mac_addr[1] << 8);
3659 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3660
3661 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3662 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3663}
3664
1db9b1bf
YL		 3665static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3666 const u8 *addr)
46a3df9f
S		 3667{
3668 u16 high_val = addr[1] | (addr[0] << 8);
3669 struct hclge_dev *hdev = vport->back;
3670 u32 rsh = 4 - hdev->mta_mac_sel_type;
3671 u16 ret_val = (high_val >> rsh) & 0xfff;
3672
3673 return ret_val;
3674}
3675
3676static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3677 enum hclge_mta_dmac_sel_type mta_mac_sel,
3678 bool enable)
3679{
d44f9b63 3680 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3681 struct hclge_desc desc;
3682 int ret;
3683
d44f9b63 3684 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3685 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3686
e4e87715
PL		 3687 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3688 enable);
3689 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3690 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
46a3df9f
S		 3691
3692 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3693 if (ret)
46a3df9f
S		 3694 dev_err(&hdev->pdev->dev,
3695 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3696 ret);
46a3df9f 3697
3f639907 3698 return ret;
46a3df9f
S		 3699}
3700
3701int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3702 u8 func_id,
3703 bool enable)
3704{
d44f9b63 3705 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3706 struct hclge_desc desc;
3707 int ret;
3708
d44f9b63 3709 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3710 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3711
e4e87715
PL		 3712 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3713 enable);
46a3df9f
S		 3714 req->function_id = func_id;
3715
3716 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3717 if (ret)
46a3df9f
S		 3718 dev_err(&hdev->pdev->dev,
3719 "Config func_id enable failed for cmd_send, ret =%d.\n",
3720 ret);
46a3df9f 3721
3f639907 3722 return ret;
46a3df9f
S		 3723}
3724
3725static int hclge_set_mta_table_item(struct hclge_vport *vport,
3726 u16 idx,
3727 bool enable)
3728{
3729 struct hclge_dev *hdev = vport->back;
d44f9b63 3730 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3731 struct hclge_desc desc;
a90bb9a5 3732 u16 item_idx = 0;
46a3df9f
S		 3733 int ret;
3734
d44f9b63 3735 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f 3736 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
e4e87715 3737 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
46a3df9f 3738
e4e87715
PL		 3739 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3740 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3741 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3742
3743 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3744 if (ret) {
3745 dev_err(&hdev->pdev->dev,
3746 "Config mta table item failed for cmd_send, ret =%d.\n",
3747 ret);
3748 return ret;
3749 }
3750
40cca1c5
XW		 3751 if (enable)
3752 set_bit(idx, vport->mta_shadow);
3753 else
3754 clear_bit(idx, vport->mta_shadow);
3755
46a3df9f
S		 3756 return 0;
3757}
3758
40cca1c5
XW		 3759static int hclge_update_mta_status(struct hnae3_handle *handle)
3760{
3761 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
3762 struct hclge_vport *vport = hclge_get_vport(handle);
3763 struct net_device *netdev = handle->kinfo.netdev;
3764 struct netdev_hw_addr *ha;
3765 u16 tbl_idx;
3766
3767 memset(mta_status, 0, sizeof(mta_status));
3768
3769 /* update mta_status from mc addr list */
3770 netdev_for_each_mc_addr(ha, netdev) {
3771 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
3772 set_bit(tbl_idx, mta_status);
3773 }
3774
3775 return hclge_update_mta_status_common(vport, mta_status,
3776 0, HCLGE_MTA_TBL_SIZE, true);
3777}
3778
3779int hclge_update_mta_status_common(struct hclge_vport *vport,
3780 unsigned long *status,
3781 u16 idx,
3782 u16 count,
3783 bool update_filter)
3784{
3785 struct hclge_dev *hdev = vport->back;
3786 u16 update_max = idx + count;
3787 u16 check_max;
3788 int ret = 0;
3789 bool used;
3790 u16 i;
3791
3792 /* setup mta check range */
3793 if (update_filter) {
3794 i = 0;
3795 check_max = HCLGE_MTA_TBL_SIZE;
3796 } else {
3797 i = idx;
3798 check_max = update_max;
3799 }
3800
3801 used = false;
3802 /* check and update all mta item */
3803 for (; i < check_max; i++) {
3804 /* ignore unused item */
3805 if (!test_bit(i, vport->mta_shadow))
3806 continue;
3807
3808 /* if i in update range then update it */
3809 if (i >= idx && i < update_max)
3810 if (!test_bit(i - idx, status))
3811 hclge_set_mta_table_item(vport, i, false);
3812
3813 if (!used && test_bit(i, vport->mta_shadow))
3814 used = true;
3815 }
3816
3817 /* no longer use mta, disable it */
3818 if (vport->accept_mta_mc && update_filter && !used) {
3819 ret = hclge_cfg_func_mta_filter(hdev,
3820 vport->vport_id,
3821 false);
3822 if (ret)
3823 dev_err(&hdev->pdev->dev,
3824 "disable func mta filter fail ret=%d\n",
3825 ret);
3826 else
3827 vport->accept_mta_mc = false;
3828 }
3829
3830 return ret;
3831}
3832
46a3df9f 3833static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3834 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3835{
3836 struct hclge_dev *hdev = vport->back;
3837 struct hclge_desc desc;
3838 u8 resp_code;
a90bb9a5 3839 u16 retval;
46a3df9f
S		 3840 int ret;
3841
3842 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3843
d44f9b63 3844 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3845
3846 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3847 if (ret) {
3848 dev_err(&hdev->pdev->dev,
3849 "del mac addr failed for cmd_send, ret =%d.\n",
3850 ret);
3851 return ret;
3852 }
a90bb9a5
YL		 3853 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3854 retval = le16_to_cpu(desc.retval);
46a3df9f 3855
a90bb9a5 3856 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3857 HCLGE_MAC_VLAN_REMOVE);
3858}
3859
3860static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3861 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3862 struct hclge_desc *desc,
3863 bool is_mc)
3864{
3865 struct hclge_dev *hdev = vport->back;
3866 u8 resp_code;
a90bb9a5 3867 u16 retval;
46a3df9f
S		 3868 int ret;
3869
3870 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3871 if (is_mc) {
3872 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3873 memcpy(desc[0].data,
3874 req,
d44f9b63 3875 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3876 hclge_cmd_setup_basic_desc(&desc[1],
3877 HCLGE_OPC_MAC_VLAN_ADD,
3878 true);
3879 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3880 hclge_cmd_setup_basic_desc(&desc[2],
3881 HCLGE_OPC_MAC_VLAN_ADD,
3882 true);
3883 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3884 } else {
3885 memcpy(desc[0].data,
3886 req,
d44f9b63 3887 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3888 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3889 }
3890 if (ret) {
3891 dev_err(&hdev->pdev->dev,
3892 "lookup mac addr failed for cmd_send, ret =%d.\n",
3893 ret);
3894 return ret;
3895 }
a90bb9a5
YL		 3896 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3897 retval = le16_to_cpu(desc[0].retval);
46a3df9f 3898
a90bb9a5 3899 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3900 HCLGE_MAC_VLAN_LKUP);
3901}
3902
3903static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3904 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3905 struct hclge_desc *mc_desc)
3906{
3907 struct hclge_dev *hdev = vport->back;
3908 int cfg_status;
3909 u8 resp_code;
a90bb9a5 3910 u16 retval;
46a3df9f
S		 3911 int ret;
3912
3913 if (!mc_desc) {
3914 struct hclge_desc desc;
3915
3916 hclge_cmd_setup_basic_desc(&desc,
3917 HCLGE_OPC_MAC_VLAN_ADD,
3918 false);
d44f9b63
YL		 3919 memcpy(desc.data, req,
3920 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3921 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 3922 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3923 retval = le16_to_cpu(desc.retval);
3924
3925 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3926 resp_code,
3927 HCLGE_MAC_VLAN_ADD);
3928 } else {
c3b6f755 3929 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 3930 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3931 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 3932 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3933 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 3934 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3935 memcpy(mc_desc[0].data, req,
d44f9b63 3936 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3937 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 3938 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3939 retval = le16_to_cpu(mc_desc[0].retval);
3940
3941 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3942 resp_code,
3943 HCLGE_MAC_VLAN_ADD);
3944 }
3945
3946 if (ret) {
3947 dev_err(&hdev->pdev->dev,
3948 "add mac addr failed for cmd_send, ret =%d.\n",
3949 ret);
3950 return ret;
3951 }
3952
3953 return cfg_status;
3954}
3955
3956static int hclge_add_uc_addr(struct hnae3_handle *handle,
3957 const unsigned char *addr)
3958{
3959 struct hclge_vport *vport = hclge_get_vport(handle);
3960
3961 return hclge_add_uc_addr_common(vport, addr);
3962}
3963
3964int hclge_add_uc_addr_common(struct hclge_vport *vport,
3965 const unsigned char *addr)
3966{
3967 struct hclge_dev *hdev = vport->back;
d44f9b63 3968 struct hclge_mac_vlan_tbl_entry_cmd req;
d07b6bb4 3969 struct hclge_desc desc;
a90bb9a5 3970 u16 egress_port = 0;
aa7a795e 3971 int ret;
46a3df9f
S		 3972
3973 /* mac addr check */
3974 if (is_zero_ether_addr(addr) ||
3975 is_broadcast_ether_addr(addr) ||
3976 is_multicast_ether_addr(addr)) {
3977 dev_err(&hdev->pdev->dev,
3978 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3979 addr,
3980 is_zero_ether_addr(addr),
3981 is_broadcast_ether_addr(addr),
3982 is_multicast_ether_addr(addr));
3983 return -EINVAL;
3984 }
3985
3986 memset(&req, 0, sizeof(req));
e4e87715 3987 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 3988
e4e87715
PL		 3989 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
3990 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 3991
3992 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 3993
3994 hclge_prepare_mac_addr(&req, addr);
3995
d07b6bb4
JS		 3996 /* Lookup the mac address in the mac_vlan table, and add
3997 * it if the entry is inexistent. Repeated unicast entry
3998 * is not allowed in the mac vlan table.
3999 */
4000 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4001 if (ret == -ENOENT)
4002 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4003
4004 /* check if we just hit the duplicate */
4005 if (!ret)
4006 ret = -EINVAL;
4007
4008 dev_err(&hdev->pdev->dev,
4009 "PF failed to add unicast entry(%pM) in the MAC table\n",
4010 addr);
46a3df9f 4011
aa7a795e 4012 return ret;
46a3df9f
S		 4013}
4014
4015static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4016 const unsigned char *addr)
4017{
4018 struct hclge_vport *vport = hclge_get_vport(handle);
4019
4020 return hclge_rm_uc_addr_common(vport, addr);
4021}
4022
4023int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4024 const unsigned char *addr)
4025{
4026 struct hclge_dev *hdev = vport->back;
d44f9b63 4027 struct hclge_mac_vlan_tbl_entry_cmd req;
aa7a795e 4028 int ret;
46a3df9f
S		 4029
4030 /* mac addr check */
4031 if (is_zero_ether_addr(addr) ||
4032 is_broadcast_ether_addr(addr) ||
4033 is_multicast_ether_addr(addr)) {
4034 dev_dbg(&hdev->pdev->dev,
4035 "Remove mac err! invalid mac:%pM.\n",
4036 addr);
4037 return -EINVAL;
4038 }
4039
4040 memset(&req, 0, sizeof(req));
e4e87715
PL		 4041 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4042 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 4043 hclge_prepare_mac_addr(&req, addr);
aa7a795e 4044 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4045
aa7a795e 4046 return ret;
46a3df9f
S		 4047}
4048
4049static int hclge_add_mc_addr(struct hnae3_handle *handle,
4050 const unsigned char *addr)
4051{
4052 struct hclge_vport *vport = hclge_get_vport(handle);
4053
a10829c4 4054 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 4055}
4056
4057int hclge_add_mc_addr_common(struct hclge_vport *vport,
4058 const unsigned char *addr)
4059{
4060 struct hclge_dev *hdev = vport->back;
d44f9b63 4061 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4062 struct hclge_desc desc[3];
4063 u16 tbl_idx;
4064 int status;
4065
4066 /* mac addr check */
4067 if (!is_multicast_ether_addr(addr)) {
4068 dev_err(&hdev->pdev->dev,
4069 "Add mc mac err! invalid mac:%pM.\n",
4070 addr);
4071 return -EINVAL;
4072 }
4073 memset(&req, 0, sizeof(req));
e4e87715
PL		 4074 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4075 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4076 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 4077 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 4078 hclge_prepare_mac_addr(&req, addr);
4079 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4080 if (!status) {
4081 /* This mac addr exist, update VFID for it */
4082 hclge_update_desc_vfid(desc, vport->vport_id, false);
4083 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4084 } else {
4085 /* This mac addr do not exist, add new entry for it */
4086 memset(desc[0].data, 0, sizeof(desc[0].data));
4087 memset(desc[1].data, 0, sizeof(desc[0].data));
4088 memset(desc[2].data, 0, sizeof(desc[0].data));
4089 hclge_update_desc_vfid(desc, vport->vport_id, false);
4090 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4091 }
4092
40cca1c5
XW		 4093 /* If mc mac vlan table is full, use MTA table */
4094 if (status == -ENOSPC) {
4095 if (!vport->accept_mta_mc) {
4096 status = hclge_cfg_func_mta_filter(hdev,
4097 vport->vport_id,
4098 true);
4099 if (status) {
4100 dev_err(&hdev->pdev->dev,
4101 "set mta filter mode fail ret=%d\n",
4102 status);
4103 return status;
4104 }
4105 vport->accept_mta_mc = true;
4106 }
4107
4108 /* Set MTA table for this MAC address */
4109 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4110 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4111 }
46a3df9f
S		 4112
4113 return status;
4114}
4115
4116static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4117 const unsigned char *addr)
4118{
4119 struct hclge_vport *vport = hclge_get_vport(handle);
4120
4121 return hclge_rm_mc_addr_common(vport, addr);
4122}
4123
4124int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4125 const unsigned char *addr)
4126{
4127 struct hclge_dev *hdev = vport->back;
d44f9b63 4128 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4129 enum hclge_cmd_status status;
4130 struct hclge_desc desc[3];
46a3df9f
S		 4131
4132 /* mac addr check */
4133 if (!is_multicast_ether_addr(addr)) {
4134 dev_dbg(&hdev->pdev->dev,
4135 "Remove mc mac err! invalid mac:%pM.\n",
4136 addr);
4137 return -EINVAL;
4138 }
4139
4140 memset(&req, 0, sizeof(req));
e4e87715
PL		 4141 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4142 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4143 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 4144 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 4145 hclge_prepare_mac_addr(&req, addr);
4146 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4147 if (!status) {
4148 /* This mac addr exist, remove this handle's VFID for it */
4149 hclge_update_desc_vfid(desc, vport->vport_id, true);
4150
4151 if (hclge_is_all_function_id_zero(desc))
4152 /* All the vfid is zero, so need to delete this entry */
4153 status = hclge_remove_mac_vlan_tbl(vport, &req);
4154 else
4155 /* Not all the vfid is zero, update the vfid */
4156 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4157
4158 } else {
40cca1c5
XW		 4159 /* Maybe this mac address is in mta table, but it cannot be
4160 * deleted here because an entry of mta represents an address
4161 * range rather than a specific address. the delete action to
4162 * all entries will take effect in update_mta_status called by
4163 * hns3_nic_set_rx_mode.
4164 */
4165 status = 0;
46a3df9f
S		 4166 }
4167
46a3df9f
S		 4168 return status;
4169}
4170
f5aac71c
FL		 4171static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4172 u16 cmdq_resp, u8 resp_code)
4173{
4174#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4175#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4176#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4177#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4178
4179 int return_status;
4180
4181 if (cmdq_resp) {
4182 dev_err(&hdev->pdev->dev,
4183 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4184 cmdq_resp);
4185 return -EIO;
4186 }
4187
4188 switch (resp_code) {
4189 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4190 case HCLGE_ETHERTYPE_ALREADY_ADD:
4191 return_status = 0;
4192 break;
4193 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4194 dev_err(&hdev->pdev->dev,
4195 "add mac ethertype failed for manager table overflow.\n");
4196 return_status = -EIO;
4197 break;
4198 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4199 dev_err(&hdev->pdev->dev,
4200 "add mac ethertype failed for key conflict.\n");
4201 return_status = -EIO;
4202 break;
4203 default:
4204 dev_err(&hdev->pdev->dev,
4205 "add mac ethertype failed for undefined, code=%d.\n",
4206 resp_code);
4207 return_status = -EIO;
4208 }
4209
4210 return return_status;
4211}
4212
4213static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4214 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4215{
4216 struct hclge_desc desc;
4217 u8 resp_code;
4218 u16 retval;
4219 int ret;
4220
4221 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4222 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4223
4224 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4225 if (ret) {
4226 dev_err(&hdev->pdev->dev,
4227 "add mac ethertype failed for cmd_send, ret =%d.\n",
4228 ret);
4229 return ret;
4230 }
4231
4232 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4233 retval = le16_to_cpu(desc.retval);
4234
4235 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4236}
4237
4238static int init_mgr_tbl(struct hclge_dev *hdev)
4239{
4240 int ret;
4241 int i;
4242
4243 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4244 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4245 if (ret) {
4246 dev_err(&hdev->pdev->dev,
4247 "add mac ethertype failed, ret =%d.\n",
4248 ret);
4249 return ret;
4250 }
4251 }
4252
4253 return 0;
4254}
4255
46a3df9f
S		 4256static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4257{
4258 struct hclge_vport *vport = hclge_get_vport(handle);
4259 struct hclge_dev *hdev = vport->back;
4260
4261 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4262}
4263
59098055
FL		 4264static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4265 bool is_first)
46a3df9f
S		 4266{
4267 const unsigned char *new_addr = (const unsigned char *)p;
4268 struct hclge_vport *vport = hclge_get_vport(handle);
4269 struct hclge_dev *hdev = vport->back;
18838d0c 4270 int ret;
46a3df9f
S		 4271
4272 /* mac addr check */
4273 if (is_zero_ether_addr(new_addr) ||
4274 is_broadcast_ether_addr(new_addr) ||
4275 is_multicast_ether_addr(new_addr)) {
4276 dev_err(&hdev->pdev->dev,
4277 "Change uc mac err! invalid mac:%p.\n",
4278 new_addr);
4279 return -EINVAL;
4280 }
4281
59098055 4282 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4283 dev_warn(&hdev->pdev->dev,
59098055 4284 "remove old uc mac address fail.\n");
46a3df9f 4285
18838d0c
FL		 4286 ret = hclge_add_uc_addr(handle, new_addr);
4287 if (ret) {
4288 dev_err(&hdev->pdev->dev,
4289 "add uc mac address fail, ret =%d.\n",
4290 ret);
4291
59098055
FL		 4292 if (!is_first &&
4293 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4294 dev_err(&hdev->pdev->dev,
59098055 4295 "restore uc mac address fail.\n");
18838d0c
FL		 4296
4297 return -EIO;
46a3df9f
S		 4298 }
4299
e98d7183 4300 ret = hclge_pause_addr_cfg(hdev, new_addr);
18838d0c
FL		 4301 if (ret) {
4302 dev_err(&hdev->pdev->dev,
4303 "configure mac pause address fail, ret =%d.\n",
4304 ret);
4305 return -EIO;
4306 }
4307
4308 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4309
4310 return 0;
46a3df9f
S		 4311}
4312
26483246
XW		 4313static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
4314 int cmd)
4315{
4316 struct hclge_vport *vport = hclge_get_vport(handle);
4317 struct hclge_dev *hdev = vport->back;
4318
4319 if (!hdev->hw.mac.phydev)
4320 return -EOPNOTSUPP;
4321
4322 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
4323}
4324
46a3df9f
S		 4325static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4326 bool filter_en)
4327{
d44f9b63 4328 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4329 struct hclge_desc desc;
4330 int ret;
4331
4332 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4333
d44f9b63 4334 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4335 req->vlan_type = vlan_type;
4336 req->vlan_fe = filter_en;
4337
4338 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 4339 if (ret)
46a3df9f
S		 4340 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4341 ret);
46a3df9f 4342
3f639907 4343 return ret;
46a3df9f
S		 4344}
4345
391b5e93
JS		 4346#define HCLGE_FILTER_TYPE_VF 0
4347#define HCLGE_FILTER_TYPE_PORT 1
4348
4349static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4350{
4351 struct hclge_vport *vport = hclge_get_vport(handle);
4352 struct hclge_dev *hdev = vport->back;
4353
4354 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4355}
4356
dc8131d8
YL		 4357static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4358 bool is_kill, u16 vlan, u8 qos,
4359 __be16 proto)
46a3df9f
S		 4360{
4361#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4362 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4363 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4364 struct hclge_desc desc[2];
4365 u8 vf_byte_val;
4366 u8 vf_byte_off;
4367 int ret;
4368
4369 hclge_cmd_setup_basic_desc(&desc[0],
4370 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4371 hclge_cmd_setup_basic_desc(&desc[1],
4372 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4373
4374 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4375
4376 vf_byte_off = vfid / 8;
4377 vf_byte_val = 1 << (vfid % 8);
4378
d44f9b63
YL		 4379 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4380 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4381
a90bb9a5 4382 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4383 req0->vlan_cfg = is_kill;
4384
4385 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4386 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4387 else
4388 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4389
4390 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4391 if (ret) {
4392 dev_err(&hdev->pdev->dev,
4393 "Send vf vlan command fail, ret =%d.\n",
4394 ret);
4395 return ret;
4396 }
4397
4398 if (!is_kill) {
6c251711 4399#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4400 if (!req0->resp_code || req0->resp_code == 1)
4401 return 0;
4402
6c251711
YL		 4403 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4404 dev_warn(&hdev->pdev->dev,
4405 "vf vlan table is full, vf vlan filter is disabled\n");
4406 return 0;
4407 }
4408
46a3df9f
S		 4409 dev_err(&hdev->pdev->dev,
4410 "Add vf vlan filter fail, ret =%d.\n",
4411 req0->resp_code);
4412 } else {
41dafea2 4413#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
46a3df9f
S		 4414 if (!req0->resp_code)
4415 return 0;
4416
41dafea2
YL		 4417 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
4418 dev_warn(&hdev->pdev->dev,
4419 "vlan %d filter is not in vf vlan table\n",
4420 vlan);
4421 return 0;
4422 }
4423
46a3df9f
S		 4424 dev_err(&hdev->pdev->dev,
4425 "Kill vf vlan filter fail, ret =%d.\n",
4426 req0->resp_code);
4427 }
4428
4429 return -EIO;
4430}
4431
dc8131d8
YL		 4432static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4433 u16 vlan_id, bool is_kill)
46a3df9f 4434{
d44f9b63 4435 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4436 struct hclge_desc desc;
4437 u8 vlan_offset_byte_val;
4438 u8 vlan_offset_byte;
4439 u8 vlan_offset_160;
4440 int ret;
4441
4442 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4443
4444 vlan_offset_160 = vlan_id / 160;
4445 vlan_offset_byte = (vlan_id % 160) / 8;
4446 vlan_offset_byte_val = 1 << (vlan_id % 8);
4447
d44f9b63 4448 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4449 req->vlan_offset = vlan_offset_160;
4450 req->vlan_cfg = is_kill;
4451 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4452
4453 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
dc8131d8
YL		 4454 if (ret)
4455 dev_err(&hdev->pdev->dev,
4456 "port vlan command, send fail, ret =%d.\n", ret);
4457 return ret;
4458}
4459
4460static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4461 u16 vport_id, u16 vlan_id, u8 qos,
4462 bool is_kill)
4463{
4464 u16 vport_idx, vport_num = 0;
4465 int ret;
4466
daaa8521
YL		 4467 if (is_kill && !vlan_id)
4468 return 0;
4469
dc8131d8
YL		 4470 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4471 0, proto);
46a3df9f
S		 4472 if (ret) {
4473 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 4474 "Set %d vport vlan filter config fail, ret =%d.\n",
4475 vport_id, ret);
46a3df9f
S		 4476 return ret;
4477 }
4478
dc8131d8
YL		 4479 /* vlan 0 may be added twice when 8021q module is enabled */
4480 if (!is_kill && !vlan_id &&
4481 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4482 return 0;
4483
4484 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4485 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 4486 "Add port vlan failed, vport %d is already in vlan %d\n",
4487 vport_id, vlan_id);
4488 return -EINVAL;
46a3df9f
S		 4489 }
4490
dc8131d8
YL		 4491 if (is_kill &&
4492 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4493 dev_err(&hdev->pdev->dev,
4494 "Delete port vlan failed, vport %d is not in vlan %d\n",
4495 vport_id, vlan_id);
4496 return -EINVAL;
4497 }
4498
54e97d11 4499 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
dc8131d8
YL		 4500 vport_num++;
4501
4502 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4503 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4504 is_kill);
4505
4506 return ret;
4507}
4508
4509int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4510 u16 vlan_id, bool is_kill)
4511{
4512 struct hclge_vport *vport = hclge_get_vport(handle);
4513 struct hclge_dev *hdev = vport->back;
4514
4515 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4516 0, is_kill);
46a3df9f
S		 4517}
4518
4519static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4520 u16 vlan, u8 qos, __be16 proto)
4521{
4522 struct hclge_vport *vport = hclge_get_vport(handle);
4523 struct hclge_dev *hdev = vport->back;
4524
4525 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4526 return -EINVAL;
4527 if (proto != htons(ETH_P_8021Q))
4528 return -EPROTONOSUPPORT;
4529
dc8131d8 4530 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4531}
4532
5f6ea83f
PL		 4533static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4534{
4535 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4536 struct hclge_vport_vtag_tx_cfg_cmd *req;
4537 struct hclge_dev *hdev = vport->back;
4538 struct hclge_desc desc;
4539 int status;
4540
4541 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4542
4543 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4544 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4545 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e4e87715
PL		 4546 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4547 vcfg->accept_tag1 ? 1 : 0);
4548 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4549 vcfg->accept_untag1 ? 1 : 0);
4550 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4551 vcfg->accept_tag2 ? 1 : 0);
4552 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4553 vcfg->accept_untag2 ? 1 : 0);
4554 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4555 vcfg->insert_tag1_en ? 1 : 0);
4556 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4557 vcfg->insert_tag2_en ? 1 : 0);
4558 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
5f6ea83f
PL		 4559
4560 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4561 req->vf_bitmap[req->vf_offset] =
4562 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4563
4564 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4565 if (status)
4566 dev_err(&hdev->pdev->dev,
4567 "Send port txvlan cfg command fail, ret =%d\n",
4568 status);
4569
4570 return status;
4571}
4572
4573static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4574{
4575 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4576 struct hclge_vport_vtag_rx_cfg_cmd *req;
4577 struct hclge_dev *hdev = vport->back;
4578 struct hclge_desc desc;
4579 int status;
4580
4581 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4582
4583 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e4e87715
PL		 4584 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4585 vcfg->strip_tag1_en ? 1 : 0);
4586 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4587 vcfg->strip_tag2_en ? 1 : 0);
4588 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4589 vcfg->vlan1_vlan_prionly ? 1 : 0);
4590 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4591 vcfg->vlan2_vlan_prionly ? 1 : 0);
5f6ea83f
PL		 4592
4593 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4594 req->vf_bitmap[req->vf_offset] =
4595 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4596
4597 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4598 if (status)
4599 dev_err(&hdev->pdev->dev,
4600 "Send port rxvlan cfg command fail, ret =%d\n",
4601 status);
4602
4603 return status;
4604}
4605
4606static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4607{
4608 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4609 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4610 struct hclge_desc desc;
4611 int status;
4612
4613 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4614 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4615 rx_req->ot_fst_vlan_type =
4616 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4617 rx_req->ot_sec_vlan_type =
4618 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4619 rx_req->in_fst_vlan_type =
4620 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4621 rx_req->in_sec_vlan_type =
4622 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4623
4624 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4625 if (status) {
4626 dev_err(&hdev->pdev->dev,
4627 "Send rxvlan protocol type command fail, ret =%d\n",
4628 status);
4629 return status;
4630 }
4631
4632 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4633
4634 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4635 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4636 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4637
4638 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4639 if (status)
4640 dev_err(&hdev->pdev->dev,
4641 "Send txvlan protocol type command fail, ret =%d\n",
4642 status);
4643
4644 return status;
4645}
4646
46a3df9f
S		 4647static int hclge_init_vlan_config(struct hclge_dev *hdev)
4648{
5f6ea83f
PL		 4649#define HCLGE_DEF_VLAN_TYPE 0x8100
4650
5e43aef8 4651 struct hnae3_handle *handle;
5f6ea83f 4652 struct hclge_vport *vport;
46a3df9f 4653 int ret;
5f6ea83f
PL		 4654 int i;
4655
4656 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4657 if (ret)
4658 return ret;
46a3df9f 4659
5f6ea83f 4660 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4661 if (ret)
4662 return ret;
4663
5f6ea83f
PL		 4664 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4665 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4666 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4667 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4668 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4669 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4670
4671 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4672 if (ret)
4673 return ret;
46a3df9f 4674
5f6ea83f
PL		 4675 for (i = 0; i < hdev->num_alloc_vport; i++) {
4676 vport = &hdev->vport[i];
dcb35cce
PL		 4677 vport->txvlan_cfg.accept_tag1 = true;
4678 vport->txvlan_cfg.accept_untag1 = true;
4679
4680 /* accept_tag2 and accept_untag2 are not supported on
4681 * pdev revision(0x20), new revision support them. The
4682 * value of this two fields will not return error when driver
4683 * send command to fireware in revision(0x20).
4684 * This two fields can not configured by user.
4685 */
4686 vport->txvlan_cfg.accept_tag2 = true;
4687 vport->txvlan_cfg.accept_untag2 = true;
4688
5f6ea83f
PL		 4689 vport->txvlan_cfg.insert_tag1_en = false;
4690 vport->txvlan_cfg.insert_tag2_en = false;
4691 vport->txvlan_cfg.default_tag1 = 0;
4692 vport->txvlan_cfg.default_tag2 = 0;
4693
4694 ret = hclge_set_vlan_tx_offload_cfg(vport);
4695 if (ret)
4696 return ret;
4697
4698 vport->rxvlan_cfg.strip_tag1_en = false;
4699 vport->rxvlan_cfg.strip_tag2_en = true;
4700 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4701 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4702
4703 ret = hclge_set_vlan_rx_offload_cfg(vport);
4704 if (ret)
4705 return ret;
4706 }
4707
5e43aef8 4708 handle = &hdev->vport[0].nic;
dc8131d8 4709 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4710}
4711
b2641e2a 4712int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
052ece6d
PL		 4713{
4714 struct hclge_vport *vport = hclge_get_vport(handle);
4715
4716 vport->rxvlan_cfg.strip_tag1_en = false;
4717 vport->rxvlan_cfg.strip_tag2_en = enable;
4718 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4719 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4720
4721 return hclge_set_vlan_rx_offload_cfg(vport);
4722}
4723
dd72140c 4724static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 4725{
d44f9b63 4726 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 4727 struct hclge_desc desc;
2866ccb2 4728 int max_frm_size;
46a3df9f
S		 4729 int ret;
4730
2866ccb2
FL		 4731 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4732
4733 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4734 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4735 return -EINVAL;
4736
2866ccb2
FL		 4737 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4738
46a3df9f
S		 4739 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4740
d44f9b63 4741 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
2866ccb2 4742 req->max_frm_size = cpu_to_le16(max_frm_size);
8fc7346c 4743 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f
S		 4744
4745 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 4746 if (ret)
46a3df9f 4747 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3f639907
JS		 4748 else
4749 hdev->mps = max_frm_size;
2866ccb2 4750
3f639907 4751 return ret;
46a3df9f
S		 4752}
4753
dd72140c
FL		 4754static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4755{
4756 struct hclge_vport *vport = hclge_get_vport(handle);
4757 struct hclge_dev *hdev = vport->back;
4758 int ret;
4759
4760 ret = hclge_set_mac_mtu(hdev, new_mtu);
4761 if (ret) {
4762 dev_err(&hdev->pdev->dev,
4763 "Change mtu fail, ret =%d\n", ret);
4764 return ret;
4765 }
4766
4767 ret = hclge_buffer_alloc(hdev);
4768 if (ret)
4769 dev_err(&hdev->pdev->dev,
4770 "Allocate buffer fail, ret =%d\n", ret);
4771
4772 return ret;
4773}
4774
46a3df9f
S		 4775static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4776 bool enable)
4777{
d44f9b63 4778 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4779 struct hclge_desc desc;
4780 int ret;
4781
4782 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4783
d44f9b63 4784 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 4785 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e4e87715 4786 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 4787
4788 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4789 if (ret) {
4790 dev_err(&hdev->pdev->dev,
4791 "Send tqp reset cmd error, status =%d\n", ret);
4792 return ret;
4793 }
4794
4795 return 0;
4796}
4797
4798static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4799{
d44f9b63 4800 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4801 struct hclge_desc desc;
4802 int ret;
4803
4804 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4805
d44f9b63 4806 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4807 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4808
4809 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4810 if (ret) {
4811 dev_err(&hdev->pdev->dev,
4812 "Get reset status error, status =%d\n", ret);
4813 return ret;
4814 }
4815
e4e87715 4816 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 4817}
4818
814e0274
PL		 4819static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
4820 u16 queue_id)
4821{
4822 struct hnae3_queue *queue;
4823 struct hclge_tqp *tqp;
4824
4825 queue = handle->kinfo.tqp[queue_id];
4826 tqp = container_of(queue, struct hclge_tqp, q);
4827
4828 return tqp->index;
4829}
4830
84e095d6 4831void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 4832{
4833 struct hclge_vport *vport = hclge_get_vport(handle);
4834 struct hclge_dev *hdev = vport->back;
4835 int reset_try_times = 0;
4836 int reset_status;
814e0274 4837 u16 queue_gid;
46a3df9f
S		 4838 int ret;
4839
b50ae26c
PL		 4840 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
4841 return;
4842
814e0274
PL		 4843 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
4844
46a3df9f
S		 4845 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4846 if (ret) {
4847 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4848 return;
4849 }
4850
814e0274 4851 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 4852 if (ret) {
4853 dev_warn(&hdev->pdev->dev,
4854 "Send reset tqp cmd fail, ret = %d\n", ret);
4855 return;
4856 }
4857
4858 reset_try_times = 0;
4859 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4860 /* Wait for tqp hw reset */
4861 msleep(20);
814e0274 4862 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 4863 if (reset_status)
4864 break;
4865 }
4866
4867 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4868 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4869 return;
4870 }
4871
814e0274 4872 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 4873 if (ret) {
4874 dev_warn(&hdev->pdev->dev,
4875 "Deassert the soft reset fail, ret = %d\n", ret);
4876 return;
4877 }
4878}
4879
1a426f8b
PL		 4880void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
4881{
4882 struct hclge_dev *hdev = vport->back;
4883 int reset_try_times = 0;
4884 int reset_status;
4885 u16 queue_gid;
4886 int ret;
4887
4888 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
4889
4890 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
4891 if (ret) {
4892 dev_warn(&hdev->pdev->dev,
4893 "Send reset tqp cmd fail, ret = %d\n", ret);
4894 return;
4895 }
4896
4897 reset_try_times = 0;
4898 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4899 /* Wait for tqp hw reset */
4900 msleep(20);
4901 reset_status = hclge_get_reset_status(hdev, queue_gid);
4902 if (reset_status)
4903 break;
4904 }
4905
4906 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4907 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4908 return;
4909 }
4910
4911 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
4912 if (ret)
4913 dev_warn(&hdev->pdev->dev,
4914 "Deassert the soft reset fail, ret = %d\n", ret);
4915}
4916
46a3df9f
S		 4917static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4918{
4919 struct hclge_vport *vport = hclge_get_vport(handle);
4920 struct hclge_dev *hdev = vport->back;
4921
4922 return hdev->fw_version;
4923}
4924
61387774
PL		 4925static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4926{
4927 struct phy_device *phydev = hdev->hw.mac.phydev;
4928
4929 if (!phydev)
4930 return;
4931
70814e81 4932 phy_set_asym_pause(phydev, rx_en, tx_en);
61387774
PL		 4933}
4934
4935static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4936{
61387774
PL		 4937 int ret;
4938
4939 if (rx_en && tx_en)
40173a2e 4940 hdev->fc_mode_last_time = HCLGE_FC_FULL;
61387774 4941 else if (rx_en && !tx_en)
40173a2e 4942 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
61387774 4943 else if (!rx_en && tx_en)
40173a2e 4944 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
61387774 4945 else
40173a2e 4946 hdev->fc_mode_last_time = HCLGE_FC_NONE;
61387774 4947
40173a2e 4948 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
61387774 4949 return 0;
61387774
PL		 4950
4951 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4952 if (ret) {
4953 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4954 ret);
4955 return ret;
4956 }
4957
40173a2e 4958 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
61387774
PL		 4959
4960 return 0;
4961}
4962
1770a7a3
PL		 4963int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4964{
4965 struct phy_device *phydev = hdev->hw.mac.phydev;
4966 u16 remote_advertising = 0;
4967 u16 local_advertising = 0;
4968 u32 rx_pause, tx_pause;
4969 u8 flowctl;
4970
4971 if (!phydev->link || !phydev->autoneg)
4972 return 0;
4973
4974 if (phydev->advertising & ADVERTISED_Pause)
4975 local_advertising = ADVERTISE_PAUSE_CAP;
4976
4977 if (phydev->advertising & ADVERTISED_Asym_Pause)
4978 local_advertising |= ADVERTISE_PAUSE_ASYM;
4979
4980 if (phydev->pause)
4981 remote_advertising = LPA_PAUSE_CAP;
4982
4983 if (phydev->asym_pause)
4984 remote_advertising |= LPA_PAUSE_ASYM;
4985
4986 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
4987 remote_advertising);
4988 tx_pause = flowctl & FLOW_CTRL_TX;
4989 rx_pause = flowctl & FLOW_CTRL_RX;
4990
4991 if (phydev->duplex == HCLGE_MAC_HALF) {
4992 tx_pause = 0;
4993 rx_pause = 0;
4994 }
4995
4996 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
4997}
4998
46a3df9f
S		 4999static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5000 u32 *rx_en, u32 *tx_en)
5001{
5002 struct hclge_vport *vport = hclge_get_vport(handle);
5003 struct hclge_dev *hdev = vport->back;
5004
5005 *auto_neg = hclge_get_autoneg(handle);
5006
5007 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5008 *rx_en = 0;
5009 *tx_en = 0;
5010 return;
5011 }
5012
5013 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5014 *rx_en = 1;
5015 *tx_en = 0;
5016 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5017 *tx_en = 1;
5018 *rx_en = 0;
5019 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5020 *rx_en = 1;
5021 *tx_en = 1;
5022 } else {
5023 *rx_en = 0;
5024 *tx_en = 0;
5025 }
5026}
5027
61387774
PL		 5028static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5029 u32 rx_en, u32 tx_en)
5030{
5031 struct hclge_vport *vport = hclge_get_vport(handle);
5032 struct hclge_dev *hdev = vport->back;
5033 struct phy_device *phydev = hdev->hw.mac.phydev;
5034 u32 fc_autoneg;
5035
61387774
PL		 5036 fc_autoneg = hclge_get_autoneg(handle);
5037 if (auto_neg != fc_autoneg) {
5038 dev_info(&hdev->pdev->dev,
5039 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5040 return -EOPNOTSUPP;
5041 }
5042
5043 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5044 dev_info(&hdev->pdev->dev,
5045 "Priority flow control enabled. Cannot set link flow control.\n");
5046 return -EOPNOTSUPP;
5047 }
5048
5049 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5050
5051 if (!fc_autoneg)
5052 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5053
0c963e8c
FL		 5054 /* Only support flow control negotiation for netdev with
5055 * phy attached for now.
5056 */
5057 if (!phydev)
5058 return -EOPNOTSUPP;
5059
61387774
PL		 5060 return phy_start_aneg(phydev);
5061}
5062
46a3df9f
S		 5063static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5064 u8 *auto_neg, u32 *speed, u8 *duplex)
5065{
5066 struct hclge_vport *vport = hclge_get_vport(handle);
5067 struct hclge_dev *hdev = vport->back;
5068
5069 if (speed)
5070 *speed = hdev->hw.mac.speed;
5071 if (duplex)
5072 *duplex = hdev->hw.mac.duplex;
5073 if (auto_neg)
5074 *auto_neg = hdev->hw.mac.autoneg;
5075}
5076
5077static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5078{
5079 struct hclge_vport *vport = hclge_get_vport(handle);
5080 struct hclge_dev *hdev = vport->back;
5081
5082 if (media_type)
5083 *media_type = hdev->hw.mac.media_type;
5084}
5085
5086static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5087 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5088{
5089 struct hclge_vport *vport = hclge_get_vport(handle);
5090 struct hclge_dev *hdev = vport->back;
5091 struct phy_device *phydev = hdev->hw.mac.phydev;
5092 int mdix_ctrl, mdix, retval, is_resolved;
5093
5094 if (!phydev) {
5095 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5096 *tp_mdix = ETH_TP_MDI_INVALID;
5097 return;
5098 }
5099
5100 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5101
5102 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e4e87715
PL		 5103 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5104 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 5105
5106 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e4e87715
PL		 5107 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5108 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 5109
5110 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5111
5112 switch (mdix_ctrl) {
5113 case 0x0:
5114 *tp_mdix_ctrl = ETH_TP_MDI;
5115 break;
5116 case 0x1:
5117 *tp_mdix_ctrl = ETH_TP_MDI_X;
5118 break;
5119 case 0x3:
5120 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5121 break;
5122 default:
5123 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5124 break;
5125 }
5126
5127 if (!is_resolved)
5128 *tp_mdix = ETH_TP_MDI_INVALID;
5129 else if (mdix)
5130 *tp_mdix = ETH_TP_MDI_X;
5131 else
5132 *tp_mdix = ETH_TP_MDI;
5133}
5134
b01b7cf1
FL		 5135static int hclge_init_instance_hw(struct hclge_dev *hdev)
5136{
5137 return hclge_mac_connect_phy(hdev);
5138}
5139
5140static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
5141{
5142 hclge_mac_disconnect_phy(hdev);
5143}
5144
46a3df9f
S		 5145static int hclge_init_client_instance(struct hnae3_client *client,
5146 struct hnae3_ae_dev *ae_dev)
5147{
5148 struct hclge_dev *hdev = ae_dev->priv;
5149 struct hclge_vport *vport;
5150 int i, ret;
5151
5152 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5153 vport = &hdev->vport[i];
5154
5155 switch (client->type) {
5156 case HNAE3_CLIENT_KNIC:
5157
5158 hdev->nic_client = client;
5159 vport->nic.client = client;
5160 ret = client->ops->init_instance(&vport->nic);
5161 if (ret)
99a6993a 5162 return ret;
46a3df9f 5163
b01b7cf1
FL		 5164 ret = hclge_init_instance_hw(hdev);
5165 if (ret) {
5166 client->ops->uninit_instance(&vport->nic,
5167 0);
5168 return ret;
5169 }
5170
46a3df9f 5171 if (hdev->roce_client &&
e92a0843 5172 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5173 struct hnae3_client *rc = hdev->roce_client;
5174
5175 ret = hclge_init_roce_base_info(vport);
5176 if (ret)
99a6993a 5177 return ret;
46a3df9f
S		 5178
5179 ret = rc->ops->init_instance(&vport->roce);
5180 if (ret)
99a6993a 5181 return ret;
46a3df9f
S		 5182 }
5183
5184 break;
5185 case HNAE3_CLIENT_UNIC:
5186 hdev->nic_client = client;
5187 vport->nic.client = client;
5188
5189 ret = client->ops->init_instance(&vport->nic);
5190 if (ret)
99a6993a 5191 return ret;
46a3df9f
S		 5192
5193 break;
5194 case HNAE3_CLIENT_ROCE:
e92a0843 5195 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5196 hdev->roce_client = client;
5197 vport->roce.client = client;
5198 }
5199
3a46f34d 5200 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5201 ret = hclge_init_roce_base_info(vport);
5202 if (ret)
99a6993a 5203 return ret;
46a3df9f
S		 5204
5205 ret = client->ops->init_instance(&vport->roce);
5206 if (ret)
99a6993a 5207 return ret;
46a3df9f
S		 5208 }
5209 }
5210 }
5211
5212 return 0;
46a3df9f
S		 5213}
5214
5215static void hclge_uninit_client_instance(struct hnae3_client *client,
5216 struct hnae3_ae_dev *ae_dev)
5217{
5218 struct hclge_dev *hdev = ae_dev->priv;
5219 struct hclge_vport *vport;
5220 int i;
5221
5222 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5223 vport = &hdev->vport[i];
a17dcf3f 5224 if (hdev->roce_client) {
46a3df9f
S		 5225 hdev->roce_client->ops->uninit_instance(&vport->roce,
5226 0);
a17dcf3f
L		 5227 hdev->roce_client = NULL;
5228 vport->roce.client = NULL;
5229 }
46a3df9f
S		 5230 if (client->type == HNAE3_CLIENT_ROCE)
5231 return;
a17dcf3f 5232 if (client->ops->uninit_instance) {
b01b7cf1 5233 hclge_uninit_instance_hw(hdev);
46a3df9f 5234 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5235 hdev->nic_client = NULL;
5236 vport->nic.client = NULL;
5237 }
46a3df9f
S		 5238 }
5239}
5240
5241static int hclge_pci_init(struct hclge_dev *hdev)
5242{
5243 struct pci_dev *pdev = hdev->pdev;
5244 struct hclge_hw *hw;
5245 int ret;
5246
5247 ret = pci_enable_device(pdev);
5248 if (ret) {
5249 dev_err(&pdev->dev, "failed to enable PCI device\n");
3e249d3b 5250 return ret;
46a3df9f
S		 5251 }
5252
5253 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5254 if (ret) {
5255 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5256 if (ret) {
5257 dev_err(&pdev->dev,
5258 "can't set consistent PCI DMA");
5259 goto err_disable_device;
5260 }
5261 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5262 }
5263
5264 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5265 if (ret) {
5266 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5267 goto err_disable_device;
5268 }
5269
5270 pci_set_master(pdev);
5271 hw = &hdev->hw;
46a3df9f
S		 5272 hw->io_base = pcim_iomap(pdev, 2, 0);
5273 if (!hw->io_base) {
5274 dev_err(&pdev->dev, "Can't map configuration register space\n");
5275 ret = -ENOMEM;
5276 goto err_clr_master;
5277 }
5278
709eb41a
L		 5279 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5280
46a3df9f
S		 5281 return 0;
5282err_clr_master:
5283 pci_clear_master(pdev);
5284 pci_release_regions(pdev);
5285err_disable_device:
5286 pci_disable_device(pdev);
46a3df9f
S		 5287
5288 return ret;
5289}
5290
5291static void hclge_pci_uninit(struct hclge_dev *hdev)
5292{
5293 struct pci_dev *pdev = hdev->pdev;
5294
6a814413 5295 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5296 pci_free_irq_vectors(pdev);
46a3df9f
S		 5297 pci_clear_master(pdev);
5298 pci_release_mem_regions(pdev);
5299 pci_disable_device(pdev);
5300}
5301
48569cda
PL		 5302static void hclge_state_init(struct hclge_dev *hdev)
5303{
5304 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5305 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5306 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5307 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5308 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5309 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5310}
5311
5312static void hclge_state_uninit(struct hclge_dev *hdev)
5313{
5314 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5315
5316 if (hdev->service_timer.function)
5317 del_timer_sync(&hdev->service_timer);
5318 if (hdev->service_task.func)
5319 cancel_work_sync(&hdev->service_task);
5320 if (hdev->rst_service_task.func)
5321 cancel_work_sync(&hdev->rst_service_task);
5322 if (hdev->mbx_service_task.func)
5323 cancel_work_sync(&hdev->mbx_service_task);
5324}
5325
46a3df9f
S		 5326static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5327{
5328 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5329 struct hclge_dev *hdev;
5330 int ret;
5331
5332 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5333 if (!hdev) {
5334 ret = -ENOMEM;
ffd5656e 5335 goto out;
46a3df9f
S		 5336 }
5337
46a3df9f
S		 5338 hdev->pdev = pdev;
5339 hdev->ae_dev = ae_dev;
4ed340ab 5340 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 5341 ae_dev->priv = hdev;
5342
46a3df9f
S		 5343 ret = hclge_pci_init(hdev);
5344 if (ret) {
5345 dev_err(&pdev->dev, "PCI init failed\n");
ffd5656e 5346 goto out;
46a3df9f
S		 5347 }
5348
3efb960f
L		 5349 /* Firmware command queue initialize */
5350 ret = hclge_cmd_queue_init(hdev);
5351 if (ret) {
5352 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
ffd5656e 5353 goto err_pci_uninit;
3efb960f
L		 5354 }
5355
5356 /* Firmware command initialize */
46a3df9f
S		 5357 ret = hclge_cmd_init(hdev);
5358 if (ret)
ffd5656e 5359 goto err_cmd_uninit;
46a3df9f
S		 5360
5361 ret = hclge_get_cap(hdev);
5362 if (ret) {
e00e2197
CIK		 5363 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5364 ret);
ffd5656e 5365 goto err_cmd_uninit;
46a3df9f
S		 5366 }
5367
5368 ret = hclge_configure(hdev);
5369 if (ret) {
5370 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
ffd5656e 5371 goto err_cmd_uninit;
46a3df9f
S		 5372 }
5373
887c3820 5374 ret = hclge_init_msi(hdev);
46a3df9f 5375 if (ret) {
887c3820 5376 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
ffd5656e 5377 goto err_cmd_uninit;
46a3df9f
S		 5378 }
5379
466b0c00
L		 5380 ret = hclge_misc_irq_init(hdev);
5381 if (ret) {
5382 dev_err(&pdev->dev,
5383 "Misc IRQ(vector0) init error, ret = %d.\n",
5384 ret);
ffd5656e 5385 goto err_msi_uninit;
466b0c00
L		 5386 }
5387
46a3df9f
S		 5388 ret = hclge_alloc_tqps(hdev);
5389 if (ret) {
5390 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
ffd5656e 5391 goto err_msi_irq_uninit;
46a3df9f
S		 5392 }
5393
5394 ret = hclge_alloc_vport(hdev);
5395 if (ret) {
5396 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
ffd5656e 5397 goto err_msi_irq_uninit;
46a3df9f
S		 5398 }
5399
7df7dad6
L		 5400 ret = hclge_map_tqp(hdev);
5401 if (ret) {
5402 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
2312e050 5403 goto err_msi_irq_uninit;
7df7dad6
L		 5404 }
5405
c5ef83cb
HT		 5406 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5407 ret = hclge_mac_mdio_config(hdev);
5408 if (ret) {
5409 dev_err(&hdev->pdev->dev,
5410 "mdio config fail ret=%d\n", ret);
2312e050 5411 goto err_msi_irq_uninit;
c5ef83cb 5412 }
cf9cca2d 5413 }
5414
46a3df9f
S		 5415 ret = hclge_mac_init(hdev);
5416 if (ret) {
5417 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
ffd5656e 5418 goto err_mdiobus_unreg;
46a3df9f 5419 }
46a3df9f
S		 5420
5421 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5422 if (ret) {
5423 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
ffd5656e 5424 goto err_mdiobus_unreg;
46a3df9f
S		 5425 }
5426
46a3df9f
S		 5427 ret = hclge_init_vlan_config(hdev);
5428 if (ret) {
5429 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
ffd5656e 5430 goto err_mdiobus_unreg;
46a3df9f
S		 5431 }
5432
5433 ret = hclge_tm_schd_init(hdev);
5434 if (ret) {
5435 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
ffd5656e 5436 goto err_mdiobus_unreg;
68ece54e
YL		 5437 }
5438
268f5dfa 5439 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5440 ret = hclge_rss_init_hw(hdev);
5441 if (ret) {
5442 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
ffd5656e 5443 goto err_mdiobus_unreg;
46a3df9f
S		 5444 }
5445
f5aac71c
FL		 5446 ret = init_mgr_tbl(hdev);
5447 if (ret) {
5448 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
ffd5656e 5449 goto err_mdiobus_unreg;
f5aac71c
FL		 5450 }
5451
cacde272
YL		 5452 hclge_dcb_ops_set(hdev);
5453
d039ef68 5454 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5455 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 5456 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
c1a81619 5457 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5458
8e52a602
XW		 5459 hclge_clear_all_event_cause(hdev);
5460
466b0c00
L		 5461 /* Enable MISC vector(vector0) */
5462 hclge_enable_vector(&hdev->misc_vector, true);
5463
48569cda 5464 hclge_state_init(hdev);
46a3df9f
S		 5465
5466 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5467 return 0;
5468
ffd5656e
HT		 5469err_mdiobus_unreg:
5470 if (hdev->hw.mac.phydev)
5471 mdiobus_unregister(hdev->hw.mac.mdio_bus);
ffd5656e
HT		 5472err_msi_irq_uninit:
5473 hclge_misc_irq_uninit(hdev);
5474err_msi_uninit:
5475 pci_free_irq_vectors(pdev);
5476err_cmd_uninit:
5477 hclge_destroy_cmd_queue(&hdev->hw);
5478err_pci_uninit:
6a814413 5479 pcim_iounmap(pdev, hdev->hw.io_base);
ffd5656e 5480 pci_clear_master(pdev);
46a3df9f 5481 pci_release_regions(pdev);
ffd5656e 5482 pci_disable_device(pdev);
ffd5656e 5483out:
46a3df9f
S		 5484 return ret;
5485}
5486
c6dc5213 5487static void hclge_stats_clear(struct hclge_dev *hdev)
5488{
5489 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5490}
5491
4ed340ab
L		 5492static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5493{
5494 struct hclge_dev *hdev = ae_dev->priv;
5495 struct pci_dev *pdev = ae_dev->pdev;
5496 int ret;
5497
5498 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5499
c6dc5213 5500 hclge_stats_clear(hdev);
dc8131d8 5501 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5502
4ed340ab
L		 5503 ret = hclge_cmd_init(hdev);
5504 if (ret) {
5505 dev_err(&pdev->dev, "Cmd queue init failed\n");
5506 return ret;
5507 }
5508
5509 ret = hclge_get_cap(hdev);
5510 if (ret) {
5511 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5512 ret);
5513 return ret;
5514 }
5515
5516 ret = hclge_configure(hdev);
5517 if (ret) {
5518 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5519 return ret;
5520 }
5521
5522 ret = hclge_map_tqp(hdev);
5523 if (ret) {
5524 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5525 return ret;
5526 }
5527
5528 ret = hclge_mac_init(hdev);
5529 if (ret) {
5530 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5531 return ret;
5532 }
5533
4ed340ab
L		 5534 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5535 if (ret) {
5536 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5537 return ret;
5538 }
5539
5540 ret = hclge_init_vlan_config(hdev);
5541 if (ret) {
5542 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5543 return ret;
5544 }
5545
f31c1ba6 5546 ret = hclge_tm_init_hw(hdev);
4ed340ab 5547 if (ret) {
f31c1ba6 5548 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5549 return ret;
5550 }
5551
5552 ret = hclge_rss_init_hw(hdev);
5553 if (ret) {
5554 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5555 return ret;
5556 }
5557
4ed340ab
L		 5558 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5559 HCLGE_DRIVER_NAME);
5560
5561 return 0;
5562}
5563
46a3df9f
S		 5564static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5565{
5566 struct hclge_dev *hdev = ae_dev->priv;
5567 struct hclge_mac *mac = &hdev->hw.mac;
5568
48569cda 5569 hclge_state_uninit(hdev);
46a3df9f
S		 5570
5571 if (mac->phydev)
5572 mdiobus_unregister(mac->mdio_bus);
5573
466b0c00
L		 5574 /* Disable MISC vector(vector0) */
5575 hclge_enable_vector(&hdev->misc_vector, false);
8e52a602
XW		 5576 synchronize_irq(hdev->misc_vector.vector_irq);
5577
46a3df9f 5578 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 5579 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5580 hclge_pci_uninit(hdev);
5581 ae_dev->priv = NULL;
5582}
5583
482d2e9c
PL		 5584static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5585{
5586 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5587 struct hclge_vport *vport = hclge_get_vport(handle);
5588 struct hclge_dev *hdev = vport->back;
5589
5590 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5591}
5592
5593static void hclge_get_channels(struct hnae3_handle *handle,
5594 struct ethtool_channels *ch)
5595{
5596 struct hclge_vport *vport = hclge_get_vport(handle);
5597
5598 ch->max_combined = hclge_get_max_channels(handle);
5599 ch->other_count = 1;
5600 ch->max_other = 1;
5601 ch->combined_count = vport->alloc_tqps;
5602}
5603
09f2af64
PL		 5604static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5605 u16 *free_tqps, u16 *max_rss_size)
5606{
5607 struct hclge_vport *vport = hclge_get_vport(handle);
5608 struct hclge_dev *hdev = vport->back;
5609 u16 temp_tqps = 0;
5610 int i;
5611
5612 for (i = 0; i < hdev->num_tqps; i++) {
5613 if (!hdev->htqp[i].alloced)
5614 temp_tqps++;
5615 }
5616 *free_tqps = temp_tqps;
5617 *max_rss_size = hdev->rss_size_max;
5618}
5619
5620static void hclge_release_tqp(struct hclge_vport *vport)
5621{
5622 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5623 struct hclge_dev *hdev = vport->back;
5624 int i;
5625
5626 for (i = 0; i < kinfo->num_tqps; i++) {
5627 struct hclge_tqp *tqp =
5628 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5629
5630 tqp->q.handle = NULL;
5631 tqp->q.tqp_index = 0;
5632 tqp->alloced = false;
5633 }
5634
5635 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5636 kinfo->tqp = NULL;
5637}
5638
5639static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5640{
5641 struct hclge_vport *vport = hclge_get_vport(handle);
5642 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5643 struct hclge_dev *hdev = vport->back;
5644 int cur_rss_size = kinfo->rss_size;
5645 int cur_tqps = kinfo->num_tqps;
5646 u16 tc_offset[HCLGE_MAX_TC_NUM];
5647 u16 tc_valid[HCLGE_MAX_TC_NUM];
5648 u16 tc_size[HCLGE_MAX_TC_NUM];
5649 u16 roundup_size;
5650 u32 *rss_indir;
5651 int ret, i;
5652
fdace1bc 5653 /* Free old tqps, and reallocate with new tqp number when nic setup */
09f2af64
PL		 5654 hclge_release_tqp(vport);
5655
128b900d 5656 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
09f2af64
PL		 5657 if (ret) {
5658 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5659 return ret;
5660 }
5661
5662 ret = hclge_map_tqp_to_vport(hdev, vport);
5663 if (ret) {
5664 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5665 return ret;
5666 }
5667
5668 ret = hclge_tm_schd_init(hdev);
5669 if (ret) {
5670 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5671 return ret;
5672 }
5673
5674 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5675 roundup_size = ilog2(roundup_size);
5676 /* Set the RSS TC mode according to the new RSS size */
5677 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5678 tc_valid[i] = 0;
5679
5680 if (!(hdev->hw_tc_map & BIT(i)))
5681 continue;
5682
5683 tc_valid[i] = 1;
5684 tc_size[i] = roundup_size;
5685 tc_offset[i] = kinfo->rss_size * i;
5686 }
5687 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5688 if (ret)
5689 return ret;
5690
5691 /* Reinitializes the rss indirect table according to the new RSS size */
5692 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5693 if (!rss_indir)
5694 return -ENOMEM;
5695
5696 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5697 rss_indir[i] = i % kinfo->rss_size;
5698
5699 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5700 if (ret)
5701 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5702 ret);
5703
5704 kfree(rss_indir);
5705
5706 if (!ret)
5707 dev_info(&hdev->pdev->dev,
5708 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5709 cur_rss_size, kinfo->rss_size,
5710 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5711
5712 return ret;
5713}
5714
77b34110
FL		 5715static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5716 u32 *regs_num_64_bit)
5717{
5718 struct hclge_desc desc;
5719 u32 total_num;
5720 int ret;
5721
5722 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5723 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5724 if (ret) {
5725 dev_err(&hdev->pdev->dev,
5726 "Query register number cmd failed, ret = %d.\n", ret);
5727 return ret;
5728 }
5729
5730 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5731 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5732
5733 total_num = *regs_num_32_bit + *regs_num_64_bit;
5734 if (!total_num)
5735 return -EINVAL;
5736
5737 return 0;
5738}
5739
5740static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5741 void *data)
5742{
5743#define HCLGE_32_BIT_REG_RTN_DATANUM 8
5744
5745 struct hclge_desc *desc;
5746 u32 *reg_val = data;
5747 __le32 *desc_data;
5748 int cmd_num;
5749 int i, k, n;
5750 int ret;
5751
5752 if (regs_num == 0)
5753 return 0;
5754
5755 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
5756 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5757 if (!desc)
5758 return -ENOMEM;
5759
5760 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
5761 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5762 if (ret) {
5763 dev_err(&hdev->pdev->dev,
5764 "Query 32 bit register cmd failed, ret = %d.\n", ret);
5765 kfree(desc);
5766 return ret;
5767 }
5768
5769 for (i = 0; i < cmd_num; i++) {
5770 if (i == 0) {
5771 desc_data = (__le32 *)(&desc[i].data[0]);
5772 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
5773 } else {
5774 desc_data = (__le32 *)(&desc[i]);
5775 n = HCLGE_32_BIT_REG_RTN_DATANUM;
5776 }
5777 for (k = 0; k < n; k++) {
5778 *reg_val++ = le32_to_cpu(*desc_data++);
5779
5780 regs_num--;
5781 if (!regs_num)
5782 break;
5783 }
5784 }
5785
5786 kfree(desc);
5787 return 0;
5788}
5789
5790static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5791 void *data)
5792{
5793#define HCLGE_64_BIT_REG_RTN_DATANUM 4
5794
5795 struct hclge_desc *desc;
5796 u64 *reg_val = data;
5797 __le64 *desc_data;
5798 int cmd_num;
5799 int i, k, n;
5800 int ret;
5801
5802 if (regs_num == 0)
5803 return 0;
5804
5805 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
5806 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5807 if (!desc)
5808 return -ENOMEM;
5809
5810 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
5811 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5812 if (ret) {
5813 dev_err(&hdev->pdev->dev,
5814 "Query 64 bit register cmd failed, ret = %d.\n", ret);
5815 kfree(desc);
5816 return ret;
5817 }
5818
5819 for (i = 0; i < cmd_num; i++) {
5820 if (i == 0) {
5821 desc_data = (__le64 *)(&desc[i].data[0]);
5822 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
5823 } else {
5824 desc_data = (__le64 *)(&desc[i]);
5825 n = HCLGE_64_BIT_REG_RTN_DATANUM;
5826 }
5827 for (k = 0; k < n; k++) {
5828 *reg_val++ = le64_to_cpu(*desc_data++);
5829
5830 regs_num--;
5831 if (!regs_num)
5832 break;
5833 }
5834 }
5835
5836 kfree(desc);
5837 return 0;
5838}
5839
5840static int hclge_get_regs_len(struct hnae3_handle *handle)
5841{
5842 struct hclge_vport *vport = hclge_get_vport(handle);
5843 struct hclge_dev *hdev = vport->back;
5844 u32 regs_num_32_bit, regs_num_64_bit;
5845 int ret;
5846
5847 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5848 if (ret) {
5849 dev_err(&hdev->pdev->dev,
5850 "Get register number failed, ret = %d.\n", ret);
5851 return -EOPNOTSUPP;
5852 }
5853
5854 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
5855}
5856
5857static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
5858 void *data)
5859{
5860 struct hclge_vport *vport = hclge_get_vport(handle);
5861 struct hclge_dev *hdev = vport->back;
5862 u32 regs_num_32_bit, regs_num_64_bit;
5863 int ret;
5864
5865 *version = hdev->fw_version;
5866
5867 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5868 if (ret) {
5869 dev_err(&hdev->pdev->dev,
5870 "Get register number failed, ret = %d.\n", ret);
5871 return;
5872 }
5873
5874 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
5875 if (ret) {
5876 dev_err(&hdev->pdev->dev,
5877 "Get 32 bit register failed, ret = %d.\n", ret);
5878 return;
5879 }
5880
5881 data = (u32 *)data + regs_num_32_bit;
5882 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
5883 data);
5884 if (ret)
5885 dev_err(&hdev->pdev->dev,
5886 "Get 64 bit register failed, ret = %d.\n", ret);
5887}
5888
f6f75abc 5889static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
07f8e940
JS		 5890{
5891 struct hclge_set_led_state_cmd *req;
5892 struct hclge_desc desc;
5893 int ret;
5894
5895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
5896
5897 req = (struct hclge_set_led_state_cmd *)desc.data;
e4e87715
PL		 5898 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
5899 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
07f8e940
JS		 5900
5901 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5902 if (ret)
5903 dev_err(&hdev->pdev->dev,
5904 "Send set led state cmd error, ret =%d\n", ret);
5905
5906 return ret;
5907}
5908
5909enum hclge_led_status {
5910 HCLGE_LED_OFF,
5911 HCLGE_LED_ON,
5912 HCLGE_LED_NO_CHANGE = 0xFF,
5913};
5914
5915static int hclge_set_led_id(struct hnae3_handle *handle,
5916 enum ethtool_phys_id_state status)
5917{
07f8e940
JS		 5918 struct hclge_vport *vport = hclge_get_vport(handle);
5919 struct hclge_dev *hdev = vport->back;
07f8e940
JS		 5920
5921 switch (status) {
5922 case ETHTOOL_ID_ACTIVE:
f6f75abc 5923 return hclge_set_led_status(hdev, HCLGE_LED_ON);
07f8e940 5924 case ETHTOOL_ID_INACTIVE:
f6f75abc 5925 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
07f8e940 5926 default:
f6f75abc 5927 return -EINVAL;
07f8e940 5928 }
07f8e940
JS		 5929}
5930
0979aa0b
FL		 5931static void hclge_get_link_mode(struct hnae3_handle *handle,
5932 unsigned long *supported,
5933 unsigned long *advertising)
5934{
5935 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
5936 struct hclge_vport *vport = hclge_get_vport(handle);
5937 struct hclge_dev *hdev = vport->back;
5938 unsigned int idx = 0;
5939
5940 for (; idx < size; idx++) {
5941 supported[idx] = hdev->hw.mac.supported[idx];
5942 advertising[idx] = hdev->hw.mac.advertising[idx];
5943 }
5944}
5945
5946static void hclge_get_port_type(struct hnae3_handle *handle,
5947 u8 *port_type)
5948{
5949 struct hclge_vport *vport = hclge_get_vport(handle);
5950 struct hclge_dev *hdev = vport->back;
5951 u8 media_type = hdev->hw.mac.media_type;
5952
5953 switch (media_type) {
5954 case HNAE3_MEDIA_TYPE_FIBER:
5955 *port_type = PORT_FIBRE;
5956 break;
5957 case HNAE3_MEDIA_TYPE_COPPER:
5958 *port_type = PORT_TP;
5959 break;
5960 case HNAE3_MEDIA_TYPE_UNKNOWN:
5961 default:
5962 *port_type = PORT_OTHER;
5963 break;
5964 }
5965}
5966
46a3df9f
S		 5967static const struct hnae3_ae_ops hclge_ops = {
5968 .init_ae_dev = hclge_init_ae_dev,
5969 .uninit_ae_dev = hclge_uninit_ae_dev,
5970 .init_client_instance = hclge_init_client_instance,
5971 .uninit_client_instance = hclge_uninit_client_instance,
84e095d6
SM		 5972 .map_ring_to_vector = hclge_map_ring_to_vector,
5973 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 5974 .get_vector = hclge_get_vector,
0d3e6631 5975 .put_vector = hclge_put_vector,
46a3df9f 5976 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 5977 .set_loopback = hclge_set_loopback,
46a3df9f
S		 5978 .start = hclge_ae_start,
5979 .stop = hclge_ae_stop,
5980 .get_status = hclge_get_status,
5981 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5982 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5983 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5984 .get_media_type = hclge_get_media_type,
5985 .get_rss_key_size = hclge_get_rss_key_size,
5986 .get_rss_indir_size = hclge_get_rss_indir_size,
5987 .get_rss = hclge_get_rss,
5988 .set_rss = hclge_set_rss,
f7db940a 5989 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 5990 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 5991 .get_tc_size = hclge_get_tc_size,
5992 .get_mac_addr = hclge_get_mac_addr,
5993 .set_mac_addr = hclge_set_mac_addr,
26483246 5994 .do_ioctl = hclge_do_ioctl,
46a3df9f
S		 5995 .add_uc_addr = hclge_add_uc_addr,
5996 .rm_uc_addr = hclge_rm_uc_addr,
5997 .add_mc_addr = hclge_add_mc_addr,
5998 .rm_mc_addr = hclge_rm_mc_addr,
40cca1c5 5999 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6000 .set_autoneg = hclge_set_autoneg,
6001 .get_autoneg = hclge_get_autoneg,
6002 .get_pauseparam = hclge_get_pauseparam,
61387774 6003 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6004 .set_mtu = hclge_set_mtu,
6005 .reset_queue = hclge_reset_tqp,
6006 .get_stats = hclge_get_stats,
6007 .update_stats = hclge_update_stats,
6008 .get_strings = hclge_get_strings,
6009 .get_sset_count = hclge_get_sset_count,
6010 .get_fw_version = hclge_get_fw_version,
6011 .get_mdix_mode = hclge_get_mdix_mode,
391b5e93 6012 .enable_vlan_filter = hclge_enable_vlan_filter,
dc8131d8 6013 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6014 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
052ece6d 6015 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6016 .reset_event = hclge_reset_event,
09f2af64
PL		 6017 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6018 .set_channels = hclge_set_channels,
482d2e9c 6019 .get_channels = hclge_get_channels,
77b34110
FL		 6020 .get_regs_len = hclge_get_regs_len,
6021 .get_regs = hclge_get_regs,
07f8e940 6022 .set_led_id = hclge_set_led_id,
0979aa0b
FL		 6023 .get_link_mode = hclge_get_link_mode,
6024 .get_port_type = hclge_get_port_type,
46a3df9f
S		 6025};
6026
6027static struct hnae3_ae_algo ae_algo = {
6028 .ops = &hclge_ops,
46a3df9f
S		 6029 .pdev_id_table = ae_algo_pci_tbl,
6030};
6031
6032static int hclge_init(void)
6033{
6034 pr_info("%s is initializing\n", HCLGE_NAME);
6035
854cf33a
FL		 6036 hnae3_register_ae_algo(&ae_algo);
6037
6038 return 0;
46a3df9f
S		 6039}
6040
6041static void hclge_exit(void)
6042{
6043 hnae3_unregister_ae_algo(&ae_algo);
6044}
6045module_init(hclge_init);
6046module_exit(hclge_exit);
6047
6048MODULE_LICENSE("GPL");
6049MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6050MODULE_DESCRIPTION("HCLGE Driver");
6051MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)