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net: erspan: remove md NULL check
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
f2f432f2 20#include <net/rtnetlink.h>
46a3df9f 21#include "hclge_cmd.h"
cacde272 22#include "hclge_dcb.h"
46a3df9f 23#include "hclge_main.h"
dde1a86e 24#include "hclge_mbx.h"
46a3df9f
S		 25#include "hclge_mdio.h"
26#include "hclge_tm.h"
27#include "hnae3.h"
28
29#define HCLGE_NAME "hclge"
30#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
31#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
32#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
33#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
34
46a3df9f
S		 35static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
36 enum hclge_mta_dmac_sel_type mta_mac_sel,
37 bool enable);
38static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 39static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 40
41static struct hnae3_ae_algo ae_algo;
42
43static const struct pci_device_id ae_algo_pci_tbl[] = {
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 51 /* required last entry */
46a3df9f
S		 52 {0, }
53};
54
55static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
56 "Mac Loopback test",
57 "Serdes Loopback test",
58 "Phy Loopback test"
59};
60
61static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
62 {"igu_rx_oversize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
64 {"igu_rx_undersize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
66 {"igu_rx_out_all_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
68 {"igu_rx_uni_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
70 {"igu_rx_multi_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
72 {"igu_rx_broad_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
74 {"egu_tx_out_all_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
76 {"egu_tx_uni_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
78 {"egu_tx_multi_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
80 {"egu_tx_broad_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
82 {"ssu_ppp_mac_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
84 {"ssu_ppp_host_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
86 {"ppp_ssu_mac_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
88 {"ppp_ssu_host_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
90 {"ssu_tx_in_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
92 {"ssu_tx_out_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
94 {"ssu_rx_in_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
96 {"ssu_rx_out_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
98};
99
100static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
101 {"igu_rx_err_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
103 {"igu_rx_no_eof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
105 {"igu_rx_no_sof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
107 {"egu_tx_1588_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
109 {"ssu_full_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
111 {"ssu_part_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
113 {"ppp_key_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
115 {"ppp_rlt_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
117 {"ssu_key_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
119 {"pkt_curr_buf_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
121 {"qcn_fb_rcv_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
123 {"qcn_fb_drop_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
125 {"qcn_fb_invaild_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
127 {"rx_packet_tc0_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
129 {"rx_packet_tc1_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
131 {"rx_packet_tc2_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
133 {"rx_packet_tc3_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
135 {"rx_packet_tc4_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
137 {"rx_packet_tc5_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
139 {"rx_packet_tc6_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
141 {"rx_packet_tc7_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
143 {"rx_packet_tc0_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
145 {"rx_packet_tc1_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
147 {"rx_packet_tc2_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
149 {"rx_packet_tc3_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
151 {"rx_packet_tc4_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
153 {"rx_packet_tc5_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
155 {"rx_packet_tc6_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
157 {"rx_packet_tc7_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
159 {"tx_packet_tc0_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
161 {"tx_packet_tc1_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
163 {"tx_packet_tc2_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
165 {"tx_packet_tc3_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
167 {"tx_packet_tc4_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
169 {"tx_packet_tc5_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
171 {"tx_packet_tc6_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
173 {"tx_packet_tc7_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
175 {"tx_packet_tc0_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
177 {"tx_packet_tc1_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
179 {"tx_packet_tc2_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
181 {"tx_packet_tc3_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
183 {"tx_packet_tc4_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
185 {"tx_packet_tc5_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
187 {"tx_packet_tc6_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
189 {"tx_packet_tc7_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
191 {"pkt_curr_buf_tc0_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
193 {"pkt_curr_buf_tc1_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
195 {"pkt_curr_buf_tc2_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
197 {"pkt_curr_buf_tc3_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
199 {"pkt_curr_buf_tc4_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
201 {"pkt_curr_buf_tc5_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
203 {"pkt_curr_buf_tc6_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
205 {"pkt_curr_buf_tc7_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
207 {"mb_uncopy_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
209 {"lo_pri_unicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
211 {"hi_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
213 {"lo_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
215 {"rx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
217 {"tx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
219 {"nic_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
221 {"roc_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
223};
224
225static const struct hclge_comm_stats_str g_mac_stats_string[] = {
226 {"mac_tx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
228 {"mac_rx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
230 {"mac_tx_pfc_pri0_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
232 {"mac_tx_pfc_pri1_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
234 {"mac_tx_pfc_pri2_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
236 {"mac_tx_pfc_pri3_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
238 {"mac_tx_pfc_pri4_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
240 {"mac_tx_pfc_pri5_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
242 {"mac_tx_pfc_pri6_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
244 {"mac_tx_pfc_pri7_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
246 {"mac_rx_pfc_pri0_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
248 {"mac_rx_pfc_pri1_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
250 {"mac_rx_pfc_pri2_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
252 {"mac_rx_pfc_pri3_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
254 {"mac_rx_pfc_pri4_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
256 {"mac_rx_pfc_pri5_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
258 {"mac_rx_pfc_pri6_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
260 {"mac_rx_pfc_pri7_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
262 {"mac_tx_total_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
264 {"mac_tx_total_oct_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
266 {"mac_tx_good_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
268 {"mac_tx_bad_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
270 {"mac_tx_good_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
272 {"mac_tx_bad_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
274 {"mac_tx_uni_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
276 {"mac_tx_multi_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
278 {"mac_tx_broad_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
280 {"mac_tx_undersize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
282 {"mac_tx_overrsize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
284 {"mac_tx_64_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
286 {"mac_tx_65_127_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
288 {"mac_tx_128_255_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
290 {"mac_tx_256_511_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
292 {"mac_tx_512_1023_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
294 {"mac_tx_1024_1518_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
296 {"mac_tx_1519_max_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
298 {"mac_rx_total_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
300 {"mac_rx_total_oct_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
302 {"mac_rx_good_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
304 {"mac_rx_bad_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
306 {"mac_rx_good_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
308 {"mac_rx_bad_oct_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
310 {"mac_rx_uni_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
312 {"mac_rx_multi_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
314 {"mac_rx_broad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
316 {"mac_rx_undersize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
318 {"mac_rx_overrsize_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
320 {"mac_rx_64_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
322 {"mac_rx_65_127_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
324 {"mac_rx_128_255_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
326 {"mac_rx_256_511_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
328 {"mac_rx_512_1023_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
330 {"mac_rx_1024_1518_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
332 {"mac_rx_1519_max_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
334
335 {"mac_trans_fragment_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
337 {"mac_trans_undermin_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
339 {"mac_trans_jabber_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
341 {"mac_trans_err_all_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
343 {"mac_trans_from_app_good_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
345 {"mac_trans_from_app_bad_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
347 {"mac_rcv_fragment_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
349 {"mac_rcv_undermin_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
351 {"mac_rcv_jabber_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
353 {"mac_rcv_fcs_err_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
355 {"mac_rcv_send_app_good_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
357 {"mac_rcv_send_app_bad_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
359};
360
361static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
362{
363#define HCLGE_64_BIT_CMD_NUM 5
364#define HCLGE_64_BIT_RTN_DATANUM 4
365 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
366 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 367 __le64 *desc_data;
46a3df9f
S		 368 int i, k, n;
369 int ret;
370
371 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
372 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
373 if (ret) {
374 dev_err(&hdev->pdev->dev,
375 "Get 64 bit pkt stats fail, status = %d.\n", ret);
376 return ret;
377 }
378
379 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
380 if (unlikely(i == 0)) {
a90bb9a5 381 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 382 n = HCLGE_64_BIT_RTN_DATANUM - 1;
383 } else {
a90bb9a5 384 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 385 n = HCLGE_64_BIT_RTN_DATANUM;
386 }
387 for (k = 0; k < n; k++) {
a90bb9a5 388 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 389 desc_data++;
390 }
391 }
392
393 return 0;
394}
395
396static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
397{
398 stats->pkt_curr_buf_cnt = 0;
399 stats->pkt_curr_buf_tc0_cnt = 0;
400 stats->pkt_curr_buf_tc1_cnt = 0;
401 stats->pkt_curr_buf_tc2_cnt = 0;
402 stats->pkt_curr_buf_tc3_cnt = 0;
403 stats->pkt_curr_buf_tc4_cnt = 0;
404 stats->pkt_curr_buf_tc5_cnt = 0;
405 stats->pkt_curr_buf_tc6_cnt = 0;
406 stats->pkt_curr_buf_tc7_cnt = 0;
407}
408
409static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
410{
411#define HCLGE_32_BIT_CMD_NUM 8
412#define HCLGE_32_BIT_RTN_DATANUM 8
413
414 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
415 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 416 __le32 *desc_data;
46a3df9f
S		 417 int i, k, n;
418 u64 *data;
419 int ret;
420
421 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
422 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
423
424 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
425 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
426 if (ret) {
427 dev_err(&hdev->pdev->dev,
428 "Get 32 bit pkt stats fail, status = %d.\n", ret);
429
430 return ret;
431 }
432
433 hclge_reset_partial_32bit_counter(all_32_bit_stats);
434 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
435 if (unlikely(i == 0)) {
a90bb9a5
YL		 436 __le16 *desc_data_16bit;
437
46a3df9f 438 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 439 le32_to_cpu(desc[i].data[0]);
440
441 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 442 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 443 le16_to_cpu(*desc_data_16bit);
444
445 desc_data_16bit++;
46a3df9f 446 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 447 le16_to_cpu(*desc_data_16bit);
46a3df9f 448
a90bb9a5 449 desc_data = &desc[i].data[2];
46a3df9f
S		 450 n = HCLGE_32_BIT_RTN_DATANUM - 4;
451 } else {
a90bb9a5 452 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 453 n = HCLGE_32_BIT_RTN_DATANUM;
454 }
455 for (k = 0; k < n; k++) {
a90bb9a5 456 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 457 desc_data++;
458 }
459 }
460
461 return 0;
462}
463
464static int hclge_mac_update_stats(struct hclge_dev *hdev)
465{
466#define HCLGE_MAC_CMD_NUM 17
467#define HCLGE_RTN_DATA_NUM 4
468
469 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
470 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 471 __le64 *desc_data;
46a3df9f
S		 472 int i, k, n;
473 int ret;
474
475 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
476 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
477 if (ret) {
478 dev_err(&hdev->pdev->dev,
479 "Get MAC pkt stats fail, status = %d.\n", ret);
480
481 return ret;
482 }
483
484 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
485 if (unlikely(i == 0)) {
a90bb9a5 486 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 487 n = HCLGE_RTN_DATA_NUM - 2;
488 } else {
a90bb9a5 489 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 490 n = HCLGE_RTN_DATA_NUM;
491 }
492 for (k = 0; k < n; k++) {
a90bb9a5 493 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 494 desc_data++;
495 }
496 }
497
498 return 0;
499}
500
501static int hclge_tqps_update_stats(struct hnae3_handle *handle)
502{
503 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
504 struct hclge_vport *vport = hclge_get_vport(handle);
505 struct hclge_dev *hdev = vport->back;
506 struct hnae3_queue *queue;
507 struct hclge_desc desc[1];
508 struct hclge_tqp *tqp;
509 int ret, i;
510
511 for (i = 0; i < kinfo->num_tqps; i++) {
512 queue = handle->kinfo.tqp[i];
513 tqp = container_of(queue, struct hclge_tqp, q);
514 /* command : HCLGE_OPC_QUERY_IGU_STAT */
515 hclge_cmd_setup_basic_desc(&desc[0],
516 HCLGE_OPC_QUERY_RX_STATUS,
517 true);
518
a90bb9a5 519 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 520 ret = hclge_cmd_send(&hdev->hw, desc, 1);
521 if (ret) {
522 dev_err(&hdev->pdev->dev,
523 "Query tqp stat fail, status = %d,queue = %d\n",
524 ret, i);
525 return ret;
526 }
527 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
a90bb9a5 528 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 529 }
530
531 for (i = 0; i < kinfo->num_tqps; i++) {
532 queue = handle->kinfo.tqp[i];
533 tqp = container_of(queue, struct hclge_tqp, q);
534 /* command : HCLGE_OPC_QUERY_IGU_STAT */
535 hclge_cmd_setup_basic_desc(&desc[0],
536 HCLGE_OPC_QUERY_TX_STATUS,
537 true);
538
a90bb9a5 539 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 540 ret = hclge_cmd_send(&hdev->hw, desc, 1);
541 if (ret) {
542 dev_err(&hdev->pdev->dev,
543 "Query tqp stat fail, status = %d,queue = %d\n",
544 ret, i);
545 return ret;
546 }
547 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
a90bb9a5 548 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 549 }
550
551 return 0;
552}
553
554static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
555{
556 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
557 struct hclge_tqp *tqp;
558 u64 *buff = data;
559 int i;
560
561 for (i = 0; i < kinfo->num_tqps; i++) {
562 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 563 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 564 }
565
566 for (i = 0; i < kinfo->num_tqps; i++) {
567 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 568 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 569 }
570
571 return buff;
572}
573
574static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
575{
576 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
577
578 return kinfo->num_tqps * (2);
579}
580
581static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
582{
583 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
584 u8 *buff = data;
585 int i = 0;
586
587 for (i = 0; i < kinfo->num_tqps; i++) {
588 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
589 struct hclge_tqp, q);
590 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
591 tqp->index);
592 buff = buff + ETH_GSTRING_LEN;
593 }
594
595 for (i = 0; i < kinfo->num_tqps; i++) {
596 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
597 struct hclge_tqp, q);
598 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
599 tqp->index);
600 buff = buff + ETH_GSTRING_LEN;
601 }
602
603 return buff;
604}
605
606static u64 *hclge_comm_get_stats(void *comm_stats,
607 const struct hclge_comm_stats_str strs[],
608 int size, u64 *data)
609{
610 u64 *buf = data;
611 u32 i;
612
613 for (i = 0; i < size; i++)
614 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
615
616 return buf + size;
617}
618
619static u8 *hclge_comm_get_strings(u32 stringset,
620 const struct hclge_comm_stats_str strs[],
621 int size, u8 *data)
622{
623 char *buff = (char *)data;
624 u32 i;
625
626 if (stringset != ETH_SS_STATS)
627 return buff;
628
629 for (i = 0; i < size; i++) {
630 snprintf(buff, ETH_GSTRING_LEN,
631 strs[i].desc);
632 buff = buff + ETH_GSTRING_LEN;
633 }
634
635 return (u8 *)buff;
636}
637
638static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
639 struct net_device_stats *net_stats)
640{
641 net_stats->tx_dropped = 0;
642 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
643 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
644 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
645
646 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
647 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
648 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
649 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
650 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
651 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
652
653 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
654 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
655
656 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
657 net_stats->rx_length_errors =
658 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
659 net_stats->rx_length_errors +=
660 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
661 net_stats->rx_over_errors =
662 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
663}
664
665static void hclge_update_stats_for_all(struct hclge_dev *hdev)
666{
667 struct hnae3_handle *handle;
668 int status;
669
670 handle = &hdev->vport[0].nic;
671 if (handle->client) {
672 status = hclge_tqps_update_stats(handle);
673 if (status) {
674 dev_err(&hdev->pdev->dev,
675 "Update TQPS stats fail, status = %d.\n",
676 status);
677 }
678 }
679
680 status = hclge_mac_update_stats(hdev);
681 if (status)
682 dev_err(&hdev->pdev->dev,
683 "Update MAC stats fail, status = %d.\n", status);
684
685 status = hclge_32_bit_update_stats(hdev);
686 if (status)
687 dev_err(&hdev->pdev->dev,
688 "Update 32 bit stats fail, status = %d.\n",
689 status);
690
691 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
692}
693
694static void hclge_update_stats(struct hnae3_handle *handle,
695 struct net_device_stats *net_stats)
696{
697 struct hclge_vport *vport = hclge_get_vport(handle);
698 struct hclge_dev *hdev = vport->back;
699 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
700 int status;
701
702 status = hclge_mac_update_stats(hdev);
703 if (status)
704 dev_err(&hdev->pdev->dev,
705 "Update MAC stats fail, status = %d.\n",
706 status);
707
708 status = hclge_32_bit_update_stats(hdev);
709 if (status)
710 dev_err(&hdev->pdev->dev,
711 "Update 32 bit stats fail, status = %d.\n",
712 status);
713
714 status = hclge_64_bit_update_stats(hdev);
715 if (status)
716 dev_err(&hdev->pdev->dev,
717 "Update 64 bit stats fail, status = %d.\n",
718 status);
719
720 status = hclge_tqps_update_stats(handle);
721 if (status)
722 dev_err(&hdev->pdev->dev,
723 "Update TQPS stats fail, status = %d.\n",
724 status);
725
726 hclge_update_netstat(hw_stats, net_stats);
727}
728
729static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
730{
731#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
732
733 struct hclge_vport *vport = hclge_get_vport(handle);
734 struct hclge_dev *hdev = vport->back;
735 int count = 0;
736
737 /* Loopback test support rules:
738 * mac: only GE mode support
739 * serdes: all mac mode will support include GE/XGE/LGE/CGE
740 * phy: only support when phy device exist on board
741 */
742 if (stringset == ETH_SS_TEST) {
743 /* clear loopback bit flags at first */
744 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
745 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
746 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
747 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
748 count += 1;
749 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
750 } else {
751 count = -EOPNOTSUPP;
752 }
753 } else if (stringset == ETH_SS_STATS) {
754 count = ARRAY_SIZE(g_mac_stats_string) +
755 ARRAY_SIZE(g_all_32bit_stats_string) +
756 ARRAY_SIZE(g_all_64bit_stats_string) +
757 hclge_tqps_get_sset_count(handle, stringset);
758 }
759
760 return count;
761}
762
763static void hclge_get_strings(struct hnae3_handle *handle,
764 u32 stringset,
765 u8 *data)
766{
767 u8 *p = (char *)data;
768 int size;
769
770 if (stringset == ETH_SS_STATS) {
771 size = ARRAY_SIZE(g_mac_stats_string);
772 p = hclge_comm_get_strings(stringset,
773 g_mac_stats_string,
774 size,
775 p);
776 size = ARRAY_SIZE(g_all_32bit_stats_string);
777 p = hclge_comm_get_strings(stringset,
778 g_all_32bit_stats_string,
779 size,
780 p);
781 size = ARRAY_SIZE(g_all_64bit_stats_string);
782 p = hclge_comm_get_strings(stringset,
783 g_all_64bit_stats_string,
784 size,
785 p);
786 p = hclge_tqps_get_strings(handle, p);
787 } else if (stringset == ETH_SS_TEST) {
788 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
789 memcpy(p,
790 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
791 ETH_GSTRING_LEN);
792 p += ETH_GSTRING_LEN;
793 }
794 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
795 memcpy(p,
796 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
797 ETH_GSTRING_LEN);
798 p += ETH_GSTRING_LEN;
799 }
800 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
801 memcpy(p,
802 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
803 ETH_GSTRING_LEN);
804 p += ETH_GSTRING_LEN;
805 }
806 }
807}
808
809static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
810{
811 struct hclge_vport *vport = hclge_get_vport(handle);
812 struct hclge_dev *hdev = vport->back;
813 u64 *p;
814
815 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
816 g_mac_stats_string,
817 ARRAY_SIZE(g_mac_stats_string),
818 data);
819 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
820 g_all_32bit_stats_string,
821 ARRAY_SIZE(g_all_32bit_stats_string),
822 p);
823 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
824 g_all_64bit_stats_string,
825 ARRAY_SIZE(g_all_64bit_stats_string),
826 p);
827 p = hclge_tqps_get_stats(handle, p);
828}
829
830static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 831 struct hclge_func_status_cmd *status)
46a3df9f
S		 832{
833 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
834 return -EINVAL;
835
836 /* Set the pf to main pf */
837 if (status->pf_state & HCLGE_PF_STATE_MAIN)
838 hdev->flag |= HCLGE_FLAG_MAIN;
839 else
840 hdev->flag &= ~HCLGE_FLAG_MAIN;
841
46a3df9f
S		 842 return 0;
843}
844
845static int hclge_query_function_status(struct hclge_dev *hdev)
846{
d44f9b63 847 struct hclge_func_status_cmd *req;
46a3df9f
S		 848 struct hclge_desc desc;
849 int timeout = 0;
850 int ret;
851
852 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 853 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 854
855 do {
856 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
857 if (ret) {
858 dev_err(&hdev->pdev->dev,
859 "query function status failed %d.\n",
860 ret);
861
862 return ret;
863 }
864
865 /* Check pf reset is done */
866 if (req->pf_state)
867 break;
868 usleep_range(1000, 2000);
869 } while (timeout++ < 5);
870
871 ret = hclge_parse_func_status(hdev, req);
872
873 return ret;
874}
875
876static int hclge_query_pf_resource(struct hclge_dev *hdev)
877{
d44f9b63 878 struct hclge_pf_res_cmd *req;
46a3df9f
S		 879 struct hclge_desc desc;
880 int ret;
881
882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
883 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
884 if (ret) {
885 dev_err(&hdev->pdev->dev,
886 "query pf resource failed %d.\n", ret);
887 return ret;
888 }
889
d44f9b63 890 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 891 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
892 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
893
e92a0843 894 if (hnae3_dev_roce_supported(hdev)) {
887c3820 895 hdev->num_roce_msi =
46a3df9f
S		 896 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
897 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
898
899 /* PF should have NIC vectors and Roce vectors,
900 * NIC vectors are queued before Roce vectors.
901 */
887c3820 902 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 903 } else {
904 hdev->num_msi =
905 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
906 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
907 }
908
909 return 0;
910}
911
912static int hclge_parse_speed(int speed_cmd, int *speed)
913{
914 switch (speed_cmd) {
915 case 6:
916 *speed = HCLGE_MAC_SPEED_10M;
917 break;
918 case 7:
919 *speed = HCLGE_MAC_SPEED_100M;
920 break;
921 case 0:
922 *speed = HCLGE_MAC_SPEED_1G;
923 break;
924 case 1:
925 *speed = HCLGE_MAC_SPEED_10G;
926 break;
927 case 2:
928 *speed = HCLGE_MAC_SPEED_25G;
929 break;
930 case 3:
931 *speed = HCLGE_MAC_SPEED_40G;
932 break;
933 case 4:
934 *speed = HCLGE_MAC_SPEED_50G;
935 break;
936 case 5:
937 *speed = HCLGE_MAC_SPEED_100G;
938 break;
939 default:
940 return -EINVAL;
941 }
942
943 return 0;
944}
945
946static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
947{
d44f9b63 948 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 949 u64 mac_addr_tmp_high;
950 u64 mac_addr_tmp;
951 int i;
952
d44f9b63 953 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 954
955 /* get the configuration */
956 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
957 HCLGE_CFG_VMDQ_M,
958 HCLGE_CFG_VMDQ_S);
959 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
960 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
961 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
962 HCLGE_CFG_TQP_DESC_N_M,
963 HCLGE_CFG_TQP_DESC_N_S);
964
965 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
966 HCLGE_CFG_PHY_ADDR_M,
967 HCLGE_CFG_PHY_ADDR_S);
968 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
969 HCLGE_CFG_MEDIA_TP_M,
970 HCLGE_CFG_MEDIA_TP_S);
971 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
972 HCLGE_CFG_RX_BUF_LEN_M,
973 HCLGE_CFG_RX_BUF_LEN_S);
974 /* get mac_address */
975 mac_addr_tmp = __le32_to_cpu(req->param[2]);
976 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
977 HCLGE_CFG_MAC_ADDR_H_M,
978 HCLGE_CFG_MAC_ADDR_H_S);
979
980 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
981
982 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
983 HCLGE_CFG_DEFAULT_SPEED_M,
984 HCLGE_CFG_DEFAULT_SPEED_S);
985 for (i = 0; i < ETH_ALEN; i++)
986 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
987
d44f9b63 988 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f
S		 989 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
990}
991
992/* hclge_get_cfg: query the static parameter from flash
993 * @hdev: pointer to struct hclge_dev
994 * @hcfg: the config structure to be getted
995 */
996static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
997{
998 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 999 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1000 int i, ret;
1001
1002 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1003 u32 offset = 0;
1004
d44f9b63 1005 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1006 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1007 true);
a90bb9a5 1008 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1009 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1010 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1011 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1012 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1013 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1014 }
1015
1016 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1017 if (ret) {
1018 dev_err(&hdev->pdev->dev,
1019 "get config failed %d.\n", ret);
1020 return ret;
1021 }
1022
1023 hclge_parse_cfg(hcfg, desc);
1024 return 0;
1025}
1026
1027static int hclge_get_cap(struct hclge_dev *hdev)
1028{
1029 int ret;
1030
1031 ret = hclge_query_function_status(hdev);
1032 if (ret) {
1033 dev_err(&hdev->pdev->dev,
1034 "query function status error %d.\n", ret);
1035 return ret;
1036 }
1037
1038 /* get pf resource */
1039 ret = hclge_query_pf_resource(hdev);
1040 if (ret) {
1041 dev_err(&hdev->pdev->dev,
1042 "query pf resource error %d.\n", ret);
1043 return ret;
1044 }
1045
1046 return 0;
1047}
1048
1049static int hclge_configure(struct hclge_dev *hdev)
1050{
1051 struct hclge_cfg cfg;
1052 int ret, i;
1053
1054 ret = hclge_get_cfg(hdev, &cfg);
1055 if (ret) {
1056 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1057 return ret;
1058 }
1059
1060 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1061 hdev->base_tqp_pid = 0;
1062 hdev->rss_size_max = 1;
1063 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1064 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1065 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1066 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1067 hdev->num_desc = cfg.tqp_desc_num;
1068 hdev->tm_info.num_pg = 1;
cacde272 1069 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1070 hdev->tm_info.hw_pfc_map = 0;
1071
1072 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1073 if (ret) {
1074 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1075 return ret;
1076 }
1077
cacde272
YL		 1078 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1079 (hdev->tc_max < 1)) {
46a3df9f 1080 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1081 hdev->tc_max);
1082 hdev->tc_max = 1;
46a3df9f
S		 1083 }
1084
cacde272
YL		 1085 /* Dev does not support DCB */
1086 if (!hnae3_dev_dcb_supported(hdev)) {
1087 hdev->tc_max = 1;
1088 hdev->pfc_max = 0;
1089 } else {
1090 hdev->pfc_max = hdev->tc_max;
1091 }
1092
1093 hdev->tm_info.num_tc = hdev->tc_max;
1094
46a3df9f 1095 /* Currently not support uncontiuous tc */
cacde272 1096 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1097 hnae_set_bit(hdev->hw_tc_map, i, 1);
1098
1099 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1100 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1101 else
1102 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1103
1104 return ret;
1105}
1106
1107static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1108 int tso_mss_max)
1109{
d44f9b63 1110 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1111 struct hclge_desc desc;
a90bb9a5 1112 u16 tso_mss;
46a3df9f
S		 1113
1114 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1115
d44f9b63 1116 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1117
1118 tso_mss = 0;
1119 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1120 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1121 req->tso_mss_min = cpu_to_le16(tso_mss);
1122
1123 tso_mss = 0;
1124 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1125 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1126 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1127
1128 return hclge_cmd_send(&hdev->hw, &desc, 1);
1129}
1130
1131static int hclge_alloc_tqps(struct hclge_dev *hdev)
1132{
1133 struct hclge_tqp *tqp;
1134 int i;
1135
1136 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1137 sizeof(struct hclge_tqp), GFP_KERNEL);
1138 if (!hdev->htqp)
1139 return -ENOMEM;
1140
1141 tqp = hdev->htqp;
1142
1143 for (i = 0; i < hdev->num_tqps; i++) {
1144 tqp->dev = &hdev->pdev->dev;
1145 tqp->index = i;
1146
1147 tqp->q.ae_algo = &ae_algo;
1148 tqp->q.buf_size = hdev->rx_buf_len;
1149 tqp->q.desc_num = hdev->num_desc;
1150 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1151 i * HCLGE_TQP_REG_SIZE;
1152
1153 tqp++;
1154 }
1155
1156 return 0;
1157}
1158
1159static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1160 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1161{
d44f9b63 1162 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1163 struct hclge_desc desc;
1164 int ret;
1165
1166 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1167
d44f9b63 1168 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1169 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1170 req->tqp_vf = func_id;
46a3df9f
S		 1171 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1172 1 << HCLGE_TQP_MAP_EN_B;
1173 req->tqp_vid = cpu_to_le16(tqp_vid);
1174
1175 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1176 if (ret) {
1177 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1178 ret);
1179 return ret;
1180 }
1181
1182 return 0;
1183}
1184
1185static int hclge_assign_tqp(struct hclge_vport *vport,
1186 struct hnae3_queue **tqp, u16 num_tqps)
1187{
1188 struct hclge_dev *hdev = vport->back;
7df7dad6 1189 int i, alloced;
46a3df9f
S		 1190
1191 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1192 alloced < num_tqps; i++) {
1193 if (!hdev->htqp[i].alloced) {
1194 hdev->htqp[i].q.handle = &vport->nic;
1195 hdev->htqp[i].q.tqp_index = alloced;
1196 tqp[alloced] = &hdev->htqp[i].q;
1197 hdev->htqp[i].alloced = true;
46a3df9f
S		 1198 alloced++;
1199 }
1200 }
1201 vport->alloc_tqps = num_tqps;
1202
1203 return 0;
1204}
1205
1206static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1207{
1208 struct hnae3_handle *nic = &vport->nic;
1209 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1210 struct hclge_dev *hdev = vport->back;
1211 int i, ret;
1212
1213 kinfo->num_desc = hdev->num_desc;
1214 kinfo->rx_buf_len = hdev->rx_buf_len;
1215 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1216 kinfo->rss_size
1217 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1218 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1219
1220 for (i = 0; i < HNAE3_MAX_TC; i++) {
1221 if (hdev->hw_tc_map & BIT(i)) {
1222 kinfo->tc_info[i].enable = true;
1223 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1224 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1225 kinfo->tc_info[i].tc = i;
1226 } else {
1227 /* Set to default queue if TC is disable */
1228 kinfo->tc_info[i].enable = false;
1229 kinfo->tc_info[i].tqp_offset = 0;
1230 kinfo->tc_info[i].tqp_count = 1;
1231 kinfo->tc_info[i].tc = 0;
1232 }
1233 }
1234
1235 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1236 sizeof(struct hnae3_queue *), GFP_KERNEL);
1237 if (!kinfo->tqp)
1238 return -ENOMEM;
1239
1240 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1241 if (ret) {
1242 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1243 return -EINVAL;
1244 }
1245
1246 return 0;
1247}
1248
7df7dad6
L		 1249static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1250 struct hclge_vport *vport)
1251{
1252 struct hnae3_handle *nic = &vport->nic;
1253 struct hnae3_knic_private_info *kinfo;
1254 u16 i;
1255
1256 kinfo = &nic->kinfo;
1257 for (i = 0; i < kinfo->num_tqps; i++) {
1258 struct hclge_tqp *q =
1259 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1260 bool is_pf;
1261 int ret;
1262
1263 is_pf = !(vport->vport_id);
1264 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1265 i, is_pf);
1266 if (ret)
1267 return ret;
1268 }
1269
1270 return 0;
1271}
1272
1273static int hclge_map_tqp(struct hclge_dev *hdev)
1274{
1275 struct hclge_vport *vport = hdev->vport;
1276 u16 i, num_vport;
1277
1278 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1279 for (i = 0; i < num_vport; i++) {
1280 int ret;
1281
1282 ret = hclge_map_tqp_to_vport(hdev, vport);
1283 if (ret)
1284 return ret;
1285
1286 vport++;
1287 }
1288
1289 return 0;
1290}
1291
46a3df9f
S		 1292static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1293{
1294 /* this would be initialized later */
1295}
1296
1297static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1298{
1299 struct hnae3_handle *nic = &vport->nic;
1300 struct hclge_dev *hdev = vport->back;
1301 int ret;
1302
1303 nic->pdev = hdev->pdev;
1304 nic->ae_algo = &ae_algo;
1305 nic->numa_node_mask = hdev->numa_node_mask;
1306
1307 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1308 ret = hclge_knic_setup(vport, num_tqps);
1309 if (ret) {
1310 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1311 ret);
1312 return ret;
1313 }
1314 } else {
1315 hclge_unic_setup(vport, num_tqps);
1316 }
1317
1318 return 0;
1319}
1320
1321static int hclge_alloc_vport(struct hclge_dev *hdev)
1322{
1323 struct pci_dev *pdev = hdev->pdev;
1324 struct hclge_vport *vport;
1325 u32 tqp_main_vport;
1326 u32 tqp_per_vport;
1327 int num_vport, i;
1328 int ret;
1329
1330 /* We need to alloc a vport for main NIC of PF */
1331 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1332
1333 if (hdev->num_tqps < num_vport)
1334 num_vport = hdev->num_tqps;
1335
1336 /* Alloc the same number of TQPs for every vport */
1337 tqp_per_vport = hdev->num_tqps / num_vport;
1338 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1339
1340 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1341 GFP_KERNEL);
1342 if (!vport)
1343 return -ENOMEM;
1344
1345 hdev->vport = vport;
1346 hdev->num_alloc_vport = num_vport;
1347
1348#ifdef CONFIG_PCI_IOV
1349 /* Enable SRIOV */
1350 if (hdev->num_req_vfs) {
1351 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1352 hdev->num_req_vfs);
1353 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1354 if (ret) {
1355 hdev->num_alloc_vfs = 0;
1356 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1357 ret);
1358 return ret;
1359 }
1360 }
1361 hdev->num_alloc_vfs = hdev->num_req_vfs;
1362#endif
1363
1364 for (i = 0; i < num_vport; i++) {
1365 vport->back = hdev;
1366 vport->vport_id = i;
1367
1368 if (i == 0)
1369 ret = hclge_vport_setup(vport, tqp_main_vport);
1370 else
1371 ret = hclge_vport_setup(vport, tqp_per_vport);
1372 if (ret) {
1373 dev_err(&pdev->dev,
1374 "vport setup failed for vport %d, %d\n",
1375 i, ret);
1376 return ret;
1377 }
1378
1379 vport++;
1380 }
1381
1382 return 0;
1383}
1384
acf61ecd
YL		 1385static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1386 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1387{
1388/* TX buffer size is unit by 128 byte */
1389#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1390#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1391 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1392 struct hclge_desc desc;
1393 int ret;
1394 u8 i;
1395
d44f9b63 1396 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1397
1398 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1399 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1400 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1401
46a3df9f
S		 1402 req->tx_pkt_buff[i] =
1403 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1404 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1405 }
46a3df9f
S		 1406
1407 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1408 if (ret) {
1409 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1410 ret);
1411 return ret;
1412 }
1413
1414 return 0;
1415}
1416
acf61ecd
YL		 1417static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1418 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1419{
acf61ecd 1420 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1421
1422 if (ret) {
1423 dev_err(&hdev->pdev->dev,
1424 "tx buffer alloc failed %d\n", ret);
1425 return ret;
1426 }
1427
1428 return 0;
1429}
1430
1431static int hclge_get_tc_num(struct hclge_dev *hdev)
1432{
1433 int i, cnt = 0;
1434
1435 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1436 if (hdev->hw_tc_map & BIT(i))
1437 cnt++;
1438 return cnt;
1439}
1440
1441static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1442{
1443 int i, cnt = 0;
1444
1445 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1446 if (hdev->hw_tc_map & BIT(i) &&
1447 hdev->tm_info.hw_pfc_map & BIT(i))
1448 cnt++;
1449 return cnt;
1450}
1451
1452/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1453static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1454 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1455{
1456 struct hclge_priv_buf *priv;
1457 int i, cnt = 0;
1458
1459 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1460 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1461 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1462 priv->enable)
1463 cnt++;
1464 }
1465
1466 return cnt;
1467}
1468
1469/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1470static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1471 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1472{
1473 struct hclge_priv_buf *priv;
1474 int i, cnt = 0;
1475
1476 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1477 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1478 if (hdev->hw_tc_map & BIT(i) &&
1479 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1480 priv->enable)
1481 cnt++;
1482 }
1483
1484 return cnt;
1485}
1486
acf61ecd 1487static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1488{
1489 struct hclge_priv_buf *priv;
1490 u32 rx_priv = 0;
1491 int i;
1492
1493 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1494 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1495 if (priv->enable)
1496 rx_priv += priv->buf_size;
1497 }
1498 return rx_priv;
1499}
1500
acf61ecd 1501static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1502{
1503 u32 i, total_tx_size = 0;
1504
1505 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1506 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1507
1508 return total_tx_size;
1509}
1510
acf61ecd
YL		 1511static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1512 struct hclge_pkt_buf_alloc *buf_alloc,
1513 u32 rx_all)
46a3df9f
S		 1514{
1515 u32 shared_buf_min, shared_buf_tc, shared_std;
1516 int tc_num, pfc_enable_num;
1517 u32 shared_buf;
1518 u32 rx_priv;
1519 int i;
1520
1521 tc_num = hclge_get_tc_num(hdev);
1522 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1523
d221df4e
YL		 1524 if (hnae3_dev_dcb_supported(hdev))
1525 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1526 else
1527 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1528
46a3df9f
S		 1529 shared_buf_tc = pfc_enable_num * hdev->mps +
1530 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1531 hdev->mps;
1532 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1533
acf61ecd 1534 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1535 if (rx_all <= rx_priv + shared_std)
1536 return false;
1537
1538 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1539 buf_alloc->s_buf.buf_size = shared_buf;
1540 buf_alloc->s_buf.self.high = shared_buf;
1541 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1542
1543 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1544 if ((hdev->hw_tc_map & BIT(i)) &&
1545 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1546 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1547 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1548 } else {
acf61ecd
YL		 1549 buf_alloc->s_buf.tc_thrd[i].low = 0;
1550 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1551 }
1552 }
1553
1554 return true;
1555}
1556
acf61ecd
YL		 1557static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1558 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1559{
1560 u32 i, total_size;
1561
1562 total_size = hdev->pkt_buf_size;
1563
1564 /* alloc tx buffer for all enabled tc */
1565 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1566 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1567
1568 if (total_size < HCLGE_DEFAULT_TX_BUF)
1569 return -ENOMEM;
1570
1571 if (hdev->hw_tc_map & BIT(i))
1572 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1573 else
1574 priv->tx_buf_size = 0;
1575
1576 total_size -= priv->tx_buf_size;
1577 }
1578
1579 return 0;
1580}
1581
46a3df9f
S		 1582/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1583 * @hdev: pointer to struct hclge_dev
acf61ecd 1584 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1585 * @return: 0: calculate sucessful, negative: fail
1586 */
1db9b1bf
YL		 1587static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1588 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1589{
9ffe79a9 1590 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1591 int no_pfc_priv_num, pfc_priv_num;
1592 struct hclge_priv_buf *priv;
1593 int i;
1594
acf61ecd 1595 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1596
d602a525
YL		 1597 /* When DCB is not supported, rx private
1598 * buffer is not allocated.
1599 */
1600 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1601 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1602 return -ENOMEM;
1603
1604 return 0;
1605 }
1606
46a3df9f
S		 1607 /* step 1, try to alloc private buffer for all enabled tc */
1608 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1609 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1610 if (hdev->hw_tc_map & BIT(i)) {
1611 priv->enable = 1;
1612 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1613 priv->wl.low = hdev->mps;
1614 priv->wl.high = priv->wl.low + hdev->mps;
1615 priv->buf_size = priv->wl.high +
1616 HCLGE_DEFAULT_DV;
1617 } else {
1618 priv->wl.low = 0;
1619 priv->wl.high = 2 * hdev->mps;
1620 priv->buf_size = priv->wl.high;
1621 }
bb1fe9ea
YL		 1622 } else {
1623 priv->enable = 0;
1624 priv->wl.low = 0;
1625 priv->wl.high = 0;
1626 priv->buf_size = 0;
46a3df9f
S		 1627 }
1628 }
1629
acf61ecd 1630 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1631 return 0;
1632
1633 /* step 2, try to decrease the buffer size of
1634 * no pfc TC's private buffer
1635 */
1636 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1637 priv = &buf_alloc->priv_buf[i];
46a3df9f 1638
bb1fe9ea
YL		 1639 priv->enable = 0;
1640 priv->wl.low = 0;
1641 priv->wl.high = 0;
1642 priv->buf_size = 0;
1643
1644 if (!(hdev->hw_tc_map & BIT(i)))
1645 continue;
1646
1647 priv->enable = 1;
46a3df9f
S		 1648
1649 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1650 priv->wl.low = 128;
1651 priv->wl.high = priv->wl.low + hdev->mps;
1652 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1653 } else {
1654 priv->wl.low = 0;
1655 priv->wl.high = hdev->mps;
1656 priv->buf_size = priv->wl.high;
1657 }
1658 }
1659
acf61ecd 1660 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1661 return 0;
1662
1663 /* step 3, try to reduce the number of pfc disabled TCs,
1664 * which have private buffer
1665 */
1666 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1667 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1668
1669 /* let the last to be cleared first */
1670 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1671 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1672
1673 if (hdev->hw_tc_map & BIT(i) &&
1674 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1675 /* Clear the no pfc TC private buffer */
1676 priv->wl.low = 0;
1677 priv->wl.high = 0;
1678 priv->buf_size = 0;
1679 priv->enable = 0;
1680 no_pfc_priv_num--;
1681 }
1682
acf61ecd 1683 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1684 no_pfc_priv_num == 0)
1685 break;
1686 }
1687
acf61ecd 1688 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1689 return 0;
1690
1691 /* step 4, try to reduce the number of pfc enabled TCs
1692 * which have private buffer.
1693 */
acf61ecd 1694 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1695
1696 /* let the last to be cleared first */
1697 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1698 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1699
1700 if (hdev->hw_tc_map & BIT(i) &&
1701 hdev->tm_info.hw_pfc_map & BIT(i)) {
1702 /* Reduce the number of pfc TC with private buffer */
1703 priv->wl.low = 0;
1704 priv->enable = 0;
1705 priv->wl.high = 0;
1706 priv->buf_size = 0;
1707 pfc_priv_num--;
1708 }
1709
acf61ecd 1710 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1711 pfc_priv_num == 0)
1712 break;
1713 }
acf61ecd 1714 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1715 return 0;
1716
1717 return -ENOMEM;
1718}
1719
acf61ecd
YL		 1720static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1721 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1722{
d44f9b63 1723 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1724 struct hclge_desc desc;
1725 int ret;
1726 int i;
1727
1728 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1729 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1730
1731 /* Alloc private buffer TCs */
1732 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1733 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1734
1735 req->buf_num[i] =
1736 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1737 req->buf_num[i] |=
5bca3b94 1738 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1739 }
1740
b8c8bf47 1741 req->shared_buf =
acf61ecd 1742 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1743 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1744
46a3df9f
S		 1745 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1746 if (ret) {
1747 dev_err(&hdev->pdev->dev,
1748 "rx private buffer alloc cmd failed %d\n", ret);
1749 return ret;
1750 }
1751
1752 return 0;
1753}
1754
1755#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1756
acf61ecd
YL		 1757static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1758 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1759{
1760 struct hclge_rx_priv_wl_buf *req;
1761 struct hclge_priv_buf *priv;
1762 struct hclge_desc desc[2];
1763 int i, j;
1764 int ret;
1765
1766 for (i = 0; i < 2; i++) {
1767 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1768 false);
1769 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1770
1771 /* The first descriptor set the NEXT bit to 1 */
1772 if (i == 0)
1773 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1774 else
1775 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1776
1777 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1778 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1779
1780 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1781 req->tc_wl[j].high =
1782 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1783 req->tc_wl[j].high |=
1784 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1785 HCLGE_RX_PRIV_EN_B);
1786 req->tc_wl[j].low =
1787 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1788 req->tc_wl[j].low |=
1789 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1790 HCLGE_RX_PRIV_EN_B);
1791 }
1792 }
1793
1794 /* Send 2 descriptor at one time */
1795 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1796 if (ret) {
1797 dev_err(&hdev->pdev->dev,
1798 "rx private waterline config cmd failed %d\n",
1799 ret);
1800 return ret;
1801 }
1802 return 0;
1803}
1804
acf61ecd
YL		 1805static int hclge_common_thrd_config(struct hclge_dev *hdev,
1806 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1807{
acf61ecd 1808 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1809 struct hclge_rx_com_thrd *req;
1810 struct hclge_desc desc[2];
1811 struct hclge_tc_thrd *tc;
1812 int i, j;
1813 int ret;
1814
1815 for (i = 0; i < 2; i++) {
1816 hclge_cmd_setup_basic_desc(&desc[i],
1817 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1818 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1819
1820 /* The first descriptor set the NEXT bit to 1 */
1821 if (i == 0)
1822 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1823 else
1824 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1825
1826 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1827 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1828
1829 req->com_thrd[j].high =
1830 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1831 req->com_thrd[j].high |=
1832 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1833 HCLGE_RX_PRIV_EN_B);
1834 req->com_thrd[j].low =
1835 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1836 req->com_thrd[j].low |=
1837 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1838 HCLGE_RX_PRIV_EN_B);
1839 }
1840 }
1841
1842 /* Send 2 descriptors at one time */
1843 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1844 if (ret) {
1845 dev_err(&hdev->pdev->dev,
1846 "common threshold config cmd failed %d\n", ret);
1847 return ret;
1848 }
1849 return 0;
1850}
1851
acf61ecd
YL		 1852static int hclge_common_wl_config(struct hclge_dev *hdev,
1853 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1854{
acf61ecd 1855 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1856 struct hclge_rx_com_wl *req;
1857 struct hclge_desc desc;
1858 int ret;
1859
1860 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1861
1862 req = (struct hclge_rx_com_wl *)desc.data;
1863 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1864 req->com_wl.high |=
1865 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1866 HCLGE_RX_PRIV_EN_B);
1867
1868 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1869 req->com_wl.low |=
1870 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1871 HCLGE_RX_PRIV_EN_B);
1872
1873 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1874 if (ret) {
1875 dev_err(&hdev->pdev->dev,
1876 "common waterline config cmd failed %d\n", ret);
1877 return ret;
1878 }
1879
1880 return 0;
1881}
1882
1883int hclge_buffer_alloc(struct hclge_dev *hdev)
1884{
acf61ecd 1885 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1886 int ret;
1887
acf61ecd
YL		 1888 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1889 if (!pkt_buf)
46a3df9f
S		 1890 return -ENOMEM;
1891
acf61ecd 1892 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1893 if (ret) {
1894 dev_err(&hdev->pdev->dev,
1895 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1896 goto out;
9ffe79a9
YL		 1897 }
1898
acf61ecd 1899 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1900 if (ret) {
1901 dev_err(&hdev->pdev->dev,
1902 "could not alloc tx buffers %d\n", ret);
acf61ecd 1903 goto out;
46a3df9f
S		 1904 }
1905
acf61ecd 1906 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1907 if (ret) {
1908 dev_err(&hdev->pdev->dev,
1909 "could not calc rx priv buffer size for all TCs %d\n",
1910 ret);
acf61ecd 1911 goto out;
46a3df9f
S		 1912 }
1913
acf61ecd 1914 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1915 if (ret) {
1916 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1917 ret);
acf61ecd 1918 goto out;
46a3df9f
S		 1919 }
1920
2daf4a65 1921 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1922 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1923 if (ret) {
1924 dev_err(&hdev->pdev->dev,
1925 "could not configure rx private waterline %d\n",
1926 ret);
acf61ecd 1927 goto out;
2daf4a65 1928 }
46a3df9f 1929
acf61ecd 1930 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1931 if (ret) {
1932 dev_err(&hdev->pdev->dev,
1933 "could not configure common threshold %d\n",
1934 ret);
acf61ecd 1935 goto out;
2daf4a65 1936 }
46a3df9f
S		 1937 }
1938
acf61ecd
YL		 1939 ret = hclge_common_wl_config(hdev, pkt_buf);
1940 if (ret)
46a3df9f
S		 1941 dev_err(&hdev->pdev->dev,
1942 "could not configure common waterline %d\n", ret);
46a3df9f 1943
acf61ecd
YL		 1944out:
1945 kfree(pkt_buf);
1946 return ret;
46a3df9f
S		 1947}
1948
1949static int hclge_init_roce_base_info(struct hclge_vport *vport)
1950{
1951 struct hnae3_handle *roce = &vport->roce;
1952 struct hnae3_handle *nic = &vport->nic;
1953
887c3820 1954 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1955
1956 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1957 vport->back->num_msi_left == 0)
1958 return -EINVAL;
1959
1960 roce->rinfo.base_vector = vport->back->roce_base_vector;
1961
1962 roce->rinfo.netdev = nic->kinfo.netdev;
1963 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1964
1965 roce->pdev = nic->pdev;
1966 roce->ae_algo = nic->ae_algo;
1967 roce->numa_node_mask = nic->numa_node_mask;
1968
1969 return 0;
1970}
1971
887c3820 1972static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1973{
1974 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1975 int vectors;
1976 int i;
46a3df9f 1977
887c3820
SM		 1978 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1979 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1980 if (vectors < 0) {
1981 dev_err(&pdev->dev,
1982 "failed(%d) to allocate MSI/MSI-X vectors\n",
1983 vectors);
1984 return vectors;
46a3df9f 1985 }
887c3820
SM		 1986 if (vectors < hdev->num_msi)
1987 dev_warn(&hdev->pdev->dev,
1988 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1989 hdev->num_msi, vectors);
46a3df9f 1990
887c3820
SM		 1991 hdev->num_msi = vectors;
1992 hdev->num_msi_left = vectors;
1993 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 1994 hdev->roce_base_vector = hdev->base_msi_vector +
1995 HCLGE_ROCE_VECTOR_OFFSET;
1996
46a3df9f
S		 1997 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1998 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1999 if (!hdev->vector_status) {
2000 pci_free_irq_vectors(pdev);
46a3df9f 2001 return -ENOMEM;
887c3820 2002 }
46a3df9f
S		 2003
2004 for (i = 0; i < hdev->num_msi; i++)
2005 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2006
887c3820
SM		 2007 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2008 sizeof(int), GFP_KERNEL);
2009 if (!hdev->vector_irq) {
2010 pci_free_irq_vectors(pdev);
2011 return -ENOMEM;
46a3df9f 2012 }
46a3df9f
S		 2013
2014 return 0;
2015}
2016
2017static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2018{
2019 struct hclge_mac *mac = &hdev->hw.mac;
2020
2021 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2022 mac->duplex = (u8)duplex;
2023 else
2024 mac->duplex = HCLGE_MAC_FULL;
2025
2026 mac->speed = speed;
2027}
2028
2029int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2030{
d44f9b63 2031 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2032 struct hclge_desc desc;
2033 int ret;
2034
d44f9b63 2035 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2036
2037 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2038
2039 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2040
2041 switch (speed) {
2042 case HCLGE_MAC_SPEED_10M:
2043 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2044 HCLGE_CFG_SPEED_S, 6);
2045 break;
2046 case HCLGE_MAC_SPEED_100M:
2047 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2048 HCLGE_CFG_SPEED_S, 7);
2049 break;
2050 case HCLGE_MAC_SPEED_1G:
2051 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2052 HCLGE_CFG_SPEED_S, 0);
2053 break;
2054 case HCLGE_MAC_SPEED_10G:
2055 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2056 HCLGE_CFG_SPEED_S, 1);
2057 break;
2058 case HCLGE_MAC_SPEED_25G:
2059 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2060 HCLGE_CFG_SPEED_S, 2);
2061 break;
2062 case HCLGE_MAC_SPEED_40G:
2063 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2064 HCLGE_CFG_SPEED_S, 3);
2065 break;
2066 case HCLGE_MAC_SPEED_50G:
2067 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2068 HCLGE_CFG_SPEED_S, 4);
2069 break;
2070 case HCLGE_MAC_SPEED_100G:
2071 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2072 HCLGE_CFG_SPEED_S, 5);
2073 break;
2074 default:
d7629e74 2075 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2076 return -EINVAL;
2077 }
2078
2079 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2080 1);
2081
2082 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2083 if (ret) {
2084 dev_err(&hdev->pdev->dev,
2085 "mac speed/duplex config cmd failed %d.\n", ret);
2086 return ret;
2087 }
2088
2089 hclge_check_speed_dup(hdev, duplex, speed);
2090
2091 return 0;
2092}
2093
2094static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2095 u8 duplex)
2096{
2097 struct hclge_vport *vport = hclge_get_vport(handle);
2098 struct hclge_dev *hdev = vport->back;
2099
2100 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2101}
2102
2103static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2104 u8 *duplex)
2105{
d44f9b63 2106 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2107 struct hclge_desc desc;
2108 int speed_tmp;
2109 int ret;
2110
d44f9b63 2111 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2112
2113 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2114 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2115 if (ret) {
2116 dev_err(&hdev->pdev->dev,
2117 "mac speed/autoneg/duplex query cmd failed %d\n",
2118 ret);
2119 return ret;
2120 }
2121
2122 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2123 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2124 HCLGE_QUERY_SPEED_S);
2125
2126 ret = hclge_parse_speed(speed_tmp, speed);
2127 if (ret) {
2128 dev_err(&hdev->pdev->dev,
2129 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2130 return -EIO;
2131 }
2132
2133 return 0;
2134}
2135
2136static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2137{
2138 struct hclge_mac *mac = &hdev->hw.mac;
d44f9b63 2139 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2140 struct hclge_desc desc;
2141 int ret;
2142
d44f9b63 2143 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2144
2145 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2146 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2147 if (ret) {
2148 dev_err(&hdev->pdev->dev,
2149 "autoneg result query cmd failed %d.\n", ret);
2150 return ret;
2151 }
2152
2153 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2154
2155 return 0;
2156}
2157
2158static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2159{
d44f9b63 2160 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2161 struct hclge_desc desc;
a90bb9a5 2162 u32 flag = 0;
46a3df9f
S		 2163 int ret;
2164
2165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2166
d44f9b63 2167 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2168 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2169 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2170
2171 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2172 if (ret) {
2173 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2174 ret);
2175 return ret;
2176 }
2177
2178 return 0;
2179}
2180
2181static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2182{
2183 struct hclge_vport *vport = hclge_get_vport(handle);
2184 struct hclge_dev *hdev = vport->back;
2185
2186 return hclge_set_autoneg_en(hdev, enable);
2187}
2188
2189static int hclge_get_autoneg(struct hnae3_handle *handle)
2190{
2191 struct hclge_vport *vport = hclge_get_vport(handle);
2192 struct hclge_dev *hdev = vport->back;
2193
2194 hclge_query_autoneg_result(hdev);
2195
2196 return hdev->hw.mac.autoneg;
2197}
2198
2199static int hclge_mac_init(struct hclge_dev *hdev)
2200{
2201 struct hclge_mac *mac = &hdev->hw.mac;
2202 int ret;
2203
2204 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2205 if (ret) {
2206 dev_err(&hdev->pdev->dev,
2207 "Config mac speed dup fail ret=%d\n", ret);
2208 return ret;
2209 }
2210
2211 mac->link = 0;
2212
46a3df9f
S		 2213 /* Initialize the MTA table work mode */
2214 hdev->accept_mta_mc = true;
2215 hdev->enable_mta = true;
2216 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2217
2218 ret = hclge_set_mta_filter_mode(hdev,
2219 hdev->mta_mac_sel_type,
2220 hdev->enable_mta);
2221 if (ret) {
2222 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2223 ret);
2224 return ret;
2225 }
2226
2227 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2228}
2229
c1a81619
SM		 2230static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2231{
2232 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2233 schedule_work(&hdev->mbx_service_task);
2234}
2235
cb1b9f77
SM		 2236static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2237{
2238 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2239 schedule_work(&hdev->rst_service_task);
2240}
2241
46a3df9f
S		 2242static void hclge_task_schedule(struct hclge_dev *hdev)
2243{
2244 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2245 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2246 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2247 (void)schedule_work(&hdev->service_task);
2248}
2249
2250static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2251{
d44f9b63 2252 struct hclge_link_status_cmd *req;
46a3df9f
S		 2253 struct hclge_desc desc;
2254 int link_status;
2255 int ret;
2256
2257 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2258 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2259 if (ret) {
2260 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2261 ret);
2262 return ret;
2263 }
2264
d44f9b63 2265 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2266 link_status = req->status & HCLGE_LINK_STATUS;
2267
2268 return !!link_status;
2269}
2270
2271static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2272{
2273 int mac_state;
2274 int link_stat;
2275
2276 mac_state = hclge_get_mac_link_status(hdev);
2277
2278 if (hdev->hw.mac.phydev) {
2279 if (!genphy_read_status(hdev->hw.mac.phydev))
2280 link_stat = mac_state &
2281 hdev->hw.mac.phydev->link;
2282 else
2283 link_stat = 0;
2284
2285 } else {
2286 link_stat = mac_state;
2287 }
2288
2289 return !!link_stat;
2290}
2291
2292static void hclge_update_link_status(struct hclge_dev *hdev)
2293{
2294 struct hnae3_client *client = hdev->nic_client;
2295 struct hnae3_handle *handle;
2296 int state;
2297 int i;
2298
2299 if (!client)
2300 return;
2301 state = hclge_get_mac_phy_link(hdev);
2302 if (state != hdev->hw.mac.link) {
2303 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2304 handle = &hdev->vport[i].nic;
2305 client->ops->link_status_change(handle, state);
2306 }
2307 hdev->hw.mac.link = state;
2308 }
2309}
2310
2311static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2312{
2313 struct hclge_mac mac = hdev->hw.mac;
2314 u8 duplex;
2315 int speed;
2316 int ret;
2317
2318 /* get the speed and duplex as autoneg'result from mac cmd when phy
2319 * doesn't exit.
2320 */
c040366b 2321 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2322 return 0;
2323
2324 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2325 if (ret) {
2326 dev_err(&hdev->pdev->dev,
2327 "mac autoneg/speed/duplex query failed %d\n", ret);
2328 return ret;
2329 }
2330
2331 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2332 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2333 if (ret) {
2334 dev_err(&hdev->pdev->dev,
2335 "mac speed/duplex config failed %d\n", ret);
2336 return ret;
2337 }
2338 }
2339
2340 return 0;
2341}
2342
2343static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2344{
2345 struct hclge_vport *vport = hclge_get_vport(handle);
2346 struct hclge_dev *hdev = vport->back;
2347
2348 return hclge_update_speed_duplex(hdev);
2349}
2350
2351static int hclge_get_status(struct hnae3_handle *handle)
2352{
2353 struct hclge_vport *vport = hclge_get_vport(handle);
2354 struct hclge_dev *hdev = vport->back;
2355
2356 hclge_update_link_status(hdev);
2357
2358 return hdev->hw.mac.link;
2359}
2360
d039ef68 2361static void hclge_service_timer(struct timer_list *t)
46a3df9f 2362{
d039ef68 2363 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2364
d039ef68 2365 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 2366 hclge_task_schedule(hdev);
2367}
2368
2369static void hclge_service_complete(struct hclge_dev *hdev)
2370{
2371 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2372
2373 /* Flush memory before next watchdog */
2374 smp_mb__before_atomic();
2375 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2376}
2377
ca1d7669
SM		 2378static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2379{
2380 u32 rst_src_reg;
c1a81619 2381 u32 cmdq_src_reg;
ca1d7669
SM		 2382
2383 /* fetch the events from their corresponding regs */
2384 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
c1a81619
SM		 2385 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2386
2387 /* Assumption: If by any chance reset and mailbox events are reported
2388 * together then we will only process reset event in this go and will
2389 * defer the processing of the mailbox events. Since, we would have not
2390 * cleared RX CMDQ event this time we would receive again another
2391 * interrupt from H/W just for the mailbox.
2392 */
ca1d7669
SM		 2393
2394 /* check for vector0 reset event sources */
2395 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2396 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2397 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2398 return HCLGE_VECTOR0_EVENT_RST;
2399 }
2400
2401 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2402 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2403 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2404 return HCLGE_VECTOR0_EVENT_RST;
2405 }
2406
2407 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2408 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2409 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2410 return HCLGE_VECTOR0_EVENT_RST;
2411 }
2412
c1a81619
SM		 2413 /* check for vector0 mailbox(=CMDQ RX) event source */
2414 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2415 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2416 *clearval = cmdq_src_reg;
2417 return HCLGE_VECTOR0_EVENT_MBX;
2418 }
ca1d7669
SM		 2419
2420 return HCLGE_VECTOR0_EVENT_OTHER;
2421}
2422
2423static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2424 u32 regclr)
2425{
c1a81619
SM		 2426 switch (event_type) {
2427 case HCLGE_VECTOR0_EVENT_RST:
ca1d7669 2428 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
c1a81619
SM		 2429 break;
2430 case HCLGE_VECTOR0_EVENT_MBX:
2431 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2432 break;
2433 }
ca1d7669
SM		 2434}
2435
466b0c00
L		 2436static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2437{
2438 writel(enable ? 1 : 0, vector->addr);
2439}
2440
2441static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2442{
2443 struct hclge_dev *hdev = data;
ca1d7669
SM		 2444 u32 event_cause;
2445 u32 clearval;
466b0c00
L		 2446
2447 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2448 event_cause = hclge_check_event_cause(hdev, &clearval);
2449
c1a81619 2450 /* vector 0 interrupt is shared with reset and mailbox source events.*/
ca1d7669
SM		 2451 switch (event_cause) {
2452 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2453 hclge_reset_task_schedule(hdev);
ca1d7669 2454 break;
c1a81619
SM		 2455 case HCLGE_VECTOR0_EVENT_MBX:
2456 /* If we are here then,
2457 * 1. Either we are not handling any mbx task and we are not
2458 * scheduled as well
2459 * OR
2460 * 2. We could be handling a mbx task but nothing more is
2461 * scheduled.
2462 * In both cases, we should schedule mbx task as there are more
2463 * mbx messages reported by this interrupt.
2464 */
2465 hclge_mbx_task_schedule(hdev);
2466
ca1d7669
SM		 2467 default:
2468 dev_dbg(&hdev->pdev->dev,
2469 "received unknown or unhandled event of vector0\n");
2470 break;
2471 }
2472
2473 /* we should clear the source of interrupt */
2474 hclge_clear_event_cause(hdev, event_cause, clearval);
2475 hclge_enable_vector(&hdev->misc_vector, true);
466b0c00
L		 2476
2477 return IRQ_HANDLED;
2478}
2479
2480static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2481{
2482 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2483 hdev->num_msi_left += 1;
2484 hdev->num_msi_used -= 1;
2485}
2486
2487static void hclge_get_misc_vector(struct hclge_dev *hdev)
2488{
2489 struct hclge_misc_vector *vector = &hdev->misc_vector;
2490
2491 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2492
2493 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2494 hdev->vector_status[0] = 0;
2495
2496 hdev->num_msi_left -= 1;
2497 hdev->num_msi_used += 1;
2498}
2499
2500static int hclge_misc_irq_init(struct hclge_dev *hdev)
2501{
2502 int ret;
2503
2504 hclge_get_misc_vector(hdev);
2505
ca1d7669
SM		 2506 /* this would be explicitly freed in the end */
2507 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2508 0, "hclge_misc", hdev);
466b0c00
L		 2509 if (ret) {
2510 hclge_free_vector(hdev, 0);
2511 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2512 hdev->misc_vector.vector_irq);
2513 }
2514
2515 return ret;
2516}
2517
ca1d7669
SM		 2518static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2519{
2520 free_irq(hdev->misc_vector.vector_irq, hdev);
2521 hclge_free_vector(hdev, 0);
2522}
2523
4ed340ab
L		 2524static int hclge_notify_client(struct hclge_dev *hdev,
2525 enum hnae3_reset_notify_type type)
2526{
2527 struct hnae3_client *client = hdev->nic_client;
2528 u16 i;
2529
2530 if (!client->ops->reset_notify)
2531 return -EOPNOTSUPP;
2532
2533 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2534 struct hnae3_handle *handle = &hdev->vport[i].nic;
2535 int ret;
2536
2537 ret = client->ops->reset_notify(handle, type);
2538 if (ret)
2539 return ret;
2540 }
2541
2542 return 0;
2543}
2544
2545static int hclge_reset_wait(struct hclge_dev *hdev)
2546{
2547#define HCLGE_RESET_WATI_MS 100
2548#define HCLGE_RESET_WAIT_CNT 5
2549 u32 val, reg, reg_bit;
2550 u32 cnt = 0;
2551
2552 switch (hdev->reset_type) {
2553 case HNAE3_GLOBAL_RESET:
2554 reg = HCLGE_GLOBAL_RESET_REG;
2555 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2556 break;
2557 case HNAE3_CORE_RESET:
2558 reg = HCLGE_GLOBAL_RESET_REG;
2559 reg_bit = HCLGE_CORE_RESET_BIT;
2560 break;
2561 case HNAE3_FUNC_RESET:
2562 reg = HCLGE_FUN_RST_ING;
2563 reg_bit = HCLGE_FUN_RST_ING_B;
2564 break;
2565 default:
2566 dev_err(&hdev->pdev->dev,
2567 "Wait for unsupported reset type: %d\n",
2568 hdev->reset_type);
2569 return -EINVAL;
2570 }
2571
2572 val = hclge_read_dev(&hdev->hw, reg);
2573 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2574 msleep(HCLGE_RESET_WATI_MS);
2575 val = hclge_read_dev(&hdev->hw, reg);
2576 cnt++;
2577 }
2578
4ed340ab
L		 2579 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2580 dev_warn(&hdev->pdev->dev,
2581 "Wait for reset timeout: %d\n", hdev->reset_type);
2582 return -EBUSY;
2583 }
2584
2585 return 0;
2586}
2587
2588static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2589{
2590 struct hclge_desc desc;
2591 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2592 int ret;
2593
2594 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2595 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2596 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2597 req->fun_reset_vfid = func_id;
2598
2599 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2600 if (ret)
2601 dev_err(&hdev->pdev->dev,
2602 "send function reset cmd fail, status =%d\n", ret);
2603
2604 return ret;
2605}
2606
f2f432f2 2607static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2608{
2609 struct pci_dev *pdev = hdev->pdev;
2610 u32 val;
2611
f2f432f2 2612 switch (hdev->reset_type) {
4ed340ab
L		 2613 case HNAE3_GLOBAL_RESET:
2614 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2615 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2616 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2617 dev_info(&pdev->dev, "Global Reset requested\n");
2618 break;
2619 case HNAE3_CORE_RESET:
2620 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2621 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2622 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2623 dev_info(&pdev->dev, "Core Reset requested\n");
2624 break;
2625 case HNAE3_FUNC_RESET:
2626 dev_info(&pdev->dev, "PF Reset requested\n");
2627 hclge_func_reset_cmd(hdev, 0);
cb1b9f77
SM		 2628 /* schedule again to check later */
2629 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2630 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2631 break;
2632 default:
2633 dev_warn(&pdev->dev,
f2f432f2 2634 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2635 break;
2636 }
2637}
2638
f2f432f2
SM		 2639static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2640 unsigned long *addr)
2641{
2642 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2643
2644 /* return the highest priority reset level amongst all */
2645 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2646 rst_level = HNAE3_GLOBAL_RESET;
2647 else if (test_bit(HNAE3_CORE_RESET, addr))
2648 rst_level = HNAE3_CORE_RESET;
2649 else if (test_bit(HNAE3_IMP_RESET, addr))
2650 rst_level = HNAE3_IMP_RESET;
2651 else if (test_bit(HNAE3_FUNC_RESET, addr))
2652 rst_level = HNAE3_FUNC_RESET;
2653
2654 /* now, clear all other resets */
2655 clear_bit(HNAE3_GLOBAL_RESET, addr);
2656 clear_bit(HNAE3_CORE_RESET, addr);
2657 clear_bit(HNAE3_IMP_RESET, addr);
2658 clear_bit(HNAE3_FUNC_RESET, addr);
2659
2660 return rst_level;
2661}
2662
2663static void hclge_reset(struct hclge_dev *hdev)
2664{
2665 /* perform reset of the stack & ae device for a client */
2666
2667 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2668
2669 if (!hclge_reset_wait(hdev)) {
2670 rtnl_lock();
2671 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2672 hclge_reset_ae_dev(hdev->ae_dev);
2673 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2674 rtnl_unlock();
2675 } else {
2676 /* schedule again to check pending resets later */
2677 set_bit(hdev->reset_type, &hdev->reset_pending);
2678 hclge_reset_task_schedule(hdev);
2679 }
2680
2681 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2682}
2683
4ed340ab
L		 2684static void hclge_reset_event(struct hnae3_handle *handle,
2685 enum hnae3_reset_type reset)
2686{
2687 struct hclge_vport *vport = hclge_get_vport(handle);
2688 struct hclge_dev *hdev = vport->back;
2689
2690 dev_info(&hdev->pdev->dev,
2691 "Receive reset event , reset_type is %d", reset);
2692
2693 switch (reset) {
2694 case HNAE3_FUNC_RESET:
2695 case HNAE3_CORE_RESET:
2696 case HNAE3_GLOBAL_RESET:
cb1b9f77
SM		 2697 /* request reset & schedule reset task */
2698 set_bit(reset, &hdev->reset_request);
2699 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2700 break;
2701 default:
2702 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2703 break;
2704 }
2705}
2706
2707static void hclge_reset_subtask(struct hclge_dev *hdev)
2708{
f2f432f2
SM		 2709 /* check if there is any ongoing reset in the hardware. This status can
2710 * be checked from reset_pending. If there is then, we need to wait for
2711 * hardware to complete reset.
2712 * a. If we are able to figure out in reasonable time that hardware
2713 * has fully resetted then, we can proceed with driver, client
2714 * reset.
2715 * b. else, we can come back later to check this status so re-sched
2716 * now.
2717 */
2718 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2719 if (hdev->reset_type != HNAE3_NONE_RESET)
2720 hclge_reset(hdev);
4ed340ab 2721
f2f432f2
SM		 2722 /* check if we got any *new* reset requests to be honored */
2723 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2724 if (hdev->reset_type != HNAE3_NONE_RESET)
2725 hclge_do_reset(hdev);
4ed340ab 2726
4ed340ab
L		 2727 hdev->reset_type = HNAE3_NONE_RESET;
2728}
2729
cb1b9f77 2730static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2731{
cb1b9f77
SM		 2732 struct hclge_dev *hdev =
2733 container_of(work, struct hclge_dev, rst_service_task);
2734
2735 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2736 return;
2737
2738 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2739
4ed340ab 2740 hclge_reset_subtask(hdev);
cb1b9f77
SM		 2741
2742 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2743}
2744
c1a81619
SM		 2745static void hclge_mailbox_service_task(struct work_struct *work)
2746{
2747 struct hclge_dev *hdev =
2748 container_of(work, struct hclge_dev, mbx_service_task);
2749
2750 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2751 return;
2752
2753 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2754
2755 hclge_mbx_handler(hdev);
2756
2757 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2758}
2759
46a3df9f
S		 2760static void hclge_service_task(struct work_struct *work)
2761{
2762 struct hclge_dev *hdev =
2763 container_of(work, struct hclge_dev, service_task);
2764
2765 hclge_update_speed_duplex(hdev);
2766 hclge_update_link_status(hdev);
2767 hclge_update_stats_for_all(hdev);
2768 hclge_service_complete(hdev);
2769}
2770
2771static void hclge_disable_sriov(struct hclge_dev *hdev)
2772{
2a32ca13
AB		 2773 /* If our VFs are assigned we cannot shut down SR-IOV
2774 * without causing issues, so just leave the hardware
2775 * available but disabled
2776 */
2777 if (pci_vfs_assigned(hdev->pdev)) {
2778 dev_warn(&hdev->pdev->dev,
2779 "disabling driver while VFs are assigned\n");
2780 return;
2781 }
46a3df9f 2782
2a32ca13 2783 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2784}
2785
2786struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2787{
2788 /* VF handle has no client */
2789 if (!handle->client)
2790 return container_of(handle, struct hclge_vport, nic);
2791 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2792 return container_of(handle, struct hclge_vport, roce);
2793 else
2794 return container_of(handle, struct hclge_vport, nic);
2795}
2796
2797static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2798 struct hnae3_vector_info *vector_info)
2799{
2800 struct hclge_vport *vport = hclge_get_vport(handle);
2801 struct hnae3_vector_info *vector = vector_info;
2802 struct hclge_dev *hdev = vport->back;
2803 int alloc = 0;
2804 int i, j;
2805
2806 vector_num = min(hdev->num_msi_left, vector_num);
2807
2808 for (j = 0; j < vector_num; j++) {
2809 for (i = 1; i < hdev->num_msi; i++) {
2810 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2811 vector->vector = pci_irq_vector(hdev->pdev, i);
2812 vector->io_addr = hdev->hw.io_base +
2813 HCLGE_VECTOR_REG_BASE +
2814 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2815 vport->vport_id *
2816 HCLGE_VECTOR_VF_OFFSET;
2817 hdev->vector_status[i] = vport->vport_id;
887c3820 2818 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2819
2820 vector++;
2821 alloc++;
2822
2823 break;
2824 }
2825 }
2826 }
2827 hdev->num_msi_left -= alloc;
2828 hdev->num_msi_used += alloc;
2829
2830 return alloc;
2831}
2832
2833static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2834{
2835 int i;
2836
887c3820
SM		 2837 for (i = 0; i < hdev->num_msi; i++)
2838 if (vector == hdev->vector_irq[i])
2839 return i;
2840
46a3df9f
S		 2841 return -EINVAL;
2842}
2843
2844static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2845{
2846 return HCLGE_RSS_KEY_SIZE;
2847}
2848
2849static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2850{
2851 return HCLGE_RSS_IND_TBL_SIZE;
2852}
2853
2854static int hclge_get_rss_algo(struct hclge_dev *hdev)
2855{
d44f9b63 2856 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2857 struct hclge_desc desc;
2858 int rss_hash_algo;
2859 int ret;
2860
2861 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2862
2863 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2864 if (ret) {
2865 dev_err(&hdev->pdev->dev,
2866 "Get link status error, status =%d\n", ret);
2867 return ret;
2868 }
2869
d44f9b63 2870 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2871 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2872
2873 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2874 return ETH_RSS_HASH_TOP;
2875
2876 return -EINVAL;
2877}
2878
2879static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2880 const u8 hfunc, const u8 *key)
2881{
d44f9b63 2882 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2883 struct hclge_desc desc;
2884 int key_offset;
2885 int key_size;
2886 int ret;
2887
d44f9b63 2888 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2889
2890 for (key_offset = 0; key_offset < 3; key_offset++) {
2891 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2892 false);
2893
2894 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2895 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2896
2897 if (key_offset == 2)
2898 key_size =
2899 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2900 else
2901 key_size = HCLGE_RSS_HASH_KEY_NUM;
2902
2903 memcpy(req->hash_key,
2904 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2905
2906 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2907 if (ret) {
2908 dev_err(&hdev->pdev->dev,
2909 "Configure RSS config fail, status = %d\n",
2910 ret);
2911 return ret;
2912 }
2913 }
2914 return 0;
2915}
2916
2917static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2918{
d44f9b63 2919 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2920 struct hclge_desc desc;
2921 int i, j;
2922 int ret;
2923
d44f9b63 2924 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2925
2926 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2927 hclge_cmd_setup_basic_desc
2928 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2929
a90bb9a5
YL		 2930 req->start_table_index =
2931 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2932 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2933
2934 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2935 req->rss_result[j] =
2936 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2937
2938 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2939 if (ret) {
2940 dev_err(&hdev->pdev->dev,
2941 "Configure rss indir table fail,status = %d\n",
2942 ret);
2943 return ret;
2944 }
2945 }
2946 return 0;
2947}
2948
2949static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2950 u16 *tc_size, u16 *tc_offset)
2951{
d44f9b63 2952 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2953 struct hclge_desc desc;
2954 int ret;
2955 int i;
2956
2957 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2958 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2959
2960 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2961 u16 mode = 0;
2962
2963 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2964 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 2965 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 2966 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 2967 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2968
2969 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2970 }
2971
2972 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2973 if (ret) {
2974 dev_err(&hdev->pdev->dev,
2975 "Configure rss tc mode fail, status = %d\n", ret);
2976 return ret;
2977 }
2978
2979 return 0;
2980}
2981
2982static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2983{
d44f9b63 2984 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2985 struct hclge_desc desc;
2986 int ret;
2987
2988 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2989
d44f9b63 2990 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
46a3df9f
S		 2991 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2992 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2993 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2994 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2995 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2996 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2997 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2998 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2999 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3000 if (ret) {
3001 dev_err(&hdev->pdev->dev,
3002 "Configure rss input fail, status = %d\n", ret);
3003 return ret;
3004 }
3005
3006 return 0;
3007}
3008
3009static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3010 u8 *key, u8 *hfunc)
3011{
3012 struct hclge_vport *vport = hclge_get_vport(handle);
3013 struct hclge_dev *hdev = vport->back;
3014 int i;
3015
3016 /* Get hash algorithm */
3017 if (hfunc)
3018 *hfunc = hclge_get_rss_algo(hdev);
3019
3020 /* Get the RSS Key required by the user */
3021 if (key)
3022 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3023
3024 /* Get indirect table */
3025 if (indir)
3026 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3027 indir[i] = vport->rss_indirection_tbl[i];
3028
3029 return 0;
3030}
3031
3032static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3033 const u8 *key, const u8 hfunc)
3034{
3035 struct hclge_vport *vport = hclge_get_vport(handle);
3036 struct hclge_dev *hdev = vport->back;
3037 u8 hash_algo;
3038 int ret, i;
3039
3040 /* Set the RSS Hash Key if specififed by the user */
3041 if (key) {
3042 /* Update the shadow RSS key with user specified qids */
3043 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3044
3045 if (hfunc == ETH_RSS_HASH_TOP ||
3046 hfunc == ETH_RSS_HASH_NO_CHANGE)
3047 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3048 else
3049 return -EINVAL;
3050 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3051 if (ret)
3052 return ret;
3053 }
3054
3055 /* Update the shadow RSS table with user specified qids */
3056 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3057 vport->rss_indirection_tbl[i] = indir[i];
3058
3059 /* Update the hardware */
3060 ret = hclge_set_rss_indir_table(hdev, indir);
3061 return ret;
3062}
3063
f7db940a
L		 3064static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3065{
3066 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3067
3068 if (nfc->data & RXH_L4_B_2_3)
3069 hash_sets |= HCLGE_D_PORT_BIT;
3070 else
3071 hash_sets &= ~HCLGE_D_PORT_BIT;
3072
3073 if (nfc->data & RXH_IP_SRC)
3074 hash_sets |= HCLGE_S_IP_BIT;
3075 else
3076 hash_sets &= ~HCLGE_S_IP_BIT;
3077
3078 if (nfc->data & RXH_IP_DST)
3079 hash_sets |= HCLGE_D_IP_BIT;
3080 else
3081 hash_sets &= ~HCLGE_D_IP_BIT;
3082
3083 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3084 hash_sets |= HCLGE_V_TAG_BIT;
3085
3086 return hash_sets;
3087}
3088
3089static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3090 struct ethtool_rxnfc *nfc)
3091{
3092 struct hclge_vport *vport = hclge_get_vport(handle);
3093 struct hclge_dev *hdev = vport->back;
3094 struct hclge_rss_input_tuple_cmd *req;
3095 struct hclge_desc desc;
3096 u8 tuple_sets;
3097 int ret;
3098
3099 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3100 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3101 return -EINVAL;
3102
3103 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3104 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3105 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3106 if (ret) {
3107 dev_err(&hdev->pdev->dev,
3108 "Read rss tuple fail, status = %d\n", ret);
3109 return ret;
3110 }
3111
3112 hclge_cmd_reuse_desc(&desc, false);
3113
3114 tuple_sets = hclge_get_rss_hash_bits(nfc);
3115 switch (nfc->flow_type) {
3116 case TCP_V4_FLOW:
3117 req->ipv4_tcp_en = tuple_sets;
3118 break;
3119 case TCP_V6_FLOW:
3120 req->ipv6_tcp_en = tuple_sets;
3121 break;
3122 case UDP_V4_FLOW:
3123 req->ipv4_udp_en = tuple_sets;
3124 break;
3125 case UDP_V6_FLOW:
3126 req->ipv6_udp_en = tuple_sets;
3127 break;
3128 case SCTP_V4_FLOW:
3129 req->ipv4_sctp_en = tuple_sets;
3130 break;
3131 case SCTP_V6_FLOW:
3132 if ((nfc->data & RXH_L4_B_0_1) ||
3133 (nfc->data & RXH_L4_B_2_3))
3134 return -EINVAL;
3135
3136 req->ipv6_sctp_en = tuple_sets;
3137 break;
3138 case IPV4_FLOW:
3139 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3140 break;
3141 case IPV6_FLOW:
3142 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3143 break;
3144 default:
3145 return -EINVAL;
3146 }
3147
3148 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3149 if (ret)
3150 dev_err(&hdev->pdev->dev,
3151 "Set rss tuple fail, status = %d\n", ret);
3152
3153 return ret;
3154}
3155
07d29954
L		 3156static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3157 struct ethtool_rxnfc *nfc)
3158{
3159 struct hclge_vport *vport = hclge_get_vport(handle);
3160 struct hclge_dev *hdev = vport->back;
3161 struct hclge_rss_input_tuple_cmd *req;
3162 struct hclge_desc desc;
3163 u8 tuple_sets;
3164 int ret;
3165
3166 nfc->data = 0;
3167
3168 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3169 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3170 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3171 if (ret) {
3172 dev_err(&hdev->pdev->dev,
3173 "Read rss tuple fail, status = %d\n", ret);
3174 return ret;
3175 }
3176
3177 switch (nfc->flow_type) {
3178 case TCP_V4_FLOW:
3179 tuple_sets = req->ipv4_tcp_en;
3180 break;
3181 case UDP_V4_FLOW:
3182 tuple_sets = req->ipv4_udp_en;
3183 break;
3184 case TCP_V6_FLOW:
3185 tuple_sets = req->ipv6_tcp_en;
3186 break;
3187 case UDP_V6_FLOW:
3188 tuple_sets = req->ipv6_udp_en;
3189 break;
3190 case SCTP_V4_FLOW:
3191 tuple_sets = req->ipv4_sctp_en;
3192 break;
3193 case SCTP_V6_FLOW:
3194 tuple_sets = req->ipv6_sctp_en;
3195 break;
3196 case IPV4_FLOW:
3197 case IPV6_FLOW:
3198 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3199 break;
3200 default:
3201 return -EINVAL;
3202 }
3203
3204 if (!tuple_sets)
3205 return 0;
3206
3207 if (tuple_sets & HCLGE_D_PORT_BIT)
3208 nfc->data |= RXH_L4_B_2_3;
3209 if (tuple_sets & HCLGE_S_PORT_BIT)
3210 nfc->data |= RXH_L4_B_0_1;
3211 if (tuple_sets & HCLGE_D_IP_BIT)
3212 nfc->data |= RXH_IP_DST;
3213 if (tuple_sets & HCLGE_S_IP_BIT)
3214 nfc->data |= RXH_IP_SRC;
3215
3216 return 0;
3217}
3218
46a3df9f
S		 3219static int hclge_get_tc_size(struct hnae3_handle *handle)
3220{
3221 struct hclge_vport *vport = hclge_get_vport(handle);
3222 struct hclge_dev *hdev = vport->back;
3223
3224 return hdev->rss_size_max;
3225}
3226
77f255c1 3227int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f
S		 3228{
3229 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3230 struct hclge_vport *vport = hdev->vport;
3231 u16 tc_offset[HCLGE_MAX_TC_NUM];
3232 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3233 u16 tc_valid[HCLGE_MAX_TC_NUM];
3234 u16 tc_size[HCLGE_MAX_TC_NUM];
3235 u32 *rss_indir = NULL;
68ece54e 3236 u16 rss_size = 0, roundup_size;
46a3df9f
S		 3237 const u8 *key;
3238 int i, ret, j;
3239
3240 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3241 if (!rss_indir)
3242 return -ENOMEM;
3243
3244 /* Get default RSS key */
3245 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3246
3247 /* Initialize RSS indirect table for each vport */
3248 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3249 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3250 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 3251 i % vport[j].alloc_rss_size;
3252
3253 /* vport 0 is for PF */
3254 if (j != 0)
3255 continue;
3256
3257 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 3258 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3259 }
3260 }
3261 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3262 if (ret)
3263 goto err;
3264
3265 key = rss_key;
3266 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3267 if (ret)
3268 goto err;
3269
3270 ret = hclge_set_rss_input_tuple(hdev);
3271 if (ret)
3272 goto err;
3273
68ece54e
YL		 3274 /* Each TC have the same queue size, and tc_size set to hardware is
3275 * the log2 of roundup power of two of rss_size, the acutal queue
3276 * size is limited by indirection table.
3277 */
3278 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3279 dev_err(&hdev->pdev->dev,
3280 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3281 rss_size);
81359617
CJ		 3282 ret = -EINVAL;
3283 goto err;
68ece54e
YL		 3284 }
3285
3286 roundup_size = roundup_pow_of_two(rss_size);
3287 roundup_size = ilog2(roundup_size);
3288
46a3df9f 3289 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3290 tc_valid[i] = 0;
46a3df9f 3291
68ece54e
YL		 3292 if (!(hdev->hw_tc_map & BIT(i)))
3293 continue;
3294
3295 tc_valid[i] = 1;
3296 tc_size[i] = roundup_size;
3297 tc_offset[i] = rss_size * i;
46a3df9f 3298 }
68ece54e 3299
46a3df9f
S		 3300 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3301
3302err:
3303 kfree(rss_indir);
3304
3305 return ret;
3306}
3307
84e095d6
SM		 3308int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3309 int vector_id, bool en,
3310 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3311{
3312 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3313 struct hnae3_ring_chain_node *node;
3314 struct hclge_desc desc;
84e095d6
SM		 3315 struct hclge_ctrl_vector_chain_cmd *req
3316 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3317 enum hclge_cmd_status status;
3318 enum hclge_opcode_type op;
3319 u16 tqp_type_and_id;
46a3df9f
S		 3320 int i;
3321
84e095d6
SM		 3322 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3323 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3324 req->int_vector_id = vector_id;
3325
3326 i = 0;
3327 for (node = ring_chain; node; node = node->next) {
84e095d6
SM		 3328 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3329 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3330 HCLGE_INT_TYPE_S,
46a3df9f 3331 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
84e095d6
SM		 3332 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3333 HCLGE_TQP_ID_S, node->tqp_index);
3334 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3335 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3336 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
84e095d6 3337 req->vfid = vport->vport_id;
46a3df9f 3338
84e095d6
SM		 3339 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3340 if (status) {
46a3df9f
S		 3341 dev_err(&hdev->pdev->dev,
3342 "Map TQP fail, status is %d.\n",
84e095d6
SM		 3343 status);
3344 return -EIO;
46a3df9f
S		 3345 }
3346 i = 0;
3347
3348 hclge_cmd_setup_basic_desc(&desc,
84e095d6 3349 op,
46a3df9f
S		 3350 false);
3351 req->int_vector_id = vector_id;
3352 }
3353 }
3354
3355 if (i > 0) {
3356 req->int_cause_num = i;
84e095d6
SM		 3357 req->vfid = vport->vport_id;
3358 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3359 if (status) {
46a3df9f 3360 dev_err(&hdev->pdev->dev,
84e095d6
SM		 3361 "Map TQP fail, status is %d.\n", status);
3362 return -EIO;
46a3df9f
S		 3363 }
3364 }
3365
3366 return 0;
3367}
3368
84e095d6
SM		 3369static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3370 int vector,
3371 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3372{
3373 struct hclge_vport *vport = hclge_get_vport(handle);
3374 struct hclge_dev *hdev = vport->back;
3375 int vector_id;
3376
3377 vector_id = hclge_get_vector_index(hdev, vector);
3378 if (vector_id < 0) {
3379 dev_err(&hdev->pdev->dev,
84e095d6 3380 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3381 return vector_id;
3382 }
3383
84e095d6 3384 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3385}
3386
84e095d6
SM		 3387static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3388 int vector,
3389 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3390{
3391 struct hclge_vport *vport = hclge_get_vport(handle);
3392 struct hclge_dev *hdev = vport->back;
84e095d6 3393 int vector_id, ret;
46a3df9f
S		 3394
3395 vector_id = hclge_get_vector_index(hdev, vector);
3396 if (vector_id < 0) {
3397 dev_err(&handle->pdev->dev,
3398 "Get vector index fail. ret =%d\n", vector_id);
3399 return vector_id;
3400 }
3401
84e095d6
SM		 3402 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3403 if (ret) {
3404 dev_err(&handle->pdev->dev,
3405 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3406 vector_id,
3407 ret);
3408 return ret;
46a3df9f
S		 3409 }
3410
84e095d6
SM		 3411 /* Free this MSIX or MSI vector */
3412 hclge_free_vector(hdev, vector_id);
46a3df9f
S		 3413
3414 return 0;
3415}
3416
3417int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3418 struct hclge_promisc_param *param)
3419{
d44f9b63 3420 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3421 struct hclge_desc desc;
3422 int ret;
3423
3424 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3425
d44f9b63 3426 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f
S		 3427 req->vf_id = param->vf_id;
3428 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3429
3430 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3431 if (ret) {
3432 dev_err(&hdev->pdev->dev,
3433 "Set promisc mode fail, status is %d.\n", ret);
3434 return ret;
3435 }
3436 return 0;
3437}
3438
3439void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3440 bool en_mc, bool en_bc, int vport_id)
3441{
3442 if (!param)
3443 return;
3444
3445 memset(param, 0, sizeof(struct hclge_promisc_param));
3446 if (en_uc)
3447 param->enable = HCLGE_PROMISC_EN_UC;
3448 if (en_mc)
3449 param->enable |= HCLGE_PROMISC_EN_MC;
3450 if (en_bc)
3451 param->enable |= HCLGE_PROMISC_EN_BC;
3452 param->vf_id = vport_id;
3453}
3454
3455static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3456{
3457 struct hclge_vport *vport = hclge_get_vport(handle);
3458 struct hclge_dev *hdev = vport->back;
3459 struct hclge_promisc_param param;
3460
3461 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3462 hclge_cmd_set_promisc_mode(hdev, &param);
3463}
3464
3465static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3466{
3467 struct hclge_desc desc;
d44f9b63
YL		 3468 struct hclge_config_mac_mode_cmd *req =
3469 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3470 u32 loop_en = 0;
46a3df9f
S		 3471 int ret;
3472
3473 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3474 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3475 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3476 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3477 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3478 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3479 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3480 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3481 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3482 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3483 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3484 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3485 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3486 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3487 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3488 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3489
3490 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3491 if (ret)
3492 dev_err(&hdev->pdev->dev,
3493 "mac enable fail, ret =%d.\n", ret);
3494}
3495
c39c4d98
YL		 3496static int hclge_set_loopback(struct hnae3_handle *handle,
3497 enum hnae3_loop loop_mode, bool en)
3498{
3499 struct hclge_vport *vport = hclge_get_vport(handle);
3500 struct hclge_config_mac_mode_cmd *req;
3501 struct hclge_dev *hdev = vport->back;
3502 struct hclge_desc desc;
3503 u32 loop_en;
3504 int ret;
3505
3506 switch (loop_mode) {
3507 case HNAE3_MAC_INTER_LOOP_MAC:
3508 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3509 /* 1 Read out the MAC mode config at first */
3510 hclge_cmd_setup_basic_desc(&desc,
3511 HCLGE_OPC_CONFIG_MAC_MODE,
3512 true);
3513 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3514 if (ret) {
3515 dev_err(&hdev->pdev->dev,
3516 "mac loopback get fail, ret =%d.\n",
3517 ret);
3518 return ret;
3519 }
3520
3521 /* 2 Then setup the loopback flag */
3522 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3523 if (en)
3524 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3525 else
3526 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3527
3528 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3529
3530 /* 3 Config mac work mode with loopback flag
3531 * and its original configure parameters
3532 */
3533 hclge_cmd_reuse_desc(&desc, false);
3534 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3535 if (ret)
3536 dev_err(&hdev->pdev->dev,
3537 "mac loopback set fail, ret =%d.\n", ret);
3538 break;
3539 default:
3540 ret = -ENOTSUPP;
3541 dev_err(&hdev->pdev->dev,
3542 "loop_mode %d is not supported\n", loop_mode);
3543 break;
3544 }
3545
3546 return ret;
3547}
3548
46a3df9f
S		 3549static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3550 int stream_id, bool enable)
3551{
3552 struct hclge_desc desc;
d44f9b63
YL		 3553 struct hclge_cfg_com_tqp_queue_cmd *req =
3554 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3555 int ret;
3556
3557 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3558 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3559 req->stream_id = cpu_to_le16(stream_id);
3560 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3561
3562 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3563 if (ret)
3564 dev_err(&hdev->pdev->dev,
3565 "Tqp enable fail, status =%d.\n", ret);
3566 return ret;
3567}
3568
3569static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3570{
3571 struct hclge_vport *vport = hclge_get_vport(handle);
3572 struct hnae3_queue *queue;
3573 struct hclge_tqp *tqp;
3574 int i;
3575
3576 for (i = 0; i < vport->alloc_tqps; i++) {
3577 queue = handle->kinfo.tqp[i];
3578 tqp = container_of(queue, struct hclge_tqp, q);
3579 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3580 }
3581}
3582
3583static int hclge_ae_start(struct hnae3_handle *handle)
3584{
3585 struct hclge_vport *vport = hclge_get_vport(handle);
3586 struct hclge_dev *hdev = vport->back;
3587 int i, queue_id, ret;
3588
3589 for (i = 0; i < vport->alloc_tqps; i++) {
3590 /* todo clear interrupt */
3591 /* ring enable */
3592 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3593 if (queue_id < 0) {
3594 dev_warn(&hdev->pdev->dev,
3595 "Get invalid queue id, ignore it\n");
3596 continue;
3597 }
3598
3599 hclge_tqp_enable(hdev, queue_id, 0, true);
3600 }
3601 /* mac enable */
3602 hclge_cfg_mac_mode(hdev, true);
3603 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3604 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 3605
3606 ret = hclge_mac_start_phy(hdev);
3607 if (ret)
3608 return ret;
3609
3610 /* reset tqp stats */
3611 hclge_reset_tqp_stats(handle);
3612
3613 return 0;
3614}
3615
3616static void hclge_ae_stop(struct hnae3_handle *handle)
3617{
3618 struct hclge_vport *vport = hclge_get_vport(handle);
3619 struct hclge_dev *hdev = vport->back;
3620 int i, queue_id;
3621
3622 for (i = 0; i < vport->alloc_tqps; i++) {
3623 /* Ring disable */
3624 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3625 if (queue_id < 0) {
3626 dev_warn(&hdev->pdev->dev,
3627 "Get invalid queue id, ignore it\n");
3628 continue;
3629 }
3630
3631 hclge_tqp_enable(hdev, queue_id, 0, false);
3632 }
3633 /* Mac disable */
3634 hclge_cfg_mac_mode(hdev, false);
3635
3636 hclge_mac_stop_phy(hdev);
3637
3638 /* reset tqp stats */
3639 hclge_reset_tqp_stats(handle);
3640}
3641
3642static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3643 u16 cmdq_resp, u8 resp_code,
3644 enum hclge_mac_vlan_tbl_opcode op)
3645{
3646 struct hclge_dev *hdev = vport->back;
3647 int return_status = -EIO;
3648
3649 if (cmdq_resp) {
3650 dev_err(&hdev->pdev->dev,
3651 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3652 cmdq_resp);
3653 return -EIO;
3654 }
3655
3656 if (op == HCLGE_MAC_VLAN_ADD) {
3657 if ((!resp_code) || (resp_code == 1)) {
3658 return_status = 0;
3659 } else if (resp_code == 2) {
3660 return_status = -EIO;
3661 dev_err(&hdev->pdev->dev,
3662 "add mac addr failed for uc_overflow.\n");
3663 } else if (resp_code == 3) {
3664 return_status = -EIO;
3665 dev_err(&hdev->pdev->dev,
3666 "add mac addr failed for mc_overflow.\n");
3667 } else {
3668 dev_err(&hdev->pdev->dev,
3669 "add mac addr failed for undefined, code=%d.\n",
3670 resp_code);
3671 }
3672 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3673 if (!resp_code) {
3674 return_status = 0;
3675 } else if (resp_code == 1) {
3676 return_status = -EIO;
3677 dev_dbg(&hdev->pdev->dev,
3678 "remove mac addr failed for miss.\n");
3679 } else {
3680 dev_err(&hdev->pdev->dev,
3681 "remove mac addr failed for undefined, code=%d.\n",
3682 resp_code);
3683 }
3684 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3685 if (!resp_code) {
3686 return_status = 0;
3687 } else if (resp_code == 1) {
3688 return_status = -EIO;
3689 dev_dbg(&hdev->pdev->dev,
3690 "lookup mac addr failed for miss.\n");
3691 } else {
3692 dev_err(&hdev->pdev->dev,
3693 "lookup mac addr failed for undefined, code=%d.\n",
3694 resp_code);
3695 }
3696 } else {
3697 return_status = -EIO;
3698 dev_err(&hdev->pdev->dev,
3699 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3700 op);
3701 }
3702
3703 return return_status;
3704}
3705
3706static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3707{
3708 int word_num;
3709 int bit_num;
3710
3711 if (vfid > 255 || vfid < 0)
3712 return -EIO;
3713
3714 if (vfid >= 0 && vfid <= 191) {
3715 word_num = vfid / 32;
3716 bit_num = vfid % 32;
3717 if (clr)
a90bb9a5 3718 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3719 else
a90bb9a5 3720 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3721 } else {
3722 word_num = (vfid - 192) / 32;
3723 bit_num = vfid % 32;
3724 if (clr)
a90bb9a5 3725 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3726 else
a90bb9a5 3727 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3728 }
3729
3730 return 0;
3731}
3732
3733static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3734{
3735#define HCLGE_DESC_NUMBER 3
3736#define HCLGE_FUNC_NUMBER_PER_DESC 6
3737 int i, j;
3738
3739 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3740 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3741 if (desc[i].data[j])
3742 return false;
3743
3744 return true;
3745}
3746
d44f9b63 3747static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3748 const u8 *addr)
3749{
3750 const unsigned char *mac_addr = addr;
3751 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3752 (mac_addr[0]) | (mac_addr[1] << 8);
3753 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3754
3755 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3756 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3757}
3758
1db9b1bf
YL		 3759static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3760 const u8 *addr)
46a3df9f
S		 3761{
3762 u16 high_val = addr[1] | (addr[0] << 8);
3763 struct hclge_dev *hdev = vport->back;
3764 u32 rsh = 4 - hdev->mta_mac_sel_type;
3765 u16 ret_val = (high_val >> rsh) & 0xfff;
3766
3767 return ret_val;
3768}
3769
3770static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3771 enum hclge_mta_dmac_sel_type mta_mac_sel,
3772 bool enable)
3773{
d44f9b63 3774 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3775 struct hclge_desc desc;
3776 int ret;
3777
d44f9b63 3778 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3779 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3780
3781 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3782 enable);
3783 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3784 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3785
3786 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3787 if (ret) {
3788 dev_err(&hdev->pdev->dev,
3789 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3790 ret);
3791 return ret;
3792 }
3793
3794 return 0;
3795}
3796
3797int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3798 u8 func_id,
3799 bool enable)
3800{
d44f9b63 3801 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3802 struct hclge_desc desc;
3803 int ret;
3804
d44f9b63 3805 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3806 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3807
3808 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3809 enable);
3810 req->function_id = func_id;
3811
3812 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3813 if (ret) {
3814 dev_err(&hdev->pdev->dev,
3815 "Config func_id enable failed for cmd_send, ret =%d.\n",
3816 ret);
3817 return ret;
3818 }
3819
3820 return 0;
3821}
3822
3823static int hclge_set_mta_table_item(struct hclge_vport *vport,
3824 u16 idx,
3825 bool enable)
3826{
3827 struct hclge_dev *hdev = vport->back;
d44f9b63 3828 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3829 struct hclge_desc desc;
a90bb9a5 3830 u16 item_idx = 0;
46a3df9f
S		 3831 int ret;
3832
d44f9b63 3833 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 3834 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3835 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3836
a90bb9a5 3837 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 3838 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3839 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3840
3841 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3842 if (ret) {
3843 dev_err(&hdev->pdev->dev,
3844 "Config mta table item failed for cmd_send, ret =%d.\n",
3845 ret);
3846 return ret;
3847 }
3848
3849 return 0;
3850}
3851
3852static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3853 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3854{
3855 struct hclge_dev *hdev = vport->back;
3856 struct hclge_desc desc;
3857 u8 resp_code;
a90bb9a5 3858 u16 retval;
46a3df9f
S		 3859 int ret;
3860
3861 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3862
d44f9b63 3863 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3864
3865 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3866 if (ret) {
3867 dev_err(&hdev->pdev->dev,
3868 "del mac addr failed for cmd_send, ret =%d.\n",
3869 ret);
3870 return ret;
3871 }
a90bb9a5
YL		 3872 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3873 retval = le16_to_cpu(desc.retval);
46a3df9f 3874
a90bb9a5 3875 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3876 HCLGE_MAC_VLAN_REMOVE);
3877}
3878
3879static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3880 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3881 struct hclge_desc *desc,
3882 bool is_mc)
3883{
3884 struct hclge_dev *hdev = vport->back;
3885 u8 resp_code;
a90bb9a5 3886 u16 retval;
46a3df9f
S		 3887 int ret;
3888
3889 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3890 if (is_mc) {
3891 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3892 memcpy(desc[0].data,
3893 req,
d44f9b63 3894 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3895 hclge_cmd_setup_basic_desc(&desc[1],
3896 HCLGE_OPC_MAC_VLAN_ADD,
3897 true);
3898 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3899 hclge_cmd_setup_basic_desc(&desc[2],
3900 HCLGE_OPC_MAC_VLAN_ADD,
3901 true);
3902 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3903 } else {
3904 memcpy(desc[0].data,
3905 req,
d44f9b63 3906 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3907 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3908 }
3909 if (ret) {
3910 dev_err(&hdev->pdev->dev,
3911 "lookup mac addr failed for cmd_send, ret =%d.\n",
3912 ret);
3913 return ret;
3914 }
a90bb9a5
YL		 3915 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3916 retval = le16_to_cpu(desc[0].retval);
46a3df9f 3917
a90bb9a5 3918 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3919 HCLGE_MAC_VLAN_LKUP);
3920}
3921
3922static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3923 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3924 struct hclge_desc *mc_desc)
3925{
3926 struct hclge_dev *hdev = vport->back;
3927 int cfg_status;
3928 u8 resp_code;
a90bb9a5 3929 u16 retval;
46a3df9f
S		 3930 int ret;
3931
3932 if (!mc_desc) {
3933 struct hclge_desc desc;
3934
3935 hclge_cmd_setup_basic_desc(&desc,
3936 HCLGE_OPC_MAC_VLAN_ADD,
3937 false);
d44f9b63
YL		 3938 memcpy(desc.data, req,
3939 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3940 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 3941 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3942 retval = le16_to_cpu(desc.retval);
3943
3944 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3945 resp_code,
3946 HCLGE_MAC_VLAN_ADD);
3947 } else {
c3b6f755 3948 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 3949 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3950 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 3951 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3952 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 3953 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3954 memcpy(mc_desc[0].data, req,
d44f9b63 3955 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3956 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 3957 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3958 retval = le16_to_cpu(mc_desc[0].retval);
3959
3960 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3961 resp_code,
3962 HCLGE_MAC_VLAN_ADD);
3963 }
3964
3965 if (ret) {
3966 dev_err(&hdev->pdev->dev,
3967 "add mac addr failed for cmd_send, ret =%d.\n",
3968 ret);
3969 return ret;
3970 }
3971
3972 return cfg_status;
3973}
3974
3975static int hclge_add_uc_addr(struct hnae3_handle *handle,
3976 const unsigned char *addr)
3977{
3978 struct hclge_vport *vport = hclge_get_vport(handle);
3979
3980 return hclge_add_uc_addr_common(vport, addr);
3981}
3982
3983int hclge_add_uc_addr_common(struct hclge_vport *vport,
3984 const unsigned char *addr)
3985{
3986 struct hclge_dev *hdev = vport->back;
d44f9b63 3987 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 3988 enum hclge_cmd_status status;
a90bb9a5 3989 u16 egress_port = 0;
46a3df9f
S		 3990
3991 /* mac addr check */
3992 if (is_zero_ether_addr(addr) ||
3993 is_broadcast_ether_addr(addr) ||
3994 is_multicast_ether_addr(addr)) {
3995 dev_err(&hdev->pdev->dev,
3996 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3997 addr,
3998 is_zero_ether_addr(addr),
3999 is_broadcast_ether_addr(addr),
4000 is_multicast_ether_addr(addr));
4001 return -EINVAL;
4002 }
4003
4004 memset(&req, 0, sizeof(req));
4005 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4006 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4007 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4008 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 4009
4010 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4011 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4012 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 4013 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 4014 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 4015 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 4016
4017 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4018
4019 hclge_prepare_mac_addr(&req, addr);
4020
4021 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4022
4023 return status;
4024}
4025
4026static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4027 const unsigned char *addr)
4028{
4029 struct hclge_vport *vport = hclge_get_vport(handle);
4030
4031 return hclge_rm_uc_addr_common(vport, addr);
4032}
4033
4034int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4035 const unsigned char *addr)
4036{
4037 struct hclge_dev *hdev = vport->back;
d44f9b63 4038 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4039 enum hclge_cmd_status status;
4040
4041 /* mac addr check */
4042 if (is_zero_ether_addr(addr) ||
4043 is_broadcast_ether_addr(addr) ||
4044 is_multicast_ether_addr(addr)) {
4045 dev_dbg(&hdev->pdev->dev,
4046 "Remove mac err! invalid mac:%pM.\n",
4047 addr);
4048 return -EINVAL;
4049 }
4050
4051 memset(&req, 0, sizeof(req));
4052 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4053 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4054 hclge_prepare_mac_addr(&req, addr);
4055 status = hclge_remove_mac_vlan_tbl(vport, &req);
4056
4057 return status;
4058}
4059
4060static int hclge_add_mc_addr(struct hnae3_handle *handle,
4061 const unsigned char *addr)
4062{
4063 struct hclge_vport *vport = hclge_get_vport(handle);
4064
4065 return hclge_add_mc_addr_common(vport, addr);
4066}
4067
4068int hclge_add_mc_addr_common(struct hclge_vport *vport,
4069 const unsigned char *addr)
4070{
4071 struct hclge_dev *hdev = vport->back;
d44f9b63 4072 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4073 struct hclge_desc desc[3];
4074 u16 tbl_idx;
4075 int status;
4076
4077 /* mac addr check */
4078 if (!is_multicast_ether_addr(addr)) {
4079 dev_err(&hdev->pdev->dev,
4080 "Add mc mac err! invalid mac:%pM.\n",
4081 addr);
4082 return -EINVAL;
4083 }
4084 memset(&req, 0, sizeof(req));
4085 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4086 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4087 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4088 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4089 hclge_prepare_mac_addr(&req, addr);
4090 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4091 if (!status) {
4092 /* This mac addr exist, update VFID for it */
4093 hclge_update_desc_vfid(desc, vport->vport_id, false);
4094 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4095 } else {
4096 /* This mac addr do not exist, add new entry for it */
4097 memset(desc[0].data, 0, sizeof(desc[0].data));
4098 memset(desc[1].data, 0, sizeof(desc[0].data));
4099 memset(desc[2].data, 0, sizeof(desc[0].data));
4100 hclge_update_desc_vfid(desc, vport->vport_id, false);
4101 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4102 }
4103
4104 /* Set MTA table for this MAC address */
4105 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4106 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4107
4108 return status;
4109}
4110
4111static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4112 const unsigned char *addr)
4113{
4114 struct hclge_vport *vport = hclge_get_vport(handle);
4115
4116 return hclge_rm_mc_addr_common(vport, addr);
4117}
4118
4119int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4120 const unsigned char *addr)
4121{
4122 struct hclge_dev *hdev = vport->back;
d44f9b63 4123 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4124 enum hclge_cmd_status status;
4125 struct hclge_desc desc[3];
4126 u16 tbl_idx;
4127
4128 /* mac addr check */
4129 if (!is_multicast_ether_addr(addr)) {
4130 dev_dbg(&hdev->pdev->dev,
4131 "Remove mc mac err! invalid mac:%pM.\n",
4132 addr);
4133 return -EINVAL;
4134 }
4135
4136 memset(&req, 0, sizeof(req));
4137 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4138 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4139 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4140 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4141 hclge_prepare_mac_addr(&req, addr);
4142 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4143 if (!status) {
4144 /* This mac addr exist, remove this handle's VFID for it */
4145 hclge_update_desc_vfid(desc, vport->vport_id, true);
4146
4147 if (hclge_is_all_function_id_zero(desc))
4148 /* All the vfid is zero, so need to delete this entry */
4149 status = hclge_remove_mac_vlan_tbl(vport, &req);
4150 else
4151 /* Not all the vfid is zero, update the vfid */
4152 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4153
4154 } else {
4155 /* This mac addr do not exist, can't delete it */
4156 dev_err(&hdev->pdev->dev,
d7629e74 4157 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 4158 status);
4159 return -EIO;
4160 }
4161
4162 /* Set MTB table for this MAC address */
4163 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4164 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4165
4166 return status;
4167}
4168
4169static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4170{
4171 struct hclge_vport *vport = hclge_get_vport(handle);
4172 struct hclge_dev *hdev = vport->back;
4173
4174 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4175}
4176
4177static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4178{
4179 const unsigned char *new_addr = (const unsigned char *)p;
4180 struct hclge_vport *vport = hclge_get_vport(handle);
4181 struct hclge_dev *hdev = vport->back;
4182
4183 /* mac addr check */
4184 if (is_zero_ether_addr(new_addr) ||
4185 is_broadcast_ether_addr(new_addr) ||
4186 is_multicast_ether_addr(new_addr)) {
4187 dev_err(&hdev->pdev->dev,
4188 "Change uc mac err! invalid mac:%p.\n",
4189 new_addr);
4190 return -EINVAL;
4191 }
4192
4193 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4194
4195 if (!hclge_add_uc_addr(handle, new_addr)) {
4196 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4197 return 0;
4198 }
4199
4200 return -EIO;
4201}
4202
4203static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4204 bool filter_en)
4205{
d44f9b63 4206 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4207 struct hclge_desc desc;
4208 int ret;
4209
4210 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4211
d44f9b63 4212 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4213 req->vlan_type = vlan_type;
4214 req->vlan_fe = filter_en;
4215
4216 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4217 if (ret) {
4218 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4219 ret);
4220 return ret;
4221 }
4222
4223 return 0;
4224}
4225
4226int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4227 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4228{
4229#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4230 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4231 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4232 struct hclge_desc desc[2];
4233 u8 vf_byte_val;
4234 u8 vf_byte_off;
4235 int ret;
4236
4237 hclge_cmd_setup_basic_desc(&desc[0],
4238 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4239 hclge_cmd_setup_basic_desc(&desc[1],
4240 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4241
4242 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4243
4244 vf_byte_off = vfid / 8;
4245 vf_byte_val = 1 << (vfid % 8);
4246
d44f9b63
YL		 4247 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4248 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4249
a90bb9a5 4250 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4251 req0->vlan_cfg = is_kill;
4252
4253 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4254 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4255 else
4256 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4257
4258 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4259 if (ret) {
4260 dev_err(&hdev->pdev->dev,
4261 "Send vf vlan command fail, ret =%d.\n",
4262 ret);
4263 return ret;
4264 }
4265
4266 if (!is_kill) {
4267 if (!req0->resp_code || req0->resp_code == 1)
4268 return 0;
4269
4270 dev_err(&hdev->pdev->dev,
4271 "Add vf vlan filter fail, ret =%d.\n",
4272 req0->resp_code);
4273 } else {
4274 if (!req0->resp_code)
4275 return 0;
4276
4277 dev_err(&hdev->pdev->dev,
4278 "Kill vf vlan filter fail, ret =%d.\n",
4279 req0->resp_code);
4280 }
4281
4282 return -EIO;
4283}
4284
4285static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4286 __be16 proto, u16 vlan_id,
4287 bool is_kill)
4288{
4289 struct hclge_vport *vport = hclge_get_vport(handle);
4290 struct hclge_dev *hdev = vport->back;
d44f9b63 4291 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4292 struct hclge_desc desc;
4293 u8 vlan_offset_byte_val;
4294 u8 vlan_offset_byte;
4295 u8 vlan_offset_160;
4296 int ret;
4297
4298 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4299
4300 vlan_offset_160 = vlan_id / 160;
4301 vlan_offset_byte = (vlan_id % 160) / 8;
4302 vlan_offset_byte_val = 1 << (vlan_id % 8);
4303
d44f9b63 4304 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4305 req->vlan_offset = vlan_offset_160;
4306 req->vlan_cfg = is_kill;
4307 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4308
4309 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4310 if (ret) {
4311 dev_err(&hdev->pdev->dev,
4312 "port vlan command, send fail, ret =%d.\n",
4313 ret);
4314 return ret;
4315 }
4316
4317 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4318 if (ret) {
4319 dev_err(&hdev->pdev->dev,
4320 "Set pf vlan filter config fail, ret =%d.\n",
4321 ret);
4322 return -EIO;
4323 }
4324
4325 return 0;
4326}
4327
4328static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4329 u16 vlan, u8 qos, __be16 proto)
4330{
4331 struct hclge_vport *vport = hclge_get_vport(handle);
4332 struct hclge_dev *hdev = vport->back;
4333
4334 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4335 return -EINVAL;
4336 if (proto != htons(ETH_P_8021Q))
4337 return -EPROTONOSUPPORT;
4338
4339 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4340}
4341
4342static int hclge_init_vlan_config(struct hclge_dev *hdev)
4343{
4344#define HCLGE_VLAN_TYPE_VF_TABLE 0
4345#define HCLGE_VLAN_TYPE_PORT_TABLE 1
5e43aef8 4346 struct hnae3_handle *handle;
46a3df9f
S		 4347 int ret;
4348
4349 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
4350 true);
4351 if (ret)
4352 return ret;
4353
4354 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
4355 true);
5e43aef8
L		 4356 if (ret)
4357 return ret;
46a3df9f 4358
5e43aef8
L		 4359 handle = &hdev->vport[0].nic;
4360 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4361}
4362
4363static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4364{
4365 struct hclge_vport *vport = hclge_get_vport(handle);
d44f9b63 4366 struct hclge_config_max_frm_size_cmd *req;
46a3df9f
S		 4367 struct hclge_dev *hdev = vport->back;
4368 struct hclge_desc desc;
4369 int ret;
4370
4371 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
4372 return -EINVAL;
4373
4374 hdev->mps = new_mtu;
4375 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4376
d44f9b63 4377 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
46a3df9f
S		 4378 req->max_frm_size = cpu_to_le16(new_mtu);
4379
4380 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4381 if (ret) {
4382 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4383 return ret;
4384 }
4385
4386 return 0;
4387}
4388
4389static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4390 bool enable)
4391{
d44f9b63 4392 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4393 struct hclge_desc desc;
4394 int ret;
4395
4396 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4397
d44f9b63 4398 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4399 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4400 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4401
4402 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4403 if (ret) {
4404 dev_err(&hdev->pdev->dev,
4405 "Send tqp reset cmd error, status =%d\n", ret);
4406 return ret;
4407 }
4408
4409 return 0;
4410}
4411
4412static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4413{
d44f9b63 4414 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4415 struct hclge_desc desc;
4416 int ret;
4417
4418 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4419
d44f9b63 4420 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4421 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4422
4423 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4424 if (ret) {
4425 dev_err(&hdev->pdev->dev,
4426 "Get reset status error, status =%d\n", ret);
4427 return ret;
4428 }
4429
4430 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4431}
4432
84e095d6 4433void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 4434{
4435 struct hclge_vport *vport = hclge_get_vport(handle);
4436 struct hclge_dev *hdev = vport->back;
4437 int reset_try_times = 0;
4438 int reset_status;
4439 int ret;
4440
4441 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4442 if (ret) {
4443 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4444 return;
4445 }
4446
4447 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4448 if (ret) {
4449 dev_warn(&hdev->pdev->dev,
4450 "Send reset tqp cmd fail, ret = %d\n", ret);
4451 return;
4452 }
4453
4454 reset_try_times = 0;
4455 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4456 /* Wait for tqp hw reset */
4457 msleep(20);
4458 reset_status = hclge_get_reset_status(hdev, queue_id);
4459 if (reset_status)
4460 break;
4461 }
4462
4463 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4464 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4465 return;
4466 }
4467
4468 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4469 if (ret) {
4470 dev_warn(&hdev->pdev->dev,
4471 "Deassert the soft reset fail, ret = %d\n", ret);
4472 return;
4473 }
4474}
4475
4476static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4477{
4478 struct hclge_vport *vport = hclge_get_vport(handle);
4479 struct hclge_dev *hdev = vport->back;
4480
4481 return hdev->fw_version;
4482}
4483
4484static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4485 u32 *rx_en, u32 *tx_en)
4486{
4487 struct hclge_vport *vport = hclge_get_vport(handle);
4488 struct hclge_dev *hdev = vport->back;
4489
4490 *auto_neg = hclge_get_autoneg(handle);
4491
4492 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4493 *rx_en = 0;
4494 *tx_en = 0;
4495 return;
4496 }
4497
4498 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4499 *rx_en = 1;
4500 *tx_en = 0;
4501 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4502 *tx_en = 1;
4503 *rx_en = 0;
4504 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4505 *rx_en = 1;
4506 *tx_en = 1;
4507 } else {
4508 *rx_en = 0;
4509 *tx_en = 0;
4510 }
4511}
4512
4513static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4514 u8 *auto_neg, u32 *speed, u8 *duplex)
4515{
4516 struct hclge_vport *vport = hclge_get_vport(handle);
4517 struct hclge_dev *hdev = vport->back;
4518
4519 if (speed)
4520 *speed = hdev->hw.mac.speed;
4521 if (duplex)
4522 *duplex = hdev->hw.mac.duplex;
4523 if (auto_neg)
4524 *auto_neg = hdev->hw.mac.autoneg;
4525}
4526
4527static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4528{
4529 struct hclge_vport *vport = hclge_get_vport(handle);
4530 struct hclge_dev *hdev = vport->back;
4531
4532 if (media_type)
4533 *media_type = hdev->hw.mac.media_type;
4534}
4535
4536static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4537 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4538{
4539 struct hclge_vport *vport = hclge_get_vport(handle);
4540 struct hclge_dev *hdev = vport->back;
4541 struct phy_device *phydev = hdev->hw.mac.phydev;
4542 int mdix_ctrl, mdix, retval, is_resolved;
4543
4544 if (!phydev) {
4545 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4546 *tp_mdix = ETH_TP_MDI_INVALID;
4547 return;
4548 }
4549
4550 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4551
4552 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4553 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4554 HCLGE_PHY_MDIX_CTRL_S);
4555
4556 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4557 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4558 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4559
4560 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4561
4562 switch (mdix_ctrl) {
4563 case 0x0:
4564 *tp_mdix_ctrl = ETH_TP_MDI;
4565 break;
4566 case 0x1:
4567 *tp_mdix_ctrl = ETH_TP_MDI_X;
4568 break;
4569 case 0x3:
4570 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4571 break;
4572 default:
4573 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4574 break;
4575 }
4576
4577 if (!is_resolved)
4578 *tp_mdix = ETH_TP_MDI_INVALID;
4579 else if (mdix)
4580 *tp_mdix = ETH_TP_MDI_X;
4581 else
4582 *tp_mdix = ETH_TP_MDI;
4583}
4584
4585static int hclge_init_client_instance(struct hnae3_client *client,
4586 struct hnae3_ae_dev *ae_dev)
4587{
4588 struct hclge_dev *hdev = ae_dev->priv;
4589 struct hclge_vport *vport;
4590 int i, ret;
4591
4592 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4593 vport = &hdev->vport[i];
4594
4595 switch (client->type) {
4596 case HNAE3_CLIENT_KNIC:
4597
4598 hdev->nic_client = client;
4599 vport->nic.client = client;
4600 ret = client->ops->init_instance(&vport->nic);
4601 if (ret)
4602 goto err;
4603
4604 if (hdev->roce_client &&
e92a0843 4605 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4606 struct hnae3_client *rc = hdev->roce_client;
4607
4608 ret = hclge_init_roce_base_info(vport);
4609 if (ret)
4610 goto err;
4611
4612 ret = rc->ops->init_instance(&vport->roce);
4613 if (ret)
4614 goto err;
4615 }
4616
4617 break;
4618 case HNAE3_CLIENT_UNIC:
4619 hdev->nic_client = client;
4620 vport->nic.client = client;
4621
4622 ret = client->ops->init_instance(&vport->nic);
4623 if (ret)
4624 goto err;
4625
4626 break;
4627 case HNAE3_CLIENT_ROCE:
e92a0843 4628 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4629 hdev->roce_client = client;
4630 vport->roce.client = client;
4631 }
4632
3a46f34d 4633 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 4634 ret = hclge_init_roce_base_info(vport);
4635 if (ret)
4636 goto err;
4637
4638 ret = client->ops->init_instance(&vport->roce);
4639 if (ret)
4640 goto err;
4641 }
4642 }
4643 }
4644
4645 return 0;
4646err:
4647 return ret;
4648}
4649
4650static void hclge_uninit_client_instance(struct hnae3_client *client,
4651 struct hnae3_ae_dev *ae_dev)
4652{
4653 struct hclge_dev *hdev = ae_dev->priv;
4654 struct hclge_vport *vport;
4655 int i;
4656
4657 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4658 vport = &hdev->vport[i];
a17dcf3f 4659 if (hdev->roce_client) {
46a3df9f
S		 4660 hdev->roce_client->ops->uninit_instance(&vport->roce,
4661 0);
a17dcf3f
L		 4662 hdev->roce_client = NULL;
4663 vport->roce.client = NULL;
4664 }
46a3df9f
S		 4665 if (client->type == HNAE3_CLIENT_ROCE)
4666 return;
a17dcf3f 4667 if (client->ops->uninit_instance) {
46a3df9f 4668 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 4669 hdev->nic_client = NULL;
4670 vport->nic.client = NULL;
4671 }
46a3df9f
S		 4672 }
4673}
4674
4675static int hclge_pci_init(struct hclge_dev *hdev)
4676{
4677 struct pci_dev *pdev = hdev->pdev;
4678 struct hclge_hw *hw;
4679 int ret;
4680
4681 ret = pci_enable_device(pdev);
4682 if (ret) {
4683 dev_err(&pdev->dev, "failed to enable PCI device\n");
4684 goto err_no_drvdata;
4685 }
4686
4687 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4688 if (ret) {
4689 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4690 if (ret) {
4691 dev_err(&pdev->dev,
4692 "can't set consistent PCI DMA");
4693 goto err_disable_device;
4694 }
4695 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4696 }
4697
4698 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4699 if (ret) {
4700 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4701 goto err_disable_device;
4702 }
4703
4704 pci_set_master(pdev);
4705 hw = &hdev->hw;
4706 hw->back = hdev;
4707 hw->io_base = pcim_iomap(pdev, 2, 0);
4708 if (!hw->io_base) {
4709 dev_err(&pdev->dev, "Can't map configuration register space\n");
4710 ret = -ENOMEM;
4711 goto err_clr_master;
4712 }
4713
709eb41a
L		 4714 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
4715
46a3df9f
S		 4716 return 0;
4717err_clr_master:
4718 pci_clear_master(pdev);
4719 pci_release_regions(pdev);
4720err_disable_device:
4721 pci_disable_device(pdev);
4722err_no_drvdata:
4723 pci_set_drvdata(pdev, NULL);
4724
4725 return ret;
4726}
4727
4728static void hclge_pci_uninit(struct hclge_dev *hdev)
4729{
4730 struct pci_dev *pdev = hdev->pdev;
4731
887c3820 4732 pci_free_irq_vectors(pdev);
46a3df9f
S		 4733 pci_clear_master(pdev);
4734 pci_release_mem_regions(pdev);
4735 pci_disable_device(pdev);
4736}
4737
4738static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4739{
4740 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 4741 struct hclge_dev *hdev;
4742 int ret;
4743
4744 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4745 if (!hdev) {
4746 ret = -ENOMEM;
4747 goto err_hclge_dev;
4748 }
4749
46a3df9f
S		 4750 hdev->pdev = pdev;
4751 hdev->ae_dev = ae_dev;
4ed340ab 4752 hdev->reset_type = HNAE3_NONE_RESET;
cb1b9f77 4753 hdev->reset_request = 0;
ca1d7669 4754 hdev->reset_pending = 0;
46a3df9f
S		 4755 ae_dev->priv = hdev;
4756
46a3df9f
S		 4757 ret = hclge_pci_init(hdev);
4758 if (ret) {
4759 dev_err(&pdev->dev, "PCI init failed\n");
4760 goto err_pci_init;
4761 }
4762
3efb960f
L		 4763 /* Firmware command queue initialize */
4764 ret = hclge_cmd_queue_init(hdev);
4765 if (ret) {
4766 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
4767 return ret;
4768 }
4769
4770 /* Firmware command initialize */
46a3df9f
S		 4771 ret = hclge_cmd_init(hdev);
4772 if (ret)
4773 goto err_cmd_init;
4774
4775 ret = hclge_get_cap(hdev);
4776 if (ret) {
e00e2197
CIK		 4777 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4778 ret);
46a3df9f
S		 4779 return ret;
4780 }
4781
4782 ret = hclge_configure(hdev);
4783 if (ret) {
4784 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4785 return ret;
4786 }
4787
887c3820 4788 ret = hclge_init_msi(hdev);
46a3df9f 4789 if (ret) {
887c3820 4790 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
46a3df9f
S		 4791 return ret;
4792 }
4793
466b0c00
L		 4794 ret = hclge_misc_irq_init(hdev);
4795 if (ret) {
4796 dev_err(&pdev->dev,
4797 "Misc IRQ(vector0) init error, ret = %d.\n",
4798 ret);
4799 return ret;
4800 }
4801
46a3df9f
S		 4802 ret = hclge_alloc_tqps(hdev);
4803 if (ret) {
4804 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4805 return ret;
4806 }
4807
4808 ret = hclge_alloc_vport(hdev);
4809 if (ret) {
4810 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4811 return ret;
4812 }
4813
7df7dad6
L		 4814 ret = hclge_map_tqp(hdev);
4815 if (ret) {
4816 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4817 return ret;
4818 }
4819
cf9cca2d 4820 ret = hclge_mac_mdio_config(hdev);
4821 if (ret) {
4822 dev_warn(&hdev->pdev->dev,
4823 "mdio config fail ret=%d\n", ret);
4824 return ret;
4825 }
4826
46a3df9f
S		 4827 ret = hclge_mac_init(hdev);
4828 if (ret) {
4829 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4830 return ret;
4831 }
4832 ret = hclge_buffer_alloc(hdev);
4833 if (ret) {
4834 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4835 return ret;
4836 }
4837
4838 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4839 if (ret) {
4840 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4841 return ret;
4842 }
4843
46a3df9f
S		 4844 ret = hclge_init_vlan_config(hdev);
4845 if (ret) {
4846 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4847 return ret;
4848 }
4849
4850 ret = hclge_tm_schd_init(hdev);
4851 if (ret) {
4852 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4853 return ret;
68ece54e
YL		 4854 }
4855
4856 ret = hclge_rss_init_hw(hdev);
4857 if (ret) {
4858 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4859 return ret;
46a3df9f
S		 4860 }
4861
cacde272
YL		 4862 hclge_dcb_ops_set(hdev);
4863
d039ef68 4864 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 4865 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 4866 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
c1a81619 4867 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 4868
466b0c00
L		 4869 /* Enable MISC vector(vector0) */
4870 hclge_enable_vector(&hdev->misc_vector, true);
4871
46a3df9f
S		 4872 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4873 set_bit(HCLGE_STATE_DOWN, &hdev->state);
cb1b9f77
SM		 4874 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
4875 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
c1a81619
SM		 4876 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
4877 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
46a3df9f
S		 4878
4879 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4880 return 0;
4881
4882err_cmd_init:
4883 pci_release_regions(pdev);
4884err_pci_init:
4885 pci_set_drvdata(pdev, NULL);
4886err_hclge_dev:
4887 return ret;
4888}
4889
c6dc5213 4890static void hclge_stats_clear(struct hclge_dev *hdev)
4891{
4892 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
4893}
4894
4ed340ab
L		 4895static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
4896{
4897 struct hclge_dev *hdev = ae_dev->priv;
4898 struct pci_dev *pdev = ae_dev->pdev;
4899 int ret;
4900
4901 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4902
c6dc5213 4903 hclge_stats_clear(hdev);
4904
4ed340ab
L		 4905 ret = hclge_cmd_init(hdev);
4906 if (ret) {
4907 dev_err(&pdev->dev, "Cmd queue init failed\n");
4908 return ret;
4909 }
4910
4911 ret = hclge_get_cap(hdev);
4912 if (ret) {
4913 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4914 ret);
4915 return ret;
4916 }
4917
4918 ret = hclge_configure(hdev);
4919 if (ret) {
4920 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4921 return ret;
4922 }
4923
4924 ret = hclge_map_tqp(hdev);
4925 if (ret) {
4926 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4927 return ret;
4928 }
4929
4930 ret = hclge_mac_init(hdev);
4931 if (ret) {
4932 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4933 return ret;
4934 }
4935
4936 ret = hclge_buffer_alloc(hdev);
4937 if (ret) {
4938 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4939 return ret;
4940 }
4941
4942 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4943 if (ret) {
4944 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4945 return ret;
4946 }
4947
4948 ret = hclge_init_vlan_config(hdev);
4949 if (ret) {
4950 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4951 return ret;
4952 }
4953
4954 ret = hclge_tm_schd_init(hdev);
4955 if (ret) {
4956 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4957 return ret;
4958 }
4959
4960 ret = hclge_rss_init_hw(hdev);
4961 if (ret) {
4962 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4963 return ret;
4964 }
4965
4966 /* Enable MISC vector(vector0) */
4967 hclge_enable_vector(&hdev->misc_vector, true);
4968
4969 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
4970 HCLGE_DRIVER_NAME);
4971
4972 return 0;
4973}
4974
46a3df9f
S		 4975static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4976{
4977 struct hclge_dev *hdev = ae_dev->priv;
4978 struct hclge_mac *mac = &hdev->hw.mac;
4979
4980 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4981
2a32ca13
AB		 4982 if (IS_ENABLED(CONFIG_PCI_IOV))
4983 hclge_disable_sriov(hdev);
46a3df9f 4984
d039ef68 4985 if (hdev->service_timer.function)
46a3df9f
S		 4986 del_timer_sync(&hdev->service_timer);
4987 if (hdev->service_task.func)
4988 cancel_work_sync(&hdev->service_task);
cb1b9f77
SM		 4989 if (hdev->rst_service_task.func)
4990 cancel_work_sync(&hdev->rst_service_task);
c1a81619
SM		 4991 if (hdev->mbx_service_task.func)
4992 cancel_work_sync(&hdev->mbx_service_task);
46a3df9f
S		 4993
4994 if (mac->phydev)
4995 mdiobus_unregister(mac->mdio_bus);
4996
466b0c00
L		 4997 /* Disable MISC vector(vector0) */
4998 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 4999 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 5000 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5001 hclge_pci_uninit(hdev);
5002 ae_dev->priv = NULL;
5003}
5004
5005static const struct hnae3_ae_ops hclge_ops = {
5006 .init_ae_dev = hclge_init_ae_dev,
5007 .uninit_ae_dev = hclge_uninit_ae_dev,
5008 .init_client_instance = hclge_init_client_instance,
5009 .uninit_client_instance = hclge_uninit_client_instance,
84e095d6
SM		 5010 .map_ring_to_vector = hclge_map_ring_to_vector,
5011 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f
S		 5012 .get_vector = hclge_get_vector,
5013 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 5014 .set_loopback = hclge_set_loopback,
46a3df9f
S		 5015 .start = hclge_ae_start,
5016 .stop = hclge_ae_stop,
5017 .get_status = hclge_get_status,
5018 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5019 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5020 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5021 .get_media_type = hclge_get_media_type,
5022 .get_rss_key_size = hclge_get_rss_key_size,
5023 .get_rss_indir_size = hclge_get_rss_indir_size,
5024 .get_rss = hclge_get_rss,
5025 .set_rss = hclge_set_rss,
f7db940a 5026 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 5027 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 5028 .get_tc_size = hclge_get_tc_size,
5029 .get_mac_addr = hclge_get_mac_addr,
5030 .set_mac_addr = hclge_set_mac_addr,
5031 .add_uc_addr = hclge_add_uc_addr,
5032 .rm_uc_addr = hclge_rm_uc_addr,
5033 .add_mc_addr = hclge_add_mc_addr,
5034 .rm_mc_addr = hclge_rm_mc_addr,
5035 .set_autoneg = hclge_set_autoneg,
5036 .get_autoneg = hclge_get_autoneg,
5037 .get_pauseparam = hclge_get_pauseparam,
5038 .set_mtu = hclge_set_mtu,
5039 .reset_queue = hclge_reset_tqp,
5040 .get_stats = hclge_get_stats,
5041 .update_stats = hclge_update_stats,
5042 .get_strings = hclge_get_strings,
5043 .get_sset_count = hclge_get_sset_count,
5044 .get_fw_version = hclge_get_fw_version,
5045 .get_mdix_mode = hclge_get_mdix_mode,
5046 .set_vlan_filter = hclge_set_port_vlan_filter,
5047 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4ed340ab 5048 .reset_event = hclge_reset_event,
46a3df9f
S		 5049};
5050
5051static struct hnae3_ae_algo ae_algo = {
5052 .ops = &hclge_ops,
5053 .name = HCLGE_NAME,
5054 .pdev_id_table = ae_algo_pci_tbl,
5055};
5056
5057static int hclge_init(void)
5058{
5059 pr_info("%s is initializing\n", HCLGE_NAME);
5060
5061 return hnae3_register_ae_algo(&ae_algo);
5062}
5063
5064static void hclge_exit(void)
5065{
5066 hnae3_unregister_ae_algo(&ae_algo);
5067}
5068module_init(hclge_init);
5069module_exit(hclge_exit);
5070
5071MODULE_LICENSE("GPL");
5072MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5073MODULE_DESCRIPTION("HCLGE Driver");
5074MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)