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net: hns3: refactor the debugfs process
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_debugfs.h
CommitLineData
6fc22440 1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Copyright (c) 2018-2019 Hisilicon Limited. */
3
4#ifndef __HCLGE_DEBUGFS_H
5#define __HCLGE_DEBUGFS_H
6
a582b78d
ZL		 7#include <linux/etherdevice.h>
8#include "hclge_cmd.h"
9
7737f1fb 10#define HCLGE_DBG_BUF_LEN 256
11#define HCLGE_DBG_MNG_TBL_MAX 64
12
13#define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0)
14#define HCLGE_DBG_MNG_MAC_MASK_B BIT(1)
15#define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2)
16#define HCLGE_DBG_MNG_E_TYPE_B BIT(11)
17#define HCLGE_DBG_MNG_DROP_B BIT(13)
18#define HCLGE_DBG_MNG_VLAN_TAG 0x0FFF
19#define HCLGE_DBG_MNG_PF_ID 0x0007
20#define HCLGE_DBG_MNG_VF_ID 0x00FF
21
27cf979a 22/* Get DFX BD number offset */
23#define HCLGE_DBG_DFX_BIOS_OFFSET 1
24#define HCLGE_DBG_DFX_SSU_0_OFFSET 2
25#define HCLGE_DBG_DFX_SSU_1_OFFSET 3
26#define HCLGE_DBG_DFX_IGU_OFFSET 4
27#define HCLGE_DBG_DFX_RPU_0_OFFSET 5
28
29#define HCLGE_DBG_DFX_RPU_1_OFFSET 6
30#define HCLGE_DBG_DFX_NCSI_OFFSET 7
31#define HCLGE_DBG_DFX_RTC_OFFSET 8
32#define HCLGE_DBG_DFX_PPP_OFFSET 9
33#define HCLGE_DBG_DFX_RCB_OFFSET 10
34#define HCLGE_DBG_DFX_TQP_OFFSET 11
35
36#define HCLGE_DBG_DFX_SSU_2_OFFSET 12
37
6fc22440 38struct hclge_qos_pri_map_cmd {
39 u8 pri0_tc : 4,
40 pri1_tc : 4;
41 u8 pri2_tc : 4,
42 pri3_tc : 4;
43 u8 pri4_tc : 4,
44 pri5_tc : 4;
45 u8 pri6_tc : 4,
46 pri7_tc : 4;
47 u8 vlan_pri : 4,
48 rev : 4;
49};
50
c0ebebb9 51struct hclge_dbg_bitmap_cmd {
52 union {
53 u8 bitmap;
54 struct {
55 u8 bit0 : 1,
56 bit1 : 1,
57 bit2 : 1,
58 bit3 : 1,
59 bit4 : 1,
60 bit5 : 1,
61 bit6 : 1,
62 bit7 : 1;
63 };
64 };
65};
66
a582b78d
ZL		 67struct hclge_dbg_reg_common_msg {
68 int msg_num;
69 int offset;
70 enum hclge_opcode_type cmd;
71};
72
6f92bfd7 73#define HCLGE_DBG_MAX_DFX_MSG_LEN 60
27cf979a 74struct hclge_dbg_dfx_message {
75 int flag;
6f92bfd7 76 char message[HCLGE_DBG_MAX_DFX_MSG_LEN];
27cf979a 77};
78
a582b78d
ZL		 79#define HCLGE_DBG_MAC_REG_TYPE_LEN 32
80struct hclge_dbg_reg_type_info {
81 const char *reg_type;
e4b91468 82 const struct hclge_dbg_dfx_message *dfx_msg;
a582b78d
ZL		 83 struct hclge_dbg_reg_common_msg reg_msg;
84};
85
5e69ea7e
YM		 86struct hclge_dbg_func {
87 enum hnae3_dbg_cmd cmd;
88 int (*dbg_dump)(struct hclge_dev *hdev, char *buf, int len);
89};
90
e4b91468 91static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = {
27cf979a 92 {false, "Reserved"},
93 {true, "BP_CPU_STATE"},
94 {true, "DFX_MSIX_INFO_NIC_0"},
95 {true, "DFX_MSIX_INFO_NIC_1"},
96 {true, "DFX_MSIX_INFO_NIC_2"},
97 {true, "DFX_MSIX_INFO_NIC_3"},
98
99 {true, "DFX_MSIX_INFO_ROC_0"},
100 {true, "DFX_MSIX_INFO_ROC_1"},
101 {true, "DFX_MSIX_INFO_ROC_2"},
102 {true, "DFX_MSIX_INFO_ROC_3"},
103 {false, "Reserved"},
104 {false, "Reserved"},
105};
106
e4b91468 107static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = {
27cf979a 108 {false, "Reserved"},
109 {true, "SSU_ETS_PORT_STATUS"},
110 {true, "SSU_ETS_TCG_STATUS"},
111 {false, "Reserved"},
112 {false, "Reserved"},
113 {true, "SSU_BP_STATUS_0"},
114
115 {true, "SSU_BP_STATUS_1"},
116 {true, "SSU_BP_STATUS_2"},
117 {true, "SSU_BP_STATUS_3"},
118 {true, "SSU_BP_STATUS_4"},
119 {true, "SSU_BP_STATUS_5"},
120 {true, "SSU_MAC_TX_PFC_IND"},
121
122 {true, "MAC_SSU_RX_PFC_IND"},
123 {true, "BTMP_AGEING_ST_B0"},
124 {true, "BTMP_AGEING_ST_B1"},
125 {true, "BTMP_AGEING_ST_B2"},
126 {false, "Reserved"},
127 {false, "Reserved"},
128
129 {true, "FULL_DROP_NUM"},
130 {true, "PART_DROP_NUM"},
131 {true, "PPP_KEY_DROP_NUM"},
132 {true, "PPP_RLT_DROP_NUM"},
133 {true, "LO_PRI_UNICAST_RLT_DROP_NUM"},
134 {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"},
135
136 {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"},
137 {true, "NCSI_PACKET_CURR_BUFFER_CNT"},
138 {true, "BTMP_AGEING_RLS_CNT_BANK0"},
139 {true, "BTMP_AGEING_RLS_CNT_BANK1"},
140 {true, "BTMP_AGEING_RLS_CNT_BANK2"},
141 {true, "SSU_MB_RD_RLT_DROP_CNT"},
142
143 {true, "SSU_PPP_MAC_KEY_NUM_L"},
144 {true, "SSU_PPP_MAC_KEY_NUM_H"},
145 {true, "SSU_PPP_HOST_KEY_NUM_L"},
146 {true, "SSU_PPP_HOST_KEY_NUM_H"},
147 {true, "PPP_SSU_MAC_RLT_NUM_L"},
148 {true, "PPP_SSU_MAC_RLT_NUM_H"},
149
150 {true, "PPP_SSU_HOST_RLT_NUM_L"},
151 {true, "PPP_SSU_HOST_RLT_NUM_H"},
152 {true, "NCSI_RX_PACKET_IN_CNT_L"},
153 {true, "NCSI_RX_PACKET_IN_CNT_H"},
154 {true, "NCSI_TX_PACKET_OUT_CNT_L"},
155 {true, "NCSI_TX_PACKET_OUT_CNT_H"},
156
157 {true, "SSU_KEY_DROP_NUM"},
158 {true, "MB_UNCOPY_NUM"},
159 {true, "RX_OQ_DROP_PKT_CNT"},
160 {true, "TX_OQ_DROP_PKT_CNT"},
161 {true, "BANK_UNBALANCE_DROP_CNT"},
162 {true, "BANK_UNBALANCE_RX_DROP_CNT"},
163
164 {true, "NIC_L2_ERR_DROP_PKT_CNT"},
165 {true, "ROC_L2_ERR_DROP_PKT_CNT"},
166 {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"},
167 {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"},
168 {true, "RX_OQ_GLB_DROP_PKT_CNT"},
169 {false, "Reserved"},
170
171 {true, "LO_PRI_UNICAST_CUR_CNT"},
172 {true, "HI_PRI_MULTICAST_CUR_CNT"},
173 {true, "LO_PRI_MULTICAST_CUR_CNT"},
174 {false, "Reserved"},
175 {false, "Reserved"},
176 {false, "Reserved"},
177};
178
e4b91468 179static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = {
27cf979a 180 {true, "prt_id"},
181 {true, "PACKET_TC_CURR_BUFFER_CNT_0"},
182 {true, "PACKET_TC_CURR_BUFFER_CNT_1"},
183 {true, "PACKET_TC_CURR_BUFFER_CNT_2"},
184 {true, "PACKET_TC_CURR_BUFFER_CNT_3"},
185 {true, "PACKET_TC_CURR_BUFFER_CNT_4"},
186
187 {true, "PACKET_TC_CURR_BUFFER_CNT_5"},
188 {true, "PACKET_TC_CURR_BUFFER_CNT_6"},
189 {true, "PACKET_TC_CURR_BUFFER_CNT_7"},
190 {true, "PACKET_CURR_BUFFER_CNT"},
191 {false, "Reserved"},
192 {false, "Reserved"},
193
194 {true, "RX_PACKET_IN_CNT_L"},
195 {true, "RX_PACKET_IN_CNT_H"},
196 {true, "RX_PACKET_OUT_CNT_L"},
197 {true, "RX_PACKET_OUT_CNT_H"},
198 {true, "TX_PACKET_IN_CNT_L"},
199 {true, "TX_PACKET_IN_CNT_H"},
200
201 {true, "TX_PACKET_OUT_CNT_L"},
202 {true, "TX_PACKET_OUT_CNT_H"},
203 {true, "ROC_RX_PACKET_IN_CNT_L"},
204 {true, "ROC_RX_PACKET_IN_CNT_H"},
205 {true, "ROC_TX_PACKET_OUT_CNT_L"},
206 {true, "ROC_TX_PACKET_OUT_CNT_H"},
207
208 {true, "RX_PACKET_TC_IN_CNT_0_L"},
209 {true, "RX_PACKET_TC_IN_CNT_0_H"},
210 {true, "RX_PACKET_TC_IN_CNT_1_L"},
211 {true, "RX_PACKET_TC_IN_CNT_1_H"},
212 {true, "RX_PACKET_TC_IN_CNT_2_L"},
213 {true, "RX_PACKET_TC_IN_CNT_2_H"},
214
215 {true, "RX_PACKET_TC_IN_CNT_3_L"},
216 {true, "RX_PACKET_TC_IN_CNT_3_H"},
217 {true, "RX_PACKET_TC_IN_CNT_4_L"},
218 {true, "RX_PACKET_TC_IN_CNT_4_H"},
219 {true, "RX_PACKET_TC_IN_CNT_5_L"},
220 {true, "RX_PACKET_TC_IN_CNT_5_H"},
221
222 {true, "RX_PACKET_TC_IN_CNT_6_L"},
223 {true, "RX_PACKET_TC_IN_CNT_6_H"},
224 {true, "RX_PACKET_TC_IN_CNT_7_L"},
225 {true, "RX_PACKET_TC_IN_CNT_7_H"},
226 {true, "RX_PACKET_TC_OUT_CNT_0_L"},
227 {true, "RX_PACKET_TC_OUT_CNT_0_H"},
228
229 {true, "RX_PACKET_TC_OUT_CNT_1_L"},
230 {true, "RX_PACKET_TC_OUT_CNT_1_H"},
231 {true, "RX_PACKET_TC_OUT_CNT_2_L"},
232 {true, "RX_PACKET_TC_OUT_CNT_2_H"},
233 {true, "RX_PACKET_TC_OUT_CNT_3_L"},
234 {true, "RX_PACKET_TC_OUT_CNT_3_H"},
235
236 {true, "RX_PACKET_TC_OUT_CNT_4_L"},
237 {true, "RX_PACKET_TC_OUT_CNT_4_H"},
238 {true, "RX_PACKET_TC_OUT_CNT_5_L"},
239 {true, "RX_PACKET_TC_OUT_CNT_5_H"},
240 {true, "RX_PACKET_TC_OUT_CNT_6_L"},
241 {true, "RX_PACKET_TC_OUT_CNT_6_H"},
242
243 {true, "RX_PACKET_TC_OUT_CNT_7_L"},
244 {true, "RX_PACKET_TC_OUT_CNT_7_H"},
245 {true, "TX_PACKET_TC_IN_CNT_0_L"},
246 {true, "TX_PACKET_TC_IN_CNT_0_H"},
247 {true, "TX_PACKET_TC_IN_CNT_1_L"},
248 {true, "TX_PACKET_TC_IN_CNT_1_H"},
249
250 {true, "TX_PACKET_TC_IN_CNT_2_L"},
251 {true, "TX_PACKET_TC_IN_CNT_2_H"},
252 {true, "TX_PACKET_TC_IN_CNT_3_L"},
253 {true, "TX_PACKET_TC_IN_CNT_3_H"},
254 {true, "TX_PACKET_TC_IN_CNT_4_L"},
255 {true, "TX_PACKET_TC_IN_CNT_4_H"},
256
257 {true, "TX_PACKET_TC_IN_CNT_5_L"},
258 {true, "TX_PACKET_TC_IN_CNT_5_H"},
259 {true, "TX_PACKET_TC_IN_CNT_6_L"},
260 {true, "TX_PACKET_TC_IN_CNT_6_H"},
261 {true, "TX_PACKET_TC_IN_CNT_7_L"},
262 {true, "TX_PACKET_TC_IN_CNT_7_H"},
263
264 {true, "TX_PACKET_TC_OUT_CNT_0_L"},
265 {true, "TX_PACKET_TC_OUT_CNT_0_H"},
266 {true, "TX_PACKET_TC_OUT_CNT_1_L"},
267 {true, "TX_PACKET_TC_OUT_CNT_1_H"},
268 {true, "TX_PACKET_TC_OUT_CNT_2_L"},
269 {true, "TX_PACKET_TC_OUT_CNT_2_H"},
270
271 {true, "TX_PACKET_TC_OUT_CNT_3_L"},
272 {true, "TX_PACKET_TC_OUT_CNT_3_H"},
273 {true, "TX_PACKET_TC_OUT_CNT_4_L"},
274 {true, "TX_PACKET_TC_OUT_CNT_4_H"},
275 {true, "TX_PACKET_TC_OUT_CNT_5_L"},
276 {true, "TX_PACKET_TC_OUT_CNT_5_H"},
277
278 {true, "TX_PACKET_TC_OUT_CNT_6_L"},
279 {true, "TX_PACKET_TC_OUT_CNT_6_H"},
280 {true, "TX_PACKET_TC_OUT_CNT_7_L"},
281 {true, "TX_PACKET_TC_OUT_CNT_7_H"},
282 {false, "Reserved"},
283 {false, "Reserved"},
284};
285
e4b91468 286static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = {
27cf979a 287 {true, "OQ_INDEX"},
288 {true, "QUEUE_CNT"},
289 {false, "Reserved"},
290 {false, "Reserved"},
291 {false, "Reserved"},
292 {false, "Reserved"},
293};
294
e4b91468 295static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = {
27cf979a 296 {true, "prt_id"},
297 {true, "IGU_RX_ERR_PKT"},
298 {true, "IGU_RX_NO_SOF_PKT"},
299 {true, "EGU_TX_1588_SHORT_PKT"},
300 {true, "EGU_TX_1588_PKT"},
301 {true, "EGU_TX_ERR_PKT"},
302
303 {true, "IGU_RX_OUT_L2_PKT"},
304 {true, "IGU_RX_OUT_L3_PKT"},
305 {true, "IGU_RX_OUT_L4_PKT"},
306 {true, "IGU_RX_IN_L2_PKT"},
307 {true, "IGU_RX_IN_L3_PKT"},
308 {true, "IGU_RX_IN_L4_PKT"},
309
310 {true, "IGU_RX_EL3E_PKT"},
311 {true, "IGU_RX_EL4E_PKT"},
312 {true, "IGU_RX_L3E_PKT"},
313 {true, "IGU_RX_L4E_PKT"},
314 {true, "IGU_RX_ROCEE_PKT"},
315 {true, "IGU_RX_OUT_UDP0_PKT"},
316
317 {true, "IGU_RX_IN_UDP0_PKT"},
318 {false, "Reserved"},
319 {false, "Reserved"},
320 {false, "Reserved"},
321 {false, "Reserved"},
322 {false, "Reserved"},
323
324 {true, "IGU_RX_OVERSIZE_PKT_L"},
325 {true, "IGU_RX_OVERSIZE_PKT_H"},
326 {true, "IGU_RX_UNDERSIZE_PKT_L"},
327 {true, "IGU_RX_UNDERSIZE_PKT_H"},
328 {true, "IGU_RX_OUT_ALL_PKT_L"},
329 {true, "IGU_RX_OUT_ALL_PKT_H"},
330
331 {true, "IGU_TX_OUT_ALL_PKT_L"},
332 {true, "IGU_TX_OUT_ALL_PKT_H"},
333 {true, "IGU_RX_UNI_PKT_L"},
334 {true, "IGU_RX_UNI_PKT_H"},
335 {true, "IGU_RX_MULTI_PKT_L"},
336 {true, "IGU_RX_MULTI_PKT_H"},
337
338 {true, "IGU_RX_BROAD_PKT_L"},
339 {true, "IGU_RX_BROAD_PKT_H"},
340 {true, "EGU_TX_OUT_ALL_PKT_L"},
341 {true, "EGU_TX_OUT_ALL_PKT_H"},
342 {true, "EGU_TX_UNI_PKT_L"},
343 {true, "EGU_TX_UNI_PKT_H"},
344
345 {true, "EGU_TX_MULTI_PKT_L"},
346 {true, "EGU_TX_MULTI_PKT_H"},
347 {true, "EGU_TX_BROAD_PKT_L"},
348 {true, "EGU_TX_BROAD_PKT_H"},
349 {true, "IGU_TX_KEY_NUM_L"},
350 {true, "IGU_TX_KEY_NUM_H"},
351
352 {true, "IGU_RX_NON_TUN_PKT_L"},
353 {true, "IGU_RX_NON_TUN_PKT_H"},
354 {true, "IGU_RX_TUN_PKT_L"},
355 {true, "IGU_RX_TUN_PKT_H"},
356 {false, "Reserved"},
357 {false, "Reserved"},
358};
359
e4b91468 360static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = {
27cf979a 361 {true, "tc_queue_num"},
362 {true, "FSM_DFX_ST0"},
363 {true, "FSM_DFX_ST1"},
364 {true, "RPU_RX_PKT_DROP_CNT"},
365 {true, "BUF_WAIT_TIMEOUT"},
366 {true, "BUF_WAIT_TIMEOUT_QID"},
367};
368
e4b91468 369static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = {
27cf979a 370 {false, "Reserved"},
371 {true, "FIFO_DFX_ST0"},
372 {true, "FIFO_DFX_ST1"},
373 {true, "FIFO_DFX_ST2"},
374 {true, "FIFO_DFX_ST3"},
375 {true, "FIFO_DFX_ST4"},
376
377 {true, "FIFO_DFX_ST5"},
378 {false, "Reserved"},
379 {false, "Reserved"},
380 {false, "Reserved"},
381 {false, "Reserved"},
382 {false, "Reserved"},
383};
384
e4b91468 385static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = {
27cf979a 386 {false, "Reserved"},
387 {true, "NCSI_EGU_TX_FIFO_STS"},
388 {true, "NCSI_PAUSE_STATUS"},
389 {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"},
390 {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"},
391 {true, "NCSI_RX_CTRL_CKS_ERR_CNT"},
392
393 {true, "NCSI_RX_CTRL_PKT_CNT"},
394 {true, "NCSI_RX_PT_DMAC_ERR_CNT"},
395 {true, "NCSI_RX_PT_SMAC_ERR_CNT"},
396 {true, "NCSI_RX_PT_PKT_CNT"},
397 {true, "NCSI_RX_FCS_ERR_CNT"},
398 {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"},
399
400 {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"},
401 {true, "NCSI_TX_CTRL_PKT_CNT"},
402 {true, "NCSI_TX_PT_DMAC_ERR_CNT"},
403 {true, "NCSI_TX_PT_SMAC_ERR_CNT"},
404 {true, "NCSI_TX_PT_PKT_CNT"},
405 {true, "NCSI_TX_PT_PKT_TRUNC_CNT"},
406
407 {true, "NCSI_TX_PT_PKT_ERR_CNT"},
408 {true, "NCSI_TX_CTRL_PKT_ERR_CNT"},
409 {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"},
410 {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"},
411 {false, "Reserved"},
412 {false, "Reserved"},
413
414 {true, "NCSI_MAC_RX_OCTETS_OK"},
415 {true, "NCSI_MAC_RX_OCTETS_BAD"},
416 {true, "NCSI_MAC_RX_UC_PKTS"},
417 {true, "NCSI_MAC_RX_MC_PKTS"},
418 {true, "NCSI_MAC_RX_BC_PKTS"},
419 {true, "NCSI_MAC_RX_PKTS_64OCTETS"},
420
421 {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"},
422 {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"},
423 {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"},
424 {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"},
425 {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"},
426 {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"},
427
428 {true, "NCSI_MAC_RX_FCS_ERRORS"},
429 {true, "NCSI_MAC_RX_LONG_ERRORS"},
430 {true, "NCSI_MAC_RX_JABBER_ERRORS"},
431 {true, "NCSI_MAC_RX_RUNT_ERR_CNT"},
432 {true, "NCSI_MAC_RX_SHORT_ERR_CNT"},
433 {true, "NCSI_MAC_RX_FILT_PKT_CNT"},
434
435 {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"},
436 {true, "NCSI_MAC_TX_OCTETS_OK"},
437 {true, "NCSI_MAC_TX_OCTETS_BAD"},
438 {true, "NCSI_MAC_TX_UC_PKTS"},
439 {true, "NCSI_MAC_TX_MC_PKTS"},
440 {true, "NCSI_MAC_TX_BC_PKTS"},
441
442 {true, "NCSI_MAC_TX_PKTS_64OCTETS"},
443 {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"},
444 {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"},
445 {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"},
446 {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"},
447 {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"},
448
449 {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"},
450 {true, "NCSI_MAC_TX_UNDERRUN"},
451 {true, "NCSI_MAC_TX_CRC_ERROR"},
452 {true, "NCSI_MAC_TX_PAUSE_FRAMES"},
453 {true, "NCSI_MAC_RX_PAD_PKTS"},
454 {true, "NCSI_MAC_RX_PAUSE_FRAMES"},
455};
456
e4b91468 457static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = {
27cf979a 458 {false, "Reserved"},
459 {true, "LGE_IGU_AFIFO_DFX_0"},
460 {true, "LGE_IGU_AFIFO_DFX_1"},
461 {true, "LGE_IGU_AFIFO_DFX_2"},
462 {true, "LGE_IGU_AFIFO_DFX_3"},
463 {true, "LGE_IGU_AFIFO_DFX_4"},
464
465 {true, "LGE_IGU_AFIFO_DFX_5"},
466 {true, "LGE_IGU_AFIFO_DFX_6"},
467 {true, "LGE_IGU_AFIFO_DFX_7"},
468 {true, "LGE_EGU_AFIFO_DFX_0"},
469 {true, "LGE_EGU_AFIFO_DFX_1"},
470 {true, "LGE_EGU_AFIFO_DFX_2"},
471
472 {true, "LGE_EGU_AFIFO_DFX_3"},
473 {true, "LGE_EGU_AFIFO_DFX_4"},
474 {true, "LGE_EGU_AFIFO_DFX_5"},
475 {true, "LGE_EGU_AFIFO_DFX_6"},
476 {true, "LGE_EGU_AFIFO_DFX_7"},
477 {true, "CGE_IGU_AFIFO_DFX_0"},
478
479 {true, "CGE_IGU_AFIFO_DFX_1"},
480 {true, "CGE_EGU_AFIFO_DFX_0"},
481 {true, "CGE_EGU_AFIFO_DFX_1"},
482 {false, "Reserved"},
483 {false, "Reserved"},
484 {false, "Reserved"},
485};
486
e4b91468 487static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = {
27cf979a 488 {false, "Reserved"},
489 {true, "DROP_FROM_PRT_PKT_CNT"},
490 {true, "DROP_FROM_HOST_PKT_CNT"},
491 {true, "DROP_TX_VLAN_PROC_CNT"},
492 {true, "DROP_MNG_CNT"},
493 {true, "DROP_FD_CNT"},
494
495 {true, "DROP_NO_DST_CNT"},
496 {true, "DROP_MC_MBID_FULL_CNT"},
497 {true, "DROP_SC_FILTERED"},
498 {true, "PPP_MC_DROP_PKT_CNT"},
499 {true, "DROP_PT_CNT"},
500 {true, "DROP_MAC_ANTI_SPOOF_CNT"},
501
502 {true, "DROP_IG_VFV_CNT"},
503 {true, "DROP_IG_PRTV_CNT"},
504 {true, "DROP_CNM_PFC_PAUSE_CNT"},
505 {true, "DROP_TORUS_TC_CNT"},
506 {true, "DROP_TORUS_LPBK_CNT"},
507 {true, "PPP_HFS_STS"},
508
509 {true, "PPP_MC_RSLT_STS"},
510 {true, "PPP_P3U_STS"},
511 {true, "PPP_RSLT_DESCR_STS"},
512 {true, "PPP_UMV_STS_0"},
513 {true, "PPP_UMV_STS_1"},
514 {true, "PPP_VFV_STS"},
515
516 {true, "PPP_GRO_KEY_CNT"},
517 {true, "PPP_GRO_INFO_CNT"},
518 {true, "PPP_GRO_DROP_CNT"},
519 {true, "PPP_GRO_OUT_CNT"},
520 {true, "PPP_GRO_KEY_MATCH_DATA_CNT"},
521 {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"},
522
523 {true, "PPP_GRO_INFO_MATCH_CNT"},
524 {true, "PPP_GRO_FREE_ENTRY_CNT"},
525 {true, "PPP_GRO_INNER_DFX_SIGNAL"},
526 {false, "Reserved"},
527 {false, "Reserved"},
528 {false, "Reserved"},
529
530 {true, "GET_RX_PKT_CNT_L"},
531 {true, "GET_RX_PKT_CNT_H"},
532 {true, "GET_TX_PKT_CNT_L"},
533 {true, "GET_TX_PKT_CNT_H"},
534 {true, "SEND_UC_PRT2HOST_PKT_CNT_L"},
535 {true, "SEND_UC_PRT2HOST_PKT_CNT_H"},
536
537 {true, "SEND_UC_PRT2PRT_PKT_CNT_L"},
538 {true, "SEND_UC_PRT2PRT_PKT_CNT_H"},
539 {true, "SEND_UC_HOST2HOST_PKT_CNT_L"},
540 {true, "SEND_UC_HOST2HOST_PKT_CNT_H"},
541 {true, "SEND_UC_HOST2PRT_PKT_CNT_L"},
542 {true, "SEND_UC_HOST2PRT_PKT_CNT_H"},
543
544 {true, "SEND_MC_FROM_PRT_CNT_L"},
545 {true, "SEND_MC_FROM_PRT_CNT_H"},
546 {true, "SEND_MC_FROM_HOST_CNT_L"},
547 {true, "SEND_MC_FROM_HOST_CNT_H"},
548 {true, "SSU_MC_RD_CNT_L"},
549 {true, "SSU_MC_RD_CNT_H"},
550
551 {true, "SSU_MC_DROP_CNT_L"},
552 {true, "SSU_MC_DROP_CNT_H"},
553 {true, "SSU_MC_RD_PKT_CNT_L"},
554 {true, "SSU_MC_RD_PKT_CNT_H"},
555 {true, "PPP_MC_2HOST_PKT_CNT_L"},
556 {true, "PPP_MC_2HOST_PKT_CNT_H"},
557
558 {true, "PPP_MC_2PRT_PKT_CNT_L"},
559 {true, "PPP_MC_2PRT_PKT_CNT_H"},
560 {true, "NTSNOS_PKT_CNT_L"},
561 {true, "NTSNOS_PKT_CNT_H"},
562 {true, "NTUP_PKT_CNT_L"},
563 {true, "NTUP_PKT_CNT_H"},
564
565 {true, "NTLCL_PKT_CNT_L"},
566 {true, "NTLCL_PKT_CNT_H"},
567 {true, "NTTGT_PKT_CNT_L"},
568 {true, "NTTGT_PKT_CNT_H"},
569 {true, "RTNS_PKT_CNT_L"},
570 {true, "RTNS_PKT_CNT_H"},
571
572 {true, "RTLPBK_PKT_CNT_L"},
573 {true, "RTLPBK_PKT_CNT_H"},
574 {true, "NR_PKT_CNT_L"},
575 {true, "NR_PKT_CNT_H"},
576 {true, "RR_PKT_CNT_L"},
577 {true, "RR_PKT_CNT_H"},
578
579 {true, "MNG_TBL_HIT_CNT_L"},
580 {true, "MNG_TBL_HIT_CNT_H"},
581 {true, "FD_TBL_HIT_CNT_L"},
582 {true, "FD_TBL_HIT_CNT_H"},
583 {true, "FD_LKUP_CNT_L"},
584 {true, "FD_LKUP_CNT_H"},
585
586 {true, "BC_HIT_CNT_L"},
587 {true, "BC_HIT_CNT_H"},
588 {true, "UM_TBL_UC_HIT_CNT_L"},
589 {true, "UM_TBL_UC_HIT_CNT_H"},
590 {true, "UM_TBL_MC_HIT_CNT_L"},
591 {true, "UM_TBL_MC_HIT_CNT_H"},
592
593 {true, "UM_TBL_VMDQ1_HIT_CNT_L"},
594 {true, "UM_TBL_VMDQ1_HIT_CNT_H"},
595 {true, "MTA_TBL_HIT_CNT_L"},
596 {true, "MTA_TBL_HIT_CNT_H"},
597 {true, "FWD_BONDING_HIT_CNT_L"},
598 {true, "FWD_BONDING_HIT_CNT_H"},
599
600 {true, "PROMIS_TBL_HIT_CNT_L"},
601 {true, "PROMIS_TBL_HIT_CNT_H"},
602 {true, "GET_TUNL_PKT_CNT_L"},
603 {true, "GET_TUNL_PKT_CNT_H"},
604 {true, "GET_BMC_PKT_CNT_L"},
605 {true, "GET_BMC_PKT_CNT_H"},
606
607 {true, "SEND_UC_PRT2BMC_PKT_CNT_L"},
608 {true, "SEND_UC_PRT2BMC_PKT_CNT_H"},
609 {true, "SEND_UC_HOST2BMC_PKT_CNT_L"},
610 {true, "SEND_UC_HOST2BMC_PKT_CNT_H"},
611 {true, "SEND_UC_BMC2HOST_PKT_CNT_L"},
612 {true, "SEND_UC_BMC2HOST_PKT_CNT_H"},
613
614 {true, "SEND_UC_BMC2PRT_PKT_CNT_L"},
615 {true, "SEND_UC_BMC2PRT_PKT_CNT_H"},
616 {true, "PPP_MC_2BMC_PKT_CNT_L"},
617 {true, "PPP_MC_2BMC_PKT_CNT_H"},
618 {true, "VLAN_MIRR_CNT_L"},
619 {true, "VLAN_MIRR_CNT_H"},
620
621 {true, "IG_MIRR_CNT_L"},
622 {true, "IG_MIRR_CNT_H"},
623 {true, "EG_MIRR_CNT_L"},
624 {true, "EG_MIRR_CNT_H"},
625 {true, "RX_DEFAULT_HOST_HIT_CNT_L"},
626 {true, "RX_DEFAULT_HOST_HIT_CNT_H"},
627
628 {true, "LAN_PAIR_CNT_L"},
629 {true, "LAN_PAIR_CNT_H"},
630 {true, "UM_TBL_MC_HIT_PKT_CNT_L"},
631 {true, "UM_TBL_MC_HIT_PKT_CNT_H"},
632 {true, "MTA_TBL_HIT_PKT_CNT_L"},
633 {true, "MTA_TBL_HIT_PKT_CNT_H"},
634
635 {true, "PROMIS_TBL_HIT_PKT_CNT_L"},
636 {true, "PROMIS_TBL_HIT_PKT_CNT_H"},
637 {false, "Reserved"},
638 {false, "Reserved"},
639 {false, "Reserved"},
640 {false, "Reserved"},
641};
642
e4b91468 643static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = {
27cf979a 644 {false, "Reserved"},
645 {true, "FSM_DFX_ST0"},
646 {true, "FSM_DFX_ST1"},
647 {true, "FSM_DFX_ST2"},
648 {true, "FIFO_DFX_ST0"},
649 {true, "FIFO_DFX_ST1"},
650
651 {true, "FIFO_DFX_ST2"},
652 {true, "FIFO_DFX_ST3"},
653 {true, "FIFO_DFX_ST4"},
654 {true, "FIFO_DFX_ST5"},
655 {true, "FIFO_DFX_ST6"},
656 {true, "FIFO_DFX_ST7"},
657
658 {true, "FIFO_DFX_ST8"},
659 {true, "FIFO_DFX_ST9"},
660 {true, "FIFO_DFX_ST10"},
661 {true, "FIFO_DFX_ST11"},
662 {true, "Q_CREDIT_VLD_0"},
663 {true, "Q_CREDIT_VLD_1"},
664
665 {true, "Q_CREDIT_VLD_2"},
666 {true, "Q_CREDIT_VLD_3"},
667 {true, "Q_CREDIT_VLD_4"},
668 {true, "Q_CREDIT_VLD_5"},
669 {true, "Q_CREDIT_VLD_6"},
670 {true, "Q_CREDIT_VLD_7"},
671
672 {true, "Q_CREDIT_VLD_8"},
673 {true, "Q_CREDIT_VLD_9"},
674 {true, "Q_CREDIT_VLD_10"},
675 {true, "Q_CREDIT_VLD_11"},
676 {true, "Q_CREDIT_VLD_12"},
677 {true, "Q_CREDIT_VLD_13"},
678
679 {true, "Q_CREDIT_VLD_14"},
680 {true, "Q_CREDIT_VLD_15"},
681 {true, "Q_CREDIT_VLD_16"},
682 {true, "Q_CREDIT_VLD_17"},
683 {true, "Q_CREDIT_VLD_18"},
684 {true, "Q_CREDIT_VLD_19"},
685
686 {true, "Q_CREDIT_VLD_20"},
687 {true, "Q_CREDIT_VLD_21"},
688 {true, "Q_CREDIT_VLD_22"},
689 {true, "Q_CREDIT_VLD_23"},
690 {true, "Q_CREDIT_VLD_24"},
691 {true, "Q_CREDIT_VLD_25"},
692
693 {true, "Q_CREDIT_VLD_26"},
694 {true, "Q_CREDIT_VLD_27"},
695 {true, "Q_CREDIT_VLD_28"},
696 {true, "Q_CREDIT_VLD_29"},
697 {true, "Q_CREDIT_VLD_30"},
698 {true, "Q_CREDIT_VLD_31"},
699
700 {true, "GRO_BD_SERR_CNT"},
701 {true, "GRO_CONTEXT_SERR_CNT"},
702 {true, "RX_STASH_CFG_SERR_CNT"},
703 {true, "AXI_RD_FBD_SERR_CNT"},
704 {true, "GRO_BD_MERR_CNT"},
705 {true, "GRO_CONTEXT_MERR_CNT"},
706
707 {true, "RX_STASH_CFG_MERR_CNT"},
708 {true, "AXI_RD_FBD_MERR_CNT"},
709 {false, "Reserved"},
710 {false, "Reserved"},
711 {false, "Reserved"},
712 {false, "Reserved"},
713};
714
e4b91468 715static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = {
27cf979a 716 {true, "q_num"},
717 {true, "RCB_CFG_RX_RING_TAIL"},
718 {true, "RCB_CFG_RX_RING_HEAD"},
719 {true, "RCB_CFG_RX_RING_FBDNUM"},
720 {true, "RCB_CFG_RX_RING_OFFSET"},
721 {true, "RCB_CFG_RX_RING_FBDOFFSET"},
722
723 {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"},
724 {true, "RCB_CFG_TX_RING_TAIL"},
725 {true, "RCB_CFG_TX_RING_HEAD"},
726 {true, "RCB_CFG_TX_RING_FBDNUM"},
727 {true, "RCB_CFG_TX_RING_OFFSET"},
728 {true, "RCB_CFG_TX_RING_EBDNUM"},
729};
730
6fc22440 731#endif
Linux 6.x block layer and io_uring tree(s)