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net: hns3: Add "dcb register" status information query function
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_debugfs.c
CommitLineData
3c666b58 1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (c) 2018-2019 Hisilicon Limited. */
3
4#include <linux/device.h>
5
6fc22440 6#include "hclge_debugfs.h"
3c666b58 7#include "hclge_cmd.h"
8#include "hclge_main.h"
2849d4e7 9#include "hclge_tm.h"
3c666b58 10#include "hnae3.h"
11
27cf979a 12static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset)
13{
14 struct hclge_desc desc[4];
15 int ret;
16
17 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_DFX_BD_NUM, true);
18 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
19 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_DFX_BD_NUM, true);
20 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
21 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_DFX_BD_NUM, true);
22 desc[2].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
23 hclge_cmd_setup_basic_desc(&desc[3], HCLGE_OPC_DFX_BD_NUM, true);
24
25 ret = hclge_cmd_send(&hdev->hw, desc, 4);
26 if (ret != HCLGE_CMD_EXEC_SUCCESS) {
27 dev_err(&hdev->pdev->dev,
28 "get dfx bdnum fail, status is %d.\n", ret);
29 return ret;
30 }
31
32 return (int)desc[offset / 6].data[offset % 6];
33}
34
35static int hclge_dbg_cmd_send(struct hclge_dev *hdev,
36 struct hclge_desc *desc_src,
37 int index, int bd_num,
38 enum hclge_opcode_type cmd)
39{
40 struct hclge_desc *desc = desc_src;
41 int ret, i;
42
43 hclge_cmd_setup_basic_desc(desc, cmd, true);
44 desc->data[0] = cpu_to_le32(index);
45
46 for (i = 1; i < bd_num; i++) {
47 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
48 desc++;
49 hclge_cmd_setup_basic_desc(desc, cmd, true);
50 }
51
52 ret = hclge_cmd_send(&hdev->hw, desc_src, bd_num);
53 if (ret) {
54 dev_err(&hdev->pdev->dev,
55 "read reg cmd send fail, status is %d.\n", ret);
56 return ret;
57 }
58
59 return ret;
60}
61
62static void hclge_dbg_dump_reg_common(struct hclge_dev *hdev,
63 struct hclge_dbg_dfx_message *dfx_message,
64 char *cmd_buf, int msg_num, int offset,
65 enum hclge_opcode_type cmd)
66{
67 struct hclge_desc *desc_src;
68 struct hclge_desc *desc;
69 int bd_num, buf_len;
70 int ret, i;
71 int index;
72 int max;
73
74 ret = kstrtouint(cmd_buf, 10, &index);
75 index = (ret != 0) ? 0 : index;
76
77 bd_num = hclge_dbg_get_dfx_bd_num(hdev, offset);
78 if (bd_num <= 0)
79 return;
80
81 buf_len = sizeof(struct hclge_desc) * bd_num;
82 desc_src = kzalloc(buf_len, GFP_KERNEL);
83 if (!desc_src) {
84 dev_err(&hdev->pdev->dev, "call kzalloc failed\n");
85 return;
86 }
87
88 desc = desc_src;
89 ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num, cmd);
90 if (ret != HCLGE_CMD_EXEC_SUCCESS) {
91 kfree(desc_src);
92 return;
93 }
94
95 max = (bd_num * 6) <= msg_num ? (bd_num * 6) : msg_num;
96
97 desc = desc_src;
98 for (i = 0; i < max; i++) {
99 (((i / 6) > 0) && ((i % 6) == 0)) ? desc++ : desc;
100 if (dfx_message->flag)
101 dev_info(&hdev->pdev->dev, "%s: 0x%x\n",
102 dfx_message->message, desc->data[i % 6]);
103
104 dfx_message++;
105 }
106
107 kfree(desc_src);
108}
109
c0ebebb9 110static void hclge_dbg_dump_dcb(struct hclge_dev *hdev, char *cmd_buf)
111{
112 struct device *dev = &hdev->pdev->dev;
113 struct hclge_dbg_bitmap_cmd *bitmap;
114 int rq_id, pri_id, qset_id;
115 int port_id, nq_id, pg_id;
116 struct hclge_desc desc[2];
117
118 int cnt, ret;
119
120 cnt = sscanf(cmd_buf, "%i %i %i %i %i %i",
121 &port_id, &pri_id, &pg_id, &rq_id, &nq_id, &qset_id);
122 if (cnt != 6) {
123 dev_err(&hdev->pdev->dev,
124 "dump dcb: bad command parameter, cnt=%d\n", cnt);
125 return;
126 }
127
128 ret = hclge_dbg_cmd_send(hdev, desc, qset_id, 1,
129 HCLGE_OPC_QSET_DFX_STS);
130 if (ret)
131 return;
132
133 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
134 dev_info(dev, "roce_qset_mask: 0x%x\n", bitmap->bit0);
135 dev_info(dev, "nic_qs_mask: 0x%x\n", bitmap->bit1);
136 dev_info(dev, "qs_shaping_pass: 0x%x\n", bitmap->bit2);
137 dev_info(dev, "qs_bp_sts: 0x%x\n", bitmap->bit3);
138
139 ret = hclge_dbg_cmd_send(hdev, desc, pri_id, 1, HCLGE_OPC_PRI_DFX_STS);
140 if (ret)
141 return;
142
143 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
144 dev_info(dev, "pri_mask: 0x%x\n", bitmap->bit0);
145 dev_info(dev, "pri_cshaping_pass: 0x%x\n", bitmap->bit1);
146 dev_info(dev, "pri_pshaping_pass: 0x%x\n", bitmap->bit2);
147
148 ret = hclge_dbg_cmd_send(hdev, desc, pg_id, 1, HCLGE_OPC_PG_DFX_STS);
149 if (ret)
150 return;
151
152 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
153 dev_info(dev, "pg_mask: 0x%x\n", bitmap->bit0);
154 dev_info(dev, "pg_cshaping_pass: 0x%x\n", bitmap->bit1);
155 dev_info(dev, "pg_pshaping_pass: 0x%x\n", bitmap->bit2);
156
157 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1,
158 HCLGE_OPC_PORT_DFX_STS);
159 if (ret)
160 return;
161
162 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
163 dev_info(dev, "port_mask: 0x%x\n", bitmap->bit0);
164 dev_info(dev, "port_shaping_pass: 0x%x\n", bitmap->bit1);
165
166 ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, HCLGE_OPC_SCH_NQ_CNT);
167 if (ret)
168 return;
169
170 dev_info(dev, "sch_nq_cnt: 0x%x\n", desc[0].data[1]);
171
172 ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, HCLGE_OPC_SCH_RQ_CNT);
173 if (ret)
174 return;
175
176 dev_info(dev, "sch_rq_cnt: 0x%x\n", desc[0].data[1]);
177
178 ret = hclge_dbg_cmd_send(hdev, desc, 0, 2, HCLGE_OPC_TM_INTERNAL_STS);
179 if (ret)
180 return;
181
182 dev_info(dev, "pri_bp: 0x%x\n", desc[0].data[1]);
183 dev_info(dev, "fifo_dfx_info: 0x%x\n", desc[0].data[2]);
184 dev_info(dev, "sch_roce_fifo_afull_gap: 0x%x\n", desc[0].data[3]);
185 dev_info(dev, "tx_private_waterline: 0x%x\n", desc[0].data[4]);
186 dev_info(dev, "tm_bypass_en: 0x%x\n", desc[0].data[5]);
187 dev_info(dev, "SSU_TM_BYPASS_EN: 0x%x\n", desc[1].data[0]);
188 dev_info(dev, "SSU_RESERVE_CFG: 0x%x\n", desc[1].data[1]);
189
190 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1,
191 HCLGE_OPC_TM_INTERNAL_CNT);
192 if (ret)
193 return;
194
195 dev_info(dev, "SCH_NIC_NUM: 0x%x\n", desc[0].data[1]);
196 dev_info(dev, "SCH_ROCE_NUM: 0x%x\n", desc[0].data[2]);
197
198 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1,
199 HCLGE_OPC_TM_INTERNAL_STS_1);
200 if (ret)
201 return;
202
203 dev_info(dev, "TC_MAP_SEL: 0x%x\n", desc[0].data[1]);
204 dev_info(dev, "IGU_PFC_PRI_EN: 0x%x\n", desc[0].data[2]);
205 dev_info(dev, "MAC_PFC_PRI_EN: 0x%x\n", desc[0].data[3]);
206 dev_info(dev, "IGU_PRI_MAP_TC_CFG: 0x%x\n", desc[0].data[4]);
207 dev_info(dev, "IGU_TX_PRI_MAP_TC_CFG: 0x%x\n", desc[0].data[5]);
208}
209
27cf979a 210static void hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, char *cmd_buf)
211{
212 int msg_num;
213
214 if (strncmp(&cmd_buf[9], "bios common", 11) == 0) {
215 msg_num = sizeof(hclge_dbg_bios_common_reg) /
216 sizeof(struct hclge_dbg_dfx_message);
217 hclge_dbg_dump_reg_common(hdev, hclge_dbg_bios_common_reg,
218 &cmd_buf[21], msg_num,
219 HCLGE_DBG_DFX_BIOS_OFFSET,
220 HCLGE_OPC_DFX_BIOS_COMMON_REG);
221 } else if (strncmp(&cmd_buf[9], "ssu", 3) == 0) {
222 msg_num = sizeof(hclge_dbg_ssu_reg_0) /
223 sizeof(struct hclge_dbg_dfx_message);
224 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_0,
225 &cmd_buf[13], msg_num,
226 HCLGE_DBG_DFX_SSU_0_OFFSET,
227 HCLGE_OPC_DFX_SSU_REG_0);
228
229 msg_num = sizeof(hclge_dbg_ssu_reg_1) /
230 sizeof(struct hclge_dbg_dfx_message);
231 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_1,
232 &cmd_buf[13], msg_num,
233 HCLGE_DBG_DFX_SSU_1_OFFSET,
234 HCLGE_OPC_DFX_SSU_REG_1);
235
236 msg_num = sizeof(hclge_dbg_ssu_reg_2) /
237 sizeof(struct hclge_dbg_dfx_message);
238 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_2,
239 &cmd_buf[13], msg_num,
240 HCLGE_DBG_DFX_SSU_2_OFFSET,
241 HCLGE_OPC_DFX_SSU_REG_2);
242 } else if (strncmp(&cmd_buf[9], "igu egu", 7) == 0) {
243 msg_num = sizeof(hclge_dbg_igu_egu_reg) /
244 sizeof(struct hclge_dbg_dfx_message);
245 hclge_dbg_dump_reg_common(hdev, hclge_dbg_igu_egu_reg,
246 &cmd_buf[17], msg_num,
247 HCLGE_DBG_DFX_IGU_OFFSET,
248 HCLGE_OPC_DFX_IGU_EGU_REG);
249 } else if (strncmp(&cmd_buf[9], "rpu", 3) == 0) {
250 msg_num = sizeof(hclge_dbg_rpu_reg_0) /
251 sizeof(struct hclge_dbg_dfx_message);
252 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rpu_reg_0,
253 &cmd_buf[13], msg_num,
254 HCLGE_DBG_DFX_RPU_0_OFFSET,
255 HCLGE_OPC_DFX_RPU_REG_0);
256
257 msg_num = sizeof(hclge_dbg_rpu_reg_1) /
258 sizeof(struct hclge_dbg_dfx_message);
259 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rpu_reg_1,
260 &cmd_buf[13], msg_num,
261 HCLGE_DBG_DFX_RPU_1_OFFSET,
262 HCLGE_OPC_DFX_RPU_REG_1);
263 } else if (strncmp(&cmd_buf[9], "ncsi", 4) == 0) {
264 msg_num = sizeof(hclge_dbg_ncsi_reg) /
265 sizeof(struct hclge_dbg_dfx_message);
266 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ncsi_reg,
267 &cmd_buf[14], msg_num,
268 HCLGE_DBG_DFX_NCSI_OFFSET,
269 HCLGE_OPC_DFX_NCSI_REG);
270 } else if (strncmp(&cmd_buf[9], "rtc", 3) == 0) {
271 msg_num = sizeof(hclge_dbg_rtc_reg) /
272 sizeof(struct hclge_dbg_dfx_message);
273 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rtc_reg,
274 &cmd_buf[13], msg_num,
275 HCLGE_DBG_DFX_RTC_OFFSET,
276 HCLGE_OPC_DFX_RTC_REG);
277 } else if (strncmp(&cmd_buf[9], "ppp", 3) == 0) {
278 msg_num = sizeof(hclge_dbg_ppp_reg) /
279 sizeof(struct hclge_dbg_dfx_message);
280 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ppp_reg,
281 &cmd_buf[13], msg_num,
282 HCLGE_DBG_DFX_PPP_OFFSET,
283 HCLGE_OPC_DFX_PPP_REG);
284 } else if (strncmp(&cmd_buf[9], "rcb", 3) == 0) {
285 msg_num = sizeof(hclge_dbg_rcb_reg) /
286 sizeof(struct hclge_dbg_dfx_message);
287 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rcb_reg,
288 &cmd_buf[13], msg_num,
289 HCLGE_DBG_DFX_RCB_OFFSET,
290 HCLGE_OPC_DFX_RCB_REG);
291 } else if (strncmp(&cmd_buf[9], "tqp", 3) == 0) {
292 msg_num = sizeof(hclge_dbg_tqp_reg) /
293 sizeof(struct hclge_dbg_dfx_message);
294 hclge_dbg_dump_reg_common(hdev, hclge_dbg_tqp_reg,
295 &cmd_buf[13], msg_num,
296 HCLGE_DBG_DFX_TQP_OFFSET,
297 HCLGE_OPC_DFX_TQP_REG);
c0ebebb9 298 } else if (strncmp(&cmd_buf[9], "dcb", 3) == 0) {
299 hclge_dbg_dump_dcb(hdev, &cmd_buf[13]);
27cf979a 300 } else {
301 dev_info(&hdev->pdev->dev, "unknown command\n");
302 return;
303 }
304}
305
2849d4e7 306static void hclge_title_idx_print(struct hclge_dev *hdev, bool flag, int index,
307 char *title_buf, char *true_buf,
308 char *false_buf)
309{
310 if (flag)
311 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index,
312 true_buf);
313 else
314 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index,
315 false_buf);
316}
317
318static void hclge_dbg_dump_tc(struct hclge_dev *hdev)
319{
320 struct hclge_ets_tc_weight_cmd *ets_weight;
321 struct hclge_desc desc;
322 int i, ret;
323
324 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true);
325
326 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
327 if (ret) {
328 dev_err(&hdev->pdev->dev, "dump tc fail, status is %d.\n", ret);
329 return;
330 }
331
332 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
333
334 dev_info(&hdev->pdev->dev, "dump tc\n");
335 dev_info(&hdev->pdev->dev, "weight_offset: %u\n",
336 ets_weight->weight_offset);
337
338 for (i = 0; i < HNAE3_MAX_TC; i++)
339 hclge_title_idx_print(hdev, ets_weight->tc_weight[i], i,
340 "tc", "no sp mode", "sp mode");
341}
342
96227f4c 343static void hclge_dbg_dump_tm_pg(struct hclge_dev *hdev)
344{
345 struct hclge_port_shapping_cmd *port_shap_cfg_cmd;
346 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
347 struct hclge_pg_shapping_cmd *pg_shap_cfg_cmd;
348 enum hclge_opcode_type cmd;
349 struct hclge_desc desc;
350 int ret;
351
352 cmd = HCLGE_OPC_TM_PG_C_SHAPPING;
353 hclge_cmd_setup_basic_desc(&desc, cmd, true);
354 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
355 if (ret)
356 goto err_tm_pg_cmd_send;
357
358 pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
359 dev_info(&hdev->pdev->dev, "PG_C pg_id: %u\n", pg_shap_cfg_cmd->pg_id);
360 dev_info(&hdev->pdev->dev, "PG_C pg_shapping: 0x%x\n",
361 pg_shap_cfg_cmd->pg_shapping_para);
362
363 cmd = HCLGE_OPC_TM_PG_P_SHAPPING;
364 hclge_cmd_setup_basic_desc(&desc, cmd, true);
365 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
366 if (ret)
367 goto err_tm_pg_cmd_send;
368
369 pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
370 dev_info(&hdev->pdev->dev, "PG_P pg_id: %u\n", pg_shap_cfg_cmd->pg_id);
371 dev_info(&hdev->pdev->dev, "PG_P pg_shapping: 0x%x\n",
372 pg_shap_cfg_cmd->pg_shapping_para);
373
374 cmd = HCLGE_OPC_TM_PORT_SHAPPING;
375 hclge_cmd_setup_basic_desc(&desc, cmd, true);
376 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
377 if (ret)
378 goto err_tm_pg_cmd_send;
379
380 port_shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
381 dev_info(&hdev->pdev->dev, "PORT port_shapping: 0x%x\n",
382 port_shap_cfg_cmd->port_shapping_para);
383
384 cmd = HCLGE_OPC_TM_PG_SCH_MODE_CFG;
385 hclge_cmd_setup_basic_desc(&desc, cmd, true);
386 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
387 if (ret)
388 goto err_tm_pg_cmd_send;
389
390 dev_info(&hdev->pdev->dev, "PG_SCH pg_id: %u\n", desc.data[0]);
391
392 cmd = HCLGE_OPC_TM_PRI_SCH_MODE_CFG;
393 hclge_cmd_setup_basic_desc(&desc, cmd, true);
394 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
395 if (ret)
396 goto err_tm_pg_cmd_send;
397
398 dev_info(&hdev->pdev->dev, "PRI_SCH pg_id: %u\n", desc.data[0]);
399
400 cmd = HCLGE_OPC_TM_QS_SCH_MODE_CFG;
401 hclge_cmd_setup_basic_desc(&desc, cmd, true);
402 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
403 if (ret)
404 goto err_tm_pg_cmd_send;
405
406 dev_info(&hdev->pdev->dev, "QS_SCH pg_id: %u\n", desc.data[0]);
407
408 cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING;
409 hclge_cmd_setup_basic_desc(&desc, cmd, true);
410 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
411 if (ret)
412 goto err_tm_pg_cmd_send;
413
414 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
415 dev_info(&hdev->pdev->dev, "BP_TO_QSET pg_id: %u\n",
416 bp_to_qs_map_cmd->tc_id);
417 dev_info(&hdev->pdev->dev, "BP_TO_QSET pg_shapping: 0x%x\n",
418 bp_to_qs_map_cmd->qs_group_id);
419 dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_bit_map: 0x%x\n",
420 bp_to_qs_map_cmd->qs_bit_map);
421 return;
422
423err_tm_pg_cmd_send:
424 dev_err(&hdev->pdev->dev, "dump tm_pg fail(0x%x), status is %d\n",
425 cmd, ret);
426}
427
428static void hclge_dbg_dump_tm(struct hclge_dev *hdev)
429{
430 struct hclge_priority_weight_cmd *priority_weight;
431 struct hclge_pg_to_pri_link_cmd *pg_to_pri_map;
432 struct hclge_qs_to_pri_link_cmd *qs_to_pri_map;
433 struct hclge_nq_to_qs_link_cmd *nq_to_qs_map;
434 struct hclge_pri_shapping_cmd *shap_cfg_cmd;
435 struct hclge_pg_weight_cmd *pg_weight;
436 struct hclge_qs_weight_cmd *qs_weight;
437 enum hclge_opcode_type cmd;
438 struct hclge_desc desc;
439 int ret;
440
441 cmd = HCLGE_OPC_TM_PG_TO_PRI_LINK;
442 hclge_cmd_setup_basic_desc(&desc, cmd, true);
443 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
444 if (ret)
445 goto err_tm_cmd_send;
446
447 pg_to_pri_map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
448 dev_info(&hdev->pdev->dev, "dump tm\n");
449 dev_info(&hdev->pdev->dev, "PG_TO_PRI gp_id: %u\n",
450 pg_to_pri_map->pg_id);
451 dev_info(&hdev->pdev->dev, "PG_TO_PRI map: 0x%x\n",
452 pg_to_pri_map->pri_bit_map);
453
454 cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK;
455 hclge_cmd_setup_basic_desc(&desc, cmd, true);
456 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
457 if (ret)
458 goto err_tm_cmd_send;
459
460 qs_to_pri_map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
461 dev_info(&hdev->pdev->dev, "QS_TO_PRI qs_id: %u\n",
462 qs_to_pri_map->qs_id);
463 dev_info(&hdev->pdev->dev, "QS_TO_PRI priority: %u\n",
464 qs_to_pri_map->priority);
465 dev_info(&hdev->pdev->dev, "QS_TO_PRI link_vld: %u\n",
466 qs_to_pri_map->link_vld);
467
468 cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK;
469 hclge_cmd_setup_basic_desc(&desc, cmd, true);
470 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
471 if (ret)
472 goto err_tm_cmd_send;
473
474 nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
475 dev_info(&hdev->pdev->dev, "NQ_TO_QS nq_id: %u\n", nq_to_qs_map->nq_id);
476 dev_info(&hdev->pdev->dev, "NQ_TO_QS qset_id: %u\n",
477 nq_to_qs_map->qset_id);
478
479 cmd = HCLGE_OPC_TM_PG_WEIGHT;
480 hclge_cmd_setup_basic_desc(&desc, cmd, true);
481 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
482 if (ret)
483 goto err_tm_cmd_send;
484
485 pg_weight = (struct hclge_pg_weight_cmd *)desc.data;
486 dev_info(&hdev->pdev->dev, "PG pg_id: %u\n", pg_weight->pg_id);
487 dev_info(&hdev->pdev->dev, "PG dwrr: %u\n", pg_weight->dwrr);
488
489 cmd = HCLGE_OPC_TM_QS_WEIGHT;
490 hclge_cmd_setup_basic_desc(&desc, cmd, true);
491 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
492 if (ret)
493 goto err_tm_cmd_send;
494
495 qs_weight = (struct hclge_qs_weight_cmd *)desc.data;
496 dev_info(&hdev->pdev->dev, "QS qs_id: %u\n", qs_weight->qs_id);
497 dev_info(&hdev->pdev->dev, "QS dwrr: %u\n", qs_weight->dwrr);
498
499 cmd = HCLGE_OPC_TM_PRI_WEIGHT;
500 hclge_cmd_setup_basic_desc(&desc, cmd, true);
501 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
502 if (ret)
503 goto err_tm_cmd_send;
504
505 priority_weight = (struct hclge_priority_weight_cmd *)desc.data;
506 dev_info(&hdev->pdev->dev, "PRI pri_id: %u\n", priority_weight->pri_id);
507 dev_info(&hdev->pdev->dev, "PRI dwrr: %u\n", priority_weight->dwrr);
508
509 cmd = HCLGE_OPC_TM_PRI_C_SHAPPING;
510 hclge_cmd_setup_basic_desc(&desc, cmd, true);
511 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
512 if (ret)
513 goto err_tm_cmd_send;
514
515 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
516 dev_info(&hdev->pdev->dev, "PRI_C pri_id: %u\n", shap_cfg_cmd->pri_id);
517 dev_info(&hdev->pdev->dev, "PRI_C pri_shapping: 0x%x\n",
518 shap_cfg_cmd->pri_shapping_para);
519
520 cmd = HCLGE_OPC_TM_PRI_P_SHAPPING;
521 hclge_cmd_setup_basic_desc(&desc, cmd, true);
522 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
523 if (ret)
524 goto err_tm_cmd_send;
525
526 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
527 dev_info(&hdev->pdev->dev, "PRI_P pri_id: %u\n", shap_cfg_cmd->pri_id);
528 dev_info(&hdev->pdev->dev, "PRI_P pri_shapping: 0x%x\n",
529 shap_cfg_cmd->pri_shapping_para);
530
531 hclge_dbg_dump_tm_pg(hdev);
532
533 return;
534
535err_tm_cmd_send:
536 dev_err(&hdev->pdev->dev, "dump tm fail(0x%x), status is %d\n",
537 cmd, ret);
538}
539
d958919d 540static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev)
541{
542 struct hclge_cfg_pause_param_cmd *pause_param;
543 struct hclge_desc desc;
544 int ret;
545
546 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
547
548 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
549 if (ret) {
550 dev_err(&hdev->pdev->dev, "dump checksum fail, status is %d.\n",
551 ret);
552 return;
553 }
554
555 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
556 dev_info(&hdev->pdev->dev, "dump qos pause cfg\n");
557 dev_info(&hdev->pdev->dev, "pause_trans_gap: 0x%x\n",
558 pause_param->pause_trans_gap);
559 dev_info(&hdev->pdev->dev, "pause_trans_time: 0x%x\n",
560 pause_param->pause_trans_time);
561}
562
6fc22440 563static void hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev)
564{
565 struct hclge_qos_pri_map_cmd *pri_map;
566 struct hclge_desc desc;
567 int ret;
568
569 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true);
570
571 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
572 if (ret) {
573 dev_err(&hdev->pdev->dev,
574 "dump qos pri map fail, status is %d.\n", ret);
575 return;
576 }
577
578 pri_map = (struct hclge_qos_pri_map_cmd *)desc.data;
579 dev_info(&hdev->pdev->dev, "dump qos pri map\n");
580 dev_info(&hdev->pdev->dev, "vlan_to_pri: 0x%x\n", pri_map->vlan_pri);
581 dev_info(&hdev->pdev->dev, "pri_0_to_tc: 0x%x\n", pri_map->pri0_tc);
582 dev_info(&hdev->pdev->dev, "pri_1_to_tc: 0x%x\n", pri_map->pri1_tc);
583 dev_info(&hdev->pdev->dev, "pri_2_to_tc: 0x%x\n", pri_map->pri2_tc);
584 dev_info(&hdev->pdev->dev, "pri_3_to_tc: 0x%x\n", pri_map->pri3_tc);
585 dev_info(&hdev->pdev->dev, "pri_4_to_tc: 0x%x\n", pri_map->pri4_tc);
586 dev_info(&hdev->pdev->dev, "pri_5_to_tc: 0x%x\n", pri_map->pri5_tc);
587 dev_info(&hdev->pdev->dev, "pri_6_to_tc: 0x%x\n", pri_map->pri6_tc);
588 dev_info(&hdev->pdev->dev, "pri_7_to_tc: 0x%x\n", pri_map->pri7_tc);
589}
590
7d9d7f88 591static void hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev)
592{
593 struct hclge_tx_buff_alloc_cmd *tx_buf_cmd;
594 struct hclge_rx_priv_buff_cmd *rx_buf_cmd;
595 struct hclge_rx_priv_wl_buf *rx_priv_wl;
596 struct hclge_rx_com_wl *rx_packet_cnt;
597 struct hclge_rx_com_thrd *rx_com_thrd;
598 struct hclge_rx_com_wl *rx_com_wl;
599 enum hclge_opcode_type cmd;
600 struct hclge_desc desc[2];
601 int i, ret;
602
603 cmd = HCLGE_OPC_TX_BUFF_ALLOC;
604 hclge_cmd_setup_basic_desc(desc, cmd, true);
605 ret = hclge_cmd_send(&hdev->hw, desc, 1);
606 if (ret)
607 goto err_qos_cmd_send;
608
609 dev_info(&hdev->pdev->dev, "dump qos buf cfg\n");
610
611 tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc[0].data;
612 for (i = 0; i < HCLGE_TC_NUM; i++)
613 dev_info(&hdev->pdev->dev, "tx_packet_buf_tc_%d: 0x%x\n", i,
614 tx_buf_cmd->tx_pkt_buff[i]);
615
616 cmd = HCLGE_OPC_RX_PRIV_BUFF_ALLOC;
617 hclge_cmd_setup_basic_desc(desc, cmd, true);
618 ret = hclge_cmd_send(&hdev->hw, desc, 1);
619 if (ret)
620 goto err_qos_cmd_send;
621
622 dev_info(&hdev->pdev->dev, "\n");
623 rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc[0].data;
624 for (i = 0; i < HCLGE_TC_NUM; i++)
625 dev_info(&hdev->pdev->dev, "rx_packet_buf_tc_%d: 0x%x\n", i,
626 rx_buf_cmd->buf_num[i]);
627
628 dev_info(&hdev->pdev->dev, "rx_share_buf: 0x%x\n",
629 rx_buf_cmd->shared_buf);
630
631 cmd = HCLGE_OPC_RX_PRIV_WL_ALLOC;
632 hclge_cmd_setup_basic_desc(&desc[0], cmd, true);
633 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
634 hclge_cmd_setup_basic_desc(&desc[1], cmd, true);
635 ret = hclge_cmd_send(&hdev->hw, desc, 2);
636 if (ret)
637 goto err_qos_cmd_send;
638
639 dev_info(&hdev->pdev->dev, "\n");
640 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data;
641 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
642 dev_info(&hdev->pdev->dev,
643 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i,
644 rx_priv_wl->tc_wl[i].high, rx_priv_wl->tc_wl[i].low);
645
646 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data;
647 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
648 dev_info(&hdev->pdev->dev,
649 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i + 4,
650 rx_priv_wl->tc_wl[i].high, rx_priv_wl->tc_wl[i].low);
651
652 cmd = HCLGE_OPC_RX_COM_THRD_ALLOC;
653 hclge_cmd_setup_basic_desc(&desc[0], cmd, true);
654 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
655 hclge_cmd_setup_basic_desc(&desc[1], cmd, true);
656 ret = hclge_cmd_send(&hdev->hw, desc, 2);
657 if (ret)
658 goto err_qos_cmd_send;
659
660 dev_info(&hdev->pdev->dev, "\n");
661 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data;
662 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
663 dev_info(&hdev->pdev->dev,
664 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i,
665 rx_com_thrd->com_thrd[i].high,
666 rx_com_thrd->com_thrd[i].low);
667
668 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data;
669 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
670 dev_info(&hdev->pdev->dev,
671 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i + 4,
672 rx_com_thrd->com_thrd[i].high,
673 rx_com_thrd->com_thrd[i].low);
674
675 cmd = HCLGE_OPC_RX_COM_WL_ALLOC;
676 hclge_cmd_setup_basic_desc(desc, cmd, true);
677 ret = hclge_cmd_send(&hdev->hw, desc, 1);
678 if (ret)
679 goto err_qos_cmd_send;
680
681 rx_com_wl = (struct hclge_rx_com_wl *)desc[0].data;
682 dev_info(&hdev->pdev->dev, "\n");
683 dev_info(&hdev->pdev->dev, "rx_com_wl: high: 0x%x, low: 0x%x\n",
684 rx_com_wl->com_wl.high, rx_com_wl->com_wl.low);
685
686 cmd = HCLGE_OPC_RX_GBL_PKT_CNT;
687 hclge_cmd_setup_basic_desc(desc, cmd, true);
688 ret = hclge_cmd_send(&hdev->hw, desc, 1);
689 if (ret)
690 goto err_qos_cmd_send;
691
692 rx_packet_cnt = (struct hclge_rx_com_wl *)desc[0].data;
693 dev_info(&hdev->pdev->dev,
694 "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n",
695 rx_packet_cnt->com_wl.high, rx_packet_cnt->com_wl.low);
696
697 return;
698
699err_qos_cmd_send:
700 dev_err(&hdev->pdev->dev,
701 "dump qos buf cfg fail(0x%x), status is %d\n", cmd, ret);
702}
703
7737f1fb 704static void hclge_dbg_dump_mng_table(struct hclge_dev *hdev)
705{
706 struct hclge_mac_ethertype_idx_rd_cmd *req0;
707 char printf_buf[HCLGE_DBG_BUF_LEN];
708 struct hclge_desc desc;
709 int ret, i;
710
711 dev_info(&hdev->pdev->dev, "mng tab:\n");
712 memset(printf_buf, 0, HCLGE_DBG_BUF_LEN);
713 strncat(printf_buf,
714 "entry|mac_addr |mask|ether|mask|vlan|mask",
715 HCLGE_DBG_BUF_LEN - 1);
716 strncat(printf_buf + strlen(printf_buf),
717 "|i_map|i_dir|e_type|pf_id|vf_id|q_id|drop\n",
718 HCLGE_DBG_BUF_LEN - strlen(printf_buf) - 1);
719
720 dev_info(&hdev->pdev->dev, "%s", printf_buf);
721
722 for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) {
723 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD,
724 true);
725 req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data;
726 req0->index = cpu_to_le16(i);
727
728 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
729 if (ret) {
730 dev_err(&hdev->pdev->dev,
731 "call hclge_cmd_send fail, ret = %d\n", ret);
732 return;
733 }
734
735 if (!req0->resp_code)
736 continue;
737
738 memset(printf_buf, 0, HCLGE_DBG_BUF_LEN);
739 snprintf(printf_buf, HCLGE_DBG_BUF_LEN,
740 "%02u |%02x:%02x:%02x:%02x:%02x:%02x|",
741 req0->index, req0->mac_add[0], req0->mac_add[1],
742 req0->mac_add[2], req0->mac_add[3], req0->mac_add[4],
743 req0->mac_add[5]);
744
745 snprintf(printf_buf + strlen(printf_buf),
746 HCLGE_DBG_BUF_LEN - strlen(printf_buf),
747 "%x |%04x |%x |%04x|%x |%02x |%02x |",
748 !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B),
749 req0->ethter_type,
750 !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B),
751 req0->vlan_tag & HCLGE_DBG_MNG_VLAN_TAG,
752 !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B),
753 req0->i_port_bitmap, req0->i_port_direction);
754
755 snprintf(printf_buf + strlen(printf_buf),
756 HCLGE_DBG_BUF_LEN - strlen(printf_buf),
757 "%d |%d |%02d |%04d|%x\n",
758 !!(req0->egress_port & HCLGE_DBG_MNG_E_TYPE_B),
759 req0->egress_port & HCLGE_DBG_MNG_PF_ID,
760 (req0->egress_port >> 3) & HCLGE_DBG_MNG_VF_ID,
761 req0->egress_queue,
762 !!(req0->egress_port & HCLGE_DBG_MNG_DROP_B));
763
764 dev_info(&hdev->pdev->dev, "%s", printf_buf);
765 }
766}
767
3c666b58 768static void hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage,
769 bool sel_x, u32 loc)
770{
771 struct hclge_fd_tcam_config_1_cmd *req1;
772 struct hclge_fd_tcam_config_2_cmd *req2;
773 struct hclge_fd_tcam_config_3_cmd *req3;
774 struct hclge_desc desc[3];
775 int ret, i;
776 u32 *req;
777
778 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true);
779 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
780 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true);
781 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
782 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true);
783
784 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
785 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
786 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
787
788 req1->stage = stage;
789 req1->xy_sel = sel_x ? 1 : 0;
790 req1->index = cpu_to_le32(loc);
791
792 ret = hclge_cmd_send(&hdev->hw, desc, 3);
793 if (ret)
794 return;
795
796 dev_info(&hdev->pdev->dev, " read result tcam key %s(%u):\n",
797 sel_x ? "x" : "y", loc);
798
799 req = (u32 *)req1->tcam_data;
800 for (i = 0; i < 2; i++)
801 dev_info(&hdev->pdev->dev, "%08x\n", *req++);
802
803 req = (u32 *)req2->tcam_data;
804 for (i = 0; i < 6; i++)
805 dev_info(&hdev->pdev->dev, "%08x\n", *req++);
806
807 req = (u32 *)req3->tcam_data;
808 for (i = 0; i < 5; i++)
809 dev_info(&hdev->pdev->dev, "%08x\n", *req++);
810}
811
812static void hclge_dbg_fd_tcam(struct hclge_dev *hdev)
813{
814 u32 i;
815
816 for (i = 0; i < hdev->fd_cfg.rule_num[0]; i++) {
817 hclge_dbg_fd_tcam_read(hdev, 0, true, i);
818 hclge_dbg_fd_tcam_read(hdev, 0, false, i);
819 }
820}
821
822int hclge_dbg_run_cmd(struct hnae3_handle *handle, char *cmd_buf)
823{
824 struct hclge_vport *vport = hclge_get_vport(handle);
825 struct hclge_dev *hdev = vport->back;
826
827 if (strncmp(cmd_buf, "dump fd tcam", 12) == 0) {
828 hclge_dbg_fd_tcam(hdev);
2849d4e7 829 } else if (strncmp(cmd_buf, "dump tc", 7) == 0) {
830 hclge_dbg_dump_tc(hdev);
96227f4c 831 } else if (strncmp(cmd_buf, "dump tm", 7) == 0) {
832 hclge_dbg_dump_tm(hdev);
d958919d 833 } else if (strncmp(cmd_buf, "dump qos pause cfg", 18) == 0) {
834 hclge_dbg_dump_qos_pause_cfg(hdev);
6fc22440 835 } else if (strncmp(cmd_buf, "dump qos pri map", 16) == 0) {
836 hclge_dbg_dump_qos_pri_map(hdev);
7d9d7f88 837 } else if (strncmp(cmd_buf, "dump qos buf cfg", 16) == 0) {
838 hclge_dbg_dump_qos_buf_cfg(hdev);
7737f1fb 839 } else if (strncmp(cmd_buf, "dump mng tbl", 12) == 0) {
840 hclge_dbg_dump_mng_table(hdev);
27cf979a 841 } else if (strncmp(cmd_buf, "dump reg", 8) == 0) {
842 hclge_dbg_dump_reg_cmd(hdev, cmd_buf);
3c666b58 843 } else {
844 dev_info(&hdev->pdev->dev, "unknown command\n");
845 return -EINVAL;
846 }
847
848 return 0;
849}
Linux 6.x block layer and io_uring tree(s)