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d71d8381 JS |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // Copyright (c) 2016-2017 Hisilicon Limited. | |
68c0a5c7 S |
3 | |
4 | #ifndef __HCLGE_CMD_H | |
5 | #define __HCLGE_CMD_H | |
6 | #include <linux/types.h> | |
7 | #include <linux/io.h> | |
8 | ||
d458c815 | 9 | #define HCLGE_CMDQ_TX_TIMEOUT 30000 |
68c0a5c7 S |
10 | |
11 | struct hclge_dev; | |
12 | struct hclge_desc { | |
13 | __le16 opcode; | |
14 | ||
15 | #define HCLGE_CMDQ_RX_INVLD_B 0 | |
16 | #define HCLGE_CMDQ_RX_OUTVLD_B 1 | |
17 | ||
18 | __le16 flag; | |
19 | __le16 retval; | |
20 | __le16 rsv; | |
21 | __le32 data[6]; | |
22 | }; | |
23 | ||
68c0a5c7 S |
24 | struct hclge_cmq_ring { |
25 | dma_addr_t desc_dma_addr; | |
26 | struct hclge_desc *desc; | |
a10829c4 | 27 | struct hclge_dev *dev; |
68c0a5c7 S |
28 | u32 head; |
29 | u32 tail; | |
30 | ||
31 | u16 buf_size; | |
32 | u16 desc_num; | |
33 | int next_to_use; | |
34 | int next_to_clean; | |
ef0c5009 | 35 | u8 ring_type; /* cmq ring type */ |
68c0a5c7 S |
36 | spinlock_t lock; /* Command queue lock */ |
37 | }; | |
38 | ||
39 | enum hclge_cmd_return_status { | |
40 | HCLGE_CMD_EXEC_SUCCESS = 0, | |
41 | HCLGE_CMD_NO_AUTH = 1, | |
4a402f47 | 42 | HCLGE_CMD_NOT_SUPPORTED = 2, |
68c0a5c7 S |
43 | HCLGE_CMD_QUEUE_FULL = 3, |
44 | }; | |
45 | ||
46 | enum hclge_cmd_status { | |
47 | HCLGE_STATUS_SUCCESS = 0, | |
48 | HCLGE_ERR_CSQ_FULL = -1, | |
49 | HCLGE_ERR_CSQ_TIMEOUT = -2, | |
50 | HCLGE_ERR_CSQ_ERROR = -3, | |
51 | }; | |
52 | ||
466b0c00 L |
53 | struct hclge_misc_vector { |
54 | u8 __iomem *addr; | |
55 | int vector_irq; | |
56 | }; | |
57 | ||
68c0a5c7 S |
58 | struct hclge_cmq { |
59 | struct hclge_cmq_ring csq; | |
60 | struct hclge_cmq_ring crq; | |
fdace1bc | 61 | u16 tx_timeout; |
68c0a5c7 S |
62 | enum hclge_cmd_status last_status; |
63 | }; | |
64 | ||
c79301d8 JS |
65 | #define HCLGE_CMD_FLAG_IN BIT(0) |
66 | #define HCLGE_CMD_FLAG_OUT BIT(1) | |
67 | #define HCLGE_CMD_FLAG_NEXT BIT(2) | |
68 | #define HCLGE_CMD_FLAG_WR BIT(3) | |
69 | #define HCLGE_CMD_FLAG_NO_INTR BIT(4) | |
70 | #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) | |
68c0a5c7 S |
71 | |
72 | enum hclge_opcode_type { | |
fdace1bc | 73 | /* Generic commands */ |
68c0a5c7 S |
74 | HCLGE_OPC_QUERY_FW_VER = 0x0001, |
75 | HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, | |
76 | HCLGE_OPC_GBL_RST_STATUS = 0x0021, | |
77 | HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, | |
78 | HCLGE_OPC_QUERY_PF_RSRC = 0x0023, | |
79 | HCLGE_OPC_QUERY_VF_RSRC = 0x0024, | |
80 | HCLGE_OPC_GET_CFG_PARAM = 0x0025, | |
81 | ||
82 | HCLGE_OPC_STATS_64_BIT = 0x0030, | |
83 | HCLGE_OPC_STATS_32_BIT = 0x0031, | |
84 | HCLGE_OPC_STATS_MAC = 0x0032, | |
d174ea75 | 85 | HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, |
86 | HCLGE_OPC_STATS_MAC_ALL = 0x0034, | |
77b34110 FL |
87 | |
88 | HCLGE_OPC_QUERY_REG_NUM = 0x0040, | |
89 | HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, | |
90 | HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, | |
27cf979a | 91 | HCLGE_OPC_DFX_BD_NUM = 0x0043, |
92 | HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, | |
93 | HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, | |
94 | HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, | |
95 | HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, | |
96 | HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, | |
97 | HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, | |
98 | HCLGE_OPC_DFX_NCSI_REG = 0x004A, | |
99 | HCLGE_OPC_DFX_RTC_REG = 0x004B, | |
100 | HCLGE_OPC_DFX_PPP_REG = 0x004C, | |
101 | HCLGE_OPC_DFX_RCB_REG = 0x004D, | |
102 | HCLGE_OPC_DFX_TQP_REG = 0x004E, | |
103 | HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, | |
104 | HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050, | |
68c0a5c7 | 105 | |
fdace1bc | 106 | /* MAC command */ |
68c0a5c7 S |
107 | HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, |
108 | HCLGE_OPC_CONFIG_AN_MODE = 0x0304, | |
68c0a5c7 S |
109 | HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, |
110 | HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, | |
111 | HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, | |
a6345787 WL |
112 | HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, |
113 | HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, | |
114 | HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, | |
5fd50ac3 | 115 | HCLGE_OPC_SERDES_LOOPBACK = 0x0315, |
7e6ec914 | 116 | HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, |
68c0a5c7 | 117 | |
fdace1bc | 118 | /* PFC/Pause commands */ |
68c0a5c7 S |
119 | HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, |
120 | HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, | |
121 | HCLGE_OPC_CFG_MAC_PARA = 0x0703, | |
122 | HCLGE_OPC_CFG_PFC_PARA = 0x0704, | |
123 | HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, | |
124 | HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, | |
125 | HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, | |
126 | HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, | |
127 | HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, | |
128 | HCLGE_OPC_QOS_MAP = 0x070A, | |
129 | ||
130 | /* ETS/scheduler commands */ | |
131 | HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, | |
132 | HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, | |
133 | HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, | |
134 | HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, | |
135 | HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, | |
136 | HCLGE_OPC_TM_PG_WEIGHT = 0x0809, | |
137 | HCLGE_OPC_TM_QS_WEIGHT = 0x080A, | |
138 | HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, | |
139 | HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, | |
140 | HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, | |
141 | HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, | |
142 | HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, | |
143 | HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, | |
144 | HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, | |
145 | HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, | |
146 | HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, | |
147 | HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, | |
2849d4e7 | 148 | HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, |
c0ebebb9 | 149 | HCLGE_OPC_QSET_DFX_STS = 0x0844, |
150 | HCLGE_OPC_PRI_DFX_STS = 0x0845, | |
151 | HCLGE_OPC_PG_DFX_STS = 0x0846, | |
152 | HCLGE_OPC_PORT_DFX_STS = 0x0847, | |
153 | HCLGE_OPC_SCH_NQ_CNT = 0x0848, | |
154 | HCLGE_OPC_SCH_RQ_CNT = 0x0849, | |
155 | HCLGE_OPC_TM_INTERNAL_STS = 0x0850, | |
156 | HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, | |
157 | HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, | |
68c0a5c7 | 158 | |
fdace1bc | 159 | /* Packet buffer allocate commands */ |
68c0a5c7 S |
160 | HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, |
161 | HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, | |
162 | HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, | |
163 | HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, | |
164 | HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, | |
165 | HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, | |
166 | ||
68c0a5c7 S |
167 | /* TQP management command */ |
168 | HCLGE_OPC_SET_TQP_MAP = 0x0A01, | |
169 | ||
fdace1bc | 170 | /* TQP commands */ |
68c0a5c7 S |
171 | HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, |
172 | HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, | |
173 | HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, | |
82e00b86 | 174 | HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, |
68c0a5c7 S |
175 | HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, |
176 | HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, | |
177 | HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, | |
178 | HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, | |
179 | HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, | |
180 | HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, | |
181 | HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, | |
182 | ||
fdace1bc | 183 | /* TSO command */ |
68c0a5c7 | 184 | HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, |
b26a6fea | 185 | HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, |
68c0a5c7 | 186 | |
fdace1bc | 187 | /* RSS commands */ |
68c0a5c7 S |
188 | HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, |
189 | HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, | |
190 | HCLGE_OPC_RSS_TC_MODE = 0x0D08, | |
191 | HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, | |
192 | ||
193 | /* Promisuous mode command */ | |
194 | HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, | |
195 | ||
fdace1bc | 196 | /* Vlan offload commands */ |
5f6ea83f PL |
197 | HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, |
198 | HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, | |
199 | ||
fdace1bc | 200 | /* Interrupts commands */ |
68c0a5c7 S |
201 | HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, |
202 | HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, | |
203 | ||
fdace1bc | 204 | /* MAC commands */ |
68c0a5c7 S |
205 | HCLGE_OPC_MAC_VLAN_ADD = 0x1000, |
206 | HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, | |
207 | HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, | |
208 | HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, | |
39932473 | 209 | HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, |
68c0a5c7 S |
210 | HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, |
211 | HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, | |
212 | ||
fdace1bc | 213 | /* VLAN commands */ |
68c0a5c7 S |
214 | HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, |
215 | HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, | |
216 | HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, | |
217 | ||
d695964d JS |
218 | /* Flow Director commands */ |
219 | HCLGE_OPC_FD_MODE_CTRL = 0x1200, | |
220 | HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, | |
221 | HCLGE_OPC_FD_KEY_CONFIG = 0x1202, | |
11732868 JS |
222 | HCLGE_OPC_FD_TCAM_OP = 0x1203, |
223 | HCLGE_OPC_FD_AD_OP = 0x1204, | |
d695964d | 224 | |
68c0a5c7 S |
225 | /* MDIO command */ |
226 | HCLGE_OPC_MDIO_CONFIG = 0x1900, | |
227 | ||
fdace1bc | 228 | /* QCN commands */ |
68c0a5c7 S |
229 | HCLGE_OPC_QCN_MOD_CFG = 0x1A01, |
230 | HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, | |
231 | HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, | |
232 | HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, | |
233 | HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, | |
234 | HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, | |
235 | HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, | |
236 | HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, | |
237 | ||
fdace1bc | 238 | /* Mailbox command */ |
68c0a5c7 | 239 | HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, |
07f8e940 JS |
240 | |
241 | /* Led command */ | |
242 | HCLGE_OPC_LED_STATUS_CFG = 0xB000, | |
6d67ee9a | 243 | |
ffd140e2 WL |
244 | /* NCL config command */ |
245 | HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, | |
246 | ||
5d497936 | 247 | /* SFP command */ |
88d10bd6 | 248 | HCLGE_OPC_GET_SFP_INFO = 0x7104, |
5d497936 | 249 | |
6d67ee9a | 250 | /* Error INT commands */ |
7838f908 | 251 | HCLGE_MAC_COMMON_INT_EN = 0x030E, |
01865a50 | 252 | HCLGE_TM_SCH_ECC_INT_EN = 0x0829, |
c3529177 SJ |
253 | HCLGE_SSU_ECC_INT_CMD = 0x0989, |
254 | HCLGE_SSU_COMMON_INT_CMD = 0x098C, | |
f69b10b3 SJ |
255 | HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, |
256 | HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, | |
257 | HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, | |
6d67ee9a | 258 | HCLGE_COMMON_ECC_INT_CFG = 0x1505, |
332fbf57 SJ |
259 | HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, |
260 | HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, | |
261 | HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, | |
f6162d44 SM |
262 | HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, |
263 | HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, | |
264 | HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, | |
630ba007 SJ |
265 | HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, |
266 | HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, | |
267 | HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, | |
bf1faf94 | 268 | HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, |
bf1faf94 | 269 | HCLGE_IGU_COMMON_INT_EN = 0x1806, |
01865a50 | 270 | HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, |
da2d072a SJ |
271 | HCLGE_PPP_CMD0_INT_CMD = 0x2100, |
272 | HCLGE_PPP_CMD1_INT_CMD = 0x2101, | |
7737f1fb | 273 | HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, |
bf1faf94 | 274 | HCLGE_NCSI_INT_EN = 0x2401, |
68c0a5c7 S |
275 | }; |
276 | ||
277 | #define HCLGE_TQP_REG_OFFSET 0x80000 | |
278 | #define HCLGE_TQP_REG_SIZE 0x200 | |
279 | ||
280 | #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 | |
281 | #define HCLGE_RCB_INIT_FLAG_EN_B 0 | |
282 | #define HCLGE_RCB_INIT_FLAG_FINI_B 8 | |
d44f9b63 | 283 | struct hclge_config_rcb_init_cmd { |
68c0a5c7 S |
284 | __le16 rcb_init_flag; |
285 | u8 rsv[22]; | |
286 | }; | |
287 | ||
d44f9b63 | 288 | struct hclge_tqp_map_cmd { |
68c0a5c7 S |
289 | __le16 tqp_id; /* Absolute tqp id for in this pf */ |
290 | u8 tqp_vf; /* VF id */ | |
291 | #define HCLGE_TQP_MAP_TYPE_PF 0 | |
292 | #define HCLGE_TQP_MAP_TYPE_VF 1 | |
293 | #define HCLGE_TQP_MAP_TYPE_B 0 | |
294 | #define HCLGE_TQP_MAP_EN_B 1 | |
295 | u8 tqp_flag; /* Indicate it's pf or vf tqp */ | |
296 | __le16 tqp_vid; /* Virtual id in this pf/vf */ | |
297 | u8 rsv[18]; | |
298 | }; | |
299 | ||
0305b443 | 300 | #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 |
68c0a5c7 S |
301 | |
302 | enum hclge_int_type { | |
303 | HCLGE_INT_TX, | |
304 | HCLGE_INT_RX, | |
305 | HCLGE_INT_EVENT, | |
306 | }; | |
307 | ||
d44f9b63 | 308 | struct hclge_ctrl_vector_chain_cmd { |
68c0a5c7 S |
309 | u8 int_vector_id; |
310 | u8 int_cause_num; | |
311 | #define HCLGE_INT_TYPE_S 0 | |
5392902d | 312 | #define HCLGE_INT_TYPE_M GENMASK(1, 0) |
68c0a5c7 | 313 | #define HCLGE_TQP_ID_S 2 |
5392902d | 314 | #define HCLGE_TQP_ID_M GENMASK(12, 2) |
0305b443 | 315 | #define HCLGE_INT_GL_IDX_S 13 |
5392902d | 316 | #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) |
68c0a5c7 | 317 | __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; |
0305b443 L |
318 | u8 vfid; |
319 | u8 rsv; | |
68c0a5c7 S |
320 | }; |
321 | ||
f9f07091 | 322 | #define HCLGE_MAX_TC_NUM 8 |
68c0a5c7 S |
323 | #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ |
324 | #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ | |
d44f9b63 | 325 | struct hclge_tx_buff_alloc_cmd { |
f9f07091 | 326 | __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; |
68c0a5c7 S |
327 | u8 tx_buff_rsv[8]; |
328 | }; | |
329 | ||
d44f9b63 | 330 | struct hclge_rx_priv_buff_cmd { |
f9f07091 | 331 | __le16 buf_num[HCLGE_MAX_TC_NUM]; |
b8c8bf47 YL |
332 | __le16 shared_buf; |
333 | u8 rsv[6]; | |
68c0a5c7 S |
334 | }; |
335 | ||
d44f9b63 | 336 | struct hclge_query_version_cmd { |
68c0a5c7 S |
337 | __le32 firmware; |
338 | __le32 firmware_rsv[5]; | |
339 | }; | |
340 | ||
341 | #define HCLGE_RX_PRIV_EN_B 15 | |
342 | #define HCLGE_TC_NUM_ONE_DESC 4 | |
343 | struct hclge_priv_wl { | |
344 | __le16 high; | |
345 | __le16 low; | |
346 | }; | |
347 | ||
348 | struct hclge_rx_priv_wl_buf { | |
349 | struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; | |
350 | }; | |
351 | ||
352 | struct hclge_rx_com_thrd { | |
353 | struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; | |
354 | }; | |
355 | ||
356 | struct hclge_rx_com_wl { | |
357 | struct hclge_priv_wl com_wl; | |
358 | }; | |
359 | ||
360 | struct hclge_waterline { | |
361 | u32 low; | |
362 | u32 high; | |
363 | }; | |
364 | ||
365 | struct hclge_tc_thrd { | |
366 | u32 low; | |
367 | u32 high; | |
368 | }; | |
369 | ||
370 | struct hclge_priv_buf { | |
371 | struct hclge_waterline wl; /* Waterline for low and high*/ | |
372 | u32 buf_size; /* TC private buffer size */ | |
9ffe79a9 | 373 | u32 tx_buf_size; |
68c0a5c7 S |
374 | u32 enable; /* Enable TC private buffer or not */ |
375 | }; | |
376 | ||
68c0a5c7 S |
377 | struct hclge_shared_buf { |
378 | struct hclge_waterline self; | |
379 | struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; | |
380 | u32 buf_size; | |
381 | }; | |
382 | ||
acf61ecd YL |
383 | struct hclge_pkt_buf_alloc { |
384 | struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; | |
385 | struct hclge_shared_buf s_buf; | |
386 | }; | |
387 | ||
68c0a5c7 | 388 | #define HCLGE_RX_COM_WL_EN_B 15 |
d44f9b63 | 389 | struct hclge_rx_com_wl_buf_cmd { |
68c0a5c7 S |
390 | __le16 high_wl; |
391 | __le16 low_wl; | |
392 | u8 rsv[20]; | |
393 | }; | |
394 | ||
395 | #define HCLGE_RX_PKT_EN_B 15 | |
d44f9b63 | 396 | struct hclge_rx_pkt_buf_cmd { |
68c0a5c7 S |
397 | __le16 high_pkt; |
398 | __le16 low_pkt; | |
399 | u8 rsv[20]; | |
400 | }; | |
401 | ||
402 | #define HCLGE_PF_STATE_DONE_B 0 | |
403 | #define HCLGE_PF_STATE_MAIN_B 1 | |
404 | #define HCLGE_PF_STATE_BOND_B 2 | |
405 | #define HCLGE_PF_STATE_MAC_N_B 6 | |
406 | #define HCLGE_PF_MAC_NUM_MASK 0x3 | |
407 | #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) | |
408 | #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) | |
d44f9b63 | 409 | struct hclge_func_status_cmd { |
68c0a5c7 S |
410 | __le32 vf_rst_state[4]; |
411 | u8 pf_state; | |
412 | u8 mac_id; | |
413 | u8 rsv1; | |
414 | u8 pf_cnt_in_mac; | |
415 | u8 pf_num; | |
416 | u8 vf_num; | |
417 | u8 rsv[2]; | |
418 | }; | |
419 | ||
d44f9b63 | 420 | struct hclge_pf_res_cmd { |
68c0a5c7 S |
421 | __le16 tqp_num; |
422 | __le16 buf_size; | |
423 | __le16 msixcap_localid_ba_nic; | |
424 | __le16 msixcap_localid_ba_rocee; | |
375dd5e4 JS |
425 | #define HCLGE_MSIX_OFT_ROCEE_S 0 |
426 | #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) | |
68c0a5c7 | 427 | #define HCLGE_PF_VEC_NUM_S 0 |
c79301d8 | 428 | #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) |
68c0a5c7 S |
429 | __le16 pf_intr_vector_number; |
430 | __le16 pf_own_fun_number; | |
368686be YL |
431 | __le16 tx_buf_size; |
432 | __le16 dv_buf_size; | |
433 | __le32 rsv[2]; | |
68c0a5c7 S |
434 | }; |
435 | ||
436 | #define HCLGE_CFG_OFFSET_S 0 | |
5392902d | 437 | #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) |
68c0a5c7 | 438 | #define HCLGE_CFG_RD_LEN_S 24 |
5392902d | 439 | #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) |
68c0a5c7 S |
440 | #define HCLGE_CFG_RD_LEN_BYTES 16 |
441 | #define HCLGE_CFG_RD_LEN_UNIT 4 | |
442 | ||
443 | #define HCLGE_CFG_VMDQ_S 0 | |
5392902d | 444 | #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) |
68c0a5c7 | 445 | #define HCLGE_CFG_TC_NUM_S 8 |
5392902d | 446 | #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) |
68c0a5c7 | 447 | #define HCLGE_CFG_TQP_DESC_N_S 16 |
5392902d | 448 | #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) |
68c0a5c7 | 449 | #define HCLGE_CFG_PHY_ADDR_S 0 |
39e2151f | 450 | #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) |
68c0a5c7 | 451 | #define HCLGE_CFG_MEDIA_TP_S 8 |
5392902d | 452 | #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) |
68c0a5c7 | 453 | #define HCLGE_CFG_RX_BUF_LEN_S 16 |
5392902d | 454 | #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) |
68c0a5c7 | 455 | #define HCLGE_CFG_MAC_ADDR_H_S 0 |
5392902d | 456 | #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) |
68c0a5c7 | 457 | #define HCLGE_CFG_DEFAULT_SPEED_S 16 |
5392902d | 458 | #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) |
0e7a40cd PL |
459 | #define HCLGE_CFG_RSS_SIZE_S 24 |
460 | #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) | |
0979aa0b FL |
461 | #define HCLGE_CFG_SPEED_ABILITY_S 0 |
462 | #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) | |
39932473 JS |
463 | #define HCLGE_CFG_UMV_TBL_SPACE_S 16 |
464 | #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) | |
68c0a5c7 | 465 | |
d44f9b63 | 466 | struct hclge_cfg_param_cmd { |
68c0a5c7 S |
467 | __le32 offset; |
468 | __le32 rsv; | |
469 | __le32 param[4]; | |
470 | }; | |
471 | ||
472 | #define HCLGE_MAC_MODE 0x0 | |
473 | #define HCLGE_DESC_NUM 0x40 | |
474 | ||
475 | #define HCLGE_ALLOC_VALID_B 0 | |
d44f9b63 | 476 | struct hclge_vf_num_cmd { |
68c0a5c7 S |
477 | u8 alloc_valid; |
478 | u8 rsv[23]; | |
479 | }; | |
480 | ||
481 | #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 | |
482 | #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 | |
483 | #define HCLGE_RSS_HASH_KEY_NUM 16 | |
d44f9b63 | 484 | struct hclge_rss_config_cmd { |
68c0a5c7 S |
485 | u8 hash_config; |
486 | u8 rsv[7]; | |
487 | u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; | |
488 | }; | |
489 | ||
d44f9b63 | 490 | struct hclge_rss_input_tuple_cmd { |
68c0a5c7 S |
491 | u8 ipv4_tcp_en; |
492 | u8 ipv4_udp_en; | |
493 | u8 ipv4_sctp_en; | |
494 | u8 ipv4_fragment_en; | |
495 | u8 ipv6_tcp_en; | |
496 | u8 ipv6_udp_en; | |
497 | u8 ipv6_sctp_en; | |
498 | u8 ipv6_fragment_en; | |
499 | u8 rsv[16]; | |
500 | }; | |
501 | ||
502 | #define HCLGE_RSS_CFG_TBL_SIZE 16 | |
503 | ||
d44f9b63 | 504 | struct hclge_rss_indirection_table_cmd { |
a90bb9a5 YL |
505 | __le16 start_table_index; |
506 | __le16 rss_set_bitmap; | |
68c0a5c7 S |
507 | u8 rsv[4]; |
508 | u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; | |
509 | }; | |
510 | ||
511 | #define HCLGE_RSS_TC_OFFSET_S 0 | |
5392902d | 512 | #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) |
68c0a5c7 | 513 | #define HCLGE_RSS_TC_SIZE_S 12 |
5392902d | 514 | #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) |
68c0a5c7 | 515 | #define HCLGE_RSS_TC_VALID_B 15 |
d44f9b63 | 516 | struct hclge_rss_tc_mode_cmd { |
a90bb9a5 | 517 | __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; |
68c0a5c7 S |
518 | u8 rsv[8]; |
519 | }; | |
520 | ||
c79301d8 JS |
521 | #define HCLGE_LINK_STATUS_UP_B 0 |
522 | #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) | |
d44f9b63 | 523 | struct hclge_link_status_cmd { |
68c0a5c7 S |
524 | u8 status; |
525 | u8 rsv[23]; | |
526 | }; | |
527 | ||
528 | struct hclge_promisc_param { | |
529 | u8 vf_id; | |
530 | u8 enable; | |
531 | }; | |
532 | ||
96c0e861 PL |
533 | #define HCLGE_PROMISC_TX_EN_B BIT(4) |
534 | #define HCLGE_PROMISC_RX_EN_B BIT(5) | |
68c0a5c7 S |
535 | #define HCLGE_PROMISC_EN_B 1 |
536 | #define HCLGE_PROMISC_EN_ALL 0x7 | |
537 | #define HCLGE_PROMISC_EN_UC 0x1 | |
538 | #define HCLGE_PROMISC_EN_MC 0x2 | |
539 | #define HCLGE_PROMISC_EN_BC 0x4 | |
d44f9b63 | 540 | struct hclge_promisc_cfg_cmd { |
68c0a5c7 S |
541 | u8 flag; |
542 | u8 vf_id; | |
543 | __le16 rsv0; | |
544 | u8 rsv1[20]; | |
545 | }; | |
546 | ||
547 | enum hclge_promisc_type { | |
548 | HCLGE_UNICAST = 1, | |
549 | HCLGE_MULTICAST = 2, | |
550 | HCLGE_BROADCAST = 3, | |
551 | }; | |
552 | ||
553 | #define HCLGE_MAC_TX_EN_B 6 | |
554 | #define HCLGE_MAC_RX_EN_B 7 | |
555 | #define HCLGE_MAC_PAD_TX_B 11 | |
556 | #define HCLGE_MAC_PAD_RX_B 12 | |
557 | #define HCLGE_MAC_1588_TX_B 13 | |
558 | #define HCLGE_MAC_1588_RX_B 14 | |
559 | #define HCLGE_MAC_APP_LP_B 15 | |
560 | #define HCLGE_MAC_LINE_LP_B 16 | |
561 | #define HCLGE_MAC_FCS_TX_B 17 | |
562 | #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 | |
563 | #define HCLGE_MAC_RX_FCS_STRIP_B 19 | |
564 | #define HCLGE_MAC_RX_FCS_B 20 | |
565 | #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 | |
566 | #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 | |
567 | ||
d44f9b63 | 568 | struct hclge_config_mac_mode_cmd { |
68c0a5c7 S |
569 | __le32 txrx_pad_fcs_loop_en; |
570 | u8 rsv[20]; | |
571 | }; | |
572 | ||
573 | #define HCLGE_CFG_SPEED_S 0 | |
5392902d | 574 | #define HCLGE_CFG_SPEED_M GENMASK(5, 0) |
68c0a5c7 S |
575 | |
576 | #define HCLGE_CFG_DUPLEX_B 7 | |
577 | #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) | |
578 | ||
d44f9b63 | 579 | struct hclge_config_mac_speed_dup_cmd { |
68c0a5c7 S |
580 | u8 speed_dup; |
581 | ||
582 | #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 | |
583 | u8 mac_change_fec_en; | |
584 | u8 rsv[22]; | |
585 | }; | |
586 | ||
5392902d | 587 | #define HCLGE_RING_ID_MASK GENMASK(9, 0) |
68c0a5c7 S |
588 | #define HCLGE_TQP_ENABLE_B 0 |
589 | ||
590 | #define HCLGE_MAC_CFG_AN_EN_B 0 | |
591 | #define HCLGE_MAC_CFG_AN_INT_EN_B 1 | |
592 | #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 | |
593 | #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 | |
594 | #define HCLGE_MAC_CFG_AN_RST_B 4 | |
595 | ||
596 | #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) | |
597 | ||
d44f9b63 | 598 | struct hclge_config_auto_neg_cmd { |
68c0a5c7 S |
599 | __le32 cfg_an_cmd_flag; |
600 | u8 rsv[20]; | |
601 | }; | |
602 | ||
88d10bd6 JS |
603 | struct hclge_sfp_info_cmd { |
604 | __le32 speed; | |
605 | u8 query_type; /* 0: sfp speed, 1: active speed */ | |
606 | u8 active_fec; | |
607 | u8 autoneg; /* autoneg state */ | |
608 | u8 autoneg_ability; /* whether support autoneg */ | |
609 | __le32 speed_ability; /* speed ability for current media */ | |
610 | __le32 module_type; | |
611 | u8 rsv[8]; | |
5d497936 PL |
612 | }; |
613 | ||
7e6ec914 JS |
614 | #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 |
615 | #define HCLGE_MAC_CFG_FEC_MODE_S 1 | |
616 | #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) | |
617 | #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 | |
618 | #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 | |
619 | ||
620 | #define HCLGE_MAC_FEC_OFF 0 | |
621 | #define HCLGE_MAC_FEC_BASER 1 | |
622 | #define HCLGE_MAC_FEC_RS 2 | |
623 | struct hclge_config_fec_cmd { | |
624 | u8 fec_mode; | |
625 | u8 default_config; | |
626 | u8 rsv[22]; | |
627 | }; | |
628 | ||
68c0a5c7 S |
629 | #define HCLGE_MAC_UPLINK_PORT 0x100 |
630 | ||
d44f9b63 | 631 | struct hclge_config_max_frm_size_cmd { |
68c0a5c7 | 632 | __le16 max_frm_size; |
8fc7346c JS |
633 | u8 min_frm_size; |
634 | u8 rsv[21]; | |
68c0a5c7 S |
635 | }; |
636 | ||
637 | enum hclge_mac_vlan_tbl_opcode { | |
638 | HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ | |
639 | HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ | |
640 | HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ | |
641 | HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ | |
642 | }; | |
643 | ||
f8a91784 JS |
644 | #define HCLGE_MAC_VLAN_BIT0_EN_B 0 |
645 | #define HCLGE_MAC_VLAN_BIT1_EN_B 1 | |
646 | #define HCLGE_MAC_EPORT_SW_EN_B 12 | |
647 | #define HCLGE_MAC_EPORT_TYPE_B 11 | |
648 | #define HCLGE_MAC_EPORT_VFID_S 3 | |
5392902d | 649 | #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) |
f8a91784 | 650 | #define HCLGE_MAC_EPORT_PFID_S 0 |
5392902d | 651 | #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) |
d44f9b63 | 652 | struct hclge_mac_vlan_tbl_entry_cmd { |
68c0a5c7 S |
653 | u8 flags; |
654 | u8 resp_code; | |
655 | __le16 vlan_tag; | |
656 | __le32 mac_addr_hi32; | |
657 | __le16 mac_addr_lo16; | |
658 | __le16 rsv1; | |
659 | u8 entry_type; | |
660 | u8 mc_mac_en; | |
661 | __le16 egress_port; | |
662 | __le16 egress_queue; | |
663 | u8 rsv2[6]; | |
664 | }; | |
665 | ||
39932473 JS |
666 | #define HCLGE_UMV_SPC_ALC_B 0 |
667 | struct hclge_umv_spc_alc_cmd { | |
668 | u8 allocate; | |
669 | u8 rsv1[3]; | |
670 | __le32 space_size; | |
671 | u8 rsv2[16]; | |
672 | }; | |
673 | ||
f5aac71c FL |
674 | #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) |
675 | #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) | |
676 | #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) | |
677 | #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc | |
678 | ||
679 | struct hclge_mac_mgr_tbl_entry_cmd { | |
680 | u8 flags; | |
681 | u8 resp_code; | |
682 | __le16 vlan_tag; | |
683 | __le32 mac_addr_hi32; | |
684 | __le16 mac_addr_lo16; | |
685 | __le16 rsv1; | |
686 | __le16 ethter_type; | |
687 | __le16 egress_port; | |
688 | __le16 egress_queue; | |
689 | u8 sw_port_id_aware; | |
690 | u8 rsv2; | |
691 | u8 i_port_bitmap; | |
692 | u8 i_port_direction; | |
693 | u8 rsv3[2]; | |
694 | }; | |
695 | ||
d44f9b63 | 696 | struct hclge_mac_vlan_add_cmd { |
68c0a5c7 S |
697 | __le16 flags; |
698 | __le16 mac_addr_hi16; | |
699 | __le32 mac_addr_lo32; | |
700 | __le32 mac_addr_msk_hi32; | |
701 | __le16 mac_addr_msk_lo16; | |
702 | __le16 vlan_tag; | |
703 | __le16 ingress_port; | |
704 | __le16 egress_port; | |
705 | u8 rsv[4]; | |
706 | }; | |
707 | ||
708 | #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 | |
d44f9b63 | 709 | struct hclge_mac_vlan_remove_cmd { |
68c0a5c7 S |
710 | __le16 flags; |
711 | __le16 mac_addr_hi16; | |
712 | __le32 mac_addr_lo32; | |
713 | __le32 mac_addr_msk_hi32; | |
714 | __le16 mac_addr_msk_lo16; | |
715 | __le16 vlan_tag; | |
716 | __le16 ingress_port; | |
717 | __le16 egress_port; | |
718 | u8 rsv[4]; | |
719 | }; | |
720 | ||
d44f9b63 | 721 | struct hclge_vlan_filter_ctrl_cmd { |
68c0a5c7 S |
722 | u8 vlan_type; |
723 | u8 vlan_fe; | |
30ebc576 JS |
724 | u8 rsv1[2]; |
725 | u8 vf_id; | |
726 | u8 rsv2[19]; | |
68c0a5c7 S |
727 | }; |
728 | ||
d44f9b63 | 729 | struct hclge_vlan_filter_pf_cfg_cmd { |
68c0a5c7 S |
730 | u8 vlan_offset; |
731 | u8 vlan_cfg; | |
732 | u8 rsv[2]; | |
733 | u8 vlan_offset_bitmap[20]; | |
734 | }; | |
735 | ||
d44f9b63 | 736 | struct hclge_vlan_filter_vf_cfg_cmd { |
a90bb9a5 | 737 | __le16 vlan_id; |
68c0a5c7 S |
738 | u8 resp_code; |
739 | u8 rsv; | |
740 | u8 vlan_cfg; | |
741 | u8 rsv1[3]; | |
742 | u8 vf_bitmap[16]; | |
743 | }; | |
744 | ||
dcb35cce PL |
745 | #define HCLGE_ACCEPT_TAG1_B 0 |
746 | #define HCLGE_ACCEPT_UNTAG1_B 1 | |
5f6ea83f PL |
747 | #define HCLGE_PORT_INS_TAG1_EN_B 2 |
748 | #define HCLGE_PORT_INS_TAG2_EN_B 3 | |
749 | #define HCLGE_CFG_NIC_ROCE_SEL_B 4 | |
dcb35cce PL |
750 | #define HCLGE_ACCEPT_TAG2_B 5 |
751 | #define HCLGE_ACCEPT_UNTAG2_B 6 | |
752 | ||
5f6ea83f PL |
753 | struct hclge_vport_vtag_tx_cfg_cmd { |
754 | u8 vport_vlan_cfg; | |
755 | u8 vf_offset; | |
756 | u8 rsv1[2]; | |
757 | __le16 def_vlan_tag1; | |
758 | __le16 def_vlan_tag2; | |
759 | u8 vf_bitmap[8]; | |
760 | u8 rsv2[8]; | |
761 | }; | |
762 | ||
763 | #define HCLGE_REM_TAG1_EN_B 0 | |
764 | #define HCLGE_REM_TAG2_EN_B 1 | |
765 | #define HCLGE_SHOW_TAG1_EN_B 2 | |
766 | #define HCLGE_SHOW_TAG2_EN_B 3 | |
767 | struct hclge_vport_vtag_rx_cfg_cmd { | |
768 | u8 vport_vlan_cfg; | |
769 | u8 vf_offset; | |
770 | u8 rsv1[6]; | |
771 | u8 vf_bitmap[8]; | |
772 | u8 rsv2[8]; | |
773 | }; | |
774 | ||
775 | struct hclge_tx_vlan_type_cfg_cmd { | |
776 | __le16 ot_vlan_type; | |
777 | __le16 in_vlan_type; | |
778 | u8 rsv[20]; | |
779 | }; | |
780 | ||
781 | struct hclge_rx_vlan_type_cfg_cmd { | |
782 | __le16 ot_fst_vlan_type; | |
783 | __le16 ot_sec_vlan_type; | |
784 | __le16 in_fst_vlan_type; | |
785 | __le16 in_sec_vlan_type; | |
786 | u8 rsv[16]; | |
787 | }; | |
788 | ||
d44f9b63 | 789 | struct hclge_cfg_com_tqp_queue_cmd { |
68c0a5c7 S |
790 | __le16 tqp_id; |
791 | __le16 stream_id; | |
792 | u8 enable; | |
793 | u8 rsv[19]; | |
794 | }; | |
795 | ||
d44f9b63 | 796 | struct hclge_cfg_tx_queue_pointer_cmd { |
68c0a5c7 S |
797 | __le16 tqp_id; |
798 | __le16 tx_tail; | |
799 | __le16 tx_head; | |
800 | __le16 fbd_num; | |
801 | __le16 ring_offset; | |
802 | u8 rsv[14]; | |
803 | }; | |
804 | ||
7737f1fb | 805 | #pragma pack(1) |
806 | struct hclge_mac_ethertype_idx_rd_cmd { | |
807 | u8 flags; | |
808 | u8 resp_code; | |
809 | __le16 vlan_tag; | |
810 | u8 mac_add[6]; | |
811 | __le16 index; | |
812 | __le16 ethter_type; | |
813 | __le16 egress_port; | |
814 | __le16 egress_queue; | |
815 | __le16 rev0; | |
816 | u8 i_port_bitmap; | |
817 | u8 i_port_direction; | |
818 | u8 rev1[2]; | |
819 | }; | |
820 | ||
821 | #pragma pack() | |
822 | ||
68c0a5c7 | 823 | #define HCLGE_TSO_MSS_MIN_S 0 |
5392902d | 824 | #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) |
68c0a5c7 S |
825 | |
826 | #define HCLGE_TSO_MSS_MAX_S 16 | |
5392902d | 827 | #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) |
68c0a5c7 | 828 | |
d44f9b63 | 829 | struct hclge_cfg_tso_status_cmd { |
68c0a5c7 S |
830 | __le16 tso_mss_min; |
831 | __le16 tso_mss_max; | |
832 | u8 rsv[20]; | |
833 | }; | |
834 | ||
b26a6fea PL |
835 | #define HCLGE_GRO_EN_B 0 |
836 | struct hclge_cfg_gro_status_cmd { | |
837 | __le16 gro_en; | |
838 | u8 rsv[22]; | |
839 | }; | |
840 | ||
68c0a5c7 S |
841 | #define HCLGE_TSO_MSS_MIN 256 |
842 | #define HCLGE_TSO_MSS_MAX 9668 | |
843 | ||
844 | #define HCLGE_TQP_RESET_B 0 | |
d44f9b63 | 845 | struct hclge_reset_tqp_queue_cmd { |
68c0a5c7 S |
846 | __le16 tqp_id; |
847 | u8 reset_req; | |
848 | u8 ready_to_reset; | |
849 | u8 rsv[20]; | |
850 | }; | |
851 | ||
4ed340ab L |
852 | #define HCLGE_CFG_RESET_MAC_B 3 |
853 | #define HCLGE_CFG_RESET_FUNC_B 7 | |
854 | struct hclge_reset_cmd { | |
855 | u8 mac_func_reset; | |
856 | u8 fun_reset_vfid; | |
857 | u8 rsv[22]; | |
858 | }; | |
5fd50ac3 PL |
859 | |
860 | #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) | |
4dc13b96 | 861 | #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) |
5fd50ac3 PL |
862 | #define HCLGE_CMD_SERDES_DONE_B BIT(0) |
863 | #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) | |
864 | struct hclge_serdes_lb_cmd { | |
865 | u8 mask; | |
866 | u8 enable; | |
867 | u8 result; | |
868 | u8 rsv[21]; | |
869 | }; | |
870 | ||
68c0a5c7 S |
871 | #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ |
872 | #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ | |
873 | #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ | |
d221df4e | 874 | #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ |
368686be | 875 | #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */ |
68c0a5c7 S |
876 | |
877 | #define HCLGE_TYPE_CRQ 0 | |
878 | #define HCLGE_TYPE_CSQ 1 | |
879 | #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 | |
880 | #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 | |
881 | #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 | |
882 | #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 | |
883 | #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 | |
884 | #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 | |
885 | #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c | |
886 | #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 | |
887 | #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 | |
888 | #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 | |
889 | #define HCLGE_NIC_CMQ_EN_B 16 | |
890 | #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) | |
891 | #define HCLGE_NIC_CMQ_DESC_NUM 1024 | |
892 | #define HCLGE_NIC_CMQ_DESC_NUM_S 3 | |
893 | ||
07f8e940 JS |
894 | #define HCLGE_LED_LOCATE_STATE_S 0 |
895 | #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) | |
896 | ||
897 | struct hclge_set_led_state_cmd { | |
f6f75abc | 898 | u8 rsv1[3]; |
07f8e940 | 899 | u8 locate_led_config; |
f6f75abc | 900 | u8 rsv2[20]; |
07f8e940 JS |
901 | }; |
902 | ||
d695964d JS |
903 | struct hclge_get_fd_mode_cmd { |
904 | u8 mode; | |
905 | u8 enable; | |
906 | u8 rsv[22]; | |
907 | }; | |
908 | ||
909 | struct hclge_get_fd_allocation_cmd { | |
910 | __le32 stage1_entry_num; | |
911 | __le32 stage2_entry_num; | |
912 | __le16 stage1_counter_num; | |
913 | __le16 stage2_counter_num; | |
914 | u8 rsv[12]; | |
915 | }; | |
916 | ||
917 | struct hclge_set_fd_key_config_cmd { | |
918 | u8 stage; | |
919 | u8 key_select; | |
920 | u8 inner_sipv6_word_en; | |
921 | u8 inner_dipv6_word_en; | |
922 | u8 outer_sipv6_word_en; | |
923 | u8 outer_dipv6_word_en; | |
924 | u8 rsv1[2]; | |
925 | __le32 tuple_mask; | |
926 | __le32 meta_data_mask; | |
927 | u8 rsv2[8]; | |
928 | }; | |
929 | ||
11732868 JS |
930 | #define HCLGE_FD_EPORT_SW_EN_B 0 |
931 | struct hclge_fd_tcam_config_1_cmd { | |
932 | u8 stage; | |
933 | u8 xy_sel; | |
934 | u8 port_info; | |
935 | u8 rsv1[1]; | |
936 | __le32 index; | |
937 | u8 entry_vld; | |
938 | u8 rsv2[7]; | |
939 | u8 tcam_data[8]; | |
940 | }; | |
941 | ||
942 | struct hclge_fd_tcam_config_2_cmd { | |
943 | u8 tcam_data[24]; | |
944 | }; | |
945 | ||
946 | struct hclge_fd_tcam_config_3_cmd { | |
947 | u8 tcam_data[20]; | |
948 | u8 rsv[4]; | |
949 | }; | |
950 | ||
951 | #define HCLGE_FD_AD_DROP_B 0 | |
952 | #define HCLGE_FD_AD_DIRECT_QID_B 1 | |
953 | #define HCLGE_FD_AD_QID_S 2 | |
954 | #define HCLGE_FD_AD_QID_M GENMASK(12, 2) | |
955 | #define HCLGE_FD_AD_USE_COUNTER_B 12 | |
956 | #define HCLGE_FD_AD_COUNTER_NUM_S 13 | |
957 | #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) | |
958 | #define HCLGE_FD_AD_NXT_STEP_B 20 | |
959 | #define HCLGE_FD_AD_NXT_KEY_S 21 | |
960 | #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) | |
961 | #define HCLGE_FD_AD_WR_RULE_ID_B 0 | |
962 | #define HCLGE_FD_AD_RULE_ID_S 1 | |
963 | #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) | |
964 | ||
965 | struct hclge_fd_ad_config_cmd { | |
966 | u8 stage; | |
967 | u8 rsv1[3]; | |
968 | __le32 index; | |
969 | __le64 ad_data; | |
970 | u8 rsv2[8]; | |
971 | }; | |
972 | ||
68c0a5c7 S |
973 | int hclge_cmd_init(struct hclge_dev *hdev); |
974 | static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) | |
975 | { | |
976 | writel(value, base + reg); | |
977 | } | |
978 | ||
979 | #define hclge_write_dev(a, reg, value) \ | |
980 | hclge_write_reg((a)->io_base, (reg), (value)) | |
981 | #define hclge_read_dev(a, reg) \ | |
982 | hclge_read_reg((a)->io_base, (reg)) | |
983 | ||
984 | static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) | |
985 | { | |
986 | u8 __iomem *reg_addr = READ_ONCE(base); | |
987 | ||
988 | return readl(reg_addr + reg); | |
989 | } | |
990 | ||
991 | #define HCLGE_SEND_SYNC(flag) \ | |
992 | ((flag) & HCLGE_CMD_FLAG_NO_INTR) | |
993 | ||
994 | struct hclge_hw; | |
995 | int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); | |
996 | void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, | |
997 | enum hclge_opcode_type opcode, bool is_read); | |
f7db940a | 998 | void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); |
68c0a5c7 S |
999 | |
1000 | int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, | |
1001 | struct hclge_promisc_param *param); | |
1002 | ||
1003 | enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, | |
1004 | struct hclge_desc *desc); | |
1005 | enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, | |
1006 | struct hclge_desc *desc); | |
1007 | ||
232d0d55 | 1008 | void hclge_cmd_uninit(struct hclge_dev *hdev); |
3efb960f | 1009 | int hclge_cmd_queue_init(struct hclge_dev *hdev); |
68c0a5c7 | 1010 | #endif |