[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.h

// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2016-2017 Hisilicon Limited.

#ifndef __HNS3_ENET_H
#define __HNS3_ENET_H

#include <linux/if_vlan.h>

#include "hnae3.h"

#define HNS3_MOD_VERSION "1.0"

extern const char hns3_driver_version[];

enum hns3_nic_state {
	HNS3_NIC_STATE_TESTING,
	HNS3_NIC_STATE_RESETTING,
	HNS3_NIC_STATE_INITED,
	HNS3_NIC_STATE_DOWN,
	HNS3_NIC_STATE_DISABLED,
	HNS3_NIC_STATE_REMOVING,
	HNS3_NIC_STATE_SERVICE_INITED,
	HNS3_NIC_STATE_SERVICE_SCHED,
	HNS3_NIC_STATE2_RESET_REQUESTED,
	HNS3_NIC_STATE_MAX
};

#define HNS3_RING_RX_RING_BASEADDR_L_REG	0x00000
#define HNS3_RING_RX_RING_BASEADDR_H_REG	0x00004
#define HNS3_RING_RX_RING_BD_NUM_REG		0x00008
#define HNS3_RING_RX_RING_BD_LEN_REG		0x0000C
#define HNS3_RING_RX_RING_TAIL_REG		0x00018
#define HNS3_RING_RX_RING_HEAD_REG		0x0001C
#define HNS3_RING_RX_RING_FBDNUM_REG		0x00020
#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG	0x0002C

#define HNS3_RING_TX_RING_BASEADDR_L_REG	0x00040
#define HNS3_RING_TX_RING_BASEADDR_H_REG	0x00044
#define HNS3_RING_TX_RING_BD_NUM_REG		0x00048
#define HNS3_RING_TX_RING_TC_REG		0x00050
#define HNS3_RING_TX_RING_TAIL_REG		0x00058
#define HNS3_RING_TX_RING_HEAD_REG		0x0005C
#define HNS3_RING_TX_RING_FBDNUM_REG		0x00060
#define HNS3_RING_TX_RING_OFFSET_REG		0x00064
#define HNS3_RING_TX_RING_EBDNUM_REG		0x00068
#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG	0x0006C
#define HNS3_RING_TX_RING_EBD_OFFSET_REG	0x00070
#define HNS3_RING_TX_RING_BD_ERR_REG		0x00074
#define HNS3_RING_PREFETCH_EN_REG		0x0007C
#define HNS3_RING_CFG_VF_NUM_REG		0x00080
#define HNS3_RING_ASID_REG			0x0008C
#define HNS3_RING_EN_REG			0x00090
#define HNS3_RING_T0_BE_RST			0x00094
#define HNS3_RING_COULD_BE_RST			0x00098
#define HNS3_RING_WRR_WEIGHT_REG		0x0009c

#define HNS3_RING_INTMSK_RXWL_REG		0x000A0
#define HNS3_RING_INTSTS_RX_RING_REG		0x000A4
#define HNS3_RX_RING_INT_STS_REG		0x000A8
#define HNS3_RING_INTMSK_TXWL_REG		0x000AC
#define HNS3_RING_INTSTS_TX_RING_REG		0x000B0
#define HNS3_TX_RING_INT_STS_REG		0x000B4
#define HNS3_RING_INTMSK_RX_OVERTIME_REG	0x000B8
#define HNS3_RING_INTSTS_RX_OVERTIME_REG	0x000BC
#define HNS3_RING_INTMSK_TX_OVERTIME_REG	0x000C4
#define HNS3_RING_INTSTS_TX_OVERTIME_REG	0x000C8

#define HNS3_RING_MB_CTRL_REG			0x00100
#define HNS3_RING_MB_DATA_BASE_REG		0x00200

#define HNS3_TX_REG_OFFSET			0x40

#define HNS3_RX_HEAD_SIZE			256

#define HNS3_TX_TIMEOUT (5 * HZ)
#define HNS3_RING_NAME_LEN			16
#define HNS3_BUFFER_SIZE_2048			2048
#define HNS3_RING_MAX_PENDING			32760
#define HNS3_RING_MIN_PENDING			24
#define HNS3_RING_BD_MULTIPLE			8
/* max frame size of mac */
#define HNS3_MAC_MAX_FRAME			9728
#define HNS3_MAX_MTU \
	(HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))

#define HNS3_BD_SIZE_512_TYPE			0
#define HNS3_BD_SIZE_1024_TYPE			1
#define HNS3_BD_SIZE_2048_TYPE			2
#define HNS3_BD_SIZE_4096_TYPE			3

#define HNS3_RX_FLAG_VLAN_PRESENT		0x1
#define HNS3_RX_FLAG_L3ID_IPV4			0x0
#define HNS3_RX_FLAG_L3ID_IPV6			0x1
#define HNS3_RX_FLAG_L4ID_UDP			0x0
#define HNS3_RX_FLAG_L4ID_TCP			0x1

#define HNS3_RXD_DMAC_S				0
#define HNS3_RXD_DMAC_M				(0x3 << HNS3_RXD_DMAC_S)
#define HNS3_RXD_VLAN_S				2
#define HNS3_RXD_VLAN_M				(0x3 << HNS3_RXD_VLAN_S)
#define HNS3_RXD_L3ID_S				4
#define HNS3_RXD_L3ID_M				(0xf << HNS3_RXD_L3ID_S)
#define HNS3_RXD_L4ID_S				8
#define HNS3_RXD_L4ID_M				(0xf << HNS3_RXD_L4ID_S)
#define HNS3_RXD_FRAG_B				12
#define HNS3_RXD_STRP_TAGP_S			13
#define HNS3_RXD_STRP_TAGP_M			(0x3 << HNS3_RXD_STRP_TAGP_S)

#define HNS3_RXD_L2E_B				16
#define HNS3_RXD_L3E_B				17
#define HNS3_RXD_L4E_B				18
#define HNS3_RXD_TRUNCAT_B			19
#define HNS3_RXD_HOI_B				20
#define HNS3_RXD_DOI_B				21
#define HNS3_RXD_OL3E_B				22
#define HNS3_RXD_OL4E_B				23
#define HNS3_RXD_GRO_COUNT_S			24
#define HNS3_RXD_GRO_COUNT_M			(0x3f << HNS3_RXD_GRO_COUNT_S)
#define HNS3_RXD_GRO_FIXID_B			30
#define HNS3_RXD_GRO_ECN_B			31

#define HNS3_RXD_ODMAC_S			0
#define HNS3_RXD_ODMAC_M			(0x3 << HNS3_RXD_ODMAC_S)
#define HNS3_RXD_OVLAN_S			2
#define HNS3_RXD_OVLAN_M			(0x3 << HNS3_RXD_OVLAN_S)
#define HNS3_RXD_OL3ID_S			4
#define HNS3_RXD_OL3ID_M			(0xf << HNS3_RXD_OL3ID_S)
#define HNS3_RXD_OL4ID_S			8
#define HNS3_RXD_OL4ID_M			(0xf << HNS3_RXD_OL4ID_S)
#define HNS3_RXD_FBHI_S				12
#define HNS3_RXD_FBHI_M				(0x3 << HNS3_RXD_FBHI_S)
#define HNS3_RXD_FBLI_S				14
#define HNS3_RXD_FBLI_M				(0x3 << HNS3_RXD_FBLI_S)

#define HNS3_RXD_BDTYPE_S			0
#define HNS3_RXD_BDTYPE_M			(0xf << HNS3_RXD_BDTYPE_S)
#define HNS3_RXD_VLD_B				4
#define HNS3_RXD_UDP0_B				5
#define HNS3_RXD_EXTEND_B			7
#define HNS3_RXD_FE_B				8
#define HNS3_RXD_LUM_B				9
#define HNS3_RXD_CRCP_B				10
#define HNS3_RXD_L3L4P_B			11
#define HNS3_RXD_TSIND_S			12
#define HNS3_RXD_TSIND_M			(0x7 << HNS3_RXD_TSIND_S)
#define HNS3_RXD_LKBK_B				15
#define HNS3_RXD_GRO_SIZE_S			16
#define HNS3_RXD_GRO_SIZE_M			(0x3fff << HNS3_RXD_GRO_SIZE_S)

#define HNS3_TXD_L3T_S				0
#define HNS3_TXD_L3T_M				(0x3 << HNS3_TXD_L3T_S)
#define HNS3_TXD_L4T_S				2
#define HNS3_TXD_L4T_M				(0x3 << HNS3_TXD_L4T_S)
#define HNS3_TXD_L3CS_B				4
#define HNS3_TXD_L4CS_B				5
#define HNS3_TXD_VLAN_B				6
#define HNS3_TXD_TSO_B				7

#define HNS3_TXD_L2LEN_S			8
#define HNS3_TXD_L2LEN_M			(0xff << HNS3_TXD_L2LEN_S)
#define HNS3_TXD_L3LEN_S			16
#define HNS3_TXD_L3LEN_M			(0xff << HNS3_TXD_L3LEN_S)
#define HNS3_TXD_L4LEN_S			24
#define HNS3_TXD_L4LEN_M			(0xff << HNS3_TXD_L4LEN_S)

#define HNS3_TXD_OL3T_S				0
#define HNS3_TXD_OL3T_M				(0x3 << HNS3_TXD_OL3T_S)
#define HNS3_TXD_OVLAN_B			2
#define HNS3_TXD_MACSEC_B			3
#define HNS3_TXD_TUNTYPE_S			4
#define HNS3_TXD_TUNTYPE_M			(0xf << HNS3_TXD_TUNTYPE_S)

#define HNS3_TXD_BDTYPE_S			0
#define HNS3_TXD_BDTYPE_M			(0xf << HNS3_TXD_BDTYPE_S)
#define HNS3_TXD_FE_B				4
#define HNS3_TXD_SC_S				5
#define HNS3_TXD_SC_M				(0x3 << HNS3_TXD_SC_S)
#define HNS3_TXD_EXTEND_B			7
#define HNS3_TXD_VLD_B				8
#define HNS3_TXD_RI_B				9
#define HNS3_TXD_RA_B				10
#define HNS3_TXD_TSYN_B				11
#define HNS3_TXD_DECTTL_S			12
#define HNS3_TXD_DECTTL_M			(0xf << HNS3_TXD_DECTTL_S)

#define HNS3_TXD_MSS_S				0
#define HNS3_TXD_MSS_M				(0x3fff << HNS3_TXD_MSS_S)

#define HNS3_TX_LAST_SIZE_M                    0xffff

#define HNS3_VECTOR_TX_IRQ			BIT_ULL(0)
#define HNS3_VECTOR_RX_IRQ			BIT_ULL(1)

#define HNS3_VECTOR_NOT_INITED			0
#define HNS3_VECTOR_INITED			1

#define HNS3_MAX_BD_SIZE			65535
#define HNS3_MAX_BD_NUM_NORMAL			8
#define HNS3_MAX_BD_NUM_TSO			63
#define HNS3_MAX_BD_PER_PKT			MAX_SKB_FRAGS

#define HNS3_VECTOR_GL0_OFFSET			0x100
#define HNS3_VECTOR_GL1_OFFSET			0x200
#define HNS3_VECTOR_GL2_OFFSET			0x300
#define HNS3_VECTOR_RL_OFFSET			0x900
#define HNS3_VECTOR_RL_EN_B			6

#define HNS3_RING_EN_B				0

enum hns3_pkt_l2t_type {
	HNS3_L2_TYPE_UNICAST,
	HNS3_L2_TYPE_MULTICAST,
	HNS3_L2_TYPE_BROADCAST,
	HNS3_L2_TYPE_INVALID,
};

enum hns3_pkt_l3t_type {
	HNS3_L3T_NONE,
	HNS3_L3T_IPV6,
	HNS3_L3T_IPV4,
	HNS3_L3T_RESERVED
};

enum hns3_pkt_l4t_type {
	HNS3_L4T_UNKNOWN,
	HNS3_L4T_TCP,
	HNS3_L4T_UDP,
	HNS3_L4T_SCTP
};

enum hns3_pkt_ol3t_type {
	HNS3_OL3T_NONE,
	HNS3_OL3T_IPV6,
	HNS3_OL3T_IPV4_NO_CSUM,
	HNS3_OL3T_IPV4_CSUM
};

enum hns3_pkt_tun_type {
	HNS3_TUN_NONE,
	HNS3_TUN_MAC_IN_UDP,
	HNS3_TUN_NVGRE,
	HNS3_TUN_OTHER
};

/* hardware spec ring buffer format */
struct __packed hns3_desc {
	__le64 addr;
	union {
		struct {
			__le16 vlan_tag;
			__le16 send_size;
			union {
				__le32 type_cs_vlan_tso_len;
				struct {
					__u8 type_cs_vlan_tso;
					__u8 l2_len;
					__u8 l3_len;
					__u8 l4_len;
				};
			};
			__le16 outer_vlan_tag;
			__le16 tv;

		union {
			__le32 ol_type_vlan_len_msec;
			struct {
				__u8 ol_type_vlan_msec;
				__u8 ol2_len;
				__u8 ol3_len;
				__u8 ol4_len;
			};
		};

			__le32 paylen;
			__le16 bdtp_fe_sc_vld_ra_ri;
			__le16 mss;
		} tx;

		struct {
			__le32 l234_info;
			__le16 pkt_len;
			__le16 size;

			__le32 rss_hash;
			__le16 fd_id;
			__le16 vlan_tag;

			union {
				__le32 ol_info;
				struct {
					__le16 o_dm_vlan_id_fb;
					__le16 ot_vlan_tag;
				};
			};

			__le32 bd_base_info;
		} rx;
	};
};

struct hns3_desc_cb {
	dma_addr_t dma; /* dma address of this desc */
	void *buf;      /* cpu addr for a desc */

	/* priv data for the desc, e.g. skb when use with ip stack */
	void *priv;
	u32 page_offset;
	u32 length;     /* length of the buffer */

	u16 reuse_flag;

       /* desc type, used by the ring user to mark the type of the priv data */
	u16 type;
};

enum hns3_pkt_l3type {
	HNS3_L3_TYPE_IPV4,
	HNS3_L3_TYPE_IPV6,
	HNS3_L3_TYPE_ARP,
	HNS3_L3_TYPE_RARP,
	HNS3_L3_TYPE_IPV4_OPT,
	HNS3_L3_TYPE_IPV6_EXT,
	HNS3_L3_TYPE_LLDP,
	HNS3_L3_TYPE_BPDU,
	HNS3_L3_TYPE_MAC_PAUSE,
	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/

	/* reserved for 0xA~0xB */

	HNS3_L3_TYPE_CNM = 0xc,

	/* reserved for 0xD~0xE */

	HNS3_L3_TYPE_PARSE_FAIL	= 0xf /* must be last */
};

enum hns3_pkt_l4type {
	HNS3_L4_TYPE_UDP,
	HNS3_L4_TYPE_TCP,
	HNS3_L4_TYPE_GRE,
	HNS3_L4_TYPE_SCTP,
	HNS3_L4_TYPE_IGMP,
	HNS3_L4_TYPE_ICMP,

	/* reserved for 0x6~0xE */

	HNS3_L4_TYPE_PARSE_FAIL	= 0xf /* must be last */
};

enum hns3_pkt_ol3type {
	HNS3_OL3_TYPE_IPV4 = 0,
	HNS3_OL3_TYPE_IPV6,
	/* reserved for 0x2~0x3 */
	HNS3_OL3_TYPE_IPV4_OPT = 4,
	HNS3_OL3_TYPE_IPV6_EXT,

	/* reserved for 0x6~0xE */

	HNS3_OL3_TYPE_PARSE_FAIL = 0xf	/* must be last */
};

enum hns3_pkt_ol4type {
	HNS3_OL4_TYPE_NO_TUN,
	HNS3_OL4_TYPE_MAC_IN_UDP,
	HNS3_OL4_TYPE_NVGRE,
	HNS3_OL4_TYPE_UNKNOWN
};

struct ring_stats {
	u64 io_err_cnt;
	u64 sw_err_cnt;
	u64 seg_pkt_cnt;
	union {
		struct {
			u64 tx_pkts;
			u64 tx_bytes;
			u64 tx_err_cnt;
			u64 restart_queue;
			u64 tx_busy;
			u64 tx_copy;
			u64 tx_vlan_err;
			u64 tx_l4_proto_err;
			u64 tx_l2l3l4_err;
			u64 tx_tso_err;
		};
		struct {
			u64 rx_pkts;
			u64 rx_bytes;
			u64 rx_err_cnt;
			u64 reuse_pg_cnt;
			u64 err_pkt_len;
			u64 err_bd_num;
			u64 l2_err;
			u64 l3l4_csum_err;
			u64 rx_multicast;
			u64 non_reuse_pg;
		};
	};
};

struct hns3_enet_ring {
	u8 __iomem *io_base; /* base io address for the ring */
	struct hns3_desc *desc; /* dma map address space */
	struct hns3_desc_cb *desc_cb;
	struct hns3_enet_ring *next;
	struct hns3_enet_tqp_vector *tqp_vector;
	struct hnae3_queue *tqp;
	struct device *dev; /* will be used for DMA mapping of descriptors */

	/* statistic */
	struct ring_stats stats;
	struct u64_stats_sync syncp;

	dma_addr_t desc_dma_addr;
	u32 buf_size;       /* size for hnae_desc->addr, preset by AE */
	u16 desc_num;       /* total number of desc */
	int next_to_use;    /* idx of next spare desc */

	/* idx of lastest sent desc, the ring is empty when equal to
	 * next_to_use
	 */
	int next_to_clean;

	u32 pull_len; /* head length for current packet */
	u32 frag_num;
	unsigned char *va; /* first buffer address for current packet */

	u32 flag;          /* ring attribute */

	int pending_buf;
	struct sk_buff *skb;
	struct sk_buff *tail_skb;
};

struct hns_queue;

struct hns3_nic_ring_data {
	struct hns3_enet_ring *ring;
	struct napi_struct napi;
	int queue_index;
	int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
	void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
	void (*fini_process)(struct hns3_nic_ring_data *);
};

enum hns3_flow_level_range {
	HNS3_FLOW_LOW = 0,
	HNS3_FLOW_MID = 1,
	HNS3_FLOW_HIGH = 2,
	HNS3_FLOW_ULTRA = 3,
};

#define HNS3_INT_GL_MAX			0x1FE0
#define HNS3_INT_GL_50K			0x0014
#define HNS3_INT_GL_20K			0x0032
#define HNS3_INT_GL_18K			0x0036
#define HNS3_INT_GL_8K			0x007C

#define HNS3_INT_RL_MAX			0x00EC
#define HNS3_INT_RL_ENABLE_MASK		0x40

struct hns3_enet_coalesce {
	u16 int_gl;
	u8 gl_adapt_enable;
	enum hns3_flow_level_range flow_level;
};

struct hns3_enet_ring_group {
	/* array of pointers to rings */
	struct hns3_enet_ring *ring;
	u64 total_bytes;	/* total bytes processed this group */
	u64 total_packets;	/* total packets processed this group */
	u16 count;
	struct hns3_enet_coalesce coal;
};

struct hns3_enet_tqp_vector {
	struct hnae3_handle *handle;
	u8 __iomem *mask_addr;
	int vector_irq;
	int irq_init_flag;

	u16 idx;		/* index in the TQP vector array per handle. */

	struct napi_struct napi;

	struct hns3_enet_ring_group rx_group;
	struct hns3_enet_ring_group tx_group;

	cpumask_t affinity_mask;
	u16 num_tqps;	/* total number of tqps in TQP vector */
	struct irq_affinity_notify affinity_notify;

	char name[HNAE3_INT_NAME_LEN];

	unsigned long last_jiffies;
} ____cacheline_internodealigned_in_smp;

enum hns3_udp_tnl_type {
	HNS3_UDP_TNL_VXLAN,
	HNS3_UDP_TNL_GENEVE,
	HNS3_UDP_TNL_MAX,
};

struct hns3_udp_tunnel {
	u16 dst_port;
	int used;
};

struct hns3_nic_priv {
	struct hnae3_handle *ae_handle;
	u32 enet_ver;
	u32 port_id;
	struct net_device *netdev;
	struct device *dev;

	/**
	 * the cb for nic to manage the ring buffer, the first half of the
	 * array is for tx_ring and vice versa for the second half
	 */
	struct hns3_nic_ring_data *ring_data;
	struct hns3_enet_tqp_vector *tqp_vector;
	u16 vector_num;

	/* The most recently read link state */
	int link;
	u64 tx_timeout_count;

	unsigned long state;

	struct timer_list service_timer;

	struct work_struct service_task;

	struct notifier_block notifier_block;
	/* Vxlan/Geneve information */
	struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
	struct hns3_enet_coalesce tx_coal;
	struct hns3_enet_coalesce rx_coal;
};

union l3_hdr_info {
	struct iphdr *v4;
	struct ipv6hdr *v6;
	unsigned char *hdr;
};

union l4_hdr_info {
	struct tcphdr *tcp;
	struct udphdr *udp;
	struct gre_base_hdr *gre;
	unsigned char *hdr;
};

struct hns3_hw_error_info {
	enum hnae3_hw_error_type type;
	const char *msg;
};

static inline int ring_space(struct hns3_enet_ring *ring)
{
	/* This smp_load_acquire() pairs with smp_store_release() in
	 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring.
	 */
	int begin = smp_load_acquire(&ring->next_to_clean);
	int end = READ_ONCE(ring->next_to_use);

	return ((end >= begin) ? (ring->desc_num - end + begin) :
			(begin - end)) - 1;
}

static inline int is_ring_empty(struct hns3_enet_ring *ring)
{
	return ring->next_to_use == ring->next_to_clean;
}

static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
{
	return readl(base + reg);
}

static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
{
	u8 __iomem *reg_addr = READ_ONCE(base);

	writel(value, reg_addr + reg);
}

static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev)
{
	return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET ||
			   ae_dev->reset_type == HNAE3_FLR_RESET ||
			   ae_dev->reset_type == HNAE3_VF_FUNC_RESET ||
			   ae_dev->reset_type == HNAE3_VF_FULL_RESET ||
			   ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET));
}

#define hns3_read_dev(a, reg) \
	hns3_read_reg((a)->io_base, (reg))

static inline bool hns3_nic_resetting(struct net_device *netdev)
{
	struct hns3_nic_priv *priv = netdev_priv(netdev);

	return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
}

#define hns3_write_dev(a, reg, value) \
	hns3_write_reg((a)->io_base, (reg), (value))

#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
		(tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)

#define ring_to_dev(ring) ((ring)->dev)

#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
	DMA_TO_DEVICE : DMA_FROM_DEVICE)

#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])

#define hns3_buf_size(_ring) ((_ring)->buf_size)

static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
{
#if (PAGE_SIZE < 8192)
	if (ring->buf_size > (PAGE_SIZE / 2))
		return 1;
#endif
	return 0;
}

#define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))

/* iterator for handling rings in ring group */
#define hns3_for_each_ring(pos, head) \
	for (pos = (head).ring; pos; pos = pos->next)

#define hns3_get_handle(ndev) \
	(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)

#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)

#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)

void hns3_ethtool_set_ops(struct net_device *netdev);
int hns3_set_channels(struct net_device *netdev,
		      struct ethtool_channels *ch);

void hns3_clean_tx_ring(struct hns3_enet_ring *ring);
int hns3_init_all_ring(struct hns3_nic_priv *priv);
int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
int hns3_nic_reset_all_ring(struct hnae3_handle *h);
void hns3_fini_ring(struct hns3_enet_ring *ring);
netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
bool hns3_is_phys_func(struct pci_dev *pdev);
int hns3_clean_rx_ring(
		struct hns3_enet_ring *ring, int budget,
		void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));

void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
				    u32 gl_value);
void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
				    u32 gl_value);
void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
				 u32 rl_value);

void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags);

#ifdef CONFIG_HNS3_DCB
void hns3_dcbnl_setup(struct hnae3_handle *handle);
#else
static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
#endif

void hns3_dbg_init(struct hnae3_handle *handle);
void hns3_dbg_uninit(struct hnae3_handle *handle);
void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
void hns3_dbg_unregister_debugfs(void);
#endif
Commit	Line	Data
d71d8381 JS	1	// SPDX-License-Identifier: GPL-2.0+
d71d8381 JS	2	// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e S	3
	4	#ifndef __HNS3_ENET_H
	5	#define __HNS3_ENET_H
	6
681ec399 YL	7	#include <linux/if_vlan.h>
681ec399 YL	8
76ad4f0e S	9	#include "hnae3.h"
76ad4f0e S	10
3c7624d8 XW	11	#define HNS3_MOD_VERSION "1.0"
3c7624d8 XW	12
76ad4f0e S	13	extern const char hns3_driver_version[];
	14
	15	enum hns3_nic_state {
	16	HNS3_NIC_STATE_TESTING,
	17	HNS3_NIC_STATE_RESETTING,
814da63c	18	HNS3_NIC_STATE_INITED,
76ad4f0e S	19	HNS3_NIC_STATE_DOWN,
	20	HNS3_NIC_STATE_DISABLED,
	21	HNS3_NIC_STATE_REMOVING,
	22	HNS3_NIC_STATE_SERVICE_INITED,
	23	HNS3_NIC_STATE_SERVICE_SCHED,
	24	HNS3_NIC_STATE2_RESET_REQUESTED,
	25	HNS3_NIC_STATE_MAX
	26	};
	27
	28	#define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
	29	#define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
	30	#define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
	31	#define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
	32	#define HNS3_RING_RX_RING_TAIL_REG 0x00018
	33	#define HNS3_RING_RX_RING_HEAD_REG 0x0001C
	34	#define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
	35	#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
	36
	37	#define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
	38	#define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
	39	#define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
1c772154	40	#define HNS3_RING_TX_RING_TC_REG 0x00050
76ad4f0e S	41	#define HNS3_RING_TX_RING_TAIL_REG 0x00058
	42	#define HNS3_RING_TX_RING_HEAD_REG 0x0005C
	43	#define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
	44	#define HNS3_RING_TX_RING_OFFSET_REG 0x00064
e511c97d	45	#define HNS3_RING_TX_RING_EBDNUM_REG 0x00068
76ad4f0e	46	#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
e511c97d JS	47	#define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070
e511c97d JS	48	#define HNS3_RING_TX_RING_BD_ERR_REG 0x00074
76ad4f0e S	49	#define HNS3_RING_PREFETCH_EN_REG 0x0007C
	50	#define HNS3_RING_CFG_VF_NUM_REG 0x00080
	51	#define HNS3_RING_ASID_REG 0x0008C
8df0fa91	52	#define HNS3_RING_EN_REG 0x00090
76ad4f0e S	53	#define HNS3_RING_T0_BE_RST 0x00094
	54	#define HNS3_RING_COULD_BE_RST 0x00098
	55	#define HNS3_RING_WRR_WEIGHT_REG 0x0009c
	56
	57	#define HNS3_RING_INTMSK_RXWL_REG 0x000A0
	58	#define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
	59	#define HNS3_RX_RING_INT_STS_REG 0x000A8
	60	#define HNS3_RING_INTMSK_TXWL_REG 0x000AC
	61	#define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
	62	#define HNS3_TX_RING_INT_STS_REG 0x000B4
	63	#define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
	64	#define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
	65	#define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
	66	#define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
	67
	68	#define HNS3_RING_MB_CTRL_REG 0x00100
	69	#define HNS3_RING_MB_DATA_BASE_REG 0x00200
	70
	71	#define HNS3_TX_REG_OFFSET 0x40
	72
	73	#define HNS3_RX_HEAD_SIZE 256
	74
	75	#define HNS3_TX_TIMEOUT (5 * HZ)
	76	#define HNS3_RING_NAME_LEN 16
	77	#define HNS3_BUFFER_SIZE_2048 2048
a723fb8e	78	#define HNS3_RING_MAX_PENDING 32760
c0425944	79	#define HNS3_RING_MIN_PENDING 24
5668abda	80	#define HNS3_RING_BD_MULTIPLE 8
e6d7d79d YL	81	/* max frame size of mac */
	82	#define HNS3_MAC_MAX_FRAME 9728
	83	#define HNS3_MAX_MTU \
	84	(HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
76ad4f0e S	85
	86	#define HNS3_BD_SIZE_512_TYPE 0
	87	#define HNS3_BD_SIZE_1024_TYPE 1
	88	#define HNS3_BD_SIZE_2048_TYPE 2
	89	#define HNS3_BD_SIZE_4096_TYPE 3
	90
	91	#define HNS3_RX_FLAG_VLAN_PRESENT 0x1
	92	#define HNS3_RX_FLAG_L3ID_IPV4 0x0
	93	#define HNS3_RX_FLAG_L3ID_IPV6 0x1
	94	#define HNS3_RX_FLAG_L4ID_UDP 0x0
	95	#define HNS3_RX_FLAG_L4ID_TCP 0x1
	96
	97	#define HNS3_RXD_DMAC_S 0
	98	#define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
	99	#define HNS3_RXD_VLAN_S 2
	100	#define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
	101	#define HNS3_RXD_L3ID_S 4
	102	#define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
	103	#define HNS3_RXD_L4ID_S 8
	104	#define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
	105	#define HNS3_RXD_FRAG_B 12
5b5455a9 PL	106	#define HNS3_RXD_STRP_TAGP_S 13
	107	#define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
	108
76ad4f0e S	109	#define HNS3_RXD_L2E_B 16
	110	#define HNS3_RXD_L3E_B 17
	111	#define HNS3_RXD_L4E_B 18
	112	#define HNS3_RXD_TRUNCAT_B 19
	113	#define HNS3_RXD_HOI_B 20
	114	#define HNS3_RXD_DOI_B 21
	115	#define HNS3_RXD_OL3E_B 22
	116	#define HNS3_RXD_OL4E_B 23
a6d53b97 PL	117	#define HNS3_RXD_GRO_COUNT_S 24
	118	#define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
	119	#define HNS3_RXD_GRO_FIXID_B 30
	120	#define HNS3_RXD_GRO_ECN_B 31
76ad4f0e S	121
	122	#define HNS3_RXD_ODMAC_S 0
	123	#define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
	124	#define HNS3_RXD_OVLAN_S 2
	125	#define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
	126	#define HNS3_RXD_OL3ID_S 4
	127	#define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
	128	#define HNS3_RXD_OL4ID_S 8
	129	#define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
	130	#define HNS3_RXD_FBHI_S 12
	131	#define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
	132	#define HNS3_RXD_FBLI_S 14
	133	#define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
	134
	135	#define HNS3_RXD_BDTYPE_S 0
	136	#define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
	137	#define HNS3_RXD_VLD_B 4
	138	#define HNS3_RXD_UDP0_B 5
	139	#define HNS3_RXD_EXTEND_B 7
	140	#define HNS3_RXD_FE_B 8
	141	#define HNS3_RXD_LUM_B 9
	142	#define HNS3_RXD_CRCP_B 10
	143	#define HNS3_RXD_L3L4P_B 11
	144	#define HNS3_RXD_TSIND_S 12
	145	#define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
	146	#define HNS3_RXD_LKBK_B 15
a6d53b97	147	#define HNS3_RXD_GRO_SIZE_S 16
eff858c1	148	#define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
76ad4f0e S	149
	150	#define HNS3_TXD_L3T_S 0
	151	#define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
	152	#define HNS3_TXD_L4T_S 2
	153	#define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
	154	#define HNS3_TXD_L3CS_B 4
	155	#define HNS3_TXD_L4CS_B 5
	156	#define HNS3_TXD_VLAN_B 6
	157	#define HNS3_TXD_TSO_B 7
	158
	159	#define HNS3_TXD_L2LEN_S 8
	160	#define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
	161	#define HNS3_TXD_L3LEN_S 16
	162	#define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
	163	#define HNS3_TXD_L4LEN_S 24
	164	#define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
	165
	166	#define HNS3_TXD_OL3T_S 0
	167	#define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
	168	#define HNS3_TXD_OVLAN_B 2
	169	#define HNS3_TXD_MACSEC_B 3
	170	#define HNS3_TXD_TUNTYPE_S 4
	171	#define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
	172
	173	#define HNS3_TXD_BDTYPE_S 0
	174	#define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
	175	#define HNS3_TXD_FE_B 4
	176	#define HNS3_TXD_SC_S 5
	177	#define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
	178	#define HNS3_TXD_EXTEND_B 7
	179	#define HNS3_TXD_VLD_B 8
	180	#define HNS3_TXD_RI_B 9
	181	#define HNS3_TXD_RA_B 10
	182	#define HNS3_TXD_TSYN_B 11
	183	#define HNS3_TXD_DECTTL_S 12
	184	#define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
	185
	186	#define HNS3_TXD_MSS_S 0
	187	#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
	188
3fe13ed9 YL	189	#define HNS3_TX_LAST_SIZE_M 0xffff
3fe13ed9 YL	190
76ad4f0e S	191	#define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
	192	#define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
	193
	194	#define HNS3_VECTOR_NOT_INITED 0
	195	#define HNS3_VECTOR_INITED 1
	196
	197	#define HNS3_MAX_BD_SIZE 65535
42611b70 YL	198	#define HNS3_MAX_BD_NUM_NORMAL 8
42611b70 YL	199	#define HNS3_MAX_BD_NUM_TSO 63
76ad4f0e S	200	#define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
	201
	202	#define HNS3_VECTOR_GL0_OFFSET 0x100
	203	#define HNS3_VECTOR_GL1_OFFSET 0x200
	204	#define HNS3_VECTOR_GL2_OFFSET 0x300
	205	#define HNS3_VECTOR_RL_OFFSET 0x900
	206	#define HNS3_VECTOR_RL_EN_B 6
	207
8df0fa91 HT	208	#define HNS3_RING_EN_B 0
8df0fa91 HT	209
c376fa1a JS	210	enum hns3_pkt_l2t_type {
	211	HNS3_L2_TYPE_UNICAST,
	212	HNS3_L2_TYPE_MULTICAST,
	213	HNS3_L2_TYPE_BROADCAST,
	214	HNS3_L2_TYPE_INVALID,
	215	};
	216
76ad4f0e S	217	enum hns3_pkt_l3t_type {
	218	HNS3_L3T_NONE,
	219	HNS3_L3T_IPV6,
	220	HNS3_L3T_IPV4,
	221	HNS3_L3T_RESERVED
	222	};
	223
	224	enum hns3_pkt_l4t_type {
	225	HNS3_L4T_UNKNOWN,
	226	HNS3_L4T_TCP,
	227	HNS3_L4T_UDP,
	228	HNS3_L4T_SCTP
	229	};
	230
	231	enum hns3_pkt_ol3t_type {
	232	HNS3_OL3T_NONE,
	233	HNS3_OL3T_IPV6,
	234	HNS3_OL3T_IPV4_NO_CSUM,
	235	HNS3_OL3T_IPV4_CSUM
	236	};
	237
	238	enum hns3_pkt_tun_type {
	239	HNS3_TUN_NONE,
	240	HNS3_TUN_MAC_IN_UDP,
	241	HNS3_TUN_NVGRE,
	242	HNS3_TUN_OTHER
	243	};
	244
	245	/* hardware spec ring buffer format */
	246	struct __packed hns3_desc {
	247	__le64 addr;
	248	union {
	249	struct {
	250	__le16 vlan_tag;
	251	__le16 send_size;
	252	union {
	253	__le32 type_cs_vlan_tso_len;
	254	struct {
	255	__u8 type_cs_vlan_tso;
	256	__u8 l2_len;
	257	__u8 l3_len;
	258	__u8 l4_len;
	259	};
	260	};
	261	__le16 outer_vlan_tag;
	262	__le16 tv;
	263
	264	union {
	265	__le32 ol_type_vlan_len_msec;
	266	struct {
	267	__u8 ol_type_vlan_msec;
	268	__u8 ol2_len;
	269	__u8 ol3_len;
	270	__u8 ol4_len;
	271	};
	272	};
	273
	274	__le32 paylen;
	275	__le16 bdtp_fe_sc_vld_ra_ri;
	276	__le16 mss;
	277	} tx;
	278
	279	struct {
	280	__le32 l234_info;
281	__le16 pkt_len;
282	__le16 size;
283
284	__le32 rss_hash;
285	__le16 fd_id;
286	__le16 vlan_tag;
287
288	union {
289	__le32 ol_info;
290	struct {
291	__le16 o_dm_vlan_id_fb;
292	__le16 ot_vlan_tag;
293	};
294	};
295
296	__le32 bd_base_info;
297	} rx;
298	};
299	};
300
301	struct hns3_desc_cb {
302	dma_addr_t dma; /* dma address of this desc */
303	void buf; / cpu addr for a desc */
304
46ee7350	305	/* priv data for the desc, e.g. skb when use with ip stack */
76ad4f0e	306	void *priv;
27a59593	307	u32 page_offset;
48d154e7	308	u32 length; /* length of the buffer */
76ad4f0e	309
27a59593 HT	310	u16 reuse_flag;
27a59593 HT	311
76ad4f0e S	312	/* desc type, used by the ring user to mark the type of the priv data */
	313	u16 type;
	314	};
	315
	316	enum hns3_pkt_l3type {
	317	HNS3_L3_TYPE_IPV4,
	318	HNS3_L3_TYPE_IPV6,
	319	HNS3_L3_TYPE_ARP,
	320	HNS3_L3_TYPE_RARP,
	321	HNS3_L3_TYPE_IPV4_OPT,
	322	HNS3_L3_TYPE_IPV6_EXT,
	323	HNS3_L3_TYPE_LLDP,
	324	HNS3_L3_TYPE_BPDU,
	325	HNS3_L3_TYPE_MAC_PAUSE,
	326	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
	327
46ee7350	328	/* reserved for 0xA~0xB */
76ad4f0e S	329
	330	HNS3_L3_TYPE_CNM = 0xc,
	331
46ee7350	332	/* reserved for 0xD~0xE */
76ad4f0e S	333
	334	HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
	335	};
	336
	337	enum hns3_pkt_l4type {
	338	HNS3_L4_TYPE_UDP,
	339	HNS3_L4_TYPE_TCP,
	340	HNS3_L4_TYPE_GRE,
	341	HNS3_L4_TYPE_SCTP,
	342	HNS3_L4_TYPE_IGMP,
	343	HNS3_L4_TYPE_ICMP,
	344
	345	/* reserved for 0x6~0xE */
	346
	347	HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
	348	};
	349
	350	enum hns3_pkt_ol3type {
	351	HNS3_OL3_TYPE_IPV4 = 0,
	352	HNS3_OL3_TYPE_IPV6,
	353	/* reserved for 0x2~0x3 */
	354	HNS3_OL3_TYPE_IPV4_OPT = 4,
	355	HNS3_OL3_TYPE_IPV6_EXT,
	356
46ee7350	357	/* reserved for 0x6~0xE */
76ad4f0e S	358
	359	HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
	360	};
	361
	362	enum hns3_pkt_ol4type {
	363	HNS3_OL4_TYPE_NO_TUN,
	364	HNS3_OL4_TYPE_MAC_IN_UDP,
	365	HNS3_OL4_TYPE_NVGRE,
	366	HNS3_OL4_TYPE_UNKNOWN
	367	};
	368
	369	struct ring_stats {
	370	u64 io_err_cnt;
	371	u64 sw_err_cnt;
	372	u64 seg_pkt_cnt;
	373	union {
	374	struct {
	375	u64 tx_pkts;
	376	u64 tx_bytes;
	377	u64 tx_err_cnt;
	378	u64 restart_queue;
	379	u64 tx_busy;
3d5f3741	380	u64 tx_copy;
b20d7fe5 YL	381	u64 tx_vlan_err;
	382	u64 tx_l4_proto_err;
	383	u64 tx_l2l3l4_err;
	384	u64 tx_tso_err;
76ad4f0e S	385	};
	386	struct {
	387	u64 rx_pkts;
	388	u64 rx_bytes;
	389	u64 rx_err_cnt;
	390	u64 reuse_pg_cnt;
	391	u64 err_pkt_len;
76ad4f0e S	392	u64 err_bd_num;
	393	u64 l2_err;
	394	u64 l3l4_csum_err;
c376fa1a	395	u64 rx_multicast;
d21ff4f9	396	u64 non_reuse_pg;
76ad4f0e S	397	};
	398	};
	399	};
	400
	401	struct hns3_enet_ring {
	402	u8 __iomem io_base; / base io address for the ring */
	403	struct hns3_desc desc; / dma map address space */
	404	struct hns3_desc_cb *desc_cb;
	405	struct hns3_enet_ring *next;
	406	struct hns3_enet_tqp_vector *tqp_vector;
	407	struct hnae3_queue *tqp;
76ad4f0e S	408	struct device dev; / will be used for DMA mapping of descriptors */
	409
	410	/* statistic */
	411	struct ring_stats stats;
	412	struct u64_stats_sync syncp;
	413
	414	dma_addr_t desc_dma_addr;
	415	u32 buf_size; /* size for hnae_desc->addr, preset by AE */
	416	u16 desc_num; /* total number of desc */
76ad4f0e S	417	int next_to_use; /* idx of next spare desc */
	418
	419	/* idx of lastest sent desc, the ring is empty when equal to
	420	* next_to_use
	421	*/
	422	int next_to_clean;
	423
ebaf1908	424	u32 pull_len; /* head length for current packet */
81ae0e04	425	u32 frag_num;
e5597095 PL	426	unsigned char va; / first buffer address for current packet */
e5597095 PL	427
76ad4f0e	428	u32 flag; /* ring attribute */
76ad4f0e	429
e5597095 PL	430	int pending_buf;
e5597095 PL	431	struct sk_buff *skb;
81ae0e04	432	struct sk_buff *tail_skb;
76ad4f0e S	433	};
	434
	435	struct hns_queue;
	436
	437	struct hns3_nic_ring_data {
	438	struct hns3_enet_ring *ring;
	439	struct napi_struct napi;
	440	int queue_index;
	441	int (poll_one)(struct hns3_nic_ring_data , int, void *);
	442	void (ex_process)(struct hns3_nic_ring_data , struct sk_buff *);
	443	void (fini_process)(struct hns3_nic_ring_data );
	444	};
	445
76ad4f0e S	446	enum hns3_flow_level_range {
	447	HNS3_FLOW_LOW = 0,
	448	HNS3_FLOW_MID = 1,
	449	HNS3_FLOW_HIGH = 2,
	450	HNS3_FLOW_ULTRA = 3,
	451	};
	452
434776a5	453	#define HNS3_INT_GL_MAX 0x1FE0
b81c59e1 FL	454	#define HNS3_INT_GL_50K 0x0014
	455	#define HNS3_INT_GL_20K 0x0032
	456	#define HNS3_INT_GL_18K 0x0036
	457	#define HNS3_INT_GL_8K 0x007C
76ad4f0e	458
434776a5 FL	459	#define HNS3_INT_RL_MAX 0x00EC
	460	#define HNS3_INT_RL_ENABLE_MASK 0x40
	461
9bc727a9 YL	462	struct hns3_enet_coalesce {
	463	u16 int_gl;
	464	u8 gl_adapt_enable;
	465	enum hns3_flow_level_range flow_level;
	466	};
	467
76ad4f0e S	468	struct hns3_enet_ring_group {
	469	/* array of pointers to rings */
	470	struct hns3_enet_ring *ring;
	471	u64 total_bytes; /* total bytes processed this group */
	472	u64 total_packets; /* total packets processed this group */
	473	u16 count;
9bc727a9	474	struct hns3_enet_coalesce coal;
76ad4f0e S	475	};
	476
	477	struct hns3_enet_tqp_vector {
	478	struct hnae3_handle *handle;
	479	u8 __iomem *mask_addr;
	480	int vector_irq;
	481	int irq_init_flag;
	482
	483	u16 idx; /* index in the TQP vector array per handle. */
	484
	485	struct napi_struct napi;
	486
	487	struct hns3_enet_ring_group rx_group;
	488	struct hns3_enet_ring_group tx_group;
	489
874bff0b	490	cpumask_t affinity_mask;
76ad4f0e	491	u16 num_tqps; /* total number of tqps in TQP vector */
874bff0b	492	struct irq_affinity_notify affinity_notify;
76ad4f0e	493
76ad4f0e S	494	char name[HNAE3_INT_NAME_LEN];
76ad4f0e S	495
a95e1f86	496	unsigned long last_jiffies;
76ad4f0e S	497	} ____cacheline_internodealigned_in_smp;
	498
	499	enum hns3_udp_tnl_type {
	500	HNS3_UDP_TNL_VXLAN,
	501	HNS3_UDP_TNL_GENEVE,
	502	HNS3_UDP_TNL_MAX,
	503	};
	504
	505	struct hns3_udp_tunnel {
	506	u16 dst_port;
	507	int used;
	508	};
	509
	510	struct hns3_nic_priv {
	511	struct hnae3_handle *ae_handle;
	512	u32 enet_ver;
	513	u32 port_id;
	514	struct net_device *netdev;
	515	struct device *dev;
76ad4f0e S	516
	517	/**
	518	* the cb for nic to manage the ring buffer, the first half of the
	519	* array is for tx_ring and vice versa for the second half
	520	*/
	521	struct hns3_nic_ring_data *ring_data;
	522	struct hns3_enet_tqp_vector *tqp_vector;
	523	u16 vector_num;
	524
	525	/* The most recently read link state */
	526	int link;
	527	u64 tx_timeout_count;
	528
	529	unsigned long state;
	530
	531	struct timer_list service_timer;
	532
	533	struct work_struct service_task;
	534
	535	struct notifier_block notifier_block;
	536	/* Vxlan/Geneve information */
	537	struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
e4fd7502 HT	538	struct hns3_enet_coalesce tx_coal;
e4fd7502 HT	539	struct hns3_enet_coalesce rx_coal;
76ad4f0e S	540	};
	541
	542	union l3_hdr_info {
	543	struct iphdr *v4;
	544	struct ipv6hdr *v6;
	545	unsigned char *hdr;
	546	};
	547
	548	union l4_hdr_info {
	549	struct tcphdr *tcp;
	550	struct udphdr *udp;
1a6e552d	551	struct gre_base_hdr *gre;
76ad4f0e S	552	unsigned char *hdr;
	553	};
	554
a83d2961 WL	555	struct hns3_hw_error_info {
	556	enum hnae3_hw_error_type type;
	557	const char *msg;
	558	};
	559
76ad4f0e S	560	static inline int ring_space(struct hns3_enet_ring *ring)
76ad4f0e S	561	{
26cda2f1 YL	562	/* This smp_load_acquire() pairs with smp_store_release() in
	563	* hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring.
	564	*/
	565	int begin = smp_load_acquire(&ring->next_to_clean);
	566	int end = READ_ONCE(ring->next_to_use);
0aa3d88a YL	567
	568	return ((end >= begin) ? (ring->desc_num - end + begin) :
	569	(begin - end)) - 1;
76ad4f0e S	570	}
	571
	572	static inline int is_ring_empty(struct hns3_enet_ring *ring)
	573	{
	574	return ring->next_to_use == ring->next_to_clean;
	575	}
	576
8df0fa91 HT	577	static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
	578	{
	579	return readl(base + reg);
	580	}
	581
76ad4f0e S	582	static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
	583	{
	584	u8 __iomem *reg_addr = READ_ONCE(base);
	585
	586	writel(value, reg_addr + reg);
	587	}
	588
6871af29 JS	589	static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev)
6871af29 JS	590	{
dea846e8	591	return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET \|\|
6b9a97ee	592	ae_dev->reset_type == HNAE3_FLR_RESET \|\|
aa5c4f17	593	ae_dev->reset_type == HNAE3_VF_FUNC_RESET \|\|
6b9a97ee	594	ae_dev->reset_type == HNAE3_VF_FULL_RESET \|\|
aa5c4f17	595	ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET));
6871af29 JS	596	}
6871af29 JS	597
8df0fa91 HT	598	#define hns3_read_dev(a, reg) \
	599	hns3_read_reg((a)->io_base, (reg))
	600
257e4f29 HT	601	static inline bool hns3_nic_resetting(struct net_device *netdev)
	602	{
	603	struct hns3_nic_priv *priv = netdev_priv(netdev);
	604
	605	return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
	606	}
	607
76ad4f0e S	608	#define hns3_write_dev(a, reg, value) \
	609	hns3_write_reg((a)->io_base, (reg), (value))
	610
e4e87715	611	#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
76ad4f0e S	612	(tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
76ad4f0e S	613
845e0d1d	614	#define ring_to_dev(ring) ((ring)->dev)
76ad4f0e S	615
	616	#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
	617	DMA_TO_DEVICE : DMA_FROM_DEVICE)
	618
	619	#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
	620
dbba6da0 YL	621	#define hns3_buf_size(_ring) ((_ring)->buf_size)
	622
	623	static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
	624	{
	625	#if (PAGE_SIZE < 8192)
	626	if (ring->buf_size > (PAGE_SIZE / 2))
	627	return 1;
	628	#endif
	629	return 0;
	630	}
	631
	632	#define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))
76ad4f0e S	633
	634	/* iterator for handling rings in ring group */
	635	#define hns3_for_each_ring(pos, head) \
	636	for (pos = (head).ring; pos; pos = pos->next)
	637
9780cb97 YL	638	#define hns3_get_handle(ndev) \
	639	(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
	640
434776a5 FL	641	#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
	642	#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
	643
	644	#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
	645	#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
	646
76ad4f0e	647	void hns3_ethtool_set_ops(struct net_device *netdev);
09f2af64 PL	648	int hns3_set_channels(struct net_device *netdev,
09f2af64 PL	649	struct ethtool_channels *ch);
76ad4f0e	650
799997a3	651	void hns3_clean_tx_ring(struct hns3_enet_ring *ring);
5668abda L	652	int hns3_init_all_ring(struct hns3_nic_priv *priv);
5668abda L	653	int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
7b763f3f	654	int hns3_nic_reset_all_ring(struct hnae3_handle *h);
a723fb8e	655	void hns3_fini_ring(struct hns3_enet_ring *ring);
d43e5aca	656	netdev_tx_t hns3_nic_net_xmit(struct sk_buff skb, struct net_device netdev);
97afd47b	657	bool hns3_is_phys_func(struct pci_dev *pdev);
d43e5aca YL	658	int hns3_clean_rx_ring(
	659	struct hns3_enet_ring *ring, int budget,
	660	void (rx_fn)(struct hns3_enet_ring , struct sk_buff *));
986743db	661
434776a5 FL	662	void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
	663	u32 gl_value);
	664	void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
	665	u32 gl_value);
	666	void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
	667	u32 rl_value);
	668
c60edc17	669	void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
7fa6be4f	670	int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags);
c60edc17	671
986743db YL	672	#ifdef CONFIG_HNS3_DCB
	673	void hns3_dcbnl_setup(struct hnae3_handle *handle);
	674	#else
	675	static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
	676	#endif
	677
b2292360	678	void hns3_dbg_init(struct hnae3_handle *handle);
	679	void hns3_dbg_uninit(struct hnae3_handle *handle);
	680	void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
	681	void hns3_dbg_unregister_debugfs(void);
76ad4f0e	682	#endif