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net: hns3: Add missing break in misc_irq_handle
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
76ad4f0e
S		 1/*
2 * Copyright (c) 2016~2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/dma-mapping.h>
11#include <linux/etherdevice.h>
12#include <linux/interrupt.h>
13#include <linux/if_vlan.h>
14#include <linux/ip.h>
15#include <linux/ipv6.h>
16#include <linux/module.h>
17#include <linux/pci.h>
18#include <linux/skbuff.h>
19#include <linux/sctp.h>
20#include <linux/vermagic.h>
21#include <net/gre.h>
30d240df 22#include <net/pkt_cls.h>
76ad4f0e
S		 23#include <net/vxlan.h>
24
25#include "hnae3.h"
26#include "hns3_enet.h"
27
7b763f3f
FL		 28static void hns3_clear_all_ring(struct hnae3_handle *h);
29static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
30
1db9b1bf 31static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 32const char hns3_driver_version[] = VERMAGIC_STRING;
33static const char hns3_driver_string[] =
34 "Hisilicon Ethernet Network Driver for Hip08 Family";
35static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
36static struct hnae3_client client;
37
38/* hns3_pci_tbl - PCI Device ID Table
39 *
40 * Last entry must be all 0s
41 *
42 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
43 * Class, Class Mask, private data (not used) }
44 */
45static const struct pci_device_id hns3_pci_tbl[] = {
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 53 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 54 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 55 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834
SM		 58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
59 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
76ad4f0e
S		 60 /* required last entry */
61 {0, }
62};
63MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
64
65static irqreturn_t hns3_irq_handle(int irq, void *dev)
66{
67 struct hns3_enet_tqp_vector *tqp_vector = dev;
68
69 napi_schedule(&tqp_vector->napi);
70
71 return IRQ_HANDLED;
72}
73
74static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
75{
76 struct hns3_enet_tqp_vector *tqp_vectors;
77 unsigned int i;
78
79 for (i = 0; i < priv->vector_num; i++) {
80 tqp_vectors = &priv->tqp_vector[i];
81
82 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
83 continue;
84
85 /* release the irq resource */
86 free_irq(tqp_vectors->vector_irq, tqp_vectors);
87 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
88 }
89}
90
91static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
92{
93 struct hns3_enet_tqp_vector *tqp_vectors;
94 int txrx_int_idx = 0;
95 int rx_int_idx = 0;
96 int tx_int_idx = 0;
97 unsigned int i;
98 int ret;
99
100 for (i = 0; i < priv->vector_num; i++) {
101 tqp_vectors = &priv->tqp_vector[i];
102
103 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
104 continue;
105
106 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
107 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
108 "%s-%s-%d", priv->netdev->name, "TxRx",
109 txrx_int_idx++);
110 txrx_int_idx++;
111 } else if (tqp_vectors->rx_group.ring) {
112 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
113 "%s-%s-%d", priv->netdev->name, "Rx",
114 rx_int_idx++);
115 } else if (tqp_vectors->tx_group.ring) {
116 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
117 "%s-%s-%d", priv->netdev->name, "Tx",
118 tx_int_idx++);
119 } else {
120 /* Skip this unused q_vector */
121 continue;
122 }
123
124 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
125
126 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
127 tqp_vectors->name,
128 tqp_vectors);
129 if (ret) {
130 netdev_err(priv->netdev, "request irq(%d) fail\n",
131 tqp_vectors->vector_irq);
132 return ret;
133 }
134
135 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
136 }
137
138 return 0;
139}
140
141static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
142 u32 mask_en)
143{
144 writel(mask_en, tqp_vector->mask_addr);
145}
146
147static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
148{
149 napi_enable(&tqp_vector->napi);
150
151 /* enable vector */
152 hns3_mask_vector_irq(tqp_vector, 1);
153}
154
155static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
156{
157 /* disable vector */
158 hns3_mask_vector_irq(tqp_vector, 0);
159
160 disable_irq(tqp_vector->vector_irq);
161 napi_disable(&tqp_vector->napi);
162}
163
434776a5
FL		 164void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
165 u32 rl_value)
76ad4f0e 166{
434776a5
FL		 167 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
168
76ad4f0e
S		 169 /* this defines the configuration for RL (Interrupt Rate Limiter).
170 * Rl defines rate of interrupts i.e. number of interrupts-per-second
171 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
172 */
434776a5 173
9bc727a9
YL		 174 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
175 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 176 /* According to the hardware, the range of rl_reg is
177 * 0-59 and the unit is 4.
178 */
179 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
180
181 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
182}
183
184void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
185 u32 gl_value)
186{
187 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
188
189 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
190}
191
192void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
193 u32 gl_value)
194{
195 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
196
197 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 198}
199
5fd4789a
FL		 200static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
201 struct hns3_nic_priv *priv)
76ad4f0e 202{
5fd4789a
FL		 203 struct hnae3_handle *h = priv->ae_handle;
204
76ad4f0e
S		 205 /* initialize the configuration for interrupt coalescing.
206 * 1. GL (Interrupt Gap Limiter)
207 * 2. RL (Interrupt Rate Limiter)
208 */
209
5fd4789a 210 /* Default: enable interrupt coalescing self-adaptive and GL */
9bc727a9
YL		 211 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
212 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 213
9bc727a9
YL		 214 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
215 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 216
5fd4789a
FL		 217 /* Default: disable RL */
218 h->kinfo.int_rl_setting = 0;
5fd4789a 219
cd9d187b 220 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
9bc727a9
YL		 221 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
222 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 223}
224
dd38c726
YL		 225static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
226 struct hns3_nic_priv *priv)
227{
228 struct hnae3_handle *h = priv->ae_handle;
229
230 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 231 tqp_vector->tx_group.coal.int_gl);
dd38c726 232 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 233 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 234 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
235}
236
9df8f79a
YL		 237static int hns3_nic_set_real_num_queue(struct net_device *netdev)
238{
9780cb97 239 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 240 struct hnae3_knic_private_info *kinfo = &h->kinfo;
241 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
242 int ret;
243
244 ret = netif_set_real_num_tx_queues(netdev, queue_size);
245 if (ret) {
246 netdev_err(netdev,
247 "netif_set_real_num_tx_queues fail, ret=%d!\n",
248 ret);
249 return ret;
250 }
251
252 ret = netif_set_real_num_rx_queues(netdev, queue_size);
253 if (ret) {
254 netdev_err(netdev,
255 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
256 return ret;
257 }
258
259 return 0;
260}
261
678335a1
PL		 262static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
263{
264 u16 free_tqps, max_rss_size, max_tqps;
265
266 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size);
267 max_tqps = h->kinfo.num_tc * max_rss_size;
268
269 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps));
270}
271
76ad4f0e
S		 272static int hns3_nic_net_up(struct net_device *netdev)
273{
274 struct hns3_nic_priv *priv = netdev_priv(netdev);
275 struct hnae3_handle *h = priv->ae_handle;
276 int i, j;
277 int ret;
278
7b763f3f
FL		 279 ret = hns3_nic_reset_all_ring(h);
280 if (ret)
281 return ret;
282
76ad4f0e
S		 283 /* get irq resource for all vectors */
284 ret = hns3_nic_init_irq(priv);
285 if (ret) {
286 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
287 return ret;
288 }
289
290 /* enable the vectors */
291 for (i = 0; i < priv->vector_num; i++)
292 hns3_vector_enable(&priv->tqp_vector[i]);
293
294 /* start the ae_dev */
295 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
296 if (ret)
297 goto out_start_err;
298
b875cc37
JS		 299 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
300
76ad4f0e
S		 301 return 0;
302
303out_start_err:
304 for (j = i - 1; j >= 0; j--)
305 hns3_vector_disable(&priv->tqp_vector[j]);
306
307 hns3_nic_uninit_irq(priv);
308
309 return ret;
310}
311
312static int hns3_nic_net_open(struct net_device *netdev)
313{
f8fa222c 314 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 315 int ret;
316
317 netif_carrier_off(netdev);
318
9df8f79a
YL		 319 ret = hns3_nic_set_real_num_queue(netdev);
320 if (ret)
76ad4f0e 321 return ret;
76ad4f0e
S		 322
323 ret = hns3_nic_net_up(netdev);
324 if (ret) {
325 netdev_err(netdev,
326 "hns net up fail, ret=%d!\n", ret);
327 return ret;
328 }
329
6d4c3981 330 priv->ae_handle->last_reset_time = jiffies;
76ad4f0e
S		 331 return 0;
332}
333
334static void hns3_nic_net_down(struct net_device *netdev)
335{
336 struct hns3_nic_priv *priv = netdev_priv(netdev);
337 const struct hnae3_ae_ops *ops;
338 int i;
339
b875cc37
JS		 340 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
341 return;
342
7b763f3f
FL		 343 /* disable vectors */
344 for (i = 0; i < priv->vector_num; i++)
345 hns3_vector_disable(&priv->tqp_vector[i]);
346
76ad4f0e
S		 347 /* stop ae_dev */
348 ops = priv->ae_handle->ae_algo->ops;
349 if (ops->stop)
350 ops->stop(priv->ae_handle);
351
76ad4f0e
S		 352 /* free irq resources */
353 hns3_nic_uninit_irq(priv);
7b763f3f
FL		 354
355 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 356}
357
358static int hns3_nic_net_stop(struct net_device *netdev)
359{
360 netif_tx_stop_all_queues(netdev);
361 netif_carrier_off(netdev);
362
363 hns3_nic_net_down(netdev);
364
365 return 0;
366}
367
76ad4f0e
S		 368static int hns3_nic_uc_sync(struct net_device *netdev,
369 const unsigned char *addr)
370{
9780cb97 371 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 372
373 if (h->ae_algo->ops->add_uc_addr)
374 return h->ae_algo->ops->add_uc_addr(h, addr);
375
376 return 0;
377}
378
379static int hns3_nic_uc_unsync(struct net_device *netdev,
380 const unsigned char *addr)
381{
9780cb97 382 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 383
384 if (h->ae_algo->ops->rm_uc_addr)
385 return h->ae_algo->ops->rm_uc_addr(h, addr);
386
387 return 0;
388}
389
390static int hns3_nic_mc_sync(struct net_device *netdev,
391 const unsigned char *addr)
392{
9780cb97 393 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 394
720a8478 395 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 396 return h->ae_algo->ops->add_mc_addr(h, addr);
397
398 return 0;
399}
400
401static int hns3_nic_mc_unsync(struct net_device *netdev,
402 const unsigned char *addr)
403{
9780cb97 404 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 405
720a8478 406 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 407 return h->ae_algo->ops->rm_mc_addr(h, addr);
408
409 return 0;
410}
411
1db9b1bf 412static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 413{
9780cb97 414 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 415
416 if (h->ae_algo->ops->set_promisc_mode) {
417 if (netdev->flags & IFF_PROMISC)
3b75c3df
PL		 418 h->ae_algo->ops->set_promisc_mode(h, true, true);
419 else if (netdev->flags & IFF_ALLMULTI)
420 h->ae_algo->ops->set_promisc_mode(h, false, true);
76ad4f0e 421 else
3b75c3df 422 h->ae_algo->ops->set_promisc_mode(h, false, false);
76ad4f0e
S		 423 }
424 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync))
425 netdev_err(netdev, "sync uc address fail\n");
426 if (netdev->flags & IFF_MULTICAST)
427 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync))
428 netdev_err(netdev, "sync mc address fail\n");
429}
430
431static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
432 u16 *mss, u32 *type_cs_vlan_tso)
433{
434 u32 l4_offset, hdr_len;
435 union l3_hdr_info l3;
436 union l4_hdr_info l4;
437 u32 l4_paylen;
438 int ret;
439
440 if (!skb_is_gso(skb))
441 return 0;
442
443 ret = skb_cow_head(skb, 0);
444 if (ret)
445 return ret;
446
447 l3.hdr = skb_network_header(skb);
448 l4.hdr = skb_transport_header(skb);
449
450 /* Software should clear the IPv4's checksum field when tso is
451 * needed.
452 */
453 if (l3.v4->version == 4)
454 l3.v4->check = 0;
455
456 /* tunnel packet.*/
457 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
458 SKB_GSO_GRE_CSUM |
459 SKB_GSO_UDP_TUNNEL |
460 SKB_GSO_UDP_TUNNEL_CSUM)) {
461 if ((!(skb_shinfo(skb)->gso_type &
462 SKB_GSO_PARTIAL)) &&
463 (skb_shinfo(skb)->gso_type &
464 SKB_GSO_UDP_TUNNEL_CSUM)) {
465 /* Software should clear the udp's checksum
466 * field when tso is needed.
467 */
468 l4.udp->check = 0;
469 }
470 /* reset l3&l4 pointers from outer to inner headers */
471 l3.hdr = skb_inner_network_header(skb);
472 l4.hdr = skb_inner_transport_header(skb);
473
474 /* Software should clear the IPv4's checksum field when
475 * tso is needed.
476 */
477 if (l3.v4->version == 4)
478 l3.v4->check = 0;
479 }
480
481 /* normal or tunnel packet*/
482 l4_offset = l4.hdr - skb->data;
483 hdr_len = (l4.tcp->doff * 4) + l4_offset;
484
485 /* remove payload length from inner pseudo checksum when tso*/
486 l4_paylen = skb->len - l4_offset;
487 csum_replace_by_diff(&l4.tcp->check,
488 (__force __wsum)htonl(l4_paylen));
489
490 /* find the txbd field values */
491 *paylen = skb->len - hdr_len;
492 hnae_set_bit(*type_cs_vlan_tso,
493 HNS3_TXD_TSO_B, 1);
494
495 /* get MSS for TSO */
496 *mss = skb_shinfo(skb)->gso_size;
497
498 return 0;
499}
500
1898d4e4
S		 501static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
502 u8 *il4_proto)
76ad4f0e
S		 503{
504 union {
505 struct iphdr *v4;
506 struct ipv6hdr *v6;
507 unsigned char *hdr;
508 } l3;
509 unsigned char *l4_hdr;
510 unsigned char *exthdr;
511 u8 l4_proto_tmp;
512 __be16 frag_off;
513
514 /* find outer header point */
515 l3.hdr = skb_network_header(skb);
35f58fd7 516 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 517
518 if (skb->protocol == htons(ETH_P_IPV6)) {
519 exthdr = l3.hdr + sizeof(*l3.v6);
520 l4_proto_tmp = l3.v6->nexthdr;
521 if (l4_hdr != exthdr)
522 ipv6_skip_exthdr(skb, exthdr - skb->data,
523 &l4_proto_tmp, &frag_off);
524 } else if (skb->protocol == htons(ETH_P_IP)) {
525 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 526 } else {
527 return -EINVAL;
76ad4f0e
S		 528 }
529
530 *ol4_proto = l4_proto_tmp;
531
532 /* tunnel packet */
533 if (!skb->encapsulation) {
534 *il4_proto = 0;
1898d4e4 535 return 0;
76ad4f0e
S		 536 }
537
538 /* find inner header point */
539 l3.hdr = skb_inner_network_header(skb);
540 l4_hdr = skb_inner_transport_header(skb);
541
542 if (l3.v6->version == 6) {
543 exthdr = l3.hdr + sizeof(*l3.v6);
544 l4_proto_tmp = l3.v6->nexthdr;
545 if (l4_hdr != exthdr)
546 ipv6_skip_exthdr(skb, exthdr - skb->data,
547 &l4_proto_tmp, &frag_off);
548 } else if (l3.v4->version == 4) {
549 l4_proto_tmp = l3.v4->protocol;
550 }
551
552 *il4_proto = l4_proto_tmp;
1898d4e4
S		 553
554 return 0;
76ad4f0e
S		 555}
556
557static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
558 u8 il4_proto, u32 *type_cs_vlan_tso,
559 u32 *ol_type_vlan_len_msec)
560{
561 union {
562 struct iphdr *v4;
563 struct ipv6hdr *v6;
564 unsigned char *hdr;
565 } l3;
566 union {
567 struct tcphdr *tcp;
568 struct udphdr *udp;
569 struct gre_base_hdr *gre;
570 unsigned char *hdr;
571 } l4;
572 unsigned char *l2_hdr;
573 u8 l4_proto = ol4_proto;
574 u32 ol2_len;
575 u32 ol3_len;
576 u32 ol4_len;
577 u32 l2_len;
578 u32 l3_len;
579
580 l3.hdr = skb_network_header(skb);
581 l4.hdr = skb_transport_header(skb);
582
583 /* compute L2 header size for normal packet, defined in 2 Bytes */
584 l2_len = l3.hdr - skb->data;
585 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
586 HNS3_TXD_L2LEN_S, l2_len >> 1);
587
588 /* tunnel packet*/
589 if (skb->encapsulation) {
590 /* compute OL2 header size, defined in 2 Bytes */
591 ol2_len = l2_len;
592 hnae_set_field(*ol_type_vlan_len_msec,
593 HNS3_TXD_L2LEN_M,
594 HNS3_TXD_L2LEN_S, ol2_len >> 1);
595
596 /* compute OL3 header size, defined in 4 Bytes */
597 ol3_len = l4.hdr - l3.hdr;
598 hnae_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
599 HNS3_TXD_L3LEN_S, ol3_len >> 2);
600
601 /* MAC in UDP, MAC in GRE (0x6558)*/
602 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
603 /* switch MAC header ptr from outer to inner header.*/
604 l2_hdr = skb_inner_mac_header(skb);
605
606 /* compute OL4 header size, defined in 4 Bytes. */
607 ol4_len = l2_hdr - l4.hdr;
608 hnae_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_M,
609 HNS3_TXD_L4LEN_S, ol4_len >> 2);
610
611 /* switch IP header ptr from outer to inner header */
612 l3.hdr = skb_inner_network_header(skb);
613
614 /* compute inner l2 header size, defined in 2 Bytes. */
615 l2_len = l3.hdr - l2_hdr;
616 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
617 HNS3_TXD_L2LEN_S, l2_len >> 1);
618 } else {
619 /* skb packet types not supported by hardware,
620 * txbd len fild doesn't be filled.
621 */
622 return;
623 }
624
625 /* switch L4 header pointer from outer to inner */
626 l4.hdr = skb_inner_transport_header(skb);
627
628 l4_proto = il4_proto;
629 }
630
631 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
632 l3_len = l4.hdr - l3.hdr;
633 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
634 HNS3_TXD_L3LEN_S, l3_len >> 2);
635
636 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
637 switch (l4_proto) {
638 case IPPROTO_TCP:
639 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
640 HNS3_TXD_L4LEN_S, l4.tcp->doff);
641 break;
642 case IPPROTO_SCTP:
643 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
644 HNS3_TXD_L4LEN_S, (sizeof(struct sctphdr) >> 2));
645 break;
646 case IPPROTO_UDP:
647 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
648 HNS3_TXD_L4LEN_S, (sizeof(struct udphdr) >> 2));
649 break;
650 default:
651 /* skb packet types not supported by hardware,
652 * txbd len fild doesn't be filled.
653 */
654 return;
655 }
656}
657
658static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
659 u8 il4_proto, u32 *type_cs_vlan_tso,
660 u32 *ol_type_vlan_len_msec)
661{
662 union {
663 struct iphdr *v4;
664 struct ipv6hdr *v6;
665 unsigned char *hdr;
666 } l3;
667 u32 l4_proto = ol4_proto;
668
669 l3.hdr = skb_network_header(skb);
670
671 /* define OL3 type and tunnel type(OL4).*/
672 if (skb->encapsulation) {
673 /* define outer network header type.*/
674 if (skb->protocol == htons(ETH_P_IP)) {
675 if (skb_is_gso(skb))
676 hnae_set_field(*ol_type_vlan_len_msec,
677 HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
678 HNS3_OL3T_IPV4_CSUM);
679 else
680 hnae_set_field(*ol_type_vlan_len_msec,
681 HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
682 HNS3_OL3T_IPV4_NO_CSUM);
683
684 } else if (skb->protocol == htons(ETH_P_IPV6)) {
685 hnae_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
686 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
687 }
688
689 /* define tunnel type(OL4).*/
690 switch (l4_proto) {
691 case IPPROTO_UDP:
692 hnae_set_field(*ol_type_vlan_len_msec,
693 HNS3_TXD_TUNTYPE_M,
694 HNS3_TXD_TUNTYPE_S,
695 HNS3_TUN_MAC_IN_UDP);
696 break;
697 case IPPROTO_GRE:
698 hnae_set_field(*ol_type_vlan_len_msec,
699 HNS3_TXD_TUNTYPE_M,
700 HNS3_TXD_TUNTYPE_S,
701 HNS3_TUN_NVGRE);
702 break;
703 default:
704 /* drop the skb tunnel packet if hardware don't support,
705 * because hardware can't calculate csum when TSO.
706 */
707 if (skb_is_gso(skb))
708 return -EDOM;
709
710 /* the stack computes the IP header already,
711 * driver calculate l4 checksum when not TSO.
712 */
713 skb_checksum_help(skb);
714 return 0;
715 }
716
717 l3.hdr = skb_inner_network_header(skb);
718 l4_proto = il4_proto;
719 }
720
721 if (l3.v4->version == 4) {
722 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
723 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
724
725 /* the stack computes the IP header already, the only time we
726 * need the hardware to recompute it is in the case of TSO.
727 */
728 if (skb_is_gso(skb))
729 hnae_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
730
731 hnae_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
732 } else if (l3.v6->version == 6) {
733 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
734 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
735 hnae_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
736 }
737
738 switch (l4_proto) {
739 case IPPROTO_TCP:
740 hnae_set_field(*type_cs_vlan_tso,
741 HNS3_TXD_L4T_M,
742 HNS3_TXD_L4T_S,
743 HNS3_L4T_TCP);
744 break;
745 case IPPROTO_UDP:
746 hnae_set_field(*type_cs_vlan_tso,
747 HNS3_TXD_L4T_M,
748 HNS3_TXD_L4T_S,
749 HNS3_L4T_UDP);
750 break;
751 case IPPROTO_SCTP:
752 hnae_set_field(*type_cs_vlan_tso,
753 HNS3_TXD_L4T_M,
754 HNS3_TXD_L4T_S,
755 HNS3_L4T_SCTP);
756 break;
757 default:
758 /* drop the skb tunnel packet if hardware don't support,
759 * because hardware can't calculate csum when TSO.
760 */
761 if (skb_is_gso(skb))
762 return -EDOM;
763
764 /* the stack computes the IP header already,
765 * driver calculate l4 checksum when not TSO.
766 */
767 skb_checksum_help(skb);
768 return 0;
769 }
770
771 return 0;
772}
773
774static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
775{
776 /* Config bd buffer end */
777 hnae_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
3c8f5c03 778 HNS3_TXD_BDTYPE_S, 0);
76ad4f0e
S		 779 hnae_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
780 hnae_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
7036d26f 781 hnae_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
76ad4f0e
S		 782}
783
9699cffe
PL		 784static int hns3_fill_desc_vtags(struct sk_buff *skb,
785 struct hns3_enet_ring *tx_ring,
786 u32 *inner_vlan_flag,
787 u32 *out_vlan_flag,
788 u16 *inner_vtag,
789 u16 *out_vtag)
790{
791#define HNS3_TX_VLAN_PRIO_SHIFT 13
792
793 if (skb->protocol == htons(ETH_P_8021Q) &&
794 !(tx_ring->tqp->handle->kinfo.netdev->features &
795 NETIF_F_HW_VLAN_CTAG_TX)) {
796 /* When HW VLAN acceleration is turned off, and the stack
797 * sets the protocol to 802.1q, the driver just need to
798 * set the protocol to the encapsulated ethertype.
799 */
800 skb->protocol = vlan_get_protocol(skb);
801 return 0;
802 }
803
804 if (skb_vlan_tag_present(skb)) {
805 u16 vlan_tag;
806
807 vlan_tag = skb_vlan_tag_get(skb);
808 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
809
810 /* Based on hw strategy, use out_vtag in two layer tag case,
811 * and use inner_vtag in one tag case.
812 */
813 if (skb->protocol == htons(ETH_P_8021Q)) {
814 hnae_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
815 *out_vtag = vlan_tag;
816 } else {
817 hnae_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
818 *inner_vtag = vlan_tag;
819 }
820 } else if (skb->protocol == htons(ETH_P_8021Q)) {
821 struct vlan_ethhdr *vhdr;
822 int rc;
823
824 rc = skb_cow_head(skb, 0);
825 if (rc < 0)
826 return rc;
827 vhdr = (struct vlan_ethhdr *)skb->data;
828 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
829 << HNS3_TX_VLAN_PRIO_SHIFT);
830 }
831
832 skb->protocol = vlan_get_protocol(skb);
833 return 0;
834}
835
76ad4f0e
S		 836static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
837 int size, dma_addr_t dma, int frag_end,
838 enum hns_desc_type type)
839{
840 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
841 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
842 u32 ol_type_vlan_len_msec = 0;
843 u16 bdtp_fe_sc_vld_ra_ri = 0;
844 u32 type_cs_vlan_tso = 0;
845 struct sk_buff *skb;
9699cffe
PL		 846 u16 inner_vtag = 0;
847 u16 out_vtag = 0;
76ad4f0e
S		 848 u32 paylen = 0;
849 u16 mss = 0;
850 __be16 protocol;
851 u8 ol4_proto;
852 u8 il4_proto;
853 int ret;
854
855 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
856 desc_cb->priv = priv;
857 desc_cb->length = size;
858 desc_cb->dma = dma;
859 desc_cb->type = type;
860
861 /* now, fill the descriptor */
862 desc->addr = cpu_to_le64(dma);
863 desc->tx.send_size = cpu_to_le16((u16)size);
864 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
865 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
866
867 if (type == DESC_TYPE_SKB) {
868 skb = (struct sk_buff *)priv;
a90bb9a5 869 paylen = skb->len;
76ad4f0e 870
9699cffe
PL		 871 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
872 &ol_type_vlan_len_msec,
873 &inner_vtag, &out_vtag);
874 if (unlikely(ret))
875 return ret;
876
76ad4f0e
S		 877 if (skb->ip_summed == CHECKSUM_PARTIAL) {
878 skb_reset_mac_len(skb);
879 protocol = skb->protocol;
880
1898d4e4
S		 881 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
882 if (ret)
883 return ret;
76ad4f0e
S		 884 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
885 &type_cs_vlan_tso,
886 &ol_type_vlan_len_msec);
887 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
888 &type_cs_vlan_tso,
889 &ol_type_vlan_len_msec);
890 if (ret)
891 return ret;
892
893 ret = hns3_set_tso(skb, &paylen, &mss,
894 &type_cs_vlan_tso);
895 if (ret)
896 return ret;
897 }
898
899 /* Set txbd */
900 desc->tx.ol_type_vlan_len_msec =
901 cpu_to_le32(ol_type_vlan_len_msec);
902 desc->tx.type_cs_vlan_tso_len =
903 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 904 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 905 desc->tx.mss = cpu_to_le16(mss);
9699cffe
PL		 906 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
907 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
76ad4f0e
S		 908 }
909
910 /* move ring pointer to next.*/
911 ring_ptr_move_fw(ring, next_to_use);
912
913 return 0;
914}
915
916static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv,
917 int size, dma_addr_t dma, int frag_end,
918 enum hns_desc_type type)
919{
920 unsigned int frag_buf_num;
921 unsigned int k;
922 int sizeoflast;
923 int ret;
924
925 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
926 sizeoflast = size % HNS3_MAX_BD_SIZE;
927 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
928
929 /* When the frag size is bigger than hardware, split this frag */
930 for (k = 0; k < frag_buf_num; k++) {
931 ret = hns3_fill_desc(ring, priv,
932 (k == frag_buf_num - 1) ?
933 sizeoflast : HNS3_MAX_BD_SIZE,
934 dma + HNS3_MAX_BD_SIZE * k,
935 frag_end && (k == frag_buf_num - 1) ? 1 : 0,
936 (type == DESC_TYPE_SKB && !k) ?
937 DESC_TYPE_SKB : DESC_TYPE_PAGE);
938 if (ret)
939 return ret;
940 }
941
942 return 0;
943}
944
945static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
946 struct hns3_enet_ring *ring)
947{
948 struct sk_buff *skb = *out_skb;
949 struct skb_frag_struct *frag;
950 int bdnum_for_frag;
951 int frag_num;
952 int buf_num;
953 int size;
954 int i;
955
956 size = skb_headlen(skb);
957 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
958
959 frag_num = skb_shinfo(skb)->nr_frags;
960 for (i = 0; i < frag_num; i++) {
961 frag = &skb_shinfo(skb)->frags[i];
962 size = skb_frag_size(frag);
963 bdnum_for_frag =
964 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
965 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
966 return -ENOMEM;
967
968 buf_num += bdnum_for_frag;
969 }
970
971 if (buf_num > ring_space(ring))
972 return -EBUSY;
973
974 *bnum = buf_num;
975 return 0;
976}
977
978static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
979 struct hns3_enet_ring *ring)
980{
981 struct sk_buff *skb = *out_skb;
982 int buf_num;
983
984 /* No. of segments (plus a header) */
985 buf_num = skb_shinfo(skb)->nr_frags + 1;
986
987 if (buf_num > ring_space(ring))
988 return -EBUSY;
989
990 *bnum = buf_num;
991
992 return 0;
993}
994
995static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig)
996{
997 struct device *dev = ring_to_dev(ring);
998 unsigned int i;
999
1000 for (i = 0; i < ring->desc_num; i++) {
1001 /* check if this is where we started */
1002 if (ring->next_to_use == next_to_use_orig)
1003 break;
1004
1005 /* unmap the descriptor dma address */
1006 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1007 dma_unmap_single(dev,
1008 ring->desc_cb[ring->next_to_use].dma,
1009 ring->desc_cb[ring->next_to_use].length,
1010 DMA_TO_DEVICE);
1011 else
1012 dma_unmap_page(dev,
1013 ring->desc_cb[ring->next_to_use].dma,
1014 ring->desc_cb[ring->next_to_use].length,
1015 DMA_TO_DEVICE);
1016
1017 /* rollback one */
1018 ring_ptr_move_bw(ring, next_to_use);
1019 }
1020}
1021
d43e5aca 1022netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1023{
1024 struct hns3_nic_priv *priv = netdev_priv(netdev);
1025 struct hns3_nic_ring_data *ring_data =
1026 &tx_ring_data(priv, skb->queue_mapping);
1027 struct hns3_enet_ring *ring = ring_data->ring;
1028 struct device *dev = priv->dev;
1029 struct netdev_queue *dev_queue;
1030 struct skb_frag_struct *frag;
1031 int next_to_use_head;
1032 int next_to_use_frag;
1033 dma_addr_t dma;
1034 int buf_num;
1035 int seg_num;
1036 int size;
1037 int ret;
1038 int i;
1039
1040 /* Prefetch the data used later */
1041 prefetch(skb->data);
1042
1043 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1044 case -EBUSY:
1045 u64_stats_update_begin(&ring->syncp);
1046 ring->stats.tx_busy++;
1047 u64_stats_update_end(&ring->syncp);
1048
1049 goto out_net_tx_busy;
1050 case -ENOMEM:
1051 u64_stats_update_begin(&ring->syncp);
1052 ring->stats.sw_err_cnt++;
1053 u64_stats_update_end(&ring->syncp);
1054 netdev_err(netdev, "no memory to xmit!\n");
1055
1056 goto out_err_tx_ok;
1057 default:
1058 break;
1059 }
1060
1061 /* No. of segments (plus a header) */
1062 seg_num = skb_shinfo(skb)->nr_frags + 1;
1063 /* Fill the first part */
1064 size = skb_headlen(skb);
1065
1066 next_to_use_head = ring->next_to_use;
1067
1068 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1069 if (dma_mapping_error(dev, dma)) {
1070 netdev_err(netdev, "TX head DMA map failed\n");
1071 ring->stats.sw_err_cnt++;
1072 goto out_err_tx_ok;
1073 }
1074
1075 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0,
1076 DESC_TYPE_SKB);
1077 if (ret)
1078 goto head_dma_map_err;
1079
1080 next_to_use_frag = ring->next_to_use;
1081 /* Fill the fragments */
1082 for (i = 1; i < seg_num; i++) {
1083 frag = &skb_shinfo(skb)->frags[i - 1];
1084 size = skb_frag_size(frag);
1085 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1086 if (dma_mapping_error(dev, dma)) {
1087 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i);
1088 ring->stats.sw_err_cnt++;
1089 goto frag_dma_map_err;
1090 }
1091 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma,
1092 seg_num - 1 == i ? 1 : 0,
1093 DESC_TYPE_PAGE);
1094
1095 if (ret)
1096 goto frag_dma_map_err;
1097 }
1098
1099 /* Complete translate all packets */
1100 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1101 netdev_tx_sent_queue(dev_queue, skb->len);
1102
1103 wmb(); /* Commit all data before submit */
1104
1105 hnae_queue_xmit(ring->tqp, buf_num);
1106
1107 return NETDEV_TX_OK;
1108
1109frag_dma_map_err:
1110 hns_nic_dma_unmap(ring, next_to_use_frag);
1111
1112head_dma_map_err:
1113 hns_nic_dma_unmap(ring, next_to_use_head);
1114
1115out_err_tx_ok:
1116 dev_kfree_skb_any(skb);
1117 return NETDEV_TX_OK;
1118
1119out_net_tx_busy:
1120 netif_stop_subqueue(netdev, ring_data->queue_index);
1121 smp_mb(); /* Commit all data before submit */
1122
1123 return NETDEV_TX_BUSY;
1124}
1125
1126static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1127{
9780cb97 1128 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1129 struct sockaddr *mac_addr = p;
1130 int ret;
1131
1132 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1133 return -EADDRNOTAVAIL;
1134
5ec2a51e
JS		 1135 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1136 netdev_info(netdev, "already using mac address %pM\n",
1137 mac_addr->sa_data);
1138 return 0;
1139 }
1140
59098055 1141 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1142 if (ret) {
1143 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1144 return ret;
1145 }
1146
1147 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1148
1149 return 0;
1150}
1151
1152static int hns3_nic_set_features(struct net_device *netdev,
1153 netdev_features_t features)
1154{
181d454b 1155 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1156 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1157 struct hnae3_handle *h = priv->ae_handle;
052ece6d 1158 int ret;
76ad4f0e 1159
181d454b
JS		 1160 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1161 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) {
1162 priv->ops.fill_desc = hns3_fill_desc_tso;
1163 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1164 } else {
1165 priv->ops.fill_desc = hns3_fill_desc;
1166 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1167 }
76ad4f0e
S		 1168 }
1169
bd368416
JS		 1170 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1171 h->ae_algo->ops->enable_vlan_filter) {
181d454b
JS		 1172 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1173 h->ae_algo->ops->enable_vlan_filter(h, true);
1174 else
1175 h->ae_algo->ops->enable_vlan_filter(h, false);
1176 }
391b5e93 1177
bd368416
JS		 1178 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1179 h->ae_algo->ops->enable_hw_strip_rxvtag) {
052ece6d
PL		 1180 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1181 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1182 else
1183 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1184
1185 if (ret)
1186 return ret;
1187 }
1188
76ad4f0e
S		 1189 netdev->features = features;
1190 return 0;
1191}
1192
6c88d9d7
PL		 1193static void hns3_nic_get_stats64(struct net_device *netdev,
1194 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1195{
1196 struct hns3_nic_priv *priv = netdev_priv(netdev);
1197 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1198 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e
S		 1199 struct hns3_enet_ring *ring;
1200 unsigned int start;
1201 unsigned int idx;
1202 u64 tx_bytes = 0;
1203 u64 rx_bytes = 0;
1204 u64 tx_pkts = 0;
1205 u64 rx_pkts = 0;
d2a5dca8
JS		 1206 u64 tx_drop = 0;
1207 u64 rx_drop = 0;
76ad4f0e 1208
b875cc37
JS		 1209 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1210 return;
1211
c5f65480
JS		 1212 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1213
76ad4f0e
S		 1214 for (idx = 0; idx < queue_num; idx++) {
1215 /* fetch the tx stats */
1216 ring = priv->ring_data[idx].ring;
1217 do {
d36d36ce 1218 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1219 tx_bytes += ring->stats.tx_bytes;
1220 tx_pkts += ring->stats.tx_pkts;
d2a5dca8
JS		 1221 tx_drop += ring->stats.tx_busy;
1222 tx_drop += ring->stats.sw_err_cnt;
76ad4f0e
S		 1223 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1224
1225 /* fetch the rx stats */
1226 ring = priv->ring_data[idx + queue_num].ring;
1227 do {
d36d36ce 1228 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1229 rx_bytes += ring->stats.rx_bytes;
1230 rx_pkts += ring->stats.rx_pkts;
d2a5dca8
JS		 1231 rx_drop += ring->stats.non_vld_descs;
1232 rx_drop += ring->stats.err_pkt_len;
1233 rx_drop += ring->stats.l2_err;
76ad4f0e
S		 1234 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1235 }
1236
1237 stats->tx_bytes = tx_bytes;
1238 stats->tx_packets = tx_pkts;
1239 stats->rx_bytes = rx_bytes;
1240 stats->rx_packets = rx_pkts;
1241
1242 stats->rx_errors = netdev->stats.rx_errors;
1243 stats->multicast = netdev->stats.multicast;
1244 stats->rx_length_errors = netdev->stats.rx_length_errors;
1245 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1246 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1247
1248 stats->tx_errors = netdev->stats.tx_errors;
d2a5dca8
JS		 1249 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1250 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
76ad4f0e
S		 1251 stats->collisions = netdev->stats.collisions;
1252 stats->rx_over_errors = netdev->stats.rx_over_errors;
1253 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1254 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1255 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1256 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1257 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1258 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1259 stats->tx_window_errors = netdev->stats.tx_window_errors;
1260 stats->rx_compressed = netdev->stats.rx_compressed;
1261 stats->tx_compressed = netdev->stats.tx_compressed;
1262}
1263
30d240df 1264static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1265{
30d240df 1266 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1267 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1268 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1269 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1270 u8 tc = mqprio_qopt->qopt.num_tc;
1271 u16 mode = mqprio_qopt->mode;
1272 u8 hw = mqprio_qopt->qopt.hw;
1273 bool if_running;
76ad4f0e
S		 1274 unsigned int i;
1275 int ret;
1276
30d240df
YL		 1277 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1278 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1279 return -EOPNOTSUPP;
1280
76ad4f0e
S		 1281 if (tc > HNAE3_MAX_TC)
1282 return -EINVAL;
1283
76ad4f0e
S		 1284 if (!netdev)
1285 return -EINVAL;
1286
30d240df
YL		 1287 if_running = netif_running(netdev);
1288 if (if_running) {
1289 hns3_nic_net_stop(netdev);
1290 msleep(100);
76ad4f0e
S		 1291 }
1292
30d240df
YL		 1293 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1294 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e 1295 if (ret)
30d240df
YL		 1296 goto out;
1297
1298 if (tc <= 1) {
1299 netdev_reset_tc(netdev);
1300 } else {
1301 ret = netdev_set_num_tc(netdev, tc);
1302 if (ret)
1303 goto out;
1304
1305 for (i = 0; i < HNAE3_MAX_TC; i++) {
1306 if (!kinfo->tc_info[i].enable)
1307 continue;
76ad4f0e 1308
76ad4f0e
S		 1309 netdev_set_tc_queue(netdev,
1310 kinfo->tc_info[i].tc,
1311 kinfo->tc_info[i].tqp_count,
1312 kinfo->tc_info[i].tqp_offset);
30d240df 1313 }
76ad4f0e
S		 1314 }
1315
30d240df
YL		 1316 ret = hns3_nic_set_real_num_queue(netdev);
1317
1318out:
1319 if (if_running)
1320 hns3_nic_net_open(netdev);
1321
1322 return ret;
76ad4f0e
S		 1323}
1324
2572ac53 1325static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1326 void *type_data)
76ad4f0e 1327{
575ed7d3 1328 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1329 return -EOPNOTSUPP;
76ad4f0e 1330
30d240df 1331 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1332}
1333
1334static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1335 __be16 proto, u16 vid)
1336{
9780cb97 1337 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1338 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1339 int ret = -EIO;
1340
1341 if (h->ae_algo->ops->set_vlan_filter)
1342 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1343
681ec399
YL		 1344 if (!ret)
1345 set_bit(vid, priv->active_vlans);
1346
76ad4f0e
S		 1347 return ret;
1348}
1349
1350static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1351 __be16 proto, u16 vid)
1352{
9780cb97 1353 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1354 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1355 int ret = -EIO;
1356
1357 if (h->ae_algo->ops->set_vlan_filter)
1358 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1359
681ec399
YL		 1360 if (!ret)
1361 clear_bit(vid, priv->active_vlans);
1362
76ad4f0e
S		 1363 return ret;
1364}
1365
681ec399
YL		 1366static void hns3_restore_vlan(struct net_device *netdev)
1367{
1368 struct hns3_nic_priv *priv = netdev_priv(netdev);
1369 u16 vid;
1370 int ret;
1371
1372 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1373 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1374 if (ret)
1375 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n",
1376 vid, ret);
1377 }
1378}
1379
76ad4f0e
S		 1380static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1381 u8 qos, __be16 vlan_proto)
1382{
9780cb97 1383 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1384 int ret = -EIO;
1385
1386 if (h->ae_algo->ops->set_vf_vlan_filter)
1387 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1388 qos, vlan_proto);
1389
1390 return ret;
1391}
1392
a8e8b7ff
S		 1393static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1394{
9780cb97 1395 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1396 bool if_running = netif_running(netdev);
1397 int ret;
1398
1399 if (!h->ae_algo->ops->set_mtu)
1400 return -EOPNOTSUPP;
1401
1402 /* if this was called with netdev up then bring netdevice down */
1403 if (if_running) {
1404 (void)hns3_nic_net_stop(netdev);
1405 msleep(100);
1406 }
1407
1408 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1409 if (ret) {
1410 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1411 ret);
1412 return ret;
1413 }
1414
5bad95a1
FL		 1415 netdev->mtu = new_mtu;
1416
a8e8b7ff
S		 1417 /* if the netdev was running earlier, bring it up again */
1418 if (if_running && hns3_nic_net_open(netdev))
1419 ret = -EINVAL;
1420
1421 return ret;
1422}
1423
f8fa222c
L		 1424static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1425{
1426 struct hns3_nic_priv *priv = netdev_priv(ndev);
1427 struct hns3_enet_ring *tx_ring = NULL;
1428 int timeout_queue = 0;
1429 int hw_head, hw_tail;
1430 int i;
1431
1432 /* Find the stopped queue the same way the stack does */
1433 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1434 struct netdev_queue *q;
1435 unsigned long trans_start;
1436
1437 q = netdev_get_tx_queue(ndev, i);
1438 trans_start = q->trans_start;
1439 if (netif_xmit_stopped(q) &&
1440 time_after(jiffies,
1441 (trans_start + ndev->watchdog_timeo))) {
1442 timeout_queue = i;
1443 break;
1444 }
1445 }
1446
1447 if (i == ndev->num_tx_queues) {
1448 netdev_info(ndev,
1449 "no netdev TX timeout queue found, timeout count: %llu\n",
1450 priv->tx_timeout_count);
1451 return false;
1452 }
1453
1454 tx_ring = priv->ring_data[timeout_queue].ring;
1455
1456 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1457 HNS3_RING_TX_RING_HEAD_REG);
1458 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1459 HNS3_RING_TX_RING_TAIL_REG);
1460 netdev_info(ndev,
1461 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1462 priv->tx_timeout_count,
1463 timeout_queue,
1464 tx_ring->next_to_use,
1465 tx_ring->next_to_clean,
1466 hw_head,
1467 hw_tail,
1468 readl(tx_ring->tqp_vector->mask_addr));
1469
1470 return true;
1471}
1472
1473static void hns3_nic_net_timeout(struct net_device *ndev)
1474{
1475 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1476 struct hnae3_handle *h = priv->ae_handle;
1477
1478 if (!hns3_get_tx_timeo_queue_info(ndev))
1479 return;
1480
1481 priv->tx_timeout_count++;
1482
6d4c3981 1483 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo)))
f8fa222c
L		 1484 return;
1485
6d4c3981 1486 /* request the reset */
f8fa222c 1487 if (h->ae_algo->ops->reset_event)
6d4c3981 1488 h->ae_algo->ops->reset_event(h);
f8fa222c
L		 1489}
1490
76ad4f0e
S		 1491static const struct net_device_ops hns3_nic_netdev_ops = {
1492 .ndo_open = hns3_nic_net_open,
1493 .ndo_stop = hns3_nic_net_stop,
1494 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1495 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1496 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
a8e8b7ff 1497 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1498 .ndo_set_features = hns3_nic_set_features,
1499 .ndo_get_stats64 = hns3_nic_get_stats64,
1500 .ndo_setup_tc = hns3_nic_setup_tc,
1501 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1502 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1503 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1504 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1505};
1506
2312e050
FL		 1507static bool hns3_is_phys_func(struct pci_dev *pdev)
1508{
1509 u32 dev_id = pdev->device;
1510
1511 switch (dev_id) {
1512 case HNAE3_DEV_ID_GE:
1513 case HNAE3_DEV_ID_25GE:
1514 case HNAE3_DEV_ID_25GE_RDMA:
1515 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1516 case HNAE3_DEV_ID_50GE_RDMA:
1517 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1518 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1519 return true;
1520 case HNAE3_DEV_ID_100G_VF:
1521 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1522 return false;
1523 default:
1524 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1525 dev_id);
1526 }
1527
1528 return false;
1529}
1530
2312e050
FL		 1531static void hns3_disable_sriov(struct pci_dev *pdev)
1532{
1533 /* If our VFs are assigned we cannot shut down SR-IOV
1534 * without causing issues, so just leave the hardware
1535 * available but disabled
1536 */
1537 if (pci_vfs_assigned(pdev)) {
1538 dev_warn(&pdev->dev,
1539 "disabling driver while VFs are assigned\n");
1540 return;
1541 }
1542
1543 pci_disable_sriov(pdev);
1544}
1545
76ad4f0e
S		 1546/* hns3_probe - Device initialization routine
1547 * @pdev: PCI device information struct
1548 * @ent: entry in hns3_pci_tbl
1549 *
1550 * hns3_probe initializes a PF identified by a pci_dev structure.
1551 * The OS initialization, configuring of the PF private structure,
1552 * and a hardware reset occur.
1553 *
1554 * Returns 0 on success, negative on failure
1555 */
1556static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1557{
1558 struct hnae3_ae_dev *ae_dev;
1559 int ret;
1560
1561 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1562 GFP_KERNEL);
1563 if (!ae_dev) {
1564 ret = -ENOMEM;
1565 return ret;
1566 }
1567
1568 ae_dev->pdev = pdev;
e92a0843 1569 ae_dev->flag = ent->driver_data;
76ad4f0e
S		 1570 ae_dev->dev_type = HNAE3_DEV_KNIC;
1571 pci_set_drvdata(pdev, ae_dev);
1572
50fbc237 1573 hnae3_register_ae_dev(ae_dev);
2312e050 1574
2312e050 1575 return 0;
76ad4f0e
S		 1576}
1577
1578/* hns3_remove - Device removal routine
1579 * @pdev: PCI device information struct
1580 */
1581static void hns3_remove(struct pci_dev *pdev)
1582{
1583 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1584
2312e050
FL		 1585 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1586 hns3_disable_sriov(pdev);
1587
76ad4f0e 1588 hnae3_unregister_ae_dev(ae_dev);
76ad4f0e
S		 1589}
1590
fa8d82e8
PL		 1591/**
1592 * hns3_pci_sriov_configure
1593 * @pdev: pointer to a pci_dev structure
1594 * @num_vfs: number of VFs to allocate
1595 *
1596 * Enable or change the number of VFs. Called when the user updates the number
1597 * of VFs in sysfs.
1598 **/
743e1a84 1599static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 1600{
1601 int ret;
1602
1603 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1604 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1605 return -EINVAL;
1606 }
1607
1608 if (num_vfs) {
1609 ret = pci_enable_sriov(pdev, num_vfs);
1610 if (ret)
1611 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 1612 else
1613 return num_vfs;
fa8d82e8
PL		 1614 } else if (!pci_vfs_assigned(pdev)) {
1615 pci_disable_sriov(pdev);
1616 } else {
1617 dev_warn(&pdev->dev,
1618 "Unable to free VFs because some are assigned to VMs.\n");
1619 }
1620
1621 return 0;
1622}
1623
76ad4f0e
S		 1624static struct pci_driver hns3_driver = {
1625 .name = hns3_driver_name,
1626 .id_table = hns3_pci_tbl,
1627 .probe = hns3_probe,
1628 .remove = hns3_remove,
fa8d82e8 1629 .sriov_configure = hns3_pci_sriov_configure,
76ad4f0e
S		 1630};
1631
1632/* set default feature to hns3 */
1633static void hns3_set_default_feature(struct net_device *netdev)
1634{
1635 netdev->priv_flags |= IFF_UNICAST_FLT;
1636
1637 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1638 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1639 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1640 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1641 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1642
1643 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1644
1645 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1646
1647 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1648 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 1649 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1650 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1651 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1652 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1653 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1654
1655 netdev->vlan_features |=
1656 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1657 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1658 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1659 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1660 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1661
1662 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 1663 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1664 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1665 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1666 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1667 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1668}
1669
1670static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1671 struct hns3_desc_cb *cb)
1672{
1673 unsigned int order = hnae_page_order(ring);
1674 struct page *p;
1675
1676 p = dev_alloc_pages(order);
1677 if (!p)
1678 return -ENOMEM;
1679
1680 cb->priv = p;
1681 cb->page_offset = 0;
1682 cb->reuse_flag = 0;
1683 cb->buf = page_address(p);
1684 cb->length = hnae_page_size(ring);
1685 cb->type = DESC_TYPE_PAGE;
1686
76ad4f0e
S		 1687 return 0;
1688}
1689
1690static void hns3_free_buffer(struct hns3_enet_ring *ring,
1691 struct hns3_desc_cb *cb)
1692{
1693 if (cb->type == DESC_TYPE_SKB)
1694 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1695 else if (!HNAE3_IS_TX_RING(ring))
1696 put_page((struct page *)cb->priv);
1697 memset(cb, 0, sizeof(*cb));
1698}
1699
1700static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1701{
1702 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1703 cb->length, ring_to_dma_dir(ring));
1704
1705 if (dma_mapping_error(ring_to_dev(ring), cb->dma))
1706 return -EIO;
1707
1708 return 0;
1709}
1710
1711static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1712 struct hns3_desc_cb *cb)
1713{
1714 if (cb->type == DESC_TYPE_SKB)
1715 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1716 ring_to_dma_dir(ring));
1717 else
1718 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1719 ring_to_dma_dir(ring));
1720}
1721
1722static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1723{
1724 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1725 ring->desc[i].addr = 0;
1726}
1727
1728static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
1729{
1730 struct hns3_desc_cb *cb = &ring->desc_cb[i];
1731
1732 if (!ring->desc_cb[i].dma)
1733 return;
1734
1735 hns3_buffer_detach(ring, i);
1736 hns3_free_buffer(ring, cb);
1737}
1738
1739static void hns3_free_buffers(struct hns3_enet_ring *ring)
1740{
1741 int i;
1742
1743 for (i = 0; i < ring->desc_num; i++)
1744 hns3_free_buffer_detach(ring, i);
1745}
1746
1747/* free desc along with its attached buffer */
1748static void hns3_free_desc(struct hns3_enet_ring *ring)
1749{
1750 hns3_free_buffers(ring);
1751
1752 dma_unmap_single(ring_to_dev(ring), ring->desc_dma_addr,
1753 ring->desc_num * sizeof(ring->desc[0]),
1754 DMA_BIDIRECTIONAL);
1755 ring->desc_dma_addr = 0;
1756 kfree(ring->desc);
1757 ring->desc = NULL;
1758}
1759
1760static int hns3_alloc_desc(struct hns3_enet_ring *ring)
1761{
1762 int size = ring->desc_num * sizeof(ring->desc[0]);
1763
1764 ring->desc = kzalloc(size, GFP_KERNEL);
1765 if (!ring->desc)
1766 return -ENOMEM;
1767
1768 ring->desc_dma_addr = dma_map_single(ring_to_dev(ring), ring->desc,
1769 size, DMA_BIDIRECTIONAL);
1770 if (dma_mapping_error(ring_to_dev(ring), ring->desc_dma_addr)) {
1771 ring->desc_dma_addr = 0;
1772 kfree(ring->desc);
1773 ring->desc = NULL;
1774 return -ENOMEM;
1775 }
1776
1777 return 0;
1778}
1779
1780static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
1781 struct hns3_desc_cb *cb)
1782{
1783 int ret;
1784
1785 ret = hns3_alloc_buffer(ring, cb);
1786 if (ret)
1787 goto out;
1788
1789 ret = hns3_map_buffer(ring, cb);
1790 if (ret)
1791 goto out_with_buf;
1792
1793 return 0;
1794
1795out_with_buf:
564883bb 1796 hns3_free_buffer(ring, cb);
76ad4f0e
S		 1797out:
1798 return ret;
1799}
1800
1801static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
1802{
1803 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
1804
1805 if (ret)
1806 return ret;
1807
1808 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1809
1810 return 0;
1811}
1812
1813/* Allocate memory for raw pkg, and map with dma */
1814static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
1815{
1816 int i, j, ret;
1817
1818 for (i = 0; i < ring->desc_num; i++) {
1819 ret = hns3_alloc_buffer_attach(ring, i);
1820 if (ret)
1821 goto out_buffer_fail;
1822 }
1823
1824 return 0;
1825
1826out_buffer_fail:
1827 for (j = i - 1; j >= 0; j--)
1828 hns3_free_buffer_detach(ring, j);
1829 return ret;
1830}
1831
1832/* detach a in-used buffer and replace with a reserved one */
1833static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
1834 struct hns3_desc_cb *res_cb)
1835{
b9077428 1836 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 1837 ring->desc_cb[i] = *res_cb;
1838 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 1839 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 1840}
1841
1842static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
1843{
1844 ring->desc_cb[i].reuse_flag = 0;
1845 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
1846 + ring->desc_cb[i].page_offset);
7d0b130c 1847 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 1848}
1849
1850static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
1851 int *pkts)
1852{
1853 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
1854
1855 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
1856 (*bytes) += desc_cb->length;
1857 /* desc_cb will be cleaned, after hnae_free_buffer_detach*/
1858 hns3_free_buffer_detach(ring, ring->next_to_clean);
1859
1860 ring_ptr_move_fw(ring, next_to_clean);
1861}
1862
1863static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
1864{
1865 int u = ring->next_to_use;
1866 int c = ring->next_to_clean;
1867
1868 if (unlikely(h > ring->desc_num))
1869 return 0;
1870
1871 return u > c ? (h > c && h <= u) : (h > c || h <= u);
1872}
1873
24e750c4 1874bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
76ad4f0e
S		 1875{
1876 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
1877 struct netdev_queue *dev_queue;
1878 int bytes, pkts;
1879 int head;
1880
1881 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
1882 rmb(); /* Make sure head is ready before touch any data */
1883
1884 if (is_ring_empty(ring) || head == ring->next_to_clean)
24e750c4 1885 return true; /* no data to poll */
76ad4f0e
S		 1886
1887 if (!is_valid_clean_head(ring, head)) {
1888 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
1889 ring->next_to_use, ring->next_to_clean);
1890
1891 u64_stats_update_begin(&ring->syncp);
1892 ring->stats.io_err_cnt++;
1893 u64_stats_update_end(&ring->syncp);
24e750c4 1894 return true;
76ad4f0e
S		 1895 }
1896
1897 bytes = 0;
1898 pkts = 0;
1899 while (head != ring->next_to_clean && budget) {
1900 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
1901 /* Issue prefetch for next Tx descriptor */
1902 prefetch(&ring->desc_cb[ring->next_to_clean]);
1903 budget--;
1904 }
1905
1906 ring->tqp_vector->tx_group.total_bytes += bytes;
1907 ring->tqp_vector->tx_group.total_packets += pkts;
1908
1909 u64_stats_update_begin(&ring->syncp);
1910 ring->stats.tx_bytes += bytes;
1911 ring->stats.tx_pkts += pkts;
1912 u64_stats_update_end(&ring->syncp);
1913
1914 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
1915 netdev_tx_completed_queue(dev_queue, pkts, bytes);
1916
1917 if (unlikely(pkts && netif_carrier_ok(netdev) &&
1918 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
1919 /* Make sure that anybody stopping the queue after this
1920 * sees the new next_to_clean.
1921 */
1922 smp_mb();
1923 if (netif_tx_queue_stopped(dev_queue)) {
1924 netif_tx_wake_queue(dev_queue);
1925 ring->stats.restart_queue++;
1926 }
1927 }
1928
1929 return !!budget;
1930}
1931
1932static int hns3_desc_unused(struct hns3_enet_ring *ring)
1933{
1934 int ntc = ring->next_to_clean;
1935 int ntu = ring->next_to_use;
1936
1937 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
1938}
1939
1940static void
1941hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
1942{
1943 struct hns3_desc_cb *desc_cb;
1944 struct hns3_desc_cb res_cbs;
1945 int i, ret;
1946
1947 for (i = 0; i < cleand_count; i++) {
1948 desc_cb = &ring->desc_cb[ring->next_to_use];
1949 if (desc_cb->reuse_flag) {
1950 u64_stats_update_begin(&ring->syncp);
1951 ring->stats.reuse_pg_cnt++;
1952 u64_stats_update_end(&ring->syncp);
1953
1954 hns3_reuse_buffer(ring, ring->next_to_use);
1955 } else {
1956 ret = hns3_reserve_buffer_map(ring, &res_cbs);
1957 if (ret) {
1958 u64_stats_update_begin(&ring->syncp);
1959 ring->stats.sw_err_cnt++;
1960 u64_stats_update_end(&ring->syncp);
1961
1962 netdev_err(ring->tqp->handle->kinfo.netdev,
1963 "hnae reserve buffer map failed.\n");
1964 break;
1965 }
1966 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
1967 }
1968
1969 ring_ptr_move_fw(ring, next_to_use);
1970 }
1971
1972 wmb(); /* Make all data has been write before submit */
1973 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
1974}
1975
76ad4f0e
S		 1976static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
1977 struct hns3_enet_ring *ring, int pull_len,
1978 struct hns3_desc_cb *desc_cb)
1979{
1980 struct hns3_desc *desc;
1981 int truesize, size;
1982 int last_offset;
1983 bool twobufs;
1984
1985 twobufs = ((PAGE_SIZE < 8192) &&
1986 hnae_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
1987
1988 desc = &ring->desc[ring->next_to_clean];
1989 size = le16_to_cpu(desc->rx.size);
1990
f8d291f0
PL		 1991 truesize = hnae_buf_size(ring);
1992
1993 if (!twobufs)
76ad4f0e 1994 last_offset = hnae_page_size(ring) - hnae_buf_size(ring);
76ad4f0e
S		 1995
1996 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 1997 size - pull_len, truesize);
76ad4f0e
S		 1998
1999 /* Avoid re-using remote pages,flag default unreuse */
2000 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2001 return;
2002
2003 if (twobufs) {
2004 /* If we are only owner of page we can reuse it */
2005 if (likely(page_count(desc_cb->priv) == 1)) {
2006 /* Flip page offset to other buffer */
2007 desc_cb->page_offset ^= truesize;
2008
2009 desc_cb->reuse_flag = 1;
2010 /* bump ref count on page before it is given*/
2011 get_page(desc_cb->priv);
2012 }
2013 return;
2014 }
2015
2016 /* Move offset up to the next cache line */
2017 desc_cb->page_offset += truesize;
2018
2019 if (desc_cb->page_offset <= last_offset) {
2020 desc_cb->reuse_flag = 1;
2021 /* Bump ref count on page before it is given*/
2022 get_page(desc_cb->priv);
2023 }
2024}
2025
2026static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2027 struct hns3_desc *desc)
2028{
2029 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2030 int l3_type, l4_type;
2031 u32 bd_base_info;
2032 int ol4_type;
2033 u32 l234info;
2034
2035 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2036 l234info = le32_to_cpu(desc->rx.l234_info);
2037
2038 skb->ip_summed = CHECKSUM_NONE;
2039
2040 skb_checksum_none_assert(skb);
2041
2042 if (!(netdev->features & NETIF_F_RXCSUM))
2043 return;
2044
2045 /* check if hardware has done checksum */
2046 if (!hnae_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
2047 return;
2048
2049 if (unlikely(hnae_get_bit(l234info, HNS3_RXD_L3E_B) ||
2050 hnae_get_bit(l234info, HNS3_RXD_L4E_B) ||
2051 hnae_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2052 hnae_get_bit(l234info, HNS3_RXD_OL4E_B))) {
2053 netdev_err(netdev, "L3/L4 error pkt\n");
2054 u64_stats_update_begin(&ring->syncp);
2055 ring->stats.l3l4_csum_err++;
2056 u64_stats_update_end(&ring->syncp);
2057
2058 return;
2059 }
2060
2061 l3_type = hnae_get_field(l234info, HNS3_RXD_L3ID_M,
2062 HNS3_RXD_L3ID_S);
2063 l4_type = hnae_get_field(l234info, HNS3_RXD_L4ID_M,
2064 HNS3_RXD_L4ID_S);
2065
2066 ol4_type = hnae_get_field(l234info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
2067 switch (ol4_type) {
2068 case HNS3_OL4_TYPE_MAC_IN_UDP:
2069 case HNS3_OL4_TYPE_NVGRE:
2070 skb->csum_level = 1;
2071 case HNS3_OL4_TYPE_NO_TUN:
2072 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2073 if (l3_type == HNS3_L3_TYPE_IPV4 ||
2074 (l3_type == HNS3_L3_TYPE_IPV6 &&
2075 (l4_type == HNS3_L4_TYPE_UDP ||
2076 l4_type == HNS3_L4_TYPE_TCP ||
2077 l4_type == HNS3_L4_TYPE_SCTP)))
2078 skb->ip_summed = CHECKSUM_UNNECESSARY;
2079 break;
2080 }
2081}
2082
d43e5aca
YL		 2083static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2084{
2085 napi_gro_receive(&ring->tqp_vector->napi, skb);
2086}
2087
5b5455a9
PL		 2088static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2089 struct hns3_desc *desc, u32 l234info)
2090{
2091 struct pci_dev *pdev = ring->tqp->handle->pdev;
2092 u16 vlan_tag;
2093
2094 if (pdev->revision == 0x20) {
2095 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2096 if (!(vlan_tag & VLAN_VID_MASK))
2097 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2098
2099 return vlan_tag;
2100 }
2101
2102#define HNS3_STRP_OUTER_VLAN 0x1
2103#define HNS3_STRP_INNER_VLAN 0x2
2104
2105 switch (hnae_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2106 HNS3_RXD_STRP_TAGP_S)) {
2107 case HNS3_STRP_OUTER_VLAN:
2108 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2109 break;
2110 case HNS3_STRP_INNER_VLAN:
2111 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2112 break;
2113 default:
2114 vlan_tag = 0;
2115 break;
2116 }
2117
2118 return vlan_tag;
2119}
2120
76ad4f0e
S		 2121static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2122 struct sk_buff **out_skb, int *out_bnum)
2123{
2124 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2125 struct hns3_desc_cb *desc_cb;
2126 struct hns3_desc *desc;
2127 struct sk_buff *skb;
2128 unsigned char *va;
2129 u32 bd_base_info;
2130 int pull_len;
2131 u32 l234info;
2132 int length;
2133 int bnum;
2134
2135 desc = &ring->desc[ring->next_to_clean];
2136 desc_cb = &ring->desc_cb[ring->next_to_clean];
2137
2138 prefetch(desc);
2139
846fcc83 2140 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2141 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2142
2143 /* Check valid BD */
2144 if (!hnae_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2145 return -EFAULT;
2146
2147 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2148
2149 /* Prefetch first cache line of first page
2150 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2151 * line size is 64B so need to prefetch twice to make it 128B. But in
2152 * actual we can have greater size of caches with 128B Level 1 cache
2153 * lines. In such a case, single fetch would suffice to cache in the
2154 * relevant part of the header.
2155 */
2156 prefetch(va);
2157#if L1_CACHE_BYTES < 128
2158 prefetch(va + L1_CACHE_BYTES);
2159#endif
2160
2161 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2162 HNS3_RX_HEAD_SIZE);
2163 if (unlikely(!skb)) {
2164 netdev_err(netdev, "alloc rx skb fail\n");
2165
2166 u64_stats_update_begin(&ring->syncp);
2167 ring->stats.sw_err_cnt++;
2168 u64_stats_update_end(&ring->syncp);
2169
2170 return -ENOMEM;
2171 }
2172
2173 prefetchw(skb->data);
2174
2175 bnum = 1;
2176 if (length <= HNS3_RX_HEAD_SIZE) {
2177 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2178
2179 /* We can reuse buffer as-is, just make sure it is local */
2180 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2181 desc_cb->reuse_flag = 1;
2182 else /* This page cannot be reused so discard it */
2183 put_page(desc_cb->priv);
2184
2185 ring_ptr_move_fw(ring, next_to_clean);
2186 } else {
2187 u64_stats_update_begin(&ring->syncp);
2188 ring->stats.seg_pkt_cnt++;
2189 u64_stats_update_end(&ring->syncp);
2190
e63cd65f
PL		 2191 pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2192
76ad4f0e
S		 2193 memcpy(__skb_put(skb, pull_len), va,
2194 ALIGN(pull_len, sizeof(long)));
2195
2196 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb);
2197 ring_ptr_move_fw(ring, next_to_clean);
2198
2199 while (!hnae_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2200 desc = &ring->desc[ring->next_to_clean];
2201 desc_cb = &ring->desc_cb[ring->next_to_clean];
2202 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2203 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb);
2204 ring_ptr_move_fw(ring, next_to_clean);
2205 bnum++;
2206 }
2207 }
2208
2209 *out_bnum = bnum;
5b5455a9
PL		 2210
2211 l234info = le32_to_cpu(desc->rx.l234_info);
2212
846fcc83
PL		 2213 /* Based on hw strategy, the tag offloaded will be stored at
2214 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2215 * in one layer tag case.
2216 */
2217 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2218 u16 vlan_tag;
2219
5b5455a9 2220 vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info);
846fcc83
PL		 2221 if (vlan_tag & VLAN_VID_MASK)
2222 __vlan_hwaccel_put_tag(skb,
2223 htons(ETH_P_8021Q),
2224 vlan_tag);
2225 }
2226
76ad4f0e
S		 2227 if (unlikely(!hnae_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
2228 netdev_err(netdev, "no valid bd,%016llx,%016llx\n",
2229 ((u64 *)desc)[0], ((u64 *)desc)[1]);
2230 u64_stats_update_begin(&ring->syncp);
2231 ring->stats.non_vld_descs++;
2232 u64_stats_update_end(&ring->syncp);
2233
2234 dev_kfree_skb_any(skb);
2235 return -EINVAL;
2236 }
2237
2238 if (unlikely((!desc->rx.pkt_len) ||
2239 hnae_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
2240 netdev_err(netdev, "truncated pkt\n");
2241 u64_stats_update_begin(&ring->syncp);
2242 ring->stats.err_pkt_len++;
2243 u64_stats_update_end(&ring->syncp);
2244
2245 dev_kfree_skb_any(skb);
2246 return -EFAULT;
2247 }
2248
2249 if (unlikely(hnae_get_bit(l234info, HNS3_RXD_L2E_B))) {
2250 netdev_err(netdev, "L2 error pkt\n");
2251 u64_stats_update_begin(&ring->syncp);
2252 ring->stats.l2_err++;
2253 u64_stats_update_end(&ring->syncp);
2254
2255 dev_kfree_skb_any(skb);
2256 return -EFAULT;
2257 }
2258
2259 u64_stats_update_begin(&ring->syncp);
2260 ring->stats.rx_pkts++;
2261 ring->stats.rx_bytes += skb->len;
2262 u64_stats_update_end(&ring->syncp);
2263
2264 ring->tqp_vector->rx_group.total_bytes += skb->len;
2265
2266 hns3_rx_checksum(ring, skb, desc);
2267 return 0;
2268}
2269
d43e5aca
YL		 2270int hns3_clean_rx_ring(
2271 struct hns3_enet_ring *ring, int budget,
2272 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2273{
2274#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2275 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2276 int recv_pkts, recv_bds, clean_count, err;
2277 int unused_count = hns3_desc_unused(ring);
2278 struct sk_buff *skb = NULL;
2279 int num, bnum = 0;
2280
2281 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2282 rmb(); /* Make sure num taken effect before the other data is touched */
2283
2284 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2285 num -= unused_count;
2286
2287 while (recv_pkts < budget && recv_bds < num) {
2288 /* Reuse or realloc buffers */
2289 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2290 hns3_nic_alloc_rx_buffers(ring,
2291 clean_count + unused_count);
2292 clean_count = 0;
2293 unused_count = hns3_desc_unused(ring);
2294 }
2295
2296 /* Poll one pkt */
2297 err = hns3_handle_rx_bd(ring, &skb, &bnum);
2298 if (unlikely(!skb)) /* This fault cannot be repaired */
2299 goto out;
2300
2301 recv_bds += bnum;
2302 clean_count += bnum;
2303 if (unlikely(err)) { /* Do jump the err */
2304 recv_pkts++;
2305 continue;
2306 }
2307
2308 /* Do update ip stack process */
2309 skb->protocol = eth_type_trans(skb, netdev);
d43e5aca 2310 rx_fn(ring, skb);
76ad4f0e
S		 2311
2312 recv_pkts++;
2313 }
2314
2315out:
2316 /* Make all data has been write before submit */
2317 if (clean_count + unused_count > 0)
2318 hns3_nic_alloc_rx_buffers(ring,
2319 clean_count + unused_count);
2320
2321 return recv_pkts;
2322}
2323
2324static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2325{
a95e1f86
FL		 2326 struct hns3_enet_tqp_vector *tqp_vector =
2327 ring_group->ring->tqp_vector;
76ad4f0e 2328 enum hns3_flow_level_range new_flow_level;
a95e1f86
FL		 2329 int packets_per_msecs;
2330 int bytes_per_msecs;
2331 u32 time_passed_ms;
76ad4f0e 2332 u16 new_int_gl;
76ad4f0e 2333
a95e1f86 2334 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
76ad4f0e
S		 2335 return false;
2336
2337 if (ring_group->total_packets == 0) {
9bc727a9
YL		 2338 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2339 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2340 return true;
2341 }
2342
2343 /* Simple throttlerate management
2344 * 0-10MB/s lower (50000 ints/s)
2345 * 10-20MB/s middle (20000 ints/s)
2346 * 20-1249MB/s high (18000 ints/s)
2347 * > 40000pps ultra (8000 ints/s)
2348 */
9bc727a9
YL		 2349 new_flow_level = ring_group->coal.flow_level;
2350 new_int_gl = ring_group->coal.int_gl;
a95e1f86
FL		 2351 time_passed_ms =
2352 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2353
2354 if (!time_passed_ms)
2355 return false;
2356
2357 do_div(ring_group->total_packets, time_passed_ms);
2358 packets_per_msecs = ring_group->total_packets;
2359
2360 do_div(ring_group->total_bytes, time_passed_ms);
2361 bytes_per_msecs = ring_group->total_bytes;
2362
2363#define HNS3_RX_LOW_BYTE_RATE 10000
2364#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2365
2366 switch (new_flow_level) {
2367 case HNS3_FLOW_LOW:
a95e1f86 2368 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2369 new_flow_level = HNS3_FLOW_MID;
2370 break;
2371 case HNS3_FLOW_MID:
a95e1f86 2372 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2373 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 2374 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2375 new_flow_level = HNS3_FLOW_LOW;
2376 break;
2377 case HNS3_FLOW_HIGH:
2378 case HNS3_FLOW_ULTRA:
2379 default:
a95e1f86 2380 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2381 new_flow_level = HNS3_FLOW_MID;
2382 break;
2383 }
2384
a95e1f86
FL		 2385#define HNS3_RX_ULTRA_PACKET_RATE 40
2386
2387 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2388 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2389 new_flow_level = HNS3_FLOW_ULTRA;
2390
2391 switch (new_flow_level) {
2392 case HNS3_FLOW_LOW:
2393 new_int_gl = HNS3_INT_GL_50K;
2394 break;
2395 case HNS3_FLOW_MID:
2396 new_int_gl = HNS3_INT_GL_20K;
2397 break;
2398 case HNS3_FLOW_HIGH:
2399 new_int_gl = HNS3_INT_GL_18K;
2400 break;
2401 case HNS3_FLOW_ULTRA:
2402 new_int_gl = HNS3_INT_GL_8K;
2403 break;
2404 default:
2405 break;
2406 }
2407
2408 ring_group->total_bytes = 0;
2409 ring_group->total_packets = 0;
9bc727a9
YL		 2410 ring_group->coal.flow_level = new_flow_level;
2411 if (new_int_gl != ring_group->coal.int_gl) {
2412 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 2413 return true;
2414 }
2415 return false;
2416}
2417
2418static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2419{
8b1ff1ea
FL		 2420 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2421 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2422 bool rx_update, tx_update;
2423
cd9d187b
FL		 2424 if (tqp_vector->int_adapt_down > 0) {
2425 tqp_vector->int_adapt_down--;
2426 return;
2427 }
2428
9bc727a9 2429 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 2430 rx_update = hns3_get_new_int_gl(rx_group);
2431 if (rx_update)
2432 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 2433 rx_group->coal.int_gl);
8b1ff1ea
FL		 2434 }
2435
9bc727a9 2436 if (tx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 2437 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2438 if (tx_update)
2439 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 2440 tx_group->coal.int_gl);
76ad4f0e 2441 }
cd9d187b 2442
a95e1f86 2443 tqp_vector->last_jiffies = jiffies;
cd9d187b 2444 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
76ad4f0e
S		 2445}
2446
2447static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2448{
2449 struct hns3_enet_ring *ring;
2450 int rx_pkt_total = 0;
2451
2452 struct hns3_enet_tqp_vector *tqp_vector =
2453 container_of(napi, struct hns3_enet_tqp_vector, napi);
2454 bool clean_complete = true;
2455 int rx_budget;
2456
2457 /* Since the actual Tx work is minimal, we can give the Tx a larger
2458 * budget and be more aggressive about cleaning up the Tx descriptors.
2459 */
2460 hns3_for_each_ring(ring, tqp_vector->tx_group) {
2461 if (!hns3_clean_tx_ring(ring, budget))
2462 clean_complete = false;
2463 }
2464
2465 /* make sure rx ring budget not smaller than 1 */
2466 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2467
2468 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 2469 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2470 hns3_rx_skb);
76ad4f0e
S		 2471
2472 if (rx_cleaned >= rx_budget)
2473 clean_complete = false;
2474
2475 rx_pkt_total += rx_cleaned;
2476 }
2477
2478 tqp_vector->rx_group.total_packets += rx_pkt_total;
2479
2480 if (!clean_complete)
2481 return budget;
2482
2483 napi_complete(napi);
2484 hns3_update_new_int_gl(tqp_vector);
2485 hns3_mask_vector_irq(tqp_vector, 1);
2486
2487 return rx_pkt_total;
2488}
2489
2490static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2491 struct hnae3_ring_chain_node *head)
2492{
2493 struct pci_dev *pdev = tqp_vector->handle->pdev;
2494 struct hnae3_ring_chain_node *cur_chain = head;
2495 struct hnae3_ring_chain_node *chain;
2496 struct hns3_enet_ring *tx_ring;
2497 struct hns3_enet_ring *rx_ring;
2498
2499 tx_ring = tqp_vector->tx_group.ring;
2500 if (tx_ring) {
2501 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
2502 hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2503 HNAE3_RING_TYPE_TX);
11af96a4
FL		 2504 hnae_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2505 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 2506
2507 cur_chain->next = NULL;
2508
2509 while (tx_ring->next) {
2510 tx_ring = tx_ring->next;
2511
2512 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2513 GFP_KERNEL);
2514 if (!chain)
2515 return -ENOMEM;
2516
2517 cur_chain->next = chain;
2518 chain->tqp_index = tx_ring->tqp->tqp_index;
2519 hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2520 HNAE3_RING_TYPE_TX);
11af96a4
FL		 2521 hnae_set_field(chain->int_gl_idx,
2522 HNAE3_RING_GL_IDX_M,
2523 HNAE3_RING_GL_IDX_S,
2524 HNAE3_RING_GL_TX);
76ad4f0e
S		 2525
2526 cur_chain = chain;
2527 }
2528 }
2529
2530 rx_ring = tqp_vector->rx_group.ring;
2531 if (!tx_ring && rx_ring) {
2532 cur_chain->next = NULL;
2533 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
2534 hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2535 HNAE3_RING_TYPE_RX);
11af96a4
FL		 2536 hnae_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2537 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 2538
2539 rx_ring = rx_ring->next;
2540 }
2541
2542 while (rx_ring) {
2543 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2544 if (!chain)
2545 return -ENOMEM;
2546
2547 cur_chain->next = chain;
2548 chain->tqp_index = rx_ring->tqp->tqp_index;
2549 hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2550 HNAE3_RING_TYPE_RX);
11af96a4
FL		 2551 hnae_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2552 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2553
76ad4f0e
S		 2554 cur_chain = chain;
2555
2556 rx_ring = rx_ring->next;
2557 }
2558
2559 return 0;
2560}
2561
2562static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2563 struct hnae3_ring_chain_node *head)
2564{
2565 struct pci_dev *pdev = tqp_vector->handle->pdev;
2566 struct hnae3_ring_chain_node *chain_tmp, *chain;
2567
2568 chain = head->next;
2569
2570 while (chain) {
2571 chain_tmp = chain->next;
2572 devm_kfree(&pdev->dev, chain);
2573 chain = chain_tmp;
2574 }
2575}
2576
2577static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
2578 struct hns3_enet_ring *ring)
2579{
2580 ring->next = group->ring;
2581 group->ring = ring;
2582
2583 group->count++;
2584}
2585
2586static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
2587{
2588 struct hnae3_ring_chain_node vector_ring_chain;
2589 struct hnae3_handle *h = priv->ae_handle;
2590 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 2591 int ret = 0;
2592 u16 i;
2593
dd38c726
YL		 2594 for (i = 0; i < priv->vector_num; i++) {
2595 tqp_vector = &priv->tqp_vector[i];
2596 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
2597 tqp_vector->num_tqps = 0;
2598 }
76ad4f0e 2599
dd38c726
YL		 2600 for (i = 0; i < h->kinfo.num_tqps; i++) {
2601 u16 vector_i = i % priv->vector_num;
2602 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 2603
2604 tqp_vector = &priv->tqp_vector[vector_i];
2605
2606 hns3_add_ring_to_group(&tqp_vector->tx_group,
2607 priv->ring_data[i].ring);
2608
2609 hns3_add_ring_to_group(&tqp_vector->rx_group,
2610 priv->ring_data[i + tqp_num].ring);
2611
76ad4f0e
S		 2612 priv->ring_data[i].ring->tqp_vector = tqp_vector;
2613 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
dd38c726 2614 tqp_vector->num_tqps++;
76ad4f0e
S		 2615 }
2616
dd38c726 2617 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 2618 tqp_vector = &priv->tqp_vector[i];
2619
2620 tqp_vector->rx_group.total_bytes = 0;
2621 tqp_vector->rx_group.total_packets = 0;
2622 tqp_vector->tx_group.total_bytes = 0;
2623 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 2624 tqp_vector->handle = h;
2625
2626 ret = hns3_get_vector_ring_chain(tqp_vector,
2627 &vector_ring_chain);
2628 if (ret)
dd38c726 2629 return ret;
76ad4f0e
S		 2630
2631 ret = h->ae_algo->ops->map_ring_to_vector(h,
2632 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 2633
2634 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2635
dd38c726
YL		 2636 if (ret)
2637 return ret;
2638
76ad4f0e
S		 2639 netif_napi_add(priv->netdev, &tqp_vector->napi,
2640 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
2641 }
2642
dd38c726
YL		 2643 return 0;
2644}
2645
2646static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
2647{
2648 struct hnae3_handle *h = priv->ae_handle;
2649 struct hns3_enet_tqp_vector *tqp_vector;
2650 struct hnae3_vector_info *vector;
2651 struct pci_dev *pdev = h->pdev;
2652 u16 tqp_num = h->kinfo.num_tqps;
2653 u16 vector_num;
2654 int ret = 0;
2655 u16 i;
2656
2657 /* RSS size, cpu online and vector_num should be the same */
2658 /* Should consider 2p/4p later */
2659 vector_num = min_t(u16, num_online_cpus(), tqp_num);
2660 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
2661 GFP_KERNEL);
2662 if (!vector)
2663 return -ENOMEM;
2664
2665 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
2666
2667 priv->vector_num = vector_num;
2668 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
2669 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
2670 GFP_KERNEL);
2671 if (!priv->tqp_vector) {
2672 ret = -ENOMEM;
2673 goto out;
2674 }
2675
2676 for (i = 0; i < priv->vector_num; i++) {
2677 tqp_vector = &priv->tqp_vector[i];
2678 tqp_vector->idx = i;
2679 tqp_vector->mask_addr = vector[i].io_addr;
2680 tqp_vector->vector_irq = vector[i].vector;
2681 hns3_vector_gl_rl_init(tqp_vector, priv);
2682 }
2683
76ad4f0e
S		 2684out:
2685 devm_kfree(&pdev->dev, vector);
2686 return ret;
2687}
2688
dd38c726
YL		 2689static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
2690{
2691 group->ring = NULL;
2692 group->count = 0;
2693}
2694
76ad4f0e
S		 2695static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
2696{
2697 struct hnae3_ring_chain_node vector_ring_chain;
2698 struct hnae3_handle *h = priv->ae_handle;
2699 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 2700 int i, ret;
2701
2702 for (i = 0; i < priv->vector_num; i++) {
2703 tqp_vector = &priv->tqp_vector[i];
2704
2705 ret = hns3_get_vector_ring_chain(tqp_vector,
2706 &vector_ring_chain);
2707 if (ret)
2708 return ret;
2709
2710 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
2711 tqp_vector->vector_irq, &vector_ring_chain);
2712 if (ret)
2713 return ret;
2714
0d3e6631
YL		 2715 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
2716 if (ret)
2717 return ret;
2718
76ad4f0e
S		 2719 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2720
2721 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) {
2722 (void)irq_set_affinity_hint(
2723 priv->tqp_vector[i].vector_irq,
2724 NULL);
ae064e61 2725 free_irq(priv->tqp_vector[i].vector_irq,
2726 &priv->tqp_vector[i]);
76ad4f0e
S		 2727 }
2728
2729 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
dd38c726
YL		 2730 hns3_clear_ring_group(&tqp_vector->rx_group);
2731 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 2732 netif_napi_del(&priv->tqp_vector[i].napi);
2733 }
2734
dd38c726
YL		 2735 return 0;
2736}
2737
2738static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
2739{
2740 struct hnae3_handle *h = priv->ae_handle;
2741 struct pci_dev *pdev = h->pdev;
2742 int i, ret;
2743
2744 for (i = 0; i < priv->vector_num; i++) {
2745 struct hns3_enet_tqp_vector *tqp_vector;
2746
2747 tqp_vector = &priv->tqp_vector[i];
2748 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
2749 if (ret)
2750 return ret;
2751 }
76ad4f0e 2752
dd38c726 2753 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 2754 return 0;
2755}
2756
2757static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
2758 int ring_type)
2759{
2760 struct hns3_nic_ring_data *ring_data = priv->ring_data;
2761 int queue_num = priv->ae_handle->kinfo.num_tqps;
2762 struct pci_dev *pdev = priv->ae_handle->pdev;
2763 struct hns3_enet_ring *ring;
2764
2765 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
2766 if (!ring)
2767 return -ENOMEM;
2768
2769 if (ring_type == HNAE3_RING_TYPE_TX) {
2770 ring_data[q->tqp_index].ring = ring;
66b44730 2771 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 2772 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
2773 } else {
2774 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 2775 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 2776 ring->io_base = q->io_base;
2777 }
2778
2779 hnae_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
2780
76ad4f0e
S		 2781 ring->tqp = q;
2782 ring->desc = NULL;
2783 ring->desc_cb = NULL;
2784 ring->dev = priv->dev;
2785 ring->desc_dma_addr = 0;
2786 ring->buf_size = q->buf_size;
2787 ring->desc_num = q->desc_num;
2788 ring->next_to_use = 0;
2789 ring->next_to_clean = 0;
2790
2791 return 0;
2792}
2793
2794static int hns3_queue_to_ring(struct hnae3_queue *tqp,
2795 struct hns3_nic_priv *priv)
2796{
2797 int ret;
2798
2799 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
2800 if (ret)
2801 return ret;
2802
2803 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
2804 if (ret)
2805 return ret;
2806
2807 return 0;
2808}
2809
2810static int hns3_get_ring_config(struct hns3_nic_priv *priv)
2811{
2812 struct hnae3_handle *h = priv->ae_handle;
2813 struct pci_dev *pdev = h->pdev;
2814 int i, ret;
2815
2816 priv->ring_data = devm_kzalloc(&pdev->dev, h->kinfo.num_tqps *
2817 sizeof(*priv->ring_data) * 2,
2818 GFP_KERNEL);
2819 if (!priv->ring_data)
2820 return -ENOMEM;
2821
2822 for (i = 0; i < h->kinfo.num_tqps; i++) {
2823 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
2824 if (ret)
2825 goto err;
2826 }
2827
2828 return 0;
2829err:
2830 devm_kfree(&pdev->dev, priv->ring_data);
2831 return ret;
2832}
2833
09f2af64
PL		 2834static void hns3_put_ring_config(struct hns3_nic_priv *priv)
2835{
2836 struct hnae3_handle *h = priv->ae_handle;
2837 int i;
2838
2839 for (i = 0; i < h->kinfo.num_tqps; i++) {
2840 devm_kfree(priv->dev, priv->ring_data[i].ring);
2841 devm_kfree(priv->dev,
2842 priv->ring_data[i + h->kinfo.num_tqps].ring);
2843 }
2844 devm_kfree(priv->dev, priv->ring_data);
2845}
2846
76ad4f0e
S		 2847static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
2848{
2849 int ret;
2850
2851 if (ring->desc_num <= 0 || ring->buf_size <= 0)
2852 return -EINVAL;
2853
2854 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
2855 GFP_KERNEL);
2856 if (!ring->desc_cb) {
2857 ret = -ENOMEM;
2858 goto out;
2859 }
2860
2861 ret = hns3_alloc_desc(ring);
2862 if (ret)
2863 goto out_with_desc_cb;
2864
2865 if (!HNAE3_IS_TX_RING(ring)) {
2866 ret = hns3_alloc_ring_buffers(ring);
2867 if (ret)
2868 goto out_with_desc;
2869 }
2870
2871 return 0;
2872
2873out_with_desc:
2874 hns3_free_desc(ring);
2875out_with_desc_cb:
2876 kfree(ring->desc_cb);
2877 ring->desc_cb = NULL;
2878out:
2879 return ret;
2880}
2881
2882static void hns3_fini_ring(struct hns3_enet_ring *ring)
2883{
2884 hns3_free_desc(ring);
2885 kfree(ring->desc_cb);
2886 ring->desc_cb = NULL;
2887 ring->next_to_clean = 0;
2888 ring->next_to_use = 0;
2889}
2890
1db9b1bf 2891static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 2892{
2893 int bd_size_type;
2894
2895 switch (buf_size) {
2896 case 512:
2897 bd_size_type = HNS3_BD_SIZE_512_TYPE;
2898 break;
2899 case 1024:
2900 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
2901 break;
2902 case 2048:
2903 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
2904 break;
2905 case 4096:
2906 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
2907 break;
2908 default:
2909 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
2910 }
2911
2912 return bd_size_type;
2913}
2914
2915static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
2916{
2917 dma_addr_t dma = ring->desc_dma_addr;
2918 struct hnae3_queue *q = ring->tqp;
2919
2920 if (!HNAE3_IS_TX_RING(ring)) {
2921 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
2922 (u32)dma);
2923 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
2924 (u32)((dma >> 31) >> 1));
2925
2926 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
2927 hns3_buf_size2type(ring->buf_size));
2928 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
2929 ring->desc_num / 8 - 1);
2930
2931 } else {
2932 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
2933 (u32)dma);
2934 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
2935 (u32)((dma >> 31) >> 1));
2936
2937 hns3_write_dev(q, HNS3_RING_TX_RING_BD_LEN_REG,
2938 hns3_buf_size2type(ring->buf_size));
2939 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
2940 ring->desc_num / 8 - 1);
2941 }
2942}
2943
5668abda 2944int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 2945{
2946 struct hnae3_handle *h = priv->ae_handle;
2947 int ring_num = h->kinfo.num_tqps * 2;
2948 int i, j;
2949 int ret;
2950
2951 for (i = 0; i < ring_num; i++) {
2952 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
2953 if (ret) {
2954 dev_err(priv->dev,
2955 "Alloc ring memory fail! ret=%d\n", ret);
2956 goto out_when_alloc_ring_memory;
2957 }
2958
76ad4f0e
S		 2959 u64_stats_init(&priv->ring_data[i].ring->syncp);
2960 }
2961
2962 return 0;
2963
2964out_when_alloc_ring_memory:
2965 for (j = i - 1; j >= 0; j--)
ee83f776 2966 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 2967
2968 return -ENOMEM;
2969}
2970
5668abda 2971int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 2972{
2973 struct hnae3_handle *h = priv->ae_handle;
2974 int i;
2975
2976 for (i = 0; i < h->kinfo.num_tqps; i++) {
2977 if (h->ae_algo->ops->reset_queue)
2978 h->ae_algo->ops->reset_queue(h, i);
2979
2980 hns3_fini_ring(priv->ring_data[i].ring);
2981 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
2982 }
76ad4f0e
S		 2983 return 0;
2984}
2985
2986/* Set mac addr if it is configured. or leave it to the AE driver */
f09555ff 2987static void hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 2988{
2989 struct hns3_nic_priv *priv = netdev_priv(netdev);
2990 struct hnae3_handle *h = priv->ae_handle;
2991 u8 mac_addr_temp[ETH_ALEN];
2992
f09555ff 2993 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 2994 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
2995 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
2996 }
2997
2998 /* Check if the MAC address is valid, if not get a random one */
2999 if (!is_valid_ether_addr(netdev->dev_addr)) {
3000 eth_hw_addr_random(netdev);
3001 dev_warn(priv->dev, "using random MAC address %pM\n",
3002 netdev->dev_addr);
76ad4f0e 3003 }
139e8792
L		 3004
3005 if (h->ae_algo->ops->set_mac_addr)
59098055 3006 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3007
76ad4f0e
S		 3008}
3009
c7fc8fb6
JS		 3010static void hns3_uninit_mac_addr(struct net_device *netdev)
3011{
3012 struct hns3_nic_priv *priv = netdev_priv(netdev);
3013 struct hnae3_handle *h = priv->ae_handle;
3014
3015 if (h->ae_algo->ops->rm_uc_addr)
3016 h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr);
3017}
3018
76ad4f0e
S		 3019static void hns3_nic_set_priv_ops(struct net_device *netdev)
3020{
3021 struct hns3_nic_priv *priv = netdev_priv(netdev);
3022
3023 if ((netdev->features & NETIF_F_TSO) ||
3024 (netdev->features & NETIF_F_TSO6)) {
3025 priv->ops.fill_desc = hns3_fill_desc_tso;
3026 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
3027 } else {
3028 priv->ops.fill_desc = hns3_fill_desc;
3029 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
3030 }
3031}
3032
3033static int hns3_client_init(struct hnae3_handle *handle)
3034{
3035 struct pci_dev *pdev = handle->pdev;
3036 struct hns3_nic_priv *priv;
3037 struct net_device *netdev;
3038 int ret;
3039
3040 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv),
678335a1 3041 hns3_get_max_available_channels(handle));
76ad4f0e
S		 3042 if (!netdev)
3043 return -ENOMEM;
3044
3045 priv = netdev_priv(netdev);
3046 priv->dev = &pdev->dev;
3047 priv->netdev = netdev;
3048 priv->ae_handle = handle;
6d4c3981
SM		 3049 priv->ae_handle->reset_level = HNAE3_NONE_RESET;
3050 priv->ae_handle->last_reset_time = jiffies;
f8fa222c 3051 priv->tx_timeout_count = 0;
76ad4f0e
S		 3052
3053 handle->kinfo.netdev = netdev;
3054 handle->priv = (void *)priv;
3055
f09555ff 3056 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3057
3058 hns3_set_default_feature(netdev);
3059
3060 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3061 netdev->priv_flags |= IFF_UNICAST_FLT;
3062 netdev->netdev_ops = &hns3_nic_netdev_ops;
3063 SET_NETDEV_DEV(netdev, &pdev->dev);
3064 hns3_ethtool_set_ops(netdev);
3065 hns3_nic_set_priv_ops(netdev);
3066
3067 /* Carrier off reporting is important to ethtool even BEFORE open */
3068 netif_carrier_off(netdev);
3069
3070 ret = hns3_get_ring_config(priv);
3071 if (ret) {
3072 ret = -ENOMEM;
3073 goto out_get_ring_cfg;
3074 }
3075
dd38c726
YL		 3076 ret = hns3_nic_alloc_vector_data(priv);
3077 if (ret) {
3078 ret = -ENOMEM;
3079 goto out_alloc_vector_data;
3080 }
3081
76ad4f0e
S		 3082 ret = hns3_nic_init_vector_data(priv);
3083 if (ret) {
3084 ret = -ENOMEM;
3085 goto out_init_vector_data;
3086 }
3087
3088 ret = hns3_init_all_ring(priv);
3089 if (ret) {
3090 ret = -ENOMEM;
3091 goto out_init_ring_data;
3092 }
3093
3094 ret = register_netdev(netdev);
3095 if (ret) {
3096 dev_err(priv->dev, "probe register netdev fail!\n");
3097 goto out_reg_netdev_fail;
3098 }
3099
986743db
YL		 3100 hns3_dcbnl_setup(handle);
3101
a8e8b7ff
S		 3102 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */
3103 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
3104
76ad4f0e
S		 3105 return ret;
3106
3107out_reg_netdev_fail:
3108out_init_ring_data:
3109 (void)hns3_nic_uninit_vector_data(priv);
76ad4f0e 3110out_init_vector_data:
dd38c726
YL		 3111 hns3_nic_dealloc_vector_data(priv);
3112out_alloc_vector_data:
3113 priv->ring_data = NULL;
76ad4f0e
S		 3114out_get_ring_cfg:
3115 priv->ae_handle = NULL;
3116 free_netdev(netdev);
3117 return ret;
3118}
3119
3120static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3121{
3122 struct net_device *netdev = handle->kinfo.netdev;
3123 struct hns3_nic_priv *priv = netdev_priv(netdev);
3124 int ret;
3125
3126 if (netdev->reg_state != NETREG_UNINITIALIZED)
3127 unregister_netdev(netdev);
3128
7b763f3f
FL		 3129 hns3_force_clear_all_rx_ring(handle);
3130
76ad4f0e
S		 3131 ret = hns3_nic_uninit_vector_data(priv);
3132 if (ret)
3133 netdev_err(netdev, "uninit vector error\n");
3134
dd38c726
YL		 3135 ret = hns3_nic_dealloc_vector_data(priv);
3136 if (ret)
3137 netdev_err(netdev, "dealloc vector error\n");
3138
76ad4f0e
S		 3139 ret = hns3_uninit_all_ring(priv);
3140 if (ret)
3141 netdev_err(netdev, "uninit ring error\n");
3142
ec777890
YL		 3143 hns3_put_ring_config(priv);
3144
76ad4f0e
S		 3145 priv->ring_data = NULL;
3146
c7fc8fb6
JS		 3147 hns3_uninit_mac_addr(netdev);
3148
76ad4f0e
S		 3149 free_netdev(netdev);
3150}
3151
3152static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3153{
3154 struct net_device *netdev = handle->kinfo.netdev;
3155
3156 if (!netdev)
3157 return;
3158
3159 if (linkup) {
3160 netif_carrier_on(netdev);
3161 netif_tx_wake_all_queues(netdev);
3162 netdev_info(netdev, "link up\n");
3163 } else {
3164 netif_carrier_off(netdev);
3165 netif_tx_stop_all_queues(netdev);
3166 netdev_info(netdev, "link down\n");
3167 }
3168}
3169
9df8f79a
YL		 3170static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3171{
3172 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3173 struct net_device *ndev = kinfo->netdev;
075cfdd6 3174 bool if_running;
9df8f79a
YL		 3175 int ret;
3176 u8 i;
3177
3178 if (tc > HNAE3_MAX_TC)
3179 return -EINVAL;
3180
3181 if (!ndev)
3182 return -ENODEV;
3183
075cfdd6
CIK		 3184 if_running = netif_running(ndev);
3185
9df8f79a
YL		 3186 ret = netdev_set_num_tc(ndev, tc);
3187 if (ret)
3188 return ret;
3189
3190 if (if_running) {
3191 (void)hns3_nic_net_stop(ndev);
3192 msleep(100);
3193 }
3194
3195 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3196 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3197 if (ret)
3198 goto err_out;
3199
3200 if (tc <= 1) {
3201 netdev_reset_tc(ndev);
3202 goto out;
3203 }
3204
3205 for (i = 0; i < HNAE3_MAX_TC; i++) {
3206 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3207
3208 if (tc_info->enable)
3209 netdev_set_tc_queue(ndev,
3210 tc_info->tc,
3211 tc_info->tqp_count,
3212 tc_info->tqp_offset);
3213 }
3214
3215 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
3216 netdev_set_prio_tc_map(ndev, i,
3217 kinfo->prio_tc[i]);
3218 }
3219
3220out:
3221 ret = hns3_nic_set_real_num_queue(ndev);
3222
3223err_out:
3224 if (if_running)
3225 (void)hns3_nic_net_open(ndev);
3226
3227 return ret;
3228}
3229
bb6b94a8
L		 3230static void hns3_recover_hw_addr(struct net_device *ndev)
3231{
3232 struct netdev_hw_addr_list *list;
3233 struct netdev_hw_addr *ha, *tmp;
3234
3235 /* go through and sync uc_addr entries to the device */
3236 list = &ndev->uc;
3237 list_for_each_entry_safe(ha, tmp, &list->list, list)
3238 hns3_nic_uc_sync(ndev, ha->addr);
3239
3240 /* go through and sync mc_addr entries to the device */
3241 list = &ndev->mc;
3242 list_for_each_entry_safe(ha, tmp, &list->list, list)
3243 hns3_nic_mc_sync(ndev, ha->addr);
3244}
3245
beebca3a 3246static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 3247{
beebca3a 3248 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 3249 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL		 3250 hns3_free_buffer_detach(ring, ring->next_to_clean);
3251 ring_ptr_move_fw(ring, next_to_clean);
3252 }
3253}
3254
7b763f3f
FL		 3255static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3256{
3257 struct hns3_desc_cb res_cbs;
3258 int ret;
3259
3260 while (ring->next_to_use != ring->next_to_clean) {
3261 /* When a buffer is not reused, it's memory has been
3262 * freed in hns3_handle_rx_bd or will be freed by
3263 * stack, so we need to replace the buffer here.
3264 */
3265 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3266 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3267 if (ret) {
3268 u64_stats_update_begin(&ring->syncp);
3269 ring->stats.sw_err_cnt++;
3270 u64_stats_update_end(&ring->syncp);
3271 /* if alloc new buffer fail, exit directly
3272 * and reclear in up flow.
3273 */
3274 netdev_warn(ring->tqp->handle->kinfo.netdev,
3275 "reserve buffer map failed, ret = %d\n",
3276 ret);
3277 return ret;
3278 }
3279 hns3_replace_buffer(ring, ring->next_to_use,
3280 &res_cbs);
3281 }
3282 ring_ptr_move_fw(ring, next_to_use);
3283 }
3284
3285 return 0;
3286}
3287
3288static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 3289{
beebca3a
YL		 3290 while (ring->next_to_use != ring->next_to_clean) {
3291 /* When a buffer is not reused, it's memory has been
3292 * freed in hns3_handle_rx_bd or will be freed by
3293 * stack, so only need to unmap the buffer here.
3294 */
3295 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3296 hns3_unmap_buffer(ring,
3297 &ring->desc_cb[ring->next_to_use]);
3298 ring->desc_cb[ring->next_to_use].dma = 0;
3299 }
3300
3301 ring_ptr_move_fw(ring, next_to_use);
3302 }
bb6b94a8
L		 3303}
3304
7b763f3f
FL		 3305static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3306{
3307 struct net_device *ndev = h->kinfo.netdev;
3308 struct hns3_nic_priv *priv = netdev_priv(ndev);
3309 struct hns3_enet_ring *ring;
3310 u32 i;
3311
3312 for (i = 0; i < h->kinfo.num_tqps; i++) {
3313 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3314 hns3_force_clear_rx_ring(ring);
3315 }
3316}
3317
bb6b94a8
L		 3318static void hns3_clear_all_ring(struct hnae3_handle *h)
3319{
3320 struct net_device *ndev = h->kinfo.netdev;
3321 struct hns3_nic_priv *priv = netdev_priv(ndev);
3322 u32 i;
3323
3324 for (i = 0; i < h->kinfo.num_tqps; i++) {
3325 struct netdev_queue *dev_queue;
3326 struct hns3_enet_ring *ring;
3327
3328 ring = priv->ring_data[i].ring;
beebca3a 3329 hns3_clear_tx_ring(ring);
bb6b94a8
L		 3330 dev_queue = netdev_get_tx_queue(ndev,
3331 priv->ring_data[i].queue_index);
3332 netdev_tx_reset_queue(dev_queue);
3333
3334 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
7b763f3f
FL		 3335 /* Continue to clear other rings even if clearing some
3336 * rings failed.
3337 */
beebca3a 3338 hns3_clear_rx_ring(ring);
bb6b94a8
L		 3339 }
3340}
3341
7b763f3f
FL		 3342int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3343{
3344 struct net_device *ndev = h->kinfo.netdev;
3345 struct hns3_nic_priv *priv = netdev_priv(ndev);
3346 struct hns3_enet_ring *rx_ring;
3347 int i, j;
3348 int ret;
3349
3350 for (i = 0; i < h->kinfo.num_tqps; i++) {
3351 h->ae_algo->ops->reset_queue(h, i);
3352 hns3_init_ring_hw(priv->ring_data[i].ring);
3353
3354 /* We need to clear tx ring here because self test will
3355 * use the ring and will not run down before up
3356 */
3357 hns3_clear_tx_ring(priv->ring_data[i].ring);
3358 priv->ring_data[i].ring->next_to_clean = 0;
3359 priv->ring_data[i].ring->next_to_use = 0;
3360
3361 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3362 hns3_init_ring_hw(rx_ring);
3363 ret = hns3_clear_rx_ring(rx_ring);
3364 if (ret)
3365 return ret;
3366
3367 /* We can not know the hardware head and tail when this
3368 * function is called in reset flow, so we reuse all desc.
3369 */
3370 for (j = 0; j < rx_ring->desc_num; j++)
3371 hns3_reuse_buffer(rx_ring, j);
3372
3373 rx_ring->next_to_clean = 0;
3374 rx_ring->next_to_use = 0;
3375 }
3376
3377 return 0;
3378}
3379
bb6b94a8
L		 3380static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3381{
3382 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3383 struct net_device *ndev = kinfo->netdev;
3384
3385 if (!netif_running(ndev))
3386 return -EIO;
3387
3388 return hns3_nic_net_stop(ndev);
3389}
3390
3391static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3392{
3393 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
bb6b94a8
L		 3394 int ret = 0;
3395
3396 if (netif_running(kinfo->netdev)) {
3397 ret = hns3_nic_net_up(kinfo->netdev);
3398 if (ret) {
3399 netdev_err(kinfo->netdev,
3400 "hns net up fail, ret=%d!\n", ret);
3401 return ret;
3402 }
6d4c3981 3403 handle->last_reset_time = jiffies;
bb6b94a8
L		 3404 }
3405
3406 return ret;
3407}
3408
3409static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
3410{
3411 struct net_device *netdev = handle->kinfo.netdev;
3412 struct hns3_nic_priv *priv = netdev_priv(netdev);
3413 int ret;
3414
f09555ff 3415 hns3_init_mac_addr(netdev, false);
bb6b94a8
L		 3416 hns3_nic_set_rx_mode(netdev);
3417 hns3_recover_hw_addr(netdev);
3418
681ec399
YL		 3419 /* Hardware table is only clear when pf resets */
3420 if (!(handle->flags & HNAE3_SUPPORT_VF))
3421 hns3_restore_vlan(netdev);
3422
bb6b94a8
L		 3423 /* Carrier off reporting is important to ethtool even BEFORE open */
3424 netif_carrier_off(netdev);
3425
3426 ret = hns3_get_ring_config(priv);
3427 if (ret)
3428 return ret;
3429
3430 ret = hns3_nic_init_vector_data(priv);
3431 if (ret)
3432 return ret;
3433
3434 ret = hns3_init_all_ring(priv);
3435 if (ret) {
3436 hns3_nic_uninit_vector_data(priv);
3437 priv->ring_data = NULL;
3438 }
3439
3440 return ret;
3441}
3442
3443static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
3444{
3445 struct net_device *netdev = handle->kinfo.netdev;
3446 struct hns3_nic_priv *priv = netdev_priv(netdev);
3447 int ret;
3448
7b763f3f 3449 hns3_force_clear_all_rx_ring(handle);
bb6b94a8
L		 3450
3451 ret = hns3_nic_uninit_vector_data(priv);
3452 if (ret) {
3453 netdev_err(netdev, "uninit vector error\n");
3454 return ret;
3455 }
3456
3457 ret = hns3_uninit_all_ring(priv);
3458 if (ret)
3459 netdev_err(netdev, "uninit ring error\n");
3460
ec777890
YL		 3461 hns3_put_ring_config(priv);
3462
bb6b94a8
L		 3463 priv->ring_data = NULL;
3464
c7fc8fb6
JS		 3465 hns3_uninit_mac_addr(netdev);
3466
bb6b94a8
L		 3467 return ret;
3468}
3469
3470static int hns3_reset_notify(struct hnae3_handle *handle,
3471 enum hnae3_reset_notify_type type)
3472{
3473 int ret = 0;
3474
3475 switch (type) {
3476 case HNAE3_UP_CLIENT:
e1586241
SM		 3477 ret = hns3_reset_notify_up_enet(handle);
3478 break;
bb6b94a8
L		 3479 case HNAE3_DOWN_CLIENT:
3480 ret = hns3_reset_notify_down_enet(handle);
3481 break;
3482 case HNAE3_INIT_CLIENT:
3483 ret = hns3_reset_notify_init_enet(handle);
3484 break;
3485 case HNAE3_UNINIT_CLIENT:
3486 ret = hns3_reset_notify_uninit_enet(handle);
3487 break;
3488 default:
3489 break;
3490 }
3491
3492 return ret;
3493}
3494
7a242b23
YL		 3495static void hns3_restore_coal(struct hns3_nic_priv *priv,
3496 struct hns3_enet_coalesce *tx,
3497 struct hns3_enet_coalesce *rx)
3498{
3499 u16 vector_num = priv->vector_num;
3500 int i;
3501
3502 for (i = 0; i < vector_num; i++) {
3503 memcpy(&priv->tqp_vector[i].tx_group.coal, tx,
3504 sizeof(struct hns3_enet_coalesce));
3505 memcpy(&priv->tqp_vector[i].rx_group.coal, rx,
3506 sizeof(struct hns3_enet_coalesce));
3507 }
3508}
3509
3510static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num,
3511 struct hns3_enet_coalesce *tx,
3512 struct hns3_enet_coalesce *rx)
09f2af64
PL		 3513{
3514 struct hns3_nic_priv *priv = netdev_priv(netdev);
3515 struct hnae3_handle *h = hns3_get_handle(netdev);
3516 int ret;
3517
3518 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
3519 if (ret)
3520 return ret;
3521
3522 ret = hns3_get_ring_config(priv);
3523 if (ret)
3524 return ret;
3525
dd38c726
YL		 3526 ret = hns3_nic_alloc_vector_data(priv);
3527 if (ret)
3528 goto err_alloc_vector;
3529
7a242b23
YL		 3530 hns3_restore_coal(priv, tx, rx);
3531
09f2af64
PL		 3532 ret = hns3_nic_init_vector_data(priv);
3533 if (ret)
3534 goto err_uninit_vector;
3535
3536 ret = hns3_init_all_ring(priv);
3537 if (ret)
3538 goto err_put_ring;
3539
3540 return 0;
3541
3542err_put_ring:
3543 hns3_put_ring_config(priv);
3544err_uninit_vector:
3545 hns3_nic_uninit_vector_data(priv);
dd38c726
YL		 3546err_alloc_vector:
3547 hns3_nic_dealloc_vector_data(priv);
09f2af64
PL		 3548 return ret;
3549}
3550
3551static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
3552{
3553 return (new_tqp_num / num_tc) * num_tc;
3554}
3555
3556int hns3_set_channels(struct net_device *netdev,
3557 struct ethtool_channels *ch)
3558{
3559 struct hns3_nic_priv *priv = netdev_priv(netdev);
3560 struct hnae3_handle *h = hns3_get_handle(netdev);
3561 struct hnae3_knic_private_info *kinfo = &h->kinfo;
7a242b23 3562 struct hns3_enet_coalesce tx_coal, rx_coal;
09f2af64
PL		 3563 bool if_running = netif_running(netdev);
3564 u32 new_tqp_num = ch->combined_count;
3565 u16 org_tqp_num;
3566 int ret;
3567
3568 if (ch->rx_count || ch->tx_count)
3569 return -EINVAL;
3570
678335a1 3571 if (new_tqp_num > hns3_get_max_available_channels(h) ||
09f2af64
PL		 3572 new_tqp_num < kinfo->num_tc) {
3573 dev_err(&netdev->dev,
3574 "Change tqps fail, the tqp range is from %d to %d",
3575 kinfo->num_tc,
678335a1 3576 hns3_get_max_available_channels(h));
09f2af64
PL		 3577 return -EINVAL;
3578 }
3579
3580 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
3581 if (kinfo->num_tqps == new_tqp_num)
3582 return 0;
3583
3584 if (if_running)
20e4bf98 3585 hns3_nic_net_stop(netdev);
09f2af64 3586
09f2af64
PL		 3587 ret = hns3_nic_uninit_vector_data(priv);
3588 if (ret) {
3589 dev_err(&netdev->dev,
3590 "Unbind vector with tqp fail, nothing is changed");
3591 goto open_netdev;
3592 }
3593
7a242b23
YL		 3594 /* Changing the tqp num may also change the vector num,
3595 * ethtool only support setting and querying one coal
3596 * configuation for now, so save the vector 0' coal
3597 * configuation here in order to restore it.
3598 */
3599 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal,
3600 sizeof(struct hns3_enet_coalesce));
3601 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal,
3602 sizeof(struct hns3_enet_coalesce));
3603
dd38c726
YL		 3604 hns3_nic_dealloc_vector_data(priv);
3605
09f2af64 3606 hns3_uninit_all_ring(priv);
ec777890 3607 hns3_put_ring_config(priv);
09f2af64
PL		 3608
3609 org_tqp_num = h->kinfo.num_tqps;
7a242b23 3610 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal);
09f2af64 3611 if (ret) {
7a242b23
YL		 3612 ret = hns3_modify_tqp_num(netdev, org_tqp_num,
3613 &tx_coal, &rx_coal);
09f2af64
PL		 3614 if (ret) {
3615 /* If revert to old tqp failed, fatal error occurred */
3616 dev_err(&netdev->dev,
3617 "Revert to old tqp num fail, ret=%d", ret);
3618 return ret;
3619 }
3620 dev_info(&netdev->dev,
3621 "Change tqp num fail, Revert to old tqp num");
3622 }
3623
3624open_netdev:
3625 if (if_running)
20e4bf98 3626 hns3_nic_net_open(netdev);
09f2af64
PL		 3627
3628 return ret;
3629}
3630
1db9b1bf 3631static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 3632 .init_instance = hns3_client_init,
3633 .uninit_instance = hns3_client_uninit,
3634 .link_status_change = hns3_link_status_change,
9df8f79a 3635 .setup_tc = hns3_client_setup_tc,
bb6b94a8 3636 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 3637};
3638
3639/* hns3_init_module - Driver registration routine
3640 * hns3_init_module is the first routine called when the driver is
3641 * loaded. All it does is register with the PCI subsystem.
3642 */
3643static int __init hns3_init_module(void)
3644{
3645 int ret;
3646
3647 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
3648 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
3649
3650 client.type = HNAE3_CLIENT_KNIC;
3651 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
3652 hns3_driver_name);
3653
3654 client.ops = &client_ops;
3655
13562d1f
XW		 3656 INIT_LIST_HEAD(&client.node);
3657
76ad4f0e
S		 3658 ret = hnae3_register_client(&client);
3659 if (ret)
3660 return ret;
3661
3662 ret = pci_register_driver(&hns3_driver);
3663 if (ret)
3664 hnae3_unregister_client(&client);
3665
3666 return ret;
3667}
3668module_init(hns3_init_module);
3669
3670/* hns3_exit_module - Driver exit cleanup routine
3671 * hns3_exit_module is called just before the driver is removed
3672 * from memory.
3673 */
3674static void __exit hns3_exit_module(void)
3675{
3676 pci_unregister_driver(&hns3_driver);
3677 hnae3_unregister_client(&client);
3678}
3679module_exit(hns3_exit_module);
3680
3681MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
3682MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3683MODULE_LICENSE("GPL");
3684MODULE_ALIAS("pci:hns-nic");
3c7624d8 3685MODULE_VERSION(HNS3_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)