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net: use eth_hw_addr_set() instead of ether_addr_copy()
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e 10#include <linux/if_vlan.h>
e99a308d 11#include <linux/irq.h>
76ad4f0e
S		 12#include <linux/ip.h>
13#include <linux/ipv6.h>
14#include <linux/module.h>
15#include <linux/pci.h>
6ae4e733 16#include <linux/aer.h>
76ad4f0e
S		 17#include <linux/skbuff.h>
18#include <linux/sctp.h>
76ad4f0e 19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
76ad4f0e 23#include <net/vxlan.h>
a156998f 24#include <net/geneve.h>
76ad4f0e
S		 25
26#include "hnae3.h"
27#include "hns3_enet.h"
698a8954
YL		 28/* All hns3 tracepoints are defined by the include below, which
29 * must be included exactly once across the whole kernel with
30 * CREATE_TRACE_POINTS defined
31 */
32#define CREATE_TRACE_POINTS
33#include "hns3_trace.h"
76ad4f0e 34
9393eb50 35#define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
5f543a54 36#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 37
b20d7fe5
YL		 38#define hns3_rl_err(fmt, ...) \
39 do { \
40 if (net_ratelimit()) \
41 netdev_err(fmt, ##__VA_ARGS__); \
42 } while (0)
43
f96315f2 44static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
7b763f3f 45
1db9b1bf 46static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 47static const char hns3_driver_string[] =
48 "Hisilicon Ethernet Network Driver for Hip08 Family";
49static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
50static struct hnae3_client client;
51
bb87be87
YL		 52static int debug = -1;
53module_param(debug, int, 0);
54MODULE_PARM_DESC(debug, " Network interface message level setting");
55
907676b1
YL		 56static unsigned int tx_spare_buf_size;
57module_param(tx_spare_buf_size, uint, 0400);
58MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer");
59
7459775e
YL		 60static unsigned int tx_sgl = 1;
61module_param(tx_sgl, uint, 0600);
62MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
63
f7ec554b
YL		 64static bool page_pool_enabled = true;
65module_param(page_pool_enabled, bool, 0400);
66
7459775e
YL		 67#define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
68 sizeof(struct sg_table))
c74e5035 69#define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
7459775e
YL		 70 dma_get_cache_alignment())
71
bb87be87
YL		 72#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
73 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
74
eb977d99
YL		 75#define HNS3_INNER_VLAN_TAG 1
76#define HNS3_OUTER_VLAN_TAG 2
77
36c67349 78#define HNS3_MIN_TX_LEN 33U
d18e8118 79#define HNS3_MIN_TUN_PKT_LEN 65U
36c67349 80
76ad4f0e
S		 81/* hns3_pci_tbl - PCI Device ID Table
82 *
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88static const struct pci_device_id hns3_pci_tbl[] = {
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 100 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
ae6f010c
GH		 101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
102 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
c155e22b
GH		 103 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
104 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
07acf909 105 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e 106 /* required last entry */
7f2d4b7f 107 {0,}
76ad4f0e
S		 108};
109MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
110
79664077
HT		 111#define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \
112 { ptype, \
113 l, \
114 CHECKSUM_##s, \
115 HNS3_L3_TYPE_##t, \
116 1 }
117
118#define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
119 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 }
120
121static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
122 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
123 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP),
124 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP),
125 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP),
126 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL),
127 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL),
128 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL),
129 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM),
130 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL),
131 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
138 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL),
139 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4),
140 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4),
141 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4),
142 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4),
143 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4),
144 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4),
145 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4),
146 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4),
147 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4),
148 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
151 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL),
152 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL),
153 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4),
154 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4),
155 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4),
156 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4),
157 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4),
158 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4),
159 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4),
160 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
161 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6),
162 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6),
163 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6),
164 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6),
165 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6),
166 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6),
167 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6),
168 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
233 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6),
234 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6),
235 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6),
236 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6),
237 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6),
238 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6),
239 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6),
240 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6),
241 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6),
242 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
245 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL),
246 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL),
247 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4),
248 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4),
249 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4),
250 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4),
251 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4),
252 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4),
253 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4),
254 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
255 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6),
256 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6),
257 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6),
258 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6),
259 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6),
260 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6),
261 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6),
262 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
378};
379
380#define HNS3_INVALID_PTYPE \
381 ARRAY_SIZE(hns3_rx_ptype_tbl)
382
ef0c5009 383static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 384{
ef0c5009 385 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 386
fb00331b 387 napi_schedule_irqoff(&tqp_vector->napi);
307ea4ce 388 tqp_vector->event_cnt++;
76ad4f0e
S		 389
390 return IRQ_HANDLED;
391}
392
393static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
394{
395 struct hns3_enet_tqp_vector *tqp_vectors;
396 unsigned int i;
397
398 for (i = 0; i < priv->vector_num; i++) {
399 tqp_vectors = &priv->tqp_vector[i];
400
401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
402 continue;
403
ffab9691 404 /* clear the affinity mask */
874bff0b
PL		 405 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
406
76ad4f0e
S		 407 /* release the irq resource */
408 free_irq(tqp_vectors->vector_irq, tqp_vectors);
409 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
410 }
411}
412
413static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
414{
415 struct hns3_enet_tqp_vector *tqp_vectors;
416 int txrx_int_idx = 0;
417 int rx_int_idx = 0;
418 int tx_int_idx = 0;
419 unsigned int i;
420 int ret;
421
422 for (i = 0; i < priv->vector_num; i++) {
423 tqp_vectors = &priv->tqp_vector[i];
424
425 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
426 continue;
427
428 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
5bffde62
YL		 429 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
430 "%s-%s-%s-%d", hns3_driver_name,
431 pci_name(priv->ae_handle->pdev),
432 "TxRx", txrx_int_idx++);
76ad4f0e
S		 433 txrx_int_idx++;
434 } else if (tqp_vectors->rx_group.ring) {
5bffde62
YL		 435 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
436 "%s-%s-%s-%d", hns3_driver_name,
437 pci_name(priv->ae_handle->pdev),
438 "Rx", rx_int_idx++);
76ad4f0e 439 } else if (tqp_vectors->tx_group.ring) {
5bffde62
YL		 440 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
441 "%s-%s-%s-%d", hns3_driver_name,
442 pci_name(priv->ae_handle->pdev),
443 "Tx", tx_int_idx++);
76ad4f0e
S		 444 } else {
445 /* Skip this unused q_vector */
446 continue;
447 }
448
449 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
450
e99a308d 451 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
76ad4f0e 452 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 453 tqp_vectors->name, tqp_vectors);
76ad4f0e
S		 454 if (ret) {
455 netdev_err(priv->netdev, "request irq(%d) fail\n",
456 tqp_vectors->vector_irq);
d547ecdc 457 hns3_nic_uninit_irq(priv);
76ad4f0e
S		 458 return ret;
459 }
460
874bff0b
PL		 461 irq_set_affinity_hint(tqp_vectors->vector_irq,
462 &tqp_vectors->affinity_mask);
463
76ad4f0e
S		 464 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
465 }
466
467 return 0;
468}
469
470static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
471 u32 mask_en)
472{
473 writel(mask_en, tqp_vector->mask_addr);
474}
475
476static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
477{
478 napi_enable(&tqp_vector->napi);
08a10068 479 enable_irq(tqp_vector->vector_irq);
76ad4f0e
S		 480
481 /* enable vector */
482 hns3_mask_vector_irq(tqp_vector, 1);
483}
484
485static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
486{
487 /* disable vector */
488 hns3_mask_vector_irq(tqp_vector, 0);
489
490 disable_irq(tqp_vector->vector_irq);
491 napi_disable(&tqp_vector->napi);
307ea4ce
HT		 492 cancel_work_sync(&tqp_vector->rx_group.dim.work);
493 cancel_work_sync(&tqp_vector->tx_group.dim.work);
76ad4f0e
S		 494}
495
434776a5
FL		 496void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
497 u32 rl_value)
76ad4f0e 498{
434776a5
FL		 499 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
500
76ad4f0e
S		 501 /* this defines the configuration for RL (Interrupt Rate Limiter).
502 * Rl defines rate of interrupts i.e. number of interrupts-per-second
503 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
504 */
de25bcc4
HT		 505 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
506 !tqp_vector->rx_group.coal.adapt_enable)
434776a5
FL		 507 /* According to the hardware, the range of rl_reg is
508 * 0-59 and the unit is 4.
509 */
510 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
511
512 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
513}
514
515void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
516 u32 gl_value)
517{
5ac84b02 518 u32 new_val;
434776a5 519
5ac84b02
HT		 520 if (tqp_vector->rx_group.coal.unit_1us)
521 new_val = gl_value | HNS3_INT_GL_1US;
522 else
523 new_val = hns3_gl_usec_to_reg(gl_value);
524
525 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
434776a5
FL		 526}
527
528void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
529 u32 gl_value)
530{
5ac84b02
HT		 531 u32 new_val;
532
533 if (tqp_vector->tx_group.coal.unit_1us)
534 new_val = gl_value | HNS3_INT_GL_1US;
535 else
536 new_val = hns3_gl_usec_to_reg(gl_value);
434776a5 537
5ac84b02 538 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 539}
540
91bfae25
HT		 541void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
542 u32 ql_value)
76ad4f0e 543{
91bfae25
HT		 544 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
545}
546
547void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
548 u32 ql_value)
549{
550 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
551}
552
553static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
554 struct hns3_nic_priv *priv)
555{
556 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
557 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
558 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
73a13d8d
HT		 559 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
560 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
91bfae25 561
73a13d8d
HT		 562 tx_coal->adapt_enable = ptx_coal->adapt_enable;
563 rx_coal->adapt_enable = prx_coal->adapt_enable;
91bfae25 564
73a13d8d
HT		 565 tx_coal->int_gl = ptx_coal->int_gl;
566 rx_coal->int_gl = prx_coal->int_gl;
5fd4789a 567
73a13d8d
HT		 568 rx_coal->flow_level = prx_coal->flow_level;
569 tx_coal->flow_level = ptx_coal->flow_level;
5fd4789a 570
5ac84b02
HT		 571 /* device version above V3(include V3), GL can configure 1us
572 * unit, so uses 1us unit.
573 */
574 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
575 tx_coal->unit_1us = 1;
576 rx_coal->unit_1us = 1;
577 }
578
91bfae25
HT		 579 if (ae_dev->dev_specs.int_ql_max) {
580 tx_coal->ql_enable = 1;
581 rx_coal->ql_enable = 1;
582 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
583 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
73a13d8d
HT		 584 tx_coal->int_ql = ptx_coal->int_ql;
585 rx_coal->int_ql = prx_coal->int_ql;
91bfae25 586 }
76ad4f0e
S		 587}
588
91bfae25
HT		 589static void
590hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
591 struct hns3_nic_priv *priv)
dd38c726 592{
91bfae25
HT		 593 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
594 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
dd38c726
YL		 595 struct hnae3_handle *h = priv->ae_handle;
596
91bfae25
HT		 597 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
598 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
dd38c726 599 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
91bfae25
HT		 600
601 if (tx_coal->ql_enable)
602 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
603
604 if (rx_coal->ql_enable)
605 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
dd38c726
YL		 606}
607
9df8f79a
YL		 608static int hns3_nic_set_real_num_queue(struct net_device *netdev)
609{
9780cb97 610 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a 611 struct hnae3_knic_private_info *kinfo = &h->kinfo;
35244430 612 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5a5c9091 613 unsigned int queue_size = kinfo->num_tqps;
a75a8efa
YL		 614 int i, ret;
615
5a5c9091 616 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
a75a8efa
YL		 617 netdev_reset_tc(netdev);
618 } else {
35244430 619 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
a75a8efa
YL		 620 if (ret) {
621 netdev_err(netdev,
622 "netdev_set_num_tc fail, ret=%d!\n", ret);
623 return ret;
624 }
625
a8e76fef 626 for (i = 0; i < tc_info->num_tc; i++)
35244430
JS		 627 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
628 tc_info->tqp_offset[i]);
a75a8efa 629 }
9df8f79a
YL		 630
631 ret = netif_set_real_num_tx_queues(netdev, queue_size);
632 if (ret) {
633 netdev_err(netdev,
9b2f3477 634 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL		 635 return ret;
636 }
637
638 ret = netif_set_real_num_rx_queues(netdev, queue_size);
639 if (ret) {
640 netdev_err(netdev,
641 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
642 return ret;
643 }
644
645 return 0;
646}
647
77e91848 648u16 hns3_get_max_available_channels(struct hnae3_handle *h)
678335a1 649{
0d43bf45 650 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 651
0d43bf45 652 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
35244430 653 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
678335a1 654
0d43bf45 655 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 656}
657
8df0fa91
HT		 658static void hns3_tqp_enable(struct hnae3_queue *tqp)
659{
660 u32 rcb_reg;
661
662 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
663 rcb_reg |= BIT(HNS3_RING_EN_B);
664 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
665}
666
667static void hns3_tqp_disable(struct hnae3_queue *tqp)
668{
669 u32 rcb_reg;
670
671 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
672 rcb_reg &= ~BIT(HNS3_RING_EN_B);
673 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
674}
675
ffab9691
JS		 676static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
677{
678#ifdef CONFIG_RFS_ACCEL
679 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
680 netdev->rx_cpu_rmap = NULL;
681#endif
682}
683
684static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
685{
686#ifdef CONFIG_RFS_ACCEL
687 struct hns3_nic_priv *priv = netdev_priv(netdev);
688 struct hns3_enet_tqp_vector *tqp_vector;
689 int i, ret;
690
691 if (!netdev->rx_cpu_rmap) {
692 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
693 if (!netdev->rx_cpu_rmap)
694 return -ENOMEM;
695 }
696
697 for (i = 0; i < priv->vector_num; i++) {
698 tqp_vector = &priv->tqp_vector[i];
699 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
700 tqp_vector->vector_irq);
701 if (ret) {
702 hns3_free_rx_cpu_rmap(netdev);
703 return ret;
704 }
705 }
706#endif
707 return 0;
708}
709
76ad4f0e
S		 710static int hns3_nic_net_up(struct net_device *netdev)
711{
712 struct hns3_nic_priv *priv = netdev_priv(netdev);
713 struct hnae3_handle *h = priv->ae_handle;
714 int i, j;
715 int ret;
716
7b763f3f
FL		 717 ret = hns3_nic_reset_all_ring(h);
718 if (ret)
719 return ret;
720
b7b585c2
JS		 721 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
722
76ad4f0e
S		 723 /* enable the vectors */
724 for (i = 0; i < priv->vector_num; i++)
725 hns3_vector_enable(&priv->tqp_vector[i]);
726
8df0fa91
HT		 727 /* enable rcb */
728 for (j = 0; j < h->kinfo.num_tqps; j++)
729 hns3_tqp_enable(h->kinfo.tqp[j]);
730
76ad4f0e
S		 731 /* start the ae_dev */
732 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
08a10068
YL		 733 if (ret) {
734 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
735 while (j--)
736 hns3_tqp_disable(h->kinfo.tqp[j]);
8df0fa91 737
08a10068
YL		 738 for (j = i - 1; j >= 0; j--)
739 hns3_vector_disable(&priv->tqp_vector[j]);
740 }
76ad4f0e 741
76ad4f0e
S		 742 return ret;
743}
744
2a73ac3e
YL		 745static void hns3_config_xps(struct hns3_nic_priv *priv)
746{
747 int i;
748
749 for (i = 0; i < priv->vector_num; i++) {
750 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
751 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
752
753 while (ring) {
754 int ret;
755
756 ret = netif_set_xps_queue(priv->netdev,
757 &tqp_vector->affinity_mask,
758 ring->tqp->tqp_index);
759 if (ret)
760 netdev_warn(priv->netdev,
761 "set xps queue failed: %d", ret);
762
763 ring = ring->next;
764 }
765 }
766}
767
76ad4f0e
S		 768static int hns3_nic_net_open(struct net_device *netdev)
769{
8cdb992f 770 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 771 struct hnae3_handle *h = hns3_get_handle(netdev);
772 struct hnae3_knic_private_info *kinfo;
773 int i, ret;
76ad4f0e 774
257e4f29
HT		 775 if (hns3_nic_resetting(netdev))
776 return -EBUSY;
777
5b09e88e
JS		 778 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
779 netdev_warn(netdev, "net open repeatedly!\n");
780 return 0;
781 }
782
76ad4f0e
S		 783 netif_carrier_off(netdev);
784
9df8f79a
YL		 785 ret = hns3_nic_set_real_num_queue(netdev);
786 if (ret)
76ad4f0e 787 return ret;
76ad4f0e
S		 788
789 ret = hns3_nic_net_up(netdev);
790 if (ret) {
9b2f3477 791 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S		 792 return ret;
793 }
794
a75a8efa 795 kinfo = &h->kinfo;
9b2f3477 796 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
35244430 797 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
a75a8efa 798
8cdb992f
JS		 799 if (h->ae_algo->ops->set_timer_task)
800 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
801
2a73ac3e 802 hns3_config_xps(priv);
1c822948
YL		 803
804 netif_dbg(h, drv, netdev, "net open\n");
805
76ad4f0e
S		 806 return 0;
807}
808
f96315f2
HT		 809static void hns3_reset_tx_queue(struct hnae3_handle *h)
810{
811 struct net_device *ndev = h->kinfo.netdev;
812 struct hns3_nic_priv *priv = netdev_priv(ndev);
813 struct netdev_queue *dev_queue;
814 u32 i;
815
816 for (i = 0; i < h->kinfo.num_tqps; i++) {
817 dev_queue = netdev_get_tx_queue(ndev,
5f06b903 818 priv->ring[i].queue_index);
f96315f2
HT		 819 netdev_tx_reset_queue(dev_queue);
820 }
821}
822
76ad4f0e
S		 823static void hns3_nic_net_down(struct net_device *netdev)
824{
825 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 826 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 827 const struct hnae3_ae_ops *ops;
828 int i;
829
7b763f3f
FL		 830 /* disable vectors */
831 for (i = 0; i < priv->vector_num; i++)
832 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 833
834 /* disable rcb */
835 for (i = 0; i < h->kinfo.num_tqps; i++)
836 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 837
76ad4f0e
S		 838 /* stop ae_dev */
839 ops = priv->ae_handle->ae_algo->ops;
840 if (ops->stop)
841 ops->stop(priv->ae_handle);
842
3a30964a
YL		 843 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
844 * during reset process, because driver may not be able
845 * to disable the ring through firmware when downing the netdev.
846 */
847 if (!hns3_nic_resetting(netdev))
f96315f2
HT		 848 hns3_clear_all_ring(priv->ae_handle, false);
849
850 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S		 851}
852
853static int hns3_nic_net_stop(struct net_device *netdev)
854{
ff0699e0 855 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 856 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 857
858 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
859 return 0;
860
1c822948
YL		 861 netif_dbg(h, drv, netdev, "net stop\n");
862
8cdb992f
JS		 863 if (h->ae_algo->ops->set_timer_task)
864 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
865
76ad4f0e 866 netif_carrier_off(netdev);
b416e872 867 netif_tx_disable(netdev);
76ad4f0e
S		 868
869 hns3_nic_net_down(netdev);
870
871 return 0;
872}
873
76ad4f0e
S		 874static int hns3_nic_uc_sync(struct net_device *netdev,
875 const unsigned char *addr)
876{
9780cb97 877 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 878
879 if (h->ae_algo->ops->add_uc_addr)
880 return h->ae_algo->ops->add_uc_addr(h, addr);
881
882 return 0;
883}
884
885static int hns3_nic_uc_unsync(struct net_device *netdev,
886 const unsigned char *addr)
887{
9780cb97 888 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 889
ee4bcd3b
JS		 890 /* need ignore the request of removing device address, because
891 * we store the device address and other addresses of uc list
892 * in the function's mac filter list.
893 */
894 if (ether_addr_equal(addr, netdev->dev_addr))
895 return 0;
896
76ad4f0e
S		 897 if (h->ae_algo->ops->rm_uc_addr)
898 return h->ae_algo->ops->rm_uc_addr(h, addr);
899
900 return 0;
901}
902
903static int hns3_nic_mc_sync(struct net_device *netdev,
904 const unsigned char *addr)
905{
9780cb97 906 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 907
720a8478 908 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 909 return h->ae_algo->ops->add_mc_addr(h, addr);
910
911 return 0;
912}
913
914static int hns3_nic_mc_unsync(struct net_device *netdev,
915 const unsigned char *addr)
916{
9780cb97 917 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 918
720a8478 919 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 920 return h->ae_algo->ops->rm_mc_addr(h, addr);
921
922 return 0;
923}
924
c60edc17
JS		 925static u8 hns3_get_netdev_flags(struct net_device *netdev)
926{
927 u8 flags = 0;
928
2ba30662 929 if (netdev->flags & IFF_PROMISC)
28673b33 930 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
2ba30662
JS		 931 else if (netdev->flags & IFF_ALLMULTI)
932 flags = HNAE3_USER_MPE;
c60edc17
JS		 933
934 return flags;
935}
936
1db9b1bf 937static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 938{
9780cb97 939 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17 940 u8 new_flags;
76ad4f0e 941
c60edc17
JS		 942 new_flags = hns3_get_netdev_flags(netdev);
943
c631c696
JS		 944 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
945 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
c60edc17 946
c60edc17 947 /* User mode Promisc mode enable and vlan filtering is disabled to
c631c696 948 * let all packets in.
c60edc17 949 */
c60edc17 950 h->netdev_flags = new_flags;
c631c696
JS		 951 hns3_request_update_promisc_mode(h);
952}
953
954void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
955{
956 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
957
958 if (ops->request_update_promisc_mode)
959 ops->request_update_promisc_mode(handle);
c60edc17
JS		 960}
961
907676b1
YL		 962static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
963{
964 struct hns3_tx_spare *tx_spare = ring->tx_spare;
965 u32 ntc, ntu;
966
967 /* This smp_load_acquire() pairs with smp_store_release() in
968 * hns3_tx_spare_update() called in tx desc cleaning process.
969 */
970 ntc = smp_load_acquire(&tx_spare->last_to_clean);
971 ntu = tx_spare->next_to_use;
972
973 if (ntc > ntu)
974 return ntc - ntu - 1;
975
976 /* The free tx buffer is divided into two part, so pick the
977 * larger one.
978 */
38b99e1e 979 return max(ntc, tx_spare->len - ntu) - 1;
907676b1
YL		 980}
981
982static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
983{
984 struct hns3_tx_spare *tx_spare = ring->tx_spare;
985
986 if (!tx_spare ||
987 tx_spare->last_to_clean == tx_spare->next_to_clean)
988 return;
989
990 /* This smp_store_release() pairs with smp_load_acquire() in
991 * hns3_tx_spare_space() called in xmit process.
992 */
993 smp_store_release(&tx_spare->last_to_clean,
994 tx_spare->next_to_clean);
995}
996
997static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
998 struct sk_buff *skb,
999 u32 space)
1000{
1001 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1002 skb_headlen(skb);
1003
1004 if (len > ring->tx_copybreak)
1005 return false;
1006
1007 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1008 u64_stats_update_begin(&ring->syncp);
1009 ring->stats.tx_spare_full++;
1010 u64_stats_update_end(&ring->syncp);
1011 return false;
1012 }
1013
1014 return true;
1015}
1016
7459775e
YL		 1017static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1018 struct sk_buff *skb,
1019 u32 space)
1020{
1021 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1022 (!skb_has_frag_list(skb) &&
1023 skb_shinfo(skb)->nr_frags < tx_sgl))
1024 return false;
1025
1026 if (space < HNS3_MAX_SGL_SIZE) {
1027 u64_stats_update_begin(&ring->syncp);
1028 ring->stats.tx_spare_full++;
1029 u64_stats_update_end(&ring->syncp);
1030 return false;
1031 }
1032
1033 return true;
1034}
1035
907676b1
YL		 1036static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1037{
1038 struct hns3_tx_spare *tx_spare;
1039 struct page *page;
1a00197b 1040 u32 alloc_size;
907676b1
YL		 1041 dma_addr_t dma;
1042 int order;
1043
1a00197b
HT		 1044 alloc_size = tx_spare_buf_size ? tx_spare_buf_size :
1045 ring->tqp->handle->kinfo.tx_spare_buf_size;
1046 if (!alloc_size)
907676b1
YL		 1047 return;
1048
1a00197b 1049 order = get_order(alloc_size);
907676b1
YL		 1050 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1051 GFP_KERNEL);
1052 if (!tx_spare) {
1053 /* The driver still work without the tx spare buffer */
1054 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1055 return;
1056 }
1057
1058 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1059 GFP_KERNEL, order);
1060 if (!page) {
1061 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1062 devm_kfree(ring_to_dev(ring), tx_spare);
1063 return;
1064 }
1065
1066 dma = dma_map_page(ring_to_dev(ring), page, 0,
1067 PAGE_SIZE << order, DMA_TO_DEVICE);
1068 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1069 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1070 put_page(page);
1071 devm_kfree(ring_to_dev(ring), tx_spare);
1072 return;
1073 }
1074
1075 tx_spare->dma = dma;
1076 tx_spare->buf = page_address(page);
1077 tx_spare->len = PAGE_SIZE << order;
1078 ring->tx_spare = tx_spare;
1079}
1080
1081/* Use hns3_tx_spare_space() to make sure there is enough buffer
1082 * before calling below function to allocate tx buffer.
1083 */
1084static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1085 unsigned int size, dma_addr_t *dma,
1086 u32 *cb_len)
1087{
1088 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1089 u32 ntu = tx_spare->next_to_use;
1090
1091 size = ALIGN(size, dma_get_cache_alignment());
1092 *cb_len = size;
1093
1094 /* Tx spare buffer wraps back here because the end of
1095 * freed tx buffer is not enough.
1096 */
1097 if (ntu + size > tx_spare->len) {
1098 *cb_len += (tx_spare->len - ntu);
1099 ntu = 0;
1100 }
1101
1102 tx_spare->next_to_use = ntu + size;
1103 if (tx_spare->next_to_use == tx_spare->len)
1104 tx_spare->next_to_use = 0;
1105
1106 *dma = tx_spare->dma + ntu;
1107
1108 return tx_spare->buf + ntu;
1109}
1110
1111static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1112{
1113 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1114
1115 if (len > tx_spare->next_to_use) {
1116 len -= tx_spare->next_to_use;
1117 tx_spare->next_to_use = tx_spare->len - len;
1118 } else {
1119 tx_spare->next_to_use -= len;
1120 }
1121}
1122
1123static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1124 struct hns3_desc_cb *cb)
1125{
1126 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1127 u32 ntc = tx_spare->next_to_clean;
1128 u32 len = cb->length;
1129
1130 tx_spare->next_to_clean += len;
1131
1132 if (tx_spare->next_to_clean >= tx_spare->len) {
1133 tx_spare->next_to_clean -= tx_spare->len;
1134
1135 if (tx_spare->next_to_clean) {
1136 ntc = 0;
1137 len = tx_spare->next_to_clean;
1138 }
1139 }
1140
1141 /* This tx spare buffer is only really reclaimed after calling
1142 * hns3_tx_spare_update(), so it is still safe to use the info in
7459775e
YL		 1143 * the tx buffer to do the dma sync or sg unmapping after
1144 * tx_spare->next_to_clean is moved forword.
907676b1
YL		 1145 */
1146 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1147 dma_addr_t dma = tx_spare->dma + ntc;
1148
1149 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1150 DMA_TO_DEVICE);
7459775e
YL		 1151 } else {
1152 struct sg_table *sgt = tx_spare->buf + ntc;
1153
1154 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1155 DMA_TO_DEVICE);
907676b1
YL		 1156 }
1157}
1158
3e281621 1159static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
811c0830 1160 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
76ad4f0e
S		 1161{
1162 u32 l4_offset, hdr_len;
1163 union l3_hdr_info l3;
1164 union l4_hdr_info l4;
1165 u32 l4_paylen;
1166 int ret;
1167
1168 if (!skb_is_gso(skb))
1169 return 0;
1170
1171 ret = skb_cow_head(skb, 0);
8ae10cfb 1172 if (unlikely(ret < 0))
76ad4f0e
S		 1173 return ret;
1174
1175 l3.hdr = skb_network_header(skb);
1176 l4.hdr = skb_transport_header(skb);
1177
1178 /* Software should clear the IPv4's checksum field when tso is
1179 * needed.
1180 */
1181 if (l3.v4->version == 4)
1182 l3.v4->check = 0;
1183
9b2f3477 1184 /* tunnel packet */
76ad4f0e
S		 1185 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1186 SKB_GSO_GRE_CSUM |
3e281621
HT		 1187 SKB_GSO_UDP_TUNNEL |
1188 SKB_GSO_UDP_TUNNEL_CSUM)) {
76ad4f0e
S		 1189 /* reset l3&l4 pointers from outer to inner headers */
1190 l3.hdr = skb_inner_network_header(skb);
1191 l4.hdr = skb_inner_transport_header(skb);
1192
1193 /* Software should clear the IPv4's checksum field when
1194 * tso is needed.
1195 */
1196 if (l3.v4->version == 4)
1197 l3.v4->check = 0;
1198 }
1199
9b2f3477 1200 /* normal or tunnel packet */
76ad4f0e 1201 l4_offset = l4.hdr - skb->data;
76ad4f0e 1202
9b2f3477 1203 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e 1204 l4_paylen = skb->len - l4_offset;
0692cfe9
HT		 1205
1206 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1207 hdr_len = sizeof(*l4.udp) + l4_offset;
1208 csum_replace_by_diff(&l4.udp->check,
1209 (__force __wsum)htonl(l4_paylen));
1210 } else {
1211 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1212 csum_replace_by_diff(&l4.tcp->check,
1213 (__force __wsum)htonl(l4_paylen));
1214 }
76ad4f0e 1215
811c0830
YL		 1216 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1217
76ad4f0e 1218 /* find the txbd field values */
3e281621 1219 *paylen_fdop_ol4cs = skb->len - hdr_len;
cde4ffad 1220 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e 1221
3e281621
HT		 1222 /* offload outer UDP header checksum */
1223 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1224 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1225
76ad4f0e
S		 1226 /* get MSS for TSO */
1227 *mss = skb_shinfo(skb)->gso_size;
1228
698a8954
YL		 1229 trace_hns3_tso(skb);
1230
76ad4f0e
S		 1231 return 0;
1232}
1233
1898d4e4
S		 1234static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1235 u8 *il4_proto)
76ad4f0e 1236{
1a6e552d 1237 union l3_hdr_info l3;
76ad4f0e
S		 1238 unsigned char *l4_hdr;
1239 unsigned char *exthdr;
1240 u8 l4_proto_tmp;
1241 __be16 frag_off;
1242
1243 /* find outer header point */
1244 l3.hdr = skb_network_header(skb);
35f58fd7 1245 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 1246
1247 if (skb->protocol == htons(ETH_P_IPV6)) {
1248 exthdr = l3.hdr + sizeof(*l3.v6);
1249 l4_proto_tmp = l3.v6->nexthdr;
1250 if (l4_hdr != exthdr)
1251 ipv6_skip_exthdr(skb, exthdr - skb->data,
1252 &l4_proto_tmp, &frag_off);
1253 } else if (skb->protocol == htons(ETH_P_IP)) {
1254 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 1255 } else {
1256 return -EINVAL;
76ad4f0e
S		 1257 }
1258
1259 *ol4_proto = l4_proto_tmp;
1260
1261 /* tunnel packet */
1262 if (!skb->encapsulation) {
1263 *il4_proto = 0;
1898d4e4 1264 return 0;
76ad4f0e
S		 1265 }
1266
1267 /* find inner header point */
1268 l3.hdr = skb_inner_network_header(skb);
1269 l4_hdr = skb_inner_transport_header(skb);
1270
1271 if (l3.v6->version == 6) {
1272 exthdr = l3.hdr + sizeof(*l3.v6);
1273 l4_proto_tmp = l3.v6->nexthdr;
1274 if (l4_hdr != exthdr)
1275 ipv6_skip_exthdr(skb, exthdr - skb->data,
1276 &l4_proto_tmp, &frag_off);
1277 } else if (l3.v4->version == 4) {
1278 l4_proto_tmp = l3.v4->protocol;
1279 }
1280
1281 *il4_proto = l4_proto_tmp;
1898d4e4
S		 1282
1283 return 0;
76ad4f0e
S		 1284}
1285
3db084d2
YL		 1286/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1287 * and it is udp packet, which has a dest port as the IANA assigned.
1288 * the hardware is expected to do the checksum offload, but the
1289 * hardware will not do the checksum offload when udp dest port is
905416f1 1290 * 4789, 4790 or 6081.
3db084d2
YL		 1291 */
1292static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1293{
ade36cce
HT		 1294 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1295 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1a6e552d 1296 union l4_hdr_info l4;
3db084d2 1297
ade36cce
HT		 1298 /* device version above V3(include V3), the hardware can
1299 * do this checksum offload.
1300 */
1301 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1302 return false;
1303
3db084d2
YL		 1304 l4.hdr = skb_transport_header(skb);
1305
bea96410 1306 if (!(!skb->encapsulation &&
a156998f 1307 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
905416f1
HC		 1308 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1309 l4.udp->dest == htons(4790))))
3db084d2
YL		 1310 return false;
1311
3db084d2
YL		 1312 return true;
1313}
1314
757cd1e4
YL		 1315static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1316 u32 *ol_type_vlan_len_msec)
76ad4f0e 1317{
757cd1e4
YL		 1318 u32 l2_len, l3_len, l4_len;
1319 unsigned char *il2_hdr;
1a6e552d 1320 union l3_hdr_info l3;
757cd1e4 1321 union l4_hdr_info l4;
76ad4f0e
S		 1322
1323 l3.hdr = skb_network_header(skb);
757cd1e4 1324 l4.hdr = skb_transport_header(skb);
76ad4f0e 1325
757cd1e4
YL		 1326 /* compute OL2 header size, defined in 2 Bytes */
1327 l2_len = l3.hdr - skb->data;
1328 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1329
1330 /* compute OL3 header size, defined in 4 Bytes */
1331 l3_len = l4.hdr - l3.hdr;
1332 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 1333
757cd1e4 1334 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 1335 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL		 1336 l4_len = il2_hdr - l4.hdr;
1337 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1338
1339 /* define outer network header type */
1340 if (skb->protocol == htons(ETH_P_IP)) {
1341 if (skb_is_gso(skb))
cde4ffad 1342 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 1343 HNS3_TXD_OL3T_S,
1344 HNS3_OL3T_IPV4_CSUM);
1345 else
cde4ffad 1346 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 1347 HNS3_TXD_OL3T_S,
1348 HNS3_OL3T_IPV4_NO_CSUM);
757cd1e4
YL		 1349 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1350 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1351 HNS3_OL3T_IPV6);
1352 }
1353
1354 if (ol4_proto == IPPROTO_UDP)
1355 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1356 HNS3_TUN_MAC_IN_UDP);
1357 else if (ol4_proto == IPPROTO_GRE)
1358 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1359 HNS3_TUN_NVGRE);
1360}
1361
1362static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1363 u8 il4_proto, u32 *type_cs_vlan_tso,
1364 u32 *ol_type_vlan_len_msec)
1365{
c264ed44 1366 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 1367 u32 l4_proto = ol4_proto;
1368 union l4_hdr_info l4;
1369 union l3_hdr_info l3;
1370 u32 l2_len, l3_len;
1371
1372 l4.hdr = skb_transport_header(skb);
1373 l3.hdr = skb_network_header(skb);
1374
1375 /* handle encapsulation skb */
1376 if (skb->encapsulation) {
1377 /* If this is a not UDP/GRE encapsulation skb */
1378 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 1379 /* drop the skb tunnel packet if hardware don't support,
1380 * because hardware can't calculate csum when TSO.
1381 */
1382 if (skb_is_gso(skb))
1383 return -EDOM;
1384
1385 /* the stack computes the IP header already,
1386 * driver calculate l4 checksum when not TSO.
1387 */
9bb5a495 1388 return skb_checksum_help(skb);
76ad4f0e
S		 1389 }
1390
757cd1e4
YL		 1391 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1392
1393 /* switch to inner header */
1394 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 1395 l3.hdr = skb_inner_network_header(skb);
757cd1e4 1396 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 1397 l4_proto = il4_proto;
1398 }
1399
1400 if (l3.v4->version == 4) {
cde4ffad
YL		 1401 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1402 HNS3_L3T_IPV4);
76ad4f0e
S		 1403
1404 /* the stack computes the IP header already, the only time we
1405 * need the hardware to recompute it is in the case of TSO.
1406 */
1407 if (skb_is_gso(skb))
cde4ffad 1408 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 1409 } else if (l3.v6->version == 6) {
cde4ffad
YL		 1410 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1411 HNS3_L3T_IPV6);
76ad4f0e
S		 1412 }
1413
757cd1e4
YL		 1414 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1415 l2_len = l3.hdr - l2_hdr;
1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1417
1418 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1419 l3_len = l4.hdr - l3.hdr;
1420 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1421
1422 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 1423 switch (l4_proto) {
1424 case IPPROTO_TCP:
cde4ffad
YL		 1425 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1426 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1427 HNS3_L4T_TCP);
757cd1e4
YL		 1428 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1429 l4.tcp->doff);
76ad4f0e
S		 1430 break;
1431 case IPPROTO_UDP:
d18e8118
YM		 1432 if (hns3_tunnel_csum_bug(skb)) {
1433 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1434
1435 return ret ? ret : skb_checksum_help(skb);
1436 }
3db084d2 1437
cde4ffad
YL		 1438 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1439 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1440 HNS3_L4T_UDP);
757cd1e4
YL		 1441 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1442 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 1443 break;
1444 case IPPROTO_SCTP:
cde4ffad
YL		 1445 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1446 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1447 HNS3_L4T_SCTP);
757cd1e4
YL		 1448 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1449 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 1450 break;
1451 default:
1452 /* drop the skb tunnel packet if hardware don't support,
1453 * because hardware can't calculate csum when TSO.
1454 */
1455 if (skb_is_gso(skb))
1456 return -EDOM;
1457
1458 /* the stack computes the IP header already,
1459 * driver calculate l4 checksum when not TSO.
1460 */
9bb5a495 1461 return skb_checksum_help(skb);
76ad4f0e
S		 1462 }
1463
1464 return 0;
1465}
1466
eb977d99
YL		 1467static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1468 struct sk_buff *skb)
9699cffe 1469{
44e626f7 1470 struct hnae3_handle *handle = tx_ring->tqp->handle;
592b0179 1471 struct hnae3_ae_dev *ae_dev;
eb977d99
YL		 1472 struct vlan_ethhdr *vhdr;
1473 int rc;
1474
1475 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1476 skb_vlan_tag_present(skb)))
1477 return 0;
44e626f7 1478
592b0179
GL		 1479 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1480 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1481 * will cause RAS error.
44e626f7 1482 */
592b0179 1483 ae_dev = pci_get_drvdata(handle->pdev);
44e626f7 1484 if (unlikely(skb_vlan_tagged_multi(skb) &&
592b0179 1485 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
44e626f7
JS		 1486 handle->port_base_vlan_state ==
1487 HNAE3_PORT_BASE_VLAN_ENABLE))
1488 return -EINVAL;
1489
9699cffe 1490 if (skb->protocol == htons(ETH_P_8021Q) &&
eb977d99 1491 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
9699cffe
PL		 1492 /* When HW VLAN acceleration is turned off, and the stack
1493 * sets the protocol to 802.1q, the driver just need to
1494 * set the protocol to the encapsulated ethertype.
1495 */
1496 skb->protocol = vlan_get_protocol(skb);
1497 return 0;
1498 }
1499
1500 if (skb_vlan_tag_present(skb)) {
9699cffe
PL		 1501 /* Based on hw strategy, use out_vtag in two layer tag case,
1502 * and use inner_vtag in one tag case.
1503 */
eb977d99
YL		 1504 if (skb->protocol == htons(ETH_P_8021Q) &&
1505 handle->port_base_vlan_state ==
1506 HNAE3_PORT_BASE_VLAN_DISABLE)
1507 rc = HNS3_OUTER_VLAN_TAG;
1508 else
1509 rc = HNS3_INNER_VLAN_TAG;
1510
1511 skb->protocol = vlan_get_protocol(skb);
1512 return rc;
9699cffe
PL		 1513 }
1514
eb977d99
YL		 1515 rc = skb_cow_head(skb, 0);
1516 if (unlikely(rc < 0))
1517 return rc;
1518
1519 vhdr = (struct vlan_ethhdr *)skb->data;
1520 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1521 & VLAN_PRIO_MASK);
1522
9699cffe
PL		 1523 skb->protocol = vlan_get_protocol(skb);
1524 return 0;
1525}
1526
66d52f3b
HT		 1527/* check if the hardware is capable of checksum offloading */
1528static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1529{
1530 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1531
1532 /* Kindly note, due to backward compatibility of the TX descriptor,
1533 * HW checksum of the non-IP packets and GSO packets is handled at
1534 * different place in the following code
1535 */
b9046e88 1536 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
66d52f3b
HT		 1537 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1538 return false;
1539
1540 return true;
1541}
1542
eb977d99 1543static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
811c0830
YL		 1544 struct sk_buff *skb, struct hns3_desc *desc,
1545 struct hns3_desc_cb *desc_cb)
eb977d99
YL		 1546{
1547 u32 ol_type_vlan_len_msec = 0;
3e281621 1548 u32 paylen_ol4cs = skb->len;
eb977d99 1549 u32 type_cs_vlan_tso = 0;
66d52f3b 1550 u16 mss_hw_csum = 0;
eb977d99
YL		 1551 u16 inner_vtag = 0;
1552 u16 out_vtag = 0;
eb977d99
YL		 1553 int ret;
1554
1555 ret = hns3_handle_vtags(ring, skb);
1556 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1557 u64_stats_update_begin(&ring->syncp);
1558 ring->stats.tx_vlan_err++;
1559 u64_stats_update_end(&ring->syncp);
eb977d99
YL		 1560 return ret;
1561 } else if (ret == HNS3_INNER_VLAN_TAG) {
1562 inner_vtag = skb_vlan_tag_get(skb);
1563 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1564 VLAN_PRIO_MASK;
1565 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1566 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1567 out_vtag = skb_vlan_tag_get(skb);
1568 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1569 VLAN_PRIO_MASK;
1570 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1571 1);
1572 }
1573
811c0830
YL		 1574 desc_cb->send_bytes = skb->len;
1575
eb977d99
YL		 1576 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1577 u8 ol4_proto, il4_proto;
1578
66d52f3b
HT		 1579 if (hns3_check_hw_tx_csum(skb)) {
1580 /* set checksum start and offset, defined in 2 Bytes */
1581 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1582 skb_checksum_start_offset(skb) >> 1);
1583 hns3_set_field(ol_type_vlan_len_msec,
1584 HNS3_TXD_CSUM_OFFSET_S,
1585 skb->csum_offset >> 1);
1586 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1587 goto out_hw_tx_csum;
1588 }
1589
eb977d99
YL		 1590 skb_reset_mac_len(skb);
1591
1592 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
8ae10cfb 1593 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1594 u64_stats_update_begin(&ring->syncp);
1595 ring->stats.tx_l4_proto_err++;
1596 u64_stats_update_end(&ring->syncp);
eb977d99 1597 return ret;
b20d7fe5 1598 }
eb977d99
YL		 1599
1600 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1601 &type_cs_vlan_tso,
1602 &ol_type_vlan_len_msec);
8ae10cfb 1603 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1604 u64_stats_update_begin(&ring->syncp);
1605 ring->stats.tx_l2l3l4_err++;
1606 u64_stats_update_end(&ring->syncp);
eb977d99 1607 return ret;
b20d7fe5 1608 }
eb977d99 1609
3e281621 1610 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum,
811c0830 1611 &type_cs_vlan_tso, &desc_cb->send_bytes);
8ae10cfb 1612 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1613 u64_stats_update_begin(&ring->syncp);
1614 ring->stats.tx_tso_err++;
1615 u64_stats_update_end(&ring->syncp);
eb977d99 1616 return ret;
b20d7fe5 1617 }
eb977d99
YL		 1618 }
1619
66d52f3b 1620out_hw_tx_csum:
eb977d99
YL		 1621 /* Set txbd */
1622 desc->tx.ol_type_vlan_len_msec =
1623 cpu_to_le32(ol_type_vlan_len_msec);
1624 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
3e281621 1625 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs);
66d52f3b 1626 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum);
eb977d99
YL		 1627 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1628 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1629
1630 return 0;
1631}
1632
8677d78c
YL		 1633static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1634 unsigned int size)
76ad4f0e 1635{
8ae10cfb
YL		 1636#define HNS3_LIKELY_BD_NUM 1
1637
76ad4f0e 1638 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1e8a7977 1639 unsigned int frag_buf_num;
47e7b13b 1640 int k, sizeoflast;
bcdb12b7 1641
ceca4a5e 1642 if (likely(size <= HNS3_MAX_BD_SIZE)) {
ceca4a5e
YL		 1643 desc->addr = cpu_to_le64(dma);
1644 desc->tx.send_size = cpu_to_le16(size);
ceca4a5e 1645 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1646 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
ceca4a5e 1647
698a8954 1648 trace_hns3_tx_desc(ring, ring->next_to_use);
ceca4a5e 1649 ring_ptr_move_fw(ring, next_to_use);
8ae10cfb 1650 return HNS3_LIKELY_BD_NUM;
ceca4a5e
YL		 1651 }
1652
5f543a54 1653 frag_buf_num = hns3_tx_bd_count(size);
48ae74c9 1654 sizeoflast = size % HNS3_MAX_BD_SIZE;
1e8a7977
FL		 1655 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1656
1657 /* When frag size is bigger than hardware limit, split this frag */
1658 for (k = 0; k < frag_buf_num; k++) {
1e8a7977
FL		 1659 /* now, fill the descriptor */
1660 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1661 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1662 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977 1663 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1664 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1e8a7977 1665
698a8954 1666 trace_hns3_tx_desc(ring, ring->next_to_use);
9b2f3477 1667 /* move ring pointer to next */
1e8a7977
FL		 1668 ring_ptr_move_fw(ring, next_to_use);
1669
1e8a7977
FL		 1670 desc = &ring->desc[ring->next_to_use];
1671 }
76ad4f0e 1672
8ae10cfb 1673 return frag_buf_num;
76ad4f0e
S		 1674}
1675
8677d78c
YL		 1676static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1677 unsigned int type)
1678{
1679 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1680 struct device *dev = ring_to_dev(ring);
1681 unsigned int size;
1682 dma_addr_t dma;
1683
1684 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1685 struct sk_buff *skb = (struct sk_buff *)priv;
1686
1687 size = skb_headlen(skb);
1688 if (!size)
1689 return 0;
1690
1691 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
907676b1
YL		 1692 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1693 /* Head data has been filled in hns3_handle_tx_bounce(),
1694 * just return 0 here.
1695 */
1696 return 0;
8677d78c
YL		 1697 } else {
1698 skb_frag_t *frag = (skb_frag_t *)priv;
1699
1700 size = skb_frag_size(frag);
1701 if (!size)
1702 return 0;
1703
1704 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1705 }
1706
1707 if (unlikely(dma_mapping_error(dev, dma))) {
1708 u64_stats_update_begin(&ring->syncp);
1709 ring->stats.sw_err_cnt++;
1710 u64_stats_update_end(&ring->syncp);
1711 return -ENOMEM;
1712 }
1713
1714 desc_cb->priv = priv;
1715 desc_cb->length = size;
1716 desc_cb->dma = dma;
1717 desc_cb->type = type;
1718
1719 return hns3_fill_desc(ring, dma, size);
1720}
1721
8ae10cfb
YL		 1722static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1723 unsigned int bd_num)
76ad4f0e 1724{
8ae10cfb 1725 unsigned int size;
42611b70 1726 int i;
76ad4f0e 1727
8ae10cfb
YL		 1728 size = skb_headlen(skb);
1729 while (size > HNS3_MAX_BD_SIZE) {
1730 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1731 size -= HNS3_MAX_BD_SIZE;
1732
1733 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1734 return bd_num;
1735 }
76ad4f0e 1736
8ae10cfb
YL		 1737 if (size) {
1738 bd_size[bd_num++] = size;
1739 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1740 return bd_num;
1741 }
76ad4f0e 1742
3d5f3741 1743 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
d7840976 1744 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8ae10cfb
YL		 1745 size = skb_frag_size(frag);
1746 if (!size)
1747 continue;
1748
1749 while (size > HNS3_MAX_BD_SIZE) {
1750 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1751 size -= HNS3_MAX_BD_SIZE;
1752
1753 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1754 return bd_num;
1755 }
1756
1757 bd_size[bd_num++] = size;
1758 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1759 return bd_num;
1760 }
1761
1762 return bd_num;
1763}
1764
fd665b3d 1765static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
d5d5e019
YL		 1766 u8 max_non_tso_bd_num, unsigned int bd_num,
1767 unsigned int recursion_level)
8ae10cfb 1768{
d5d5e019
YL		 1769#define HNS3_MAX_RECURSION_LEVEL 24
1770
8ae10cfb 1771 struct sk_buff *frag_skb;
8ae10cfb
YL		 1772
1773 /* If the total len is within the max bd limit */
d5d5e019
YL		 1774 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1775 !skb_has_frag_list(skb) &&
fd665b3d 1776 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
8ae10cfb
YL		 1777 return skb_shinfo(skb)->nr_frags + 1U;
1778
d5d5e019
YL		 1779 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1780 return UINT_MAX;
8ae10cfb
YL		 1781
1782 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
8ae10cfb
YL		 1783 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1784 return bd_num;
1785
1786 skb_walk_frags(skb, frag_skb) {
d5d5e019
YL		 1787 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1788 bd_num, recursion_level + 1);
8ae10cfb
YL		 1789 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1790 return bd_num;
3d5f3741 1791 }
76ad4f0e 1792
3d5f3741 1793 return bd_num;
76ad4f0e
S		 1794}
1795
db4970aa
YL		 1796static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1797{
1798 if (!skb->encapsulation)
1799 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1800
1801 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1802}
1803
fd665b3d
HT		 1804/* HW need every continuous max_non_tso_bd_num buffer data to be larger
1805 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1806 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1807 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1808 * than MSS except the last max_non_tso_bd_num - 1 frags.
db4970aa 1809 */
8ae10cfb 1810static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
fd665b3d 1811 unsigned int bd_num, u8 max_non_tso_bd_num)
db4970aa 1812{
db4970aa
YL		 1813 unsigned int tot_len = 0;
1814 int i;
1815
fd665b3d 1816 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
8ae10cfb 1817 tot_len += bd_size[i];
db4970aa 1818
fd665b3d
HT		 1819 /* ensure the first max_non_tso_bd_num frags is greater than
1820 * mss + header
1821 */
1822 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
8ae10cfb 1823 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
db4970aa
YL		 1824 return true;
1825
fd665b3d
HT		 1826 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1827 * than mss except the last one.
8ae10cfb 1828 */
fd665b3d 1829 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
8ae10cfb 1830 tot_len -= bd_size[i];
fd665b3d 1831 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
db4970aa
YL		 1832
1833 if (tot_len < skb_shinfo(skb)->gso_size)
1834 return true;
1835 }
1836
1837 return false;
1838}
1839
698a8954
YL		 1840void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1841{
9d8d5a36 1842 int i;
698a8954
YL		 1843
1844 for (i = 0; i < MAX_SKB_FRAGS; i++)
1845 size[i] = skb_frag_size(&shinfo->frags[i]);
1846}
1847
d5d5e019
YL		 1848static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1849 struct sk_buff *skb,
1850 u8 max_non_tso_bd_num,
1851 unsigned int bd_num)
1852{
1853 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1854 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1855 */
1856 if (bd_num == UINT_MAX) {
1857 u64_stats_update_begin(&ring->syncp);
1858 ring->stats.over_max_recursion++;
1859 u64_stats_update_end(&ring->syncp);
1860 return -ENOMEM;
1861 }
1862
1863 /* The skb->len has exceeded the hw limitation, linearization
1864 * will not help.
1865 */
1866 if (skb->len > HNS3_MAX_TSO_SIZE ||
1867 (!skb_is_gso(skb) && skb->len >
1868 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) {
1869 u64_stats_update_begin(&ring->syncp);
1870 ring->stats.hw_limitation++;
1871 u64_stats_update_end(&ring->syncp);
1872 return -ENOMEM;
1873 }
1874
1875 if (__skb_linearize(skb)) {
1876 u64_stats_update_begin(&ring->syncp);
1877 ring->stats.sw_err_cnt++;
1878 u64_stats_update_end(&ring->syncp);
1879 return -ENOMEM;
1880 }
1881
1882 return 0;
1883}
1884
3d5f3741 1885static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
2a597eff 1886 struct net_device *netdev,
d1a37ded 1887 struct sk_buff *skb)
76ad4f0e 1888{
2a597eff 1889 struct hns3_nic_priv *priv = netdev_priv(netdev);
fd665b3d 1890 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
8ae10cfb 1891 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
42611b70 1892 unsigned int bd_num;
76ad4f0e 1893
d5d5e019 1894 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
fd665b3d 1895 if (unlikely(bd_num > max_non_tso_bd_num)) {
8ae10cfb 1896 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
fd665b3d
HT		 1897 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1898 max_non_tso_bd_num)) {
6ad595bc 1899 trace_hns3_over_max_bd(skb);
db4970aa 1900 goto out;
698a8954 1901 }
db4970aa 1902
d5d5e019
YL		 1903 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num,
1904 bd_num))
51e8439f 1905 return -ENOMEM;
3d5f3741 1906
d1a37ded 1907 bd_num = hns3_tx_bd_count(skb->len);
42611b70 1908
3d5f3741
YL		 1909 u64_stats_update_begin(&ring->syncp);
1910 ring->stats.tx_copy++;
1911 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1912 }
1913
db4970aa 1914out:
2a597eff
YL		 1915 if (likely(ring_space(ring) >= bd_num))
1916 return bd_num;
76ad4f0e 1917
2a597eff
YL		 1918 netif_stop_subqueue(netdev, ring->queue_index);
1919 smp_mb(); /* Memory barrier before checking ring_space */
1920
1921 /* Start queue in case hns3_clean_tx_ring has just made room
1922 * available and has not seen the queue stopped state performed
1923 * by netif_stop_subqueue above.
1924 */
1925 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1926 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1927 netif_start_subqueue(netdev, ring->queue_index);
1928 return bd_num;
1929 }
1930
d5d5e019
YL		 1931 u64_stats_update_begin(&ring->syncp);
1932 ring->stats.tx_busy++;
1933 u64_stats_update_end(&ring->syncp);
1934
2a597eff 1935 return -EBUSY;
76ad4f0e
S		 1936}
1937
ba3f808f 1938static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1939{
1940 struct device *dev = ring_to_dev(ring);
1941 unsigned int i;
1942
1943 for (i = 0; i < ring->desc_num; i++) {
8ceca59f 1944 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
26f1ccdf 1945 struct hns3_desc_cb *desc_cb;
8ceca59f
YL		 1946
1947 memset(desc, 0, sizeof(*desc));
1948
76ad4f0e
S		 1949 /* check if this is where we started */
1950 if (ring->next_to_use == next_to_use_orig)
1951 break;
1952
aa9d22dd
YL		 1953 /* rollback one */
1954 ring_ptr_move_bw(ring, next_to_use);
1955
26f1ccdf
YL		 1956 desc_cb = &ring->desc_cb[ring->next_to_use];
1957
1958 if (!desc_cb->dma)
8ceca59f
YL		 1959 continue;
1960
76ad4f0e 1961 /* unmap the descriptor dma address */
26f1ccdf
YL		 1962 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
1963 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
1964 DMA_TO_DEVICE);
907676b1
YL		 1965 else if (desc_cb->type &
1966 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
1967 hns3_tx_spare_rollback(ring, desc_cb->length);
26f1ccdf
YL		 1968 else if (desc_cb->length)
1969 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
76ad4f0e
S		 1970 DMA_TO_DEVICE);
1971
26f1ccdf
YL		 1972 desc_cb->length = 0;
1973 desc_cb->dma = 0;
1974 desc_cb->type = DESC_TYPE_UNKNOWN;
76ad4f0e
S		 1975 }
1976}
1977
8ae10cfb 1978static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
26f1ccdf 1979 struct sk_buff *skb, unsigned int type)
8ae10cfb 1980{
d5d5e019 1981 struct sk_buff *frag_skb;
8ae10cfb
YL		 1982 int i, ret, bd_num = 0;
1983
8677d78c
YL		 1984 ret = hns3_map_and_fill_desc(ring, skb, type);
1985 if (unlikely(ret < 0))
1986 return ret;
8ae10cfb 1987
8677d78c 1988 bd_num += ret;
8ae10cfb
YL		 1989
1990 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1991 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1992
8677d78c 1993 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
8ae10cfb
YL		 1994 if (unlikely(ret < 0))
1995 return ret;
1996
1997 bd_num += ret;
1998 }
1999
d5d5e019
YL		 2000 skb_walk_frags(skb, frag_skb) {
2001 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2002 DESC_TYPE_FRAGLIST_SKB);
2003 if (unlikely(ret < 0))
2004 return ret;
2005
2006 bd_num += ret;
2007 }
2008
8ae10cfb
YL		 2009 return bd_num;
2010}
2011
f6061a05
YL		 2012static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2013 bool doorbell)
2014{
2015 ring->pending_buf += num;
2016
2017 if (!doorbell) {
2018 u64_stats_update_begin(&ring->syncp);
2019 ring->stats.tx_more++;
2020 u64_stats_update_end(&ring->syncp);
2021 return;
2022 }
2023
2024 if (!ring->pending_buf)
2025 return;
2026
48ee56fd
YL		 2027 writel(ring->pending_buf,
2028 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
f6061a05 2029 ring->pending_buf = 0;
20d06ca2 2030 WRITE_ONCE(ring->last_to_use, ring->next_to_use);
f6061a05
YL		 2031}
2032
0bf5eb78
HT		 2033static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2034 struct hns3_desc *desc)
2035{
2036 struct hnae3_handle *h = hns3_get_handle(netdev);
2037
2038 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2039 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2040 return;
2041
2042 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2043}
2044
907676b1
YL		 2045static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2046 struct sk_buff *skb)
2047{
2048 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2049 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2050 unsigned int size = skb_headlen(skb);
2051 dma_addr_t dma;
2052 int bd_num = 0;
2053 u32 cb_len;
2054 void *buf;
2055 int ret;
2056
2057 if (skb->len <= ring->tx_copybreak) {
2058 size = skb->len;
2059 type = DESC_TYPE_BOUNCE_ALL;
2060 }
2061
2062 /* hns3_can_use_tx_bounce() is called to ensure the below
2063 * function can always return the tx buffer.
2064 */
2065 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2066
2067 ret = skb_copy_bits(skb, 0, buf, size);
2068 if (unlikely(ret < 0)) {
2069 hns3_tx_spare_rollback(ring, cb_len);
2070 u64_stats_update_begin(&ring->syncp);
2071 ring->stats.copy_bits_err++;
2072 u64_stats_update_end(&ring->syncp);
2073 return ret;
2074 }
2075
2076 desc_cb->priv = skb;
2077 desc_cb->length = cb_len;
2078 desc_cb->dma = dma;
2079 desc_cb->type = type;
2080
2081 bd_num += hns3_fill_desc(ring, dma, size);
2082
2083 if (type == DESC_TYPE_BOUNCE_HEAD) {
2084 ret = hns3_fill_skb_to_desc(ring, skb,
2085 DESC_TYPE_BOUNCE_HEAD);
2086 if (unlikely(ret < 0))
2087 return ret;
2088
2089 bd_num += ret;
2090 }
2091
2092 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2093 DMA_TO_DEVICE);
2094
2095 u64_stats_update_begin(&ring->syncp);
2096 ring->stats.tx_bounce++;
2097 u64_stats_update_end(&ring->syncp);
2098 return bd_num;
2099}
2100
7459775e
YL		 2101static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2102 struct sk_buff *skb)
2103{
2104 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2105 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2106 struct sg_table *sgt;
2107 int i, bd_num = 0;
2108 dma_addr_t dma;
2109 u32 cb_len;
2110 int nents;
2111
2112 if (skb_has_frag_list(skb))
2113 nfrag = HNS3_MAX_TSO_BD_NUM;
2114
2115 /* hns3_can_use_tx_sgl() is called to ensure the below
2116 * function can always return the tx buffer.
2117 */
2118 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2119 &dma, &cb_len);
2120
2121 /* scatterlist follows by the sg table */
2122 sgt->sgl = (struct scatterlist *)(sgt + 1);
2123 sg_init_table(sgt->sgl, nfrag);
2124 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2125 if (unlikely(nents < 0)) {
2126 hns3_tx_spare_rollback(ring, cb_len);
2127 u64_stats_update_begin(&ring->syncp);
2128 ring->stats.skb2sgl_err++;
2129 u64_stats_update_end(&ring->syncp);
2130 return -ENOMEM;
2131 }
2132
2133 sgt->orig_nents = nents;
2134 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2135 DMA_TO_DEVICE);
2136 if (unlikely(!sgt->nents)) {
2137 hns3_tx_spare_rollback(ring, cb_len);
2138 u64_stats_update_begin(&ring->syncp);
2139 ring->stats.map_sg_err++;
2140 u64_stats_update_end(&ring->syncp);
2141 return -ENOMEM;
2142 }
2143
2144 desc_cb->priv = skb;
2145 desc_cb->length = cb_len;
2146 desc_cb->dma = dma;
2147 desc_cb->type = DESC_TYPE_SGL_SKB;
2148
2149 for (i = 0; i < sgt->nents; i++)
2150 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2151 sg_dma_len(sgt->sgl + i));
2152
2153 u64_stats_update_begin(&ring->syncp);
2154 ring->stats.tx_sgl++;
2155 u64_stats_update_end(&ring->syncp);
2156
2157 return bd_num;
2158}
2159
907676b1
YL		 2160static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2161 struct sk_buff *skb)
2162{
2163 u32 space;
2164
2165 if (!ring->tx_spare)
2166 goto out;
2167
2168 space = hns3_tx_spare_space(ring);
2169
7459775e
YL		 2170 if (hns3_can_use_tx_sgl(ring, skb, space))
2171 return hns3_handle_tx_sgl(ring, skb);
2172
907676b1
YL		 2173 if (hns3_can_use_tx_bounce(ring, skb, space))
2174 return hns3_handle_tx_bounce(ring, skb);
2175
2176out:
2177 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2178}
2179
d43e5aca 2180netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 2181{
2182 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f06b903 2183 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
811c0830 2184 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
76ad4f0e 2185 struct netdev_queue *dev_queue;
8ae10cfb 2186 int pre_ntu, next_to_use_head;
f6061a05 2187 bool doorbell;
76ad4f0e 2188 int ret;
76ad4f0e 2189
36c67349 2190 /* Hardware can only handle short frames above 32 bytes */
f6061a05
YL		 2191 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2192 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
97b9e5c1
YL		 2193
2194 u64_stats_update_begin(&ring->syncp);
2195 ring->stats.sw_err_cnt++;
2196 u64_stats_update_end(&ring->syncp);
2197
36c67349 2198 return NETDEV_TX_OK;
f6061a05 2199 }
36c67349 2200
76ad4f0e
S		 2201 /* Prefetch the data used later */
2202 prefetch(skb->data);
2203
d1a37ded 2204 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
8ae10cfb
YL		 2205 if (unlikely(ret <= 0)) {
2206 if (ret == -EBUSY) {
f6061a05 2207 hns3_tx_doorbell(ring, 0, true);
2a597eff 2208 return NETDEV_TX_BUSY;
3d5f3741 2209 }
76ad4f0e 2210
8ae10cfb 2211 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
76ad4f0e 2212 goto out_err_tx_ok;
76ad4f0e
S		 2213 }
2214
76ad4f0e
S		 2215 next_to_use_head = ring->next_to_use;
2216
811c0830
YL		 2217 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2218 desc_cb);
cfdaeba5
YL		 2219 if (unlikely(ret < 0))
2220 goto fill_err;
2221
d5d5e019
YL		 2222 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2223 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2224 * need to be notified to the hw.
2225 */
907676b1 2226 ret = hns3_handle_desc_filling(ring, skb);
d5d5e019 2227 if (unlikely(ret <= 0))
aa9d22dd 2228 goto fill_err;
76ad4f0e 2229
8ae10cfb
YL		 2230 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2231 (ring->desc_num - 1);
0bf5eb78
HT		 2232
2233 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2234 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2235
8ae10cfb
YL		 2236 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2237 cpu_to_le16(BIT(HNS3_TXD_FE_B));
698a8954 2238 trace_hns3_tx_desc(ring, pre_ntu);
76ad4f0e 2239
0bf5eb78
HT		 2240 skb_tx_timestamp(skb);
2241
76ad4f0e 2242 /* Complete translate all packets */
5f06b903 2243 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
811c0830 2244 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
f6061a05 2245 netdev_xmit_more());
d5d5e019 2246 hns3_tx_doorbell(ring, ret, doorbell);
76ad4f0e
S		 2247
2248 return NETDEV_TX_OK;
2249
aa9d22dd 2250fill_err:
ba3f808f 2251 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 2252
2253out_err_tx_ok:
2254 dev_kfree_skb_any(skb);
f6061a05 2255 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
76ad4f0e 2256 return NETDEV_TX_OK;
76ad4f0e
S		 2257}
2258
2259static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2260{
9780cb97 2261 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2262 struct sockaddr *mac_addr = p;
2263 int ret;
2264
2265 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2266 return -EADDRNOTAVAIL;
2267
5ec2a51e
JS		 2268 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2269 netdev_info(netdev, "already using mac address %pM\n",
2270 mac_addr->sa_data);
2271 return 0;
2272 }
2273
8e6de441
HT		 2274 /* For VF device, if there is a perm_addr, then the user will not
2275 * be allowed to change the address.
2276 */
2277 if (!hns3_is_phys_func(h->pdev) &&
2278 !is_zero_ether_addr(netdev->perm_addr)) {
2279 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
2280 netdev->perm_addr, mac_addr->sa_data);
2281 return -EPERM;
2282 }
2283
59098055 2284 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 2285 if (ret) {
2286 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2287 return ret;
2288 }
2289
2290 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
2291
2292 return 0;
2293}
2294
26483246
XW		 2295static int hns3_nic_do_ioctl(struct net_device *netdev,
2296 struct ifreq *ifr, int cmd)
2297{
2298 struct hnae3_handle *h = hns3_get_handle(netdev);
2299
2300 if (!netif_running(netdev))
2301 return -EINVAL;
2302
2303 if (!h->ae_algo->ops->do_ioctl)
2304 return -EOPNOTSUPP;
2305
2306 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2307}
2308
76ad4f0e
S		 2309static int hns3_nic_set_features(struct net_device *netdev,
2310 netdev_features_t features)
2311{
181d454b 2312 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 2313 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 2314 struct hnae3_handle *h = priv->ae_handle;
1731be4c 2315 bool enable;
052ece6d 2316 int ret;
76ad4f0e 2317
5c9f6b39 2318 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 2319 enable = !!(features & NETIF_F_GRO_HW);
2320 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 2321 if (ret)
2322 return ret;
2323 }
2324
bd368416
JS		 2325 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2326 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 2327 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2328 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 2329 if (ret)
2330 return ret;
2331 }
2332
c17852a8 2333 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 2334 enable = !!(features & NETIF_F_NTUPLE);
2335 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 2336 }
2337
0205ec04
JS		 2338 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2339 h->ae_algo->ops->cls_flower_active(h)) {
2340 netdev_err(netdev,
2341 "there are offloaded TC filters active, cannot disable HW TC offload");
2342 return -EINVAL;
2343 }
2344
2ba30662
JS		 2345 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2346 h->ae_algo->ops->enable_vlan_filter) {
2347 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2348 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2349 if (ret)
2350 return ret;
2351 }
2352
76ad4f0e
S		 2353 netdev->features = features;
2354 return 0;
2355}
2356
2a7556bb
YL		 2357static netdev_features_t hns3_features_check(struct sk_buff *skb,
2358 struct net_device *dev,
2359 netdev_features_t features)
2360{
2361#define HNS3_MAX_HDR_LEN 480U
2362#define HNS3_MAX_L4_HDR_LEN 60U
2363
2364 size_t len;
2365
2366 if (skb->ip_summed != CHECKSUM_PARTIAL)
2367 return features;
2368
2369 if (skb->encapsulation)
2370 len = skb_inner_transport_header(skb) - skb->data;
2371 else
2372 len = skb_transport_header(skb) - skb->data;
2373
2374 /* Assume L4 is 60 byte as TCP is the only protocol with a
2375 * a flexible value, and it's max len is 60 bytes.
2376 */
2377 len += HNS3_MAX_L4_HDR_LEN;
2378
2379 /* Hardware only supports checksum on the skb with a max header
2380 * len of 480 bytes.
2381 */
2382 if (len > HNS3_MAX_HDR_LEN)
2383 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2384
2385 return features;
2386}
2387
6c88d9d7
PL		 2388static void hns3_nic_get_stats64(struct net_device *netdev,
2389 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 2390{
2391 struct hns3_nic_priv *priv = netdev_priv(netdev);
2392 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 2393 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 2394 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 2395 u64 rx_length_errors = 0;
2396 u64 rx_crc_errors = 0;
2397 u64 rx_multicast = 0;
76ad4f0e 2398 unsigned int start;
d3ec4ef6
JS		 2399 u64 tx_errors = 0;
2400 u64 rx_errors = 0;
76ad4f0e
S		 2401 unsigned int idx;
2402 u64 tx_bytes = 0;
2403 u64 rx_bytes = 0;
2404 u64 tx_pkts = 0;
2405 u64 rx_pkts = 0;
d2a5dca8
JS		 2406 u64 tx_drop = 0;
2407 u64 rx_drop = 0;
76ad4f0e 2408
b875cc37
JS		 2409 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2410 return;
2411
c5f65480
JS		 2412 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
2413
76ad4f0e
S		 2414 for (idx = 0; idx < queue_num; idx++) {
2415 /* fetch the tx stats */
5f06b903 2416 ring = &priv->ring[idx];
76ad4f0e 2417 do {
d36d36ce 2418 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 2419 tx_bytes += ring->stats.tx_bytes;
2420 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 2421 tx_drop += ring->stats.sw_err_cnt;
b20d7fe5
YL		 2422 tx_drop += ring->stats.tx_vlan_err;
2423 tx_drop += ring->stats.tx_l4_proto_err;
2424 tx_drop += ring->stats.tx_l2l3l4_err;
2425 tx_drop += ring->stats.tx_tso_err;
d5d5e019
YL		 2426 tx_drop += ring->stats.over_max_recursion;
2427 tx_drop += ring->stats.hw_limitation;
907676b1 2428 tx_drop += ring->stats.copy_bits_err;
7459775e
YL		 2429 tx_drop += ring->stats.skb2sgl_err;
2430 tx_drop += ring->stats.map_sg_err;
d3ec4ef6 2431 tx_errors += ring->stats.sw_err_cnt;
b20d7fe5
YL		 2432 tx_errors += ring->stats.tx_vlan_err;
2433 tx_errors += ring->stats.tx_l4_proto_err;
2434 tx_errors += ring->stats.tx_l2l3l4_err;
2435 tx_errors += ring->stats.tx_tso_err;
d5d5e019
YL		 2436 tx_errors += ring->stats.over_max_recursion;
2437 tx_errors += ring->stats.hw_limitation;
907676b1 2438 tx_errors += ring->stats.copy_bits_err;
7459775e
YL		 2439 tx_errors += ring->stats.skb2sgl_err;
2440 tx_errors += ring->stats.map_sg_err;
76ad4f0e
S		 2441 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2442
2443 /* fetch the rx stats */
5f06b903 2444 ring = &priv->ring[idx + queue_num];
76ad4f0e 2445 do {
d36d36ce 2446 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 2447 rx_bytes += ring->stats.rx_bytes;
2448 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 2449 rx_drop += ring->stats.l2_err;
d3ec4ef6 2450 rx_errors += ring->stats.l2_err;
8b552079 2451 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 2452 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS		 2453 rx_multicast += ring->stats.rx_multicast;
2454 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 2455 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2456 }
2457
2458 stats->tx_bytes = tx_bytes;
2459 stats->tx_packets = tx_pkts;
2460 stats->rx_bytes = rx_bytes;
2461 stats->rx_packets = rx_pkts;
2462
d3ec4ef6
JS		 2463 stats->rx_errors = rx_errors;
2464 stats->multicast = rx_multicast;
2465 stats->rx_length_errors = rx_length_errors;
2466 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 2467 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2468
d3ec4ef6
JS		 2469 stats->tx_errors = tx_errors;
2470 stats->rx_dropped = rx_drop;
2471 stats->tx_dropped = tx_drop;
76ad4f0e
S		 2472 stats->collisions = netdev->stats.collisions;
2473 stats->rx_over_errors = netdev->stats.rx_over_errors;
2474 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2475 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2476 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2477 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2478 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2479 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2480 stats->tx_window_errors = netdev->stats.tx_window_errors;
2481 stats->rx_compressed = netdev->stats.rx_compressed;
2482 stats->tx_compressed = netdev->stats.tx_compressed;
2483}
2484
30d240df 2485static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 2486{
30d240df 2487 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
75718800 2488 struct hnae3_knic_private_info *kinfo;
30d240df
YL		 2489 u8 tc = mqprio_qopt->qopt.num_tc;
2490 u16 mode = mqprio_qopt->mode;
2491 u8 hw = mqprio_qopt->qopt.hw;
75718800 2492 struct hnae3_handle *h;
76ad4f0e 2493
30d240df
YL		 2494 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2495 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2496 return -EOPNOTSUPP;
2497
76ad4f0e
S		 2498 if (tc > HNAE3_MAX_TC)
2499 return -EINVAL;
2500
76ad4f0e
S		 2501 if (!netdev)
2502 return -EINVAL;
2503
75718800
YL		 2504 h = hns3_get_handle(netdev);
2505 kinfo = &h->kinfo;
2506
1c822948
YL		 2507 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2508
1cce5eb6 2509 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
5a5c9091 2510 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
76ad4f0e
S		 2511}
2512
0205ec04
JS		 2513static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2514 struct flow_cls_offload *flow)
2515{
2516 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2517 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2518
2519 switch (flow->command) {
2520 case FLOW_CLS_REPLACE:
2521 if (h->ae_algo->ops->add_cls_flower)
2522 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2523 break;
2524 case FLOW_CLS_DESTROY:
2525 if (h->ae_algo->ops->del_cls_flower)
2526 return h->ae_algo->ops->del_cls_flower(h, flow);
2527 break;
2528 default:
2529 break;
2530 }
2531
2532 return -EOPNOTSUPP;
2533}
2534
2535static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2536 void *cb_priv)
2537{
2538 struct hns3_nic_priv *priv = cb_priv;
2539
2540 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2541 return -EOPNOTSUPP;
2542
2543 switch (type) {
2544 case TC_SETUP_CLSFLOWER:
2545 return hns3_setup_tc_cls_flower(priv, type_data);
2546 default:
2547 return -EOPNOTSUPP;
2548 }
2549}
2550
2551static LIST_HEAD(hns3_block_cb_list);
2552
2572ac53 2553static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 2554 void *type_data)
76ad4f0e 2555{
0205ec04
JS		 2556 struct hns3_nic_priv *priv = netdev_priv(dev);
2557 int ret;
2558
2559 switch (type) {
2560 case TC_SETUP_QDISC_MQPRIO:
2561 ret = hns3_setup_tc(dev, type_data);
2562 break;
2563 case TC_SETUP_BLOCK:
2564 ret = flow_block_cb_setup_simple(type_data,
2565 &hns3_block_cb_list,
2566 hns3_setup_tc_block_cb,
2567 priv, priv, true);
2568 break;
2569 default:
38cf0426 2570 return -EOPNOTSUPP;
0205ec04 2571 }
76ad4f0e 2572
0205ec04 2573 return ret;
76ad4f0e
S		 2574}
2575
2576static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2577 __be16 proto, u16 vid)
2578{
9780cb97 2579 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2580 int ret = -EIO;
2581
2582 if (h->ae_algo->ops->set_vlan_filter)
2583 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2584
2585 return ret;
2586}
2587
2588static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2589 __be16 proto, u16 vid)
2590{
9780cb97 2591 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2592 int ret = -EIO;
2593
2594 if (h->ae_algo->ops->set_vlan_filter)
2595 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2596
7fa6be4f 2597 return ret;
681ec399
YL		 2598}
2599
76ad4f0e
S		 2600static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2601 u8 qos, __be16 vlan_proto)
2602{
9780cb97 2603 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2604 int ret = -EIO;
2605
1c822948 2606 netif_dbg(h, drv, netdev,
39edaf24
GL		 2607 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2608 vf, vlan, qos, ntohs(vlan_proto));
1c822948 2609
76ad4f0e
S		 2610 if (h->ae_algo->ops->set_vf_vlan_filter)
2611 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 2612 qos, vlan_proto);
76ad4f0e
S		 2613
2614 return ret;
2615}
2616
22044f95
JS		 2617static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2618{
2619 struct hnae3_handle *handle = hns3_get_handle(netdev);
2620
2621 if (hns3_nic_resetting(netdev))
2622 return -EBUSY;
2623
2624 if (!handle->ae_algo->ops->set_vf_spoofchk)
2625 return -EOPNOTSUPP;
2626
2627 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2628}
2629
e196ec75
JS		 2630static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2631{
2632 struct hnae3_handle *handle = hns3_get_handle(netdev);
2633
2634 if (!handle->ae_algo->ops->set_vf_trust)
2635 return -EOPNOTSUPP;
2636
2637 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2638}
2639
a8e8b7ff
S		 2640static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2641{
9780cb97 2642 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 2643 int ret;
2644
6ff7ed80
HT		 2645 if (hns3_nic_resetting(netdev))
2646 return -EBUSY;
2647
a8e8b7ff
S		 2648 if (!h->ae_algo->ops->set_mtu)
2649 return -EOPNOTSUPP;
2650
1c822948
YL		 2651 netif_dbg(h, drv, netdev,
2652 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2653
a8e8b7ff 2654 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 2655 if (ret)
a8e8b7ff
S		 2656 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2657 ret);
93d8daf4
YL		 2658 else
2659 netdev->mtu = new_mtu;
5bad95a1 2660
a8e8b7ff
S		 2661 return ret;
2662}
2663
f8fa222c
L		 2664static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2665{
2666 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 2667 struct hnae3_handle *h = hns3_get_handle(ndev);
0bfdf286 2668 struct hns3_enet_ring *tx_ring;
e511c97d 2669 struct napi_struct *napi;
f8fa222c
L		 2670 int timeout_queue = 0;
2671 int hw_head, hw_tail;
e511c97d
JS		 2672 int fbd_num, fbd_oft;
2673 int ebd_num, ebd_oft;
2674 int bd_num, bd_err;
2675 int ring_en, tc;
f8fa222c
L		 2676 int i;
2677
2678 /* Find the stopped queue the same way the stack does */
fa6c4084 2679 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 2680 struct netdev_queue *q;
2681 unsigned long trans_start;
2682
2683 q = netdev_get_tx_queue(ndev, i);
2684 trans_start = q->trans_start;
2685 if (netif_xmit_stopped(q) &&
2686 time_after(jiffies,
2687 (trans_start + ndev->watchdog_timeo))) {
2688 timeout_queue = i;
647522a5
YL		 2689 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2690 q->state,
2691 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L		 2692 break;
2693 }
2694 }
2695
2696 if (i == ndev->num_tx_queues) {
2697 netdev_info(ndev,
2698 "no netdev TX timeout queue found, timeout count: %llu\n",
2699 priv->tx_timeout_count);
2700 return false;
2701 }
2702
beab694a
JS		 2703 priv->tx_timeout_count++;
2704
5f06b903 2705 tx_ring = &priv->ring[timeout_queue];
e511c97d
JS		 2706 napi = &tx_ring->tqp_vector->napi;
2707
2708 netdev_info(ndev,
2709 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2710 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2711 tx_ring->next_to_clean, napi->state);
2712
2713 netdev_info(ndev,
20d06ca2 2714 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
e511c97d 2715 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
20d06ca2 2716 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
e511c97d
JS		 2717
2718 netdev_info(ndev,
f6061a05
YL		 2719 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2720 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
e511c97d
JS		 2721 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2722
2723 /* When mac received many pause frames continuous, it's unable to send
2724 * packets, which may cause tx timeout
2725 */
615466ce
YM		 2726 if (h->ae_algo->ops->get_mac_stats) {
2727 struct hns3_mac_stats mac_stats;
e511c97d 2728
615466ce 2729 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
e511c97d 2730 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
615466ce 2731 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
e511c97d 2732 }
f8fa222c
L		 2733
2734 hw_head = readl_relaxed(tx_ring->tqp->io_base +
2735 HNS3_RING_TX_RING_HEAD_REG);
2736 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
2737 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 2738 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
2739 HNS3_RING_TX_RING_FBDNUM_REG);
2740 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
2741 HNS3_RING_TX_RING_OFFSET_REG);
2742 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
2743 HNS3_RING_TX_RING_EBDNUM_REG);
2744 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
2745 HNS3_RING_TX_RING_EBD_OFFSET_REG);
2746 bd_num = readl_relaxed(tx_ring->tqp->io_base +
2747 HNS3_RING_TX_RING_BD_NUM_REG);
2748 bd_err = readl_relaxed(tx_ring->tqp->io_base +
2749 HNS3_RING_TX_RING_BD_ERR_REG);
2750 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
2751 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
2752
f8fa222c 2753 netdev_info(ndev,
e511c97d
JS		 2754 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2755 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 2756 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 2757 netdev_info(ndev,
2758 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2759 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 2760
2761 return true;
2762}
2763
0290bd29 2764static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
f8fa222c
L		 2765{
2766 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 2767 struct hnae3_handle *h = priv->ae_handle;
2768
2769 if (!hns3_get_tx_timeo_queue_info(ndev))
2770 return;
2771
0742ed7c
HT		 2772 /* request the reset, and let the hclge to determine
2773 * which reset level should be done
2774 */
f8fa222c 2775 if (h->ae_algo->ops->reset_event)
6ae4e733 2776 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 2777}
2778
d93ed94f
JS		 2779#ifdef CONFIG_RFS_ACCEL
2780static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2781 u16 rxq_index, u32 flow_id)
2782{
2783 struct hnae3_handle *h = hns3_get_handle(dev);
2784 struct flow_keys fkeys;
2785
2786 if (!h->ae_algo->ops->add_arfs_entry)
2787 return -EOPNOTSUPP;
2788
2789 if (skb->encapsulation)
2790 return -EPROTONOSUPPORT;
2791
2792 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2793 return -EPROTONOSUPPORT;
2794
2795 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2796 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2797 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2798 fkeys.basic.ip_proto != IPPROTO_UDP))
2799 return -EPROTONOSUPPORT;
2800
2801 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2802}
2803#endif
2804
6430f744
YM		 2805static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2806 struct ifla_vf_info *ivf)
2807{
2808 struct hnae3_handle *h = hns3_get_handle(ndev);
2809
2810 if (!h->ae_algo->ops->get_vf_config)
2811 return -EOPNOTSUPP;
2812
2813 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2814}
2815
2816static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2817 int link_state)
2818{
2819 struct hnae3_handle *h = hns3_get_handle(ndev);
2820
2821 if (!h->ae_algo->ops->set_vf_link_state)
2822 return -EOPNOTSUPP;
2823
2824 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2825}
2826
ee9e4424
YL		 2827static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2828 int min_tx_rate, int max_tx_rate)
2829{
2830 struct hnae3_handle *h = hns3_get_handle(ndev);
2831
2832 if (!h->ae_algo->ops->set_vf_rate)
2833 return -EOPNOTSUPP;
2834
2835 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2836 false);
2837}
2838
8e6de441
HT		 2839static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2840{
2841 struct hnae3_handle *h = hns3_get_handle(netdev);
2842
2843 if (!h->ae_algo->ops->set_vf_mac)
2844 return -EOPNOTSUPP;
2845
2846 if (is_multicast_ether_addr(mac)) {
2847 netdev_err(netdev,
2848 "Invalid MAC:%pM specified. Could not set MAC\n",
2849 mac);
2850 return -EINVAL;
2851 }
2852
2853 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2854}
2855
76ad4f0e
S		 2856static const struct net_device_ops hns3_nic_netdev_ops = {
2857 .ndo_open = hns3_nic_net_open,
2858 .ndo_stop = hns3_nic_net_stop,
2859 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 2860 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 2861 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
a7605370 2862 .ndo_eth_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 2863 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e 2864 .ndo_set_features = hns3_nic_set_features,
2a7556bb 2865 .ndo_features_check = hns3_features_check,
76ad4f0e
S		 2866 .ndo_get_stats64 = hns3_nic_get_stats64,
2867 .ndo_setup_tc = hns3_nic_setup_tc,
2868 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 2869 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2870 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2871 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
22044f95 2872 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
e196ec75 2873 .ndo_set_vf_trust = hns3_set_vf_trust,
d93ed94f
JS		 2874#ifdef CONFIG_RFS_ACCEL
2875 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2876#endif
6430f744
YM		 2877 .ndo_get_vf_config = hns3_nic_get_vf_config,
2878 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
ee9e4424 2879 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
8e6de441 2880 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
76ad4f0e
S		 2881};
2882
97afd47b 2883bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 2884{
2885 u32 dev_id = pdev->device;
2886
2887 switch (dev_id) {
2888 case HNAE3_DEV_ID_GE:
2889 case HNAE3_DEV_ID_25GE:
2890 case HNAE3_DEV_ID_25GE_RDMA:
2891 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2892 case HNAE3_DEV_ID_50GE_RDMA:
2893 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2894 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
ae6f010c 2895 case HNAE3_DEV_ID_200G_RDMA:
2312e050 2896 return true;
c155e22b
GH		 2897 case HNAE3_DEV_ID_VF:
2898 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
2312e050
FL		 2899 return false;
2900 default:
adcf738b 2901 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2312e050
FL		 2902 dev_id);
2903 }
2904
2905 return false;
2906}
2907
2312e050
FL		 2908static void hns3_disable_sriov(struct pci_dev *pdev)
2909{
2910 /* If our VFs are assigned we cannot shut down SR-IOV
2911 * without causing issues, so just leave the hardware
2912 * available but disabled
2913 */
2914 if (pci_vfs_assigned(pdev)) {
2915 dev_warn(&pdev->dev,
2916 "disabling driver while VFs are assigned\n");
2917 return;
2918 }
2919
2920 pci_disable_sriov(pdev);
2921}
2922
76ad4f0e
S		 2923/* hns3_probe - Device initialization routine
2924 * @pdev: PCI device information struct
2925 * @ent: entry in hns3_pci_tbl
2926 *
2927 * hns3_probe initializes a PF identified by a pci_dev structure.
2928 * The OS initialization, configuring of the PF private structure,
2929 * and a hardware reset occur.
2930 *
2931 * Returns 0 on success, negative on failure
2932 */
2933static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2934{
2935 struct hnae3_ae_dev *ae_dev;
2936 int ret;
2937
9b2f3477 2938 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
60df7e91
HT		 2939 if (!ae_dev)
2940 return -ENOMEM;
76ad4f0e
S		 2941
2942 ae_dev->pdev = pdev;
e92a0843 2943 ae_dev->flag = ent->driver_data;
76ad4f0e
S		 2944 pci_set_drvdata(pdev, ae_dev);
2945
74354140 2946 ret = hnae3_register_ae_dev(ae_dev);
674a1357 2947 if (ret)
74354140 2948 pci_set_drvdata(pdev, NULL);
2312e050 2949
74354140 2950 return ret;
76ad4f0e
S		 2951}
2952
2953/* hns3_remove - Device removal routine
2954 * @pdev: PCI device information struct
2955 */
2956static void hns3_remove(struct pci_dev *pdev)
2957{
2958 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2959
2312e050
FL		 2960 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2961 hns3_disable_sriov(pdev);
2962
76ad4f0e 2963 hnae3_unregister_ae_dev(ae_dev);
ac864c23 2964 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 2965}
2966
fa8d82e8
PL		 2967/**
2968 * hns3_pci_sriov_configure
2969 * @pdev: pointer to a pci_dev structure
2970 * @num_vfs: number of VFs to allocate
2971 *
2972 * Enable or change the number of VFs. Called when the user updates the number
2973 * of VFs in sysfs.
2974 **/
743e1a84 2975static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 2976{
2977 int ret;
2978
2979 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2980 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2981 return -EINVAL;
2982 }
2983
2984 if (num_vfs) {
2985 ret = pci_enable_sriov(pdev, num_vfs);
2986 if (ret)
2987 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 2988 else
2989 return num_vfs;
fa8d82e8
PL		 2990 } else if (!pci_vfs_assigned(pdev)) {
2991 pci_disable_sriov(pdev);
2992 } else {
2993 dev_warn(&pdev->dev,
2994 "Unable to free VFs because some are assigned to VMs.\n");
2995 }
2996
2997 return 0;
2998}
2999
ce2c1d2e
YL		 3000static void hns3_shutdown(struct pci_dev *pdev)
3001{
3002 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3003
3004 hnae3_unregister_ae_dev(ae_dev);
ce2c1d2e
YL		 3005 pci_set_drvdata(pdev, NULL);
3006
3007 if (system_state == SYSTEM_POWER_OFF)
3008 pci_set_power_state(pdev, PCI_D3hot);
3009}
3010
715c58e9
JZ		 3011static int __maybe_unused hns3_suspend(struct device *dev)
3012{
3013 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3014
d0494135 3015 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
715c58e9 3016 dev_info(dev, "Begin to suspend.\n");
d0494135 3017 if (ae_dev->ops && ae_dev->ops->reset_prepare)
715c58e9
JZ		 3018 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3019 }
3020
3021 return 0;
3022}
3023
3024static int __maybe_unused hns3_resume(struct device *dev)
3025{
3026 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3027
d0494135 3028 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
715c58e9 3029 dev_info(dev, "Begin to resume.\n");
d0494135 3030 if (ae_dev->ops && ae_dev->ops->reset_done)
715c58e9
JZ		 3031 ae_dev->ops->reset_done(ae_dev);
3032 }
3033
3034 return 0;
3035}
3036
5a9f0eac
SJ		 3037static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3038 pci_channel_state_t state)
3039{
3040 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3041 pci_ers_result_t ret;
3042
c5aaf176 3043 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
5a9f0eac
SJ		 3044
3045 if (state == pci_channel_io_perm_failure)
3046 return PCI_ERS_RESULT_DISCONNECT;
3047
661262bc 3048 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 3049 dev_err(&pdev->dev,
661262bc 3050 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ		 3051 return PCI_ERS_RESULT_NONE;
3052 }
3053
381c356e
SJ		 3054 if (ae_dev->ops->handle_hw_ras_error)
3055 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 3056 else
3057 return PCI_ERS_RESULT_NONE;
3058
3059 return ret;
3060}
3061
6ae4e733
SJ		 3062static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3063{
3064 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 3065 const struct hnae3_ae_ops *ops;
123297b7 3066 enum hnae3_reset_type reset_type;
6ae4e733
SJ		 3067 struct device *dev = &pdev->dev;
3068
661262bc
WL		 3069 if (!ae_dev || !ae_dev->ops)
3070 return PCI_ERS_RESULT_NONE;
3071
ad9bf545 3072 ops = ae_dev->ops;
6ae4e733 3073 /* request the reset */
fa17c708
GH		 3074 if (ops->reset_event && ops->get_reset_level &&
3075 ops->set_default_reset_request) {
9d5e67d1 3076 if (ae_dev->hw_err_reset_req) {
123297b7
SJ		 3077 reset_type = ops->get_reset_level(ae_dev,
3078 &ae_dev->hw_err_reset_req);
3079 ops->set_default_reset_request(ae_dev, reset_type);
3080 dev_info(dev, "requesting reset due to PCI error\n");
3081 ops->reset_event(pdev, NULL);
3082 }
69b51bbb 3083
6ae4e733
SJ		 3084 return PCI_ERS_RESULT_RECOVERED;
3085 }
3086
3087 return PCI_ERS_RESULT_DISCONNECT;
3088}
3089
6b9a97ee
HT		 3090static void hns3_reset_prepare(struct pci_dev *pdev)
3091{
3092 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3093
8de91e92 3094 dev_info(&pdev->dev, "FLR prepare\n");
bb1890d5
JZ		 3095 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3096 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
6b9a97ee
HT		 3097}
3098
3099static void hns3_reset_done(struct pci_dev *pdev)
3100{
3101 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3102
8de91e92 3103 dev_info(&pdev->dev, "FLR done\n");
bb1890d5
JZ		 3104 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3105 ae_dev->ops->reset_done(ae_dev);
6b9a97ee
HT		 3106}
3107
5a9f0eac
SJ		 3108static const struct pci_error_handlers hns3_err_handler = {
3109 .error_detected = hns3_error_detected,
6ae4e733 3110 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 3111 .reset_prepare = hns3_reset_prepare,
3112 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 3113};
3114
715c58e9
JZ		 3115static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3116
76ad4f0e
S		 3117static struct pci_driver hns3_driver = {
3118 .name = hns3_driver_name,
3119 .id_table = hns3_pci_tbl,
3120 .probe = hns3_probe,
3121 .remove = hns3_remove,
ce2c1d2e 3122 .shutdown = hns3_shutdown,
715c58e9 3123 .driver.pm = &hns3_pm_ops,
fa8d82e8 3124 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 3125 .err_handler = &hns3_err_handler,
76ad4f0e
S		 3126};
3127
3128/* set default feature to hns3 */
3129static void hns3_set_default_feature(struct net_device *netdev)
3130{
3e85af6a
PL		 3131 struct hnae3_handle *h = hns3_get_handle(netdev);
3132 struct pci_dev *pdev = h->pdev;
295ba232 3133 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3e85af6a 3134
76ad4f0e
S		 3135 netdev->priv_flags |= IFF_UNICAST_FLT;
3136
76ad4f0e
S		 3137 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
3138
66d52f3b 3139 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 3140 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 3141 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3142 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3143 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 3144 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
76ad4f0e 3145
295ba232 3146 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
5c9f6b39 3147 netdev->features |= NETIF_F_GRO_HW;
c17852a8 3148
dc9b5ce0 3149 if (!(h->flags & HNAE3_SUPPORT_VF))
c17852a8 3150 netdev->features |= NETIF_F_NTUPLE;
c17852a8 3151 }
0692cfe9 3152
dc9b5ce0 3153 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
0692cfe9 3154 netdev->features |= NETIF_F_GSO_UDP_L4;
66d52f3b 3155
dc9b5ce0 3156 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
66d52f3b 3157 netdev->features |= NETIF_F_HW_CSUM;
dc9b5ce0 3158 else
66d52f3b 3159 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3e281621 3160
dc9b5ce0 3161 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3e281621 3162 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
0205ec04 3163
dc9b5ce0 3164 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
0205ec04 3165 netdev->features |= NETIF_F_HW_TC;
2ba30662 3166
dc9b5ce0
JS		 3167 netdev->hw_features |= netdev->features;
3168 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3169 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3170
3171 netdev->vlan_features |= netdev->features &
3172 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3173 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3174 NETIF_F_HW_TC);
3175
3176 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
76ad4f0e
S		 3177}
3178
3179static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3180 struct hns3_desc_cb *cb)
3181{
dbba6da0 3182 unsigned int order = hns3_page_order(ring);
76ad4f0e
S		 3183 struct page *p;
3184
93188e96
YL		 3185 if (ring->page_pool) {
3186 p = page_pool_dev_alloc_frag(ring->page_pool,
3187 &cb->page_offset,
3188 hns3_buf_size(ring));
3189 if (unlikely(!p))
3190 return -ENOMEM;
3191
3192 cb->priv = p;
3193 cb->buf = page_address(p);
3194 cb->dma = page_pool_get_dma_addr(p);
3195 cb->type = DESC_TYPE_PP_FRAG;
3196 cb->reuse_flag = 0;
3197 return 0;
3198 }
3199
76ad4f0e
S		 3200 p = dev_alloc_pages(order);
3201 if (!p)
3202 return -ENOMEM;
3203
3204 cb->priv = p;
3205 cb->page_offset = 0;
3206 cb->reuse_flag = 0;
3207 cb->buf = page_address(p);
dbba6da0 3208 cb->length = hns3_page_size(ring);
76ad4f0e 3209 cb->type = DESC_TYPE_PAGE;
aeda9bf8
YL		 3210 page_ref_add(p, USHRT_MAX - 1);
3211 cb->pagecnt_bias = USHRT_MAX;
76ad4f0e 3212
76ad4f0e
S		 3213 return 0;
3214}
3215
3216static void hns3_free_buffer(struct hns3_enet_ring *ring,
619ae331 3217 struct hns3_desc_cb *cb, int budget)
76ad4f0e 3218{
907676b1 3219 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
7459775e 3220 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
619ae331 3221 napi_consume_skb(cb->priv, budget);
93188e96
YL		 3222 else if (!HNAE3_IS_TX_RING(ring)) {
3223 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3224 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3225 else if (cb->type & DESC_TYPE_PP_FRAG)
3226 page_pool_put_full_page(ring->page_pool, cb->priv,
3227 false);
3228 }
76ad4f0e
S		 3229 memset(cb, 0, sizeof(*cb));
3230}
3231
3232static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3233{
3234 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3235 cb->length, ring_to_dma_dir(ring));
3236
2211f4e1 3237 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 3238 return -EIO;
3239
3240 return 0;
3241}
3242
3243static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3244 struct hns3_desc_cb *cb)
3245{
26f1ccdf 3246 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
76ad4f0e
S		 3247 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3248 ring_to_dma_dir(ring));
907676b1 3249 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
76ad4f0e
S		 3250 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3251 ring_to_dma_dir(ring));
7459775e
YL		 3252 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3253 DESC_TYPE_SGL_SKB))
907676b1 3254 hns3_tx_spare_reclaim_cb(ring, cb);
76ad4f0e
S		 3255}
3256
3257static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3258{
3259 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3260 ring->desc[i].addr = 0;
3261}
3262
619ae331
YL		 3263static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3264 int budget)
76ad4f0e
S		 3265{
3266 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3267
3268 if (!ring->desc_cb[i].dma)
3269 return;
3270
3271 hns3_buffer_detach(ring, i);
619ae331 3272 hns3_free_buffer(ring, cb, budget);
76ad4f0e
S		 3273}
3274
3275static void hns3_free_buffers(struct hns3_enet_ring *ring)
3276{
3277 int i;
3278
3279 for (i = 0; i < ring->desc_num; i++)
619ae331 3280 hns3_free_buffer_detach(ring, i, 0);
76ad4f0e
S		 3281}
3282
3283/* free desc along with its attached buffer */
3284static void hns3_free_desc(struct hns3_enet_ring *ring)
3285{
024cc792
HT		 3286 int size = ring->desc_num * sizeof(ring->desc[0]);
3287
76ad4f0e
S		 3288 hns3_free_buffers(ring);
3289
024cc792
HT		 3290 if (ring->desc) {
3291 dma_free_coherent(ring_to_dev(ring), size,
3292 ring->desc, ring->desc_dma_addr);
3293 ring->desc = NULL;
3294 }
76ad4f0e
S		 3295}
3296
3297static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3298{
3299 int size = ring->desc_num * sizeof(ring->desc[0]);
3300
750afb08
LC		 3301 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3302 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 3303 if (!ring->desc)
3304 return -ENOMEM;
3305
76ad4f0e
S		 3306 return 0;
3307}
3308
4d2cad32 3309static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
76ad4f0e
S		 3310 struct hns3_desc_cb *cb)
3311{
3312 int ret;
3313
3314 ret = hns3_alloc_buffer(ring, cb);
93188e96 3315 if (ret || ring->page_pool)
76ad4f0e
S		 3316 goto out;
3317
3318 ret = hns3_map_buffer(ring, cb);
3319 if (ret)
3320 goto out_with_buf;
3321
3322 return 0;
3323
3324out_with_buf:
619ae331 3325 hns3_free_buffer(ring, cb, 0);
76ad4f0e
S		 3326out:
3327 return ret;
3328}
3329
4d2cad32 3330static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
76ad4f0e 3331{
4d2cad32 3332 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 3333
3334 if (ret)
3335 return ret;
3336
93188e96
YL		 3337 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3338 ring->desc_cb[i].page_offset);
76ad4f0e
S		 3339
3340 return 0;
3341}
3342
3343/* Allocate memory for raw pkg, and map with dma */
3344static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3345{
3346 int i, j, ret;
3347
3348 for (i = 0; i < ring->desc_num; i++) {
4d2cad32 3349 ret = hns3_alloc_and_attach_buffer(ring, i);
76ad4f0e
S		 3350 if (ret)
3351 goto out_buffer_fail;
3352 }
3353
3354 return 0;
3355
3356out_buffer_fail:
3357 for (j = i - 1; j >= 0; j--)
619ae331 3358 hns3_free_buffer_detach(ring, j, 0);
76ad4f0e
S		 3359 return ret;
3360}
3361
9b2f3477 3362/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S		 3363static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3364 struct hns3_desc_cb *res_cb)
3365{
b9077428 3366 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e 3367 ring->desc_cb[i] = *res_cb;
93188e96
YL		 3368 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3369 ring->desc_cb[i].page_offset);
7d0b130c 3370 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 3371}
3372
3373static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3374{
3375 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL		 3376 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3377 ring->desc_cb[i].page_offset);
7d0b130c 3378 ring->desc[i].rx.bd_base_info = 0;
c2a2e127
BS		 3379
3380 dma_sync_single_for_device(ring_to_dev(ring),
3381 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3382 hns3_buf_size(ring),
3383 DMA_FROM_DEVICE);
76ad4f0e
S		 3384}
3385
20d06ca2 3386static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
619ae331 3387 int *bytes, int *pkts, int budget)
76ad4f0e 3388{
20d06ca2
YL		 3389 /* pair with ring->last_to_use update in hns3_tx_doorbell(),
3390 * smp_store_release() is not used in hns3_tx_doorbell() because
3391 * the doorbell operation already have the needed barrier operation.
3392 */
3393 int ltu = smp_load_acquire(&ring->last_to_use);
26cda2f1
YL		 3394 int ntc = ring->next_to_clean;
3395 struct hns3_desc_cb *desc_cb;
20d06ca2
YL		 3396 bool reclaimed = false;
3397 struct hns3_desc *desc;
3398
3399 while (ltu != ntc) {
3400 desc = &ring->desc[ntc];
3401
3402 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3403 BIT(HNS3_TXD_VLD_B))
3404 break;
76ad4f0e 3405
ce74370c 3406 desc_cb = &ring->desc_cb[ntc];
811c0830 3407
907676b1 3408 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
7459775e
YL		 3409 DESC_TYPE_BOUNCE_HEAD |
3410 DESC_TYPE_SGL_SKB)) {
811c0830
YL		 3411 (*pkts)++;
3412 (*bytes) += desc_cb->send_bytes;
3413 }
3414
ce74370c 3415 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
619ae331 3416 hns3_free_buffer_detach(ring, ntc, budget);
76ad4f0e 3417
ce74370c
YL		 3418 if (++ntc == ring->desc_num)
3419 ntc = 0;
3420
3421 /* Issue prefetch for next Tx descriptor */
3422 prefetch(&ring->desc_cb[ntc]);
20d06ca2 3423 reclaimed = true;
ce74370c 3424 }
26cda2f1 3425
20d06ca2
YL		 3426 if (unlikely(!reclaimed))
3427 return false;
3428
26cda2f1
YL		 3429 /* This smp_store_release() pairs with smp_load_acquire() in
3430 * ring_space called by hns3_nic_net_xmit.
3431 */
3432 smp_store_release(&ring->next_to_clean, ntc);
907676b1
YL		 3433
3434 hns3_tx_spare_update(ring);
3435
20d06ca2 3436 return true;
76ad4f0e
S		 3437}
3438
619ae331 3439void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
76ad4f0e 3440{
c8711956 3441 struct net_device *netdev = ring_to_netdev(ring);
7a810110 3442 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 3443 struct netdev_queue *dev_queue;
3444 int bytes, pkts;
76ad4f0e
S		 3445
3446 bytes = 0;
3447 pkts = 0;
20d06ca2 3448
619ae331 3449 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
20d06ca2 3450 return;
76ad4f0e
S		 3451
3452 ring->tqp_vector->tx_group.total_bytes += bytes;
3453 ring->tqp_vector->tx_group.total_packets += pkts;
3454
3455 u64_stats_update_begin(&ring->syncp);
3456 ring->stats.tx_bytes += bytes;
3457 ring->stats.tx_pkts += pkts;
3458 u64_stats_update_end(&ring->syncp);
3459
3460 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3461 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3462
2a597eff 3463 if (unlikely(netif_carrier_ok(netdev) &&
8ae10cfb 3464 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
76ad4f0e
S		 3465 /* Make sure that anybody stopping the queue after this
3466 * sees the new next_to_clean.
3467 */
3468 smp_mb();
7a810110
JS		 3469 if (netif_tx_queue_stopped(dev_queue) &&
3470 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 3471 netif_tx_wake_queue(dev_queue);
3472 ring->stats.restart_queue++;
3473 }
3474 }
76ad4f0e
S		 3475}
3476
3477static int hns3_desc_unused(struct hns3_enet_ring *ring)
3478{
3479 int ntc = ring->next_to_clean;
3480 int ntu = ring->next_to_use;
3481
3482 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3483}
3484
9b2f3477
WL		 3485static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3486 int cleand_count)
76ad4f0e
S		 3487{
3488 struct hns3_desc_cb *desc_cb;
3489 struct hns3_desc_cb res_cbs;
3490 int i, ret;
3491
3492 for (i = 0; i < cleand_count; i++) {
3493 desc_cb = &ring->desc_cb[ring->next_to_use];
3494 if (desc_cb->reuse_flag) {
3495 u64_stats_update_begin(&ring->syncp);
3496 ring->stats.reuse_pg_cnt++;
3497 u64_stats_update_end(&ring->syncp);
3498
3499 hns3_reuse_buffer(ring, ring->next_to_use);
3500 } else {
4d2cad32 3501 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
76ad4f0e
S		 3502 if (ret) {
3503 u64_stats_update_begin(&ring->syncp);
3504 ring->stats.sw_err_cnt++;
3505 u64_stats_update_end(&ring->syncp);
3506
c8711956 3507 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5
YL		 3508 "alloc rx buffer failed: %d\n",
3509 ret);
76ad4f0e
S		 3510 break;
3511 }
3512 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 3513
3514 u64_stats_update_begin(&ring->syncp);
3515 ring->stats.non_reuse_pg++;
3516 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 3517 }
3518
3519 ring_ptr_move_fw(ring, next_to_use);
3520 }
3521
48ee56fd 3522 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
76ad4f0e
S		 3523}
3524
aeda9bf8
YL		 3525static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3526{
fa7711b8 3527 return page_count(cb->priv) == cb->pagecnt_bias;
aeda9bf8
YL		 3528}
3529
76ad4f0e
S		 3530static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3531 struct hns3_enet_ring *ring, int pull_len,
3532 struct hns3_desc_cb *desc_cb)
3533{
389ca146 3534 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
fa7711b8 3535 u32 frag_offset = desc_cb->page_offset + pull_len;
389ca146 3536 int size = le16_to_cpu(desc->rx.size);
dbba6da0 3537 u32 truesize = hns3_buf_size(ring);
fa7711b8 3538 u32 frag_size = size - pull_len;
96104500 3539 bool reused;
76ad4f0e 3540
93188e96
YL		 3541 if (ring->page_pool) {
3542 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3543 frag_size, truesize);
3544 return;
3545 }
3546
fa7711b8
YL		 3547 /* Avoid re-using remote or pfmem page */
3548 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3549 goto out;
76ad4f0e 3550
96104500
YL		 3551 reused = hns3_can_reuse_page(desc_cb);
3552
3553 /* Rx page can be reused when:
3554 * 1. Rx page is only owned by the driver when page_offset
3555 * is zero, which means 0 @ truesize will be used by
3556 * stack after skb_add_rx_frag() is called, and the rest
3557 * of rx page can be reused by driver.
3558 * Or
3559 * 2. Rx page is only owned by the driver when page_offset
3560 * is non-zero, which means page_offset @ truesize will
3561 * be used by stack after skb_add_rx_frag() is called,
3562 * and 0 @ truesize can be reused by driver.
389ca146 3563 */
96104500
YL		 3564 if ((!desc_cb->page_offset && reused) ||
3565 ((desc_cb->page_offset + truesize + truesize) <=
3566 hns3_page_size(ring) && desc_cb->page_offset)) {
fa7711b8 3567 desc_cb->page_offset += truesize;
389ca146 3568 desc_cb->reuse_flag = 1;
96104500
YL		 3569 } else if (desc_cb->page_offset && reused) {
3570 desc_cb->page_offset = 0;
3571 desc_cb->reuse_flag = 1;
99f6b5fb
YL		 3572 } else if (frag_size <= ring->rx_copybreak) {
3573 void *frag = napi_alloc_frag(frag_size);
3574
3575 if (unlikely(!frag)) {
3576 u64_stats_update_begin(&ring->syncp);
3577 ring->stats.frag_alloc_err++;
3578 u64_stats_update_end(&ring->syncp);
3579
3580 hns3_rl_err(ring_to_netdev(ring),
3581 "failed to allocate rx frag\n");
3582 goto out;
3583 }
3584
3585 desc_cb->reuse_flag = 1;
3586 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3587 skb_add_rx_frag(skb, i, virt_to_page(frag),
3588 offset_in_page(frag), frag_size, frag_size);
3589
3590 u64_stats_update_begin(&ring->syncp);
3591 ring->stats.frag_alloc++;
3592 u64_stats_update_end(&ring->syncp);
3593 return;
aeda9bf8
YL		 3594 }
3595
fa7711b8
YL		 3596out:
3597 desc_cb->pagecnt_bias--;
3598
aeda9bf8
YL		 3599 if (unlikely(!desc_cb->pagecnt_bias)) {
3600 page_ref_add(desc_cb->priv, USHRT_MAX);
3601 desc_cb->pagecnt_bias = USHRT_MAX;
76ad4f0e 3602 }
fa7711b8
YL		 3603
3604 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3605 frag_size, truesize);
3606
3607 if (unlikely(!desc_cb->reuse_flag))
3608 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
76ad4f0e
S		 3609}
3610
e2ee1c5a 3611static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL		 3612{
3613 __be16 type = skb->protocol;
3614 struct tcphdr *th;
3615 int depth = 0;
3616
e2ee1c5a 3617 while (eth_type_vlan(type)) {
d474d88f
YL		 3618 struct vlan_hdr *vh;
3619
3620 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3621 return -EFAULT;
3622
3623 vh = (struct vlan_hdr *)(skb->data + depth);
3624 type = vh->h_vlan_encapsulated_proto;
3625 depth += VLAN_HLEN;
3626 }
3627
e2ee1c5a
YL		 3628 skb_set_network_header(skb, depth);
3629
d474d88f 3630 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL		 3631 const struct iphdr *iph = ip_hdr(skb);
3632
d474d88f 3633 depth += sizeof(struct iphdr);
e2ee1c5a
YL		 3634 skb_set_transport_header(skb, depth);
3635 th = tcp_hdr(skb);
3636 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3637 iph->daddr, 0);
d474d88f 3638 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL		 3639 const struct ipv6hdr *iph = ipv6_hdr(skb);
3640
d474d88f 3641 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL		 3642 skb_set_transport_header(skb, depth);
3643 th = tcp_hdr(skb);
3644 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3645 &iph->daddr, 0);
d474d88f 3646 } else {
b20d7fe5
YL		 3647 hns3_rl_err(skb->dev,
3648 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3649 be16_to_cpu(type), depth);
d474d88f
YL		 3650 return -EFAULT;
3651 }
3652
d474d88f
YL		 3653 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3654 if (th->cwr)
3655 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3656
e2ee1c5a
YL		 3657 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3658 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 3659
e2ee1c5a
YL		 3660 skb->csum_start = (unsigned char *)th - skb->head;
3661 skb->csum_offset = offsetof(struct tcphdr, check);
3662 skb->ip_summed = CHECKSUM_PARTIAL;
698a8954
YL		 3663
3664 trace_hns3_gro(skb);
3665
d474d88f
YL		 3666 return 0;
3667}
3668
1ddc028a
HT		 3669static bool hns3_checksum_complete(struct hns3_enet_ring *ring,
3670 struct sk_buff *skb, u32 ptype, u16 csum)
4b2fe769 3671{
1ddc028a
HT		 3672 if (ptype == HNS3_INVALID_PTYPE ||
3673 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3674 return false;
4b2fe769
HT		 3675
3676 u64_stats_update_begin(&ring->syncp);
3677 ring->stats.csum_complete++;
3678 u64_stats_update_end(&ring->syncp);
3679 skb->ip_summed = CHECKSUM_COMPLETE;
1ddc028a
HT		 3680 skb->csum = csum_unfold((__force __sum16)csum);
3681
3682 return true;
4b2fe769
HT		 3683}
3684
79664077
HT		 3685static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3686 u32 ol_info, u32 ptype)
76ad4f0e 3687{
76ad4f0e 3688 int l3_type, l4_type;
76ad4f0e 3689 int ol4_type;
76ad4f0e 3690
79664077
HT		 3691 if (ptype != HNS3_INVALID_PTYPE) {
3692 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3693 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
76ad4f0e
S		 3694
3695 return;
3696 }
3697
39c38824 3698 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 3699 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 3700 switch (ol4_type) {
3701 case HNS3_OL4_TYPE_MAC_IN_UDP:
3702 case HNS3_OL4_TYPE_NVGRE:
3703 skb->csum_level = 1;
df561f66 3704 fallthrough;
76ad4f0e 3705 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 3706 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3707 HNS3_RXD_L3ID_S);
3708 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3709 HNS3_RXD_L4ID_S);
76ad4f0e 3710 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 3711 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3712 l3_type == HNS3_L3_TYPE_IPV6) &&
3713 (l4_type == HNS3_L4_TYPE_UDP ||
3714 l4_type == HNS3_L4_TYPE_TCP ||
3715 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 3716 skb->ip_summed = CHECKSUM_UNNECESSARY;
3717 break;
fa7a4bd5
JS		 3718 default:
3719 break;
76ad4f0e
S		 3720 }
3721}
3722
79664077 3723static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
1ddc028a
HT		 3724 u32 l234info, u32 bd_base_info, u32 ol_info,
3725 u16 csum)
79664077
HT		 3726{
3727 struct net_device *netdev = ring_to_netdev(ring);
3728 struct hns3_nic_priv *priv = netdev_priv(netdev);
3729 u32 ptype = HNS3_INVALID_PTYPE;
3730
3731 skb->ip_summed = CHECKSUM_NONE;
3732
3733 skb_checksum_none_assert(skb);
3734
3735 if (!(netdev->features & NETIF_F_RXCSUM))
3736 return;
3737
3738 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3739 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3740 HNS3_RXD_PTYPE_S);
3741
1ddc028a 3742 if (hns3_checksum_complete(ring, skb, ptype, csum))
79664077 3743 return;
79664077
HT		 3744
3745 /* check if hardware has done checksum */
3746 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3747 return;
3748
3749 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3750 BIT(HNS3_RXD_OL3E_B) |
3751 BIT(HNS3_RXD_OL4E_B)))) {
3752 u64_stats_update_begin(&ring->syncp);
3753 ring->stats.l3l4_csum_err++;
3754 u64_stats_update_end(&ring->syncp);
3755
3756 return;
3757 }
3758
3759 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3760}
3761
d43e5aca
YL		 3762static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3763{
81ae0e04
PL		 3764 if (skb_has_frag_list(skb))
3765 napi_gro_flush(&ring->tqp_vector->napi, false);
3766
d43e5aca
YL		 3767 napi_gro_receive(&ring->tqp_vector->napi, skb);
3768}
3769
701a6d6a
JS		 3770static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3771 struct hns3_desc *desc, u32 l234info,
3772 u16 *vlan_tag)
5b5455a9 3773{
44e626f7 3774 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 3775 struct pci_dev *pdev = ring->tqp->handle->pdev;
295ba232 3776 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5b5455a9 3777
295ba232 3778 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
701a6d6a
JS		 3779 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3780 if (!(*vlan_tag & VLAN_VID_MASK))
3781 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 3782
701a6d6a 3783 return (*vlan_tag != 0);
5b5455a9
PL		 3784 }
3785
3786#define HNS3_STRP_OUTER_VLAN 0x1
3787#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 3788#define HNS3_STRP_BOTH 0x3
5b5455a9 3789
44e626f7
JS		 3790 /* Hardware always insert VLAN tag into RX descriptor when
3791 * remove the tag from packet, driver needs to determine
3792 * reporting which tag to stack.
3793 */
e4e87715
PL		 3794 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3795 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 3796 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 3797 if (handle->port_base_vlan_state !=
3798 HNAE3_PORT_BASE_VLAN_DISABLE)
3799 return false;
3800
701a6d6a
JS		 3801 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3802 return true;
5b5455a9 3803 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 3804 if (handle->port_base_vlan_state !=
3805 HNAE3_PORT_BASE_VLAN_DISABLE)
3806 return false;
3807
701a6d6a 3808 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 3809 return true;
3810 case HNS3_STRP_BOTH:
3811 if (handle->port_base_vlan_state ==
3812 HNAE3_PORT_BASE_VLAN_DISABLE)
3813 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3814 else
3815 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3816
701a6d6a 3817 return true;
5b5455a9 3818 default:
701a6d6a 3819 return false;
5b5455a9 3820 }
5b5455a9
PL		 3821}
3822
8c30e194
YL		 3823static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
3824{
3825 ring->desc[ring->next_to_clean].rx.bd_base_info &=
3826 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
3827 ring->next_to_clean += 1;
3828
3829 if (unlikely(ring->next_to_clean == ring->desc_num))
3830 ring->next_to_clean = 0;
3831}
3832
b9a8f883 3833static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL		 3834 unsigned char *va)
3835{
e5597095 3836 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
c8711956 3837 struct net_device *netdev = ring_to_netdev(ring);
e5597095
PL		 3838 struct sk_buff *skb;
3839
3840 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
3841 skb = ring->skb;
3842 if (unlikely(!skb)) {
b20d7fe5 3843 hns3_rl_err(netdev, "alloc rx skb fail\n");
e5597095
PL		 3844
3845 u64_stats_update_begin(&ring->syncp);
3846 ring->stats.sw_err_cnt++;
3847 u64_stats_update_end(&ring->syncp);
3848
3849 return -ENOMEM;
3850 }
3851
698a8954 3852 trace_hns3_rx_desc(ring);
e5597095
PL		 3853 prefetchw(skb->data);
3854
3855 ring->pending_buf = 1;
81ae0e04
PL		 3856 ring->frag_num = 0;
3857 ring->tail_skb = NULL;
e5597095
PL		 3858 if (length <= HNS3_RX_HEAD_SIZE) {
3859 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
3860
a79afa78
AL		 3861 /* We can reuse buffer as-is, just make sure it is reusable */
3862 if (dev_page_is_reusable(desc_cb->priv))
e5597095 3863 desc_cb->reuse_flag = 1;
93188e96
YL		 3864 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
3865 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
3866 false);
e5597095 3867 else /* This page cannot be reused so discard it */
aeda9bf8
YL		 3868 __page_frag_cache_drain(desc_cb->priv,
3869 desc_cb->pagecnt_bias);
e5597095 3870
8c30e194 3871 hns3_rx_ring_move_fw(ring);
e5597095
PL		 3872 return 0;
3873 }
93188e96
YL		 3874
3875 if (ring->page_pool)
3876 skb_mark_for_recycle(skb);
3877
e5597095
PL		 3878 u64_stats_update_begin(&ring->syncp);
3879 ring->stats.seg_pkt_cnt++;
3880 u64_stats_update_end(&ring->syncp);
3881
c43f1255 3882 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 3883 __skb_put(skb, ring->pull_len);
81ae0e04 3884 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095 3885 desc_cb);
8c30e194 3886 hns3_rx_ring_move_fw(ring);
e5597095 3887
b2598318 3888 return 0;
e5597095
PL		 3889}
3890
b2598318 3891static int hns3_add_frag(struct hns3_enet_ring *ring)
e5597095 3892{
d35bced8
YL		 3893 struct sk_buff *skb = ring->skb;
3894 struct sk_buff *head_skb = skb;
81ae0e04 3895 struct sk_buff *new_skb;
e5597095 3896 struct hns3_desc_cb *desc_cb;
b2598318 3897 struct hns3_desc *desc;
e5597095 3898 u32 bd_base_info;
e5597095 3899
b2598318 3900 do {
e5597095
PL		 3901 desc = &ring->desc[ring->next_to_clean];
3902 desc_cb = &ring->desc_cb[ring->next_to_clean];
3903 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 3904 /* make sure HW write desc complete */
3905 dma_rmb();
e8149933 3906 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 3907 return -ENXIO;
3908
81ae0e04 3909 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
7fda3a93 3910 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
81ae0e04 3911 if (unlikely(!new_skb)) {
c8711956 3912 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5 3913 "alloc rx fraglist skb fail\n");
81ae0e04
PL		 3914 return -ENXIO;
3915 }
93188e96
YL		 3916
3917 if (ring->page_pool)
3918 skb_mark_for_recycle(new_skb);
3919
81ae0e04
PL		 3920 ring->frag_num = 0;
3921
3922 if (ring->tail_skb) {
3923 ring->tail_skb->next = new_skb;
3924 ring->tail_skb = new_skb;
3925 } else {
3926 skb_shinfo(skb)->frag_list = new_skb;
3927 ring->tail_skb = new_skb;
3928 }
3929 }
3930
3931 if (ring->tail_skb) {
dbba6da0 3932 head_skb->truesize += hns3_buf_size(ring);
81ae0e04
PL		 3933 head_skb->data_len += le16_to_cpu(desc->rx.size);
3934 head_skb->len += le16_to_cpu(desc->rx.size);
3935 skb = ring->tail_skb;
3936 }
3937
c2a2e127
BS		 3938 dma_sync_single_for_cpu(ring_to_dev(ring),
3939 desc_cb->dma + desc_cb->page_offset,
3940 hns3_buf_size(ring),
3941 DMA_FROM_DEVICE);
3942
81ae0e04 3943 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
698a8954 3944 trace_hns3_rx_desc(ring);
8c30e194 3945 hns3_rx_ring_move_fw(ring);
e5597095 3946 ring->pending_buf++;
b2598318 3947 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
e5597095
PL		 3948
3949 return 0;
3950}
3951
d474d88f
YL		 3952static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
3953 struct sk_buff *skb, u32 l234info,
1ddc028a 3954 u32 bd_base_info, u32 ol_info, u16 csum)
a6d53b97 3955{
79664077
HT		 3956 struct net_device *netdev = ring_to_netdev(ring);
3957 struct hns3_nic_priv *priv = netdev_priv(netdev);
a6d53b97
PL		 3958 u32 l3_type;
3959
e2ee1c5a
YL		 3960 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
3961 HNS3_RXD_GRO_SIZE_M,
3962 HNS3_RXD_GRO_SIZE_S);
a6d53b97 3963 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 3964 if (!skb_shinfo(skb)->gso_size) {
1ddc028a
HT		 3965 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
3966 csum);
d474d88f
YL		 3967 return 0;
3968 }
a6d53b97 3969
e2ee1c5a
YL		 3970 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
3971 HNS3_RXD_GRO_COUNT_M,
3972 HNS3_RXD_GRO_COUNT_S);
a6d53b97 3973
79664077
HT		 3974 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
3975 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3976 HNS3_RXD_PTYPE_S);
3977
3978 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
3979 } else {
3980 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3981 HNS3_RXD_L3ID_S);
3982 }
3983
a6d53b97
PL		 3984 if (l3_type == HNS3_L3_TYPE_IPV4)
3985 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
3986 else if (l3_type == HNS3_L3_TYPE_IPV6)
3987 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
3988 else
d474d88f 3989 return -EFAULT;
a6d53b97 3990
e2ee1c5a 3991 return hns3_gro_complete(skb, l234info);
a6d53b97
PL		 3992}
3993
232fc64b 3994static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 3995 struct sk_buff *skb, u32 rss_hash)
232fc64b 3996{
232fc64b
PL		 3997 struct hnae3_handle *handle = ring->tqp->handle;
3998 enum pkt_hash_types rss_type;
3999
ea485867 4000 if (rss_hash)
232fc64b
PL		 4001 rss_type = handle->kinfo.rss_type;
4002 else
4003 rss_type = PKT_HASH_TYPE_NONE;
4004
ea485867 4005 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 4006}
4007
ea485867 4008static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e 4009{
c8711956 4010 struct net_device *netdev = ring_to_netdev(ring);
c376fa1a 4011 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 4012 u32 bd_base_info, l234info, ol_info;
ea485867 4013 struct hns3_desc *desc;
d474d88f 4014 unsigned int len;
ea485867 4015 int pre_ntc, ret;
1ddc028a 4016 u16 csum;
ea485867
YL		 4017
4018 /* bdinfo handled below is only valid on the last BD of the
4019 * current packet, and ring->next_to_clean indicates the first
4020 * descriptor of next packet, so need - 1 below.
4021 */
4022 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4023 (ring->desc_num - 1);
4024 desc = &ring->desc[pre_ntc];
4025 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4026 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 4027 ol_info = le32_to_cpu(desc->rx.ol_info);
1ddc028a 4028 csum = le16_to_cpu(desc->csum);
d474d88f 4029
0bf5eb78
HT		 4030 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4031 struct hnae3_handle *h = hns3_get_handle(netdev);
4032 u32 nsec = le32_to_cpu(desc->ts_nsec);
4033 u32 sec = le32_to_cpu(desc->ts_sec);
4034
4035 if (h->ae_algo->ops->get_rx_hwts)
4036 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4037 }
4038
d474d88f
YL		 4039 /* Based on hw strategy, the tag offloaded will be stored at
4040 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4041 * in one layer tag case.
4042 */
4043 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4044 u16 vlan_tag;
4045
4046 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4047 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4048 vlan_tag);
4049 }
4050
d474d88f
YL		 4051 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4052 BIT(HNS3_RXD_L2E_B))))) {
4053 u64_stats_update_begin(&ring->syncp);
4054 if (l234info & BIT(HNS3_RXD_L2E_B))
4055 ring->stats.l2_err++;
4056 else
4057 ring->stats.err_pkt_len++;
4058 u64_stats_update_end(&ring->syncp);
4059
4060 return -EFAULT;
4061 }
4062
4063 len = skb->len;
4064
4065 /* Do update ip stack process */
4066 skb->protocol = eth_type_trans(skb, netdev);
4067
4068 /* This is needed in order to enable forwarding support */
39c38824 4069 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
1ddc028a 4070 bd_base_info, ol_info, csum);
d474d88f
YL		 4071 if (unlikely(ret)) {
4072 u64_stats_update_begin(&ring->syncp);
4073 ring->stats.rx_err_cnt++;
4074 u64_stats_update_end(&ring->syncp);
4075 return ret;
4076 }
4077
4078 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4079 HNS3_RXD_DMAC_S);
4080
4081 u64_stats_update_begin(&ring->syncp);
4082 ring->stats.rx_pkts++;
4083 ring->stats.rx_bytes += len;
4084
4085 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4086 ring->stats.rx_multicast++;
4087
4088 u64_stats_update_end(&ring->syncp);
4089
4090 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 4091
4092 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 4093 return 0;
4094}
4095
d35bced8 4096static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
d474d88f 4097{
e5597095 4098 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 4099 struct hns3_desc_cb *desc_cb;
4100 struct hns3_desc *desc;
b9a8f883 4101 unsigned int length;
76ad4f0e 4102 u32 bd_base_info;
e5597095 4103 int ret;
76ad4f0e
S		 4104
4105 desc = &ring->desc[ring->next_to_clean];
4106 desc_cb = &ring->desc_cb[ring->next_to_clean];
4107
4108 prefetch(desc);
4109
8c30e194
YL		 4110 if (!skb) {
4111 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
8c30e194
YL		 4112 /* Check valid BD */
4113 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4114 return -ENXIO;
4115
4116 dma_rmb();
4117 length = le16_to_cpu(desc->rx.size);
76ad4f0e 4118
cb0e3e61 4119 ring->va = desc_cb->buf + desc_cb->page_offset;
76ad4f0e 4120
c2a2e127
BS		 4121 dma_sync_single_for_cpu(ring_to_dev(ring),
4122 desc_cb->dma + desc_cb->page_offset,
4123 hns3_buf_size(ring),
4124 DMA_FROM_DEVICE);
c2a2e127 4125
8c30e194
YL		 4126 /* Prefetch first cache line of first page.
4127 * Idea is to cache few bytes of the header of the packet.
4128 * Our L1 Cache line size is 64B so need to prefetch twice to make
4129 * it 128B. But in actual we can have greater size of caches with
4130 * 128B Level 1 cache lines. In such a case, single fetch would
4131 * suffice to cache in the relevant part of the header.
4132 */
4133 net_prefetch(ring->va);
76ad4f0e 4134
e5597095 4135 ret = hns3_alloc_skb(ring, length, ring->va);
d35bced8 4136 skb = ring->skb;
76ad4f0e 4137
e5597095
PL		 4138 if (ret < 0) /* alloc buffer fail */
4139 return ret;
b2598318
YL		 4140 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4141 ret = hns3_add_frag(ring);
e5597095
PL		 4142 if (ret)
4143 return ret;
e5597095 4144 }
76ad4f0e 4145 } else {
b2598318 4146 ret = hns3_add_frag(ring);
e5597095
PL		 4147 if (ret)
4148 return ret;
b2598318 4149 }
76ad4f0e 4150
b2598318
YL		 4151 /* As the head data may be changed when GRO enable, copy
4152 * the head data in after other data rx completed
4153 */
4154 if (skb->len > HNS3_RX_HEAD_SIZE)
e5597095
PL		 4155 memcpy(skb->data, ring->va,
4156 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e 4157
ea485867 4158 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 4159 if (unlikely(ret)) {
76ad4f0e 4160 dev_kfree_skb_any(skb);
d474d88f 4161 return ret;
76ad4f0e
S		 4162 }
4163
d93ed94f 4164 skb_record_rx_queue(skb, ring->tqp->tqp_index);
76ad4f0e
S		 4165 return 0;
4166}
4167
9b2f3477
WL		 4168int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4169 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 4170{
4171#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
63380a1a 4172 int unused_count = hns3_desc_unused(ring);
a4ee7624 4173 int recv_pkts = 0;
8c30e194 4174 int err;
76ad4f0e 4175
63380a1a 4176 unused_count -= ring->pending_buf;
76ad4f0e 4177
8c30e194 4178 while (recv_pkts < budget) {
76ad4f0e 4179 /* Reuse or realloc buffers */
a4ee7624
YL		 4180 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4181 hns3_nic_alloc_rx_buffers(ring, unused_count);
e5597095
PL		 4182 unused_count = hns3_desc_unused(ring) -
4183 ring->pending_buf;
76ad4f0e
S		 4184 }
4185
4186 /* Poll one pkt */
d35bced8
YL		 4187 err = hns3_handle_rx_bd(ring);
4188 /* Do not get FE for the packet or failed to alloc skb */
4189 if (unlikely(!ring->skb || err == -ENXIO)) {
76ad4f0e 4190 goto out;
d35bced8
YL		 4191 } else if (likely(!err)) {
4192 rx_fn(ring, ring->skb);
4193 recv_pkts++;
76ad4f0e
S		 4194 }
4195
a4ee7624 4196 unused_count += ring->pending_buf;
e5597095
PL		 4197 ring->skb = NULL;
4198 ring->pending_buf = 0;
76ad4f0e
S		 4199 }
4200
4201out:
4202 /* Make all data has been write before submit */
a4ee7624
YL		 4203 if (unused_count > 0)
4204 hns3_nic_alloc_rx_buffers(ring, unused_count);
76ad4f0e
S		 4205
4206 return recv_pkts;
4207}
4208
307ea4ce 4209static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
76ad4f0e 4210{
307ea4ce
HT		 4211 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4212 struct dim_sample sample = {};
4a43caf5 4213
307ea4ce
HT		 4214 if (!rx_group->coal.adapt_enable)
4215 return;
76ad4f0e 4216
307ea4ce
HT		 4217 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4218 rx_group->total_bytes, &sample);
4219 net_dim(&rx_group->dim, sample);
76ad4f0e
S		 4220}
4221
307ea4ce 4222static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
76ad4f0e 4223{
8b1ff1ea 4224 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
307ea4ce 4225 struct dim_sample sample = {};
8b1ff1ea 4226
307ea4ce 4227 if (!tx_group->coal.adapt_enable)
cd9d187b 4228 return;
cd9d187b 4229
307ea4ce
HT		 4230 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4231 tx_group->total_bytes, &sample);
4232 net_dim(&tx_group->dim, sample);
76ad4f0e
S		 4233}
4234
4235static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4236{
ff0699e0 4237 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 4238 struct hns3_enet_ring *ring;
4239 int rx_pkt_total = 0;
4240
4241 struct hns3_enet_tqp_vector *tqp_vector =
4242 container_of(napi, struct hns3_enet_tqp_vector, napi);
4243 bool clean_complete = true;
ceca4a5e 4244 int rx_budget = budget;
76ad4f0e 4245
ff0699e0
HT		 4246 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4247 napi_complete(napi);
4248 return 0;
4249 }
4250
76ad4f0e
S		 4251 /* Since the actual Tx work is minimal, we can give the Tx a larger
4252 * budget and be more aggressive about cleaning up the Tx descriptors.
4253 */
799997a3 4254 hns3_for_each_ring(ring, tqp_vector->tx_group)
619ae331 4255 hns3_clean_tx_ring(ring, budget);
76ad4f0e
S		 4256
4257 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 4258 if (tqp_vector->num_tqps > 1)
4259 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 4260
4261 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 4262 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4263 hns3_rx_skb);
76ad4f0e
S		 4264 if (rx_cleaned >= rx_budget)
4265 clean_complete = false;
4266
4267 rx_pkt_total += rx_cleaned;
4268 }
4269
4270 tqp_vector->rx_group.total_packets += rx_pkt_total;
4271
4272 if (!clean_complete)
4273 return budget;
4274
531eba0f
HT		 4275 if (napi_complete(napi) &&
4276 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
307ea4ce
HT		 4277 hns3_update_rx_int_coalesce(tqp_vector);
4278 hns3_update_tx_int_coalesce(tqp_vector);
4279
ff0699e0
HT		 4280 hns3_mask_vector_irq(tqp_vector, 1);
4281 }
76ad4f0e
S		 4282
4283 return rx_pkt_total;
4284}
4285
4286static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4287 struct hnae3_ring_chain_node *head)
4288{
4289 struct pci_dev *pdev = tqp_vector->handle->pdev;
4290 struct hnae3_ring_chain_node *cur_chain = head;
4291 struct hnae3_ring_chain_node *chain;
4292 struct hns3_enet_ring *tx_ring;
4293 struct hns3_enet_ring *rx_ring;
4294
4295 tx_ring = tqp_vector->tx_group.ring;
4296 if (tx_ring) {
4297 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 4298 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4299 HNAE3_RING_TYPE_TX);
4300 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4301 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 4302
4303 cur_chain->next = NULL;
4304
4305 while (tx_ring->next) {
4306 tx_ring = tx_ring->next;
4307
4308 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
4309 GFP_KERNEL);
4310 if (!chain)
73b907a0 4311 goto err_free_chain;
76ad4f0e
S		 4312
4313 cur_chain->next = chain;
4314 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 4315 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4316 HNAE3_RING_TYPE_TX);
4317 hnae3_set_field(chain->int_gl_idx,
4318 HNAE3_RING_GL_IDX_M,
4319 HNAE3_RING_GL_IDX_S,
4320 HNAE3_RING_GL_TX);
76ad4f0e
S		 4321
4322 cur_chain = chain;
4323 }
4324 }
4325
4326 rx_ring = tqp_vector->rx_group.ring;
4327 if (!tx_ring && rx_ring) {
4328 cur_chain->next = NULL;
4329 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 4330 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4331 HNAE3_RING_TYPE_RX);
4332 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4333 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 4334
4335 rx_ring = rx_ring->next;
4336 }
4337
4338 while (rx_ring) {
4339 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4340 if (!chain)
73b907a0 4341 goto err_free_chain;
76ad4f0e
S		 4342
4343 cur_chain->next = chain;
4344 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 4345 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4346 HNAE3_RING_TYPE_RX);
4347 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4348 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 4349
76ad4f0e
S		 4350 cur_chain = chain;
4351
4352 rx_ring = rx_ring->next;
4353 }
4354
4355 return 0;
73b907a0
HT		 4356
4357err_free_chain:
4358 cur_chain = head->next;
4359 while (cur_chain) {
4360 chain = cur_chain->next;
cda69d24 4361 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 4362 cur_chain = chain;
4363 }
cda69d24 4364 head->next = NULL;
73b907a0
HT		 4365
4366 return -ENOMEM;
76ad4f0e
S		 4367}
4368
4369static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4370 struct hnae3_ring_chain_node *head)
4371{
4372 struct pci_dev *pdev = tqp_vector->handle->pdev;
4373 struct hnae3_ring_chain_node *chain_tmp, *chain;
4374
4375 chain = head->next;
4376
4377 while (chain) {
4378 chain_tmp = chain->next;
4379 devm_kfree(&pdev->dev, chain);
4380 chain = chain_tmp;
4381 }
4382}
4383
4384static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4385 struct hns3_enet_ring *ring)
4386{
4387 ring->next = group->ring;
4388 group->ring = ring;
4389
4390 group->count++;
4391}
4392
874bff0b
PL		 4393static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4394{
4395 struct pci_dev *pdev = priv->ae_handle->pdev;
4396 struct hns3_enet_tqp_vector *tqp_vector;
4397 int num_vectors = priv->vector_num;
4398 int numa_node;
4399 int vector_i;
4400
4401 numa_node = dev_to_node(&pdev->dev);
4402
4403 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4404 tqp_vector = &priv->tqp_vector[vector_i];
4405 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4406 &tqp_vector->affinity_mask);
4407 }
4408}
4409
307ea4ce
HT		 4410static void hns3_rx_dim_work(struct work_struct *work)
4411{
4412 struct dim *dim = container_of(work, struct dim, work);
4413 struct hns3_enet_ring_group *group = container_of(dim,
4414 struct hns3_enet_ring_group, dim);
4415 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4416 struct dim_cq_moder cur_moder =
4417 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4418
4419 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4420 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4421
4422 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4423 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4424 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4425 }
4426
4427 dim->state = DIM_START_MEASURE;
4428}
4429
4430static void hns3_tx_dim_work(struct work_struct *work)
4431{
4432 struct dim *dim = container_of(work, struct dim, work);
4433 struct hns3_enet_ring_group *group = container_of(dim,
4434 struct hns3_enet_ring_group, dim);
4435 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4436 struct dim_cq_moder cur_moder =
4437 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4438
4439 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4440 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4441
4442 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4443 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4444 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4445 }
4446
4447 dim->state = DIM_START_MEASURE;
4448}
4449
4450static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4451{
4452 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
307ea4ce 4453 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
307ea4ce
HT		 4454}
4455
76ad4f0e
S		 4456static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4457{
76ad4f0e
S		 4458 struct hnae3_handle *h = priv->ae_handle;
4459 struct hns3_enet_tqp_vector *tqp_vector;
9d8d5a36 4460 int ret;
ece4bf46 4461 int i;
76ad4f0e 4462
874bff0b
PL		 4463 hns3_nic_set_cpumask(priv);
4464
dd38c726
YL		 4465 for (i = 0; i < priv->vector_num; i++) {
4466 tqp_vector = &priv->tqp_vector[i];
91bfae25 4467 hns3_vector_coalesce_init_hw(tqp_vector, priv);
dd38c726 4468 tqp_vector->num_tqps = 0;
307ea4ce 4469 hns3_nic_init_dim(tqp_vector);
dd38c726 4470 }
76ad4f0e 4471
dd38c726
YL		 4472 for (i = 0; i < h->kinfo.num_tqps; i++) {
4473 u16 vector_i = i % priv->vector_num;
4474 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 4475
4476 tqp_vector = &priv->tqp_vector[vector_i];
4477
4478 hns3_add_ring_to_group(&tqp_vector->tx_group,
5f06b903 4479 &priv->ring[i]);
76ad4f0e
S		 4480
4481 hns3_add_ring_to_group(&tqp_vector->rx_group,
5f06b903 4482 &priv->ring[i + tqp_num]);
76ad4f0e 4483
5f06b903
YL		 4484 priv->ring[i].tqp_vector = tqp_vector;
4485 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
dd38c726 4486 tqp_vector->num_tqps++;
76ad4f0e
S		 4487 }
4488
dd38c726 4489 for (i = 0; i < priv->vector_num; i++) {
d392ecd1
SM		 4490 struct hnae3_ring_chain_node vector_ring_chain;
4491
76ad4f0e
S		 4492 tqp_vector = &priv->tqp_vector[i];
4493
4494 tqp_vector->rx_group.total_bytes = 0;
4495 tqp_vector->rx_group.total_packets = 0;
4496 tqp_vector->tx_group.total_bytes = 0;
4497 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 4498 tqp_vector->handle = h;
4499
4500 ret = hns3_get_vector_ring_chain(tqp_vector,
4501 &vector_ring_chain);
4502 if (ret)
cda69d24 4503 goto map_ring_fail;
76ad4f0e
S		 4504
4505 ret = h->ae_algo->ops->map_ring_to_vector(h,
4506 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 4507
4508 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4509
dd38c726 4510 if (ret)
ece4bf46 4511 goto map_ring_fail;
dd38c726 4512
76ad4f0e
S		 4513 netif_napi_add(priv->netdev, &tqp_vector->napi,
4514 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
4515 }
4516
dd38c726 4517 return 0;
ece4bf46
HT		 4518
4519map_ring_fail:
4520 while (i--)
4521 netif_napi_del(&priv->tqp_vector[i].napi);
4522
4523 return ret;
dd38c726
YL		 4524}
4525
73a13d8d
HT		 4526static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4527{
4528 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4529 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4530 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4531
4532 /* initialize the configuration for interrupt coalescing.
4533 * 1. GL (Interrupt Gap Limiter)
4534 * 2. RL (Interrupt Rate Limiter)
4535 * 3. QL (Interrupt Quantity Limiter)
4536 *
4537 * Default: enable interrupt coalescing self-adaptive and GL
4538 */
4539 tx_coal->adapt_enable = 1;
4540 rx_coal->adapt_enable = 1;
4541
4542 tx_coal->int_gl = HNS3_INT_GL_50K;
4543 rx_coal->int_gl = HNS3_INT_GL_50K;
4544
4545 rx_coal->flow_level = HNS3_FLOW_LOW;
4546 tx_coal->flow_level = HNS3_FLOW_LOW;
4547
4548 if (ae_dev->dev_specs.int_ql_max) {
4549 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4550 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4551 }
4552}
4553
dd38c726
YL		 4554static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4555{
4556 struct hnae3_handle *h = priv->ae_handle;
4557 struct hns3_enet_tqp_vector *tqp_vector;
4558 struct hnae3_vector_info *vector;
4559 struct pci_dev *pdev = h->pdev;
4560 u16 tqp_num = h->kinfo.num_tqps;
4561 u16 vector_num;
4562 int ret = 0;
4563 u16 i;
4564
4565 /* RSS size, cpu online and vector_num should be the same */
4566 /* Should consider 2p/4p later */
4567 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610 4568
dd38c726
YL		 4569 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4570 GFP_KERNEL);
4571 if (!vector)
4572 return -ENOMEM;
4573
9b2f3477 4574 /* save the actual available vector number */
dd38c726
YL		 4575 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4576
4577 priv->vector_num = vector_num;
4578 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4579 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4580 GFP_KERNEL);
4581 if (!priv->tqp_vector) {
4582 ret = -ENOMEM;
4583 goto out;
4584 }
4585
4586 for (i = 0; i < priv->vector_num; i++) {
4587 tqp_vector = &priv->tqp_vector[i];
4588 tqp_vector->idx = i;
4589 tqp_vector->mask_addr = vector[i].io_addr;
4590 tqp_vector->vector_irq = vector[i].vector;
91bfae25 4591 hns3_vector_coalesce_init(tqp_vector, priv);
dd38c726
YL		 4592 }
4593
76ad4f0e
S		 4594out:
4595 devm_kfree(&pdev->dev, vector);
4596 return ret;
4597}
4598
dd38c726
YL		 4599static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4600{
4601 group->ring = NULL;
4602 group->count = 0;
4603}
4604
e2152785 4605static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 4606{
4607 struct hnae3_ring_chain_node vector_ring_chain;
4608 struct hnae3_handle *h = priv->ae_handle;
4609 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 4610 int i;
76ad4f0e
S		 4611
4612 for (i = 0; i < priv->vector_num; i++) {
4613 tqp_vector = &priv->tqp_vector[i];
4614
2c9dd668
HT		 4615 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4616 continue;
4617
ff7dfcdd
HT		 4618 /* Since the mapping can be overwritten, when fail to get the
4619 * chain between vector and ring, we should go on to deal with
4620 * the remaining options.
4621 */
4622 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
4623 dev_warn(priv->dev, "failed to get ring chain\n");
76ad4f0e 4624
e2152785 4625 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 4626 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 4627
4628 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4629
dd38c726
YL		 4630 hns3_clear_ring_group(&tqp_vector->rx_group);
4631 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 4632 netif_napi_del(&priv->tqp_vector[i].napi);
4633 }
dd38c726
YL		 4634}
4635
08a10068 4636static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
dd38c726
YL		 4637{
4638 struct hnae3_handle *h = priv->ae_handle;
4639 struct pci_dev *pdev = h->pdev;
4640 int i, ret;
4641
4642 for (i = 0; i < priv->vector_num; i++) {
4643 struct hns3_enet_tqp_vector *tqp_vector;
4644
4645 tqp_vector = &priv->tqp_vector[i];
4646 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4647 if (ret)
08a10068 4648 return;
dd38c726 4649 }
76ad4f0e 4650
dd38c726 4651 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 4652}
4653
5f06b903
YL		 4654static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4655 unsigned int ring_type)
76ad4f0e 4656{
76ad4f0e 4657 int queue_num = priv->ae_handle->kinfo.num_tqps;
76ad4f0e 4658 struct hns3_enet_ring *ring;
c0425944 4659 int desc_num;
76ad4f0e 4660
76ad4f0e 4661 if (ring_type == HNAE3_RING_TYPE_TX) {
5f06b903 4662 ring = &priv->ring[q->tqp_index];
c0425944 4663 desc_num = priv->ae_handle->kinfo.num_tx_desc;
5f06b903 4664 ring->queue_index = q->tqp_index;
907676b1
YL		 4665 ring->tx_copybreak = priv->tx_copybreak;
4666 ring->last_to_use = 0;
76ad4f0e 4667 } else {
5f06b903 4668 ring = &priv->ring[q->tqp_index + queue_num];
c0425944 4669 desc_num = priv->ae_handle->kinfo.num_rx_desc;
5f06b903 4670 ring->queue_index = q->tqp_index;
99f6b5fb 4671 ring->rx_copybreak = priv->rx_copybreak;
76ad4f0e
S		 4672 }
4673
e4e87715 4674 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 4675
76ad4f0e
S		 4676 ring->tqp = q;
4677 ring->desc = NULL;
4678 ring->desc_cb = NULL;
4679 ring->dev = priv->dev;
4680 ring->desc_dma_addr = 0;
4681 ring->buf_size = q->buf_size;
2c9dd668 4682 ring->desc_num = desc_num;
76ad4f0e
S		 4683 ring->next_to_use = 0;
4684 ring->next_to_clean = 0;
76ad4f0e
S		 4685}
4686
5f06b903
YL		 4687static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4688 struct hns3_nic_priv *priv)
76ad4f0e 4689{
5f06b903
YL		 4690 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4691 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
76ad4f0e
S		 4692}
4693
4694static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4695{
4696 struct hnae3_handle *h = priv->ae_handle;
4697 struct pci_dev *pdev = h->pdev;
5f06b903 4698 int i;
76ad4f0e 4699
5f06b903
YL		 4700 priv->ring = devm_kzalloc(&pdev->dev,
4701 array3_size(h->kinfo.num_tqps,
4702 sizeof(*priv->ring), 2),
4703 GFP_KERNEL);
4704 if (!priv->ring)
76ad4f0e
S		 4705 return -ENOMEM;
4706
5f06b903
YL		 4707 for (i = 0; i < h->kinfo.num_tqps; i++)
4708 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
76ad4f0e
S		 4709
4710 return 0;
76ad4f0e
S		 4711}
4712
09f2af64
PL		 4713static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4714{
5f06b903 4715 if (!priv->ring)
7b8f622e
HT		 4716 return;
4717
5f06b903
YL		 4718 devm_kfree(priv->dev, priv->ring);
4719 priv->ring = NULL;
09f2af64
PL		 4720}
4721
93188e96
YL		 4722static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4723{
4724 struct page_pool_params pp_params = {
4725 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4726 PP_FLAG_DMA_SYNC_DEV,
4727 .order = hns3_page_order(ring),
4728 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4729 (PAGE_SIZE << hns3_page_order(ring)),
4730 .nid = dev_to_node(ring_to_dev(ring)),
4731 .dev = ring_to_dev(ring),
4732 .dma_dir = DMA_FROM_DEVICE,
4733 .offset = 0,
4734 .max_len = PAGE_SIZE << hns3_page_order(ring),
4735 };
4736
4737 ring->page_pool = page_pool_create(&pp_params);
4738 if (IS_ERR(ring->page_pool)) {
4739 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4740 PTR_ERR(ring->page_pool));
4741 ring->page_pool = NULL;
4742 }
4743}
4744
76ad4f0e
S		 4745static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4746{
4747 int ret;
4748
4749 if (ring->desc_num <= 0 || ring->buf_size <= 0)
4750 return -EINVAL;
4751
77296bf6
YL		 4752 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4753 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 4754 if (!ring->desc_cb) {
4755 ret = -ENOMEM;
4756 goto out;
4757 }
4758
4759 ret = hns3_alloc_desc(ring);
4760 if (ret)
4761 goto out_with_desc_cb;
4762
4763 if (!HNAE3_IS_TX_RING(ring)) {
f7ec554b
YL		 4764 if (page_pool_enabled)
4765 hns3_alloc_page_pool(ring);
93188e96 4766
76ad4f0e
S		 4767 ret = hns3_alloc_ring_buffers(ring);
4768 if (ret)
4769 goto out_with_desc;
907676b1
YL		 4770 } else {
4771 hns3_init_tx_spare_buffer(ring);
76ad4f0e
S		 4772 }
4773
4774 return 0;
4775
4776out_with_desc:
4777 hns3_free_desc(ring);
4778out_with_desc_cb:
77296bf6 4779 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 4780 ring->desc_cb = NULL;
4781out:
4782 return ret;
4783}
4784
a723fb8e 4785void hns3_fini_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 4786{
4787 hns3_free_desc(ring);
77296bf6 4788 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 4789 ring->desc_cb = NULL;
4790 ring->next_to_clean = 0;
4791 ring->next_to_use = 0;
20d06ca2 4792 ring->last_to_use = 0;
ac574b80 4793 ring->pending_buf = 0;
907676b1 4794 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
ac574b80
PL		 4795 dev_kfree_skb_any(ring->skb);
4796 ring->skb = NULL;
907676b1
YL		 4797 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
4798 struct hns3_tx_spare *tx_spare = ring->tx_spare;
4799
4800 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
4801 DMA_TO_DEVICE);
4802 free_pages((unsigned long)tx_spare->buf,
4803 get_order(tx_spare->len));
4804 devm_kfree(ring_to_dev(ring), tx_spare);
4805 ring->tx_spare = NULL;
ac574b80 4806 }
93188e96
YL		 4807
4808 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
4809 page_pool_destroy(ring->page_pool);
4810 ring->page_pool = NULL;
4811 }
76ad4f0e
S		 4812}
4813
1db9b1bf 4814static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 4815{
4816 int bd_size_type;
4817
4818 switch (buf_size) {
4819 case 512:
4820 bd_size_type = HNS3_BD_SIZE_512_TYPE;
4821 break;
4822 case 1024:
4823 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
4824 break;
4825 case 2048:
4826 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4827 break;
4828 case 4096:
4829 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
4830 break;
4831 default:
4832 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4833 }
4834
4835 return bd_size_type;
4836}
4837
4838static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
4839{
4840 dma_addr_t dma = ring->desc_dma_addr;
4841 struct hnae3_queue *q = ring->tqp;
4842
4843 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 4844 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S		 4845 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
4846 (u32)((dma >> 31) >> 1));
4847
4848 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
4849 hns3_buf_size2type(ring->buf_size));
4850 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
4851 ring->desc_num / 8 - 1);
76ad4f0e
S		 4852 } else {
4853 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
4854 (u32)dma);
4855 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
4856 (u32)((dma >> 31) >> 1));
4857
76ad4f0e
S		 4858 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
4859 ring->desc_num / 8 - 1);
4860 }
4861}
4862
1c772154
YL		 4863static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
4864{
4865 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
35244430 4866 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
1c772154
YL		 4867 int i;
4868
a8e76fef 4869 for (i = 0; i < tc_info->num_tc; i++) {
1c772154
YL		 4870 int j;
4871
35244430 4872 for (j = 0; j < tc_info->tqp_count[i]; j++) {
1c772154
YL		 4873 struct hnae3_queue *q;
4874
35244430
JS		 4875 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
4876 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
1c772154
YL		 4877 }
4878 }
4879}
4880
5668abda 4881int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 4882{
4883 struct hnae3_handle *h = priv->ae_handle;
4884 int ring_num = h->kinfo.num_tqps * 2;
4885 int i, j;
4886 int ret;
4887
4888 for (i = 0; i < ring_num; i++) {
5f06b903 4889 ret = hns3_alloc_ring_memory(&priv->ring[i]);
76ad4f0e
S		 4890 if (ret) {
4891 dev_err(priv->dev,
4892 "Alloc ring memory fail! ret=%d\n", ret);
4893 goto out_when_alloc_ring_memory;
4894 }
4895
5f06b903 4896 u64_stats_init(&priv->ring[i].syncp);
76ad4f0e
S		 4897 }
4898
4899 return 0;
4900
4901out_when_alloc_ring_memory:
4902 for (j = i - 1; j >= 0; j--)
5f06b903 4903 hns3_fini_ring(&priv->ring[j]);
76ad4f0e
S		 4904
4905 return -ENOMEM;
4906}
4907
64749c9c 4908static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 4909{
4910 struct hnae3_handle *h = priv->ae_handle;
4911 int i;
4912
4913 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903
YL		 4914 hns3_fini_ring(&priv->ring[i]);
4915 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
76ad4f0e 4916 }
76ad4f0e
S		 4917}
4918
4919/* Set mac addr if it is configured. or leave it to the AE driver */
8e6de441 4920static int hns3_init_mac_addr(struct net_device *netdev)
76ad4f0e
S		 4921{
4922 struct hns3_nic_priv *priv = netdev_priv(netdev);
4923 struct hnae3_handle *h = priv->ae_handle;
4924 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 4925 int ret = 0;
76ad4f0e 4926
8e6de441 4927 if (h->ae_algo->ops->get_mac_addr)
76ad4f0e 4928 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
76ad4f0e
S		 4929
4930 /* Check if the MAC address is valid, if not get a random one */
8e6de441 4931 if (!is_valid_ether_addr(mac_addr_temp)) {
76ad4f0e
S		 4932 eth_hw_addr_random(netdev);
4933 dev_warn(priv->dev, "using random MAC address %pM\n",
4934 netdev->dev_addr);
ee4bcd3b 4935 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
8e6de441
HT		 4936 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
4937 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
ee4bcd3b
JS		 4938 } else {
4939 return 0;
76ad4f0e 4940 }
139e8792
L		 4941
4942 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 4943 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 4944
7fa6be4f 4945 return ret;
76ad4f0e
S		 4946}
4947
c8a8045b
HT		 4948static int hns3_init_phy(struct net_device *netdev)
4949{
4950 struct hnae3_handle *h = hns3_get_handle(netdev);
4951 int ret = 0;
4952
4953 if (h->ae_algo->ops->mac_connect_phy)
4954 ret = h->ae_algo->ops->mac_connect_phy(h);
4955
4956 return ret;
4957}
4958
4959static void hns3_uninit_phy(struct net_device *netdev)
4960{
4961 struct hnae3_handle *h = hns3_get_handle(netdev);
4962
4963 if (h->ae_algo->ops->mac_disconnect_phy)
4964 h->ae_algo->ops->mac_disconnect_phy(h);
4965}
4966
a6d818e3
YL		 4967static int hns3_client_start(struct hnae3_handle *handle)
4968{
4969 if (!handle->ae_algo->ops->client_start)
4970 return 0;
4971
4972 return handle->ae_algo->ops->client_start(handle);
4973}
4974
4975static void hns3_client_stop(struct hnae3_handle *handle)
4976{
4977 if (!handle->ae_algo->ops->client_stop)
4978 return;
4979
4980 handle->ae_algo->ops->client_stop(handle);
4981}
4982
bb87be87
YL		 4983static void hns3_info_show(struct hns3_nic_priv *priv)
4984{
4985 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
4986
4987 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
adcf738b
GL		 4988 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
4989 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
4990 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
4991 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
4992 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
4993 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
35244430
JS		 4994 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
4995 kinfo->tc_info.num_tc);
adcf738b 4996 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
bb87be87
YL		 4997}
4998
9f0c6f4b
YM		 4999static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5000 enum dim_cq_period_mode mode, bool is_tx)
5001{
5002 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5003 struct hnae3_handle *handle = priv->ae_handle;
5004 int i;
5005
5006 if (is_tx) {
5007 priv->tx_cqe_mode = mode;
5008
5009 for (i = 0; i < priv->vector_num; i++)
5010 priv->tqp_vector[i].tx_group.dim.mode = mode;
5011 } else {
5012 priv->rx_cqe_mode = mode;
5013
5014 for (i = 0; i < priv->vector_num; i++)
5015 priv->tqp_vector[i].rx_group.dim.mode = mode;
5016 }
5017
5018 /* only device version above V3(include V3), GL can switch CQ/EQ
5019 * period mode.
5020 */
5021 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
5022 u32 new_mode;
5023 u64 reg;
5024
5025 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5026 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5027 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5028
5029 writel(new_mode, handle->kinfo.io_base + reg);
5030 }
5031}
5032
cce1689e
YM		 5033void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5034 enum dim_cq_period_mode tx_mode,
5035 enum dim_cq_period_mode rx_mode)
9f0c6f4b
YM		 5036{
5037 hns3_set_cq_period_mode(priv, tx_mode, true);
5038 hns3_set_cq_period_mode(priv, rx_mode, false);
5039}
5040
c511dfff
HT		 5041static void hns3_state_init(struct hnae3_handle *handle)
5042{
5043 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5044 struct net_device *netdev = handle->kinfo.netdev;
5045 struct hns3_nic_priv *priv = netdev_priv(netdev);
5046
5047 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5048
5049 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5050 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5051
5052 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5053 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5054
5055 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5056 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5057}
5058
76ad4f0e
S		 5059static int hns3_client_init(struct hnae3_handle *handle)
5060{
5061 struct pci_dev *pdev = handle->pdev;
fd665b3d 5062 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
0d43bf45 5063 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 5064 struct hns3_nic_priv *priv;
5065 struct net_device *netdev;
5066 int ret;
5067
0d43bf45
HT		 5068 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5069 &max_rss_size);
5070 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 5071 if (!netdev)
5072 return -ENOMEM;
5073
5074 priv = netdev_priv(netdev);
5075 priv->dev = &pdev->dev;
5076 priv->netdev = netdev;
5077 priv->ae_handle = handle;
f8fa222c 5078 priv->tx_timeout_count = 0;
fd665b3d 5079 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
b7b585c2 5080 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 5081
bb87be87
YL		 5082 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5083
76ad4f0e
S		 5084 handle->kinfo.netdev = netdev;
5085 handle->priv = (void *)priv;
5086
8e6de441 5087 hns3_init_mac_addr(netdev);
76ad4f0e
S		 5088
5089 hns3_set_default_feature(netdev);
5090
5091 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5092 netdev->priv_flags |= IFF_UNICAST_FLT;
5093 netdev->netdev_ops = &hns3_nic_netdev_ops;
5094 SET_NETDEV_DEV(netdev, &pdev->dev);
5095 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 5096
5097 /* Carrier off reporting is important to ethtool even BEFORE open */
5098 netif_carrier_off(netdev);
5099
5100 ret = hns3_get_ring_config(priv);
5101 if (ret) {
5102 ret = -ENOMEM;
5103 goto out_get_ring_cfg;
5104 }
5105
73a13d8d
HT		 5106 hns3_nic_init_coal_cfg(priv);
5107
dd38c726
YL		 5108 ret = hns3_nic_alloc_vector_data(priv);
5109 if (ret) {
5110 ret = -ENOMEM;
5111 goto out_alloc_vector_data;
5112 }
5113
76ad4f0e
S		 5114 ret = hns3_nic_init_vector_data(priv);
5115 if (ret) {
5116 ret = -ENOMEM;
5117 goto out_init_vector_data;
5118 }
5119
5120 ret = hns3_init_all_ring(priv);
5121 if (ret) {
5122 ret = -ENOMEM;
5f06b903 5123 goto out_init_ring;
76ad4f0e
S		 5124 }
5125
9f0c6f4b
YM		 5126 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5127 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5128
c8a8045b
HT		 5129 ret = hns3_init_phy(netdev);
5130 if (ret)
5131 goto out_init_phy;
5132
08a10068
YL		 5133 /* the device can work without cpu rmap, only aRFS needs it */
5134 ret = hns3_set_rx_cpu_rmap(netdev);
5135 if (ret)
5136 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5137
5138 ret = hns3_nic_init_irq(priv);
5139 if (ret) {
5140 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5141 hns3_free_rx_cpu_rmap(netdev);
5142 goto out_init_irq_fail;
5143 }
5144
a6d818e3
YL		 5145 ret = hns3_client_start(handle);
5146 if (ret) {
5147 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 5148 goto out_client_start;
a6d818e3
YL		 5149 }
5150
986743db
YL		 5151 hns3_dcbnl_setup(handle);
5152
5e69ea7e
YM		 5153 ret = hns3_dbg_init(handle);
5154 if (ret) {
5155 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5156 ret);
5157 goto out_client_start;
5158 }
b2292360 5159
e070c8b9 5160 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
a8e8b7ff 5161
c511dfff 5162 hns3_state_init(handle);
5e7414cd 5163
a289a7e5
JS		 5164 ret = register_netdev(netdev);
5165 if (ret) {
5166 dev_err(priv->dev, "probe register netdev fail!\n");
5167 goto out_reg_netdev_fail;
5168 }
5169
bb87be87
YL		 5170 if (netif_msg_drv(handle))
5171 hns3_info_show(priv);
5172
76ad4f0e
S		 5173 return ret;
5174
a289a7e5
JS		 5175out_reg_netdev_fail:
5176 hns3_dbg_uninit(handle);
18655128 5177out_client_start:
08a10068
YL		 5178 hns3_free_rx_cpu_rmap(netdev);
5179 hns3_nic_uninit_irq(priv);
5180out_init_irq_fail:
c8a8045b
HT		 5181 hns3_uninit_phy(netdev);
5182out_init_phy:
5183 hns3_uninit_all_ring(priv);
5f06b903 5184out_init_ring:
e2152785 5185 hns3_nic_uninit_vector_data(priv);
76ad4f0e 5186out_init_vector_data:
dd38c726
YL		 5187 hns3_nic_dealloc_vector_data(priv);
5188out_alloc_vector_data:
5f06b903 5189 priv->ring = NULL;
76ad4f0e
S		 5190out_get_ring_cfg:
5191 priv->ae_handle = NULL;
5192 free_netdev(netdev);
5193 return ret;
5194}
5195
5196static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5197{
5198 struct net_device *netdev = handle->kinfo.netdev;
5199 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 5200
5201 if (netdev->reg_state != NETREG_UNINITIALIZED)
5202 unregister_netdev(netdev);
5203
eb32c896
HT		 5204 hns3_client_stop(handle);
5205
0d2f68c7
HT		 5206 hns3_uninit_phy(netdev);
5207
814da63c
HT		 5208 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5209 netdev_warn(netdev, "already uninitialized\n");
5210 goto out_netdev_free;
5211 }
5212
08a10068
YL		 5213 hns3_free_rx_cpu_rmap(netdev);
5214
5215 hns3_nic_uninit_irq(priv);
5216
f96315f2 5217 hns3_clear_all_ring(handle, true);
7b763f3f 5218
e2152785 5219 hns3_nic_uninit_vector_data(priv);
76ad4f0e 5220
08a10068 5221 hns3_nic_dealloc_vector_data(priv);
dd38c726 5222
64749c9c 5223 hns3_uninit_all_ring(priv);
76ad4f0e 5224
ec777890
YL		 5225 hns3_put_ring_config(priv);
5226
814da63c 5227out_netdev_free:
e22b5e72 5228 hns3_dbg_uninit(handle);
76ad4f0e
S		 5229 free_netdev(netdev);
5230}
5231
5232static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5233{
5234 struct net_device *netdev = handle->kinfo.netdev;
5235
5236 if (!netdev)
5237 return;
5238
5239 if (linkup) {
76ad4f0e 5240 netif_tx_wake_all_queues(netdev);
a7e90ee5 5241 netif_carrier_on(netdev);
bb87be87
YL		 5242 if (netif_msg_link(handle))
5243 netdev_info(netdev, "link up\n");
76ad4f0e
S		 5244 } else {
5245 netif_carrier_off(netdev);
5246 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 5247 if (netif_msg_link(handle))
5248 netdev_info(netdev, "link down\n");
76ad4f0e
S		 5249 }
5250}
5251
beebca3a 5252static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 5253{
beebca3a 5254 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 5255 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
619ae331 5256 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
beebca3a
YL		 5257 ring_ptr_move_fw(ring, next_to_clean);
5258 }
f6061a05
YL		 5259
5260 ring->pending_buf = 0;
beebca3a
YL		 5261}
5262
7b763f3f
FL		 5263static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5264{
5265 struct hns3_desc_cb res_cbs;
5266 int ret;
5267
5268 while (ring->next_to_use != ring->next_to_clean) {
5269 /* When a buffer is not reused, it's memory has been
5270 * freed in hns3_handle_rx_bd or will be freed by
5271 * stack, so we need to replace the buffer here.
5272 */
5273 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4d2cad32 5274 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
7b763f3f
FL		 5275 if (ret) {
5276 u64_stats_update_begin(&ring->syncp);
5277 ring->stats.sw_err_cnt++;
5278 u64_stats_update_end(&ring->syncp);
5279 /* if alloc new buffer fail, exit directly
5280 * and reclear in up flow.
5281 */
c8711956 5282 netdev_warn(ring_to_netdev(ring),
7b763f3f
FL		 5283 "reserve buffer map failed, ret = %d\n",
5284 ret);
5285 return ret;
5286 }
9b2f3477 5287 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL		 5288 }
5289 ring_ptr_move_fw(ring, next_to_use);
5290 }
5291
cc5ff6e9
PL		 5292 /* Free the pending skb in rx ring */
5293 if (ring->skb) {
5294 dev_kfree_skb_any(ring->skb);
5295 ring->skb = NULL;
5296 ring->pending_buf = 0;
5297 }
5298
7b763f3f
FL		 5299 return 0;
5300}
5301
5302static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 5303{
beebca3a
YL		 5304 while (ring->next_to_use != ring->next_to_clean) {
5305 /* When a buffer is not reused, it's memory has been
5306 * freed in hns3_handle_rx_bd or will be freed by
5307 * stack, so only need to unmap the buffer here.
5308 */
5309 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5310 hns3_unmap_buffer(ring,
5311 &ring->desc_cb[ring->next_to_use]);
5312 ring->desc_cb[ring->next_to_use].dma = 0;
5313 }
5314
5315 ring_ptr_move_fw(ring, next_to_use);
5316 }
bb6b94a8
L		 5317}
5318
f96315f2 5319static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L		 5320{
5321 struct net_device *ndev = h->kinfo.netdev;
5322 struct hns3_nic_priv *priv = netdev_priv(ndev);
5323 u32 i;
5324
5325 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L		 5326 struct hns3_enet_ring *ring;
5327
5f06b903 5328 ring = &priv->ring[i];
beebca3a 5329 hns3_clear_tx_ring(ring);
bb6b94a8 5330
5f06b903 5331 ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 5332 /* Continue to clear other rings even if clearing some
5333 * rings failed.
5334 */
f96315f2
HT		 5335 if (force)
5336 hns3_force_clear_rx_ring(ring);
5337 else
5338 hns3_clear_rx_ring(ring);
bb6b94a8
L		 5339 }
5340}
5341
7b763f3f
FL		 5342int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5343{
5344 struct net_device *ndev = h->kinfo.netdev;
5345 struct hns3_nic_priv *priv = netdev_priv(ndev);
5346 struct hns3_enet_ring *rx_ring;
5347 int i, j;
5348 int ret;
5349
8fa86551
YM		 5350 ret = h->ae_algo->ops->reset_queue(h);
5351 if (ret)
5352 return ret;
7fa6be4f 5353
8fa86551 5354 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903 5355 hns3_init_ring_hw(&priv->ring[i]);
7b763f3f
FL		 5356
5357 /* We need to clear tx ring here because self test will
5358 * use the ring and will not run down before up
5359 */
5f06b903
YL		 5360 hns3_clear_tx_ring(&priv->ring[i]);
5361 priv->ring[i].next_to_clean = 0;
5362 priv->ring[i].next_to_use = 0;
20d06ca2 5363 priv->ring[i].last_to_use = 0;
7b763f3f 5364
5f06b903 5365 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 5366 hns3_init_ring_hw(rx_ring);
5367 ret = hns3_clear_rx_ring(rx_ring);
5368 if (ret)
5369 return ret;
5370
5371 /* We can not know the hardware head and tail when this
5372 * function is called in reset flow, so we reuse all desc.
5373 */
5374 for (j = 0; j < rx_ring->desc_num; j++)
5375 hns3_reuse_buffer(rx_ring, j);
5376
5377 rx_ring->next_to_clean = 0;
5378 rx_ring->next_to_use = 0;
5379 }
5380
1c772154
YL		 5381 hns3_init_tx_ring_tc(priv);
5382
7b763f3f
FL		 5383 return 0;
5384}
5385
bb6b94a8
L		 5386static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5387{
5388 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5389 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 5390 struct hns3_nic_priv *priv = netdev_priv(ndev);
5391
5392 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5393 return 0;
bb6b94a8
L		 5394
5395 if (!netif_running(ndev))
6b1385cc 5396 return 0;
bb6b94a8
L		 5397
5398 return hns3_nic_net_stop(ndev);
5399}
5400
5401static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5402{
5403 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 5404 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 5405 int ret = 0;
5406
b4047aac
JS		 5407 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5408 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5409 return -EFAULT;
5410 }
5411
e8884027
HT		 5412 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5413
bb6b94a8 5414 if (netif_running(kinfo->netdev)) {
e8884027 5415 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 5416 if (ret) {
e8884027 5417 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 5418 netdev_err(kinfo->netdev,
9b2f3477 5419 "net up fail, ret=%d!\n", ret);
bb6b94a8
L		 5420 return ret;
5421 }
bb6b94a8
L		 5422 }
5423
5424 return ret;
5425}
5426
5427static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5428{
5429 struct net_device *netdev = handle->kinfo.netdev;
5430 struct hns3_nic_priv *priv = netdev_priv(netdev);
5431 int ret;
5432
bb6b94a8
L		 5433 /* Carrier off reporting is important to ethtool even BEFORE open */
5434 netif_carrier_off(netdev);
5435
2c9dd668 5436 ret = hns3_get_ring_config(priv);
862d969a
HT		 5437 if (ret)
5438 return ret;
5439
2c9dd668
HT		 5440 ret = hns3_nic_alloc_vector_data(priv);
5441 if (ret)
5442 goto err_put_ring;
5443
bb6b94a8
L		 5444 ret = hns3_nic_init_vector_data(priv);
5445 if (ret)
862d969a 5446 goto err_dealloc_vector;
bb6b94a8
L		 5447
5448 ret = hns3_init_all_ring(priv);
862d969a
HT		 5449 if (ret)
5450 goto err_uninit_vector;
bb6b94a8 5451
9f0c6f4b
YM		 5452 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5453
08a10068
YL		 5454 /* the device can work without cpu rmap, only aRFS needs it */
5455 ret = hns3_set_rx_cpu_rmap(netdev);
5456 if (ret)
5457 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5458
5459 ret = hns3_nic_init_irq(priv);
5460 if (ret) {
5461 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5462 hns3_free_rx_cpu_rmap(netdev);
5463 goto err_init_irq_fail;
5464 }
5465
ee4bcd3b
JS		 5466 if (!hns3_is_phys_func(handle->pdev))
5467 hns3_init_mac_addr(netdev);
5468
cd513a69
HT		 5469 ret = hns3_client_start(handle);
5470 if (ret) {
5471 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
08a10068 5472 goto err_client_start_fail;
cd513a69
HT		 5473 }
5474
814da63c
HT		 5475 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5476
862d969a
HT		 5477 return ret;
5478
08a10068
YL		 5479err_client_start_fail:
5480 hns3_free_rx_cpu_rmap(netdev);
5481 hns3_nic_uninit_irq(priv);
5482err_init_irq_fail:
cd513a69 5483 hns3_uninit_all_ring(priv);
862d969a
HT		 5484err_uninit_vector:
5485 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 5486err_dealloc_vector:
5487 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 5488err_put_ring:
5489 hns3_put_ring_config(priv);
862d969a 5490
bb6b94a8
L		 5491 return ret;
5492}
5493
5494static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5495{
5496 struct net_device *netdev = handle->kinfo.netdev;
5497 struct hns3_nic_priv *priv = netdev_priv(netdev);
bb6b94a8 5498
1eeb3367 5499 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 5500 netdev_warn(netdev, "already uninitialized\n");
5501 return 0;
5502 }
5503
08a10068
YL		 5504 hns3_free_rx_cpu_rmap(netdev);
5505 hns3_nic_uninit_irq(priv);
f96315f2
HT		 5506 hns3_clear_all_ring(handle, true);
5507 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 5508
e2152785 5509 hns3_nic_uninit_vector_data(priv);
bb6b94a8 5510
08a10068 5511 hns3_nic_dealloc_vector_data(priv);
862d969a 5512
64749c9c 5513 hns3_uninit_all_ring(priv);
bb6b94a8 5514
2c9dd668 5515 hns3_put_ring_config(priv);
2c9dd668 5516
205238f4 5517 return 0;
bb6b94a8
L		 5518}
5519
5520static int hns3_reset_notify(struct hnae3_handle *handle,
5521 enum hnae3_reset_notify_type type)
5522{
5523 int ret = 0;
5524
5525 switch (type) {
5526 case HNAE3_UP_CLIENT:
e1586241
SM		 5527 ret = hns3_reset_notify_up_enet(handle);
5528 break;
bb6b94a8
L		 5529 case HNAE3_DOWN_CLIENT:
5530 ret = hns3_reset_notify_down_enet(handle);
5531 break;
5532 case HNAE3_INIT_CLIENT:
5533 ret = hns3_reset_notify_init_enet(handle);
5534 break;
5535 case HNAE3_UNINIT_CLIENT:
5536 ret = hns3_reset_notify_uninit_enet(handle);
5537 break;
5538 default:
5539 break;
5540 }
5541
5542 return ret;
5543}
5544
3a5a5f06
PL		 5545static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5546 bool rxfh_configured)
5547{
5548 int ret;
5549
5550 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5551 rxfh_configured);
5552 if (ret) {
5553 dev_err(&handle->pdev->dev,
5554 "Change tqp num(%u) fail.\n", new_tqp_num);
5555 return ret;
5556 }
5557
5558 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5559 if (ret)
5560 return ret;
5561
5562 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5563 if (ret)
5564 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5565
5566 return ret;
5567}
5568
09f2af64
PL		 5569int hns3_set_channels(struct net_device *netdev,
5570 struct ethtool_channels *ch)
5571{
09f2af64
PL		 5572 struct hnae3_handle *h = hns3_get_handle(netdev);
5573 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 5574 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 5575 u32 new_tqp_num = ch->combined_count;
5576 u16 org_tqp_num;
5577 int ret;
5578
44950d28
JS		 5579 if (hns3_nic_resetting(netdev))
5580 return -EBUSY;
5581
09f2af64
PL		 5582 if (ch->rx_count || ch->tx_count)
5583 return -EINVAL;
5584
5a5c9091
JS		 5585 if (kinfo->tc_info.mqprio_active) {
5586 dev_err(&netdev->dev,
5587 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5588 return -EINVAL;
5589 }
5590
678335a1 5591 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 5592 new_tqp_num < 1) {
09f2af64 5593 dev_err(&netdev->dev,
adcf738b 5594 "Change tqps fail, the tqp range is from 1 to %u",
678335a1 5595 hns3_get_max_available_channels(h));
09f2af64
PL		 5596 return -EINVAL;
5597 }
5598
c78b5b6c 5599 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 5600 return 0;
5601
1c822948
YL		 5602 netif_dbg(h, drv, netdev,
5603 "set channels: tqp_num=%u, rxfh=%d\n",
5604 new_tqp_num, rxfh_configured);
5605
65749f73
HT		 5606 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5607 if (ret)
5608 return ret;
dd38c726 5609
65749f73
HT		 5610 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5611 if (ret)
5612 return ret;
09f2af64
PL		 5613
5614 org_tqp_num = h->kinfo.num_tqps;
3a5a5f06 5615 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 5616 if (ret) {
3a5a5f06
PL		 5617 int ret1;
5618
5619 netdev_warn(netdev,
5620 "Change channels fail, revert to old value\n");
5621 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5622 if (ret1) {
5623 netdev_err(netdev,
5624 "revert to old channel fail\n");
5625 return ret1;
09f2af64 5626 }
3a5a5f06 5627
65749f73 5628 return ret;
3a5a5f06 5629 }
09f2af64 5630
3a5a5f06 5631 return 0;
09f2af64
PL		 5632}
5633
a83d2961
WL		 5634static const struct hns3_hw_error_info hns3_hw_err[] = {
5635 { .type = HNAE3_PPU_POISON_ERROR,
5636 .msg = "PPU poison" },
5637 { .type = HNAE3_CMDQ_ECC_ERROR,
5638 .msg = "IMP CMDQ error" },
5639 { .type = HNAE3_IMP_RD_POISON_ERROR,
5640 .msg = "IMP RD poison" },
6cd131dd
YM		 5641 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5642 .msg = "ROCEE AXI RESP error" },
a83d2961
WL		 5643};
5644
5645static void hns3_process_hw_error(struct hnae3_handle *handle,
5646 enum hnae3_hw_error_type type)
5647{
5648 int i;
5649
5650 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5651 if (hns3_hw_err[i].type == type) {
5652 dev_err(&handle->pdev->dev, "Detected %s!\n",
5653 hns3_hw_err[i].msg);
5654 break;
5655 }
5656 }
5657}
5658
1db9b1bf 5659static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 5660 .init_instance = hns3_client_init,
5661 .uninit_instance = hns3_client_uninit,
5662 .link_status_change = hns3_link_status_change,
bb6b94a8 5663 .reset_notify = hns3_reset_notify,
a83d2961 5664 .process_hw_error = hns3_process_hw_error,
76ad4f0e
S		 5665};
5666
5667/* hns3_init_module - Driver registration routine
5668 * hns3_init_module is the first routine called when the driver is
5669 * loaded. All it does is register with the PCI subsystem.
5670 */
5671static int __init hns3_init_module(void)
5672{
5673 int ret;
5674
5675 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5676 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5677
5678 client.type = HNAE3_CLIENT_KNIC;
cdc37385 5679 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
76ad4f0e
S		 5680 hns3_driver_name);
5681
5682 client.ops = &client_ops;
5683
13562d1f
XW		 5684 INIT_LIST_HEAD(&client.node);
5685
b2292360 5686 hns3_dbg_register_debugfs(hns3_driver_name);
5687
76ad4f0e
S		 5688 ret = hnae3_register_client(&client);
5689 if (ret)
b2292360 5690 goto err_reg_client;
76ad4f0e
S		 5691
5692 ret = pci_register_driver(&hns3_driver);
5693 if (ret)
b2292360 5694 goto err_reg_driver;
76ad4f0e
S		 5695
5696 return ret;
b2292360 5697
5698err_reg_driver:
5699 hnae3_unregister_client(&client);
5700err_reg_client:
5701 hns3_dbg_unregister_debugfs();
5702 return ret;
76ad4f0e
S		 5703}
5704module_init(hns3_init_module);
5705
5706/* hns3_exit_module - Driver exit cleanup routine
5707 * hns3_exit_module is called just before the driver is removed
5708 * from memory.
5709 */
5710static void __exit hns3_exit_module(void)
5711{
5712 pci_unregister_driver(&hns3_driver);
5713 hnae3_unregister_client(&client);
b2292360 5714 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 5715}
5716module_exit(hns3_exit_module);
5717
5718MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
5719MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5720MODULE_LICENSE("GPL");
5721MODULE_ALIAS("pci:hns-nic");
Linux 6.x block layer and io_uring tree(s)