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net: introduce common dev_page_is_reusable()
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e 10#include <linux/if_vlan.h>
e99a308d 11#include <linux/irq.h>
76ad4f0e
S		 12#include <linux/ip.h>
13#include <linux/ipv6.h>
14#include <linux/module.h>
15#include <linux/pci.h>
6ae4e733 16#include <linux/aer.h>
76ad4f0e
S		 17#include <linux/skbuff.h>
18#include <linux/sctp.h>
76ad4f0e 19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
76ad4f0e 23#include <net/vxlan.h>
a156998f 24#include <net/geneve.h>
76ad4f0e
S		 25
26#include "hnae3.h"
27#include "hns3_enet.h"
698a8954
YL		 28/* All hns3 tracepoints are defined by the include below, which
29 * must be included exactly once across the whole kernel with
30 * CREATE_TRACE_POINTS defined
31 */
32#define CREATE_TRACE_POINTS
33#include "hns3_trace.h"
76ad4f0e 34
cde4ffad 35#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 36#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 37
b20d7fe5
YL		 38#define hns3_rl_err(fmt, ...) \
39 do { \
40 if (net_ratelimit()) \
41 netdev_err(fmt, ##__VA_ARGS__); \
42 } while (0)
43
f96315f2 44static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
7b763f3f 45
1db9b1bf 46static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 47static const char hns3_driver_string[] =
48 "Hisilicon Ethernet Network Driver for Hip08 Family";
49static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
50static struct hnae3_client client;
51
bb87be87
YL		 52static int debug = -1;
53module_param(debug, int, 0);
54MODULE_PARM_DESC(debug, " Network interface message level setting");
55
56#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
58
eb977d99
YL		 59#define HNS3_INNER_VLAN_TAG 1
60#define HNS3_OUTER_VLAN_TAG 2
61
36c67349
YL		 62#define HNS3_MIN_TX_LEN 33U
63
76ad4f0e
S		 64/* hns3_pci_tbl - PCI Device ID Table
65 *
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
71static const struct pci_device_id hns3_pci_tbl[] = {
72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
ae6f010c
GH		 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
85 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
c155e22b
GH		 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
07acf909 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 89 /* required last entry */
90 {0, }
91};
92MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
93
ef0c5009 94static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 95{
ef0c5009 96 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 97
fb00331b 98 napi_schedule_irqoff(&tqp_vector->napi);
76ad4f0e
S		 99
100 return IRQ_HANDLED;
101}
102
103static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
104{
105 struct hns3_enet_tqp_vector *tqp_vectors;
106 unsigned int i;
107
108 for (i = 0; i < priv->vector_num; i++) {
109 tqp_vectors = &priv->tqp_vector[i];
110
111 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
112 continue;
113
ffab9691 114 /* clear the affinity mask */
874bff0b
PL		 115 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
116
76ad4f0e
S		 117 /* release the irq resource */
118 free_irq(tqp_vectors->vector_irq, tqp_vectors);
119 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
120 }
121}
122
123static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
124{
125 struct hns3_enet_tqp_vector *tqp_vectors;
126 int txrx_int_idx = 0;
127 int rx_int_idx = 0;
128 int tx_int_idx = 0;
129 unsigned int i;
130 int ret;
131
132 for (i = 0; i < priv->vector_num; i++) {
133 tqp_vectors = &priv->tqp_vector[i];
134
135 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
136 continue;
137
138 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
5bffde62
YL		 139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
140 "%s-%s-%s-%d", hns3_driver_name,
141 pci_name(priv->ae_handle->pdev),
142 "TxRx", txrx_int_idx++);
76ad4f0e
S		 143 txrx_int_idx++;
144 } else if (tqp_vectors->rx_group.ring) {
5bffde62
YL		 145 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
146 "%s-%s-%s-%d", hns3_driver_name,
147 pci_name(priv->ae_handle->pdev),
148 "Rx", rx_int_idx++);
76ad4f0e 149 } else if (tqp_vectors->tx_group.ring) {
5bffde62
YL		 150 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
151 "%s-%s-%s-%d", hns3_driver_name,
152 pci_name(priv->ae_handle->pdev),
153 "Tx", tx_int_idx++);
76ad4f0e
S		 154 } else {
155 /* Skip this unused q_vector */
156 continue;
157 }
158
159 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
160
e99a308d 161 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
76ad4f0e 162 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 163 tqp_vectors->name, tqp_vectors);
76ad4f0e
S		 164 if (ret) {
165 netdev_err(priv->netdev, "request irq(%d) fail\n",
166 tqp_vectors->vector_irq);
d547ecdc 167 hns3_nic_uninit_irq(priv);
76ad4f0e
S		 168 return ret;
169 }
170
874bff0b
PL		 171 irq_set_affinity_hint(tqp_vectors->vector_irq,
172 &tqp_vectors->affinity_mask);
173
76ad4f0e
S		 174 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
175 }
176
177 return 0;
178}
179
180static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
181 u32 mask_en)
182{
183 writel(mask_en, tqp_vector->mask_addr);
184}
185
186static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
187{
188 napi_enable(&tqp_vector->napi);
08a10068 189 enable_irq(tqp_vector->vector_irq);
76ad4f0e
S		 190
191 /* enable vector */
192 hns3_mask_vector_irq(tqp_vector, 1);
193}
194
195static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
196{
197 /* disable vector */
198 hns3_mask_vector_irq(tqp_vector, 0);
199
200 disable_irq(tqp_vector->vector_irq);
201 napi_disable(&tqp_vector->napi);
202}
203
434776a5
FL		 204void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
205 u32 rl_value)
76ad4f0e 206{
434776a5
FL		 207 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
208
76ad4f0e
S		 209 /* this defines the configuration for RL (Interrupt Rate Limiter).
210 * Rl defines rate of interrupts i.e. number of interrupts-per-second
211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
212 */
434776a5 213
de25bcc4
HT		 214 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
215 !tqp_vector->rx_group.coal.adapt_enable)
434776a5
FL		 216 /* According to the hardware, the range of rl_reg is
217 * 0-59 and the unit is 4.
218 */
219 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
220
221 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
222}
223
224void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
225 u32 gl_value)
226{
5ac84b02 227 u32 new_val;
434776a5 228
5ac84b02
HT		 229 if (tqp_vector->rx_group.coal.unit_1us)
230 new_val = gl_value | HNS3_INT_GL_1US;
231 else
232 new_val = hns3_gl_usec_to_reg(gl_value);
233
234 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
434776a5
FL		 235}
236
237void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
238 u32 gl_value)
239{
5ac84b02
HT		 240 u32 new_val;
241
242 if (tqp_vector->tx_group.coal.unit_1us)
243 new_val = gl_value | HNS3_INT_GL_1US;
244 else
245 new_val = hns3_gl_usec_to_reg(gl_value);
434776a5 246
5ac84b02 247 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 248}
249
91bfae25
HT		 250void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
251 u32 ql_value)
76ad4f0e 252{
91bfae25
HT		 253 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
254}
255
256void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
257 u32 ql_value)
258{
259 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
260}
261
262static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
263 struct hns3_nic_priv *priv)
264{
265 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
266 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
267 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
268
76ad4f0e
S		 269 /* initialize the configuration for interrupt coalescing.
270 * 1. GL (Interrupt Gap Limiter)
271 * 2. RL (Interrupt Rate Limiter)
91bfae25 272 * 3. QL (Interrupt Quantity Limiter)
46ee7350
GL		 273 *
274 * Default: enable interrupt coalescing self-adaptive and GL
76ad4f0e 275 */
de25bcc4
HT		 276 tx_coal->adapt_enable = 1;
277 rx_coal->adapt_enable = 1;
91bfae25
HT		 278
279 tx_coal->int_gl = HNS3_INT_GL_50K;
280 rx_coal->int_gl = HNS3_INT_GL_50K;
5fd4789a 281
91bfae25
HT		 282 rx_coal->flow_level = HNS3_FLOW_LOW;
283 tx_coal->flow_level = HNS3_FLOW_LOW;
5fd4789a 284
5ac84b02
HT		 285 /* device version above V3(include V3), GL can configure 1us
286 * unit, so uses 1us unit.
287 */
288 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
289 tx_coal->unit_1us = 1;
290 rx_coal->unit_1us = 1;
291 }
292
91bfae25
HT		 293 if (ae_dev->dev_specs.int_ql_max) {
294 tx_coal->ql_enable = 1;
295 rx_coal->ql_enable = 1;
296 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
297 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
298 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
299 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
300 }
76ad4f0e
S		 301}
302
91bfae25
HT		 303static void
304hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
305 struct hns3_nic_priv *priv)
dd38c726 306{
91bfae25
HT		 307 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
308 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
dd38c726
YL		 309 struct hnae3_handle *h = priv->ae_handle;
310
91bfae25
HT		 311 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
312 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
dd38c726 313 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
91bfae25
HT		 314
315 if (tx_coal->ql_enable)
316 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
317
318 if (rx_coal->ql_enable)
319 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
dd38c726
YL		 320}
321
9df8f79a
YL		 322static int hns3_nic_set_real_num_queue(struct net_device *netdev)
323{
9780cb97 324 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a 325 struct hnae3_knic_private_info *kinfo = &h->kinfo;
35244430 326 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5a5c9091 327 unsigned int queue_size = kinfo->num_tqps;
a75a8efa
YL		 328 int i, ret;
329
5a5c9091 330 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
a75a8efa
YL		 331 netdev_reset_tc(netdev);
332 } else {
35244430 333 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
a75a8efa
YL		 334 if (ret) {
335 netdev_err(netdev,
336 "netdev_set_num_tc fail, ret=%d!\n", ret);
337 return ret;
338 }
339
340 for (i = 0; i < HNAE3_MAX_TC; i++) {
35244430 341 if (!test_bit(i, &tc_info->tc_en))
a75a8efa
YL		 342 continue;
343
35244430
JS		 344 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
345 tc_info->tqp_offset[i]);
a75a8efa
YL		 346 }
347 }
9df8f79a
YL		 348
349 ret = netif_set_real_num_tx_queues(netdev, queue_size);
350 if (ret) {
351 netdev_err(netdev,
9b2f3477 352 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL		 353 return ret;
354 }
355
356 ret = netif_set_real_num_rx_queues(netdev, queue_size);
357 if (ret) {
358 netdev_err(netdev,
359 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
360 return ret;
361 }
362
363 return 0;
364}
365
678335a1
PL		 366static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
367{
0d43bf45 368 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 369
0d43bf45 370 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
35244430 371 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
678335a1 372
0d43bf45 373 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 374}
375
8df0fa91
HT		 376static void hns3_tqp_enable(struct hnae3_queue *tqp)
377{
378 u32 rcb_reg;
379
380 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
381 rcb_reg |= BIT(HNS3_RING_EN_B);
382 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
383}
384
385static void hns3_tqp_disable(struct hnae3_queue *tqp)
386{
387 u32 rcb_reg;
388
389 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
390 rcb_reg &= ~BIT(HNS3_RING_EN_B);
391 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
392}
393
ffab9691
JS		 394static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
395{
396#ifdef CONFIG_RFS_ACCEL
397 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
398 netdev->rx_cpu_rmap = NULL;
399#endif
400}
401
402static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
403{
404#ifdef CONFIG_RFS_ACCEL
405 struct hns3_nic_priv *priv = netdev_priv(netdev);
406 struct hns3_enet_tqp_vector *tqp_vector;
407 int i, ret;
408
409 if (!netdev->rx_cpu_rmap) {
410 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
411 if (!netdev->rx_cpu_rmap)
412 return -ENOMEM;
413 }
414
415 for (i = 0; i < priv->vector_num; i++) {
416 tqp_vector = &priv->tqp_vector[i];
417 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
418 tqp_vector->vector_irq);
419 if (ret) {
420 hns3_free_rx_cpu_rmap(netdev);
421 return ret;
422 }
423 }
424#endif
425 return 0;
426}
427
76ad4f0e
S		 428static int hns3_nic_net_up(struct net_device *netdev)
429{
430 struct hns3_nic_priv *priv = netdev_priv(netdev);
431 struct hnae3_handle *h = priv->ae_handle;
432 int i, j;
433 int ret;
434
7b763f3f
FL		 435 ret = hns3_nic_reset_all_ring(h);
436 if (ret)
437 return ret;
438
b7b585c2
JS		 439 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
440
76ad4f0e
S		 441 /* enable the vectors */
442 for (i = 0; i < priv->vector_num; i++)
443 hns3_vector_enable(&priv->tqp_vector[i]);
444
8df0fa91
HT		 445 /* enable rcb */
446 for (j = 0; j < h->kinfo.num_tqps; j++)
447 hns3_tqp_enable(h->kinfo.tqp[j]);
448
76ad4f0e
S		 449 /* start the ae_dev */
450 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
08a10068
YL		 451 if (ret) {
452 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
453 while (j--)
454 hns3_tqp_disable(h->kinfo.tqp[j]);
8df0fa91 455
08a10068
YL		 456 for (j = i - 1; j >= 0; j--)
457 hns3_vector_disable(&priv->tqp_vector[j]);
458 }
76ad4f0e 459
76ad4f0e
S		 460 return ret;
461}
462
2a73ac3e
YL		 463static void hns3_config_xps(struct hns3_nic_priv *priv)
464{
465 int i;
466
467 for (i = 0; i < priv->vector_num; i++) {
468 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
469 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
470
471 while (ring) {
472 int ret;
473
474 ret = netif_set_xps_queue(priv->netdev,
475 &tqp_vector->affinity_mask,
476 ring->tqp->tqp_index);
477 if (ret)
478 netdev_warn(priv->netdev,
479 "set xps queue failed: %d", ret);
480
481 ring = ring->next;
482 }
483 }
484}
485
76ad4f0e
S		 486static int hns3_nic_net_open(struct net_device *netdev)
487{
8cdb992f 488 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 489 struct hnae3_handle *h = hns3_get_handle(netdev);
490 struct hnae3_knic_private_info *kinfo;
491 int i, ret;
76ad4f0e 492
257e4f29
HT		 493 if (hns3_nic_resetting(netdev))
494 return -EBUSY;
495
76ad4f0e
S		 496 netif_carrier_off(netdev);
497
9df8f79a
YL		 498 ret = hns3_nic_set_real_num_queue(netdev);
499 if (ret)
76ad4f0e 500 return ret;
76ad4f0e
S		 501
502 ret = hns3_nic_net_up(netdev);
503 if (ret) {
9b2f3477 504 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S		 505 return ret;
506 }
507
a75a8efa 508 kinfo = &h->kinfo;
9b2f3477 509 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
35244430 510 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
a75a8efa 511
8cdb992f
JS		 512 if (h->ae_algo->ops->set_timer_task)
513 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
514
2a73ac3e 515 hns3_config_xps(priv);
1c822948
YL		 516
517 netif_dbg(h, drv, netdev, "net open\n");
518
76ad4f0e
S		 519 return 0;
520}
521
f96315f2
HT		 522static void hns3_reset_tx_queue(struct hnae3_handle *h)
523{
524 struct net_device *ndev = h->kinfo.netdev;
525 struct hns3_nic_priv *priv = netdev_priv(ndev);
526 struct netdev_queue *dev_queue;
527 u32 i;
528
529 for (i = 0; i < h->kinfo.num_tqps; i++) {
530 dev_queue = netdev_get_tx_queue(ndev,
5f06b903 531 priv->ring[i].queue_index);
f96315f2
HT		 532 netdev_tx_reset_queue(dev_queue);
533 }
534}
535
76ad4f0e
S		 536static void hns3_nic_net_down(struct net_device *netdev)
537{
538 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 539 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 540 const struct hnae3_ae_ops *ops;
541 int i;
542
7b763f3f
FL		 543 /* disable vectors */
544 for (i = 0; i < priv->vector_num; i++)
545 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 546
547 /* disable rcb */
548 for (i = 0; i < h->kinfo.num_tqps; i++)
549 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 550
76ad4f0e
S		 551 /* stop ae_dev */
552 ops = priv->ae_handle->ae_algo->ops;
553 if (ops->stop)
554 ops->stop(priv->ae_handle);
555
3a30964a
YL		 556 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
557 * during reset process, because driver may not be able
558 * to disable the ring through firmware when downing the netdev.
559 */
560 if (!hns3_nic_resetting(netdev))
f96315f2
HT		 561 hns3_clear_all_ring(priv->ae_handle, false);
562
563 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S		 564}
565
566static int hns3_nic_net_stop(struct net_device *netdev)
567{
ff0699e0 568 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 569 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 570
571 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
572 return 0;
573
1c822948
YL		 574 netif_dbg(h, drv, netdev, "net stop\n");
575
8cdb992f
JS		 576 if (h->ae_algo->ops->set_timer_task)
577 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
578
76ad4f0e
S		 579 netif_tx_stop_all_queues(netdev);
580 netif_carrier_off(netdev);
581
582 hns3_nic_net_down(netdev);
583
584 return 0;
585}
586
76ad4f0e
S		 587static int hns3_nic_uc_sync(struct net_device *netdev,
588 const unsigned char *addr)
589{
9780cb97 590 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 591
592 if (h->ae_algo->ops->add_uc_addr)
593 return h->ae_algo->ops->add_uc_addr(h, addr);
594
595 return 0;
596}
597
598static int hns3_nic_uc_unsync(struct net_device *netdev,
599 const unsigned char *addr)
600{
9780cb97 601 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 602
ee4bcd3b
JS		 603 /* need ignore the request of removing device address, because
604 * we store the device address and other addresses of uc list
605 * in the function's mac filter list.
606 */
607 if (ether_addr_equal(addr, netdev->dev_addr))
608 return 0;
609
76ad4f0e
S		 610 if (h->ae_algo->ops->rm_uc_addr)
611 return h->ae_algo->ops->rm_uc_addr(h, addr);
612
613 return 0;
614}
615
616static int hns3_nic_mc_sync(struct net_device *netdev,
617 const unsigned char *addr)
618{
9780cb97 619 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 620
720a8478 621 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 622 return h->ae_algo->ops->add_mc_addr(h, addr);
623
624 return 0;
625}
626
627static int hns3_nic_mc_unsync(struct net_device *netdev,
628 const unsigned char *addr)
629{
9780cb97 630 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 631
720a8478 632 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 633 return h->ae_algo->ops->rm_mc_addr(h, addr);
634
635 return 0;
636}
637
c60edc17
JS		 638static u8 hns3_get_netdev_flags(struct net_device *netdev)
639{
640 u8 flags = 0;
641
642 if (netdev->flags & IFF_PROMISC) {
28673b33 643 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS		 644 } else {
645 flags |= HNAE3_VLAN_FLTR;
646 if (netdev->flags & IFF_ALLMULTI)
647 flags |= HNAE3_USER_MPE;
648 }
649
650 return flags;
651}
652
1db9b1bf 653static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 654{
9780cb97 655 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17 656 u8 new_flags;
76ad4f0e 657
c60edc17
JS		 658 new_flags = hns3_get_netdev_flags(netdev);
659
c631c696
JS		 660 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
661 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
c60edc17 662
c60edc17 663 /* User mode Promisc mode enable and vlan filtering is disabled to
c631c696 664 * let all packets in.
c60edc17 665 */
c60edc17 666 h->netdev_flags = new_flags;
c631c696
JS		 667 hns3_request_update_promisc_mode(h);
668}
669
670void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
671{
672 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
673
674 if (ops->request_update_promisc_mode)
675 ops->request_update_promisc_mode(handle);
c60edc17
JS		 676}
677
c60edc17
JS		 678void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
679{
680 struct hns3_nic_priv *priv = netdev_priv(netdev);
681 struct hnae3_handle *h = priv->ae_handle;
295ba232 682 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
c60edc17
JS		 683 bool last_state;
684
295ba232
GH		 685 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 &&
686 h->ae_algo->ops->enable_vlan_filter) {
c60edc17
JS		 687 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
688 if (enable != last_state) {
689 netdev_info(netdev,
690 "%s vlan filter\n",
691 enable ? "enable" : "disable");
692 h->ae_algo->ops->enable_vlan_filter(h, enable);
693 }
40cca1c5 694 }
76ad4f0e
S		 695}
696
3e281621 697static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
76ad4f0e
S		 698 u16 *mss, u32 *type_cs_vlan_tso)
699{
700 u32 l4_offset, hdr_len;
701 union l3_hdr_info l3;
702 union l4_hdr_info l4;
703 u32 l4_paylen;
704 int ret;
705
706 if (!skb_is_gso(skb))
707 return 0;
708
709 ret = skb_cow_head(skb, 0);
8ae10cfb 710 if (unlikely(ret < 0))
76ad4f0e
S		 711 return ret;
712
713 l3.hdr = skb_network_header(skb);
714 l4.hdr = skb_transport_header(skb);
715
716 /* Software should clear the IPv4's checksum field when tso is
717 * needed.
718 */
719 if (l3.v4->version == 4)
720 l3.v4->check = 0;
721
9b2f3477 722 /* tunnel packet */
76ad4f0e
S		 723 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
724 SKB_GSO_GRE_CSUM |
3e281621
HT		 725 SKB_GSO_UDP_TUNNEL |
726 SKB_GSO_UDP_TUNNEL_CSUM)) {
76ad4f0e
S		 727 /* reset l3&l4 pointers from outer to inner headers */
728 l3.hdr = skb_inner_network_header(skb);
729 l4.hdr = skb_inner_transport_header(skb);
730
731 /* Software should clear the IPv4's checksum field when
732 * tso is needed.
733 */
734 if (l3.v4->version == 4)
735 l3.v4->check = 0;
736 }
737
9b2f3477 738 /* normal or tunnel packet */
76ad4f0e 739 l4_offset = l4.hdr - skb->data;
76ad4f0e 740
9b2f3477 741 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e 742 l4_paylen = skb->len - l4_offset;
0692cfe9
HT		 743
744 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
745 hdr_len = sizeof(*l4.udp) + l4_offset;
746 csum_replace_by_diff(&l4.udp->check,
747 (__force __wsum)htonl(l4_paylen));
748 } else {
749 hdr_len = (l4.tcp->doff << 2) + l4_offset;
750 csum_replace_by_diff(&l4.tcp->check,
751 (__force __wsum)htonl(l4_paylen));
752 }
76ad4f0e
S		 753
754 /* find the txbd field values */
3e281621 755 *paylen_fdop_ol4cs = skb->len - hdr_len;
cde4ffad 756 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e 757
3e281621
HT		 758 /* offload outer UDP header checksum */
759 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
760 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
761
76ad4f0e
S		 762 /* get MSS for TSO */
763 *mss = skb_shinfo(skb)->gso_size;
764
698a8954
YL		 765 trace_hns3_tso(skb);
766
76ad4f0e
S		 767 return 0;
768}
769
1898d4e4
S		 770static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
771 u8 *il4_proto)
76ad4f0e 772{
1a6e552d 773 union l3_hdr_info l3;
76ad4f0e
S		 774 unsigned char *l4_hdr;
775 unsigned char *exthdr;
776 u8 l4_proto_tmp;
777 __be16 frag_off;
778
779 /* find outer header point */
780 l3.hdr = skb_network_header(skb);
35f58fd7 781 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 782
783 if (skb->protocol == htons(ETH_P_IPV6)) {
784 exthdr = l3.hdr + sizeof(*l3.v6);
785 l4_proto_tmp = l3.v6->nexthdr;
786 if (l4_hdr != exthdr)
787 ipv6_skip_exthdr(skb, exthdr - skb->data,
788 &l4_proto_tmp, &frag_off);
789 } else if (skb->protocol == htons(ETH_P_IP)) {
790 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 791 } else {
792 return -EINVAL;
76ad4f0e
S		 793 }
794
795 *ol4_proto = l4_proto_tmp;
796
797 /* tunnel packet */
798 if (!skb->encapsulation) {
799 *il4_proto = 0;
1898d4e4 800 return 0;
76ad4f0e
S		 801 }
802
803 /* find inner header point */
804 l3.hdr = skb_inner_network_header(skb);
805 l4_hdr = skb_inner_transport_header(skb);
806
807 if (l3.v6->version == 6) {
808 exthdr = l3.hdr + sizeof(*l3.v6);
809 l4_proto_tmp = l3.v6->nexthdr;
810 if (l4_hdr != exthdr)
811 ipv6_skip_exthdr(skb, exthdr - skb->data,
812 &l4_proto_tmp, &frag_off);
813 } else if (l3.v4->version == 4) {
814 l4_proto_tmp = l3.v4->protocol;
815 }
816
817 *il4_proto = l4_proto_tmp;
1898d4e4
S		 818
819 return 0;
76ad4f0e
S		 820}
821
3db084d2
YL		 822/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
823 * and it is udp packet, which has a dest port as the IANA assigned.
824 * the hardware is expected to do the checksum offload, but the
825 * hardware will not do the checksum offload when udp dest port is
a156998f 826 * 4789 or 6081.
3db084d2
YL		 827 */
828static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
829{
ade36cce
HT		 830 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
831 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1a6e552d 832 union l4_hdr_info l4;
3db084d2 833
ade36cce
HT		 834 /* device version above V3(include V3), the hardware can
835 * do this checksum offload.
836 */
837 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
838 return false;
839
3db084d2
YL		 840 l4.hdr = skb_transport_header(skb);
841
bea96410 842 if (!(!skb->encapsulation &&
a156998f
YL		 843 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
844 l4.udp->dest == htons(GENEVE_UDP_PORT))))
3db084d2
YL		 845 return false;
846
847 skb_checksum_help(skb);
848
849 return true;
850}
851
757cd1e4
YL		 852static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
853 u32 *ol_type_vlan_len_msec)
76ad4f0e 854{
757cd1e4
YL		 855 u32 l2_len, l3_len, l4_len;
856 unsigned char *il2_hdr;
1a6e552d 857 union l3_hdr_info l3;
757cd1e4 858 union l4_hdr_info l4;
76ad4f0e
S		 859
860 l3.hdr = skb_network_header(skb);
757cd1e4 861 l4.hdr = skb_transport_header(skb);
76ad4f0e 862
757cd1e4
YL		 863 /* compute OL2 header size, defined in 2 Bytes */
864 l2_len = l3.hdr - skb->data;
865 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
866
867 /* compute OL3 header size, defined in 4 Bytes */
868 l3_len = l4.hdr - l3.hdr;
869 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 870
757cd1e4 871 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 872 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL		 873 l4_len = il2_hdr - l4.hdr;
874 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
875
876 /* define outer network header type */
877 if (skb->protocol == htons(ETH_P_IP)) {
878 if (skb_is_gso(skb))
cde4ffad 879 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 880 HNS3_TXD_OL3T_S,
881 HNS3_OL3T_IPV4_CSUM);
882 else
cde4ffad 883 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 884 HNS3_TXD_OL3T_S,
885 HNS3_OL3T_IPV4_NO_CSUM);
886
887 } else if (skb->protocol == htons(ETH_P_IPV6)) {
888 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
889 HNS3_OL3T_IPV6);
890 }
891
892 if (ol4_proto == IPPROTO_UDP)
893 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
894 HNS3_TUN_MAC_IN_UDP);
895 else if (ol4_proto == IPPROTO_GRE)
896 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
897 HNS3_TUN_NVGRE);
898}
899
900static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
901 u8 il4_proto, u32 *type_cs_vlan_tso,
902 u32 *ol_type_vlan_len_msec)
903{
c264ed44 904 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 905 u32 l4_proto = ol4_proto;
906 union l4_hdr_info l4;
907 union l3_hdr_info l3;
908 u32 l2_len, l3_len;
909
910 l4.hdr = skb_transport_header(skb);
911 l3.hdr = skb_network_header(skb);
912
913 /* handle encapsulation skb */
914 if (skb->encapsulation) {
915 /* If this is a not UDP/GRE encapsulation skb */
916 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 917 /* drop the skb tunnel packet if hardware don't support,
918 * because hardware can't calculate csum when TSO.
919 */
920 if (skb_is_gso(skb))
921 return -EDOM;
922
923 /* the stack computes the IP header already,
924 * driver calculate l4 checksum when not TSO.
925 */
926 skb_checksum_help(skb);
927 return 0;
928 }
929
757cd1e4
YL		 930 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
931
932 /* switch to inner header */
933 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 934 l3.hdr = skb_inner_network_header(skb);
757cd1e4 935 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 936 l4_proto = il4_proto;
937 }
938
939 if (l3.v4->version == 4) {
cde4ffad
YL		 940 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
941 HNS3_L3T_IPV4);
76ad4f0e
S		 942
943 /* the stack computes the IP header already, the only time we
944 * need the hardware to recompute it is in the case of TSO.
945 */
946 if (skb_is_gso(skb))
cde4ffad 947 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 948 } else if (l3.v6->version == 6) {
cde4ffad
YL		 949 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
950 HNS3_L3T_IPV6);
76ad4f0e
S		 951 }
952
757cd1e4
YL		 953 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
954 l2_len = l3.hdr - l2_hdr;
955 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
956
957 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
958 l3_len = l4.hdr - l3.hdr;
959 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
960
961 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 962 switch (l4_proto) {
963 case IPPROTO_TCP:
cde4ffad
YL		 964 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
965 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
966 HNS3_L4T_TCP);
757cd1e4
YL		 967 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
968 l4.tcp->doff);
76ad4f0e
S		 969 break;
970 case IPPROTO_UDP:
3db084d2
YL		 971 if (hns3_tunnel_csum_bug(skb))
972 break;
973
cde4ffad
YL		 974 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
975 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
976 HNS3_L4T_UDP);
757cd1e4
YL		 977 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
978 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 979 break;
980 case IPPROTO_SCTP:
cde4ffad
YL		 981 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
982 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
983 HNS3_L4T_SCTP);
757cd1e4
YL		 984 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
985 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 986 break;
987 default:
988 /* drop the skb tunnel packet if hardware don't support,
989 * because hardware can't calculate csum when TSO.
990 */
991 if (skb_is_gso(skb))
992 return -EDOM;
993
994 /* the stack computes the IP header already,
995 * driver calculate l4 checksum when not TSO.
996 */
997 skb_checksum_help(skb);
998 return 0;
999 }
1000
1001 return 0;
1002}
1003
eb977d99
YL		 1004static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1005 struct sk_buff *skb)
9699cffe 1006{
44e626f7 1007 struct hnae3_handle *handle = tx_ring->tqp->handle;
592b0179 1008 struct hnae3_ae_dev *ae_dev;
eb977d99
YL		 1009 struct vlan_ethhdr *vhdr;
1010 int rc;
1011
1012 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1013 skb_vlan_tag_present(skb)))
1014 return 0;
44e626f7 1015
592b0179
GL		 1016 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1017 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1018 * will cause RAS error.
44e626f7 1019 */
592b0179 1020 ae_dev = pci_get_drvdata(handle->pdev);
44e626f7 1021 if (unlikely(skb_vlan_tagged_multi(skb) &&
592b0179 1022 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
44e626f7
JS		 1023 handle->port_base_vlan_state ==
1024 HNAE3_PORT_BASE_VLAN_ENABLE))
1025 return -EINVAL;
1026
9699cffe 1027 if (skb->protocol == htons(ETH_P_8021Q) &&
eb977d99 1028 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
9699cffe
PL		 1029 /* When HW VLAN acceleration is turned off, and the stack
1030 * sets the protocol to 802.1q, the driver just need to
1031 * set the protocol to the encapsulated ethertype.
1032 */
1033 skb->protocol = vlan_get_protocol(skb);
1034 return 0;
1035 }
1036
1037 if (skb_vlan_tag_present(skb)) {
9699cffe
PL		 1038 /* Based on hw strategy, use out_vtag in two layer tag case,
1039 * and use inner_vtag in one tag case.
1040 */
eb977d99
YL		 1041 if (skb->protocol == htons(ETH_P_8021Q) &&
1042 handle->port_base_vlan_state ==
1043 HNAE3_PORT_BASE_VLAN_DISABLE)
1044 rc = HNS3_OUTER_VLAN_TAG;
1045 else
1046 rc = HNS3_INNER_VLAN_TAG;
1047
1048 skb->protocol = vlan_get_protocol(skb);
1049 return rc;
9699cffe
PL		 1050 }
1051
eb977d99
YL		 1052 rc = skb_cow_head(skb, 0);
1053 if (unlikely(rc < 0))
1054 return rc;
1055
1056 vhdr = (struct vlan_ethhdr *)skb->data;
1057 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1058 & VLAN_PRIO_MASK);
1059
9699cffe
PL		 1060 skb->protocol = vlan_get_protocol(skb);
1061 return 0;
1062}
1063
66d52f3b
HT		 1064/* check if the hardware is capable of checksum offloading */
1065static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1066{
1067 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1068
1069 /* Kindly note, due to backward compatibility of the TX descriptor,
1070 * HW checksum of the non-IP packets and GSO packets is handled at
1071 * different place in the following code
1072 */
b9046e88 1073 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
66d52f3b
HT		 1074 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1075 return false;
1076
1077 return true;
1078}
1079
eb977d99
YL		 1080static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1081 struct sk_buff *skb, struct hns3_desc *desc)
1082{
1083 u32 ol_type_vlan_len_msec = 0;
3e281621 1084 u32 paylen_ol4cs = skb->len;
eb977d99 1085 u32 type_cs_vlan_tso = 0;
66d52f3b 1086 u16 mss_hw_csum = 0;
eb977d99
YL		 1087 u16 inner_vtag = 0;
1088 u16 out_vtag = 0;
eb977d99
YL		 1089 int ret;
1090
1091 ret = hns3_handle_vtags(ring, skb);
1092 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1093 u64_stats_update_begin(&ring->syncp);
1094 ring->stats.tx_vlan_err++;
1095 u64_stats_update_end(&ring->syncp);
eb977d99
YL		 1096 return ret;
1097 } else if (ret == HNS3_INNER_VLAN_TAG) {
1098 inner_vtag = skb_vlan_tag_get(skb);
1099 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1100 VLAN_PRIO_MASK;
1101 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1102 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1103 out_vtag = skb_vlan_tag_get(skb);
1104 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1105 VLAN_PRIO_MASK;
1106 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1107 1);
1108 }
1109
1110 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1111 u8 ol4_proto, il4_proto;
1112
66d52f3b
HT		 1113 if (hns3_check_hw_tx_csum(skb)) {
1114 /* set checksum start and offset, defined in 2 Bytes */
1115 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1116 skb_checksum_start_offset(skb) >> 1);
1117 hns3_set_field(ol_type_vlan_len_msec,
1118 HNS3_TXD_CSUM_OFFSET_S,
1119 skb->csum_offset >> 1);
1120 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1121 goto out_hw_tx_csum;
1122 }
1123
eb977d99
YL		 1124 skb_reset_mac_len(skb);
1125
1126 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
8ae10cfb 1127 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1128 u64_stats_update_begin(&ring->syncp);
1129 ring->stats.tx_l4_proto_err++;
1130 u64_stats_update_end(&ring->syncp);
eb977d99 1131 return ret;
b20d7fe5 1132 }
eb977d99
YL		 1133
1134 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1135 &type_cs_vlan_tso,
1136 &ol_type_vlan_len_msec);
8ae10cfb 1137 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1138 u64_stats_update_begin(&ring->syncp);
1139 ring->stats.tx_l2l3l4_err++;
1140 u64_stats_update_end(&ring->syncp);
eb977d99 1141 return ret;
b20d7fe5 1142 }
eb977d99 1143
3e281621 1144 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum,
eb977d99 1145 &type_cs_vlan_tso);
8ae10cfb 1146 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1147 u64_stats_update_begin(&ring->syncp);
1148 ring->stats.tx_tso_err++;
1149 u64_stats_update_end(&ring->syncp);
eb977d99 1150 return ret;
b20d7fe5 1151 }
eb977d99
YL		 1152 }
1153
66d52f3b 1154out_hw_tx_csum:
eb977d99
YL		 1155 /* Set txbd */
1156 desc->tx.ol_type_vlan_len_msec =
1157 cpu_to_le32(ol_type_vlan_len_msec);
1158 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
3e281621 1159 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs);
66d52f3b 1160 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum);
eb977d99
YL		 1161 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1162 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1163
1164 return 0;
1165}
1166
76ad4f0e 1167static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
8ae10cfb 1168 unsigned int size, enum hns_desc_type type)
76ad4f0e 1169{
8ae10cfb
YL		 1170#define HNS3_LIKELY_BD_NUM 1
1171
76ad4f0e
S		 1172 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1173 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1174 struct device *dev = ring_to_dev(ring);
d7840976 1175 skb_frag_t *frag;
1e8a7977 1176 unsigned int frag_buf_num;
47e7b13b 1177 int k, sizeoflast;
5188f218 1178 dma_addr_t dma;
76ad4f0e 1179
cfdaeba5
YL		 1180 if (type == DESC_TYPE_FRAGLIST_SKB ||
1181 type == DESC_TYPE_SKB) {
74ef402e
HT		 1182 struct sk_buff *skb = (struct sk_buff *)priv;
1183
5188f218
PL		 1184 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1185 } else {
d7840976 1186 frag = (skb_frag_t *)priv;
5188f218
PL		 1187 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1188 }
1189
845e0d1d 1190 if (unlikely(dma_mapping_error(dev, dma))) {
b20d7fe5 1191 u64_stats_update_begin(&ring->syncp);
5188f218 1192 ring->stats.sw_err_cnt++;
b20d7fe5 1193 u64_stats_update_end(&ring->syncp);
5188f218 1194 return -ENOMEM;
76ad4f0e
S		 1195 }
1196
0ec3b6a7 1197 desc_cb->priv = priv;
bcdb12b7 1198 desc_cb->length = size;
0ec3b6a7
YL		 1199 desc_cb->dma = dma;
1200 desc_cb->type = type;
bcdb12b7 1201
ceca4a5e 1202 if (likely(size <= HNS3_MAX_BD_SIZE)) {
ceca4a5e
YL		 1203 desc->addr = cpu_to_le64(dma);
1204 desc->tx.send_size = cpu_to_le16(size);
ceca4a5e 1205 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1206 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
ceca4a5e 1207
698a8954 1208 trace_hns3_tx_desc(ring, ring->next_to_use);
ceca4a5e 1209 ring_ptr_move_fw(ring, next_to_use);
8ae10cfb 1210 return HNS3_LIKELY_BD_NUM;
ceca4a5e
YL		 1211 }
1212
5f543a54 1213 frag_buf_num = hns3_tx_bd_count(size);
48ae74c9 1214 sizeoflast = size % HNS3_MAX_BD_SIZE;
1e8a7977
FL		 1215 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1216
1217 /* When frag size is bigger than hardware limit, split this frag */
1218 for (k = 0; k < frag_buf_num; k++) {
1e8a7977
FL		 1219 /* now, fill the descriptor */
1220 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1221 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1222 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977 1223 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1224 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1e8a7977 1225
698a8954 1226 trace_hns3_tx_desc(ring, ring->next_to_use);
9b2f3477 1227 /* move ring pointer to next */
1e8a7977
FL		 1228 ring_ptr_move_fw(ring, next_to_use);
1229
1e8a7977
FL		 1230 desc = &ring->desc[ring->next_to_use];
1231 }
76ad4f0e 1232
8ae10cfb 1233 return frag_buf_num;
76ad4f0e
S		 1234}
1235
8ae10cfb
YL		 1236static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1237 unsigned int bd_num)
76ad4f0e 1238{
8ae10cfb 1239 unsigned int size;
42611b70 1240 int i;
76ad4f0e 1241
8ae10cfb
YL		 1242 size = skb_headlen(skb);
1243 while (size > HNS3_MAX_BD_SIZE) {
1244 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1245 size -= HNS3_MAX_BD_SIZE;
1246
1247 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1248 return bd_num;
1249 }
76ad4f0e 1250
8ae10cfb
YL		 1251 if (size) {
1252 bd_size[bd_num++] = size;
1253 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1254 return bd_num;
1255 }
76ad4f0e 1256
3d5f3741 1257 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
d7840976 1258 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8ae10cfb
YL		 1259 size = skb_frag_size(frag);
1260 if (!size)
1261 continue;
1262
1263 while (size > HNS3_MAX_BD_SIZE) {
1264 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1265 size -= HNS3_MAX_BD_SIZE;
1266
1267 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1268 return bd_num;
1269 }
1270
1271 bd_size[bd_num++] = size;
1272 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1273 return bd_num;
1274 }
1275
1276 return bd_num;
1277}
1278
fd665b3d
HT		 1279static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1280 u8 max_non_tso_bd_num)
8ae10cfb
YL		 1281{
1282 struct sk_buff *frag_skb;
1283 unsigned int bd_num = 0;
1284
1285 /* If the total len is within the max bd limit */
1286 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
fd665b3d 1287 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
8ae10cfb
YL		 1288 return skb_shinfo(skb)->nr_frags + 1U;
1289
1290 /* The below case will always be linearized, return
1291 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1292 */
1293 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
fd665b3d
HT		 1294 (!skb_is_gso(skb) && skb->len >
1295 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))))
8ae10cfb
YL		 1296 return HNS3_MAX_TSO_BD_NUM + 1U;
1297
1298 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1299
1300 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1301 return bd_num;
1302
1303 skb_walk_frags(skb, frag_skb) {
1304 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1305 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1306 return bd_num;
3d5f3741 1307 }
76ad4f0e 1308
3d5f3741 1309 return bd_num;
76ad4f0e
S		 1310}
1311
db4970aa
YL		 1312static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1313{
1314 if (!skb->encapsulation)
1315 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1316
1317 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1318}
1319
fd665b3d
HT		 1320/* HW need every continuous max_non_tso_bd_num buffer data to be larger
1321 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1322 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1323 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1324 * than MSS except the last max_non_tso_bd_num - 1 frags.
db4970aa 1325 */
8ae10cfb 1326static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
fd665b3d 1327 unsigned int bd_num, u8 max_non_tso_bd_num)
db4970aa 1328{
db4970aa
YL		 1329 unsigned int tot_len = 0;
1330 int i;
1331
fd665b3d 1332 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
8ae10cfb 1333 tot_len += bd_size[i];
db4970aa 1334
fd665b3d
HT		 1335 /* ensure the first max_non_tso_bd_num frags is greater than
1336 * mss + header
1337 */
1338 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
8ae10cfb 1339 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
db4970aa
YL		 1340 return true;
1341
fd665b3d
HT		 1342 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1343 * than mss except the last one.
8ae10cfb 1344 */
fd665b3d 1345 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
8ae10cfb 1346 tot_len -= bd_size[i];
fd665b3d 1347 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
db4970aa
YL		 1348
1349 if (tot_len < skb_shinfo(skb)->gso_size)
1350 return true;
1351 }
1352
1353 return false;
1354}
1355
698a8954
YL		 1356void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1357{
9d8d5a36 1358 int i;
698a8954
YL		 1359
1360 for (i = 0; i < MAX_SKB_FRAGS; i++)
1361 size[i] = skb_frag_size(&shinfo->frags[i]);
1362}
1363
3d5f3741 1364static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
2a597eff 1365 struct net_device *netdev,
d1a37ded 1366 struct sk_buff *skb)
76ad4f0e 1367{
2a597eff 1368 struct hns3_nic_priv *priv = netdev_priv(netdev);
fd665b3d 1369 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
8ae10cfb 1370 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
42611b70 1371 unsigned int bd_num;
76ad4f0e 1372
fd665b3d
HT		 1373 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num);
1374 if (unlikely(bd_num > max_non_tso_bd_num)) {
8ae10cfb 1375 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
fd665b3d
HT		 1376 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1377 max_non_tso_bd_num)) {
6ad595bc 1378 trace_hns3_over_max_bd(skb);
db4970aa 1379 goto out;
698a8954 1380 }
db4970aa 1381
d1a37ded 1382 if (__skb_linearize(skb))
51e8439f 1383 return -ENOMEM;
3d5f3741 1384
d1a37ded
YL		 1385 bd_num = hns3_tx_bd_count(skb->len);
1386 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1387 (!skb_is_gso(skb) &&
fd665b3d 1388 bd_num > max_non_tso_bd_num)) {
6ad595bc 1389 trace_hns3_over_max_bd(skb);
42611b70 1390 return -ENOMEM;
698a8954 1391 }
42611b70 1392
3d5f3741
YL		 1393 u64_stats_update_begin(&ring->syncp);
1394 ring->stats.tx_copy++;
1395 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1396 }
1397
db4970aa 1398out:
2a597eff
YL		 1399 if (likely(ring_space(ring) >= bd_num))
1400 return bd_num;
76ad4f0e 1401
2a597eff
YL		 1402 netif_stop_subqueue(netdev, ring->queue_index);
1403 smp_mb(); /* Memory barrier before checking ring_space */
1404
1405 /* Start queue in case hns3_clean_tx_ring has just made room
1406 * available and has not seen the queue stopped state performed
1407 * by netif_stop_subqueue above.
1408 */
1409 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1410 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1411 netif_start_subqueue(netdev, ring->queue_index);
1412 return bd_num;
1413 }
1414
1415 return -EBUSY;
76ad4f0e
S		 1416}
1417
ba3f808f 1418static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1419{
1420 struct device *dev = ring_to_dev(ring);
1421 unsigned int i;
1422
1423 for (i = 0; i < ring->desc_num; i++) {
8ceca59f
YL		 1424 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1425
1426 memset(desc, 0, sizeof(*desc));
1427
76ad4f0e
S		 1428 /* check if this is where we started */
1429 if (ring->next_to_use == next_to_use_orig)
1430 break;
1431
aa9d22dd
YL		 1432 /* rollback one */
1433 ring_ptr_move_bw(ring, next_to_use);
1434
8ceca59f
YL		 1435 if (!ring->desc_cb[ring->next_to_use].dma)
1436 continue;
1437
76ad4f0e 1438 /* unmap the descriptor dma address */
74ef402e
HT		 1439 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
1440 ring->desc_cb[ring->next_to_use].type ==
1441 DESC_TYPE_FRAGLIST_SKB)
76ad4f0e
S		 1442 dma_unmap_single(dev,
1443 ring->desc_cb[ring->next_to_use].dma,
1444 ring->desc_cb[ring->next_to_use].length,
1445 DMA_TO_DEVICE);
bcdb12b7 1446 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1447 dma_unmap_page(dev,
1448 ring->desc_cb[ring->next_to_use].dma,
1449 ring->desc_cb[ring->next_to_use].length,
1450 DMA_TO_DEVICE);
1451
bcdb12b7 1452 ring->desc_cb[ring->next_to_use].length = 0;
aa9d22dd 1453 ring->desc_cb[ring->next_to_use].dma = 0;
8ceca59f 1454 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN;
76ad4f0e
S		 1455 }
1456}
1457
8ae10cfb
YL		 1458static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1459 struct sk_buff *skb, enum hns_desc_type type)
1460{
1461 unsigned int size = skb_headlen(skb);
1462 int i, ret, bd_num = 0;
1463
1464 if (size) {
1465 ret = hns3_fill_desc(ring, skb, size, type);
1466 if (unlikely(ret < 0))
1467 return ret;
1468
1469 bd_num += ret;
1470 }
1471
1472 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1473 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1474
1475 size = skb_frag_size(frag);
1476 if (!size)
1477 continue;
1478
1479 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1480 if (unlikely(ret < 0))
1481 return ret;
1482
1483 bd_num += ret;
1484 }
1485
1486 return bd_num;
1487}
1488
f6061a05
YL		 1489static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
1490 bool doorbell)
1491{
1492 ring->pending_buf += num;
1493
1494 if (!doorbell) {
1495 u64_stats_update_begin(&ring->syncp);
1496 ring->stats.tx_more++;
1497 u64_stats_update_end(&ring->syncp);
1498 return;
1499 }
1500
1501 if (!ring->pending_buf)
1502 return;
1503
48ee56fd
YL		 1504 writel(ring->pending_buf,
1505 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
f6061a05 1506 ring->pending_buf = 0;
20d06ca2 1507 WRITE_ONCE(ring->last_to_use, ring->next_to_use);
f6061a05
YL		 1508}
1509
d43e5aca 1510netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1511{
1512 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f06b903 1513 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
76ad4f0e 1514 struct netdev_queue *dev_queue;
8ae10cfb
YL		 1515 int pre_ntu, next_to_use_head;
1516 struct sk_buff *frag_skb;
1517 int bd_num = 0;
f6061a05 1518 bool doorbell;
76ad4f0e 1519 int ret;
76ad4f0e 1520
36c67349 1521 /* Hardware can only handle short frames above 32 bytes */
f6061a05
YL		 1522 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
1523 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
36c67349 1524 return NETDEV_TX_OK;
f6061a05 1525 }
36c67349 1526
76ad4f0e
S		 1527 /* Prefetch the data used later */
1528 prefetch(skb->data);
1529
d1a37ded 1530 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
8ae10cfb
YL		 1531 if (unlikely(ret <= 0)) {
1532 if (ret == -EBUSY) {
3d5f3741
YL		 1533 u64_stats_update_begin(&ring->syncp);
1534 ring->stats.tx_busy++;
1535 u64_stats_update_end(&ring->syncp);
f6061a05 1536 hns3_tx_doorbell(ring, 0, true);
2a597eff 1537 return NETDEV_TX_BUSY;
8ae10cfb 1538 } else if (ret == -ENOMEM) {
3d5f3741
YL		 1539 u64_stats_update_begin(&ring->syncp);
1540 ring->stats.sw_err_cnt++;
1541 u64_stats_update_end(&ring->syncp);
1542 }
76ad4f0e 1543
8ae10cfb 1544 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
76ad4f0e 1545 goto out_err_tx_ok;
76ad4f0e
S		 1546 }
1547
76ad4f0e
S		 1548 next_to_use_head = ring->next_to_use;
1549
cfdaeba5
YL		 1550 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use]);
1551 if (unlikely(ret < 0))
1552 goto fill_err;
1553
8ae10cfb
YL		 1554 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1555 if (unlikely(ret < 0))
aa9d22dd 1556 goto fill_err;
76ad4f0e 1557
8ae10cfb 1558 bd_num += ret;
5188f218 1559
8ae10cfb 1560 skb_walk_frags(skb, frag_skb) {
74ef402e
HT		 1561 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1562 DESC_TYPE_FRAGLIST_SKB);
8ae10cfb 1563 if (unlikely(ret < 0))
aa9d22dd 1564 goto fill_err;
8ae10cfb
YL		 1565
1566 bd_num += ret;
76ad4f0e 1567 }
5c6cfd30 1568
8ae10cfb
YL		 1569 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1570 (ring->desc_num - 1);
1571 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1572 cpu_to_le16(BIT(HNS3_TXD_FE_B));
698a8954 1573 trace_hns3_tx_desc(ring, pre_ntu);
76ad4f0e
S		 1574
1575 /* Complete translate all packets */
5f06b903 1576 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
f6061a05
YL		 1577 doorbell = __netdev_tx_sent_queue(dev_queue, skb->len,
1578 netdev_xmit_more());
1579 hns3_tx_doorbell(ring, bd_num, doorbell);
76ad4f0e
S		 1580
1581 return NETDEV_TX_OK;
1582
aa9d22dd 1583fill_err:
ba3f808f 1584 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1585
1586out_err_tx_ok:
1587 dev_kfree_skb_any(skb);
f6061a05 1588 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
76ad4f0e 1589 return NETDEV_TX_OK;
76ad4f0e
S		 1590}
1591
1592static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1593{
9780cb97 1594 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1595 struct sockaddr *mac_addr = p;
1596 int ret;
1597
1598 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1599 return -EADDRNOTAVAIL;
1600
5ec2a51e
JS		 1601 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1602 netdev_info(netdev, "already using mac address %pM\n",
1603 mac_addr->sa_data);
1604 return 0;
1605 }
1606
8e6de441
HT		 1607 /* For VF device, if there is a perm_addr, then the user will not
1608 * be allowed to change the address.
1609 */
1610 if (!hns3_is_phys_func(h->pdev) &&
1611 !is_zero_ether_addr(netdev->perm_addr)) {
1612 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1613 netdev->perm_addr, mac_addr->sa_data);
1614 return -EPERM;
1615 }
1616
59098055 1617 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1618 if (ret) {
1619 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1620 return ret;
1621 }
1622
1623 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1624
1625 return 0;
1626}
1627
26483246
XW		 1628static int hns3_nic_do_ioctl(struct net_device *netdev,
1629 struct ifreq *ifr, int cmd)
1630{
1631 struct hnae3_handle *h = hns3_get_handle(netdev);
1632
1633 if (!netif_running(netdev))
1634 return -EINVAL;
1635
1636 if (!h->ae_algo->ops->do_ioctl)
1637 return -EOPNOTSUPP;
1638
1639 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1640}
1641
76ad4f0e
S		 1642static int hns3_nic_set_features(struct net_device *netdev,
1643 netdev_features_t features)
1644{
181d454b 1645 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1646 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1647 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1648 bool enable;
052ece6d 1649 int ret;
76ad4f0e 1650
5c9f6b39 1651 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 1652 enable = !!(features & NETIF_F_GRO_HW);
1653 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 1654 if (ret)
1655 return ret;
1656 }
1657
bd368416
JS		 1658 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1659 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 1660 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1661 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 1662 if (ret)
1663 return ret;
1664 }
1665
c17852a8 1666 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 1667 enable = !!(features & NETIF_F_NTUPLE);
1668 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 1669 }
1670
0205ec04
JS		 1671 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
1672 h->ae_algo->ops->cls_flower_active(h)) {
1673 netdev_err(netdev,
1674 "there are offloaded TC filters active, cannot disable HW TC offload");
1675 return -EINVAL;
1676 }
1677
76ad4f0e
S		 1678 netdev->features = features;
1679 return 0;
1680}
1681
2a7556bb
YL		 1682static netdev_features_t hns3_features_check(struct sk_buff *skb,
1683 struct net_device *dev,
1684 netdev_features_t features)
1685{
1686#define HNS3_MAX_HDR_LEN 480U
1687#define HNS3_MAX_L4_HDR_LEN 60U
1688
1689 size_t len;
1690
1691 if (skb->ip_summed != CHECKSUM_PARTIAL)
1692 return features;
1693
1694 if (skb->encapsulation)
1695 len = skb_inner_transport_header(skb) - skb->data;
1696 else
1697 len = skb_transport_header(skb) - skb->data;
1698
1699 /* Assume L4 is 60 byte as TCP is the only protocol with a
1700 * a flexible value, and it's max len is 60 bytes.
1701 */
1702 len += HNS3_MAX_L4_HDR_LEN;
1703
1704 /* Hardware only supports checksum on the skb with a max header
1705 * len of 480 bytes.
1706 */
1707 if (len > HNS3_MAX_HDR_LEN)
1708 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1709
1710 return features;
1711}
1712
6c88d9d7
PL		 1713static void hns3_nic_get_stats64(struct net_device *netdev,
1714 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1715{
1716 struct hns3_nic_priv *priv = netdev_priv(netdev);
1717 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1718 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1719 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 1720 u64 rx_length_errors = 0;
1721 u64 rx_crc_errors = 0;
1722 u64 rx_multicast = 0;
76ad4f0e 1723 unsigned int start;
d3ec4ef6
JS		 1724 u64 tx_errors = 0;
1725 u64 rx_errors = 0;
76ad4f0e
S		 1726 unsigned int idx;
1727 u64 tx_bytes = 0;
1728 u64 rx_bytes = 0;
1729 u64 tx_pkts = 0;
1730 u64 rx_pkts = 0;
d2a5dca8
JS		 1731 u64 tx_drop = 0;
1732 u64 rx_drop = 0;
76ad4f0e 1733
b875cc37
JS		 1734 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1735 return;
1736
c5f65480
JS		 1737 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1738
76ad4f0e
S		 1739 for (idx = 0; idx < queue_num; idx++) {
1740 /* fetch the tx stats */
5f06b903 1741 ring = &priv->ring[idx];
76ad4f0e 1742 do {
d36d36ce 1743 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1744 tx_bytes += ring->stats.tx_bytes;
1745 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1746 tx_drop += ring->stats.sw_err_cnt;
b20d7fe5
YL		 1747 tx_drop += ring->stats.tx_vlan_err;
1748 tx_drop += ring->stats.tx_l4_proto_err;
1749 tx_drop += ring->stats.tx_l2l3l4_err;
1750 tx_drop += ring->stats.tx_tso_err;
d3ec4ef6 1751 tx_errors += ring->stats.sw_err_cnt;
b20d7fe5
YL		 1752 tx_errors += ring->stats.tx_vlan_err;
1753 tx_errors += ring->stats.tx_l4_proto_err;
1754 tx_errors += ring->stats.tx_l2l3l4_err;
1755 tx_errors += ring->stats.tx_tso_err;
76ad4f0e
S		 1756 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1757
1758 /* fetch the rx stats */
5f06b903 1759 ring = &priv->ring[idx + queue_num];
76ad4f0e 1760 do {
d36d36ce 1761 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1762 rx_bytes += ring->stats.rx_bytes;
1763 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1764 rx_drop += ring->stats.l2_err;
d3ec4ef6 1765 rx_errors += ring->stats.l2_err;
8b552079 1766 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 1767 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS		 1768 rx_multicast += ring->stats.rx_multicast;
1769 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 1770 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1771 }
1772
1773 stats->tx_bytes = tx_bytes;
1774 stats->tx_packets = tx_pkts;
1775 stats->rx_bytes = rx_bytes;
1776 stats->rx_packets = rx_pkts;
1777
d3ec4ef6
JS		 1778 stats->rx_errors = rx_errors;
1779 stats->multicast = rx_multicast;
1780 stats->rx_length_errors = rx_length_errors;
1781 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 1782 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1783
d3ec4ef6
JS		 1784 stats->tx_errors = tx_errors;
1785 stats->rx_dropped = rx_drop;
1786 stats->tx_dropped = tx_drop;
76ad4f0e
S		 1787 stats->collisions = netdev->stats.collisions;
1788 stats->rx_over_errors = netdev->stats.rx_over_errors;
1789 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1790 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1791 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1792 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1793 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1794 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1795 stats->tx_window_errors = netdev->stats.tx_window_errors;
1796 stats->rx_compressed = netdev->stats.rx_compressed;
1797 stats->tx_compressed = netdev->stats.tx_compressed;
1798}
1799
30d240df 1800static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1801{
30d240df 1802 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
75718800 1803 struct hnae3_knic_private_info *kinfo;
30d240df
YL		 1804 u8 tc = mqprio_qopt->qopt.num_tc;
1805 u16 mode = mqprio_qopt->mode;
1806 u8 hw = mqprio_qopt->qopt.hw;
75718800 1807 struct hnae3_handle *h;
76ad4f0e 1808
30d240df
YL		 1809 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1810 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1811 return -EOPNOTSUPP;
1812
76ad4f0e
S		 1813 if (tc > HNAE3_MAX_TC)
1814 return -EINVAL;
1815
76ad4f0e
S		 1816 if (!netdev)
1817 return -EINVAL;
1818
75718800
YL		 1819 h = hns3_get_handle(netdev);
1820 kinfo = &h->kinfo;
1821
1c822948
YL		 1822 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1823
1cce5eb6 1824 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
5a5c9091 1825 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
76ad4f0e
S		 1826}
1827
0205ec04
JS		 1828static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
1829 struct flow_cls_offload *flow)
1830{
1831 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
1832 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
1833
1834 switch (flow->command) {
1835 case FLOW_CLS_REPLACE:
1836 if (h->ae_algo->ops->add_cls_flower)
1837 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
1838 break;
1839 case FLOW_CLS_DESTROY:
1840 if (h->ae_algo->ops->del_cls_flower)
1841 return h->ae_algo->ops->del_cls_flower(h, flow);
1842 break;
1843 default:
1844 break;
1845 }
1846
1847 return -EOPNOTSUPP;
1848}
1849
1850static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1851 void *cb_priv)
1852{
1853 struct hns3_nic_priv *priv = cb_priv;
1854
1855 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
1856 return -EOPNOTSUPP;
1857
1858 switch (type) {
1859 case TC_SETUP_CLSFLOWER:
1860 return hns3_setup_tc_cls_flower(priv, type_data);
1861 default:
1862 return -EOPNOTSUPP;
1863 }
1864}
1865
1866static LIST_HEAD(hns3_block_cb_list);
1867
2572ac53 1868static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1869 void *type_data)
76ad4f0e 1870{
0205ec04
JS		 1871 struct hns3_nic_priv *priv = netdev_priv(dev);
1872 int ret;
1873
1874 switch (type) {
1875 case TC_SETUP_QDISC_MQPRIO:
1876 ret = hns3_setup_tc(dev, type_data);
1877 break;
1878 case TC_SETUP_BLOCK:
1879 ret = flow_block_cb_setup_simple(type_data,
1880 &hns3_block_cb_list,
1881 hns3_setup_tc_block_cb,
1882 priv, priv, true);
1883 break;
1884 default:
38cf0426 1885 return -EOPNOTSUPP;
0205ec04 1886 }
76ad4f0e 1887
0205ec04 1888 return ret;
76ad4f0e
S		 1889}
1890
1891static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1892 __be16 proto, u16 vid)
1893{
9780cb97 1894 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1895 int ret = -EIO;
1896
1897 if (h->ae_algo->ops->set_vlan_filter)
1898 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1899
1900 return ret;
1901}
1902
1903static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1904 __be16 proto, u16 vid)
1905{
9780cb97 1906 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1907 int ret = -EIO;
1908
1909 if (h->ae_algo->ops->set_vlan_filter)
1910 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1911
7fa6be4f 1912 return ret;
681ec399
YL		 1913}
1914
76ad4f0e
S		 1915static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1916 u8 qos, __be16 vlan_proto)
1917{
9780cb97 1918 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1919 int ret = -EIO;
1920
1c822948 1921 netif_dbg(h, drv, netdev,
39edaf24
GL		 1922 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1923 vf, vlan, qos, ntohs(vlan_proto));
1c822948 1924
76ad4f0e
S		 1925 if (h->ae_algo->ops->set_vf_vlan_filter)
1926 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 1927 qos, vlan_proto);
76ad4f0e
S		 1928
1929 return ret;
1930}
1931
22044f95
JS		 1932static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1933{
1934 struct hnae3_handle *handle = hns3_get_handle(netdev);
1935
1936 if (hns3_nic_resetting(netdev))
1937 return -EBUSY;
1938
1939 if (!handle->ae_algo->ops->set_vf_spoofchk)
1940 return -EOPNOTSUPP;
1941
1942 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1943}
1944
e196ec75
JS		 1945static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1946{
1947 struct hnae3_handle *handle = hns3_get_handle(netdev);
1948
1949 if (!handle->ae_algo->ops->set_vf_trust)
1950 return -EOPNOTSUPP;
1951
1952 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1953}
1954
a8e8b7ff
S		 1955static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1956{
9780cb97 1957 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1958 int ret;
1959
6ff7ed80
HT		 1960 if (hns3_nic_resetting(netdev))
1961 return -EBUSY;
1962
a8e8b7ff
S		 1963 if (!h->ae_algo->ops->set_mtu)
1964 return -EOPNOTSUPP;
1965
1c822948
YL		 1966 netif_dbg(h, drv, netdev,
1967 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1968
a8e8b7ff 1969 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1970 if (ret)
a8e8b7ff
S		 1971 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1972 ret);
93d8daf4
YL		 1973 else
1974 netdev->mtu = new_mtu;
5bad95a1 1975
a8e8b7ff
S		 1976 return ret;
1977}
1978
f8fa222c
L		 1979static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1980{
1981 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1982 struct hnae3_handle *h = hns3_get_handle(ndev);
0bfdf286 1983 struct hns3_enet_ring *tx_ring;
e511c97d 1984 struct napi_struct *napi;
f8fa222c
L		 1985 int timeout_queue = 0;
1986 int hw_head, hw_tail;
e511c97d
JS		 1987 int fbd_num, fbd_oft;
1988 int ebd_num, ebd_oft;
1989 int bd_num, bd_err;
1990 int ring_en, tc;
f8fa222c
L		 1991 int i;
1992
1993 /* Find the stopped queue the same way the stack does */
fa6c4084 1994 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 1995 struct netdev_queue *q;
1996 unsigned long trans_start;
1997
1998 q = netdev_get_tx_queue(ndev, i);
1999 trans_start = q->trans_start;
2000 if (netif_xmit_stopped(q) &&
2001 time_after(jiffies,
2002 (trans_start + ndev->watchdog_timeo))) {
2003 timeout_queue = i;
647522a5
YL		 2004 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2005 q->state,
2006 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L		 2007 break;
2008 }
2009 }
2010
2011 if (i == ndev->num_tx_queues) {
2012 netdev_info(ndev,
2013 "no netdev TX timeout queue found, timeout count: %llu\n",
2014 priv->tx_timeout_count);
2015 return false;
2016 }
2017
beab694a
JS		 2018 priv->tx_timeout_count++;
2019
5f06b903 2020 tx_ring = &priv->ring[timeout_queue];
e511c97d
JS		 2021 napi = &tx_ring->tqp_vector->napi;
2022
2023 netdev_info(ndev,
2024 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2025 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2026 tx_ring->next_to_clean, napi->state);
2027
2028 netdev_info(ndev,
20d06ca2 2029 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
e511c97d 2030 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
20d06ca2 2031 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
e511c97d
JS		 2032
2033 netdev_info(ndev,
f6061a05
YL		 2034 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2035 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
e511c97d
JS		 2036 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2037
2038 /* When mac received many pause frames continuous, it's unable to send
2039 * packets, which may cause tx timeout
2040 */
615466ce
YM		 2041 if (h->ae_algo->ops->get_mac_stats) {
2042 struct hns3_mac_stats mac_stats;
e511c97d 2043
615466ce 2044 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
e511c97d 2045 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
615466ce 2046 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
e511c97d 2047 }
f8fa222c
L		 2048
2049 hw_head = readl_relaxed(tx_ring->tqp->io_base +
2050 HNS3_RING_TX_RING_HEAD_REG);
2051 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
2052 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 2053 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
2054 HNS3_RING_TX_RING_FBDNUM_REG);
2055 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
2056 HNS3_RING_TX_RING_OFFSET_REG);
2057 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
2058 HNS3_RING_TX_RING_EBDNUM_REG);
2059 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
2060 HNS3_RING_TX_RING_EBD_OFFSET_REG);
2061 bd_num = readl_relaxed(tx_ring->tqp->io_base +
2062 HNS3_RING_TX_RING_BD_NUM_REG);
2063 bd_err = readl_relaxed(tx_ring->tqp->io_base +
2064 HNS3_RING_TX_RING_BD_ERR_REG);
2065 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
2066 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
2067
f8fa222c 2068 netdev_info(ndev,
e511c97d
JS		 2069 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2070 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 2071 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 2072 netdev_info(ndev,
2073 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2074 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 2075
2076 return true;
2077}
2078
0290bd29 2079static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
f8fa222c
L		 2080{
2081 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 2082 struct hnae3_handle *h = priv->ae_handle;
2083
2084 if (!hns3_get_tx_timeo_queue_info(ndev))
2085 return;
2086
0742ed7c
HT		 2087 /* request the reset, and let the hclge to determine
2088 * which reset level should be done
2089 */
f8fa222c 2090 if (h->ae_algo->ops->reset_event)
6ae4e733 2091 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 2092}
2093
d93ed94f
JS		 2094#ifdef CONFIG_RFS_ACCEL
2095static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2096 u16 rxq_index, u32 flow_id)
2097{
2098 struct hnae3_handle *h = hns3_get_handle(dev);
2099 struct flow_keys fkeys;
2100
2101 if (!h->ae_algo->ops->add_arfs_entry)
2102 return -EOPNOTSUPP;
2103
2104 if (skb->encapsulation)
2105 return -EPROTONOSUPPORT;
2106
2107 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2108 return -EPROTONOSUPPORT;
2109
2110 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2111 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2112 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2113 fkeys.basic.ip_proto != IPPROTO_UDP))
2114 return -EPROTONOSUPPORT;
2115
2116 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2117}
2118#endif
2119
6430f744
YM		 2120static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2121 struct ifla_vf_info *ivf)
2122{
2123 struct hnae3_handle *h = hns3_get_handle(ndev);
2124
2125 if (!h->ae_algo->ops->get_vf_config)
2126 return -EOPNOTSUPP;
2127
2128 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2129}
2130
2131static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2132 int link_state)
2133{
2134 struct hnae3_handle *h = hns3_get_handle(ndev);
2135
2136 if (!h->ae_algo->ops->set_vf_link_state)
2137 return -EOPNOTSUPP;
2138
2139 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2140}
2141
ee9e4424
YL		 2142static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2143 int min_tx_rate, int max_tx_rate)
2144{
2145 struct hnae3_handle *h = hns3_get_handle(ndev);
2146
2147 if (!h->ae_algo->ops->set_vf_rate)
2148 return -EOPNOTSUPP;
2149
2150 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2151 false);
2152}
2153
8e6de441
HT		 2154static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2155{
2156 struct hnae3_handle *h = hns3_get_handle(netdev);
2157
2158 if (!h->ae_algo->ops->set_vf_mac)
2159 return -EOPNOTSUPP;
2160
2161 if (is_multicast_ether_addr(mac)) {
2162 netdev_err(netdev,
2163 "Invalid MAC:%pM specified. Could not set MAC\n",
2164 mac);
2165 return -EINVAL;
2166 }
2167
2168 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2169}
2170
76ad4f0e
S		 2171static const struct net_device_ops hns3_nic_netdev_ops = {
2172 .ndo_open = hns3_nic_net_open,
2173 .ndo_stop = hns3_nic_net_stop,
2174 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 2175 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 2176 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 2177 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 2178 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e 2179 .ndo_set_features = hns3_nic_set_features,
2a7556bb 2180 .ndo_features_check = hns3_features_check,
76ad4f0e
S		 2181 .ndo_get_stats64 = hns3_nic_get_stats64,
2182 .ndo_setup_tc = hns3_nic_setup_tc,
2183 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 2184 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2185 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2186 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
22044f95 2187 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
e196ec75 2188 .ndo_set_vf_trust = hns3_set_vf_trust,
d93ed94f
JS		 2189#ifdef CONFIG_RFS_ACCEL
2190 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2191#endif
6430f744
YM		 2192 .ndo_get_vf_config = hns3_nic_get_vf_config,
2193 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
ee9e4424 2194 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
8e6de441 2195 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
76ad4f0e
S		 2196};
2197
97afd47b 2198bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 2199{
2200 u32 dev_id = pdev->device;
2201
2202 switch (dev_id) {
2203 case HNAE3_DEV_ID_GE:
2204 case HNAE3_DEV_ID_25GE:
2205 case HNAE3_DEV_ID_25GE_RDMA:
2206 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2207 case HNAE3_DEV_ID_50GE_RDMA:
2208 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2209 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
ae6f010c 2210 case HNAE3_DEV_ID_200G_RDMA:
2312e050 2211 return true;
c155e22b
GH		 2212 case HNAE3_DEV_ID_VF:
2213 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
2312e050
FL		 2214 return false;
2215 default:
adcf738b 2216 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2312e050
FL		 2217 dev_id);
2218 }
2219
2220 return false;
2221}
2222
2312e050
FL		 2223static void hns3_disable_sriov(struct pci_dev *pdev)
2224{
2225 /* If our VFs are assigned we cannot shut down SR-IOV
2226 * without causing issues, so just leave the hardware
2227 * available but disabled
2228 */
2229 if (pci_vfs_assigned(pdev)) {
2230 dev_warn(&pdev->dev,
2231 "disabling driver while VFs are assigned\n");
2232 return;
2233 }
2234
2235 pci_disable_sriov(pdev);
2236}
2237
76ad4f0e
S		 2238/* hns3_probe - Device initialization routine
2239 * @pdev: PCI device information struct
2240 * @ent: entry in hns3_pci_tbl
2241 *
2242 * hns3_probe initializes a PF identified by a pci_dev structure.
2243 * The OS initialization, configuring of the PF private structure,
2244 * and a hardware reset occur.
2245 *
2246 * Returns 0 on success, negative on failure
2247 */
2248static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2249{
2250 struct hnae3_ae_dev *ae_dev;
2251 int ret;
2252
9b2f3477 2253 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
60df7e91
HT		 2254 if (!ae_dev)
2255 return -ENOMEM;
76ad4f0e
S		 2256
2257 ae_dev->pdev = pdev;
e92a0843 2258 ae_dev->flag = ent->driver_data;
76ad4f0e
S		 2259 pci_set_drvdata(pdev, ae_dev);
2260
74354140 2261 ret = hnae3_register_ae_dev(ae_dev);
674a1357 2262 if (ret)
74354140 2263 pci_set_drvdata(pdev, NULL);
2312e050 2264
74354140 2265 return ret;
76ad4f0e
S		 2266}
2267
2268/* hns3_remove - Device removal routine
2269 * @pdev: PCI device information struct
2270 */
2271static void hns3_remove(struct pci_dev *pdev)
2272{
2273 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2274
2312e050
FL		 2275 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2276 hns3_disable_sriov(pdev);
2277
76ad4f0e 2278 hnae3_unregister_ae_dev(ae_dev);
ac864c23 2279 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 2280}
2281
fa8d82e8
PL		 2282/**
2283 * hns3_pci_sriov_configure
2284 * @pdev: pointer to a pci_dev structure
2285 * @num_vfs: number of VFs to allocate
2286 *
2287 * Enable or change the number of VFs. Called when the user updates the number
2288 * of VFs in sysfs.
2289 **/
743e1a84 2290static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 2291{
2292 int ret;
2293
2294 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2295 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2296 return -EINVAL;
2297 }
2298
2299 if (num_vfs) {
2300 ret = pci_enable_sriov(pdev, num_vfs);
2301 if (ret)
2302 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 2303 else
2304 return num_vfs;
fa8d82e8
PL		 2305 } else if (!pci_vfs_assigned(pdev)) {
2306 pci_disable_sriov(pdev);
2307 } else {
2308 dev_warn(&pdev->dev,
2309 "Unable to free VFs because some are assigned to VMs.\n");
2310 }
2311
2312 return 0;
2313}
2314
ce2c1d2e
YL		 2315static void hns3_shutdown(struct pci_dev *pdev)
2316{
2317 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2318
2319 hnae3_unregister_ae_dev(ae_dev);
ce2c1d2e
YL		 2320 pci_set_drvdata(pdev, NULL);
2321
2322 if (system_state == SYSTEM_POWER_OFF)
2323 pci_set_power_state(pdev, PCI_D3hot);
2324}
2325
5a9f0eac
SJ		 2326static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2327 pci_channel_state_t state)
2328{
2329 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2330 pci_ers_result_t ret;
2331
2332 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2333
2334 if (state == pci_channel_io_perm_failure)
2335 return PCI_ERS_RESULT_DISCONNECT;
2336
661262bc 2337 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 2338 dev_err(&pdev->dev,
661262bc 2339 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ		 2340 return PCI_ERS_RESULT_NONE;
2341 }
2342
381c356e
SJ		 2343 if (ae_dev->ops->handle_hw_ras_error)
2344 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 2345 else
2346 return PCI_ERS_RESULT_NONE;
2347
2348 return ret;
2349}
2350
6ae4e733
SJ		 2351static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2352{
2353 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 2354 const struct hnae3_ae_ops *ops;
123297b7 2355 enum hnae3_reset_type reset_type;
6ae4e733
SJ		 2356 struct device *dev = &pdev->dev;
2357
661262bc
WL		 2358 if (!ae_dev || !ae_dev->ops)
2359 return PCI_ERS_RESULT_NONE;
2360
ad9bf545 2361 ops = ae_dev->ops;
6ae4e733 2362 /* request the reset */
fa17c708
GH		 2363 if (ops->reset_event && ops->get_reset_level &&
2364 ops->set_default_reset_request) {
9d5e67d1 2365 if (ae_dev->hw_err_reset_req) {
123297b7
SJ		 2366 reset_type = ops->get_reset_level(ae_dev,
2367 &ae_dev->hw_err_reset_req);
2368 ops->set_default_reset_request(ae_dev, reset_type);
2369 dev_info(dev, "requesting reset due to PCI error\n");
2370 ops->reset_event(pdev, NULL);
2371 }
69b51bbb 2372
6ae4e733
SJ		 2373 return PCI_ERS_RESULT_RECOVERED;
2374 }
2375
2376 return PCI_ERS_RESULT_DISCONNECT;
2377}
2378
6b9a97ee
HT		 2379static void hns3_reset_prepare(struct pci_dev *pdev)
2380{
2381 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2382
8de91e92 2383 dev_info(&pdev->dev, "FLR prepare\n");
6b9a97ee
HT		 2384 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2385 ae_dev->ops->flr_prepare(ae_dev);
2386}
2387
2388static void hns3_reset_done(struct pci_dev *pdev)
2389{
2390 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2391
8de91e92 2392 dev_info(&pdev->dev, "FLR done\n");
6b9a97ee
HT		 2393 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2394 ae_dev->ops->flr_done(ae_dev);
2395}
2396
5a9f0eac
SJ		 2397static const struct pci_error_handlers hns3_err_handler = {
2398 .error_detected = hns3_error_detected,
6ae4e733 2399 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 2400 .reset_prepare = hns3_reset_prepare,
2401 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 2402};
2403
76ad4f0e
S		 2404static struct pci_driver hns3_driver = {
2405 .name = hns3_driver_name,
2406 .id_table = hns3_pci_tbl,
2407 .probe = hns3_probe,
2408 .remove = hns3_remove,
ce2c1d2e 2409 .shutdown = hns3_shutdown,
fa8d82e8 2410 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 2411 .err_handler = &hns3_err_handler,
76ad4f0e
S		 2412};
2413
2414/* set default feature to hns3 */
2415static void hns3_set_default_feature(struct net_device *netdev)
2416{
3e85af6a
PL		 2417 struct hnae3_handle *h = hns3_get_handle(netdev);
2418 struct pci_dev *pdev = h->pdev;
295ba232 2419 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3e85af6a 2420
76ad4f0e
S		 2421 netdev->priv_flags |= IFF_UNICAST_FLT;
2422
66d52f3b 2423 netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
76ad4f0e
S		 2424 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2425 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 2426 NETIF_F_SCTP_CRC | NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
76ad4f0e
S		 2427
2428 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2429
66d52f3b 2430 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2431 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2432 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2433 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2434 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 2435 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
76ad4f0e 2436
66d52f3b 2437 netdev->vlan_features |= NETIF_F_RXCSUM |
76ad4f0e
S		 2438 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2439 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2440 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 2441 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
76ad4f0e 2442
66d52f3b
HT		 2443 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
2444 NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2445 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2446 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2447 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 2448 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3e85af6a 2449
295ba232 2450 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
77af09c6 2451 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2452 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 2453
2454 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2455 netdev->hw_features |= NETIF_F_NTUPLE;
2456 netdev->features |= NETIF_F_NTUPLE;
2457 }
2458 }
0692cfe9
HT		 2459
2460 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) {
2461 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
2462 netdev->features |= NETIF_F_GSO_UDP_L4;
2463 netdev->vlan_features |= NETIF_F_GSO_UDP_L4;
2464 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4;
2465 }
66d52f3b
HT		 2466
2467 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) {
2468 netdev->hw_features |= NETIF_F_HW_CSUM;
2469 netdev->features |= NETIF_F_HW_CSUM;
2470 netdev->vlan_features |= NETIF_F_HW_CSUM;
2471 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
2472 } else {
2473 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2474 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2475 netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2476 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2477 }
3e281621
HT		 2478
2479 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) {
2480 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2481 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2482 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2483 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2484 }
0205ec04
JS		 2485
2486 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) {
2487 netdev->hw_features |= NETIF_F_HW_TC;
2488 netdev->features |= NETIF_F_HW_TC;
2489 }
76ad4f0e
S		 2490}
2491
2492static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2493 struct hns3_desc_cb *cb)
2494{
dbba6da0 2495 unsigned int order = hns3_page_order(ring);
76ad4f0e
S		 2496 struct page *p;
2497
2498 p = dev_alloc_pages(order);
2499 if (!p)
2500 return -ENOMEM;
2501
2502 cb->priv = p;
2503 cb->page_offset = 0;
2504 cb->reuse_flag = 0;
2505 cb->buf = page_address(p);
dbba6da0 2506 cb->length = hns3_page_size(ring);
76ad4f0e 2507 cb->type = DESC_TYPE_PAGE;
aeda9bf8
YL		 2508 page_ref_add(p, USHRT_MAX - 1);
2509 cb->pagecnt_bias = USHRT_MAX;
76ad4f0e 2510
76ad4f0e
S		 2511 return 0;
2512}
2513
2514static void hns3_free_buffer(struct hns3_enet_ring *ring,
619ae331 2515 struct hns3_desc_cb *cb, int budget)
76ad4f0e
S		 2516{
2517 if (cb->type == DESC_TYPE_SKB)
619ae331 2518 napi_consume_skb(cb->priv, budget);
aeda9bf8
YL		 2519 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias)
2520 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
76ad4f0e
S		 2521 memset(cb, 0, sizeof(*cb));
2522}
2523
2524static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2525{
2526 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2527 cb->length, ring_to_dma_dir(ring));
2528
2211f4e1 2529 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 2530 return -EIO;
2531
2532 return 0;
2533}
2534
2535static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2536 struct hns3_desc_cb *cb)
2537{
74ef402e 2538 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
76ad4f0e
S		 2539 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2540 ring_to_dma_dir(ring));
bcdb12b7 2541 else if (cb->length)
76ad4f0e
S		 2542 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2543 ring_to_dma_dir(ring));
2544}
2545
2546static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2547{
2548 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2549 ring->desc[i].addr = 0;
2550}
2551
619ae331
YL		 2552static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
2553 int budget)
76ad4f0e
S		 2554{
2555 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2556
2557 if (!ring->desc_cb[i].dma)
2558 return;
2559
2560 hns3_buffer_detach(ring, i);
619ae331 2561 hns3_free_buffer(ring, cb, budget);
76ad4f0e
S		 2562}
2563
2564static void hns3_free_buffers(struct hns3_enet_ring *ring)
2565{
2566 int i;
2567
2568 for (i = 0; i < ring->desc_num; i++)
619ae331 2569 hns3_free_buffer_detach(ring, i, 0);
76ad4f0e
S		 2570}
2571
2572/* free desc along with its attached buffer */
2573static void hns3_free_desc(struct hns3_enet_ring *ring)
2574{
024cc792
HT		 2575 int size = ring->desc_num * sizeof(ring->desc[0]);
2576
76ad4f0e
S		 2577 hns3_free_buffers(ring);
2578
024cc792
HT		 2579 if (ring->desc) {
2580 dma_free_coherent(ring_to_dev(ring), size,
2581 ring->desc, ring->desc_dma_addr);
2582 ring->desc = NULL;
2583 }
76ad4f0e
S		 2584}
2585
2586static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2587{
2588 int size = ring->desc_num * sizeof(ring->desc[0]);
2589
750afb08
LC		 2590 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2591 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 2592 if (!ring->desc)
2593 return -ENOMEM;
2594
76ad4f0e
S		 2595 return 0;
2596}
2597
4d2cad32 2598static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
76ad4f0e
S		 2599 struct hns3_desc_cb *cb)
2600{
2601 int ret;
2602
2603 ret = hns3_alloc_buffer(ring, cb);
2604 if (ret)
2605 goto out;
2606
2607 ret = hns3_map_buffer(ring, cb);
2608 if (ret)
2609 goto out_with_buf;
2610
2611 return 0;
2612
2613out_with_buf:
619ae331 2614 hns3_free_buffer(ring, cb, 0);
76ad4f0e
S		 2615out:
2616 return ret;
2617}
2618
4d2cad32 2619static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
76ad4f0e 2620{
4d2cad32 2621 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2622
2623 if (ret)
2624 return ret;
2625
2626 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2627
2628 return 0;
2629}
2630
2631/* Allocate memory for raw pkg, and map with dma */
2632static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2633{
2634 int i, j, ret;
2635
2636 for (i = 0; i < ring->desc_num; i++) {
4d2cad32 2637 ret = hns3_alloc_and_attach_buffer(ring, i);
76ad4f0e
S		 2638 if (ret)
2639 goto out_buffer_fail;
2640 }
2641
2642 return 0;
2643
2644out_buffer_fail:
2645 for (j = i - 1; j >= 0; j--)
619ae331 2646 hns3_free_buffer_detach(ring, j, 0);
76ad4f0e
S		 2647 return ret;
2648}
2649
9b2f3477 2650/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S		 2651static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2652 struct hns3_desc_cb *res_cb)
2653{
b9077428 2654 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2655 ring->desc_cb[i] = *res_cb;
2656 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2657 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2658}
2659
2660static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2661{
2662 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL		 2663 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2664 ring->desc_cb[i].page_offset);
7d0b130c 2665 ring->desc[i].rx.bd_base_info = 0;
c2a2e127
BS		 2666
2667 dma_sync_single_for_device(ring_to_dev(ring),
2668 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
2669 hns3_buf_size(ring),
2670 DMA_FROM_DEVICE);
76ad4f0e
S		 2671}
2672
20d06ca2 2673static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
619ae331 2674 int *bytes, int *pkts, int budget)
76ad4f0e 2675{
20d06ca2
YL		 2676 /* pair with ring->last_to_use update in hns3_tx_doorbell(),
2677 * smp_store_release() is not used in hns3_tx_doorbell() because
2678 * the doorbell operation already have the needed barrier operation.
2679 */
2680 int ltu = smp_load_acquire(&ring->last_to_use);
26cda2f1
YL		 2681 int ntc = ring->next_to_clean;
2682 struct hns3_desc_cb *desc_cb;
20d06ca2
YL		 2683 bool reclaimed = false;
2684 struct hns3_desc *desc;
2685
2686 while (ltu != ntc) {
2687 desc = &ring->desc[ntc];
2688
2689 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
2690 BIT(HNS3_TXD_VLD_B))
2691 break;
76ad4f0e 2692
ce74370c
YL		 2693 desc_cb = &ring->desc_cb[ntc];
2694 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2695 (*bytes) += desc_cb->length;
2696 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
619ae331 2697 hns3_free_buffer_detach(ring, ntc, budget);
76ad4f0e 2698
ce74370c
YL		 2699 if (++ntc == ring->desc_num)
2700 ntc = 0;
2701
2702 /* Issue prefetch for next Tx descriptor */
2703 prefetch(&ring->desc_cb[ntc]);
20d06ca2 2704 reclaimed = true;
ce74370c 2705 }
26cda2f1 2706
20d06ca2
YL		 2707 if (unlikely(!reclaimed))
2708 return false;
2709
26cda2f1
YL		 2710 /* This smp_store_release() pairs with smp_load_acquire() in
2711 * ring_space called by hns3_nic_net_xmit.
2712 */
2713 smp_store_release(&ring->next_to_clean, ntc);
20d06ca2 2714 return true;
76ad4f0e
S		 2715}
2716
619ae331 2717void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
76ad4f0e 2718{
c8711956 2719 struct net_device *netdev = ring_to_netdev(ring);
7a810110 2720 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2721 struct netdev_queue *dev_queue;
2722 int bytes, pkts;
76ad4f0e
S		 2723
2724 bytes = 0;
2725 pkts = 0;
20d06ca2 2726
619ae331 2727 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
20d06ca2 2728 return;
76ad4f0e
S		 2729
2730 ring->tqp_vector->tx_group.total_bytes += bytes;
2731 ring->tqp_vector->tx_group.total_packets += pkts;
2732
2733 u64_stats_update_begin(&ring->syncp);
2734 ring->stats.tx_bytes += bytes;
2735 ring->stats.tx_pkts += pkts;
2736 u64_stats_update_end(&ring->syncp);
2737
2738 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2739 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2740
2a597eff 2741 if (unlikely(netif_carrier_ok(netdev) &&
8ae10cfb 2742 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
76ad4f0e
S		 2743 /* Make sure that anybody stopping the queue after this
2744 * sees the new next_to_clean.
2745 */
2746 smp_mb();
7a810110
JS		 2747 if (netif_tx_queue_stopped(dev_queue) &&
2748 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2749 netif_tx_wake_queue(dev_queue);
2750 ring->stats.restart_queue++;
2751 }
2752 }
76ad4f0e
S		 2753}
2754
2755static int hns3_desc_unused(struct hns3_enet_ring *ring)
2756{
2757 int ntc = ring->next_to_clean;
2758 int ntu = ring->next_to_use;
2759
2760 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2761}
2762
9b2f3477
WL		 2763static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2764 int cleand_count)
76ad4f0e
S		 2765{
2766 struct hns3_desc_cb *desc_cb;
2767 struct hns3_desc_cb res_cbs;
2768 int i, ret;
2769
2770 for (i = 0; i < cleand_count; i++) {
2771 desc_cb = &ring->desc_cb[ring->next_to_use];
2772 if (desc_cb->reuse_flag) {
2773 u64_stats_update_begin(&ring->syncp);
2774 ring->stats.reuse_pg_cnt++;
2775 u64_stats_update_end(&ring->syncp);
2776
2777 hns3_reuse_buffer(ring, ring->next_to_use);
2778 } else {
4d2cad32 2779 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
76ad4f0e
S		 2780 if (ret) {
2781 u64_stats_update_begin(&ring->syncp);
2782 ring->stats.sw_err_cnt++;
2783 u64_stats_update_end(&ring->syncp);
2784
c8711956 2785 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5
YL		 2786 "alloc rx buffer failed: %d\n",
2787 ret);
76ad4f0e
S		 2788 break;
2789 }
2790 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 2791
2792 u64_stats_update_begin(&ring->syncp);
2793 ring->stats.non_reuse_pg++;
2794 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 2795 }
2796
2797 ring_ptr_move_fw(ring, next_to_use);
2798 }
2799
48ee56fd 2800 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
76ad4f0e
S		 2801}
2802
08bb3857
YL		 2803static bool hns3_page_is_reusable(struct page *page)
2804{
2805 return page_to_nid(page) == numa_mem_id() &&
2806 !page_is_pfmemalloc(page);
2807}
2808
aeda9bf8
YL		 2809static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
2810{
2811 return (page_count(cb->priv) - cb->pagecnt_bias) == 1;
2812}
2813
76ad4f0e
S		 2814static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2815 struct hns3_enet_ring *ring, int pull_len,
2816 struct hns3_desc_cb *desc_cb)
2817{
389ca146
YL		 2818 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2819 int size = le16_to_cpu(desc->rx.size);
dbba6da0 2820 u32 truesize = hns3_buf_size(ring);
76ad4f0e 2821
aeda9bf8 2822 desc_cb->pagecnt_bias--;
76ad4f0e 2823 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2824 size - pull_len, truesize);
76ad4f0e 2825
389ca146
YL		 2826 /* Avoid re-using remote pages, or the stack is still using the page
2827 * when page_offset rollback to zero, flag default unreuse
2828 */
08bb3857 2829 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
aeda9bf8
YL		 2830 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) {
2831 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
76ad4f0e 2832 return;
aeda9bf8 2833 }
76ad4f0e
S		 2834
2835 /* Move offset up to the next cache line */
2836 desc_cb->page_offset += truesize;
2837
dbba6da0 2838 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
76ad4f0e 2839 desc_cb->reuse_flag = 1;
aeda9bf8 2840 } else if (hns3_can_reuse_page(desc_cb)) {
389ca146
YL		 2841 desc_cb->reuse_flag = 1;
2842 desc_cb->page_offset = 0;
aeda9bf8
YL		 2843 } else if (desc_cb->pagecnt_bias) {
2844 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
2845 return;
2846 }
2847
2848 if (unlikely(!desc_cb->pagecnt_bias)) {
2849 page_ref_add(desc_cb->priv, USHRT_MAX);
2850 desc_cb->pagecnt_bias = USHRT_MAX;
76ad4f0e
S		 2851 }
2852}
2853
e2ee1c5a 2854static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL		 2855{
2856 __be16 type = skb->protocol;
2857 struct tcphdr *th;
2858 int depth = 0;
2859
e2ee1c5a 2860 while (eth_type_vlan(type)) {
d474d88f
YL		 2861 struct vlan_hdr *vh;
2862
2863 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2864 return -EFAULT;
2865
2866 vh = (struct vlan_hdr *)(skb->data + depth);
2867 type = vh->h_vlan_encapsulated_proto;
2868 depth += VLAN_HLEN;
2869 }
2870
e2ee1c5a
YL		 2871 skb_set_network_header(skb, depth);
2872
d474d88f 2873 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL		 2874 const struct iphdr *iph = ip_hdr(skb);
2875
d474d88f 2876 depth += sizeof(struct iphdr);
e2ee1c5a
YL		 2877 skb_set_transport_header(skb, depth);
2878 th = tcp_hdr(skb);
2879 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2880 iph->daddr, 0);
d474d88f 2881 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL		 2882 const struct ipv6hdr *iph = ipv6_hdr(skb);
2883
d474d88f 2884 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL		 2885 skb_set_transport_header(skb, depth);
2886 th = tcp_hdr(skb);
2887 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2888 &iph->daddr, 0);
d474d88f 2889 } else {
b20d7fe5
YL		 2890 hns3_rl_err(skb->dev,
2891 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2892 be16_to_cpu(type), depth);
d474d88f
YL		 2893 return -EFAULT;
2894 }
2895
d474d88f
YL		 2896 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2897 if (th->cwr)
2898 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2899
e2ee1c5a
YL		 2900 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2901 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 2902
e2ee1c5a
YL		 2903 skb->csum_start = (unsigned char *)th - skb->head;
2904 skb->csum_offset = offsetof(struct tcphdr, check);
2905 skb->ip_summed = CHECKSUM_PARTIAL;
698a8954
YL		 2906
2907 trace_hns3_gro(skb);
2908
d474d88f
YL		 2909 return 0;
2910}
2911
4b2fe769
HT		 2912static void hns3_checksum_complete(struct hns3_enet_ring *ring,
2913 struct sk_buff *skb, u32 l234info)
2914{
2915 u32 lo, hi;
2916
2917 u64_stats_update_begin(&ring->syncp);
2918 ring->stats.csum_complete++;
2919 u64_stats_update_end(&ring->syncp);
2920 skb->ip_summed = CHECKSUM_COMPLETE;
2921 lo = hnae3_get_field(l234info, HNS3_RXD_L2_CSUM_L_M,
2922 HNS3_RXD_L2_CSUM_L_S);
2923 hi = hnae3_get_field(l234info, HNS3_RXD_L2_CSUM_H_M,
2924 HNS3_RXD_L2_CSUM_H_S);
2925 skb->csum = csum_unfold((__force __sum16)(lo | hi << 8));
2926}
2927
76ad4f0e 2928static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
39c38824 2929 u32 l234info, u32 bd_base_info, u32 ol_info)
76ad4f0e 2930{
c8711956 2931 struct net_device *netdev = ring_to_netdev(ring);
76ad4f0e 2932 int l3_type, l4_type;
76ad4f0e 2933 int ol4_type;
76ad4f0e
S		 2934
2935 skb->ip_summed = CHECKSUM_NONE;
2936
2937 skb_checksum_none_assert(skb);
2938
2939 if (!(netdev->features & NETIF_F_RXCSUM))
2940 return;
2941
4b2fe769
HT		 2942 if (l234info & BIT(HNS3_RXD_L2_CSUM_B)) {
2943 hns3_checksum_complete(ring, skb, l234info);
2944 return;
2945 }
2946
76ad4f0e 2947 /* check if hardware has done checksum */
e8149933 2948 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S		 2949 return;
2950
f4772dee
DC		 2951 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2952 BIT(HNS3_RXD_OL3E_B) |
e8149933 2953 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S		 2954 u64_stats_update_begin(&ring->syncp);
2955 ring->stats.l3l4_csum_err++;
2956 u64_stats_update_end(&ring->syncp);
2957
2958 return;
2959 }
2960
39c38824 2961 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 2962 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2963 switch (ol4_type) {
2964 case HNS3_OL4_TYPE_MAC_IN_UDP:
2965 case HNS3_OL4_TYPE_NVGRE:
2966 skb->csum_level = 1;
df561f66 2967 fallthrough;
76ad4f0e 2968 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 2969 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2970 HNS3_RXD_L3ID_S);
2971 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2972 HNS3_RXD_L4ID_S);
2973
76ad4f0e 2974 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2975 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2976 l3_type == HNS3_L3_TYPE_IPV6) &&
2977 (l4_type == HNS3_L4_TYPE_UDP ||
2978 l4_type == HNS3_L4_TYPE_TCP ||
2979 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2980 skb->ip_summed = CHECKSUM_UNNECESSARY;
2981 break;
fa7a4bd5
JS		 2982 default:
2983 break;
76ad4f0e
S		 2984 }
2985}
2986
d43e5aca
YL		 2987static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2988{
81ae0e04
PL		 2989 if (skb_has_frag_list(skb))
2990 napi_gro_flush(&ring->tqp_vector->napi, false);
2991
d43e5aca
YL		 2992 napi_gro_receive(&ring->tqp_vector->napi, skb);
2993}
2994
701a6d6a
JS		 2995static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2996 struct hns3_desc *desc, u32 l234info,
2997 u16 *vlan_tag)
5b5455a9 2998{
44e626f7 2999 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 3000 struct pci_dev *pdev = ring->tqp->handle->pdev;
295ba232 3001 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5b5455a9 3002
295ba232 3003 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
701a6d6a
JS		 3004 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3005 if (!(*vlan_tag & VLAN_VID_MASK))
3006 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 3007
701a6d6a 3008 return (*vlan_tag != 0);
5b5455a9
PL		 3009 }
3010
3011#define HNS3_STRP_OUTER_VLAN 0x1
3012#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 3013#define HNS3_STRP_BOTH 0x3
5b5455a9 3014
44e626f7
JS		 3015 /* Hardware always insert VLAN tag into RX descriptor when
3016 * remove the tag from packet, driver needs to determine
3017 * reporting which tag to stack.
3018 */
e4e87715
PL		 3019 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3020 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 3021 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 3022 if (handle->port_base_vlan_state !=
3023 HNAE3_PORT_BASE_VLAN_DISABLE)
3024 return false;
3025
701a6d6a
JS		 3026 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3027 return true;
5b5455a9 3028 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 3029 if (handle->port_base_vlan_state !=
3030 HNAE3_PORT_BASE_VLAN_DISABLE)
3031 return false;
3032
701a6d6a 3033 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 3034 return true;
3035 case HNS3_STRP_BOTH:
3036 if (handle->port_base_vlan_state ==
3037 HNAE3_PORT_BASE_VLAN_DISABLE)
3038 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3039 else
3040 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3041
701a6d6a 3042 return true;
5b5455a9 3043 default:
701a6d6a 3044 return false;
5b5455a9 3045 }
5b5455a9
PL		 3046}
3047
8c30e194
YL		 3048static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
3049{
3050 ring->desc[ring->next_to_clean].rx.bd_base_info &=
3051 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
3052 ring->next_to_clean += 1;
3053
3054 if (unlikely(ring->next_to_clean == ring->desc_num))
3055 ring->next_to_clean = 0;
3056}
3057
b9a8f883 3058static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL		 3059 unsigned char *va)
3060{
e5597095 3061 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
c8711956 3062 struct net_device *netdev = ring_to_netdev(ring);
e5597095
PL		 3063 struct sk_buff *skb;
3064
3065 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
3066 skb = ring->skb;
3067 if (unlikely(!skb)) {
b20d7fe5 3068 hns3_rl_err(netdev, "alloc rx skb fail\n");
e5597095
PL		 3069
3070 u64_stats_update_begin(&ring->syncp);
3071 ring->stats.sw_err_cnt++;
3072 u64_stats_update_end(&ring->syncp);
3073
3074 return -ENOMEM;
3075 }
3076
698a8954 3077 trace_hns3_rx_desc(ring);
e5597095
PL		 3078 prefetchw(skb->data);
3079
3080 ring->pending_buf = 1;
81ae0e04
PL		 3081 ring->frag_num = 0;
3082 ring->tail_skb = NULL;
e5597095
PL		 3083 if (length <= HNS3_RX_HEAD_SIZE) {
3084 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
3085
3086 /* We can reuse buffer as-is, just make sure it is local */
08bb3857 3087 if (likely(hns3_page_is_reusable(desc_cb->priv)))
e5597095
PL		 3088 desc_cb->reuse_flag = 1;
3089 else /* This page cannot be reused so discard it */
aeda9bf8
YL		 3090 __page_frag_cache_drain(desc_cb->priv,
3091 desc_cb->pagecnt_bias);
e5597095 3092
8c30e194 3093 hns3_rx_ring_move_fw(ring);
e5597095
PL		 3094 return 0;
3095 }
3096 u64_stats_update_begin(&ring->syncp);
3097 ring->stats.seg_pkt_cnt++;
3098 u64_stats_update_end(&ring->syncp);
3099
c43f1255 3100 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 3101 __skb_put(skb, ring->pull_len);
81ae0e04 3102 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095 3103 desc_cb);
8c30e194 3104 hns3_rx_ring_move_fw(ring);
e5597095 3105
b2598318 3106 return 0;
e5597095
PL		 3107}
3108
b2598318 3109static int hns3_add_frag(struct hns3_enet_ring *ring)
e5597095 3110{
d35bced8
YL		 3111 struct sk_buff *skb = ring->skb;
3112 struct sk_buff *head_skb = skb;
81ae0e04 3113 struct sk_buff *new_skb;
e5597095 3114 struct hns3_desc_cb *desc_cb;
b2598318 3115 struct hns3_desc *desc;
e5597095 3116 u32 bd_base_info;
e5597095 3117
b2598318 3118 do {
e5597095
PL		 3119 desc = &ring->desc[ring->next_to_clean];
3120 desc_cb = &ring->desc_cb[ring->next_to_clean];
3121 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 3122 /* make sure HW write desc complete */
3123 dma_rmb();
e8149933 3124 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 3125 return -ENXIO;
3126
81ae0e04 3127 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
7fda3a93 3128 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
81ae0e04 3129 if (unlikely(!new_skb)) {
c8711956 3130 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5 3131 "alloc rx fraglist skb fail\n");
81ae0e04
PL		 3132 return -ENXIO;
3133 }
3134 ring->frag_num = 0;
3135
3136 if (ring->tail_skb) {
3137 ring->tail_skb->next = new_skb;
3138 ring->tail_skb = new_skb;
3139 } else {
3140 skb_shinfo(skb)->frag_list = new_skb;
3141 ring->tail_skb = new_skb;
3142 }
3143 }
3144
3145 if (ring->tail_skb) {
dbba6da0 3146 head_skb->truesize += hns3_buf_size(ring);
81ae0e04
PL		 3147 head_skb->data_len += le16_to_cpu(desc->rx.size);
3148 head_skb->len += le16_to_cpu(desc->rx.size);
3149 skb = ring->tail_skb;
3150 }
3151
c2a2e127
BS		 3152 dma_sync_single_for_cpu(ring_to_dev(ring),
3153 desc_cb->dma + desc_cb->page_offset,
3154 hns3_buf_size(ring),
3155 DMA_FROM_DEVICE);
3156
81ae0e04 3157 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
698a8954 3158 trace_hns3_rx_desc(ring);
8c30e194 3159 hns3_rx_ring_move_fw(ring);
e5597095 3160 ring->pending_buf++;
b2598318 3161 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
e5597095
PL		 3162
3163 return 0;
3164}
3165
d474d88f
YL		 3166static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
3167 struct sk_buff *skb, u32 l234info,
39c38824 3168 u32 bd_base_info, u32 ol_info)
a6d53b97 3169{
a6d53b97
PL		 3170 u32 l3_type;
3171
e2ee1c5a
YL		 3172 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
3173 HNS3_RXD_GRO_SIZE_M,
3174 HNS3_RXD_GRO_SIZE_S);
a6d53b97 3175 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 3176 if (!skb_shinfo(skb)->gso_size) {
39c38824 3177 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
d474d88f
YL		 3178 return 0;
3179 }
a6d53b97 3180
e2ee1c5a
YL		 3181 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
3182 HNS3_RXD_GRO_COUNT_M,
3183 HNS3_RXD_GRO_COUNT_S);
a6d53b97 3184
9b2f3477 3185 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
a6d53b97
PL		 3186 if (l3_type == HNS3_L3_TYPE_IPV4)
3187 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
3188 else if (l3_type == HNS3_L3_TYPE_IPV6)
3189 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
3190 else
d474d88f 3191 return -EFAULT;
a6d53b97 3192
e2ee1c5a 3193 return hns3_gro_complete(skb, l234info);
a6d53b97
PL		 3194}
3195
232fc64b 3196static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 3197 struct sk_buff *skb, u32 rss_hash)
232fc64b 3198{
232fc64b
PL		 3199 struct hnae3_handle *handle = ring->tqp->handle;
3200 enum pkt_hash_types rss_type;
3201
ea485867 3202 if (rss_hash)
232fc64b
PL		 3203 rss_type = handle->kinfo.rss_type;
3204 else
3205 rss_type = PKT_HASH_TYPE_NONE;
3206
ea485867 3207 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 3208}
3209
ea485867 3210static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e 3211{
c8711956 3212 struct net_device *netdev = ring_to_netdev(ring);
c376fa1a 3213 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 3214 u32 bd_base_info, l234info, ol_info;
ea485867 3215 struct hns3_desc *desc;
d474d88f 3216 unsigned int len;
ea485867
YL		 3217 int pre_ntc, ret;
3218
3219 /* bdinfo handled below is only valid on the last BD of the
3220 * current packet, and ring->next_to_clean indicates the first
3221 * descriptor of next packet, so need - 1 below.
3222 */
3223 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
3224 (ring->desc_num - 1);
3225 desc = &ring->desc[pre_ntc];
3226 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3227 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 3228 ol_info = le32_to_cpu(desc->rx.ol_info);
d474d88f
YL		 3229
3230 /* Based on hw strategy, the tag offloaded will be stored at
3231 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
3232 * in one layer tag case.
3233 */
3234 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3235 u16 vlan_tag;
3236
3237 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
3238 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3239 vlan_tag);
3240 }
3241
d474d88f
YL		 3242 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3243 BIT(HNS3_RXD_L2E_B))))) {
3244 u64_stats_update_begin(&ring->syncp);
3245 if (l234info & BIT(HNS3_RXD_L2E_B))
3246 ring->stats.l2_err++;
3247 else
3248 ring->stats.err_pkt_len++;
3249 u64_stats_update_end(&ring->syncp);
3250
3251 return -EFAULT;
3252 }
3253
3254 len = skb->len;
3255
3256 /* Do update ip stack process */
3257 skb->protocol = eth_type_trans(skb, netdev);
3258
3259 /* This is needed in order to enable forwarding support */
39c38824
YL		 3260 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3261 bd_base_info, ol_info);
d474d88f
YL		 3262 if (unlikely(ret)) {
3263 u64_stats_update_begin(&ring->syncp);
3264 ring->stats.rx_err_cnt++;
3265 u64_stats_update_end(&ring->syncp);
3266 return ret;
3267 }
3268
3269 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3270 HNS3_RXD_DMAC_S);
3271
3272 u64_stats_update_begin(&ring->syncp);
3273 ring->stats.rx_pkts++;
3274 ring->stats.rx_bytes += len;
3275
3276 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3277 ring->stats.rx_multicast++;
3278
3279 u64_stats_update_end(&ring->syncp);
3280
3281 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 3282
3283 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 3284 return 0;
3285}
3286
d35bced8 3287static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
d474d88f 3288{
e5597095 3289 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 3290 struct hns3_desc_cb *desc_cb;
3291 struct hns3_desc *desc;
b9a8f883 3292 unsigned int length;
76ad4f0e 3293 u32 bd_base_info;
e5597095 3294 int ret;
76ad4f0e
S		 3295
3296 desc = &ring->desc[ring->next_to_clean];
3297 desc_cb = &ring->desc_cb[ring->next_to_clean];
3298
3299 prefetch(desc);
3300
8c30e194
YL		 3301 if (!skb) {
3302 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e 3303
8c30e194
YL		 3304 /* Check valid BD */
3305 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3306 return -ENXIO;
3307
3308 dma_rmb();
3309 length = le16_to_cpu(desc->rx.size);
76ad4f0e 3310
cb0e3e61 3311 ring->va = desc_cb->buf + desc_cb->page_offset;
76ad4f0e 3312
c2a2e127
BS		 3313 dma_sync_single_for_cpu(ring_to_dev(ring),
3314 desc_cb->dma + desc_cb->page_offset,
3315 hns3_buf_size(ring),
3316 DMA_FROM_DEVICE);
c2a2e127 3317
8c30e194
YL		 3318 /* Prefetch first cache line of first page.
3319 * Idea is to cache few bytes of the header of the packet.
3320 * Our L1 Cache line size is 64B so need to prefetch twice to make
3321 * it 128B. But in actual we can have greater size of caches with
3322 * 128B Level 1 cache lines. In such a case, single fetch would
3323 * suffice to cache in the relevant part of the header.
3324 */
3325 net_prefetch(ring->va);
76ad4f0e 3326
e5597095 3327 ret = hns3_alloc_skb(ring, length, ring->va);
d35bced8 3328 skb = ring->skb;
76ad4f0e 3329
e5597095
PL		 3330 if (ret < 0) /* alloc buffer fail */
3331 return ret;
b2598318
YL		 3332 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3333 ret = hns3_add_frag(ring);
e5597095
PL		 3334 if (ret)
3335 return ret;
e5597095 3336 }
76ad4f0e 3337 } else {
b2598318 3338 ret = hns3_add_frag(ring);
e5597095
PL		 3339 if (ret)
3340 return ret;
b2598318 3341 }
76ad4f0e 3342
b2598318
YL		 3343 /* As the head data may be changed when GRO enable, copy
3344 * the head data in after other data rx completed
3345 */
3346 if (skb->len > HNS3_RX_HEAD_SIZE)
e5597095
PL		 3347 memcpy(skb->data, ring->va,
3348 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e 3349
ea485867 3350 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 3351 if (unlikely(ret)) {
76ad4f0e 3352 dev_kfree_skb_any(skb);
d474d88f 3353 return ret;
76ad4f0e
S		 3354 }
3355
d93ed94f 3356 skb_record_rx_queue(skb, ring->tqp->tqp_index);
76ad4f0e
S		 3357 return 0;
3358}
3359
9b2f3477
WL		 3360int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3361 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 3362{
3363#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
63380a1a 3364 int unused_count = hns3_desc_unused(ring);
a4ee7624 3365 int recv_pkts = 0;
8c30e194 3366 int err;
76ad4f0e 3367
63380a1a 3368 unused_count -= ring->pending_buf;
76ad4f0e 3369
8c30e194 3370 while (recv_pkts < budget) {
76ad4f0e 3371 /* Reuse or realloc buffers */
a4ee7624
YL		 3372 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3373 hns3_nic_alloc_rx_buffers(ring, unused_count);
e5597095
PL		 3374 unused_count = hns3_desc_unused(ring) -
3375 ring->pending_buf;
76ad4f0e
S		 3376 }
3377
3378 /* Poll one pkt */
d35bced8
YL		 3379 err = hns3_handle_rx_bd(ring);
3380 /* Do not get FE for the packet or failed to alloc skb */
3381 if (unlikely(!ring->skb || err == -ENXIO)) {
76ad4f0e 3382 goto out;
d35bced8
YL		 3383 } else if (likely(!err)) {
3384 rx_fn(ring, ring->skb);
3385 recv_pkts++;
76ad4f0e
S		 3386 }
3387
a4ee7624 3388 unused_count += ring->pending_buf;
e5597095
PL		 3389 ring->skb = NULL;
3390 ring->pending_buf = 0;
76ad4f0e
S		 3391 }
3392
3393out:
3394 /* Make all data has been write before submit */
a4ee7624
YL		 3395 if (unused_count > 0)
3396 hns3_nic_alloc_rx_buffers(ring, unused_count);
76ad4f0e
S		 3397
3398 return recv_pkts;
3399}
3400
4a43caf5 3401static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
76ad4f0e 3402{
4a43caf5
YL		 3403#define HNS3_RX_LOW_BYTE_RATE 10000
3404#define HNS3_RX_MID_BYTE_RATE 20000
3405#define HNS3_RX_ULTRA_PACKET_RATE 40
3406
76ad4f0e 3407 enum hns3_flow_level_range new_flow_level;
4a43caf5
YL		 3408 struct hns3_enet_tqp_vector *tqp_vector;
3409 int packets_per_msecs, bytes_per_msecs;
a95e1f86 3410 u32 time_passed_ms;
76ad4f0e 3411
4a43caf5 3412 tqp_vector = ring_group->ring->tqp_vector;
a95e1f86
FL		 3413 time_passed_ms =
3414 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
a95e1f86
FL		 3415 if (!time_passed_ms)
3416 return false;
3417
3418 do_div(ring_group->total_packets, time_passed_ms);
3419 packets_per_msecs = ring_group->total_packets;
3420
3421 do_div(ring_group->total_bytes, time_passed_ms);
3422 bytes_per_msecs = ring_group->total_bytes;
3423
4a43caf5 3424 new_flow_level = ring_group->coal.flow_level;
76ad4f0e 3425
4a43caf5
YL		 3426 /* Simple throttlerate management
3427 * 0-10MB/s lower (50000 ints/s)
3428 * 10-20MB/s middle (20000 ints/s)
3429 * 20-1249MB/s high (18000 ints/s)
3430 * > 40000pps ultra (8000 ints/s)
3431 */
76ad4f0e
S		 3432 switch (new_flow_level) {
3433 case HNS3_FLOW_LOW:
a95e1f86 3434 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 3435 new_flow_level = HNS3_FLOW_MID;
3436 break;
3437 case HNS3_FLOW_MID:
a95e1f86 3438 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 3439 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 3440 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 3441 new_flow_level = HNS3_FLOW_LOW;
3442 break;
3443 case HNS3_FLOW_HIGH:
3444 case HNS3_FLOW_ULTRA:
3445 default:
a95e1f86 3446 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 3447 new_flow_level = HNS3_FLOW_MID;
3448 break;
3449 }
3450
a95e1f86
FL		 3451 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3452 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 3453 new_flow_level = HNS3_FLOW_ULTRA;
3454
4a43caf5
YL		 3455 ring_group->total_bytes = 0;
3456 ring_group->total_packets = 0;
3457 ring_group->coal.flow_level = new_flow_level;
3458
3459 return true;
3460}
3461
3462static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3463{
3464 struct hns3_enet_tqp_vector *tqp_vector;
3465 u16 new_int_gl;
3466
3467 if (!ring_group->ring)
3468 return false;
3469
3470 tqp_vector = ring_group->ring->tqp_vector;
3471 if (!tqp_vector->last_jiffies)
3472 return false;
3473
3474 if (ring_group->total_packets == 0) {
3475 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3476 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3477 return true;
3478 }
3479
3480 if (!hns3_get_new_flow_lvl(ring_group))
3481 return false;
3482
3483 new_int_gl = ring_group->coal.int_gl;
3484 switch (ring_group->coal.flow_level) {
76ad4f0e
S		 3485 case HNS3_FLOW_LOW:
3486 new_int_gl = HNS3_INT_GL_50K;
3487 break;
3488 case HNS3_FLOW_MID:
3489 new_int_gl = HNS3_INT_GL_20K;
3490 break;
3491 case HNS3_FLOW_HIGH:
3492 new_int_gl = HNS3_INT_GL_18K;
3493 break;
3494 case HNS3_FLOW_ULTRA:
3495 new_int_gl = HNS3_INT_GL_8K;
3496 break;
3497 default:
3498 break;
3499 }
3500
9bc727a9
YL		 3501 if (new_int_gl != ring_group->coal.int_gl) {
3502 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 3503 return true;
3504 }
3505 return false;
3506}
3507
3508static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3509{
8b1ff1ea
FL		 3510 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3511 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3512 bool rx_update, tx_update;
3513
7445565c
PL		 3514 /* update param every 1000ms */
3515 if (time_before(jiffies,
3516 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3517 return;
cd9d187b 3518
de25bcc4 3519 if (rx_group->coal.adapt_enable) {
8b1ff1ea
FL		 3520 rx_update = hns3_get_new_int_gl(rx_group);
3521 if (rx_update)
3522 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3523 rx_group->coal.int_gl);
8b1ff1ea
FL		 3524 }
3525
de25bcc4 3526 if (tx_group->coal.adapt_enable) {
9e50dc11 3527 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL		 3528 if (tx_update)
3529 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3530 tx_group->coal.int_gl);
76ad4f0e 3531 }
cd9d187b 3532
a95e1f86 3533 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 3534}
3535
3536static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3537{
ff0699e0 3538 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 3539 struct hns3_enet_ring *ring;
3540 int rx_pkt_total = 0;
3541
3542 struct hns3_enet_tqp_vector *tqp_vector =
3543 container_of(napi, struct hns3_enet_tqp_vector, napi);
3544 bool clean_complete = true;
ceca4a5e 3545 int rx_budget = budget;
76ad4f0e 3546
ff0699e0
HT		 3547 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3548 napi_complete(napi);
3549 return 0;
3550 }
3551
76ad4f0e
S		 3552 /* Since the actual Tx work is minimal, we can give the Tx a larger
3553 * budget and be more aggressive about cleaning up the Tx descriptors.
3554 */
799997a3 3555 hns3_for_each_ring(ring, tqp_vector->tx_group)
619ae331 3556 hns3_clean_tx_ring(ring, budget);
76ad4f0e
S		 3557
3558 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 3559 if (tqp_vector->num_tqps > 1)
3560 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 3561
3562 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 3563 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3564 hns3_rx_skb);
76ad4f0e
S		 3565
3566 if (rx_cleaned >= rx_budget)
3567 clean_complete = false;
3568
3569 rx_pkt_total += rx_cleaned;
3570 }
3571
3572 tqp_vector->rx_group.total_packets += rx_pkt_total;
3573
3574 if (!clean_complete)
3575 return budget;
3576
531eba0f
HT		 3577 if (napi_complete(napi) &&
3578 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 3579 hns3_update_new_int_gl(tqp_vector);
3580 hns3_mask_vector_irq(tqp_vector, 1);
3581 }
76ad4f0e
S		 3582
3583 return rx_pkt_total;
3584}
3585
3586static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3587 struct hnae3_ring_chain_node *head)
3588{
3589 struct pci_dev *pdev = tqp_vector->handle->pdev;
3590 struct hnae3_ring_chain_node *cur_chain = head;
3591 struct hnae3_ring_chain_node *chain;
3592 struct hns3_enet_ring *tx_ring;
3593 struct hns3_enet_ring *rx_ring;
3594
3595 tx_ring = tqp_vector->tx_group.ring;
3596 if (tx_ring) {
3597 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3598 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3599 HNAE3_RING_TYPE_TX);
3600 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3601 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 3602
3603 cur_chain->next = NULL;
3604
3605 while (tx_ring->next) {
3606 tx_ring = tx_ring->next;
3607
3608 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3609 GFP_KERNEL);
3610 if (!chain)
73b907a0 3611 goto err_free_chain;
76ad4f0e
S		 3612
3613 cur_chain->next = chain;
3614 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3615 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3616 HNAE3_RING_TYPE_TX);
3617 hnae3_set_field(chain->int_gl_idx,
3618 HNAE3_RING_GL_IDX_M,
3619 HNAE3_RING_GL_IDX_S,
3620 HNAE3_RING_GL_TX);
76ad4f0e
S		 3621
3622 cur_chain = chain;
3623 }
3624 }
3625
3626 rx_ring = tqp_vector->rx_group.ring;
3627 if (!tx_ring && rx_ring) {
3628 cur_chain->next = NULL;
3629 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3630 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3631 HNAE3_RING_TYPE_RX);
3632 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3633 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 3634
3635 rx_ring = rx_ring->next;
3636 }
3637
3638 while (rx_ring) {
3639 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3640 if (!chain)
73b907a0 3641 goto err_free_chain;
76ad4f0e
S		 3642
3643 cur_chain->next = chain;
3644 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3645 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3646 HNAE3_RING_TYPE_RX);
3647 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3648 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3649
76ad4f0e
S		 3650 cur_chain = chain;
3651
3652 rx_ring = rx_ring->next;
3653 }
3654
3655 return 0;
73b907a0
HT		 3656
3657err_free_chain:
3658 cur_chain = head->next;
3659 while (cur_chain) {
3660 chain = cur_chain->next;
cda69d24 3661 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 3662 cur_chain = chain;
3663 }
cda69d24 3664 head->next = NULL;
73b907a0
HT		 3665
3666 return -ENOMEM;
76ad4f0e
S		 3667}
3668
3669static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3670 struct hnae3_ring_chain_node *head)
3671{
3672 struct pci_dev *pdev = tqp_vector->handle->pdev;
3673 struct hnae3_ring_chain_node *chain_tmp, *chain;
3674
3675 chain = head->next;
3676
3677 while (chain) {
3678 chain_tmp = chain->next;
3679 devm_kfree(&pdev->dev, chain);
3680 chain = chain_tmp;
3681 }
3682}
3683
3684static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3685 struct hns3_enet_ring *ring)
3686{
3687 ring->next = group->ring;
3688 group->ring = ring;
3689
3690 group->count++;
3691}
3692
874bff0b
PL		 3693static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3694{
3695 struct pci_dev *pdev = priv->ae_handle->pdev;
3696 struct hns3_enet_tqp_vector *tqp_vector;
3697 int num_vectors = priv->vector_num;
3698 int numa_node;
3699 int vector_i;
3700
3701 numa_node = dev_to_node(&pdev->dev);
3702
3703 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3704 tqp_vector = &priv->tqp_vector[vector_i];
3705 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3706 &tqp_vector->affinity_mask);
3707 }
3708}
3709
76ad4f0e
S		 3710static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3711{
3712 struct hnae3_ring_chain_node vector_ring_chain;
3713 struct hnae3_handle *h = priv->ae_handle;
3714 struct hns3_enet_tqp_vector *tqp_vector;
9d8d5a36 3715 int ret;
ece4bf46 3716 int i;
76ad4f0e 3717
874bff0b
PL		 3718 hns3_nic_set_cpumask(priv);
3719
dd38c726
YL		 3720 for (i = 0; i < priv->vector_num; i++) {
3721 tqp_vector = &priv->tqp_vector[i];
91bfae25 3722 hns3_vector_coalesce_init_hw(tqp_vector, priv);
dd38c726
YL		 3723 tqp_vector->num_tqps = 0;
3724 }
76ad4f0e 3725
dd38c726
YL		 3726 for (i = 0; i < h->kinfo.num_tqps; i++) {
3727 u16 vector_i = i % priv->vector_num;
3728 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3729
3730 tqp_vector = &priv->tqp_vector[vector_i];
3731
3732 hns3_add_ring_to_group(&tqp_vector->tx_group,
5f06b903 3733 &priv->ring[i]);
76ad4f0e
S		 3734
3735 hns3_add_ring_to_group(&tqp_vector->rx_group,
5f06b903 3736 &priv->ring[i + tqp_num]);
76ad4f0e 3737
5f06b903
YL		 3738 priv->ring[i].tqp_vector = tqp_vector;
3739 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
dd38c726 3740 tqp_vector->num_tqps++;
76ad4f0e
S		 3741 }
3742
dd38c726 3743 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3744 tqp_vector = &priv->tqp_vector[i];
3745
3746 tqp_vector->rx_group.total_bytes = 0;
3747 tqp_vector->rx_group.total_packets = 0;
3748 tqp_vector->tx_group.total_bytes = 0;
3749 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3750 tqp_vector->handle = h;
3751
3752 ret = hns3_get_vector_ring_chain(tqp_vector,
3753 &vector_ring_chain);
3754 if (ret)
cda69d24 3755 goto map_ring_fail;
76ad4f0e
S		 3756
3757 ret = h->ae_algo->ops->map_ring_to_vector(h,
3758 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3759
3760 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3761
dd38c726 3762 if (ret)
ece4bf46 3763 goto map_ring_fail;
dd38c726 3764
76ad4f0e
S		 3765 netif_napi_add(priv->netdev, &tqp_vector->napi,
3766 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3767 }
3768
dd38c726 3769 return 0;
ece4bf46
HT		 3770
3771map_ring_fail:
3772 while (i--)
3773 netif_napi_del(&priv->tqp_vector[i].napi);
3774
3775 return ret;
dd38c726
YL		 3776}
3777
3778static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3779{
3780 struct hnae3_handle *h = priv->ae_handle;
3781 struct hns3_enet_tqp_vector *tqp_vector;
3782 struct hnae3_vector_info *vector;
3783 struct pci_dev *pdev = h->pdev;
3784 u16 tqp_num = h->kinfo.num_tqps;
3785 u16 vector_num;
3786 int ret = 0;
3787 u16 i;
3788
3789 /* RSS size, cpu online and vector_num should be the same */
3790 /* Should consider 2p/4p later */
3791 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610 3792
dd38c726
YL		 3793 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3794 GFP_KERNEL);
3795 if (!vector)
3796 return -ENOMEM;
3797
9b2f3477 3798 /* save the actual available vector number */
dd38c726
YL		 3799 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3800
3801 priv->vector_num = vector_num;
3802 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3803 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3804 GFP_KERNEL);
3805 if (!priv->tqp_vector) {
3806 ret = -ENOMEM;
3807 goto out;
3808 }
3809
3810 for (i = 0; i < priv->vector_num; i++) {
3811 tqp_vector = &priv->tqp_vector[i];
3812 tqp_vector->idx = i;
3813 tqp_vector->mask_addr = vector[i].io_addr;
3814 tqp_vector->vector_irq = vector[i].vector;
91bfae25 3815 hns3_vector_coalesce_init(tqp_vector, priv);
dd38c726
YL		 3816 }
3817
76ad4f0e
S		 3818out:
3819 devm_kfree(&pdev->dev, vector);
3820 return ret;
3821}
3822
dd38c726
YL		 3823static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3824{
3825 group->ring = NULL;
3826 group->count = 0;
3827}
3828
e2152785 3829static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 3830{
3831 struct hnae3_ring_chain_node vector_ring_chain;
3832 struct hnae3_handle *h = priv->ae_handle;
3833 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3834 int i;
76ad4f0e
S		 3835
3836 for (i = 0; i < priv->vector_num; i++) {
3837 tqp_vector = &priv->tqp_vector[i];
3838
2c9dd668
HT		 3839 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3840 continue;
3841
ff7dfcdd
HT		 3842 /* Since the mapping can be overwritten, when fail to get the
3843 * chain between vector and ring, we should go on to deal with
3844 * the remaining options.
3845 */
3846 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3847 dev_warn(priv->dev, "failed to get ring chain\n");
76ad4f0e 3848
e2152785 3849 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3850 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3851
3852 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3853
dd38c726
YL		 3854 hns3_clear_ring_group(&tqp_vector->rx_group);
3855 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3856 netif_napi_del(&priv->tqp_vector[i].napi);
3857 }
dd38c726
YL		 3858}
3859
08a10068 3860static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
dd38c726
YL		 3861{
3862 struct hnae3_handle *h = priv->ae_handle;
3863 struct pci_dev *pdev = h->pdev;
3864 int i, ret;
3865
3866 for (i = 0; i < priv->vector_num; i++) {
3867 struct hns3_enet_tqp_vector *tqp_vector;
3868
3869 tqp_vector = &priv->tqp_vector[i];
3870 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3871 if (ret)
08a10068 3872 return;
dd38c726 3873 }
76ad4f0e 3874
dd38c726 3875 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3876}
3877
5f06b903
YL		 3878static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3879 unsigned int ring_type)
76ad4f0e 3880{
76ad4f0e 3881 int queue_num = priv->ae_handle->kinfo.num_tqps;
76ad4f0e 3882 struct hns3_enet_ring *ring;
c0425944 3883 int desc_num;
76ad4f0e 3884
76ad4f0e 3885 if (ring_type == HNAE3_RING_TYPE_TX) {
5f06b903 3886 ring = &priv->ring[q->tqp_index];
c0425944 3887 desc_num = priv->ae_handle->kinfo.num_tx_desc;
5f06b903 3888 ring->queue_index = q->tqp_index;
76ad4f0e 3889 } else {
5f06b903 3890 ring = &priv->ring[q->tqp_index + queue_num];
c0425944 3891 desc_num = priv->ae_handle->kinfo.num_rx_desc;
5f06b903 3892 ring->queue_index = q->tqp_index;
76ad4f0e
S		 3893 }
3894
e4e87715 3895 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3896
76ad4f0e
S		 3897 ring->tqp = q;
3898 ring->desc = NULL;
3899 ring->desc_cb = NULL;
3900 ring->dev = priv->dev;
3901 ring->desc_dma_addr = 0;
3902 ring->buf_size = q->buf_size;
2c9dd668 3903 ring->desc_num = desc_num;
76ad4f0e
S		 3904 ring->next_to_use = 0;
3905 ring->next_to_clean = 0;
20d06ca2 3906 ring->last_to_use = 0;
76ad4f0e
S		 3907}
3908
5f06b903
YL		 3909static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3910 struct hns3_nic_priv *priv)
76ad4f0e 3911{
5f06b903
YL		 3912 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3913 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
76ad4f0e
S		 3914}
3915
3916static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3917{
3918 struct hnae3_handle *h = priv->ae_handle;
3919 struct pci_dev *pdev = h->pdev;
5f06b903 3920 int i;
76ad4f0e 3921
5f06b903
YL		 3922 priv->ring = devm_kzalloc(&pdev->dev,
3923 array3_size(h->kinfo.num_tqps,
3924 sizeof(*priv->ring), 2),
3925 GFP_KERNEL);
3926 if (!priv->ring)
76ad4f0e
S		 3927 return -ENOMEM;
3928
5f06b903
YL		 3929 for (i = 0; i < h->kinfo.num_tqps; i++)
3930 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
76ad4f0e
S		 3931
3932 return 0;
76ad4f0e
S		 3933}
3934
09f2af64
PL		 3935static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3936{
5f06b903 3937 if (!priv->ring)
7b8f622e
HT		 3938 return;
3939
5f06b903
YL		 3940 devm_kfree(priv->dev, priv->ring);
3941 priv->ring = NULL;
09f2af64
PL		 3942}
3943
76ad4f0e
S		 3944static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3945{
3946 int ret;
3947
3948 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3949 return -EINVAL;
3950
77296bf6
YL		 3951 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3952 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 3953 if (!ring->desc_cb) {
3954 ret = -ENOMEM;
3955 goto out;
3956 }
3957
3958 ret = hns3_alloc_desc(ring);
3959 if (ret)
3960 goto out_with_desc_cb;
3961
3962 if (!HNAE3_IS_TX_RING(ring)) {
3963 ret = hns3_alloc_ring_buffers(ring);
3964 if (ret)
3965 goto out_with_desc;
3966 }
3967
3968 return 0;
3969
3970out_with_desc:
3971 hns3_free_desc(ring);
3972out_with_desc_cb:
77296bf6 3973 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3974 ring->desc_cb = NULL;
3975out:
3976 return ret;
3977}
3978
a723fb8e 3979void hns3_fini_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 3980{
3981 hns3_free_desc(ring);
77296bf6 3982 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3983 ring->desc_cb = NULL;
3984 ring->next_to_clean = 0;
3985 ring->next_to_use = 0;
20d06ca2 3986 ring->last_to_use = 0;
ac574b80
PL		 3987 ring->pending_buf = 0;
3988 if (ring->skb) {
3989 dev_kfree_skb_any(ring->skb);
3990 ring->skb = NULL;
3991 }
76ad4f0e
S		 3992}
3993
1db9b1bf 3994static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3995{
3996 int bd_size_type;
3997
3998 switch (buf_size) {
3999 case 512:
4000 bd_size_type = HNS3_BD_SIZE_512_TYPE;
4001 break;
4002 case 1024:
4003 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
4004 break;
4005 case 2048:
4006 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4007 break;
4008 case 4096:
4009 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
4010 break;
4011 default:
4012 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4013 }
4014
4015 return bd_size_type;
4016}
4017
4018static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
4019{
4020 dma_addr_t dma = ring->desc_dma_addr;
4021 struct hnae3_queue *q = ring->tqp;
4022
4023 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 4024 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S		 4025 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
4026 (u32)((dma >> 31) >> 1));
4027
4028 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
4029 hns3_buf_size2type(ring->buf_size));
4030 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
4031 ring->desc_num / 8 - 1);
4032
4033 } else {
4034 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
4035 (u32)dma);
4036 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
4037 (u32)((dma >> 31) >> 1));
4038
76ad4f0e
S		 4039 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
4040 ring->desc_num / 8 - 1);
4041 }
4042}
4043
1c772154
YL		 4044static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
4045{
4046 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
35244430 4047 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
1c772154
YL		 4048 int i;
4049
4050 for (i = 0; i < HNAE3_MAX_TC; i++) {
1c772154
YL		 4051 int j;
4052
35244430 4053 if (!test_bit(i, &tc_info->tc_en))
1c772154
YL		 4054 continue;
4055
35244430 4056 for (j = 0; j < tc_info->tqp_count[i]; j++) {
1c772154
YL		 4057 struct hnae3_queue *q;
4058
35244430
JS		 4059 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
4060 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
1c772154
YL		 4061 }
4062 }
4063}
4064
5668abda 4065int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 4066{
4067 struct hnae3_handle *h = priv->ae_handle;
4068 int ring_num = h->kinfo.num_tqps * 2;
4069 int i, j;
4070 int ret;
4071
4072 for (i = 0; i < ring_num; i++) {
5f06b903 4073 ret = hns3_alloc_ring_memory(&priv->ring[i]);
76ad4f0e
S		 4074 if (ret) {
4075 dev_err(priv->dev,
4076 "Alloc ring memory fail! ret=%d\n", ret);
4077 goto out_when_alloc_ring_memory;
4078 }
4079
5f06b903 4080 u64_stats_init(&priv->ring[i].syncp);
76ad4f0e
S		 4081 }
4082
4083 return 0;
4084
4085out_when_alloc_ring_memory:
4086 for (j = i - 1; j >= 0; j--)
5f06b903 4087 hns3_fini_ring(&priv->ring[j]);
76ad4f0e
S		 4088
4089 return -ENOMEM;
4090}
4091
5668abda 4092int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 4093{
4094 struct hnae3_handle *h = priv->ae_handle;
4095 int i;
4096
4097 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903
YL		 4098 hns3_fini_ring(&priv->ring[i]);
4099 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
76ad4f0e 4100 }
76ad4f0e
S		 4101 return 0;
4102}
4103
4104/* Set mac addr if it is configured. or leave it to the AE driver */
8e6de441 4105static int hns3_init_mac_addr(struct net_device *netdev)
76ad4f0e
S		 4106{
4107 struct hns3_nic_priv *priv = netdev_priv(netdev);
4108 struct hnae3_handle *h = priv->ae_handle;
4109 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 4110 int ret = 0;
76ad4f0e 4111
8e6de441 4112 if (h->ae_algo->ops->get_mac_addr)
76ad4f0e 4113 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
76ad4f0e
S		 4114
4115 /* Check if the MAC address is valid, if not get a random one */
8e6de441 4116 if (!is_valid_ether_addr(mac_addr_temp)) {
76ad4f0e
S		 4117 eth_hw_addr_random(netdev);
4118 dev_warn(priv->dev, "using random MAC address %pM\n",
4119 netdev->dev_addr);
ee4bcd3b 4120 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
8e6de441
HT		 4121 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
4122 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
ee4bcd3b
JS		 4123 } else {
4124 return 0;
76ad4f0e 4125 }
139e8792
L		 4126
4127 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 4128 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 4129
7fa6be4f 4130 return ret;
76ad4f0e
S		 4131}
4132
c8a8045b
HT		 4133static int hns3_init_phy(struct net_device *netdev)
4134{
4135 struct hnae3_handle *h = hns3_get_handle(netdev);
4136 int ret = 0;
4137
4138 if (h->ae_algo->ops->mac_connect_phy)
4139 ret = h->ae_algo->ops->mac_connect_phy(h);
4140
4141 return ret;
4142}
4143
4144static void hns3_uninit_phy(struct net_device *netdev)
4145{
4146 struct hnae3_handle *h = hns3_get_handle(netdev);
4147
4148 if (h->ae_algo->ops->mac_disconnect_phy)
4149 h->ae_algo->ops->mac_disconnect_phy(h);
4150}
4151
6871af29
JS		 4152static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
4153{
4154 struct hnae3_handle *h = hns3_get_handle(netdev);
4155
4156 if (h->ae_algo->ops->del_all_fd_entries)
4157 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
4158}
4159
a6d818e3
YL		 4160static int hns3_client_start(struct hnae3_handle *handle)
4161{
4162 if (!handle->ae_algo->ops->client_start)
4163 return 0;
4164
4165 return handle->ae_algo->ops->client_start(handle);
4166}
4167
4168static void hns3_client_stop(struct hnae3_handle *handle)
4169{
4170 if (!handle->ae_algo->ops->client_stop)
4171 return;
4172
4173 handle->ae_algo->ops->client_stop(handle);
4174}
4175
bb87be87
YL		 4176static void hns3_info_show(struct hns3_nic_priv *priv)
4177{
4178 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
4179
4180 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
adcf738b
GL		 4181 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
4182 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
4183 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
4184 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
4185 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
4186 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
35244430
JS		 4187 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
4188 kinfo->tc_info.num_tc);
adcf738b 4189 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
bb87be87
YL		 4190}
4191
76ad4f0e
S		 4192static int hns3_client_init(struct hnae3_handle *handle)
4193{
4194 struct pci_dev *pdev = handle->pdev;
fd665b3d 4195 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
0d43bf45 4196 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 4197 struct hns3_nic_priv *priv;
4198 struct net_device *netdev;
4199 int ret;
4200
0d43bf45
HT		 4201 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
4202 &max_rss_size);
4203 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 4204 if (!netdev)
4205 return -ENOMEM;
4206
4207 priv = netdev_priv(netdev);
4208 priv->dev = &pdev->dev;
4209 priv->netdev = netdev;
4210 priv->ae_handle = handle;
f8fa222c 4211 priv->tx_timeout_count = 0;
fd665b3d 4212 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
b7b585c2 4213 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 4214
bb87be87
YL		 4215 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
4216
76ad4f0e
S		 4217 handle->kinfo.netdev = netdev;
4218 handle->priv = (void *)priv;
4219
8e6de441 4220 hns3_init_mac_addr(netdev);
76ad4f0e
S		 4221
4222 hns3_set_default_feature(netdev);
4223
4224 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
4225 netdev->priv_flags |= IFF_UNICAST_FLT;
4226 netdev->netdev_ops = &hns3_nic_netdev_ops;
4227 SET_NETDEV_DEV(netdev, &pdev->dev);
4228 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 4229
4230 /* Carrier off reporting is important to ethtool even BEFORE open */
4231 netif_carrier_off(netdev);
4232
4233 ret = hns3_get_ring_config(priv);
4234 if (ret) {
4235 ret = -ENOMEM;
4236 goto out_get_ring_cfg;
4237 }
4238
dd38c726
YL		 4239 ret = hns3_nic_alloc_vector_data(priv);
4240 if (ret) {
4241 ret = -ENOMEM;
4242 goto out_alloc_vector_data;
4243 }
4244
76ad4f0e
S		 4245 ret = hns3_nic_init_vector_data(priv);
4246 if (ret) {
4247 ret = -ENOMEM;
4248 goto out_init_vector_data;
4249 }
4250
4251 ret = hns3_init_all_ring(priv);
4252 if (ret) {
4253 ret = -ENOMEM;
5f06b903 4254 goto out_init_ring;
76ad4f0e
S		 4255 }
4256
c8a8045b
HT		 4257 ret = hns3_init_phy(netdev);
4258 if (ret)
4259 goto out_init_phy;
4260
76ad4f0e
S		 4261 ret = register_netdev(netdev);
4262 if (ret) {
4263 dev_err(priv->dev, "probe register netdev fail!\n");
4264 goto out_reg_netdev_fail;
4265 }
4266
08a10068
YL		 4267 /* the device can work without cpu rmap, only aRFS needs it */
4268 ret = hns3_set_rx_cpu_rmap(netdev);
4269 if (ret)
4270 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4271
4272 ret = hns3_nic_init_irq(priv);
4273 if (ret) {
4274 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4275 hns3_free_rx_cpu_rmap(netdev);
4276 goto out_init_irq_fail;
4277 }
4278
a6d818e3
YL		 4279 ret = hns3_client_start(handle);
4280 if (ret) {
4281 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 4282 goto out_client_start;
a6d818e3
YL		 4283 }
4284
986743db
YL		 4285 hns3_dcbnl_setup(handle);
4286
b2292360 4287 hns3_dbg_init(handle);
4288
a0b43717 4289 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 4290 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 4291
66d52f3b
HT		 4292 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
4293 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
4294
814da63c
HT		 4295 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4296
5e7414cd
JS		 4297 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
4298 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
4299
bb87be87
YL		 4300 if (netif_msg_drv(handle))
4301 hns3_info_show(priv);
4302
76ad4f0e
S		 4303 return ret;
4304
18655128 4305out_client_start:
08a10068
YL		 4306 hns3_free_rx_cpu_rmap(netdev);
4307 hns3_nic_uninit_irq(priv);
4308out_init_irq_fail:
18655128 4309 unregister_netdev(netdev);
76ad4f0e 4310out_reg_netdev_fail:
c8a8045b
HT		 4311 hns3_uninit_phy(netdev);
4312out_init_phy:
4313 hns3_uninit_all_ring(priv);
5f06b903 4314out_init_ring:
e2152785 4315 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4316out_init_vector_data:
dd38c726
YL		 4317 hns3_nic_dealloc_vector_data(priv);
4318out_alloc_vector_data:
5f06b903 4319 priv->ring = NULL;
76ad4f0e
S		 4320out_get_ring_cfg:
4321 priv->ae_handle = NULL;
4322 free_netdev(netdev);
4323 return ret;
4324}
4325
4326static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4327{
4328 struct net_device *netdev = handle->kinfo.netdev;
4329 struct hns3_nic_priv *priv = netdev_priv(netdev);
4330 int ret;
4331
4332 if (netdev->reg_state != NETREG_UNINITIALIZED)
4333 unregister_netdev(netdev);
4334
eb32c896
HT		 4335 hns3_client_stop(handle);
4336
0d2f68c7
HT		 4337 hns3_uninit_phy(netdev);
4338
814da63c
HT		 4339 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4340 netdev_warn(netdev, "already uninitialized\n");
4341 goto out_netdev_free;
4342 }
4343
08a10068
YL		 4344 hns3_free_rx_cpu_rmap(netdev);
4345
4346 hns3_nic_uninit_irq(priv);
4347
dc5e6064
JS		 4348 hns3_del_all_fd_rules(netdev, true);
4349
f96315f2 4350 hns3_clear_all_ring(handle, true);
7b763f3f 4351
e2152785 4352 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4353
08a10068 4354 hns3_nic_dealloc_vector_data(priv);
dd38c726 4355
76ad4f0e
S		 4356 ret = hns3_uninit_all_ring(priv);
4357 if (ret)
4358 netdev_err(netdev, "uninit ring error\n");
4359
ec777890
YL		 4360 hns3_put_ring_config(priv);
4361
814da63c 4362out_netdev_free:
e22b5e72 4363 hns3_dbg_uninit(handle);
76ad4f0e
S		 4364 free_netdev(netdev);
4365}
4366
4367static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4368{
4369 struct net_device *netdev = handle->kinfo.netdev;
4370
4371 if (!netdev)
4372 return;
4373
4374 if (linkup) {
76ad4f0e 4375 netif_tx_wake_all_queues(netdev);
a7e90ee5 4376 netif_carrier_on(netdev);
bb87be87
YL		 4377 if (netif_msg_link(handle))
4378 netdev_info(netdev, "link up\n");
76ad4f0e
S		 4379 } else {
4380 netif_carrier_off(netdev);
4381 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 4382 if (netif_msg_link(handle))
4383 netdev_info(netdev, "link down\n");
76ad4f0e
S		 4384 }
4385}
4386
9df8f79a
YL		 4387static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4388{
4389 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4390 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL		 4391
4392 if (tc > HNAE3_MAX_TC)
4393 return -EINVAL;
4394
4395 if (!ndev)
4396 return -ENODEV;
4397
a1ef124e 4398 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL		 4399}
4400
beebca3a 4401static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 4402{
beebca3a 4403 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 4404 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
619ae331 4405 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
beebca3a
YL		 4406 ring_ptr_move_fw(ring, next_to_clean);
4407 }
f6061a05
YL		 4408
4409 ring->pending_buf = 0;
beebca3a
YL		 4410}
4411
7b763f3f
FL		 4412static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4413{
4414 struct hns3_desc_cb res_cbs;
4415 int ret;
4416
4417 while (ring->next_to_use != ring->next_to_clean) {
4418 /* When a buffer is not reused, it's memory has been
4419 * freed in hns3_handle_rx_bd or will be freed by
4420 * stack, so we need to replace the buffer here.
4421 */
4422 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4d2cad32 4423 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
7b763f3f
FL		 4424 if (ret) {
4425 u64_stats_update_begin(&ring->syncp);
4426 ring->stats.sw_err_cnt++;
4427 u64_stats_update_end(&ring->syncp);
4428 /* if alloc new buffer fail, exit directly
4429 * and reclear in up flow.
4430 */
c8711956 4431 netdev_warn(ring_to_netdev(ring),
7b763f3f
FL		 4432 "reserve buffer map failed, ret = %d\n",
4433 ret);
4434 return ret;
4435 }
9b2f3477 4436 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL		 4437 }
4438 ring_ptr_move_fw(ring, next_to_use);
4439 }
4440
cc5ff6e9
PL		 4441 /* Free the pending skb in rx ring */
4442 if (ring->skb) {
4443 dev_kfree_skb_any(ring->skb);
4444 ring->skb = NULL;
4445 ring->pending_buf = 0;
4446 }
4447
7b763f3f
FL		 4448 return 0;
4449}
4450
4451static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4452{
beebca3a
YL		 4453 while (ring->next_to_use != ring->next_to_clean) {
4454 /* When a buffer is not reused, it's memory has been
4455 * freed in hns3_handle_rx_bd or will be freed by
4456 * stack, so only need to unmap the buffer here.
4457 */
4458 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4459 hns3_unmap_buffer(ring,
4460 &ring->desc_cb[ring->next_to_use]);
4461 ring->desc_cb[ring->next_to_use].dma = 0;
4462 }
4463
4464 ring_ptr_move_fw(ring, next_to_use);
4465 }
bb6b94a8
L		 4466}
4467
f96315f2 4468static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L		 4469{
4470 struct net_device *ndev = h->kinfo.netdev;
4471 struct hns3_nic_priv *priv = netdev_priv(ndev);
4472 u32 i;
4473
4474 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L		 4475 struct hns3_enet_ring *ring;
4476
5f06b903 4477 ring = &priv->ring[i];
beebca3a 4478 hns3_clear_tx_ring(ring);
bb6b94a8 4479
5f06b903 4480 ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 4481 /* Continue to clear other rings even if clearing some
4482 * rings failed.
4483 */
f96315f2
HT		 4484 if (force)
4485 hns3_force_clear_rx_ring(ring);
4486 else
4487 hns3_clear_rx_ring(ring);
bb6b94a8
L		 4488 }
4489}
4490
7b763f3f
FL		 4491int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4492{
4493 struct net_device *ndev = h->kinfo.netdev;
4494 struct hns3_nic_priv *priv = netdev_priv(ndev);
4495 struct hns3_enet_ring *rx_ring;
4496 int i, j;
4497 int ret;
4498
4499 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 4500 ret = h->ae_algo->ops->reset_queue(h, i);
4501 if (ret)
4502 return ret;
4503
5f06b903 4504 hns3_init_ring_hw(&priv->ring[i]);
7b763f3f
FL		 4505
4506 /* We need to clear tx ring here because self test will
4507 * use the ring and will not run down before up
4508 */
5f06b903
YL		 4509 hns3_clear_tx_ring(&priv->ring[i]);
4510 priv->ring[i].next_to_clean = 0;
4511 priv->ring[i].next_to_use = 0;
20d06ca2 4512 priv->ring[i].last_to_use = 0;
7b763f3f 4513
5f06b903 4514 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 4515 hns3_init_ring_hw(rx_ring);
4516 ret = hns3_clear_rx_ring(rx_ring);
4517 if (ret)
4518 return ret;
4519
4520 /* We can not know the hardware head and tail when this
4521 * function is called in reset flow, so we reuse all desc.
4522 */
4523 for (j = 0; j < rx_ring->desc_num; j++)
4524 hns3_reuse_buffer(rx_ring, j);
4525
4526 rx_ring->next_to_clean = 0;
4527 rx_ring->next_to_use = 0;
4528 }
4529
1c772154
YL		 4530 hns3_init_tx_ring_tc(priv);
4531
7b763f3f
FL		 4532 return 0;
4533}
4534
e4fd7502
HT		 4535static void hns3_store_coal(struct hns3_nic_priv *priv)
4536{
4537 /* ethtool only support setting and querying one coal
46ee7350
GL		 4538 * configuration for now, so save the vector 0' coal
4539 * configuration here in order to restore it.
e4fd7502
HT		 4540 */
4541 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4542 sizeof(struct hns3_enet_coalesce));
4543 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4544 sizeof(struct hns3_enet_coalesce));
4545}
4546
4547static void hns3_restore_coal(struct hns3_nic_priv *priv)
4548{
4549 u16 vector_num = priv->vector_num;
4550 int i;
4551
4552 for (i = 0; i < vector_num; i++) {
4553 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4554 sizeof(struct hns3_enet_coalesce));
4555 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4556 sizeof(struct hns3_enet_coalesce));
4557 }
4558}
4559
bb6b94a8
L		 4560static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4561{
4562 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4563 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 4564 struct hns3_nic_priv *priv = netdev_priv(ndev);
4565
4566 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4567 return 0;
bb6b94a8
L		 4568
4569 if (!netif_running(ndev))
6b1385cc 4570 return 0;
bb6b94a8
L		 4571
4572 return hns3_nic_net_stop(ndev);
4573}
4574
4575static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4576{
4577 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4578 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4579 int ret = 0;
4580
e8884027
HT		 4581 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4582
bb6b94a8 4583 if (netif_running(kinfo->netdev)) {
e8884027 4584 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4585 if (ret) {
e8884027 4586 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 4587 netdev_err(kinfo->netdev,
9b2f3477 4588 "net up fail, ret=%d!\n", ret);
bb6b94a8
L		 4589 return ret;
4590 }
bb6b94a8
L		 4591 }
4592
4593 return ret;
4594}
4595
4596static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4597{
4598 struct net_device *netdev = handle->kinfo.netdev;
4599 struct hns3_nic_priv *priv = netdev_priv(netdev);
4600 int ret;
4601
bb6b94a8
L		 4602 /* Carrier off reporting is important to ethtool even BEFORE open */
4603 netif_carrier_off(netdev);
4604
2c9dd668 4605 ret = hns3_get_ring_config(priv);
862d969a
HT		 4606 if (ret)
4607 return ret;
4608
2c9dd668
HT		 4609 ret = hns3_nic_alloc_vector_data(priv);
4610 if (ret)
4611 goto err_put_ring;
4612
e4fd7502
HT		 4613 hns3_restore_coal(priv);
4614
bb6b94a8
L		 4615 ret = hns3_nic_init_vector_data(priv);
4616 if (ret)
862d969a 4617 goto err_dealloc_vector;
bb6b94a8
L		 4618
4619 ret = hns3_init_all_ring(priv);
862d969a
HT		 4620 if (ret)
4621 goto err_uninit_vector;
bb6b94a8 4622
08a10068
YL		 4623 /* the device can work without cpu rmap, only aRFS needs it */
4624 ret = hns3_set_rx_cpu_rmap(netdev);
4625 if (ret)
4626 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4627
4628 ret = hns3_nic_init_irq(priv);
4629 if (ret) {
4630 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4631 hns3_free_rx_cpu_rmap(netdev);
4632 goto err_init_irq_fail;
4633 }
4634
ee4bcd3b
JS		 4635 if (!hns3_is_phys_func(handle->pdev))
4636 hns3_init_mac_addr(netdev);
4637
cd513a69
HT		 4638 ret = hns3_client_start(handle);
4639 if (ret) {
4640 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
08a10068 4641 goto err_client_start_fail;
cd513a69
HT		 4642 }
4643
814da63c
HT		 4644 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4645
862d969a
HT		 4646 return ret;
4647
08a10068
YL		 4648err_client_start_fail:
4649 hns3_free_rx_cpu_rmap(netdev);
4650 hns3_nic_uninit_irq(priv);
4651err_init_irq_fail:
cd513a69 4652 hns3_uninit_all_ring(priv);
862d969a
HT		 4653err_uninit_vector:
4654 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 4655err_dealloc_vector:
4656 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 4657err_put_ring:
4658 hns3_put_ring_config(priv);
862d969a 4659
bb6b94a8
L		 4660 return ret;
4661}
4662
4663static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4664{
4665 struct net_device *netdev = handle->kinfo.netdev;
4666 struct hns3_nic_priv *priv = netdev_priv(netdev);
4667 int ret;
4668
1eeb3367 4669 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 4670 netdev_warn(netdev, "already uninitialized\n");
4671 return 0;
4672 }
4673
08a10068
YL		 4674 hns3_free_rx_cpu_rmap(netdev);
4675 hns3_nic_uninit_irq(priv);
f96315f2
HT		 4676 hns3_clear_all_ring(handle, true);
4677 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 4678
e2152785 4679 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4680
e4fd7502
HT		 4681 hns3_store_coal(priv);
4682
08a10068 4683 hns3_nic_dealloc_vector_data(priv);
862d969a 4684
bb6b94a8
L		 4685 ret = hns3_uninit_all_ring(priv);
4686 if (ret)
4687 netdev_err(netdev, "uninit ring error\n");
4688
2c9dd668 4689 hns3_put_ring_config(priv);
2c9dd668 4690
bb6b94a8
L		 4691 return ret;
4692}
4693
4694static int hns3_reset_notify(struct hnae3_handle *handle,
4695 enum hnae3_reset_notify_type type)
4696{
4697 int ret = 0;
4698
4699 switch (type) {
4700 case HNAE3_UP_CLIENT:
e1586241
SM		 4701 ret = hns3_reset_notify_up_enet(handle);
4702 break;
bb6b94a8
L		 4703 case HNAE3_DOWN_CLIENT:
4704 ret = hns3_reset_notify_down_enet(handle);
4705 break;
4706 case HNAE3_INIT_CLIENT:
4707 ret = hns3_reset_notify_init_enet(handle);
4708 break;
4709 case HNAE3_UNINIT_CLIENT:
4710 ret = hns3_reset_notify_uninit_enet(handle);
4711 break;
4712 default:
4713 break;
4714 }
4715
4716 return ret;
4717}
4718
3a5a5f06
PL		 4719static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4720 bool rxfh_configured)
4721{
4722 int ret;
4723
4724 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4725 rxfh_configured);
4726 if (ret) {
4727 dev_err(&handle->pdev->dev,
4728 "Change tqp num(%u) fail.\n", new_tqp_num);
4729 return ret;
4730 }
4731
4732 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4733 if (ret)
4734 return ret;
4735
4736 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4737 if (ret)
4738 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4739
4740 return ret;
4741}
4742
09f2af64
PL		 4743int hns3_set_channels(struct net_device *netdev,
4744 struct ethtool_channels *ch)
4745{
09f2af64
PL		 4746 struct hnae3_handle *h = hns3_get_handle(netdev);
4747 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4748 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 4749 u32 new_tqp_num = ch->combined_count;
4750 u16 org_tqp_num;
4751 int ret;
4752
44950d28
JS		 4753 if (hns3_nic_resetting(netdev))
4754 return -EBUSY;
4755
09f2af64
PL		 4756 if (ch->rx_count || ch->tx_count)
4757 return -EINVAL;
4758
5a5c9091
JS		 4759 if (kinfo->tc_info.mqprio_active) {
4760 dev_err(&netdev->dev,
4761 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
4762 return -EINVAL;
4763 }
4764
678335a1 4765 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4766 new_tqp_num < 1) {
09f2af64 4767 dev_err(&netdev->dev,
adcf738b 4768 "Change tqps fail, the tqp range is from 1 to %u",
678335a1 4769 hns3_get_max_available_channels(h));
09f2af64
PL		 4770 return -EINVAL;
4771 }
4772
c78b5b6c 4773 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 4774 return 0;
4775
1c822948
YL		 4776 netif_dbg(h, drv, netdev,
4777 "set channels: tqp_num=%u, rxfh=%d\n",
4778 new_tqp_num, rxfh_configured);
4779
65749f73
HT		 4780 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4781 if (ret)
4782 return ret;
dd38c726 4783
65749f73
HT		 4784 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4785 if (ret)
4786 return ret;
09f2af64
PL		 4787
4788 org_tqp_num = h->kinfo.num_tqps;
3a5a5f06 4789 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4790 if (ret) {
3a5a5f06
PL		 4791 int ret1;
4792
4793 netdev_warn(netdev,
4794 "Change channels fail, revert to old value\n");
4795 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4796 if (ret1) {
4797 netdev_err(netdev,
4798 "revert to old channel fail\n");
4799 return ret1;
09f2af64 4800 }
3a5a5f06 4801
65749f73 4802 return ret;
3a5a5f06 4803 }
09f2af64 4804
3a5a5f06 4805 return 0;
09f2af64
PL		 4806}
4807
a83d2961
WL		 4808static const struct hns3_hw_error_info hns3_hw_err[] = {
4809 { .type = HNAE3_PPU_POISON_ERROR,
4810 .msg = "PPU poison" },
4811 { .type = HNAE3_CMDQ_ECC_ERROR,
4812 .msg = "IMP CMDQ error" },
4813 { .type = HNAE3_IMP_RD_POISON_ERROR,
4814 .msg = "IMP RD poison" },
6cd131dd
YM		 4815 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
4816 .msg = "ROCEE AXI RESP error" },
a83d2961
WL		 4817};
4818
4819static void hns3_process_hw_error(struct hnae3_handle *handle,
4820 enum hnae3_hw_error_type type)
4821{
4822 int i;
4823
4824 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4825 if (hns3_hw_err[i].type == type) {
4826 dev_err(&handle->pdev->dev, "Detected %s!\n",
4827 hns3_hw_err[i].msg);
4828 break;
4829 }
4830 }
4831}
4832
1db9b1bf 4833static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4834 .init_instance = hns3_client_init,
4835 .uninit_instance = hns3_client_uninit,
4836 .link_status_change = hns3_link_status_change,
9df8f79a 4837 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4838 .reset_notify = hns3_reset_notify,
a83d2961 4839 .process_hw_error = hns3_process_hw_error,
76ad4f0e
S		 4840};
4841
4842/* hns3_init_module - Driver registration routine
4843 * hns3_init_module is the first routine called when the driver is
4844 * loaded. All it does is register with the PCI subsystem.
4845 */
4846static int __init hns3_init_module(void)
4847{
4848 int ret;
4849
4850 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4851 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4852
4853 client.type = HNAE3_CLIENT_KNIC;
cdc37385 4854 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
76ad4f0e
S		 4855 hns3_driver_name);
4856
4857 client.ops = &client_ops;
4858
13562d1f
XW		 4859 INIT_LIST_HEAD(&client.node);
4860
b2292360 4861 hns3_dbg_register_debugfs(hns3_driver_name);
4862
76ad4f0e
S		 4863 ret = hnae3_register_client(&client);
4864 if (ret)
b2292360 4865 goto err_reg_client;
76ad4f0e
S		 4866
4867 ret = pci_register_driver(&hns3_driver);
4868 if (ret)
b2292360 4869 goto err_reg_driver;
76ad4f0e
S		 4870
4871 return ret;
b2292360 4872
4873err_reg_driver:
4874 hnae3_unregister_client(&client);
4875err_reg_client:
4876 hns3_dbg_unregister_debugfs();
4877 return ret;
76ad4f0e
S		 4878}
4879module_init(hns3_init_module);
4880
4881/* hns3_exit_module - Driver exit cleanup routine
4882 * hns3_exit_module is called just before the driver is removed
4883 * from memory.
4884 */
4885static void __exit hns3_exit_module(void)
4886{
4887 pci_unregister_driver(&hns3_driver);
4888 hnae3_unregister_client(&client);
b2292360 4889 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4890}
4891module_exit(hns3_exit_module);
4892
4893MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4894MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4895MODULE_LICENSE("GPL");
4896MODULE_ALIAS("pci:hns-nic");
Linux 6.x block layer and io_uring tree(s)