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cxgb4vf: convert to use DEFINE_SEQ_ATTRIBUTE macro
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e 10#include <linux/if_vlan.h>
e99a308d 11#include <linux/irq.h>
76ad4f0e
S		 12#include <linux/ip.h>
13#include <linux/ipv6.h>
14#include <linux/module.h>
15#include <linux/pci.h>
6ae4e733 16#include <linux/aer.h>
76ad4f0e
S		 17#include <linux/skbuff.h>
18#include <linux/sctp.h>
76ad4f0e 19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
76ad4f0e 23#include <net/vxlan.h>
a156998f 24#include <net/geneve.h>
76ad4f0e
S		 25
26#include "hnae3.h"
27#include "hns3_enet.h"
698a8954
YL		 28/* All hns3 tracepoints are defined by the include below, which
29 * must be included exactly once across the whole kernel with
30 * CREATE_TRACE_POINTS defined
31 */
32#define CREATE_TRACE_POINTS
33#include "hns3_trace.h"
76ad4f0e 34
cde4ffad 35#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 36#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 37
b20d7fe5
YL		 38#define hns3_rl_err(fmt, ...) \
39 do { \
40 if (net_ratelimit()) \
41 netdev_err(fmt, ##__VA_ARGS__); \
42 } while (0)
43
f96315f2 44static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
7b763f3f 45
1db9b1bf 46static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 47static const char hns3_driver_string[] =
48 "Hisilicon Ethernet Network Driver for Hip08 Family";
49static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
50static struct hnae3_client client;
51
bb87be87
YL		 52static int debug = -1;
53module_param(debug, int, 0);
54MODULE_PARM_DESC(debug, " Network interface message level setting");
55
56#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
58
eb977d99
YL		 59#define HNS3_INNER_VLAN_TAG 1
60#define HNS3_OUTER_VLAN_TAG 2
61
36c67349
YL		 62#define HNS3_MIN_TX_LEN 33U
63
76ad4f0e
S		 64/* hns3_pci_tbl - PCI Device ID Table
65 *
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
71static const struct pci_device_id hns3_pci_tbl[] = {
72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
07acf909
JS		 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
86 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 87 /* required last entry */
88 {0, }
89};
90MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
91
ef0c5009 92static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 93{
ef0c5009 94 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 95
fb00331b 96 napi_schedule_irqoff(&tqp_vector->napi);
76ad4f0e
S		 97
98 return IRQ_HANDLED;
99}
100
101static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
102{
103 struct hns3_enet_tqp_vector *tqp_vectors;
104 unsigned int i;
105
106 for (i = 0; i < priv->vector_num; i++) {
107 tqp_vectors = &priv->tqp_vector[i];
108
109 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
110 continue;
111
ffab9691 112 /* clear the affinity mask */
874bff0b
PL		 113 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
114
76ad4f0e
S		 115 /* release the irq resource */
116 free_irq(tqp_vectors->vector_irq, tqp_vectors);
117 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
118 }
119}
120
121static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
122{
123 struct hns3_enet_tqp_vector *tqp_vectors;
124 int txrx_int_idx = 0;
125 int rx_int_idx = 0;
126 int tx_int_idx = 0;
127 unsigned int i;
128 int ret;
129
130 for (i = 0; i < priv->vector_num; i++) {
131 tqp_vectors = &priv->tqp_vector[i];
132
133 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
134 continue;
135
136 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
5bffde62
YL		 137 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
138 "%s-%s-%s-%d", hns3_driver_name,
139 pci_name(priv->ae_handle->pdev),
140 "TxRx", txrx_int_idx++);
76ad4f0e
S		 141 txrx_int_idx++;
142 } else if (tqp_vectors->rx_group.ring) {
5bffde62
YL		 143 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
144 "%s-%s-%s-%d", hns3_driver_name,
145 pci_name(priv->ae_handle->pdev),
146 "Rx", rx_int_idx++);
76ad4f0e 147 } else if (tqp_vectors->tx_group.ring) {
5bffde62
YL		 148 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
149 "%s-%s-%s-%d", hns3_driver_name,
150 pci_name(priv->ae_handle->pdev),
151 "Tx", tx_int_idx++);
76ad4f0e
S		 152 } else {
153 /* Skip this unused q_vector */
154 continue;
155 }
156
157 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
158
e99a308d 159 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
76ad4f0e 160 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 161 tqp_vectors->name, tqp_vectors);
76ad4f0e
S		 162 if (ret) {
163 netdev_err(priv->netdev, "request irq(%d) fail\n",
164 tqp_vectors->vector_irq);
d547ecdc 165 hns3_nic_uninit_irq(priv);
76ad4f0e
S		 166 return ret;
167 }
168
874bff0b
PL		 169 irq_set_affinity_hint(tqp_vectors->vector_irq,
170 &tqp_vectors->affinity_mask);
171
76ad4f0e
S		 172 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
173 }
174
175 return 0;
176}
177
178static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
179 u32 mask_en)
180{
181 writel(mask_en, tqp_vector->mask_addr);
182}
183
184static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
185{
186 napi_enable(&tqp_vector->napi);
08a10068 187 enable_irq(tqp_vector->vector_irq);
76ad4f0e
S		 188
189 /* enable vector */
190 hns3_mask_vector_irq(tqp_vector, 1);
191}
192
193static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
194{
195 /* disable vector */
196 hns3_mask_vector_irq(tqp_vector, 0);
197
198 disable_irq(tqp_vector->vector_irq);
199 napi_disable(&tqp_vector->napi);
200}
201
434776a5
FL		 202void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
203 u32 rl_value)
76ad4f0e 204{
434776a5
FL		 205 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
206
76ad4f0e
S		 207 /* this defines the configuration for RL (Interrupt Rate Limiter).
208 * Rl defines rate of interrupts i.e. number of interrupts-per-second
209 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
210 */
434776a5 211
9bc727a9
YL		 212 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
213 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 214 /* According to the hardware, the range of rl_reg is
215 * 0-59 and the unit is 4.
216 */
217 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
218
219 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
220}
221
222void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
223 u32 gl_value)
224{
225 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
226
227 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
228}
229
230void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
231 u32 gl_value)
232{
233 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
234
235 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 236}
237
5fd4789a
FL		 238static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
239 struct hns3_nic_priv *priv)
76ad4f0e
S		 240{
241 /* initialize the configuration for interrupt coalescing.
242 * 1. GL (Interrupt Gap Limiter)
243 * 2. RL (Interrupt Rate Limiter)
46ee7350
GL		 244 *
245 * Default: enable interrupt coalescing self-adaptive and GL
76ad4f0e 246 */
9bc727a9
YL		 247 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
248 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 249
9bc727a9
YL		 250 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
251 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 252
9bc727a9
YL		 253 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
254 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 255}
256
dd38c726
YL		 257static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
258 struct hns3_nic_priv *priv)
259{
260 struct hnae3_handle *h = priv->ae_handle;
261
262 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 263 tqp_vector->tx_group.coal.int_gl);
dd38c726 264 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 265 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 266 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
267}
268
9df8f79a
YL		 269static int hns3_nic_set_real_num_queue(struct net_device *netdev)
270{
9780cb97 271 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 272 struct hnae3_knic_private_info *kinfo = &h->kinfo;
273 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
a75a8efa
YL		 274 int i, ret;
275
276 if (kinfo->num_tc <= 1) {
277 netdev_reset_tc(netdev);
278 } else {
279 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
280 if (ret) {
281 netdev_err(netdev,
282 "netdev_set_num_tc fail, ret=%d!\n", ret);
283 return ret;
284 }
285
286 for (i = 0; i < HNAE3_MAX_TC; i++) {
287 if (!kinfo->tc_info[i].enable)
288 continue;
289
290 netdev_set_tc_queue(netdev,
291 kinfo->tc_info[i].tc,
292 kinfo->tc_info[i].tqp_count,
293 kinfo->tc_info[i].tqp_offset);
294 }
295 }
9df8f79a
YL		 296
297 ret = netif_set_real_num_tx_queues(netdev, queue_size);
298 if (ret) {
299 netdev_err(netdev,
9b2f3477 300 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL		 301 return ret;
302 }
303
304 ret = netif_set_real_num_rx_queues(netdev, queue_size);
305 if (ret) {
306 netdev_err(netdev,
307 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
308 return ret;
309 }
310
311 return 0;
312}
313
678335a1
PL		 314static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
315{
0d43bf45 316 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 317
0d43bf45
HT		 318 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
319 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 320
0d43bf45 321 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 322}
323
8df0fa91
HT		 324static void hns3_tqp_enable(struct hnae3_queue *tqp)
325{
326 u32 rcb_reg;
327
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg |= BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
331}
332
333static void hns3_tqp_disable(struct hnae3_queue *tqp)
334{
335 u32 rcb_reg;
336
337 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
338 rcb_reg &= ~BIT(HNS3_RING_EN_B);
339 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
340}
341
ffab9691
JS		 342static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
343{
344#ifdef CONFIG_RFS_ACCEL
345 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
346 netdev->rx_cpu_rmap = NULL;
347#endif
348}
349
350static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
351{
352#ifdef CONFIG_RFS_ACCEL
353 struct hns3_nic_priv *priv = netdev_priv(netdev);
354 struct hns3_enet_tqp_vector *tqp_vector;
355 int i, ret;
356
357 if (!netdev->rx_cpu_rmap) {
358 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
359 if (!netdev->rx_cpu_rmap)
360 return -ENOMEM;
361 }
362
363 for (i = 0; i < priv->vector_num; i++) {
364 tqp_vector = &priv->tqp_vector[i];
365 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
366 tqp_vector->vector_irq);
367 if (ret) {
368 hns3_free_rx_cpu_rmap(netdev);
369 return ret;
370 }
371 }
372#endif
373 return 0;
374}
375
76ad4f0e
S		 376static int hns3_nic_net_up(struct net_device *netdev)
377{
378 struct hns3_nic_priv *priv = netdev_priv(netdev);
379 struct hnae3_handle *h = priv->ae_handle;
380 int i, j;
381 int ret;
382
7b763f3f
FL		 383 ret = hns3_nic_reset_all_ring(h);
384 if (ret)
385 return ret;
386
b7b585c2
JS		 387 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
388
76ad4f0e
S		 389 /* enable the vectors */
390 for (i = 0; i < priv->vector_num; i++)
391 hns3_vector_enable(&priv->tqp_vector[i]);
392
8df0fa91
HT		 393 /* enable rcb */
394 for (j = 0; j < h->kinfo.num_tqps; j++)
395 hns3_tqp_enable(h->kinfo.tqp[j]);
396
76ad4f0e
S		 397 /* start the ae_dev */
398 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
08a10068
YL		 399 if (ret) {
400 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
401 while (j--)
402 hns3_tqp_disable(h->kinfo.tqp[j]);
8df0fa91 403
08a10068
YL		 404 for (j = i - 1; j >= 0; j--)
405 hns3_vector_disable(&priv->tqp_vector[j]);
406 }
76ad4f0e 407
76ad4f0e
S		 408 return ret;
409}
410
2a73ac3e
YL		 411static void hns3_config_xps(struct hns3_nic_priv *priv)
412{
413 int i;
414
415 for (i = 0; i < priv->vector_num; i++) {
416 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
417 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
418
419 while (ring) {
420 int ret;
421
422 ret = netif_set_xps_queue(priv->netdev,
423 &tqp_vector->affinity_mask,
424 ring->tqp->tqp_index);
425 if (ret)
426 netdev_warn(priv->netdev,
427 "set xps queue failed: %d", ret);
428
429 ring = ring->next;
430 }
431 }
432}
433
76ad4f0e
S		 434static int hns3_nic_net_open(struct net_device *netdev)
435{
8cdb992f 436 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 437 struct hnae3_handle *h = hns3_get_handle(netdev);
438 struct hnae3_knic_private_info *kinfo;
439 int i, ret;
76ad4f0e 440
257e4f29
HT		 441 if (hns3_nic_resetting(netdev))
442 return -EBUSY;
443
76ad4f0e
S		 444 netif_carrier_off(netdev);
445
9df8f79a
YL		 446 ret = hns3_nic_set_real_num_queue(netdev);
447 if (ret)
76ad4f0e 448 return ret;
76ad4f0e
S		 449
450 ret = hns3_nic_net_up(netdev);
451 if (ret) {
9b2f3477 452 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S		 453 return ret;
454 }
455
a75a8efa 456 kinfo = &h->kinfo;
9b2f3477
WL		 457 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
458 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
a75a8efa 459
8cdb992f
JS		 460 if (h->ae_algo->ops->set_timer_task)
461 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
462
2a73ac3e 463 hns3_config_xps(priv);
1c822948
YL		 464
465 netif_dbg(h, drv, netdev, "net open\n");
466
76ad4f0e
S		 467 return 0;
468}
469
f96315f2
HT		 470static void hns3_reset_tx_queue(struct hnae3_handle *h)
471{
472 struct net_device *ndev = h->kinfo.netdev;
473 struct hns3_nic_priv *priv = netdev_priv(ndev);
474 struct netdev_queue *dev_queue;
475 u32 i;
476
477 for (i = 0; i < h->kinfo.num_tqps; i++) {
478 dev_queue = netdev_get_tx_queue(ndev,
5f06b903 479 priv->ring[i].queue_index);
f96315f2
HT		 480 netdev_tx_reset_queue(dev_queue);
481 }
482}
483
76ad4f0e
S		 484static void hns3_nic_net_down(struct net_device *netdev)
485{
486 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 487 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 488 const struct hnae3_ae_ops *ops;
489 int i;
490
7b763f3f
FL		 491 /* disable vectors */
492 for (i = 0; i < priv->vector_num; i++)
493 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 494
495 /* disable rcb */
496 for (i = 0; i < h->kinfo.num_tqps; i++)
497 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 498
76ad4f0e
S		 499 /* stop ae_dev */
500 ops = priv->ae_handle->ae_algo->ops;
501 if (ops->stop)
502 ops->stop(priv->ae_handle);
503
3a30964a
YL		 504 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
505 * during reset process, because driver may not be able
506 * to disable the ring through firmware when downing the netdev.
507 */
508 if (!hns3_nic_resetting(netdev))
f96315f2
HT		 509 hns3_clear_all_ring(priv->ae_handle, false);
510
511 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S		 512}
513
514static int hns3_nic_net_stop(struct net_device *netdev)
515{
ff0699e0 516 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 517 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 518
519 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
520 return 0;
521
1c822948
YL		 522 netif_dbg(h, drv, netdev, "net stop\n");
523
8cdb992f
JS		 524 if (h->ae_algo->ops->set_timer_task)
525 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
526
76ad4f0e
S		 527 netif_tx_stop_all_queues(netdev);
528 netif_carrier_off(netdev);
529
530 hns3_nic_net_down(netdev);
531
532 return 0;
533}
534
76ad4f0e
S		 535static int hns3_nic_uc_sync(struct net_device *netdev,
536 const unsigned char *addr)
537{
9780cb97 538 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 539
540 if (h->ae_algo->ops->add_uc_addr)
541 return h->ae_algo->ops->add_uc_addr(h, addr);
542
543 return 0;
544}
545
546static int hns3_nic_uc_unsync(struct net_device *netdev,
547 const unsigned char *addr)
548{
9780cb97 549 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 550
ee4bcd3b
JS		 551 /* need ignore the request of removing device address, because
552 * we store the device address and other addresses of uc list
553 * in the function's mac filter list.
554 */
555 if (ether_addr_equal(addr, netdev->dev_addr))
556 return 0;
557
76ad4f0e
S		 558 if (h->ae_algo->ops->rm_uc_addr)
559 return h->ae_algo->ops->rm_uc_addr(h, addr);
560
561 return 0;
562}
563
564static int hns3_nic_mc_sync(struct net_device *netdev,
565 const unsigned char *addr)
566{
9780cb97 567 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 568
720a8478 569 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 570 return h->ae_algo->ops->add_mc_addr(h, addr);
571
572 return 0;
573}
574
575static int hns3_nic_mc_unsync(struct net_device *netdev,
576 const unsigned char *addr)
577{
9780cb97 578 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 579
720a8478 580 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 581 return h->ae_algo->ops->rm_mc_addr(h, addr);
582
583 return 0;
584}
585
c60edc17
JS		 586static u8 hns3_get_netdev_flags(struct net_device *netdev)
587{
588 u8 flags = 0;
589
590 if (netdev->flags & IFF_PROMISC) {
28673b33 591 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS		 592 } else {
593 flags |= HNAE3_VLAN_FLTR;
594 if (netdev->flags & IFF_ALLMULTI)
595 flags |= HNAE3_USER_MPE;
596 }
597
598 return flags;
599}
600
1db9b1bf 601static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 602{
9780cb97 603 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17 604 u8 new_flags;
76ad4f0e 605
c60edc17
JS		 606 new_flags = hns3_get_netdev_flags(netdev);
607
c631c696
JS		 608 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
609 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
c60edc17 610
c60edc17 611 /* User mode Promisc mode enable and vlan filtering is disabled to
c631c696 612 * let all packets in.
c60edc17 613 */
c60edc17 614 h->netdev_flags = new_flags;
c631c696
JS		 615 hns3_request_update_promisc_mode(h);
616}
617
618void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
619{
620 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
621
622 if (ops->request_update_promisc_mode)
623 ops->request_update_promisc_mode(handle);
c60edc17
JS		 624}
625
c60edc17
JS		 626void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
627{
628 struct hns3_nic_priv *priv = netdev_priv(netdev);
629 struct hnae3_handle *h = priv->ae_handle;
630 bool last_state;
631
632 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
633 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
634 if (enable != last_state) {
635 netdev_info(netdev,
636 "%s vlan filter\n",
637 enable ? "enable" : "disable");
638 h->ae_algo->ops->enable_vlan_filter(h, enable);
639 }
40cca1c5 640 }
76ad4f0e
S		 641}
642
643static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
644 u16 *mss, u32 *type_cs_vlan_tso)
645{
646 u32 l4_offset, hdr_len;
647 union l3_hdr_info l3;
648 union l4_hdr_info l4;
649 u32 l4_paylen;
650 int ret;
651
652 if (!skb_is_gso(skb))
653 return 0;
654
655 ret = skb_cow_head(skb, 0);
8ae10cfb 656 if (unlikely(ret < 0))
76ad4f0e
S		 657 return ret;
658
659 l3.hdr = skb_network_header(skb);
660 l4.hdr = skb_transport_header(skb);
661
662 /* Software should clear the IPv4's checksum field when tso is
663 * needed.
664 */
665 if (l3.v4->version == 4)
666 l3.v4->check = 0;
667
9b2f3477 668 /* tunnel packet */
76ad4f0e
S		 669 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
670 SKB_GSO_GRE_CSUM |
671 SKB_GSO_UDP_TUNNEL |
672 SKB_GSO_UDP_TUNNEL_CSUM)) {
673 if ((!(skb_shinfo(skb)->gso_type &
674 SKB_GSO_PARTIAL)) &&
675 (skb_shinfo(skb)->gso_type &
676 SKB_GSO_UDP_TUNNEL_CSUM)) {
677 /* Software should clear the udp's checksum
678 * field when tso is needed.
679 */
680 l4.udp->check = 0;
681 }
682 /* reset l3&l4 pointers from outer to inner headers */
683 l3.hdr = skb_inner_network_header(skb);
684 l4.hdr = skb_inner_transport_header(skb);
685
686 /* Software should clear the IPv4's checksum field when
687 * tso is needed.
688 */
689 if (l3.v4->version == 4)
690 l3.v4->check = 0;
691 }
692
9b2f3477 693 /* normal or tunnel packet */
76ad4f0e 694 l4_offset = l4.hdr - skb->data;
3fe13ed9 695 hdr_len = (l4.tcp->doff << 2) + l4_offset;
76ad4f0e 696
9b2f3477 697 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e
S		 698 l4_paylen = skb->len - l4_offset;
699 csum_replace_by_diff(&l4.tcp->check,
700 (__force __wsum)htonl(l4_paylen));
701
702 /* find the txbd field values */
703 *paylen = skb->len - hdr_len;
cde4ffad 704 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 705
706 /* get MSS for TSO */
707 *mss = skb_shinfo(skb)->gso_size;
708
698a8954
YL		 709 trace_hns3_tso(skb);
710
76ad4f0e
S		 711 return 0;
712}
713
1898d4e4
S		 714static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
715 u8 *il4_proto)
76ad4f0e 716{
1a6e552d 717 union l3_hdr_info l3;
76ad4f0e
S		 718 unsigned char *l4_hdr;
719 unsigned char *exthdr;
720 u8 l4_proto_tmp;
721 __be16 frag_off;
722
723 /* find outer header point */
724 l3.hdr = skb_network_header(skb);
35f58fd7 725 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 726
727 if (skb->protocol == htons(ETH_P_IPV6)) {
728 exthdr = l3.hdr + sizeof(*l3.v6);
729 l4_proto_tmp = l3.v6->nexthdr;
730 if (l4_hdr != exthdr)
731 ipv6_skip_exthdr(skb, exthdr - skb->data,
732 &l4_proto_tmp, &frag_off);
733 } else if (skb->protocol == htons(ETH_P_IP)) {
734 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 735 } else {
736 return -EINVAL;
76ad4f0e
S		 737 }
738
739 *ol4_proto = l4_proto_tmp;
740
741 /* tunnel packet */
742 if (!skb->encapsulation) {
743 *il4_proto = 0;
1898d4e4 744 return 0;
76ad4f0e
S		 745 }
746
747 /* find inner header point */
748 l3.hdr = skb_inner_network_header(skb);
749 l4_hdr = skb_inner_transport_header(skb);
750
751 if (l3.v6->version == 6) {
752 exthdr = l3.hdr + sizeof(*l3.v6);
753 l4_proto_tmp = l3.v6->nexthdr;
754 if (l4_hdr != exthdr)
755 ipv6_skip_exthdr(skb, exthdr - skb->data,
756 &l4_proto_tmp, &frag_off);
757 } else if (l3.v4->version == 4) {
758 l4_proto_tmp = l3.v4->protocol;
759 }
760
761 *il4_proto = l4_proto_tmp;
1898d4e4
S		 762
763 return 0;
76ad4f0e
S		 764}
765
3db084d2
YL		 766/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
767 * and it is udp packet, which has a dest port as the IANA assigned.
768 * the hardware is expected to do the checksum offload, but the
769 * hardware will not do the checksum offload when udp dest port is
a156998f 770 * 4789 or 6081.
3db084d2
YL		 771 */
772static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
773{
1a6e552d 774 union l4_hdr_info l4;
3db084d2
YL		 775
776 l4.hdr = skb_transport_header(skb);
777
bea96410 778 if (!(!skb->encapsulation &&
a156998f
YL		 779 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
780 l4.udp->dest == htons(GENEVE_UDP_PORT))))
3db084d2
YL		 781 return false;
782
783 skb_checksum_help(skb);
784
785 return true;
786}
787
757cd1e4
YL		 788static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
789 u32 *ol_type_vlan_len_msec)
76ad4f0e 790{
757cd1e4
YL		 791 u32 l2_len, l3_len, l4_len;
792 unsigned char *il2_hdr;
1a6e552d 793 union l3_hdr_info l3;
757cd1e4 794 union l4_hdr_info l4;
76ad4f0e
S		 795
796 l3.hdr = skb_network_header(skb);
757cd1e4 797 l4.hdr = skb_transport_header(skb);
76ad4f0e 798
757cd1e4
YL		 799 /* compute OL2 header size, defined in 2 Bytes */
800 l2_len = l3.hdr - skb->data;
801 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
802
803 /* compute OL3 header size, defined in 4 Bytes */
804 l3_len = l4.hdr - l3.hdr;
805 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 806
757cd1e4 807 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 808 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL		 809 l4_len = il2_hdr - l4.hdr;
810 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
811
812 /* define outer network header type */
813 if (skb->protocol == htons(ETH_P_IP)) {
814 if (skb_is_gso(skb))
cde4ffad 815 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 816 HNS3_TXD_OL3T_S,
817 HNS3_OL3T_IPV4_CSUM);
818 else
cde4ffad 819 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 820 HNS3_TXD_OL3T_S,
821 HNS3_OL3T_IPV4_NO_CSUM);
822
823 } else if (skb->protocol == htons(ETH_P_IPV6)) {
824 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
825 HNS3_OL3T_IPV6);
826 }
827
828 if (ol4_proto == IPPROTO_UDP)
829 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
830 HNS3_TUN_MAC_IN_UDP);
831 else if (ol4_proto == IPPROTO_GRE)
832 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
833 HNS3_TUN_NVGRE);
834}
835
836static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
837 u8 il4_proto, u32 *type_cs_vlan_tso,
838 u32 *ol_type_vlan_len_msec)
839{
c264ed44 840 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 841 u32 l4_proto = ol4_proto;
842 union l4_hdr_info l4;
843 union l3_hdr_info l3;
844 u32 l2_len, l3_len;
845
846 l4.hdr = skb_transport_header(skb);
847 l3.hdr = skb_network_header(skb);
848
849 /* handle encapsulation skb */
850 if (skb->encapsulation) {
851 /* If this is a not UDP/GRE encapsulation skb */
852 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 853 /* drop the skb tunnel packet if hardware don't support,
854 * because hardware can't calculate csum when TSO.
855 */
856 if (skb_is_gso(skb))
857 return -EDOM;
858
859 /* the stack computes the IP header already,
860 * driver calculate l4 checksum when not TSO.
861 */
862 skb_checksum_help(skb);
863 return 0;
864 }
865
757cd1e4
YL		 866 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
867
868 /* switch to inner header */
869 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 870 l3.hdr = skb_inner_network_header(skb);
757cd1e4 871 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 872 l4_proto = il4_proto;
873 }
874
875 if (l3.v4->version == 4) {
cde4ffad
YL		 876 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
877 HNS3_L3T_IPV4);
76ad4f0e
S		 878
879 /* the stack computes the IP header already, the only time we
880 * need the hardware to recompute it is in the case of TSO.
881 */
882 if (skb_is_gso(skb))
cde4ffad 883 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 884 } else if (l3.v6->version == 6) {
cde4ffad
YL		 885 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
886 HNS3_L3T_IPV6);
76ad4f0e
S		 887 }
888
757cd1e4
YL		 889 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
890 l2_len = l3.hdr - l2_hdr;
891 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
892
893 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
894 l3_len = l4.hdr - l3.hdr;
895 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
896
897 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 898 switch (l4_proto) {
899 case IPPROTO_TCP:
cde4ffad
YL		 900 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
901 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
902 HNS3_L4T_TCP);
757cd1e4
YL		 903 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
904 l4.tcp->doff);
76ad4f0e
S		 905 break;
906 case IPPROTO_UDP:
3db084d2
YL		 907 if (hns3_tunnel_csum_bug(skb))
908 break;
909
cde4ffad
YL		 910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
911 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
912 HNS3_L4T_UDP);
757cd1e4
YL		 913 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
914 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 915 break;
916 case IPPROTO_SCTP:
cde4ffad
YL		 917 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
918 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
919 HNS3_L4T_SCTP);
757cd1e4
YL		 920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
921 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 922 break;
923 default:
924 /* drop the skb tunnel packet if hardware don't support,
925 * because hardware can't calculate csum when TSO.
926 */
927 if (skb_is_gso(skb))
928 return -EDOM;
929
930 /* the stack computes the IP header already,
931 * driver calculate l4 checksum when not TSO.
932 */
933 skb_checksum_help(skb);
934 return 0;
935 }
936
937 return 0;
938}
939
eb977d99
YL		 940static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
941 struct sk_buff *skb)
9699cffe 942{
44e626f7 943 struct hnae3_handle *handle = tx_ring->tqp->handle;
eb977d99
YL		 944 struct vlan_ethhdr *vhdr;
945 int rc;
946
947 if (!(skb->protocol == htons(ETH_P_8021Q) ||
948 skb_vlan_tag_present(skb)))
949 return 0;
44e626f7
JS		 950
951 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
952 * header is allowed in skb, otherwise it will cause RAS error.
953 */
954 if (unlikely(skb_vlan_tagged_multi(skb) &&
955 handle->port_base_vlan_state ==
956 HNAE3_PORT_BASE_VLAN_ENABLE))
957 return -EINVAL;
958
9699cffe 959 if (skb->protocol == htons(ETH_P_8021Q) &&
eb977d99 960 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
9699cffe
PL		 961 /* When HW VLAN acceleration is turned off, and the stack
962 * sets the protocol to 802.1q, the driver just need to
963 * set the protocol to the encapsulated ethertype.
964 */
965 skb->protocol = vlan_get_protocol(skb);
966 return 0;
967 }
968
969 if (skb_vlan_tag_present(skb)) {
9699cffe
PL		 970 /* Based on hw strategy, use out_vtag in two layer tag case,
971 * and use inner_vtag in one tag case.
972 */
eb977d99
YL		 973 if (skb->protocol == htons(ETH_P_8021Q) &&
974 handle->port_base_vlan_state ==
975 HNAE3_PORT_BASE_VLAN_DISABLE)
976 rc = HNS3_OUTER_VLAN_TAG;
977 else
978 rc = HNS3_INNER_VLAN_TAG;
979
980 skb->protocol = vlan_get_protocol(skb);
981 return rc;
9699cffe
PL		 982 }
983
eb977d99
YL		 984 rc = skb_cow_head(skb, 0);
985 if (unlikely(rc < 0))
986 return rc;
987
988 vhdr = (struct vlan_ethhdr *)skb->data;
989 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
990 & VLAN_PRIO_MASK);
991
9699cffe
PL		 992 skb->protocol = vlan_get_protocol(skb);
993 return 0;
994}
995
eb977d99
YL		 996static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
997 struct sk_buff *skb, struct hns3_desc *desc)
998{
999 u32 ol_type_vlan_len_msec = 0;
1000 u32 type_cs_vlan_tso = 0;
1001 u32 paylen = skb->len;
1002 u16 inner_vtag = 0;
1003 u16 out_vtag = 0;
1004 u16 mss = 0;
1005 int ret;
1006
1007 ret = hns3_handle_vtags(ring, skb);
1008 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1009 u64_stats_update_begin(&ring->syncp);
1010 ring->stats.tx_vlan_err++;
1011 u64_stats_update_end(&ring->syncp);
eb977d99
YL		 1012 return ret;
1013 } else if (ret == HNS3_INNER_VLAN_TAG) {
1014 inner_vtag = skb_vlan_tag_get(skb);
1015 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1016 VLAN_PRIO_MASK;
1017 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1018 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1019 out_vtag = skb_vlan_tag_get(skb);
1020 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1021 VLAN_PRIO_MASK;
1022 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1023 1);
1024 }
1025
1026 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1027 u8 ol4_proto, il4_proto;
1028
1029 skb_reset_mac_len(skb);
1030
1031 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
8ae10cfb 1032 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1033 u64_stats_update_begin(&ring->syncp);
1034 ring->stats.tx_l4_proto_err++;
1035 u64_stats_update_end(&ring->syncp);
eb977d99 1036 return ret;
b20d7fe5 1037 }
eb977d99
YL		 1038
1039 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1040 &type_cs_vlan_tso,
1041 &ol_type_vlan_len_msec);
8ae10cfb 1042 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1043 u64_stats_update_begin(&ring->syncp);
1044 ring->stats.tx_l2l3l4_err++;
1045 u64_stats_update_end(&ring->syncp);
eb977d99 1046 return ret;
b20d7fe5 1047 }
eb977d99
YL		 1048
1049 ret = hns3_set_tso(skb, &paylen, &mss,
1050 &type_cs_vlan_tso);
8ae10cfb 1051 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1052 u64_stats_update_begin(&ring->syncp);
1053 ring->stats.tx_tso_err++;
1054 u64_stats_update_end(&ring->syncp);
eb977d99 1055 return ret;
b20d7fe5 1056 }
eb977d99
YL		 1057 }
1058
1059 /* Set txbd */
1060 desc->tx.ol_type_vlan_len_msec =
1061 cpu_to_le32(ol_type_vlan_len_msec);
1062 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1063 desc->tx.paylen = cpu_to_le32(paylen);
1064 desc->tx.mss = cpu_to_le16(mss);
1065 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1066 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1067
1068 return 0;
1069}
1070
76ad4f0e 1071static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
8ae10cfb 1072 unsigned int size, enum hns_desc_type type)
76ad4f0e 1073{
8ae10cfb
YL		 1074#define HNS3_LIKELY_BD_NUM 1
1075
76ad4f0e
S		 1076 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1077 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1078 struct device *dev = ring_to_dev(ring);
d7840976 1079 skb_frag_t *frag;
1e8a7977 1080 unsigned int frag_buf_num;
47e7b13b 1081 int k, sizeoflast;
5188f218 1082 dma_addr_t dma;
76ad4f0e 1083
cfdaeba5
YL		 1084 if (type == DESC_TYPE_FRAGLIST_SKB ||
1085 type == DESC_TYPE_SKB) {
74ef402e
HT		 1086 struct sk_buff *skb = (struct sk_buff *)priv;
1087
5188f218
PL		 1088 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1089 } else {
d7840976 1090 frag = (skb_frag_t *)priv;
5188f218
PL		 1091 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1092 }
1093
845e0d1d 1094 if (unlikely(dma_mapping_error(dev, dma))) {
b20d7fe5 1095 u64_stats_update_begin(&ring->syncp);
5188f218 1096 ring->stats.sw_err_cnt++;
b20d7fe5 1097 u64_stats_update_end(&ring->syncp);
5188f218 1098 return -ENOMEM;
76ad4f0e
S		 1099 }
1100
0ec3b6a7 1101 desc_cb->priv = priv;
bcdb12b7 1102 desc_cb->length = size;
0ec3b6a7
YL		 1103 desc_cb->dma = dma;
1104 desc_cb->type = type;
bcdb12b7 1105
ceca4a5e 1106 if (likely(size <= HNS3_MAX_BD_SIZE)) {
ceca4a5e
YL		 1107 desc->addr = cpu_to_le64(dma);
1108 desc->tx.send_size = cpu_to_le16(size);
ceca4a5e 1109 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1110 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
ceca4a5e 1111
698a8954 1112 trace_hns3_tx_desc(ring, ring->next_to_use);
ceca4a5e 1113 ring_ptr_move_fw(ring, next_to_use);
8ae10cfb 1114 return HNS3_LIKELY_BD_NUM;
ceca4a5e
YL		 1115 }
1116
5f543a54 1117 frag_buf_num = hns3_tx_bd_count(size);
48ae74c9 1118 sizeoflast = size % HNS3_MAX_BD_SIZE;
1e8a7977
FL		 1119 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1120
1121 /* When frag size is bigger than hardware limit, split this frag */
1122 for (k = 0; k < frag_buf_num; k++) {
1e8a7977
FL		 1123 /* now, fill the descriptor */
1124 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1125 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1126 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977 1127 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1128 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1e8a7977 1129
698a8954 1130 trace_hns3_tx_desc(ring, ring->next_to_use);
9b2f3477 1131 /* move ring pointer to next */
1e8a7977
FL		 1132 ring_ptr_move_fw(ring, next_to_use);
1133
1e8a7977
FL		 1134 desc = &ring->desc[ring->next_to_use];
1135 }
76ad4f0e 1136
8ae10cfb 1137 return frag_buf_num;
76ad4f0e
S		 1138}
1139
8ae10cfb
YL		 1140static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1141 unsigned int bd_num)
76ad4f0e 1142{
8ae10cfb 1143 unsigned int size;
42611b70 1144 int i;
76ad4f0e 1145
8ae10cfb
YL		 1146 size = skb_headlen(skb);
1147 while (size > HNS3_MAX_BD_SIZE) {
1148 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1149 size -= HNS3_MAX_BD_SIZE;
1150
1151 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1152 return bd_num;
1153 }
76ad4f0e 1154
8ae10cfb
YL		 1155 if (size) {
1156 bd_size[bd_num++] = size;
1157 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1158 return bd_num;
1159 }
76ad4f0e 1160
3d5f3741 1161 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
d7840976 1162 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8ae10cfb
YL		 1163 size = skb_frag_size(frag);
1164 if (!size)
1165 continue;
1166
1167 while (size > HNS3_MAX_BD_SIZE) {
1168 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1169 size -= HNS3_MAX_BD_SIZE;
1170
1171 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1172 return bd_num;
1173 }
1174
1175 bd_size[bd_num++] = size;
1176 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1177 return bd_num;
1178 }
1179
1180 return bd_num;
1181}
1182
1183static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1184{
1185 struct sk_buff *frag_skb;
1186 unsigned int bd_num = 0;
1187
1188 /* If the total len is within the max bd limit */
1189 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1190 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1191 return skb_shinfo(skb)->nr_frags + 1U;
1192
1193 /* The below case will always be linearized, return
1194 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1195 */
1196 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1197 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1198 return HNS3_MAX_TSO_BD_NUM + 1U;
1199
1200 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1201
1202 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1203 return bd_num;
1204
1205 skb_walk_frags(skb, frag_skb) {
1206 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1207 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1208 return bd_num;
3d5f3741 1209 }
76ad4f0e 1210
3d5f3741 1211 return bd_num;
76ad4f0e
S		 1212}
1213
db4970aa
YL		 1214static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1215{
1216 if (!skb->encapsulation)
1217 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1218
1219 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1220}
1221
1222/* HW need every continuous 8 buffer data to be larger than MSS,
1223 * we simplify it by ensuring skb_headlen + the first continuous
1224 * 7 frags to to be larger than gso header len + mss, and the remaining
1225 * continuous 7 frags to be larger than MSS except the last 7 frags.
1226 */
8ae10cfb
YL		 1227static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1228 unsigned int bd_num)
db4970aa 1229{
db4970aa
YL		 1230 unsigned int tot_len = 0;
1231 int i;
1232
8ae10cfb
YL		 1233 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1234 tot_len += bd_size[i];
db4970aa 1235
8ae10cfb
YL		 1236 /* ensure the first 8 frags is greater than mss + header */
1237 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1238 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
db4970aa
YL		 1239 return true;
1240
8ae10cfb
YL		 1241 /* ensure every continuous 7 buffer is greater than mss
1242 * except the last one.
1243 */
1244 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1245 tot_len -= bd_size[i];
1246 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
db4970aa
YL		 1247
1248 if (tot_len < skb_shinfo(skb)->gso_size)
1249 return true;
1250 }
1251
1252 return false;
1253}
1254
698a8954
YL		 1255void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1256{
1257 int i = 0;
1258
1259 for (i = 0; i < MAX_SKB_FRAGS; i++)
1260 size[i] = skb_frag_size(&shinfo->frags[i]);
1261}
1262
3d5f3741 1263static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
2a597eff 1264 struct net_device *netdev,
d1a37ded 1265 struct sk_buff *skb)
76ad4f0e 1266{
2a597eff 1267 struct hns3_nic_priv *priv = netdev_priv(netdev);
8ae10cfb 1268 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
42611b70 1269 unsigned int bd_num;
76ad4f0e 1270
8ae10cfb
YL		 1271 bd_num = hns3_tx_bd_num(skb, bd_size);
1272 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
8ae10cfb 1273 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
698a8954
YL		 1274 !hns3_skb_need_linearized(skb, bd_size, bd_num)) {
1275 trace_hns3_over_8bd(skb);
db4970aa 1276 goto out;
698a8954 1277 }
db4970aa 1278
d1a37ded 1279 if (__skb_linearize(skb))
51e8439f 1280 return -ENOMEM;
3d5f3741 1281
d1a37ded
YL		 1282 bd_num = hns3_tx_bd_count(skb->len);
1283 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1284 (!skb_is_gso(skb) &&
698a8954
YL		 1285 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1286 trace_hns3_over_8bd(skb);
42611b70 1287 return -ENOMEM;
698a8954 1288 }
42611b70 1289
3d5f3741
YL		 1290 u64_stats_update_begin(&ring->syncp);
1291 ring->stats.tx_copy++;
1292 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1293 }
1294
db4970aa 1295out:
2a597eff
YL		 1296 if (likely(ring_space(ring) >= bd_num))
1297 return bd_num;
76ad4f0e 1298
2a597eff
YL		 1299 netif_stop_subqueue(netdev, ring->queue_index);
1300 smp_mb(); /* Memory barrier before checking ring_space */
1301
1302 /* Start queue in case hns3_clean_tx_ring has just made room
1303 * available and has not seen the queue stopped state performed
1304 * by netif_stop_subqueue above.
1305 */
1306 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1307 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1308 netif_start_subqueue(netdev, ring->queue_index);
1309 return bd_num;
1310 }
1311
1312 return -EBUSY;
76ad4f0e
S		 1313}
1314
ba3f808f 1315static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1316{
1317 struct device *dev = ring_to_dev(ring);
1318 unsigned int i;
1319
1320 for (i = 0; i < ring->desc_num; i++) {
8ceca59f
YL		 1321 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1322
1323 memset(desc, 0, sizeof(*desc));
1324
76ad4f0e
S		 1325 /* check if this is where we started */
1326 if (ring->next_to_use == next_to_use_orig)
1327 break;
1328
aa9d22dd
YL		 1329 /* rollback one */
1330 ring_ptr_move_bw(ring, next_to_use);
1331
8ceca59f
YL		 1332 if (!ring->desc_cb[ring->next_to_use].dma)
1333 continue;
1334
76ad4f0e 1335 /* unmap the descriptor dma address */
74ef402e
HT		 1336 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
1337 ring->desc_cb[ring->next_to_use].type ==
1338 DESC_TYPE_FRAGLIST_SKB)
76ad4f0e
S		 1339 dma_unmap_single(dev,
1340 ring->desc_cb[ring->next_to_use].dma,
1341 ring->desc_cb[ring->next_to_use].length,
1342 DMA_TO_DEVICE);
bcdb12b7 1343 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1344 dma_unmap_page(dev,
1345 ring->desc_cb[ring->next_to_use].dma,
1346 ring->desc_cb[ring->next_to_use].length,
1347 DMA_TO_DEVICE);
1348
bcdb12b7 1349 ring->desc_cb[ring->next_to_use].length = 0;
aa9d22dd 1350 ring->desc_cb[ring->next_to_use].dma = 0;
8ceca59f 1351 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN;
76ad4f0e
S		 1352 }
1353}
1354
8ae10cfb
YL		 1355static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1356 struct sk_buff *skb, enum hns_desc_type type)
1357{
1358 unsigned int size = skb_headlen(skb);
1359 int i, ret, bd_num = 0;
1360
1361 if (size) {
1362 ret = hns3_fill_desc(ring, skb, size, type);
1363 if (unlikely(ret < 0))
1364 return ret;
1365
1366 bd_num += ret;
1367 }
1368
1369 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1370 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1371
1372 size = skb_frag_size(frag);
1373 if (!size)
1374 continue;
1375
1376 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1377 if (unlikely(ret < 0))
1378 return ret;
1379
1380 bd_num += ret;
1381 }
1382
1383 return bd_num;
1384}
1385
d43e5aca 1386netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1387{
1388 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f06b903 1389 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
76ad4f0e 1390 struct netdev_queue *dev_queue;
8ae10cfb
YL		 1391 int pre_ntu, next_to_use_head;
1392 struct sk_buff *frag_skb;
1393 int bd_num = 0;
76ad4f0e 1394 int ret;
76ad4f0e 1395
36c67349
YL		 1396 /* Hardware can only handle short frames above 32 bytes */
1397 if (skb_put_padto(skb, HNS3_MIN_TX_LEN))
1398 return NETDEV_TX_OK;
1399
76ad4f0e
S		 1400 /* Prefetch the data used later */
1401 prefetch(skb->data);
1402
d1a37ded 1403 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
8ae10cfb
YL		 1404 if (unlikely(ret <= 0)) {
1405 if (ret == -EBUSY) {
3d5f3741
YL		 1406 u64_stats_update_begin(&ring->syncp);
1407 ring->stats.tx_busy++;
1408 u64_stats_update_end(&ring->syncp);
2a597eff 1409 return NETDEV_TX_BUSY;
8ae10cfb 1410 } else if (ret == -ENOMEM) {
3d5f3741
YL		 1411 u64_stats_update_begin(&ring->syncp);
1412 ring->stats.sw_err_cnt++;
1413 u64_stats_update_end(&ring->syncp);
1414 }
76ad4f0e 1415
8ae10cfb 1416 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
76ad4f0e 1417 goto out_err_tx_ok;
76ad4f0e
S		 1418 }
1419
76ad4f0e
S		 1420 next_to_use_head = ring->next_to_use;
1421
cfdaeba5
YL		 1422 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use]);
1423 if (unlikely(ret < 0))
1424 goto fill_err;
1425
8ae10cfb
YL		 1426 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1427 if (unlikely(ret < 0))
aa9d22dd 1428 goto fill_err;
76ad4f0e 1429
8ae10cfb 1430 bd_num += ret;
5188f218 1431
8ae10cfb 1432 skb_walk_frags(skb, frag_skb) {
74ef402e
HT		 1433 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1434 DESC_TYPE_FRAGLIST_SKB);
8ae10cfb 1435 if (unlikely(ret < 0))
aa9d22dd 1436 goto fill_err;
8ae10cfb
YL		 1437
1438 bd_num += ret;
76ad4f0e 1439 }
5c6cfd30 1440
8ae10cfb
YL		 1441 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1442 (ring->desc_num - 1);
1443 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1444 cpu_to_le16(BIT(HNS3_TXD_FE_B));
698a8954 1445 trace_hns3_tx_desc(ring, pre_ntu);
76ad4f0e
S		 1446
1447 /* Complete translate all packets */
5f06b903 1448 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
76ad4f0e
S		 1449 netdev_tx_sent_queue(dev_queue, skb->len);
1450
1451 wmb(); /* Commit all data before submit */
1452
8ae10cfb 1453 hnae3_queue_xmit(ring->tqp, bd_num);
76ad4f0e
S		 1454
1455 return NETDEV_TX_OK;
1456
aa9d22dd 1457fill_err:
ba3f808f 1458 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1459
1460out_err_tx_ok:
1461 dev_kfree_skb_any(skb);
1462 return NETDEV_TX_OK;
76ad4f0e
S		 1463}
1464
1465static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1466{
9780cb97 1467 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1468 struct sockaddr *mac_addr = p;
1469 int ret;
1470
1471 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1472 return -EADDRNOTAVAIL;
1473
5ec2a51e
JS		 1474 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1475 netdev_info(netdev, "already using mac address %pM\n",
1476 mac_addr->sa_data);
1477 return 0;
1478 }
1479
8e6de441
HT		 1480 /* For VF device, if there is a perm_addr, then the user will not
1481 * be allowed to change the address.
1482 */
1483 if (!hns3_is_phys_func(h->pdev) &&
1484 !is_zero_ether_addr(netdev->perm_addr)) {
1485 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1486 netdev->perm_addr, mac_addr->sa_data);
1487 return -EPERM;
1488 }
1489
59098055 1490 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1491 if (ret) {
1492 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1493 return ret;
1494 }
1495
1496 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1497
1498 return 0;
1499}
1500
26483246
XW		 1501static int hns3_nic_do_ioctl(struct net_device *netdev,
1502 struct ifreq *ifr, int cmd)
1503{
1504 struct hnae3_handle *h = hns3_get_handle(netdev);
1505
1506 if (!netif_running(netdev))
1507 return -EINVAL;
1508
1509 if (!h->ae_algo->ops->do_ioctl)
1510 return -EOPNOTSUPP;
1511
1512 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1513}
1514
76ad4f0e
S		 1515static int hns3_nic_set_features(struct net_device *netdev,
1516 netdev_features_t features)
1517{
181d454b 1518 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1519 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1520 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1521 bool enable;
052ece6d 1522 int ret;
76ad4f0e 1523
5c9f6b39 1524 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 1525 enable = !!(features & NETIF_F_GRO_HW);
1526 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 1527 if (ret)
1528 return ret;
1529 }
1530
bd368416
JS		 1531 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1532 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 1533 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1534 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 1535 if (ret)
1536 return ret;
1537 }
1538
c17852a8 1539 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 1540 enable = !!(features & NETIF_F_NTUPLE);
1541 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 1542 }
1543
76ad4f0e
S		 1544 netdev->features = features;
1545 return 0;
1546}
1547
2a7556bb
YL		 1548static netdev_features_t hns3_features_check(struct sk_buff *skb,
1549 struct net_device *dev,
1550 netdev_features_t features)
1551{
1552#define HNS3_MAX_HDR_LEN 480U
1553#define HNS3_MAX_L4_HDR_LEN 60U
1554
1555 size_t len;
1556
1557 if (skb->ip_summed != CHECKSUM_PARTIAL)
1558 return features;
1559
1560 if (skb->encapsulation)
1561 len = skb_inner_transport_header(skb) - skb->data;
1562 else
1563 len = skb_transport_header(skb) - skb->data;
1564
1565 /* Assume L4 is 60 byte as TCP is the only protocol with a
1566 * a flexible value, and it's max len is 60 bytes.
1567 */
1568 len += HNS3_MAX_L4_HDR_LEN;
1569
1570 /* Hardware only supports checksum on the skb with a max header
1571 * len of 480 bytes.
1572 */
1573 if (len > HNS3_MAX_HDR_LEN)
1574 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1575
1576 return features;
1577}
1578
6c88d9d7
PL		 1579static void hns3_nic_get_stats64(struct net_device *netdev,
1580 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1581{
1582 struct hns3_nic_priv *priv = netdev_priv(netdev);
1583 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1584 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1585 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 1586 u64 rx_length_errors = 0;
1587 u64 rx_crc_errors = 0;
1588 u64 rx_multicast = 0;
76ad4f0e 1589 unsigned int start;
d3ec4ef6
JS		 1590 u64 tx_errors = 0;
1591 u64 rx_errors = 0;
76ad4f0e
S		 1592 unsigned int idx;
1593 u64 tx_bytes = 0;
1594 u64 rx_bytes = 0;
1595 u64 tx_pkts = 0;
1596 u64 rx_pkts = 0;
d2a5dca8
JS		 1597 u64 tx_drop = 0;
1598 u64 rx_drop = 0;
76ad4f0e 1599
b875cc37
JS		 1600 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1601 return;
1602
c5f65480
JS		 1603 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1604
76ad4f0e
S		 1605 for (idx = 0; idx < queue_num; idx++) {
1606 /* fetch the tx stats */
5f06b903 1607 ring = &priv->ring[idx];
76ad4f0e 1608 do {
d36d36ce 1609 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1610 tx_bytes += ring->stats.tx_bytes;
1611 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1612 tx_drop += ring->stats.sw_err_cnt;
b20d7fe5
YL		 1613 tx_drop += ring->stats.tx_vlan_err;
1614 tx_drop += ring->stats.tx_l4_proto_err;
1615 tx_drop += ring->stats.tx_l2l3l4_err;
1616 tx_drop += ring->stats.tx_tso_err;
d3ec4ef6 1617 tx_errors += ring->stats.sw_err_cnt;
b20d7fe5
YL		 1618 tx_errors += ring->stats.tx_vlan_err;
1619 tx_errors += ring->stats.tx_l4_proto_err;
1620 tx_errors += ring->stats.tx_l2l3l4_err;
1621 tx_errors += ring->stats.tx_tso_err;
76ad4f0e
S		 1622 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1623
1624 /* fetch the rx stats */
5f06b903 1625 ring = &priv->ring[idx + queue_num];
76ad4f0e 1626 do {
d36d36ce 1627 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1628 rx_bytes += ring->stats.rx_bytes;
1629 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1630 rx_drop += ring->stats.l2_err;
d3ec4ef6 1631 rx_errors += ring->stats.l2_err;
8b552079 1632 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 1633 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS		 1634 rx_multicast += ring->stats.rx_multicast;
1635 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 1636 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1637 }
1638
1639 stats->tx_bytes = tx_bytes;
1640 stats->tx_packets = tx_pkts;
1641 stats->rx_bytes = rx_bytes;
1642 stats->rx_packets = rx_pkts;
1643
d3ec4ef6
JS		 1644 stats->rx_errors = rx_errors;
1645 stats->multicast = rx_multicast;
1646 stats->rx_length_errors = rx_length_errors;
1647 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 1648 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1649
d3ec4ef6
JS		 1650 stats->tx_errors = tx_errors;
1651 stats->rx_dropped = rx_drop;
1652 stats->tx_dropped = tx_drop;
76ad4f0e
S		 1653 stats->collisions = netdev->stats.collisions;
1654 stats->rx_over_errors = netdev->stats.rx_over_errors;
1655 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1656 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1657 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1658 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1659 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1660 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1661 stats->tx_window_errors = netdev->stats.tx_window_errors;
1662 stats->rx_compressed = netdev->stats.rx_compressed;
1663 stats->tx_compressed = netdev->stats.tx_compressed;
1664}
1665
30d240df 1666static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1667{
30d240df 1668 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
30d240df 1669 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
75718800 1670 struct hnae3_knic_private_info *kinfo;
30d240df
YL		 1671 u8 tc = mqprio_qopt->qopt.num_tc;
1672 u16 mode = mqprio_qopt->mode;
1673 u8 hw = mqprio_qopt->qopt.hw;
75718800 1674 struct hnae3_handle *h;
76ad4f0e 1675
30d240df
YL		 1676 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1677 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1678 return -EOPNOTSUPP;
1679
76ad4f0e
S		 1680 if (tc > HNAE3_MAX_TC)
1681 return -EINVAL;
1682
76ad4f0e
S		 1683 if (!netdev)
1684 return -EINVAL;
1685
75718800
YL		 1686 h = hns3_get_handle(netdev);
1687 kinfo = &h->kinfo;
1688
1c822948
YL		 1689 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1690
1cce5eb6 1691 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
5eb01ddf 1692 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
76ad4f0e
S		 1693}
1694
2572ac53 1695static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1696 void *type_data)
76ad4f0e 1697{
575ed7d3 1698 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1699 return -EOPNOTSUPP;
76ad4f0e 1700
30d240df 1701 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1702}
1703
1704static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1705 __be16 proto, u16 vid)
1706{
9780cb97 1707 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1708 int ret = -EIO;
1709
1710 if (h->ae_algo->ops->set_vlan_filter)
1711 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1712
1713 return ret;
1714}
1715
1716static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1717 __be16 proto, u16 vid)
1718{
9780cb97 1719 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1720 int ret = -EIO;
1721
1722 if (h->ae_algo->ops->set_vlan_filter)
1723 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1724
7fa6be4f 1725 return ret;
681ec399
YL		 1726}
1727
76ad4f0e
S		 1728static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1729 u8 qos, __be16 vlan_proto)
1730{
9780cb97 1731 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1732 int ret = -EIO;
1733
1c822948 1734 netif_dbg(h, drv, netdev,
39edaf24
GL		 1735 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1736 vf, vlan, qos, ntohs(vlan_proto));
1c822948 1737
76ad4f0e
S		 1738 if (h->ae_algo->ops->set_vf_vlan_filter)
1739 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 1740 qos, vlan_proto);
76ad4f0e
S		 1741
1742 return ret;
1743}
1744
22044f95
JS		 1745static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1746{
1747 struct hnae3_handle *handle = hns3_get_handle(netdev);
1748
1749 if (hns3_nic_resetting(netdev))
1750 return -EBUSY;
1751
1752 if (!handle->ae_algo->ops->set_vf_spoofchk)
1753 return -EOPNOTSUPP;
1754
1755 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1756}
1757
e196ec75
JS		 1758static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1759{
1760 struct hnae3_handle *handle = hns3_get_handle(netdev);
1761
1762 if (!handle->ae_algo->ops->set_vf_trust)
1763 return -EOPNOTSUPP;
1764
1765 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1766}
1767
a8e8b7ff
S		 1768static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1769{
9780cb97 1770 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1771 int ret;
1772
6ff7ed80
HT		 1773 if (hns3_nic_resetting(netdev))
1774 return -EBUSY;
1775
a8e8b7ff
S		 1776 if (!h->ae_algo->ops->set_mtu)
1777 return -EOPNOTSUPP;
1778
1c822948
YL		 1779 netif_dbg(h, drv, netdev,
1780 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1781
a8e8b7ff 1782 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1783 if (ret)
a8e8b7ff
S		 1784 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1785 ret);
93d8daf4
YL		 1786 else
1787 netdev->mtu = new_mtu;
5bad95a1 1788
a8e8b7ff
S		 1789 return ret;
1790}
1791
f8fa222c
L		 1792static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1793{
1794 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1795 struct hnae3_handle *h = hns3_get_handle(ndev);
0bfdf286 1796 struct hns3_enet_ring *tx_ring;
e511c97d 1797 struct napi_struct *napi;
f8fa222c
L		 1798 int timeout_queue = 0;
1799 int hw_head, hw_tail;
e511c97d
JS		 1800 int fbd_num, fbd_oft;
1801 int ebd_num, ebd_oft;
1802 int bd_num, bd_err;
1803 int ring_en, tc;
f8fa222c
L		 1804 int i;
1805
1806 /* Find the stopped queue the same way the stack does */
fa6c4084 1807 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 1808 struct netdev_queue *q;
1809 unsigned long trans_start;
1810
1811 q = netdev_get_tx_queue(ndev, i);
1812 trans_start = q->trans_start;
1813 if (netif_xmit_stopped(q) &&
1814 time_after(jiffies,
1815 (trans_start + ndev->watchdog_timeo))) {
1816 timeout_queue = i;
647522a5
YL		 1817 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1818 q->state,
1819 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L		 1820 break;
1821 }
1822 }
1823
1824 if (i == ndev->num_tx_queues) {
1825 netdev_info(ndev,
1826 "no netdev TX timeout queue found, timeout count: %llu\n",
1827 priv->tx_timeout_count);
1828 return false;
1829 }
1830
beab694a
JS		 1831 priv->tx_timeout_count++;
1832
5f06b903 1833 tx_ring = &priv->ring[timeout_queue];
e511c97d
JS		 1834 napi = &tx_ring->tqp_vector->napi;
1835
1836 netdev_info(ndev,
1837 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1838 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1839 tx_ring->next_to_clean, napi->state);
1840
1841 netdev_info(ndev,
1842 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1843 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1844 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1845
1846 netdev_info(ndev,
1847 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1848 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1849 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1850
1851 /* When mac received many pause frames continuous, it's unable to send
1852 * packets, which may cause tx timeout
1853 */
615466ce
YM		 1854 if (h->ae_algo->ops->get_mac_stats) {
1855 struct hns3_mac_stats mac_stats;
e511c97d 1856
615466ce 1857 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
e511c97d 1858 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
615466ce 1859 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
e511c97d 1860 }
f8fa222c
L		 1861
1862 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1863 HNS3_RING_TX_RING_HEAD_REG);
1864 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1865 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 1866 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1867 HNS3_RING_TX_RING_FBDNUM_REG);
1868 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1869 HNS3_RING_TX_RING_OFFSET_REG);
1870 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1871 HNS3_RING_TX_RING_EBDNUM_REG);
1872 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1873 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1874 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1875 HNS3_RING_TX_RING_BD_NUM_REG);
1876 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1877 HNS3_RING_TX_RING_BD_ERR_REG);
1878 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1879 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1880
f8fa222c 1881 netdev_info(ndev,
e511c97d
JS		 1882 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1883 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 1884 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 1885 netdev_info(ndev,
1886 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1887 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 1888
1889 return true;
1890}
1891
0290bd29 1892static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
f8fa222c
L		 1893{
1894 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1895 struct hnae3_handle *h = priv->ae_handle;
1896
1897 if (!hns3_get_tx_timeo_queue_info(ndev))
1898 return;
1899
0742ed7c
HT		 1900 /* request the reset, and let the hclge to determine
1901 * which reset level should be done
1902 */
f8fa222c 1903 if (h->ae_algo->ops->reset_event)
6ae4e733 1904 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1905}
1906
d93ed94f
JS		 1907#ifdef CONFIG_RFS_ACCEL
1908static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1909 u16 rxq_index, u32 flow_id)
1910{
1911 struct hnae3_handle *h = hns3_get_handle(dev);
1912 struct flow_keys fkeys;
1913
1914 if (!h->ae_algo->ops->add_arfs_entry)
1915 return -EOPNOTSUPP;
1916
1917 if (skb->encapsulation)
1918 return -EPROTONOSUPPORT;
1919
1920 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1921 return -EPROTONOSUPPORT;
1922
1923 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1924 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1925 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1926 fkeys.basic.ip_proto != IPPROTO_UDP))
1927 return -EPROTONOSUPPORT;
1928
1929 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1930}
1931#endif
1932
6430f744
YM		 1933static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1934 struct ifla_vf_info *ivf)
1935{
1936 struct hnae3_handle *h = hns3_get_handle(ndev);
1937
1938 if (!h->ae_algo->ops->get_vf_config)
1939 return -EOPNOTSUPP;
1940
1941 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1942}
1943
1944static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1945 int link_state)
1946{
1947 struct hnae3_handle *h = hns3_get_handle(ndev);
1948
1949 if (!h->ae_algo->ops->set_vf_link_state)
1950 return -EOPNOTSUPP;
1951
1952 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1953}
1954
ee9e4424
YL		 1955static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1956 int min_tx_rate, int max_tx_rate)
1957{
1958 struct hnae3_handle *h = hns3_get_handle(ndev);
1959
1960 if (!h->ae_algo->ops->set_vf_rate)
1961 return -EOPNOTSUPP;
1962
1963 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1964 false);
1965}
1966
8e6de441
HT		 1967static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1968{
1969 struct hnae3_handle *h = hns3_get_handle(netdev);
1970
1971 if (!h->ae_algo->ops->set_vf_mac)
1972 return -EOPNOTSUPP;
1973
1974 if (is_multicast_ether_addr(mac)) {
1975 netdev_err(netdev,
1976 "Invalid MAC:%pM specified. Could not set MAC\n",
1977 mac);
1978 return -EINVAL;
1979 }
1980
1981 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
1982}
1983
76ad4f0e
S		 1984static const struct net_device_ops hns3_nic_netdev_ops = {
1985 .ndo_open = hns3_nic_net_open,
1986 .ndo_stop = hns3_nic_net_stop,
1987 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1988 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1989 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1990 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1991 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e 1992 .ndo_set_features = hns3_nic_set_features,
2a7556bb 1993 .ndo_features_check = hns3_features_check,
76ad4f0e
S		 1994 .ndo_get_stats64 = hns3_nic_get_stats64,
1995 .ndo_setup_tc = hns3_nic_setup_tc,
1996 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1997 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1998 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1999 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
22044f95 2000 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
e196ec75 2001 .ndo_set_vf_trust = hns3_set_vf_trust,
d93ed94f
JS		 2002#ifdef CONFIG_RFS_ACCEL
2003 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2004#endif
6430f744
YM		 2005 .ndo_get_vf_config = hns3_nic_get_vf_config,
2006 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
ee9e4424 2007 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
8e6de441 2008 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
76ad4f0e
S		 2009};
2010
97afd47b 2011bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 2012{
2013 u32 dev_id = pdev->device;
2014
2015 switch (dev_id) {
2016 case HNAE3_DEV_ID_GE:
2017 case HNAE3_DEV_ID_25GE:
2018 case HNAE3_DEV_ID_25GE_RDMA:
2019 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2020 case HNAE3_DEV_ID_50GE_RDMA:
2021 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2022 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2023 return true;
2024 case HNAE3_DEV_ID_100G_VF:
2025 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2026 return false;
2027 default:
adcf738b 2028 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2312e050
FL		 2029 dev_id);
2030 }
2031
2032 return false;
2033}
2034
2312e050
FL		 2035static void hns3_disable_sriov(struct pci_dev *pdev)
2036{
2037 /* If our VFs are assigned we cannot shut down SR-IOV
2038 * without causing issues, so just leave the hardware
2039 * available but disabled
2040 */
2041 if (pci_vfs_assigned(pdev)) {
2042 dev_warn(&pdev->dev,
2043 "disabling driver while VFs are assigned\n");
2044 return;
2045 }
2046
2047 pci_disable_sriov(pdev);
2048}
2049
d695964d
JS		 2050static void hns3_get_dev_capability(struct pci_dev *pdev,
2051 struct hnae3_ae_dev *ae_dev)
2052{
b26a6fea 2053 if (pdev->revision >= 0x21) {
d695964d 2054 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL		 2055 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2056 }
d695964d
JS		 2057}
2058
76ad4f0e
S		 2059/* hns3_probe - Device initialization routine
2060 * @pdev: PCI device information struct
2061 * @ent: entry in hns3_pci_tbl
2062 *
2063 * hns3_probe initializes a PF identified by a pci_dev structure.
2064 * The OS initialization, configuring of the PF private structure,
2065 * and a hardware reset occur.
2066 *
2067 * Returns 0 on success, negative on failure
2068 */
2069static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2070{
2071 struct hnae3_ae_dev *ae_dev;
2072 int ret;
2073
9b2f3477 2074 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
60df7e91
HT		 2075 if (!ae_dev)
2076 return -ENOMEM;
76ad4f0e
S		 2077
2078 ae_dev->pdev = pdev;
e92a0843 2079 ae_dev->flag = ent->driver_data;
d695964d 2080 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 2081 pci_set_drvdata(pdev, ae_dev);
2082
74354140 2083 ret = hnae3_register_ae_dev(ae_dev);
674a1357 2084 if (ret)
74354140 2085 pci_set_drvdata(pdev, NULL);
2312e050 2086
74354140 2087 return ret;
76ad4f0e
S		 2088}
2089
2090/* hns3_remove - Device removal routine
2091 * @pdev: PCI device information struct
2092 */
2093static void hns3_remove(struct pci_dev *pdev)
2094{
2095 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2096
2312e050
FL		 2097 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2098 hns3_disable_sriov(pdev);
2099
76ad4f0e 2100 hnae3_unregister_ae_dev(ae_dev);
ac864c23 2101 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 2102}
2103
fa8d82e8
PL		 2104/**
2105 * hns3_pci_sriov_configure
2106 * @pdev: pointer to a pci_dev structure
2107 * @num_vfs: number of VFs to allocate
2108 *
2109 * Enable or change the number of VFs. Called when the user updates the number
2110 * of VFs in sysfs.
2111 **/
743e1a84 2112static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 2113{
2114 int ret;
2115
2116 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2117 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2118 return -EINVAL;
2119 }
2120
2121 if (num_vfs) {
2122 ret = pci_enable_sriov(pdev, num_vfs);
2123 if (ret)
2124 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 2125 else
2126 return num_vfs;
fa8d82e8
PL		 2127 } else if (!pci_vfs_assigned(pdev)) {
2128 pci_disable_sriov(pdev);
2129 } else {
2130 dev_warn(&pdev->dev,
2131 "Unable to free VFs because some are assigned to VMs.\n");
2132 }
2133
2134 return 0;
2135}
2136
ce2c1d2e
YL		 2137static void hns3_shutdown(struct pci_dev *pdev)
2138{
2139 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2140
2141 hnae3_unregister_ae_dev(ae_dev);
ce2c1d2e
YL		 2142 pci_set_drvdata(pdev, NULL);
2143
2144 if (system_state == SYSTEM_POWER_OFF)
2145 pci_set_power_state(pdev, PCI_D3hot);
2146}
2147
5a9f0eac
SJ		 2148static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2149 pci_channel_state_t state)
2150{
2151 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2152 pci_ers_result_t ret;
2153
2154 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2155
2156 if (state == pci_channel_io_perm_failure)
2157 return PCI_ERS_RESULT_DISCONNECT;
2158
661262bc 2159 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 2160 dev_err(&pdev->dev,
661262bc 2161 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ		 2162 return PCI_ERS_RESULT_NONE;
2163 }
2164
381c356e
SJ		 2165 if (ae_dev->ops->handle_hw_ras_error)
2166 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 2167 else
2168 return PCI_ERS_RESULT_NONE;
2169
2170 return ret;
2171}
2172
6ae4e733
SJ		 2173static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2174{
2175 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 2176 const struct hnae3_ae_ops *ops;
123297b7 2177 enum hnae3_reset_type reset_type;
6ae4e733
SJ		 2178 struct device *dev = &pdev->dev;
2179
661262bc
WL		 2180 if (!ae_dev || !ae_dev->ops)
2181 return PCI_ERS_RESULT_NONE;
2182
ad9bf545 2183 ops = ae_dev->ops;
6ae4e733 2184 /* request the reset */
fa17c708
GH		 2185 if (ops->reset_event && ops->get_reset_level &&
2186 ops->set_default_reset_request) {
9d5e67d1 2187 if (ae_dev->hw_err_reset_req) {
123297b7
SJ		 2188 reset_type = ops->get_reset_level(ae_dev,
2189 &ae_dev->hw_err_reset_req);
2190 ops->set_default_reset_request(ae_dev, reset_type);
2191 dev_info(dev, "requesting reset due to PCI error\n");
2192 ops->reset_event(pdev, NULL);
2193 }
69b51bbb 2194
6ae4e733
SJ		 2195 return PCI_ERS_RESULT_RECOVERED;
2196 }
2197
2198 return PCI_ERS_RESULT_DISCONNECT;
2199}
2200
6b9a97ee
HT		 2201static void hns3_reset_prepare(struct pci_dev *pdev)
2202{
2203 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2204
8de91e92 2205 dev_info(&pdev->dev, "FLR prepare\n");
6b9a97ee
HT		 2206 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2207 ae_dev->ops->flr_prepare(ae_dev);
2208}
2209
2210static void hns3_reset_done(struct pci_dev *pdev)
2211{
2212 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2213
8de91e92 2214 dev_info(&pdev->dev, "FLR done\n");
6b9a97ee
HT		 2215 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2216 ae_dev->ops->flr_done(ae_dev);
2217}
2218
5a9f0eac
SJ		 2219static const struct pci_error_handlers hns3_err_handler = {
2220 .error_detected = hns3_error_detected,
6ae4e733 2221 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 2222 .reset_prepare = hns3_reset_prepare,
2223 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 2224};
2225
76ad4f0e
S		 2226static struct pci_driver hns3_driver = {
2227 .name = hns3_driver_name,
2228 .id_table = hns3_pci_tbl,
2229 .probe = hns3_probe,
2230 .remove = hns3_remove,
ce2c1d2e 2231 .shutdown = hns3_shutdown,
fa8d82e8 2232 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 2233 .err_handler = &hns3_err_handler,
76ad4f0e
S		 2234};
2235
2236/* set default feature to hns3 */
2237static void hns3_set_default_feature(struct net_device *netdev)
2238{
3e85af6a
PL		 2239 struct hnae3_handle *h = hns3_get_handle(netdev);
2240 struct pci_dev *pdev = h->pdev;
2241
76ad4f0e
S		 2242 netdev->priv_flags |= IFF_UNICAST_FLT;
2243
2244 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2245 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2246 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2247 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2248 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2249 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
76ad4f0e
S		 2250
2251 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2252
2253 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2254 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2255 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2256 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2257 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2258 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2259 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2260 NETIF_F_FRAGLIST;
76ad4f0e
S		 2261
2262 netdev->vlan_features |=
2263 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2264 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2265 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2266 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2267 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2268 NETIF_F_FRAGLIST;
76ad4f0e
S		 2269
2270 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 2271 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2272 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2273 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2274 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2275 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2276 NETIF_F_FRAGLIST;
3e85af6a 2277
c17852a8 2278 if (pdev->revision >= 0x21) {
77af09c6 2279 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2280 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 2281
2282 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2283 netdev->hw_features |= NETIF_F_NTUPLE;
2284 netdev->features |= NETIF_F_NTUPLE;
2285 }
2286 }
76ad4f0e
S		 2287}
2288
2289static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2290 struct hns3_desc_cb *cb)
2291{
dbba6da0 2292 unsigned int order = hns3_page_order(ring);
76ad4f0e
S		 2293 struct page *p;
2294
2295 p = dev_alloc_pages(order);
2296 if (!p)
2297 return -ENOMEM;
2298
2299 cb->priv = p;
2300 cb->page_offset = 0;
2301 cb->reuse_flag = 0;
2302 cb->buf = page_address(p);
dbba6da0 2303 cb->length = hns3_page_size(ring);
76ad4f0e
S		 2304 cb->type = DESC_TYPE_PAGE;
2305
76ad4f0e
S		 2306 return 0;
2307}
2308
2309static void hns3_free_buffer(struct hns3_enet_ring *ring,
2310 struct hns3_desc_cb *cb)
2311{
2312 if (cb->type == DESC_TYPE_SKB)
2313 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2314 else if (!HNAE3_IS_TX_RING(ring))
2315 put_page((struct page *)cb->priv);
2316 memset(cb, 0, sizeof(*cb));
2317}
2318
2319static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2320{
2321 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2322 cb->length, ring_to_dma_dir(ring));
2323
2211f4e1 2324 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 2325 return -EIO;
2326
2327 return 0;
2328}
2329
2330static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2331 struct hns3_desc_cb *cb)
2332{
74ef402e 2333 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
76ad4f0e
S		 2334 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2335 ring_to_dma_dir(ring));
bcdb12b7 2336 else if (cb->length)
76ad4f0e
S		 2337 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2338 ring_to_dma_dir(ring));
2339}
2340
2341static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2342{
2343 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2344 ring->desc[i].addr = 0;
2345}
2346
2347static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2348{
2349 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2350
2351 if (!ring->desc_cb[i].dma)
2352 return;
2353
2354 hns3_buffer_detach(ring, i);
2355 hns3_free_buffer(ring, cb);
2356}
2357
2358static void hns3_free_buffers(struct hns3_enet_ring *ring)
2359{
2360 int i;
2361
2362 for (i = 0; i < ring->desc_num; i++)
2363 hns3_free_buffer_detach(ring, i);
2364}
2365
2366/* free desc along with its attached buffer */
2367static void hns3_free_desc(struct hns3_enet_ring *ring)
2368{
024cc792
HT		 2369 int size = ring->desc_num * sizeof(ring->desc[0]);
2370
76ad4f0e
S		 2371 hns3_free_buffers(ring);
2372
024cc792
HT		 2373 if (ring->desc) {
2374 dma_free_coherent(ring_to_dev(ring), size,
2375 ring->desc, ring->desc_dma_addr);
2376 ring->desc = NULL;
2377 }
76ad4f0e
S		 2378}
2379
2380static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2381{
2382 int size = ring->desc_num * sizeof(ring->desc[0]);
2383
750afb08
LC		 2384 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2385 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 2386 if (!ring->desc)
2387 return -ENOMEM;
2388
76ad4f0e
S		 2389 return 0;
2390}
2391
4d2cad32 2392static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
76ad4f0e
S		 2393 struct hns3_desc_cb *cb)
2394{
2395 int ret;
2396
2397 ret = hns3_alloc_buffer(ring, cb);
2398 if (ret)
2399 goto out;
2400
2401 ret = hns3_map_buffer(ring, cb);
2402 if (ret)
2403 goto out_with_buf;
2404
2405 return 0;
2406
2407out_with_buf:
564883bb 2408 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2409out:
2410 return ret;
2411}
2412
4d2cad32 2413static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
76ad4f0e 2414{
4d2cad32 2415 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2416
2417 if (ret)
2418 return ret;
2419
2420 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2421
2422 return 0;
2423}
2424
2425/* Allocate memory for raw pkg, and map with dma */
2426static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2427{
2428 int i, j, ret;
2429
2430 for (i = 0; i < ring->desc_num; i++) {
4d2cad32 2431 ret = hns3_alloc_and_attach_buffer(ring, i);
76ad4f0e
S		 2432 if (ret)
2433 goto out_buffer_fail;
2434 }
2435
2436 return 0;
2437
2438out_buffer_fail:
2439 for (j = i - 1; j >= 0; j--)
2440 hns3_free_buffer_detach(ring, j);
2441 return ret;
2442}
2443
9b2f3477 2444/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S		 2445static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2446 struct hns3_desc_cb *res_cb)
2447{
b9077428 2448 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2449 ring->desc_cb[i] = *res_cb;
2450 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2451 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2452}
2453
2454static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2455{
2456 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL		 2457 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2458 ring->desc_cb[i].page_offset);
7d0b130c 2459 ring->desc[i].rx.bd_base_info = 0;
c2a2e127
BS		 2460
2461 dma_sync_single_for_device(ring_to_dev(ring),
2462 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
2463 hns3_buf_size(ring),
2464 DMA_FROM_DEVICE);
76ad4f0e
S		 2465}
2466
ce74370c
YL		 2467static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2468 int *bytes, int *pkts)
76ad4f0e 2469{
26cda2f1
YL		 2470 int ntc = ring->next_to_clean;
2471 struct hns3_desc_cb *desc_cb;
76ad4f0e 2472
ce74370c
YL		 2473 while (head != ntc) {
2474 desc_cb = &ring->desc_cb[ntc];
2475 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2476 (*bytes) += desc_cb->length;
2477 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2478 hns3_free_buffer_detach(ring, ntc);
76ad4f0e 2479
ce74370c
YL		 2480 if (++ntc == ring->desc_num)
2481 ntc = 0;
2482
2483 /* Issue prefetch for next Tx descriptor */
2484 prefetch(&ring->desc_cb[ntc]);
2485 }
26cda2f1
YL		 2486
2487 /* This smp_store_release() pairs with smp_load_acquire() in
2488 * ring_space called by hns3_nic_net_xmit.
2489 */
2490 smp_store_release(&ring->next_to_clean, ntc);
76ad4f0e
S		 2491}
2492
2493static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2494{
2495 int u = ring->next_to_use;
2496 int c = ring->next_to_clean;
2497
2498 if (unlikely(h > ring->desc_num))
2499 return 0;
2500
2501 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2502}
2503
799997a3 2504void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e 2505{
c8711956 2506 struct net_device *netdev = ring_to_netdev(ring);
7a810110 2507 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2508 struct netdev_queue *dev_queue;
2509 int bytes, pkts;
2510 int head;
2511
2512 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
76ad4f0e
S		 2513
2514 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2515 return; /* no data to poll */
76ad4f0e 2516
88b7c58c
YL		 2517 rmb(); /* Make sure head is ready before touch any data */
2518
0e6084aa 2519 if (unlikely(!is_valid_clean_head(ring, head))) {
09783d44
YL		 2520 hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head,
2521 ring->next_to_use, ring->next_to_clean);
76ad4f0e
S		 2522
2523 u64_stats_update_begin(&ring->syncp);
2524 ring->stats.io_err_cnt++;
2525 u64_stats_update_end(&ring->syncp);
799997a3 2526 return;
76ad4f0e
S		 2527 }
2528
2529 bytes = 0;
2530 pkts = 0;
ce74370c 2531 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
76ad4f0e
S		 2532
2533 ring->tqp_vector->tx_group.total_bytes += bytes;
2534 ring->tqp_vector->tx_group.total_packets += pkts;
2535
2536 u64_stats_update_begin(&ring->syncp);
2537 ring->stats.tx_bytes += bytes;
2538 ring->stats.tx_pkts += pkts;
2539 u64_stats_update_end(&ring->syncp);
2540
2541 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2542 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2543
2a597eff 2544 if (unlikely(netif_carrier_ok(netdev) &&
8ae10cfb 2545 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
76ad4f0e
S		 2546 /* Make sure that anybody stopping the queue after this
2547 * sees the new next_to_clean.
2548 */
2549 smp_mb();
7a810110
JS		 2550 if (netif_tx_queue_stopped(dev_queue) &&
2551 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2552 netif_tx_wake_queue(dev_queue);
2553 ring->stats.restart_queue++;
2554 }
2555 }
76ad4f0e
S		 2556}
2557
2558static int hns3_desc_unused(struct hns3_enet_ring *ring)
2559{
2560 int ntc = ring->next_to_clean;
2561 int ntu = ring->next_to_use;
2562
2563 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2564}
2565
9b2f3477
WL		 2566static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2567 int cleand_count)
76ad4f0e
S		 2568{
2569 struct hns3_desc_cb *desc_cb;
2570 struct hns3_desc_cb res_cbs;
2571 int i, ret;
2572
2573 for (i = 0; i < cleand_count; i++) {
2574 desc_cb = &ring->desc_cb[ring->next_to_use];
2575 if (desc_cb->reuse_flag) {
2576 u64_stats_update_begin(&ring->syncp);
2577 ring->stats.reuse_pg_cnt++;
2578 u64_stats_update_end(&ring->syncp);
2579
2580 hns3_reuse_buffer(ring, ring->next_to_use);
2581 } else {
4d2cad32 2582 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
76ad4f0e
S		 2583 if (ret) {
2584 u64_stats_update_begin(&ring->syncp);
2585 ring->stats.sw_err_cnt++;
2586 u64_stats_update_end(&ring->syncp);
2587
c8711956 2588 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5
YL		 2589 "alloc rx buffer failed: %d\n",
2590 ret);
76ad4f0e
S		 2591 break;
2592 }
2593 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 2594
2595 u64_stats_update_begin(&ring->syncp);
2596 ring->stats.non_reuse_pg++;
2597 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 2598 }
2599
2600 ring_ptr_move_fw(ring, next_to_use);
2601 }
2602
2603 wmb(); /* Make all data has been write before submit */
2604 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2605}
2606
08bb3857
YL		 2607static bool hns3_page_is_reusable(struct page *page)
2608{
2609 return page_to_nid(page) == numa_mem_id() &&
2610 !page_is_pfmemalloc(page);
2611}
2612
76ad4f0e
S		 2613static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2614 struct hns3_enet_ring *ring, int pull_len,
2615 struct hns3_desc_cb *desc_cb)
2616{
389ca146
YL		 2617 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2618 int size = le16_to_cpu(desc->rx.size);
dbba6da0 2619 u32 truesize = hns3_buf_size(ring);
76ad4f0e
S		 2620
2621 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2622 size - pull_len, truesize);
76ad4f0e 2623
389ca146
YL		 2624 /* Avoid re-using remote pages, or the stack is still using the page
2625 * when page_offset rollback to zero, flag default unreuse
2626 */
08bb3857 2627 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
389ca146 2628 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
76ad4f0e 2629 return;
76ad4f0e
S		 2630
2631 /* Move offset up to the next cache line */
2632 desc_cb->page_offset += truesize;
2633
dbba6da0 2634 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
76ad4f0e 2635 desc_cb->reuse_flag = 1;
9b2f3477 2636 /* Bump ref count on page before it is given */
76ad4f0e 2637 get_page(desc_cb->priv);
389ca146
YL		 2638 } else if (page_count(desc_cb->priv) == 1) {
2639 desc_cb->reuse_flag = 1;
2640 desc_cb->page_offset = 0;
2641 get_page(desc_cb->priv);
76ad4f0e
S		 2642 }
2643}
2644
e2ee1c5a 2645static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL		 2646{
2647 __be16 type = skb->protocol;
2648 struct tcphdr *th;
2649 int depth = 0;
2650
e2ee1c5a 2651 while (eth_type_vlan(type)) {
d474d88f
YL		 2652 struct vlan_hdr *vh;
2653
2654 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2655 return -EFAULT;
2656
2657 vh = (struct vlan_hdr *)(skb->data + depth);
2658 type = vh->h_vlan_encapsulated_proto;
2659 depth += VLAN_HLEN;
2660 }
2661
e2ee1c5a
YL		 2662 skb_set_network_header(skb, depth);
2663
d474d88f 2664 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL		 2665 const struct iphdr *iph = ip_hdr(skb);
2666
d474d88f 2667 depth += sizeof(struct iphdr);
e2ee1c5a
YL		 2668 skb_set_transport_header(skb, depth);
2669 th = tcp_hdr(skb);
2670 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2671 iph->daddr, 0);
d474d88f 2672 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL		 2673 const struct ipv6hdr *iph = ipv6_hdr(skb);
2674
d474d88f 2675 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL		 2676 skb_set_transport_header(skb, depth);
2677 th = tcp_hdr(skb);
2678 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2679 &iph->daddr, 0);
d474d88f 2680 } else {
b20d7fe5
YL		 2681 hns3_rl_err(skb->dev,
2682 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2683 be16_to_cpu(type), depth);
d474d88f
YL		 2684 return -EFAULT;
2685 }
2686
d474d88f
YL		 2687 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2688 if (th->cwr)
2689 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2690
e2ee1c5a
YL		 2691 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2692 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 2693
e2ee1c5a
YL		 2694 skb->csum_start = (unsigned char *)th - skb->head;
2695 skb->csum_offset = offsetof(struct tcphdr, check);
2696 skb->ip_summed = CHECKSUM_PARTIAL;
698a8954
YL		 2697
2698 trace_hns3_gro(skb);
2699
d474d88f
YL		 2700 return 0;
2701}
2702
76ad4f0e 2703static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
39c38824 2704 u32 l234info, u32 bd_base_info, u32 ol_info)
76ad4f0e 2705{
c8711956 2706 struct net_device *netdev = ring_to_netdev(ring);
76ad4f0e 2707 int l3_type, l4_type;
76ad4f0e 2708 int ol4_type;
76ad4f0e
S		 2709
2710 skb->ip_summed = CHECKSUM_NONE;
2711
2712 skb_checksum_none_assert(skb);
2713
2714 if (!(netdev->features & NETIF_F_RXCSUM))
2715 return;
2716
2717 /* check if hardware has done checksum */
e8149933 2718 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S		 2719 return;
2720
f4772dee
DC		 2721 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2722 BIT(HNS3_RXD_OL3E_B) |
e8149933 2723 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S		 2724 u64_stats_update_begin(&ring->syncp);
2725 ring->stats.l3l4_csum_err++;
2726 u64_stats_update_end(&ring->syncp);
2727
2728 return;
2729 }
2730
39c38824 2731 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 2732 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2733 switch (ol4_type) {
2734 case HNS3_OL4_TYPE_MAC_IN_UDP:
2735 case HNS3_OL4_TYPE_NVGRE:
2736 skb->csum_level = 1;
df561f66 2737 fallthrough;
76ad4f0e 2738 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 2739 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2740 HNS3_RXD_L3ID_S);
2741 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2742 HNS3_RXD_L4ID_S);
2743
76ad4f0e 2744 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2745 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2746 l3_type == HNS3_L3_TYPE_IPV6) &&
2747 (l4_type == HNS3_L4_TYPE_UDP ||
2748 l4_type == HNS3_L4_TYPE_TCP ||
2749 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2750 skb->ip_summed = CHECKSUM_UNNECESSARY;
2751 break;
fa7a4bd5
JS		 2752 default:
2753 break;
76ad4f0e
S		 2754 }
2755}
2756
d43e5aca
YL		 2757static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2758{
81ae0e04
PL		 2759 if (skb_has_frag_list(skb))
2760 napi_gro_flush(&ring->tqp_vector->napi, false);
2761
d43e5aca
YL		 2762 napi_gro_receive(&ring->tqp_vector->napi, skb);
2763}
2764
701a6d6a
JS		 2765static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2766 struct hns3_desc *desc, u32 l234info,
2767 u16 *vlan_tag)
5b5455a9 2768{
44e626f7 2769 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 2770 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL		 2771
2772 if (pdev->revision == 0x20) {
701a6d6a
JS		 2773 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2774 if (!(*vlan_tag & VLAN_VID_MASK))
2775 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2776
701a6d6a 2777 return (*vlan_tag != 0);
5b5455a9
PL		 2778 }
2779
2780#define HNS3_STRP_OUTER_VLAN 0x1
2781#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 2782#define HNS3_STRP_BOTH 0x3
5b5455a9 2783
44e626f7
JS		 2784 /* Hardware always insert VLAN tag into RX descriptor when
2785 * remove the tag from packet, driver needs to determine
2786 * reporting which tag to stack.
2787 */
e4e87715
PL		 2788 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2789 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2790 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 2791 if (handle->port_base_vlan_state !=
2792 HNAE3_PORT_BASE_VLAN_DISABLE)
2793 return false;
2794
701a6d6a
JS		 2795 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2796 return true;
5b5455a9 2797 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 2798 if (handle->port_base_vlan_state !=
2799 HNAE3_PORT_BASE_VLAN_DISABLE)
2800 return false;
2801
701a6d6a 2802 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 2803 return true;
2804 case HNS3_STRP_BOTH:
2805 if (handle->port_base_vlan_state ==
2806 HNAE3_PORT_BASE_VLAN_DISABLE)
2807 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2808 else
2809 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2810
701a6d6a 2811 return true;
5b5455a9 2812 default:
701a6d6a 2813 return false;
5b5455a9 2814 }
5b5455a9
PL		 2815}
2816
b9a8f883 2817static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL		 2818 unsigned char *va)
2819{
e5597095 2820 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
c8711956 2821 struct net_device *netdev = ring_to_netdev(ring);
e5597095
PL		 2822 struct sk_buff *skb;
2823
2824 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2825 skb = ring->skb;
2826 if (unlikely(!skb)) {
b20d7fe5 2827 hns3_rl_err(netdev, "alloc rx skb fail\n");
e5597095
PL		 2828
2829 u64_stats_update_begin(&ring->syncp);
2830 ring->stats.sw_err_cnt++;
2831 u64_stats_update_end(&ring->syncp);
2832
2833 return -ENOMEM;
2834 }
2835
698a8954 2836 trace_hns3_rx_desc(ring);
e5597095
PL		 2837 prefetchw(skb->data);
2838
2839 ring->pending_buf = 1;
81ae0e04
PL		 2840 ring->frag_num = 0;
2841 ring->tail_skb = NULL;
e5597095
PL		 2842 if (length <= HNS3_RX_HEAD_SIZE) {
2843 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2844
2845 /* We can reuse buffer as-is, just make sure it is local */
08bb3857 2846 if (likely(hns3_page_is_reusable(desc_cb->priv)))
e5597095
PL		 2847 desc_cb->reuse_flag = 1;
2848 else /* This page cannot be reused so discard it */
2849 put_page(desc_cb->priv);
2850
2851 ring_ptr_move_fw(ring, next_to_clean);
2852 return 0;
2853 }
2854 u64_stats_update_begin(&ring->syncp);
2855 ring->stats.seg_pkt_cnt++;
2856 u64_stats_update_end(&ring->syncp);
2857
c43f1255 2858 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 2859 __skb_put(skb, ring->pull_len);
81ae0e04 2860 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL		 2861 desc_cb);
2862 ring_ptr_move_fw(ring, next_to_clean);
2863
b2598318 2864 return 0;
e5597095
PL		 2865}
2866
b2598318 2867static int hns3_add_frag(struct hns3_enet_ring *ring)
e5597095 2868{
d35bced8
YL		 2869 struct sk_buff *skb = ring->skb;
2870 struct sk_buff *head_skb = skb;
81ae0e04 2871 struct sk_buff *new_skb;
e5597095 2872 struct hns3_desc_cb *desc_cb;
b2598318 2873 struct hns3_desc *desc;
e5597095 2874 u32 bd_base_info;
e5597095 2875
b2598318 2876 do {
e5597095
PL		 2877 desc = &ring->desc[ring->next_to_clean];
2878 desc_cb = &ring->desc_cb[ring->next_to_clean];
2879 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 2880 /* make sure HW write desc complete */
2881 dma_rmb();
e8149933 2882 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 2883 return -ENXIO;
2884
81ae0e04 2885 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
7fda3a93 2886 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
81ae0e04 2887 if (unlikely(!new_skb)) {
c8711956 2888 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5 2889 "alloc rx fraglist skb fail\n");
81ae0e04
PL		 2890 return -ENXIO;
2891 }
2892 ring->frag_num = 0;
2893
2894 if (ring->tail_skb) {
2895 ring->tail_skb->next = new_skb;
2896 ring->tail_skb = new_skb;
2897 } else {
2898 skb_shinfo(skb)->frag_list = new_skb;
2899 ring->tail_skb = new_skb;
2900 }
2901 }
2902
2903 if (ring->tail_skb) {
dbba6da0 2904 head_skb->truesize += hns3_buf_size(ring);
81ae0e04
PL		 2905 head_skb->data_len += le16_to_cpu(desc->rx.size);
2906 head_skb->len += le16_to_cpu(desc->rx.size);
2907 skb = ring->tail_skb;
2908 }
2909
c2a2e127
BS		 2910 dma_sync_single_for_cpu(ring_to_dev(ring),
2911 desc_cb->dma + desc_cb->page_offset,
2912 hns3_buf_size(ring),
2913 DMA_FROM_DEVICE);
2914
81ae0e04 2915 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
698a8954 2916 trace_hns3_rx_desc(ring);
e5597095
PL		 2917 ring_ptr_move_fw(ring, next_to_clean);
2918 ring->pending_buf++;
b2598318 2919 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
e5597095
PL		 2920
2921 return 0;
2922}
2923
d474d88f
YL		 2924static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2925 struct sk_buff *skb, u32 l234info,
39c38824 2926 u32 bd_base_info, u32 ol_info)
a6d53b97 2927{
a6d53b97
PL		 2928 u32 l3_type;
2929
e2ee1c5a
YL		 2930 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2931 HNS3_RXD_GRO_SIZE_M,
2932 HNS3_RXD_GRO_SIZE_S);
a6d53b97 2933 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 2934 if (!skb_shinfo(skb)->gso_size) {
39c38824 2935 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
d474d88f
YL		 2936 return 0;
2937 }
a6d53b97 2938
e2ee1c5a
YL		 2939 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2940 HNS3_RXD_GRO_COUNT_M,
2941 HNS3_RXD_GRO_COUNT_S);
a6d53b97 2942
9b2f3477 2943 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
a6d53b97
PL		 2944 if (l3_type == HNS3_L3_TYPE_IPV4)
2945 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2946 else if (l3_type == HNS3_L3_TYPE_IPV6)
2947 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2948 else
d474d88f 2949 return -EFAULT;
a6d53b97 2950
e2ee1c5a 2951 return hns3_gro_complete(skb, l234info);
a6d53b97
PL		 2952}
2953
232fc64b 2954static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 2955 struct sk_buff *skb, u32 rss_hash)
232fc64b 2956{
232fc64b
PL		 2957 struct hnae3_handle *handle = ring->tqp->handle;
2958 enum pkt_hash_types rss_type;
2959
ea485867 2960 if (rss_hash)
232fc64b
PL		 2961 rss_type = handle->kinfo.rss_type;
2962 else
2963 rss_type = PKT_HASH_TYPE_NONE;
2964
ea485867 2965 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 2966}
2967
ea485867 2968static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e 2969{
c8711956 2970 struct net_device *netdev = ring_to_netdev(ring);
c376fa1a 2971 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 2972 u32 bd_base_info, l234info, ol_info;
ea485867 2973 struct hns3_desc *desc;
d474d88f 2974 unsigned int len;
ea485867
YL		 2975 int pre_ntc, ret;
2976
2977 /* bdinfo handled below is only valid on the last BD of the
2978 * current packet, and ring->next_to_clean indicates the first
2979 * descriptor of next packet, so need - 1 below.
2980 */
2981 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2982 (ring->desc_num - 1);
2983 desc = &ring->desc[pre_ntc];
2984 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2985 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 2986 ol_info = le32_to_cpu(desc->rx.ol_info);
d474d88f
YL		 2987
2988 /* Based on hw strategy, the tag offloaded will be stored at
2989 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2990 * in one layer tag case.
2991 */
2992 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2993 u16 vlan_tag;
2994
2995 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2996 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2997 vlan_tag);
2998 }
2999
d474d88f
YL		 3000 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3001 BIT(HNS3_RXD_L2E_B))))) {
3002 u64_stats_update_begin(&ring->syncp);
3003 if (l234info & BIT(HNS3_RXD_L2E_B))
3004 ring->stats.l2_err++;
3005 else
3006 ring->stats.err_pkt_len++;
3007 u64_stats_update_end(&ring->syncp);
3008
3009 return -EFAULT;
3010 }
3011
3012 len = skb->len;
3013
3014 /* Do update ip stack process */
3015 skb->protocol = eth_type_trans(skb, netdev);
3016
3017 /* This is needed in order to enable forwarding support */
39c38824
YL		 3018 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3019 bd_base_info, ol_info);
d474d88f
YL		 3020 if (unlikely(ret)) {
3021 u64_stats_update_begin(&ring->syncp);
3022 ring->stats.rx_err_cnt++;
3023 u64_stats_update_end(&ring->syncp);
3024 return ret;
3025 }
3026
3027 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3028 HNS3_RXD_DMAC_S);
3029
3030 u64_stats_update_begin(&ring->syncp);
3031 ring->stats.rx_pkts++;
3032 ring->stats.rx_bytes += len;
3033
3034 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3035 ring->stats.rx_multicast++;
3036
3037 u64_stats_update_end(&ring->syncp);
3038
3039 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 3040
3041 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 3042 return 0;
3043}
3044
d35bced8 3045static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
d474d88f 3046{
e5597095 3047 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 3048 struct hns3_desc_cb *desc_cb;
3049 struct hns3_desc *desc;
b9a8f883 3050 unsigned int length;
76ad4f0e 3051 u32 bd_base_info;
e5597095 3052 int ret;
76ad4f0e
S		 3053
3054 desc = &ring->desc[ring->next_to_clean];
3055 desc_cb = &ring->desc_cb[ring->next_to_clean];
3056
3057 prefetch(desc);
3058
846fcc83 3059 length = le16_to_cpu(desc->rx.size);
76ad4f0e 3060 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 3061
3062 /* Check valid BD */
e8149933 3063 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
e5597095 3064 return -ENXIO;
76ad4f0e 3065
c2a2e127 3066 if (!skb) {
cb0e3e61 3067 ring->va = desc_cb->buf + desc_cb->page_offset;
76ad4f0e 3068
c2a2e127
BS		 3069 dma_sync_single_for_cpu(ring_to_dev(ring),
3070 desc_cb->dma + desc_cb->page_offset,
3071 hns3_buf_size(ring),
3072 DMA_FROM_DEVICE);
3073 }
3074
76ad4f0e
S		 3075 /* Prefetch first cache line of first page
3076 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3077 * line size is 64B so need to prefetch twice to make it 128B. But in
3078 * actual we can have greater size of caches with 128B Level 1 cache
3079 * lines. In such a case, single fetch would suffice to cache in the
3080 * relevant part of the header.
3081 */
f468f21b 3082 net_prefetch(ring->va);
76ad4f0e 3083
e5597095
PL		 3084 if (!skb) {
3085 ret = hns3_alloc_skb(ring, length, ring->va);
d35bced8 3086 skb = ring->skb;
76ad4f0e 3087
e5597095
PL		 3088 if (ret < 0) /* alloc buffer fail */
3089 return ret;
b2598318
YL		 3090 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3091 ret = hns3_add_frag(ring);
e5597095
PL		 3092 if (ret)
3093 return ret;
e5597095 3094 }
76ad4f0e 3095 } else {
b2598318 3096 ret = hns3_add_frag(ring);
e5597095
PL		 3097 if (ret)
3098 return ret;
b2598318 3099 }
76ad4f0e 3100
b2598318
YL		 3101 /* As the head data may be changed when GRO enable, copy
3102 * the head data in after other data rx completed
3103 */
3104 if (skb->len > HNS3_RX_HEAD_SIZE)
e5597095
PL		 3105 memcpy(skb->data, ring->va,
3106 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e 3107
ea485867 3108 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 3109 if (unlikely(ret)) {
76ad4f0e 3110 dev_kfree_skb_any(skb);
d474d88f 3111 return ret;
76ad4f0e
S		 3112 }
3113
d93ed94f 3114 skb_record_rx_queue(skb, ring->tqp->tqp_index);
76ad4f0e
S		 3115 return 0;
3116}
3117
9b2f3477
WL		 3118int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3119 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 3120{
3121#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
63380a1a 3122 int unused_count = hns3_desc_unused(ring);
a4ee7624
YL		 3123 int recv_pkts = 0;
3124 int recv_bds = 0;
3125 int err, num;
76ad4f0e
S		 3126
3127 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
76ad4f0e 3128 num -= unused_count;
63380a1a 3129 unused_count -= ring->pending_buf;
76ad4f0e 3130
88b7c58c
YL		 3131 if (num <= 0)
3132 goto out;
3133
3134 rmb(); /* Make sure num taken effect before the other data is touched */
3135
76ad4f0e
S		 3136 while (recv_pkts < budget && recv_bds < num) {
3137 /* Reuse or realloc buffers */
a4ee7624
YL		 3138 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3139 hns3_nic_alloc_rx_buffers(ring, unused_count);
e5597095
PL		 3140 unused_count = hns3_desc_unused(ring) -
3141 ring->pending_buf;
76ad4f0e
S		 3142 }
3143
3144 /* Poll one pkt */
d35bced8
YL		 3145 err = hns3_handle_rx_bd(ring);
3146 /* Do not get FE for the packet or failed to alloc skb */
3147 if (unlikely(!ring->skb || err == -ENXIO)) {
76ad4f0e 3148 goto out;
d35bced8
YL		 3149 } else if (likely(!err)) {
3150 rx_fn(ring, ring->skb);
3151 recv_pkts++;
76ad4f0e
S		 3152 }
3153
e5597095 3154 recv_bds += ring->pending_buf;
a4ee7624 3155 unused_count += ring->pending_buf;
e5597095
PL		 3156 ring->skb = NULL;
3157 ring->pending_buf = 0;
76ad4f0e
S		 3158 }
3159
3160out:
3161 /* Make all data has been write before submit */
a4ee7624
YL		 3162 if (unused_count > 0)
3163 hns3_nic_alloc_rx_buffers(ring, unused_count);
76ad4f0e
S		 3164
3165 return recv_pkts;
3166}
3167
4a43caf5 3168static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
76ad4f0e 3169{
4a43caf5
YL		 3170#define HNS3_RX_LOW_BYTE_RATE 10000
3171#define HNS3_RX_MID_BYTE_RATE 20000
3172#define HNS3_RX_ULTRA_PACKET_RATE 40
3173
76ad4f0e 3174 enum hns3_flow_level_range new_flow_level;
4a43caf5
YL		 3175 struct hns3_enet_tqp_vector *tqp_vector;
3176 int packets_per_msecs, bytes_per_msecs;
a95e1f86 3177 u32 time_passed_ms;
76ad4f0e 3178
4a43caf5 3179 tqp_vector = ring_group->ring->tqp_vector;
a95e1f86
FL		 3180 time_passed_ms =
3181 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
a95e1f86
FL		 3182 if (!time_passed_ms)
3183 return false;
3184
3185 do_div(ring_group->total_packets, time_passed_ms);
3186 packets_per_msecs = ring_group->total_packets;
3187
3188 do_div(ring_group->total_bytes, time_passed_ms);
3189 bytes_per_msecs = ring_group->total_bytes;
3190
4a43caf5 3191 new_flow_level = ring_group->coal.flow_level;
76ad4f0e 3192
4a43caf5
YL		 3193 /* Simple throttlerate management
3194 * 0-10MB/s lower (50000 ints/s)
3195 * 10-20MB/s middle (20000 ints/s)
3196 * 20-1249MB/s high (18000 ints/s)
3197 * > 40000pps ultra (8000 ints/s)
3198 */
76ad4f0e
S		 3199 switch (new_flow_level) {
3200 case HNS3_FLOW_LOW:
a95e1f86 3201 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 3202 new_flow_level = HNS3_FLOW_MID;
3203 break;
3204 case HNS3_FLOW_MID:
a95e1f86 3205 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 3206 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 3207 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 3208 new_flow_level = HNS3_FLOW_LOW;
3209 break;
3210 case HNS3_FLOW_HIGH:
3211 case HNS3_FLOW_ULTRA:
3212 default:
a95e1f86 3213 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 3214 new_flow_level = HNS3_FLOW_MID;
3215 break;
3216 }
3217
a95e1f86
FL		 3218 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3219 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 3220 new_flow_level = HNS3_FLOW_ULTRA;
3221
4a43caf5
YL		 3222 ring_group->total_bytes = 0;
3223 ring_group->total_packets = 0;
3224 ring_group->coal.flow_level = new_flow_level;
3225
3226 return true;
3227}
3228
3229static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3230{
3231 struct hns3_enet_tqp_vector *tqp_vector;
3232 u16 new_int_gl;
3233
3234 if (!ring_group->ring)
3235 return false;
3236
3237 tqp_vector = ring_group->ring->tqp_vector;
3238 if (!tqp_vector->last_jiffies)
3239 return false;
3240
3241 if (ring_group->total_packets == 0) {
3242 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3243 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3244 return true;
3245 }
3246
3247 if (!hns3_get_new_flow_lvl(ring_group))
3248 return false;
3249
3250 new_int_gl = ring_group->coal.int_gl;
3251 switch (ring_group->coal.flow_level) {
76ad4f0e
S		 3252 case HNS3_FLOW_LOW:
3253 new_int_gl = HNS3_INT_GL_50K;
3254 break;
3255 case HNS3_FLOW_MID:
3256 new_int_gl = HNS3_INT_GL_20K;
3257 break;
3258 case HNS3_FLOW_HIGH:
3259 new_int_gl = HNS3_INT_GL_18K;
3260 break;
3261 case HNS3_FLOW_ULTRA:
3262 new_int_gl = HNS3_INT_GL_8K;
3263 break;
3264 default:
3265 break;
3266 }
3267
9bc727a9
YL		 3268 if (new_int_gl != ring_group->coal.int_gl) {
3269 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 3270 return true;
3271 }
3272 return false;
3273}
3274
3275static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3276{
8b1ff1ea
FL		 3277 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3278 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3279 bool rx_update, tx_update;
3280
7445565c
PL		 3281 /* update param every 1000ms */
3282 if (time_before(jiffies,
3283 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3284 return;
cd9d187b 3285
9bc727a9 3286 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 3287 rx_update = hns3_get_new_int_gl(rx_group);
3288 if (rx_update)
3289 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3290 rx_group->coal.int_gl);
8b1ff1ea
FL		 3291 }
3292
9bc727a9 3293 if (tx_group->coal.gl_adapt_enable) {
9e50dc11 3294 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL		 3295 if (tx_update)
3296 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3297 tx_group->coal.int_gl);
76ad4f0e 3298 }
cd9d187b 3299
a95e1f86 3300 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 3301}
3302
3303static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3304{
ff0699e0 3305 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 3306 struct hns3_enet_ring *ring;
3307 int rx_pkt_total = 0;
3308
3309 struct hns3_enet_tqp_vector *tqp_vector =
3310 container_of(napi, struct hns3_enet_tqp_vector, napi);
3311 bool clean_complete = true;
ceca4a5e 3312 int rx_budget = budget;
76ad4f0e 3313
ff0699e0
HT		 3314 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3315 napi_complete(napi);
3316 return 0;
3317 }
3318
76ad4f0e
S		 3319 /* Since the actual Tx work is minimal, we can give the Tx a larger
3320 * budget and be more aggressive about cleaning up the Tx descriptors.
3321 */
799997a3
PL		 3322 hns3_for_each_ring(ring, tqp_vector->tx_group)
3323 hns3_clean_tx_ring(ring);
76ad4f0e
S		 3324
3325 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 3326 if (tqp_vector->num_tqps > 1)
3327 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 3328
3329 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 3330 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3331 hns3_rx_skb);
76ad4f0e
S		 3332
3333 if (rx_cleaned >= rx_budget)
3334 clean_complete = false;
3335
3336 rx_pkt_total += rx_cleaned;
3337 }
3338
3339 tqp_vector->rx_group.total_packets += rx_pkt_total;
3340
3341 if (!clean_complete)
3342 return budget;
3343
531eba0f
HT		 3344 if (napi_complete(napi) &&
3345 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 3346 hns3_update_new_int_gl(tqp_vector);
3347 hns3_mask_vector_irq(tqp_vector, 1);
3348 }
76ad4f0e
S		 3349
3350 return rx_pkt_total;
3351}
3352
3353static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3354 struct hnae3_ring_chain_node *head)
3355{
3356 struct pci_dev *pdev = tqp_vector->handle->pdev;
3357 struct hnae3_ring_chain_node *cur_chain = head;
3358 struct hnae3_ring_chain_node *chain;
3359 struct hns3_enet_ring *tx_ring;
3360 struct hns3_enet_ring *rx_ring;
3361
3362 tx_ring = tqp_vector->tx_group.ring;
3363 if (tx_ring) {
3364 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3365 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3366 HNAE3_RING_TYPE_TX);
3367 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3368 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 3369
3370 cur_chain->next = NULL;
3371
3372 while (tx_ring->next) {
3373 tx_ring = tx_ring->next;
3374
3375 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3376 GFP_KERNEL);
3377 if (!chain)
73b907a0 3378 goto err_free_chain;
76ad4f0e
S		 3379
3380 cur_chain->next = chain;
3381 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3382 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3383 HNAE3_RING_TYPE_TX);
3384 hnae3_set_field(chain->int_gl_idx,
3385 HNAE3_RING_GL_IDX_M,
3386 HNAE3_RING_GL_IDX_S,
3387 HNAE3_RING_GL_TX);
76ad4f0e
S		 3388
3389 cur_chain = chain;
3390 }
3391 }
3392
3393 rx_ring = tqp_vector->rx_group.ring;
3394 if (!tx_ring && rx_ring) {
3395 cur_chain->next = NULL;
3396 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3397 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3398 HNAE3_RING_TYPE_RX);
3399 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3400 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 3401
3402 rx_ring = rx_ring->next;
3403 }
3404
3405 while (rx_ring) {
3406 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3407 if (!chain)
73b907a0 3408 goto err_free_chain;
76ad4f0e
S		 3409
3410 cur_chain->next = chain;
3411 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3412 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3413 HNAE3_RING_TYPE_RX);
3414 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3415 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3416
76ad4f0e
S		 3417 cur_chain = chain;
3418
3419 rx_ring = rx_ring->next;
3420 }
3421
3422 return 0;
73b907a0
HT		 3423
3424err_free_chain:
3425 cur_chain = head->next;
3426 while (cur_chain) {
3427 chain = cur_chain->next;
cda69d24 3428 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 3429 cur_chain = chain;
3430 }
cda69d24 3431 head->next = NULL;
73b907a0
HT		 3432
3433 return -ENOMEM;
76ad4f0e
S		 3434}
3435
3436static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3437 struct hnae3_ring_chain_node *head)
3438{
3439 struct pci_dev *pdev = tqp_vector->handle->pdev;
3440 struct hnae3_ring_chain_node *chain_tmp, *chain;
3441
3442 chain = head->next;
3443
3444 while (chain) {
3445 chain_tmp = chain->next;
3446 devm_kfree(&pdev->dev, chain);
3447 chain = chain_tmp;
3448 }
3449}
3450
3451static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3452 struct hns3_enet_ring *ring)
3453{
3454 ring->next = group->ring;
3455 group->ring = ring;
3456
3457 group->count++;
3458}
3459
874bff0b
PL		 3460static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3461{
3462 struct pci_dev *pdev = priv->ae_handle->pdev;
3463 struct hns3_enet_tqp_vector *tqp_vector;
3464 int num_vectors = priv->vector_num;
3465 int numa_node;
3466 int vector_i;
3467
3468 numa_node = dev_to_node(&pdev->dev);
3469
3470 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3471 tqp_vector = &priv->tqp_vector[vector_i];
3472 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3473 &tqp_vector->affinity_mask);
3474 }
3475}
3476
76ad4f0e
S		 3477static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3478{
3479 struct hnae3_ring_chain_node vector_ring_chain;
3480 struct hnae3_handle *h = priv->ae_handle;
3481 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3482 int ret = 0;
ece4bf46 3483 int i;
76ad4f0e 3484
874bff0b
PL		 3485 hns3_nic_set_cpumask(priv);
3486
dd38c726
YL		 3487 for (i = 0; i < priv->vector_num; i++) {
3488 tqp_vector = &priv->tqp_vector[i];
3489 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3490 tqp_vector->num_tqps = 0;
3491 }
76ad4f0e 3492
dd38c726
YL		 3493 for (i = 0; i < h->kinfo.num_tqps; i++) {
3494 u16 vector_i = i % priv->vector_num;
3495 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3496
3497 tqp_vector = &priv->tqp_vector[vector_i];
3498
3499 hns3_add_ring_to_group(&tqp_vector->tx_group,
5f06b903 3500 &priv->ring[i]);
76ad4f0e
S		 3501
3502 hns3_add_ring_to_group(&tqp_vector->rx_group,
5f06b903 3503 &priv->ring[i + tqp_num]);
76ad4f0e 3504
5f06b903
YL		 3505 priv->ring[i].tqp_vector = tqp_vector;
3506 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
dd38c726 3507 tqp_vector->num_tqps++;
76ad4f0e
S		 3508 }
3509
dd38c726 3510 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3511 tqp_vector = &priv->tqp_vector[i];
3512
3513 tqp_vector->rx_group.total_bytes = 0;
3514 tqp_vector->rx_group.total_packets = 0;
3515 tqp_vector->tx_group.total_bytes = 0;
3516 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3517 tqp_vector->handle = h;
3518
3519 ret = hns3_get_vector_ring_chain(tqp_vector,
3520 &vector_ring_chain);
3521 if (ret)
cda69d24 3522 goto map_ring_fail;
76ad4f0e
S		 3523
3524 ret = h->ae_algo->ops->map_ring_to_vector(h,
3525 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3526
3527 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3528
dd38c726 3529 if (ret)
ece4bf46 3530 goto map_ring_fail;
dd38c726 3531
76ad4f0e
S		 3532 netif_napi_add(priv->netdev, &tqp_vector->napi,
3533 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3534 }
3535
dd38c726 3536 return 0;
ece4bf46
HT		 3537
3538map_ring_fail:
3539 while (i--)
3540 netif_napi_del(&priv->tqp_vector[i].napi);
3541
3542 return ret;
dd38c726
YL		 3543}
3544
3545static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3546{
75edb610
JS		 3547#define HNS3_VECTOR_PF_MAX_NUM 64
3548
dd38c726
YL		 3549 struct hnae3_handle *h = priv->ae_handle;
3550 struct hns3_enet_tqp_vector *tqp_vector;
3551 struct hnae3_vector_info *vector;
3552 struct pci_dev *pdev = h->pdev;
3553 u16 tqp_num = h->kinfo.num_tqps;
3554 u16 vector_num;
3555 int ret = 0;
3556 u16 i;
3557
3558 /* RSS size, cpu online and vector_num should be the same */
3559 /* Should consider 2p/4p later */
3560 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS		 3561 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3562
dd38c726
YL		 3563 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3564 GFP_KERNEL);
3565 if (!vector)
3566 return -ENOMEM;
3567
9b2f3477 3568 /* save the actual available vector number */
dd38c726
YL		 3569 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3570
3571 priv->vector_num = vector_num;
3572 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3573 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3574 GFP_KERNEL);
3575 if (!priv->tqp_vector) {
3576 ret = -ENOMEM;
3577 goto out;
3578 }
3579
3580 for (i = 0; i < priv->vector_num; i++) {
3581 tqp_vector = &priv->tqp_vector[i];
3582 tqp_vector->idx = i;
3583 tqp_vector->mask_addr = vector[i].io_addr;
3584 tqp_vector->vector_irq = vector[i].vector;
3585 hns3_vector_gl_rl_init(tqp_vector, priv);
3586 }
3587
76ad4f0e
S		 3588out:
3589 devm_kfree(&pdev->dev, vector);
3590 return ret;
3591}
3592
dd38c726
YL		 3593static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3594{
3595 group->ring = NULL;
3596 group->count = 0;
3597}
3598
e2152785 3599static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 3600{
3601 struct hnae3_ring_chain_node vector_ring_chain;
3602 struct hnae3_handle *h = priv->ae_handle;
3603 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3604 int i;
76ad4f0e
S		 3605
3606 for (i = 0; i < priv->vector_num; i++) {
3607 tqp_vector = &priv->tqp_vector[i];
3608
2c9dd668
HT		 3609 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3610 continue;
3611
ff7dfcdd
HT		 3612 /* Since the mapping can be overwritten, when fail to get the
3613 * chain between vector and ring, we should go on to deal with
3614 * the remaining options.
3615 */
3616 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3617 dev_warn(priv->dev, "failed to get ring chain\n");
76ad4f0e 3618
e2152785 3619 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3620 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3621
3622 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3623
dd38c726
YL		 3624 hns3_clear_ring_group(&tqp_vector->rx_group);
3625 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3626 netif_napi_del(&priv->tqp_vector[i].napi);
3627 }
dd38c726
YL		 3628}
3629
08a10068 3630static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
dd38c726
YL		 3631{
3632 struct hnae3_handle *h = priv->ae_handle;
3633 struct pci_dev *pdev = h->pdev;
3634 int i, ret;
3635
3636 for (i = 0; i < priv->vector_num; i++) {
3637 struct hns3_enet_tqp_vector *tqp_vector;
3638
3639 tqp_vector = &priv->tqp_vector[i];
3640 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3641 if (ret)
08a10068 3642 return;
dd38c726 3643 }
76ad4f0e 3644
dd38c726 3645 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3646}
3647
5f06b903
YL		 3648static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3649 unsigned int ring_type)
76ad4f0e 3650{
76ad4f0e 3651 int queue_num = priv->ae_handle->kinfo.num_tqps;
76ad4f0e 3652 struct hns3_enet_ring *ring;
c0425944 3653 int desc_num;
76ad4f0e 3654
76ad4f0e 3655 if (ring_type == HNAE3_RING_TYPE_TX) {
5f06b903 3656 ring = &priv->ring[q->tqp_index];
c0425944 3657 desc_num = priv->ae_handle->kinfo.num_tx_desc;
5f06b903 3658 ring->queue_index = q->tqp_index;
76ad4f0e 3659 } else {
5f06b903 3660 ring = &priv->ring[q->tqp_index + queue_num];
c0425944 3661 desc_num = priv->ae_handle->kinfo.num_rx_desc;
5f06b903 3662 ring->queue_index = q->tqp_index;
76ad4f0e
S		 3663 }
3664
e4e87715 3665 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3666
76ad4f0e
S		 3667 ring->tqp = q;
3668 ring->desc = NULL;
3669 ring->desc_cb = NULL;
3670 ring->dev = priv->dev;
3671 ring->desc_dma_addr = 0;
3672 ring->buf_size = q->buf_size;
2c9dd668 3673 ring->desc_num = desc_num;
76ad4f0e
S		 3674 ring->next_to_use = 0;
3675 ring->next_to_clean = 0;
76ad4f0e
S		 3676}
3677
5f06b903
YL		 3678static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3679 struct hns3_nic_priv *priv)
76ad4f0e 3680{
5f06b903
YL		 3681 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3682 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
76ad4f0e
S		 3683}
3684
3685static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3686{
3687 struct hnae3_handle *h = priv->ae_handle;
3688 struct pci_dev *pdev = h->pdev;
5f06b903 3689 int i;
76ad4f0e 3690
5f06b903
YL		 3691 priv->ring = devm_kzalloc(&pdev->dev,
3692 array3_size(h->kinfo.num_tqps,
3693 sizeof(*priv->ring), 2),
3694 GFP_KERNEL);
3695 if (!priv->ring)
76ad4f0e
S		 3696 return -ENOMEM;
3697
5f06b903
YL		 3698 for (i = 0; i < h->kinfo.num_tqps; i++)
3699 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
76ad4f0e
S		 3700
3701 return 0;
76ad4f0e
S		 3702}
3703
09f2af64
PL		 3704static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3705{
5f06b903 3706 if (!priv->ring)
7b8f622e
HT		 3707 return;
3708
5f06b903
YL		 3709 devm_kfree(priv->dev, priv->ring);
3710 priv->ring = NULL;
09f2af64
PL		 3711}
3712
76ad4f0e
S		 3713static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3714{
3715 int ret;
3716
3717 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3718 return -EINVAL;
3719
77296bf6
YL		 3720 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3721 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 3722 if (!ring->desc_cb) {
3723 ret = -ENOMEM;
3724 goto out;
3725 }
3726
3727 ret = hns3_alloc_desc(ring);
3728 if (ret)
3729 goto out_with_desc_cb;
3730
3731 if (!HNAE3_IS_TX_RING(ring)) {
3732 ret = hns3_alloc_ring_buffers(ring);
3733 if (ret)
3734 goto out_with_desc;
3735 }
3736
3737 return 0;
3738
3739out_with_desc:
3740 hns3_free_desc(ring);
3741out_with_desc_cb:
77296bf6 3742 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3743 ring->desc_cb = NULL;
3744out:
3745 return ret;
3746}
3747
a723fb8e 3748void hns3_fini_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 3749{
3750 hns3_free_desc(ring);
77296bf6 3751 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3752 ring->desc_cb = NULL;
3753 ring->next_to_clean = 0;
3754 ring->next_to_use = 0;
ac574b80
PL		 3755 ring->pending_buf = 0;
3756 if (ring->skb) {
3757 dev_kfree_skb_any(ring->skb);
3758 ring->skb = NULL;
3759 }
76ad4f0e
S		 3760}
3761
1db9b1bf 3762static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3763{
3764 int bd_size_type;
3765
3766 switch (buf_size) {
3767 case 512:
3768 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3769 break;
3770 case 1024:
3771 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3772 break;
3773 case 2048:
3774 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3775 break;
3776 case 4096:
3777 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3778 break;
3779 default:
3780 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3781 }
3782
3783 return bd_size_type;
3784}
3785
3786static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3787{
3788 dma_addr_t dma = ring->desc_dma_addr;
3789 struct hnae3_queue *q = ring->tqp;
3790
3791 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 3792 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S		 3793 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3794 (u32)((dma >> 31) >> 1));
3795
3796 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3797 hns3_buf_size2type(ring->buf_size));
3798 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3799 ring->desc_num / 8 - 1);
3800
3801 } else {
3802 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3803 (u32)dma);
3804 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3805 (u32)((dma >> 31) >> 1));
3806
76ad4f0e
S		 3807 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3808 ring->desc_num / 8 - 1);
3809 }
3810}
3811
1c772154
YL		 3812static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3813{
3814 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3815 int i;
3816
3817 for (i = 0; i < HNAE3_MAX_TC; i++) {
3818 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3819 int j;
3820
3821 if (!tc_info->enable)
3822 continue;
3823
3824 for (j = 0; j < tc_info->tqp_count; j++) {
3825 struct hnae3_queue *q;
3826
5f06b903 3827 q = priv->ring[tc_info->tqp_offset + j].tqp;
1c772154
YL		 3828 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3829 tc_info->tc);
3830 }
3831 }
3832}
3833
5668abda 3834int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3835{
3836 struct hnae3_handle *h = priv->ae_handle;
3837 int ring_num = h->kinfo.num_tqps * 2;
3838 int i, j;
3839 int ret;
3840
3841 for (i = 0; i < ring_num; i++) {
5f06b903 3842 ret = hns3_alloc_ring_memory(&priv->ring[i]);
76ad4f0e
S		 3843 if (ret) {
3844 dev_err(priv->dev,
3845 "Alloc ring memory fail! ret=%d\n", ret);
3846 goto out_when_alloc_ring_memory;
3847 }
3848
5f06b903 3849 u64_stats_init(&priv->ring[i].syncp);
76ad4f0e
S		 3850 }
3851
3852 return 0;
3853
3854out_when_alloc_ring_memory:
3855 for (j = i - 1; j >= 0; j--)
5f06b903 3856 hns3_fini_ring(&priv->ring[j]);
76ad4f0e
S		 3857
3858 return -ENOMEM;
3859}
3860
5668abda 3861int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3862{
3863 struct hnae3_handle *h = priv->ae_handle;
3864 int i;
3865
3866 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903
YL		 3867 hns3_fini_ring(&priv->ring[i]);
3868 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
76ad4f0e 3869 }
76ad4f0e
S		 3870 return 0;
3871}
3872
3873/* Set mac addr if it is configured. or leave it to the AE driver */
8e6de441 3874static int hns3_init_mac_addr(struct net_device *netdev)
76ad4f0e
S		 3875{
3876 struct hns3_nic_priv *priv = netdev_priv(netdev);
3877 struct hnae3_handle *h = priv->ae_handle;
3878 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3879 int ret = 0;
76ad4f0e 3880
8e6de441 3881 if (h->ae_algo->ops->get_mac_addr)
76ad4f0e 3882 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
76ad4f0e
S		 3883
3884 /* Check if the MAC address is valid, if not get a random one */
8e6de441 3885 if (!is_valid_ether_addr(mac_addr_temp)) {
76ad4f0e
S		 3886 eth_hw_addr_random(netdev);
3887 dev_warn(priv->dev, "using random MAC address %pM\n",
3888 netdev->dev_addr);
ee4bcd3b 3889 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
8e6de441
HT		 3890 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3891 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
ee4bcd3b
JS		 3892 } else {
3893 return 0;
76ad4f0e 3894 }
139e8792
L		 3895
3896 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3897 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3898
7fa6be4f 3899 return ret;
76ad4f0e
S		 3900}
3901
c8a8045b
HT		 3902static int hns3_init_phy(struct net_device *netdev)
3903{
3904 struct hnae3_handle *h = hns3_get_handle(netdev);
3905 int ret = 0;
3906
3907 if (h->ae_algo->ops->mac_connect_phy)
3908 ret = h->ae_algo->ops->mac_connect_phy(h);
3909
3910 return ret;
3911}
3912
3913static void hns3_uninit_phy(struct net_device *netdev)
3914{
3915 struct hnae3_handle *h = hns3_get_handle(netdev);
3916
3917 if (h->ae_algo->ops->mac_disconnect_phy)
3918 h->ae_algo->ops->mac_disconnect_phy(h);
3919}
3920
6871af29
JS		 3921static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3922{
3923 struct hnae3_handle *h = hns3_get_handle(netdev);
3924
3925 if (h->ae_algo->ops->del_all_fd_entries)
3926 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3927}
3928
a6d818e3
YL		 3929static int hns3_client_start(struct hnae3_handle *handle)
3930{
3931 if (!handle->ae_algo->ops->client_start)
3932 return 0;
3933
3934 return handle->ae_algo->ops->client_start(handle);
3935}
3936
3937static void hns3_client_stop(struct hnae3_handle *handle)
3938{
3939 if (!handle->ae_algo->ops->client_stop)
3940 return;
3941
3942 handle->ae_algo->ops->client_stop(handle);
3943}
3944
bb87be87
YL		 3945static void hns3_info_show(struct hns3_nic_priv *priv)
3946{
3947 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3948
3949 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
adcf738b
GL		 3950 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3951 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3952 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3953 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3954 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3955 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3956 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3957 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
bb87be87
YL		 3958}
3959
76ad4f0e
S		 3960static int hns3_client_init(struct hnae3_handle *handle)
3961{
3962 struct pci_dev *pdev = handle->pdev;
0d43bf45 3963 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3964 struct hns3_nic_priv *priv;
3965 struct net_device *netdev;
3966 int ret;
3967
0d43bf45
HT		 3968 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3969 &max_rss_size);
3970 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3971 if (!netdev)
3972 return -ENOMEM;
3973
3974 priv = netdev_priv(netdev);
3975 priv->dev = &pdev->dev;
3976 priv->netdev = netdev;
3977 priv->ae_handle = handle;
f8fa222c 3978 priv->tx_timeout_count = 0;
b7b585c2 3979 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 3980
bb87be87
YL		 3981 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3982
76ad4f0e
S		 3983 handle->kinfo.netdev = netdev;
3984 handle->priv = (void *)priv;
3985
8e6de441 3986 hns3_init_mac_addr(netdev);
76ad4f0e
S		 3987
3988 hns3_set_default_feature(netdev);
3989
3990 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3991 netdev->priv_flags |= IFF_UNICAST_FLT;
3992 netdev->netdev_ops = &hns3_nic_netdev_ops;
3993 SET_NETDEV_DEV(netdev, &pdev->dev);
3994 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 3995
3996 /* Carrier off reporting is important to ethtool even BEFORE open */
3997 netif_carrier_off(netdev);
3998
3999 ret = hns3_get_ring_config(priv);
4000 if (ret) {
4001 ret = -ENOMEM;
4002 goto out_get_ring_cfg;
4003 }
4004
dd38c726
YL		 4005 ret = hns3_nic_alloc_vector_data(priv);
4006 if (ret) {
4007 ret = -ENOMEM;
4008 goto out_alloc_vector_data;
4009 }
4010
76ad4f0e
S		 4011 ret = hns3_nic_init_vector_data(priv);
4012 if (ret) {
4013 ret = -ENOMEM;
4014 goto out_init_vector_data;
4015 }
4016
4017 ret = hns3_init_all_ring(priv);
4018 if (ret) {
4019 ret = -ENOMEM;
5f06b903 4020 goto out_init_ring;
76ad4f0e
S		 4021 }
4022
c8a8045b
HT		 4023 ret = hns3_init_phy(netdev);
4024 if (ret)
4025 goto out_init_phy;
4026
76ad4f0e
S		 4027 ret = register_netdev(netdev);
4028 if (ret) {
4029 dev_err(priv->dev, "probe register netdev fail!\n");
4030 goto out_reg_netdev_fail;
4031 }
4032
08a10068
YL		 4033 /* the device can work without cpu rmap, only aRFS needs it */
4034 ret = hns3_set_rx_cpu_rmap(netdev);
4035 if (ret)
4036 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4037
4038 ret = hns3_nic_init_irq(priv);
4039 if (ret) {
4040 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4041 hns3_free_rx_cpu_rmap(netdev);
4042 goto out_init_irq_fail;
4043 }
4044
a6d818e3
YL		 4045 ret = hns3_client_start(handle);
4046 if (ret) {
4047 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 4048 goto out_client_start;
a6d818e3
YL		 4049 }
4050
986743db
YL		 4051 hns3_dcbnl_setup(handle);
4052
b2292360 4053 hns3_dbg_init(handle);
4054
a0b43717 4055 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 4056 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 4057
814da63c
HT		 4058 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4059
bb87be87
YL		 4060 if (netif_msg_drv(handle))
4061 hns3_info_show(priv);
4062
76ad4f0e
S		 4063 return ret;
4064
18655128 4065out_client_start:
08a10068
YL		 4066 hns3_free_rx_cpu_rmap(netdev);
4067 hns3_nic_uninit_irq(priv);
4068out_init_irq_fail:
18655128 4069 unregister_netdev(netdev);
76ad4f0e 4070out_reg_netdev_fail:
c8a8045b
HT		 4071 hns3_uninit_phy(netdev);
4072out_init_phy:
4073 hns3_uninit_all_ring(priv);
5f06b903 4074out_init_ring:
e2152785 4075 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4076out_init_vector_data:
dd38c726
YL		 4077 hns3_nic_dealloc_vector_data(priv);
4078out_alloc_vector_data:
5f06b903 4079 priv->ring = NULL;
76ad4f0e
S		 4080out_get_ring_cfg:
4081 priv->ae_handle = NULL;
4082 free_netdev(netdev);
4083 return ret;
4084}
4085
4086static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4087{
4088 struct net_device *netdev = handle->kinfo.netdev;
4089 struct hns3_nic_priv *priv = netdev_priv(netdev);
4090 int ret;
4091
4092 if (netdev->reg_state != NETREG_UNINITIALIZED)
4093 unregister_netdev(netdev);
4094
eb32c896
HT		 4095 hns3_client_stop(handle);
4096
0d2f68c7
HT		 4097 hns3_uninit_phy(netdev);
4098
814da63c
HT		 4099 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4100 netdev_warn(netdev, "already uninitialized\n");
4101 goto out_netdev_free;
4102 }
4103
08a10068
YL		 4104 hns3_free_rx_cpu_rmap(netdev);
4105
4106 hns3_nic_uninit_irq(priv);
4107
dc5e6064
JS		 4108 hns3_del_all_fd_rules(netdev, true);
4109
f96315f2 4110 hns3_clear_all_ring(handle, true);
7b763f3f 4111
e2152785 4112 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4113
08a10068 4114 hns3_nic_dealloc_vector_data(priv);
dd38c726 4115
76ad4f0e
S		 4116 ret = hns3_uninit_all_ring(priv);
4117 if (ret)
4118 netdev_err(netdev, "uninit ring error\n");
4119
ec777890
YL		 4120 hns3_put_ring_config(priv);
4121
814da63c 4122out_netdev_free:
e22b5e72 4123 hns3_dbg_uninit(handle);
76ad4f0e
S		 4124 free_netdev(netdev);
4125}
4126
4127static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4128{
4129 struct net_device *netdev = handle->kinfo.netdev;
4130
4131 if (!netdev)
4132 return;
4133
4134 if (linkup) {
76ad4f0e 4135 netif_tx_wake_all_queues(netdev);
a7e90ee5 4136 netif_carrier_on(netdev);
bb87be87
YL		 4137 if (netif_msg_link(handle))
4138 netdev_info(netdev, "link up\n");
76ad4f0e
S		 4139 } else {
4140 netif_carrier_off(netdev);
4141 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 4142 if (netif_msg_link(handle))
4143 netdev_info(netdev, "link down\n");
76ad4f0e
S		 4144 }
4145}
4146
9df8f79a
YL		 4147static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4148{
4149 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4150 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL		 4151
4152 if (tc > HNAE3_MAX_TC)
4153 return -EINVAL;
4154
4155 if (!ndev)
4156 return -ENODEV;
4157
a1ef124e 4158 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL		 4159}
4160
beebca3a 4161static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 4162{
beebca3a 4163 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 4164 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL		 4165 hns3_free_buffer_detach(ring, ring->next_to_clean);
4166 ring_ptr_move_fw(ring, next_to_clean);
4167 }
4168}
4169
7b763f3f
FL		 4170static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4171{
4172 struct hns3_desc_cb res_cbs;
4173 int ret;
4174
4175 while (ring->next_to_use != ring->next_to_clean) {
4176 /* When a buffer is not reused, it's memory has been
4177 * freed in hns3_handle_rx_bd or will be freed by
4178 * stack, so we need to replace the buffer here.
4179 */
4180 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4d2cad32 4181 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
7b763f3f
FL		 4182 if (ret) {
4183 u64_stats_update_begin(&ring->syncp);
4184 ring->stats.sw_err_cnt++;
4185 u64_stats_update_end(&ring->syncp);
4186 /* if alloc new buffer fail, exit directly
4187 * and reclear in up flow.
4188 */
c8711956 4189 netdev_warn(ring_to_netdev(ring),
7b763f3f
FL		 4190 "reserve buffer map failed, ret = %d\n",
4191 ret);
4192 return ret;
4193 }
9b2f3477 4194 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL		 4195 }
4196 ring_ptr_move_fw(ring, next_to_use);
4197 }
4198
cc5ff6e9
PL		 4199 /* Free the pending skb in rx ring */
4200 if (ring->skb) {
4201 dev_kfree_skb_any(ring->skb);
4202 ring->skb = NULL;
4203 ring->pending_buf = 0;
4204 }
4205
7b763f3f
FL		 4206 return 0;
4207}
4208
4209static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4210{
beebca3a
YL		 4211 while (ring->next_to_use != ring->next_to_clean) {
4212 /* When a buffer is not reused, it's memory has been
4213 * freed in hns3_handle_rx_bd or will be freed by
4214 * stack, so only need to unmap the buffer here.
4215 */
4216 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4217 hns3_unmap_buffer(ring,
4218 &ring->desc_cb[ring->next_to_use]);
4219 ring->desc_cb[ring->next_to_use].dma = 0;
4220 }
4221
4222 ring_ptr_move_fw(ring, next_to_use);
4223 }
bb6b94a8
L		 4224}
4225
f96315f2 4226static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L		 4227{
4228 struct net_device *ndev = h->kinfo.netdev;
4229 struct hns3_nic_priv *priv = netdev_priv(ndev);
4230 u32 i;
4231
4232 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L		 4233 struct hns3_enet_ring *ring;
4234
5f06b903 4235 ring = &priv->ring[i];
beebca3a 4236 hns3_clear_tx_ring(ring);
bb6b94a8 4237
5f06b903 4238 ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 4239 /* Continue to clear other rings even if clearing some
4240 * rings failed.
4241 */
f96315f2
HT		 4242 if (force)
4243 hns3_force_clear_rx_ring(ring);
4244 else
4245 hns3_clear_rx_ring(ring);
bb6b94a8
L		 4246 }
4247}
4248
7b763f3f
FL		 4249int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4250{
4251 struct net_device *ndev = h->kinfo.netdev;
4252 struct hns3_nic_priv *priv = netdev_priv(ndev);
4253 struct hns3_enet_ring *rx_ring;
4254 int i, j;
4255 int ret;
4256
4257 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 4258 ret = h->ae_algo->ops->reset_queue(h, i);
4259 if (ret)
4260 return ret;
4261
5f06b903 4262 hns3_init_ring_hw(&priv->ring[i]);
7b763f3f
FL		 4263
4264 /* We need to clear tx ring here because self test will
4265 * use the ring and will not run down before up
4266 */
5f06b903
YL		 4267 hns3_clear_tx_ring(&priv->ring[i]);
4268 priv->ring[i].next_to_clean = 0;
4269 priv->ring[i].next_to_use = 0;
7b763f3f 4270
5f06b903 4271 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 4272 hns3_init_ring_hw(rx_ring);
4273 ret = hns3_clear_rx_ring(rx_ring);
4274 if (ret)
4275 return ret;
4276
4277 /* We can not know the hardware head and tail when this
4278 * function is called in reset flow, so we reuse all desc.
4279 */
4280 for (j = 0; j < rx_ring->desc_num; j++)
4281 hns3_reuse_buffer(rx_ring, j);
4282
4283 rx_ring->next_to_clean = 0;
4284 rx_ring->next_to_use = 0;
4285 }
4286
1c772154
YL		 4287 hns3_init_tx_ring_tc(priv);
4288
7b763f3f
FL		 4289 return 0;
4290}
4291
e4fd7502
HT		 4292static void hns3_store_coal(struct hns3_nic_priv *priv)
4293{
4294 /* ethtool only support setting and querying one coal
46ee7350
GL		 4295 * configuration for now, so save the vector 0' coal
4296 * configuration here in order to restore it.
e4fd7502
HT		 4297 */
4298 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4299 sizeof(struct hns3_enet_coalesce));
4300 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4301 sizeof(struct hns3_enet_coalesce));
4302}
4303
4304static void hns3_restore_coal(struct hns3_nic_priv *priv)
4305{
4306 u16 vector_num = priv->vector_num;
4307 int i;
4308
4309 for (i = 0; i < vector_num; i++) {
4310 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4311 sizeof(struct hns3_enet_coalesce));
4312 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4313 sizeof(struct hns3_enet_coalesce));
4314 }
4315}
4316
bb6b94a8
L		 4317static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4318{
4319 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4320 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 4321 struct hns3_nic_priv *priv = netdev_priv(ndev);
4322
4323 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4324 return 0;
bb6b94a8
L		 4325
4326 if (!netif_running(ndev))
6b1385cc 4327 return 0;
bb6b94a8
L		 4328
4329 return hns3_nic_net_stop(ndev);
4330}
4331
4332static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4333{
4334 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4335 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4336 int ret = 0;
4337
e8884027
HT		 4338 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4339
bb6b94a8 4340 if (netif_running(kinfo->netdev)) {
e8884027 4341 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4342 if (ret) {
e8884027 4343 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 4344 netdev_err(kinfo->netdev,
9b2f3477 4345 "net up fail, ret=%d!\n", ret);
bb6b94a8
L		 4346 return ret;
4347 }
bb6b94a8
L		 4348 }
4349
4350 return ret;
4351}
4352
4353static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4354{
4355 struct net_device *netdev = handle->kinfo.netdev;
4356 struct hns3_nic_priv *priv = netdev_priv(netdev);
4357 int ret;
4358
bb6b94a8
L		 4359 /* Carrier off reporting is important to ethtool even BEFORE open */
4360 netif_carrier_off(netdev);
4361
2c9dd668 4362 ret = hns3_get_ring_config(priv);
862d969a
HT		 4363 if (ret)
4364 return ret;
4365
2c9dd668
HT		 4366 ret = hns3_nic_alloc_vector_data(priv);
4367 if (ret)
4368 goto err_put_ring;
4369
e4fd7502
HT		 4370 hns3_restore_coal(priv);
4371
bb6b94a8
L		 4372 ret = hns3_nic_init_vector_data(priv);
4373 if (ret)
862d969a 4374 goto err_dealloc_vector;
bb6b94a8
L		 4375
4376 ret = hns3_init_all_ring(priv);
862d969a
HT		 4377 if (ret)
4378 goto err_uninit_vector;
bb6b94a8 4379
08a10068
YL		 4380 /* the device can work without cpu rmap, only aRFS needs it */
4381 ret = hns3_set_rx_cpu_rmap(netdev);
4382 if (ret)
4383 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4384
4385 ret = hns3_nic_init_irq(priv);
4386 if (ret) {
4387 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4388 hns3_free_rx_cpu_rmap(netdev);
4389 goto err_init_irq_fail;
4390 }
4391
ee4bcd3b
JS		 4392 if (!hns3_is_phys_func(handle->pdev))
4393 hns3_init_mac_addr(netdev);
4394
cd513a69
HT		 4395 ret = hns3_client_start(handle);
4396 if (ret) {
4397 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
08a10068 4398 goto err_client_start_fail;
cd513a69
HT		 4399 }
4400
814da63c
HT		 4401 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4402
862d969a
HT		 4403 return ret;
4404
08a10068
YL		 4405err_client_start_fail:
4406 hns3_free_rx_cpu_rmap(netdev);
4407 hns3_nic_uninit_irq(priv);
4408err_init_irq_fail:
cd513a69 4409 hns3_uninit_all_ring(priv);
862d969a
HT		 4410err_uninit_vector:
4411 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 4412err_dealloc_vector:
4413 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 4414err_put_ring:
4415 hns3_put_ring_config(priv);
862d969a 4416
bb6b94a8
L		 4417 return ret;
4418}
4419
4420static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4421{
4422 struct net_device *netdev = handle->kinfo.netdev;
4423 struct hns3_nic_priv *priv = netdev_priv(netdev);
4424 int ret;
4425
1eeb3367 4426 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 4427 netdev_warn(netdev, "already uninitialized\n");
4428 return 0;
4429 }
4430
08a10068
YL		 4431 hns3_free_rx_cpu_rmap(netdev);
4432 hns3_nic_uninit_irq(priv);
f96315f2
HT		 4433 hns3_clear_all_ring(handle, true);
4434 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 4435
e2152785 4436 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4437
e4fd7502
HT		 4438 hns3_store_coal(priv);
4439
08a10068 4440 hns3_nic_dealloc_vector_data(priv);
862d969a 4441
bb6b94a8
L		 4442 ret = hns3_uninit_all_ring(priv);
4443 if (ret)
4444 netdev_err(netdev, "uninit ring error\n");
4445
2c9dd668 4446 hns3_put_ring_config(priv);
2c9dd668 4447
bb6b94a8
L		 4448 return ret;
4449}
4450
4451static int hns3_reset_notify(struct hnae3_handle *handle,
4452 enum hnae3_reset_notify_type type)
4453{
4454 int ret = 0;
4455
4456 switch (type) {
4457 case HNAE3_UP_CLIENT:
e1586241
SM		 4458 ret = hns3_reset_notify_up_enet(handle);
4459 break;
bb6b94a8
L		 4460 case HNAE3_DOWN_CLIENT:
4461 ret = hns3_reset_notify_down_enet(handle);
4462 break;
4463 case HNAE3_INIT_CLIENT:
4464 ret = hns3_reset_notify_init_enet(handle);
4465 break;
4466 case HNAE3_UNINIT_CLIENT:
4467 ret = hns3_reset_notify_uninit_enet(handle);
4468 break;
4469 default:
4470 break;
4471 }
4472
4473 return ret;
4474}
4475
3a5a5f06
PL		 4476static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4477 bool rxfh_configured)
4478{
4479 int ret;
4480
4481 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4482 rxfh_configured);
4483 if (ret) {
4484 dev_err(&handle->pdev->dev,
4485 "Change tqp num(%u) fail.\n", new_tqp_num);
4486 return ret;
4487 }
4488
4489 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4490 if (ret)
4491 return ret;
4492
4493 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4494 if (ret)
4495 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4496
4497 return ret;
4498}
4499
09f2af64
PL		 4500int hns3_set_channels(struct net_device *netdev,
4501 struct ethtool_channels *ch)
4502{
09f2af64
PL		 4503 struct hnae3_handle *h = hns3_get_handle(netdev);
4504 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4505 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 4506 u32 new_tqp_num = ch->combined_count;
4507 u16 org_tqp_num;
4508 int ret;
4509
44950d28
JS		 4510 if (hns3_nic_resetting(netdev))
4511 return -EBUSY;
4512
09f2af64
PL		 4513 if (ch->rx_count || ch->tx_count)
4514 return -EINVAL;
4515
678335a1 4516 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4517 new_tqp_num < 1) {
09f2af64 4518 dev_err(&netdev->dev,
adcf738b 4519 "Change tqps fail, the tqp range is from 1 to %u",
678335a1 4520 hns3_get_max_available_channels(h));
09f2af64
PL		 4521 return -EINVAL;
4522 }
4523
c78b5b6c 4524 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 4525 return 0;
4526
1c822948
YL		 4527 netif_dbg(h, drv, netdev,
4528 "set channels: tqp_num=%u, rxfh=%d\n",
4529 new_tqp_num, rxfh_configured);
4530
65749f73
HT		 4531 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4532 if (ret)
4533 return ret;
dd38c726 4534
65749f73
HT		 4535 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4536 if (ret)
4537 return ret;
09f2af64
PL		 4538
4539 org_tqp_num = h->kinfo.num_tqps;
3a5a5f06 4540 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4541 if (ret) {
3a5a5f06
PL		 4542 int ret1;
4543
4544 netdev_warn(netdev,
4545 "Change channels fail, revert to old value\n");
4546 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4547 if (ret1) {
4548 netdev_err(netdev,
4549 "revert to old channel fail\n");
4550 return ret1;
09f2af64 4551 }
3a5a5f06 4552
65749f73 4553 return ret;
3a5a5f06 4554 }
09f2af64 4555
3a5a5f06 4556 return 0;
09f2af64
PL		 4557}
4558
a83d2961
WL		 4559static const struct hns3_hw_error_info hns3_hw_err[] = {
4560 { .type = HNAE3_PPU_POISON_ERROR,
4561 .msg = "PPU poison" },
4562 { .type = HNAE3_CMDQ_ECC_ERROR,
4563 .msg = "IMP CMDQ error" },
4564 { .type = HNAE3_IMP_RD_POISON_ERROR,
4565 .msg = "IMP RD poison" },
4566};
4567
4568static void hns3_process_hw_error(struct hnae3_handle *handle,
4569 enum hnae3_hw_error_type type)
4570{
4571 int i;
4572
4573 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4574 if (hns3_hw_err[i].type == type) {
4575 dev_err(&handle->pdev->dev, "Detected %s!\n",
4576 hns3_hw_err[i].msg);
4577 break;
4578 }
4579 }
4580}
4581
1db9b1bf 4582static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4583 .init_instance = hns3_client_init,
4584 .uninit_instance = hns3_client_uninit,
4585 .link_status_change = hns3_link_status_change,
9df8f79a 4586 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4587 .reset_notify = hns3_reset_notify,
a83d2961 4588 .process_hw_error = hns3_process_hw_error,
76ad4f0e
S		 4589};
4590
4591/* hns3_init_module - Driver registration routine
4592 * hns3_init_module is the first routine called when the driver is
4593 * loaded. All it does is register with the PCI subsystem.
4594 */
4595static int __init hns3_init_module(void)
4596{
4597 int ret;
4598
4599 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4600 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4601
4602 client.type = HNAE3_CLIENT_KNIC;
cdc37385 4603 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
76ad4f0e
S		 4604 hns3_driver_name);
4605
4606 client.ops = &client_ops;
4607
13562d1f
XW		 4608 INIT_LIST_HEAD(&client.node);
4609
b2292360 4610 hns3_dbg_register_debugfs(hns3_driver_name);
4611
76ad4f0e
S		 4612 ret = hnae3_register_client(&client);
4613 if (ret)
b2292360 4614 goto err_reg_client;
76ad4f0e
S		 4615
4616 ret = pci_register_driver(&hns3_driver);
4617 if (ret)
b2292360 4618 goto err_reg_driver;
76ad4f0e
S		 4619
4620 return ret;
b2292360 4621
4622err_reg_driver:
4623 hnae3_unregister_client(&client);
4624err_reg_client:
4625 hns3_dbg_unregister_debugfs();
4626 return ret;
76ad4f0e
S		 4627}
4628module_init(hns3_init_module);
4629
4630/* hns3_exit_module - Driver exit cleanup routine
4631 * hns3_exit_module is called just before the driver is removed
4632 * from memory.
4633 */
4634static void __exit hns3_exit_module(void)
4635{
4636 pci_unregister_driver(&hns3_driver);
4637 hnae3_unregister_client(&client);
b2292360 4638 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4639}
4640module_exit(hns3_exit_module);
4641
4642MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4643MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4644MODULE_LICENSE("GPL");
4645MODULE_ALIAS("pci:hns-nic");
Linux 6.x block layer and io_uring tree(s)