projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: hns3: remove unnecessary variable initialization
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e 10#include <linux/if_vlan.h>
e99a308d 11#include <linux/irq.h>
76ad4f0e
S		 12#include <linux/ip.h>
13#include <linux/ipv6.h>
14#include <linux/module.h>
15#include <linux/pci.h>
6ae4e733 16#include <linux/aer.h>
76ad4f0e
S		 17#include <linux/skbuff.h>
18#include <linux/sctp.h>
76ad4f0e 19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
76ad4f0e 23#include <net/vxlan.h>
a156998f 24#include <net/geneve.h>
76ad4f0e
S		 25
26#include "hnae3.h"
27#include "hns3_enet.h"
698a8954
YL		 28/* All hns3 tracepoints are defined by the include below, which
29 * must be included exactly once across the whole kernel with
30 * CREATE_TRACE_POINTS defined
31 */
32#define CREATE_TRACE_POINTS
33#include "hns3_trace.h"
76ad4f0e 34
cde4ffad 35#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 36#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 37
b20d7fe5
YL		 38#define hns3_rl_err(fmt, ...) \
39 do { \
40 if (net_ratelimit()) \
41 netdev_err(fmt, ##__VA_ARGS__); \
42 } while (0)
43
f96315f2 44static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
7b763f3f 45
1db9b1bf 46static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 47static const char hns3_driver_string[] =
48 "Hisilicon Ethernet Network Driver for Hip08 Family";
49static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
50static struct hnae3_client client;
51
bb87be87
YL		 52static int debug = -1;
53module_param(debug, int, 0);
54MODULE_PARM_DESC(debug, " Network interface message level setting");
55
56#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
58
eb977d99
YL		 59#define HNS3_INNER_VLAN_TAG 1
60#define HNS3_OUTER_VLAN_TAG 2
61
36c67349
YL		 62#define HNS3_MIN_TX_LEN 33U
63
76ad4f0e
S		 64/* hns3_pci_tbl - PCI Device ID Table
65 *
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
71static const struct pci_device_id hns3_pci_tbl[] = {
72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
07acf909
JS		 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
86 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 87 /* required last entry */
88 {0, }
89};
90MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
91
ef0c5009 92static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 93{
ef0c5009 94 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 95
fb00331b 96 napi_schedule_irqoff(&tqp_vector->napi);
76ad4f0e
S		 97
98 return IRQ_HANDLED;
99}
100
101static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
102{
103 struct hns3_enet_tqp_vector *tqp_vectors;
104 unsigned int i;
105
106 for (i = 0; i < priv->vector_num; i++) {
107 tqp_vectors = &priv->tqp_vector[i];
108
109 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
110 continue;
111
ffab9691 112 /* clear the affinity mask */
874bff0b
PL		 113 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
114
76ad4f0e
S		 115 /* release the irq resource */
116 free_irq(tqp_vectors->vector_irq, tqp_vectors);
117 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
118 }
119}
120
121static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
122{
123 struct hns3_enet_tqp_vector *tqp_vectors;
124 int txrx_int_idx = 0;
125 int rx_int_idx = 0;
126 int tx_int_idx = 0;
127 unsigned int i;
128 int ret;
129
130 for (i = 0; i < priv->vector_num; i++) {
131 tqp_vectors = &priv->tqp_vector[i];
132
133 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
134 continue;
135
136 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
5bffde62
YL		 137 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
138 "%s-%s-%s-%d", hns3_driver_name,
139 pci_name(priv->ae_handle->pdev),
140 "TxRx", txrx_int_idx++);
76ad4f0e
S		 141 txrx_int_idx++;
142 } else if (tqp_vectors->rx_group.ring) {
5bffde62
YL		 143 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
144 "%s-%s-%s-%d", hns3_driver_name,
145 pci_name(priv->ae_handle->pdev),
146 "Rx", rx_int_idx++);
76ad4f0e 147 } else if (tqp_vectors->tx_group.ring) {
5bffde62
YL		 148 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
149 "%s-%s-%s-%d", hns3_driver_name,
150 pci_name(priv->ae_handle->pdev),
151 "Tx", tx_int_idx++);
76ad4f0e
S		 152 } else {
153 /* Skip this unused q_vector */
154 continue;
155 }
156
157 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
158
e99a308d 159 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
76ad4f0e 160 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 161 tqp_vectors->name, tqp_vectors);
76ad4f0e
S		 162 if (ret) {
163 netdev_err(priv->netdev, "request irq(%d) fail\n",
164 tqp_vectors->vector_irq);
d547ecdc 165 hns3_nic_uninit_irq(priv);
76ad4f0e
S		 166 return ret;
167 }
168
874bff0b
PL		 169 irq_set_affinity_hint(tqp_vectors->vector_irq,
170 &tqp_vectors->affinity_mask);
171
76ad4f0e
S		 172 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
173 }
174
175 return 0;
176}
177
178static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
179 u32 mask_en)
180{
181 writel(mask_en, tqp_vector->mask_addr);
182}
183
184static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
185{
186 napi_enable(&tqp_vector->napi);
08a10068 187 enable_irq(tqp_vector->vector_irq);
76ad4f0e
S		 188
189 /* enable vector */
190 hns3_mask_vector_irq(tqp_vector, 1);
191}
192
193static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
194{
195 /* disable vector */
196 hns3_mask_vector_irq(tqp_vector, 0);
197
198 disable_irq(tqp_vector->vector_irq);
199 napi_disable(&tqp_vector->napi);
200}
201
434776a5
FL		 202void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
203 u32 rl_value)
76ad4f0e 204{
434776a5
FL		 205 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
206
76ad4f0e
S		 207 /* this defines the configuration for RL (Interrupt Rate Limiter).
208 * Rl defines rate of interrupts i.e. number of interrupts-per-second
209 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
210 */
434776a5 211
9bc727a9
YL		 212 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
213 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 214 /* According to the hardware, the range of rl_reg is
215 * 0-59 and the unit is 4.
216 */
217 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
218
219 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
220}
221
222void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
223 u32 gl_value)
224{
225 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
226
227 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
228}
229
230void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
231 u32 gl_value)
232{
233 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
234
235 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 236}
237
5fd4789a
FL		 238static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
239 struct hns3_nic_priv *priv)
76ad4f0e
S		 240{
241 /* initialize the configuration for interrupt coalescing.
242 * 1. GL (Interrupt Gap Limiter)
243 * 2. RL (Interrupt Rate Limiter)
46ee7350
GL		 244 *
245 * Default: enable interrupt coalescing self-adaptive and GL
76ad4f0e 246 */
9bc727a9
YL		 247 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
248 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 249
9bc727a9
YL		 250 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
251 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 252
9bc727a9
YL		 253 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
254 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 255}
256
dd38c726
YL		 257static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
258 struct hns3_nic_priv *priv)
259{
260 struct hnae3_handle *h = priv->ae_handle;
261
262 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 263 tqp_vector->tx_group.coal.int_gl);
dd38c726 264 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 265 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 266 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
267}
268
9df8f79a
YL		 269static int hns3_nic_set_real_num_queue(struct net_device *netdev)
270{
9780cb97 271 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 272 struct hnae3_knic_private_info *kinfo = &h->kinfo;
273 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
a75a8efa
YL		 274 int i, ret;
275
276 if (kinfo->num_tc <= 1) {
277 netdev_reset_tc(netdev);
278 } else {
279 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
280 if (ret) {
281 netdev_err(netdev,
282 "netdev_set_num_tc fail, ret=%d!\n", ret);
283 return ret;
284 }
285
286 for (i = 0; i < HNAE3_MAX_TC; i++) {
287 if (!kinfo->tc_info[i].enable)
288 continue;
289
290 netdev_set_tc_queue(netdev,
291 kinfo->tc_info[i].tc,
292 kinfo->tc_info[i].tqp_count,
293 kinfo->tc_info[i].tqp_offset);
294 }
295 }
9df8f79a
YL		 296
297 ret = netif_set_real_num_tx_queues(netdev, queue_size);
298 if (ret) {
299 netdev_err(netdev,
9b2f3477 300 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL		 301 return ret;
302 }
303
304 ret = netif_set_real_num_rx_queues(netdev, queue_size);
305 if (ret) {
306 netdev_err(netdev,
307 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
308 return ret;
309 }
310
311 return 0;
312}
313
678335a1
PL		 314static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
315{
0d43bf45 316 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 317
0d43bf45
HT		 318 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
319 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 320
0d43bf45 321 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 322}
323
8df0fa91
HT		 324static void hns3_tqp_enable(struct hnae3_queue *tqp)
325{
326 u32 rcb_reg;
327
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg |= BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
331}
332
333static void hns3_tqp_disable(struct hnae3_queue *tqp)
334{
335 u32 rcb_reg;
336
337 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
338 rcb_reg &= ~BIT(HNS3_RING_EN_B);
339 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
340}
341
ffab9691
JS		 342static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
343{
344#ifdef CONFIG_RFS_ACCEL
345 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
346 netdev->rx_cpu_rmap = NULL;
347#endif
348}
349
350static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
351{
352#ifdef CONFIG_RFS_ACCEL
353 struct hns3_nic_priv *priv = netdev_priv(netdev);
354 struct hns3_enet_tqp_vector *tqp_vector;
355 int i, ret;
356
357 if (!netdev->rx_cpu_rmap) {
358 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
359 if (!netdev->rx_cpu_rmap)
360 return -ENOMEM;
361 }
362
363 for (i = 0; i < priv->vector_num; i++) {
364 tqp_vector = &priv->tqp_vector[i];
365 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
366 tqp_vector->vector_irq);
367 if (ret) {
368 hns3_free_rx_cpu_rmap(netdev);
369 return ret;
370 }
371 }
372#endif
373 return 0;
374}
375
76ad4f0e
S		 376static int hns3_nic_net_up(struct net_device *netdev)
377{
378 struct hns3_nic_priv *priv = netdev_priv(netdev);
379 struct hnae3_handle *h = priv->ae_handle;
380 int i, j;
381 int ret;
382
7b763f3f
FL		 383 ret = hns3_nic_reset_all_ring(h);
384 if (ret)
385 return ret;
386
b7b585c2
JS		 387 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
388
76ad4f0e
S		 389 /* enable the vectors */
390 for (i = 0; i < priv->vector_num; i++)
391 hns3_vector_enable(&priv->tqp_vector[i]);
392
8df0fa91
HT		 393 /* enable rcb */
394 for (j = 0; j < h->kinfo.num_tqps; j++)
395 hns3_tqp_enable(h->kinfo.tqp[j]);
396
76ad4f0e
S		 397 /* start the ae_dev */
398 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
08a10068
YL		 399 if (ret) {
400 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
401 while (j--)
402 hns3_tqp_disable(h->kinfo.tqp[j]);
8df0fa91 403
08a10068
YL		 404 for (j = i - 1; j >= 0; j--)
405 hns3_vector_disable(&priv->tqp_vector[j]);
406 }
76ad4f0e 407
76ad4f0e
S		 408 return ret;
409}
410
2a73ac3e
YL		 411static void hns3_config_xps(struct hns3_nic_priv *priv)
412{
413 int i;
414
415 for (i = 0; i < priv->vector_num; i++) {
416 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
417 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
418
419 while (ring) {
420 int ret;
421
422 ret = netif_set_xps_queue(priv->netdev,
423 &tqp_vector->affinity_mask,
424 ring->tqp->tqp_index);
425 if (ret)
426 netdev_warn(priv->netdev,
427 "set xps queue failed: %d", ret);
428
429 ring = ring->next;
430 }
431 }
432}
433
76ad4f0e
S		 434static int hns3_nic_net_open(struct net_device *netdev)
435{
8cdb992f 436 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 437 struct hnae3_handle *h = hns3_get_handle(netdev);
438 struct hnae3_knic_private_info *kinfo;
439 int i, ret;
76ad4f0e 440
257e4f29
HT		 441 if (hns3_nic_resetting(netdev))
442 return -EBUSY;
443
76ad4f0e
S		 444 netif_carrier_off(netdev);
445
9df8f79a
YL		 446 ret = hns3_nic_set_real_num_queue(netdev);
447 if (ret)
76ad4f0e 448 return ret;
76ad4f0e
S		 449
450 ret = hns3_nic_net_up(netdev);
451 if (ret) {
9b2f3477 452 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S		 453 return ret;
454 }
455
a75a8efa 456 kinfo = &h->kinfo;
9b2f3477
WL		 457 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
458 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
a75a8efa 459
8cdb992f
JS		 460 if (h->ae_algo->ops->set_timer_task)
461 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
462
2a73ac3e 463 hns3_config_xps(priv);
1c822948
YL		 464
465 netif_dbg(h, drv, netdev, "net open\n");
466
76ad4f0e
S		 467 return 0;
468}
469
f96315f2
HT		 470static void hns3_reset_tx_queue(struct hnae3_handle *h)
471{
472 struct net_device *ndev = h->kinfo.netdev;
473 struct hns3_nic_priv *priv = netdev_priv(ndev);
474 struct netdev_queue *dev_queue;
475 u32 i;
476
477 for (i = 0; i < h->kinfo.num_tqps; i++) {
478 dev_queue = netdev_get_tx_queue(ndev,
5f06b903 479 priv->ring[i].queue_index);
f96315f2
HT		 480 netdev_tx_reset_queue(dev_queue);
481 }
482}
483
76ad4f0e
S		 484static void hns3_nic_net_down(struct net_device *netdev)
485{
486 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 487 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 488 const struct hnae3_ae_ops *ops;
489 int i;
490
7b763f3f
FL		 491 /* disable vectors */
492 for (i = 0; i < priv->vector_num; i++)
493 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 494
495 /* disable rcb */
496 for (i = 0; i < h->kinfo.num_tqps; i++)
497 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 498
76ad4f0e
S		 499 /* stop ae_dev */
500 ops = priv->ae_handle->ae_algo->ops;
501 if (ops->stop)
502 ops->stop(priv->ae_handle);
503
3a30964a
YL		 504 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
505 * during reset process, because driver may not be able
506 * to disable the ring through firmware when downing the netdev.
507 */
508 if (!hns3_nic_resetting(netdev))
f96315f2
HT		 509 hns3_clear_all_ring(priv->ae_handle, false);
510
511 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S		 512}
513
514static int hns3_nic_net_stop(struct net_device *netdev)
515{
ff0699e0 516 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 517 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 518
519 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
520 return 0;
521
1c822948
YL		 522 netif_dbg(h, drv, netdev, "net stop\n");
523
8cdb992f
JS		 524 if (h->ae_algo->ops->set_timer_task)
525 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
526
76ad4f0e
S		 527 netif_tx_stop_all_queues(netdev);
528 netif_carrier_off(netdev);
529
530 hns3_nic_net_down(netdev);
531
532 return 0;
533}
534
76ad4f0e
S		 535static int hns3_nic_uc_sync(struct net_device *netdev,
536 const unsigned char *addr)
537{
9780cb97 538 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 539
540 if (h->ae_algo->ops->add_uc_addr)
541 return h->ae_algo->ops->add_uc_addr(h, addr);
542
543 return 0;
544}
545
546static int hns3_nic_uc_unsync(struct net_device *netdev,
547 const unsigned char *addr)
548{
9780cb97 549 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 550
ee4bcd3b
JS		 551 /* need ignore the request of removing device address, because
552 * we store the device address and other addresses of uc list
553 * in the function's mac filter list.
554 */
555 if (ether_addr_equal(addr, netdev->dev_addr))
556 return 0;
557
76ad4f0e
S		 558 if (h->ae_algo->ops->rm_uc_addr)
559 return h->ae_algo->ops->rm_uc_addr(h, addr);
560
561 return 0;
562}
563
564static int hns3_nic_mc_sync(struct net_device *netdev,
565 const unsigned char *addr)
566{
9780cb97 567 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 568
720a8478 569 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 570 return h->ae_algo->ops->add_mc_addr(h, addr);
571
572 return 0;
573}
574
575static int hns3_nic_mc_unsync(struct net_device *netdev,
576 const unsigned char *addr)
577{
9780cb97 578 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 579
720a8478 580 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 581 return h->ae_algo->ops->rm_mc_addr(h, addr);
582
583 return 0;
584}
585
c60edc17
JS		 586static u8 hns3_get_netdev_flags(struct net_device *netdev)
587{
588 u8 flags = 0;
589
590 if (netdev->flags & IFF_PROMISC) {
28673b33 591 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS		 592 } else {
593 flags |= HNAE3_VLAN_FLTR;
594 if (netdev->flags & IFF_ALLMULTI)
595 flags |= HNAE3_USER_MPE;
596 }
597
598 return flags;
599}
600
1db9b1bf 601static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 602{
9780cb97 603 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17 604 u8 new_flags;
76ad4f0e 605
c60edc17
JS		 606 new_flags = hns3_get_netdev_flags(netdev);
607
c631c696
JS		 608 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
609 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
c60edc17 610
c60edc17 611 /* User mode Promisc mode enable and vlan filtering is disabled to
c631c696 612 * let all packets in.
c60edc17 613 */
c60edc17 614 h->netdev_flags = new_flags;
c631c696
JS		 615 hns3_request_update_promisc_mode(h);
616}
617
618void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
619{
620 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
621
622 if (ops->request_update_promisc_mode)
623 ops->request_update_promisc_mode(handle);
c60edc17
JS		 624}
625
c60edc17
JS		 626void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
627{
628 struct hns3_nic_priv *priv = netdev_priv(netdev);
629 struct hnae3_handle *h = priv->ae_handle;
630 bool last_state;
631
632 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
633 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
634 if (enable != last_state) {
635 netdev_info(netdev,
636 "%s vlan filter\n",
637 enable ? "enable" : "disable");
638 h->ae_algo->ops->enable_vlan_filter(h, enable);
639 }
40cca1c5 640 }
76ad4f0e
S		 641}
642
643static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
644 u16 *mss, u32 *type_cs_vlan_tso)
645{
646 u32 l4_offset, hdr_len;
647 union l3_hdr_info l3;
648 union l4_hdr_info l4;
649 u32 l4_paylen;
650 int ret;
651
652 if (!skb_is_gso(skb))
653 return 0;
654
655 ret = skb_cow_head(skb, 0);
8ae10cfb 656 if (unlikely(ret < 0))
76ad4f0e
S		 657 return ret;
658
659 l3.hdr = skb_network_header(skb);
660 l4.hdr = skb_transport_header(skb);
661
662 /* Software should clear the IPv4's checksum field when tso is
663 * needed.
664 */
665 if (l3.v4->version == 4)
666 l3.v4->check = 0;
667
9b2f3477 668 /* tunnel packet */
76ad4f0e
S		 669 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
670 SKB_GSO_GRE_CSUM |
671 SKB_GSO_UDP_TUNNEL |
672 SKB_GSO_UDP_TUNNEL_CSUM)) {
673 if ((!(skb_shinfo(skb)->gso_type &
674 SKB_GSO_PARTIAL)) &&
675 (skb_shinfo(skb)->gso_type &
676 SKB_GSO_UDP_TUNNEL_CSUM)) {
677 /* Software should clear the udp's checksum
678 * field when tso is needed.
679 */
680 l4.udp->check = 0;
681 }
682 /* reset l3&l4 pointers from outer to inner headers */
683 l3.hdr = skb_inner_network_header(skb);
684 l4.hdr = skb_inner_transport_header(skb);
685
686 /* Software should clear the IPv4's checksum field when
687 * tso is needed.
688 */
689 if (l3.v4->version == 4)
690 l3.v4->check = 0;
691 }
692
9b2f3477 693 /* normal or tunnel packet */
76ad4f0e 694 l4_offset = l4.hdr - skb->data;
3fe13ed9 695 hdr_len = (l4.tcp->doff << 2) + l4_offset;
76ad4f0e 696
9b2f3477 697 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e
S		 698 l4_paylen = skb->len - l4_offset;
699 csum_replace_by_diff(&l4.tcp->check,
700 (__force __wsum)htonl(l4_paylen));
701
702 /* find the txbd field values */
703 *paylen = skb->len - hdr_len;
cde4ffad 704 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 705
706 /* get MSS for TSO */
707 *mss = skb_shinfo(skb)->gso_size;
708
698a8954
YL		 709 trace_hns3_tso(skb);
710
76ad4f0e
S		 711 return 0;
712}
713
1898d4e4
S		 714static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
715 u8 *il4_proto)
76ad4f0e 716{
1a6e552d 717 union l3_hdr_info l3;
76ad4f0e
S		 718 unsigned char *l4_hdr;
719 unsigned char *exthdr;
720 u8 l4_proto_tmp;
721 __be16 frag_off;
722
723 /* find outer header point */
724 l3.hdr = skb_network_header(skb);
35f58fd7 725 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 726
727 if (skb->protocol == htons(ETH_P_IPV6)) {
728 exthdr = l3.hdr + sizeof(*l3.v6);
729 l4_proto_tmp = l3.v6->nexthdr;
730 if (l4_hdr != exthdr)
731 ipv6_skip_exthdr(skb, exthdr - skb->data,
732 &l4_proto_tmp, &frag_off);
733 } else if (skb->protocol == htons(ETH_P_IP)) {
734 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 735 } else {
736 return -EINVAL;
76ad4f0e
S		 737 }
738
739 *ol4_proto = l4_proto_tmp;
740
741 /* tunnel packet */
742 if (!skb->encapsulation) {
743 *il4_proto = 0;
1898d4e4 744 return 0;
76ad4f0e
S		 745 }
746
747 /* find inner header point */
748 l3.hdr = skb_inner_network_header(skb);
749 l4_hdr = skb_inner_transport_header(skb);
750
751 if (l3.v6->version == 6) {
752 exthdr = l3.hdr + sizeof(*l3.v6);
753 l4_proto_tmp = l3.v6->nexthdr;
754 if (l4_hdr != exthdr)
755 ipv6_skip_exthdr(skb, exthdr - skb->data,
756 &l4_proto_tmp, &frag_off);
757 } else if (l3.v4->version == 4) {
758 l4_proto_tmp = l3.v4->protocol;
759 }
760
761 *il4_proto = l4_proto_tmp;
1898d4e4
S		 762
763 return 0;
76ad4f0e
S		 764}
765
3db084d2
YL		 766/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
767 * and it is udp packet, which has a dest port as the IANA assigned.
768 * the hardware is expected to do the checksum offload, but the
769 * hardware will not do the checksum offload when udp dest port is
a156998f 770 * 4789 or 6081.
3db084d2
YL		 771 */
772static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
773{
1a6e552d 774 union l4_hdr_info l4;
3db084d2
YL		 775
776 l4.hdr = skb_transport_header(skb);
777
bea96410 778 if (!(!skb->encapsulation &&
a156998f
YL		 779 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
780 l4.udp->dest == htons(GENEVE_UDP_PORT))))
3db084d2
YL		 781 return false;
782
783 skb_checksum_help(skb);
784
785 return true;
786}
787
757cd1e4
YL		 788static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
789 u32 *ol_type_vlan_len_msec)
76ad4f0e 790{
757cd1e4
YL		 791 u32 l2_len, l3_len, l4_len;
792 unsigned char *il2_hdr;
1a6e552d 793 union l3_hdr_info l3;
757cd1e4 794 union l4_hdr_info l4;
76ad4f0e
S		 795
796 l3.hdr = skb_network_header(skb);
757cd1e4 797 l4.hdr = skb_transport_header(skb);
76ad4f0e 798
757cd1e4
YL		 799 /* compute OL2 header size, defined in 2 Bytes */
800 l2_len = l3.hdr - skb->data;
801 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
802
803 /* compute OL3 header size, defined in 4 Bytes */
804 l3_len = l4.hdr - l3.hdr;
805 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 806
757cd1e4 807 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 808 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL		 809 l4_len = il2_hdr - l4.hdr;
810 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
811
812 /* define outer network header type */
813 if (skb->protocol == htons(ETH_P_IP)) {
814 if (skb_is_gso(skb))
cde4ffad 815 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 816 HNS3_TXD_OL3T_S,
817 HNS3_OL3T_IPV4_CSUM);
818 else
cde4ffad 819 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 820 HNS3_TXD_OL3T_S,
821 HNS3_OL3T_IPV4_NO_CSUM);
822
823 } else if (skb->protocol == htons(ETH_P_IPV6)) {
824 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
825 HNS3_OL3T_IPV6);
826 }
827
828 if (ol4_proto == IPPROTO_UDP)
829 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
830 HNS3_TUN_MAC_IN_UDP);
831 else if (ol4_proto == IPPROTO_GRE)
832 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
833 HNS3_TUN_NVGRE);
834}
835
836static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
837 u8 il4_proto, u32 *type_cs_vlan_tso,
838 u32 *ol_type_vlan_len_msec)
839{
c264ed44 840 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 841 u32 l4_proto = ol4_proto;
842 union l4_hdr_info l4;
843 union l3_hdr_info l3;
844 u32 l2_len, l3_len;
845
846 l4.hdr = skb_transport_header(skb);
847 l3.hdr = skb_network_header(skb);
848
849 /* handle encapsulation skb */
850 if (skb->encapsulation) {
851 /* If this is a not UDP/GRE encapsulation skb */
852 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 853 /* drop the skb tunnel packet if hardware don't support,
854 * because hardware can't calculate csum when TSO.
855 */
856 if (skb_is_gso(skb))
857 return -EDOM;
858
859 /* the stack computes the IP header already,
860 * driver calculate l4 checksum when not TSO.
861 */
862 skb_checksum_help(skb);
863 return 0;
864 }
865
757cd1e4
YL		 866 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
867
868 /* switch to inner header */
869 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 870 l3.hdr = skb_inner_network_header(skb);
757cd1e4 871 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 872 l4_proto = il4_proto;
873 }
874
875 if (l3.v4->version == 4) {
cde4ffad
YL		 876 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
877 HNS3_L3T_IPV4);
76ad4f0e
S		 878
879 /* the stack computes the IP header already, the only time we
880 * need the hardware to recompute it is in the case of TSO.
881 */
882 if (skb_is_gso(skb))
cde4ffad 883 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 884 } else if (l3.v6->version == 6) {
cde4ffad
YL		 885 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
886 HNS3_L3T_IPV6);
76ad4f0e
S		 887 }
888
757cd1e4
YL		 889 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
890 l2_len = l3.hdr - l2_hdr;
891 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
892
893 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
894 l3_len = l4.hdr - l3.hdr;
895 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
896
897 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 898 switch (l4_proto) {
899 case IPPROTO_TCP:
cde4ffad
YL		 900 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
901 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
902 HNS3_L4T_TCP);
757cd1e4
YL		 903 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
904 l4.tcp->doff);
76ad4f0e
S		 905 break;
906 case IPPROTO_UDP:
3db084d2
YL		 907 if (hns3_tunnel_csum_bug(skb))
908 break;
909
cde4ffad
YL		 910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
911 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
912 HNS3_L4T_UDP);
757cd1e4
YL		 913 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
914 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 915 break;
916 case IPPROTO_SCTP:
cde4ffad
YL		 917 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
918 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
919 HNS3_L4T_SCTP);
757cd1e4
YL		 920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
921 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 922 break;
923 default:
924 /* drop the skb tunnel packet if hardware don't support,
925 * because hardware can't calculate csum when TSO.
926 */
927 if (skb_is_gso(skb))
928 return -EDOM;
929
930 /* the stack computes the IP header already,
931 * driver calculate l4 checksum when not TSO.
932 */
933 skb_checksum_help(skb);
934 return 0;
935 }
936
937 return 0;
938}
939
eb977d99
YL		 940static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
941 struct sk_buff *skb)
9699cffe 942{
44e626f7 943 struct hnae3_handle *handle = tx_ring->tqp->handle;
eb977d99
YL		 944 struct vlan_ethhdr *vhdr;
945 int rc;
946
947 if (!(skb->protocol == htons(ETH_P_8021Q) ||
948 skb_vlan_tag_present(skb)))
949 return 0;
44e626f7
JS		 950
951 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
952 * header is allowed in skb, otherwise it will cause RAS error.
953 */
954 if (unlikely(skb_vlan_tagged_multi(skb) &&
955 handle->port_base_vlan_state ==
956 HNAE3_PORT_BASE_VLAN_ENABLE))
957 return -EINVAL;
958
9699cffe 959 if (skb->protocol == htons(ETH_P_8021Q) &&
eb977d99 960 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
9699cffe
PL		 961 /* When HW VLAN acceleration is turned off, and the stack
962 * sets the protocol to 802.1q, the driver just need to
963 * set the protocol to the encapsulated ethertype.
964 */
965 skb->protocol = vlan_get_protocol(skb);
966 return 0;
967 }
968
969 if (skb_vlan_tag_present(skb)) {
9699cffe
PL		 970 /* Based on hw strategy, use out_vtag in two layer tag case,
971 * and use inner_vtag in one tag case.
972 */
eb977d99
YL		 973 if (skb->protocol == htons(ETH_P_8021Q) &&
974 handle->port_base_vlan_state ==
975 HNAE3_PORT_BASE_VLAN_DISABLE)
976 rc = HNS3_OUTER_VLAN_TAG;
977 else
978 rc = HNS3_INNER_VLAN_TAG;
979
980 skb->protocol = vlan_get_protocol(skb);
981 return rc;
9699cffe
PL		 982 }
983
eb977d99
YL		 984 rc = skb_cow_head(skb, 0);
985 if (unlikely(rc < 0))
986 return rc;
987
988 vhdr = (struct vlan_ethhdr *)skb->data;
989 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
990 & VLAN_PRIO_MASK);
991
9699cffe
PL		 992 skb->protocol = vlan_get_protocol(skb);
993 return 0;
994}
995
eb977d99
YL		 996static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
997 struct sk_buff *skb, struct hns3_desc *desc)
998{
999 u32 ol_type_vlan_len_msec = 0;
1000 u32 type_cs_vlan_tso = 0;
1001 u32 paylen = skb->len;
1002 u16 inner_vtag = 0;
1003 u16 out_vtag = 0;
1004 u16 mss = 0;
1005 int ret;
1006
1007 ret = hns3_handle_vtags(ring, skb);
1008 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1009 u64_stats_update_begin(&ring->syncp);
1010 ring->stats.tx_vlan_err++;
1011 u64_stats_update_end(&ring->syncp);
eb977d99
YL		 1012 return ret;
1013 } else if (ret == HNS3_INNER_VLAN_TAG) {
1014 inner_vtag = skb_vlan_tag_get(skb);
1015 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1016 VLAN_PRIO_MASK;
1017 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1018 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1019 out_vtag = skb_vlan_tag_get(skb);
1020 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1021 VLAN_PRIO_MASK;
1022 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1023 1);
1024 }
1025
1026 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1027 u8 ol4_proto, il4_proto;
1028
1029 skb_reset_mac_len(skb);
1030
1031 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
8ae10cfb 1032 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1033 u64_stats_update_begin(&ring->syncp);
1034 ring->stats.tx_l4_proto_err++;
1035 u64_stats_update_end(&ring->syncp);
eb977d99 1036 return ret;
b20d7fe5 1037 }
eb977d99
YL		 1038
1039 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1040 &type_cs_vlan_tso,
1041 &ol_type_vlan_len_msec);
8ae10cfb 1042 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1043 u64_stats_update_begin(&ring->syncp);
1044 ring->stats.tx_l2l3l4_err++;
1045 u64_stats_update_end(&ring->syncp);
eb977d99 1046 return ret;
b20d7fe5 1047 }
eb977d99
YL		 1048
1049 ret = hns3_set_tso(skb, &paylen, &mss,
1050 &type_cs_vlan_tso);
8ae10cfb 1051 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1052 u64_stats_update_begin(&ring->syncp);
1053 ring->stats.tx_tso_err++;
1054 u64_stats_update_end(&ring->syncp);
eb977d99 1055 return ret;
b20d7fe5 1056 }
eb977d99
YL		 1057 }
1058
1059 /* Set txbd */
1060 desc->tx.ol_type_vlan_len_msec =
1061 cpu_to_le32(ol_type_vlan_len_msec);
1062 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1063 desc->tx.paylen = cpu_to_le32(paylen);
1064 desc->tx.mss = cpu_to_le16(mss);
1065 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1066 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1067
1068 return 0;
1069}
1070
76ad4f0e 1071static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
8ae10cfb 1072 unsigned int size, enum hns_desc_type type)
76ad4f0e 1073{
8ae10cfb
YL		 1074#define HNS3_LIKELY_BD_NUM 1
1075
76ad4f0e
S		 1076 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1077 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1078 struct device *dev = ring_to_dev(ring);
d7840976 1079 skb_frag_t *frag;
1e8a7977 1080 unsigned int frag_buf_num;
47e7b13b 1081 int k, sizeoflast;
5188f218 1082 dma_addr_t dma;
76ad4f0e 1083
cfdaeba5
YL		 1084 if (type == DESC_TYPE_FRAGLIST_SKB ||
1085 type == DESC_TYPE_SKB) {
74ef402e
HT		 1086 struct sk_buff *skb = (struct sk_buff *)priv;
1087
5188f218
PL		 1088 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1089 } else {
d7840976 1090 frag = (skb_frag_t *)priv;
5188f218
PL		 1091 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1092 }
1093
845e0d1d 1094 if (unlikely(dma_mapping_error(dev, dma))) {
b20d7fe5 1095 u64_stats_update_begin(&ring->syncp);
5188f218 1096 ring->stats.sw_err_cnt++;
b20d7fe5 1097 u64_stats_update_end(&ring->syncp);
5188f218 1098 return -ENOMEM;
76ad4f0e
S		 1099 }
1100
0ec3b6a7 1101 desc_cb->priv = priv;
bcdb12b7 1102 desc_cb->length = size;
0ec3b6a7
YL		 1103 desc_cb->dma = dma;
1104 desc_cb->type = type;
bcdb12b7 1105
ceca4a5e 1106 if (likely(size <= HNS3_MAX_BD_SIZE)) {
ceca4a5e
YL		 1107 desc->addr = cpu_to_le64(dma);
1108 desc->tx.send_size = cpu_to_le16(size);
ceca4a5e 1109 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1110 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
ceca4a5e 1111
698a8954 1112 trace_hns3_tx_desc(ring, ring->next_to_use);
ceca4a5e 1113 ring_ptr_move_fw(ring, next_to_use);
8ae10cfb 1114 return HNS3_LIKELY_BD_NUM;
ceca4a5e
YL		 1115 }
1116
5f543a54 1117 frag_buf_num = hns3_tx_bd_count(size);
48ae74c9 1118 sizeoflast = size % HNS3_MAX_BD_SIZE;
1e8a7977
FL		 1119 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1120
1121 /* When frag size is bigger than hardware limit, split this frag */
1122 for (k = 0; k < frag_buf_num; k++) {
1e8a7977
FL		 1123 /* now, fill the descriptor */
1124 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1125 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1126 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977 1127 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1128 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1e8a7977 1129
698a8954 1130 trace_hns3_tx_desc(ring, ring->next_to_use);
9b2f3477 1131 /* move ring pointer to next */
1e8a7977
FL		 1132 ring_ptr_move_fw(ring, next_to_use);
1133
1e8a7977
FL		 1134 desc = &ring->desc[ring->next_to_use];
1135 }
76ad4f0e 1136
8ae10cfb 1137 return frag_buf_num;
76ad4f0e
S		 1138}
1139
8ae10cfb
YL		 1140static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1141 unsigned int bd_num)
76ad4f0e 1142{
8ae10cfb 1143 unsigned int size;
42611b70 1144 int i;
76ad4f0e 1145
8ae10cfb
YL		 1146 size = skb_headlen(skb);
1147 while (size > HNS3_MAX_BD_SIZE) {
1148 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1149 size -= HNS3_MAX_BD_SIZE;
1150
1151 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1152 return bd_num;
1153 }
76ad4f0e 1154
8ae10cfb
YL		 1155 if (size) {
1156 bd_size[bd_num++] = size;
1157 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1158 return bd_num;
1159 }
76ad4f0e 1160
3d5f3741 1161 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
d7840976 1162 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8ae10cfb
YL		 1163 size = skb_frag_size(frag);
1164 if (!size)
1165 continue;
1166
1167 while (size > HNS3_MAX_BD_SIZE) {
1168 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1169 size -= HNS3_MAX_BD_SIZE;
1170
1171 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1172 return bd_num;
1173 }
1174
1175 bd_size[bd_num++] = size;
1176 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1177 return bd_num;
1178 }
1179
1180 return bd_num;
1181}
1182
1183static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1184{
1185 struct sk_buff *frag_skb;
1186 unsigned int bd_num = 0;
1187
1188 /* If the total len is within the max bd limit */
1189 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1190 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1191 return skb_shinfo(skb)->nr_frags + 1U;
1192
1193 /* The below case will always be linearized, return
1194 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1195 */
1196 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1197 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1198 return HNS3_MAX_TSO_BD_NUM + 1U;
1199
1200 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1201
1202 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1203 return bd_num;
1204
1205 skb_walk_frags(skb, frag_skb) {
1206 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1207 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1208 return bd_num;
3d5f3741 1209 }
76ad4f0e 1210
3d5f3741 1211 return bd_num;
76ad4f0e
S		 1212}
1213
db4970aa
YL		 1214static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1215{
1216 if (!skb->encapsulation)
1217 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1218
1219 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1220}
1221
1222/* HW need every continuous 8 buffer data to be larger than MSS,
1223 * we simplify it by ensuring skb_headlen + the first continuous
1224 * 7 frags to to be larger than gso header len + mss, and the remaining
1225 * continuous 7 frags to be larger than MSS except the last 7 frags.
1226 */
8ae10cfb
YL		 1227static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1228 unsigned int bd_num)
db4970aa 1229{
db4970aa
YL		 1230 unsigned int tot_len = 0;
1231 int i;
1232
8ae10cfb
YL		 1233 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1234 tot_len += bd_size[i];
db4970aa 1235
8ae10cfb
YL		 1236 /* ensure the first 8 frags is greater than mss + header */
1237 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1238 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
db4970aa
YL		 1239 return true;
1240
8ae10cfb
YL		 1241 /* ensure every continuous 7 buffer is greater than mss
1242 * except the last one.
1243 */
1244 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1245 tot_len -= bd_size[i];
1246 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
db4970aa
YL		 1247
1248 if (tot_len < skb_shinfo(skb)->gso_size)
1249 return true;
1250 }
1251
1252 return false;
1253}
1254
698a8954
YL		 1255void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1256{
9d8d5a36 1257 int i;
698a8954
YL		 1258
1259 for (i = 0; i < MAX_SKB_FRAGS; i++)
1260 size[i] = skb_frag_size(&shinfo->frags[i]);
1261}
1262
3d5f3741 1263static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
2a597eff 1264 struct net_device *netdev,
d1a37ded 1265 struct sk_buff *skb)
76ad4f0e 1266{
2a597eff 1267 struct hns3_nic_priv *priv = netdev_priv(netdev);
8ae10cfb 1268 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
42611b70 1269 unsigned int bd_num;
76ad4f0e 1270
8ae10cfb
YL		 1271 bd_num = hns3_tx_bd_num(skb, bd_size);
1272 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
8ae10cfb 1273 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
698a8954
YL		 1274 !hns3_skb_need_linearized(skb, bd_size, bd_num)) {
1275 trace_hns3_over_8bd(skb);
db4970aa 1276 goto out;
698a8954 1277 }
db4970aa 1278
d1a37ded 1279 if (__skb_linearize(skb))
51e8439f 1280 return -ENOMEM;
3d5f3741 1281
d1a37ded
YL		 1282 bd_num = hns3_tx_bd_count(skb->len);
1283 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1284 (!skb_is_gso(skb) &&
698a8954
YL		 1285 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1286 trace_hns3_over_8bd(skb);
42611b70 1287 return -ENOMEM;
698a8954 1288 }
42611b70 1289
3d5f3741
YL		 1290 u64_stats_update_begin(&ring->syncp);
1291 ring->stats.tx_copy++;
1292 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1293 }
1294
db4970aa 1295out:
2a597eff
YL		 1296 if (likely(ring_space(ring) >= bd_num))
1297 return bd_num;
76ad4f0e 1298
2a597eff
YL		 1299 netif_stop_subqueue(netdev, ring->queue_index);
1300 smp_mb(); /* Memory barrier before checking ring_space */
1301
1302 /* Start queue in case hns3_clean_tx_ring has just made room
1303 * available and has not seen the queue stopped state performed
1304 * by netif_stop_subqueue above.
1305 */
1306 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1307 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1308 netif_start_subqueue(netdev, ring->queue_index);
1309 return bd_num;
1310 }
1311
1312 return -EBUSY;
76ad4f0e
S		 1313}
1314
ba3f808f 1315static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1316{
1317 struct device *dev = ring_to_dev(ring);
1318 unsigned int i;
1319
1320 for (i = 0; i < ring->desc_num; i++) {
8ceca59f
YL		 1321 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1322
1323 memset(desc, 0, sizeof(*desc));
1324
76ad4f0e
S		 1325 /* check if this is where we started */
1326 if (ring->next_to_use == next_to_use_orig)
1327 break;
1328
aa9d22dd
YL		 1329 /* rollback one */
1330 ring_ptr_move_bw(ring, next_to_use);
1331
8ceca59f
YL		 1332 if (!ring->desc_cb[ring->next_to_use].dma)
1333 continue;
1334
76ad4f0e 1335 /* unmap the descriptor dma address */
74ef402e
HT		 1336 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
1337 ring->desc_cb[ring->next_to_use].type ==
1338 DESC_TYPE_FRAGLIST_SKB)
76ad4f0e
S		 1339 dma_unmap_single(dev,
1340 ring->desc_cb[ring->next_to_use].dma,
1341 ring->desc_cb[ring->next_to_use].length,
1342 DMA_TO_DEVICE);
bcdb12b7 1343 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1344 dma_unmap_page(dev,
1345 ring->desc_cb[ring->next_to_use].dma,
1346 ring->desc_cb[ring->next_to_use].length,
1347 DMA_TO_DEVICE);
1348
bcdb12b7 1349 ring->desc_cb[ring->next_to_use].length = 0;
aa9d22dd 1350 ring->desc_cb[ring->next_to_use].dma = 0;
8ceca59f 1351 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN;
76ad4f0e
S		 1352 }
1353}
1354
8ae10cfb
YL		 1355static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1356 struct sk_buff *skb, enum hns_desc_type type)
1357{
1358 unsigned int size = skb_headlen(skb);
1359 int i, ret, bd_num = 0;
1360
1361 if (size) {
1362 ret = hns3_fill_desc(ring, skb, size, type);
1363 if (unlikely(ret < 0))
1364 return ret;
1365
1366 bd_num += ret;
1367 }
1368
1369 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1370 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1371
1372 size = skb_frag_size(frag);
1373 if (!size)
1374 continue;
1375
1376 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1377 if (unlikely(ret < 0))
1378 return ret;
1379
1380 bd_num += ret;
1381 }
1382
1383 return bd_num;
1384}
1385
f6061a05
YL		 1386static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
1387 bool doorbell)
1388{
1389 ring->pending_buf += num;
1390
1391 if (!doorbell) {
1392 u64_stats_update_begin(&ring->syncp);
1393 ring->stats.tx_more++;
1394 u64_stats_update_end(&ring->syncp);
1395 return;
1396 }
1397
1398 if (!ring->pending_buf)
1399 return;
1400
48ee56fd
YL		 1401 writel(ring->pending_buf,
1402 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
f6061a05 1403 ring->pending_buf = 0;
20d06ca2 1404 WRITE_ONCE(ring->last_to_use, ring->next_to_use);
f6061a05
YL		 1405}
1406
d43e5aca 1407netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1408{
1409 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f06b903 1410 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
76ad4f0e 1411 struct netdev_queue *dev_queue;
8ae10cfb
YL		 1412 int pre_ntu, next_to_use_head;
1413 struct sk_buff *frag_skb;
1414 int bd_num = 0;
f6061a05 1415 bool doorbell;
76ad4f0e 1416 int ret;
76ad4f0e 1417
36c67349 1418 /* Hardware can only handle short frames above 32 bytes */
f6061a05
YL		 1419 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
1420 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
36c67349 1421 return NETDEV_TX_OK;
f6061a05 1422 }
36c67349 1423
76ad4f0e
S		 1424 /* Prefetch the data used later */
1425 prefetch(skb->data);
1426
d1a37ded 1427 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
8ae10cfb
YL		 1428 if (unlikely(ret <= 0)) {
1429 if (ret == -EBUSY) {
3d5f3741
YL		 1430 u64_stats_update_begin(&ring->syncp);
1431 ring->stats.tx_busy++;
1432 u64_stats_update_end(&ring->syncp);
f6061a05 1433 hns3_tx_doorbell(ring, 0, true);
2a597eff 1434 return NETDEV_TX_BUSY;
8ae10cfb 1435 } else if (ret == -ENOMEM) {
3d5f3741
YL		 1436 u64_stats_update_begin(&ring->syncp);
1437 ring->stats.sw_err_cnt++;
1438 u64_stats_update_end(&ring->syncp);
1439 }
76ad4f0e 1440
8ae10cfb 1441 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
76ad4f0e 1442 goto out_err_tx_ok;
76ad4f0e
S		 1443 }
1444
76ad4f0e
S		 1445 next_to_use_head = ring->next_to_use;
1446
cfdaeba5
YL		 1447 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use]);
1448 if (unlikely(ret < 0))
1449 goto fill_err;
1450
8ae10cfb
YL		 1451 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1452 if (unlikely(ret < 0))
aa9d22dd 1453 goto fill_err;
76ad4f0e 1454
8ae10cfb 1455 bd_num += ret;
5188f218 1456
8ae10cfb 1457 skb_walk_frags(skb, frag_skb) {
74ef402e
HT		 1458 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1459 DESC_TYPE_FRAGLIST_SKB);
8ae10cfb 1460 if (unlikely(ret < 0))
aa9d22dd 1461 goto fill_err;
8ae10cfb
YL		 1462
1463 bd_num += ret;
76ad4f0e 1464 }
5c6cfd30 1465
8ae10cfb
YL		 1466 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1467 (ring->desc_num - 1);
1468 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1469 cpu_to_le16(BIT(HNS3_TXD_FE_B));
698a8954 1470 trace_hns3_tx_desc(ring, pre_ntu);
76ad4f0e
S		 1471
1472 /* Complete translate all packets */
5f06b903 1473 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
f6061a05
YL		 1474 doorbell = __netdev_tx_sent_queue(dev_queue, skb->len,
1475 netdev_xmit_more());
1476 hns3_tx_doorbell(ring, bd_num, doorbell);
76ad4f0e
S		 1477
1478 return NETDEV_TX_OK;
1479
aa9d22dd 1480fill_err:
ba3f808f 1481 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1482
1483out_err_tx_ok:
1484 dev_kfree_skb_any(skb);
f6061a05 1485 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
76ad4f0e 1486 return NETDEV_TX_OK;
76ad4f0e
S		 1487}
1488
1489static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1490{
9780cb97 1491 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1492 struct sockaddr *mac_addr = p;
1493 int ret;
1494
1495 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1496 return -EADDRNOTAVAIL;
1497
5ec2a51e
JS		 1498 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1499 netdev_info(netdev, "already using mac address %pM\n",
1500 mac_addr->sa_data);
1501 return 0;
1502 }
1503
8e6de441
HT		 1504 /* For VF device, if there is a perm_addr, then the user will not
1505 * be allowed to change the address.
1506 */
1507 if (!hns3_is_phys_func(h->pdev) &&
1508 !is_zero_ether_addr(netdev->perm_addr)) {
1509 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1510 netdev->perm_addr, mac_addr->sa_data);
1511 return -EPERM;
1512 }
1513
59098055 1514 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1515 if (ret) {
1516 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1517 return ret;
1518 }
1519
1520 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1521
1522 return 0;
1523}
1524
26483246
XW		 1525static int hns3_nic_do_ioctl(struct net_device *netdev,
1526 struct ifreq *ifr, int cmd)
1527{
1528 struct hnae3_handle *h = hns3_get_handle(netdev);
1529
1530 if (!netif_running(netdev))
1531 return -EINVAL;
1532
1533 if (!h->ae_algo->ops->do_ioctl)
1534 return -EOPNOTSUPP;
1535
1536 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1537}
1538
76ad4f0e
S		 1539static int hns3_nic_set_features(struct net_device *netdev,
1540 netdev_features_t features)
1541{
181d454b 1542 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1543 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1544 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1545 bool enable;
052ece6d 1546 int ret;
76ad4f0e 1547
5c9f6b39 1548 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 1549 enable = !!(features & NETIF_F_GRO_HW);
1550 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 1551 if (ret)
1552 return ret;
1553 }
1554
bd368416
JS		 1555 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1556 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 1557 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1558 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 1559 if (ret)
1560 return ret;
1561 }
1562
c17852a8 1563 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 1564 enable = !!(features & NETIF_F_NTUPLE);
1565 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 1566 }
1567
76ad4f0e
S		 1568 netdev->features = features;
1569 return 0;
1570}
1571
2a7556bb
YL		 1572static netdev_features_t hns3_features_check(struct sk_buff *skb,
1573 struct net_device *dev,
1574 netdev_features_t features)
1575{
1576#define HNS3_MAX_HDR_LEN 480U
1577#define HNS3_MAX_L4_HDR_LEN 60U
1578
1579 size_t len;
1580
1581 if (skb->ip_summed != CHECKSUM_PARTIAL)
1582 return features;
1583
1584 if (skb->encapsulation)
1585 len = skb_inner_transport_header(skb) - skb->data;
1586 else
1587 len = skb_transport_header(skb) - skb->data;
1588
1589 /* Assume L4 is 60 byte as TCP is the only protocol with a
1590 * a flexible value, and it's max len is 60 bytes.
1591 */
1592 len += HNS3_MAX_L4_HDR_LEN;
1593
1594 /* Hardware only supports checksum on the skb with a max header
1595 * len of 480 bytes.
1596 */
1597 if (len > HNS3_MAX_HDR_LEN)
1598 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1599
1600 return features;
1601}
1602
6c88d9d7
PL		 1603static void hns3_nic_get_stats64(struct net_device *netdev,
1604 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1605{
1606 struct hns3_nic_priv *priv = netdev_priv(netdev);
1607 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1608 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1609 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 1610 u64 rx_length_errors = 0;
1611 u64 rx_crc_errors = 0;
1612 u64 rx_multicast = 0;
76ad4f0e 1613 unsigned int start;
d3ec4ef6
JS		 1614 u64 tx_errors = 0;
1615 u64 rx_errors = 0;
76ad4f0e
S		 1616 unsigned int idx;
1617 u64 tx_bytes = 0;
1618 u64 rx_bytes = 0;
1619 u64 tx_pkts = 0;
1620 u64 rx_pkts = 0;
d2a5dca8
JS		 1621 u64 tx_drop = 0;
1622 u64 rx_drop = 0;
76ad4f0e 1623
b875cc37
JS		 1624 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1625 return;
1626
c5f65480
JS		 1627 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1628
76ad4f0e
S		 1629 for (idx = 0; idx < queue_num; idx++) {
1630 /* fetch the tx stats */
5f06b903 1631 ring = &priv->ring[idx];
76ad4f0e 1632 do {
d36d36ce 1633 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1634 tx_bytes += ring->stats.tx_bytes;
1635 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1636 tx_drop += ring->stats.sw_err_cnt;
b20d7fe5
YL		 1637 tx_drop += ring->stats.tx_vlan_err;
1638 tx_drop += ring->stats.tx_l4_proto_err;
1639 tx_drop += ring->stats.tx_l2l3l4_err;
1640 tx_drop += ring->stats.tx_tso_err;
d3ec4ef6 1641 tx_errors += ring->stats.sw_err_cnt;
b20d7fe5
YL		 1642 tx_errors += ring->stats.tx_vlan_err;
1643 tx_errors += ring->stats.tx_l4_proto_err;
1644 tx_errors += ring->stats.tx_l2l3l4_err;
1645 tx_errors += ring->stats.tx_tso_err;
76ad4f0e
S		 1646 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1647
1648 /* fetch the rx stats */
5f06b903 1649 ring = &priv->ring[idx + queue_num];
76ad4f0e 1650 do {
d36d36ce 1651 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1652 rx_bytes += ring->stats.rx_bytes;
1653 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1654 rx_drop += ring->stats.l2_err;
d3ec4ef6 1655 rx_errors += ring->stats.l2_err;
8b552079 1656 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 1657 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS		 1658 rx_multicast += ring->stats.rx_multicast;
1659 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 1660 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1661 }
1662
1663 stats->tx_bytes = tx_bytes;
1664 stats->tx_packets = tx_pkts;
1665 stats->rx_bytes = rx_bytes;
1666 stats->rx_packets = rx_pkts;
1667
d3ec4ef6
JS		 1668 stats->rx_errors = rx_errors;
1669 stats->multicast = rx_multicast;
1670 stats->rx_length_errors = rx_length_errors;
1671 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 1672 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1673
d3ec4ef6
JS		 1674 stats->tx_errors = tx_errors;
1675 stats->rx_dropped = rx_drop;
1676 stats->tx_dropped = tx_drop;
76ad4f0e
S		 1677 stats->collisions = netdev->stats.collisions;
1678 stats->rx_over_errors = netdev->stats.rx_over_errors;
1679 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1680 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1681 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1682 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1683 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1684 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1685 stats->tx_window_errors = netdev->stats.tx_window_errors;
1686 stats->rx_compressed = netdev->stats.rx_compressed;
1687 stats->tx_compressed = netdev->stats.tx_compressed;
1688}
1689
30d240df 1690static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1691{
30d240df 1692 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
30d240df 1693 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
75718800 1694 struct hnae3_knic_private_info *kinfo;
30d240df
YL		 1695 u8 tc = mqprio_qopt->qopt.num_tc;
1696 u16 mode = mqprio_qopt->mode;
1697 u8 hw = mqprio_qopt->qopt.hw;
75718800 1698 struct hnae3_handle *h;
76ad4f0e 1699
30d240df
YL		 1700 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1701 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1702 return -EOPNOTSUPP;
1703
76ad4f0e
S		 1704 if (tc > HNAE3_MAX_TC)
1705 return -EINVAL;
1706
76ad4f0e
S		 1707 if (!netdev)
1708 return -EINVAL;
1709
75718800
YL		 1710 h = hns3_get_handle(netdev);
1711 kinfo = &h->kinfo;
1712
1c822948
YL		 1713 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1714
1cce5eb6 1715 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
5eb01ddf 1716 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
76ad4f0e
S		 1717}
1718
2572ac53 1719static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1720 void *type_data)
76ad4f0e 1721{
575ed7d3 1722 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1723 return -EOPNOTSUPP;
76ad4f0e 1724
30d240df 1725 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1726}
1727
1728static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1729 __be16 proto, u16 vid)
1730{
9780cb97 1731 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1732 int ret = -EIO;
1733
1734 if (h->ae_algo->ops->set_vlan_filter)
1735 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1736
1737 return ret;
1738}
1739
1740static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1741 __be16 proto, u16 vid)
1742{
9780cb97 1743 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1744 int ret = -EIO;
1745
1746 if (h->ae_algo->ops->set_vlan_filter)
1747 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1748
7fa6be4f 1749 return ret;
681ec399
YL		 1750}
1751
76ad4f0e
S		 1752static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1753 u8 qos, __be16 vlan_proto)
1754{
9780cb97 1755 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1756 int ret = -EIO;
1757
1c822948 1758 netif_dbg(h, drv, netdev,
39edaf24
GL		 1759 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1760 vf, vlan, qos, ntohs(vlan_proto));
1c822948 1761
76ad4f0e
S		 1762 if (h->ae_algo->ops->set_vf_vlan_filter)
1763 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 1764 qos, vlan_proto);
76ad4f0e
S		 1765
1766 return ret;
1767}
1768
22044f95
JS		 1769static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1770{
1771 struct hnae3_handle *handle = hns3_get_handle(netdev);
1772
1773 if (hns3_nic_resetting(netdev))
1774 return -EBUSY;
1775
1776 if (!handle->ae_algo->ops->set_vf_spoofchk)
1777 return -EOPNOTSUPP;
1778
1779 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1780}
1781
e196ec75
JS		 1782static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1783{
1784 struct hnae3_handle *handle = hns3_get_handle(netdev);
1785
1786 if (!handle->ae_algo->ops->set_vf_trust)
1787 return -EOPNOTSUPP;
1788
1789 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1790}
1791
a8e8b7ff
S		 1792static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1793{
9780cb97 1794 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1795 int ret;
1796
6ff7ed80
HT		 1797 if (hns3_nic_resetting(netdev))
1798 return -EBUSY;
1799
a8e8b7ff
S		 1800 if (!h->ae_algo->ops->set_mtu)
1801 return -EOPNOTSUPP;
1802
1c822948
YL		 1803 netif_dbg(h, drv, netdev,
1804 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1805
a8e8b7ff 1806 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1807 if (ret)
a8e8b7ff
S		 1808 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1809 ret);
93d8daf4
YL		 1810 else
1811 netdev->mtu = new_mtu;
5bad95a1 1812
a8e8b7ff
S		 1813 return ret;
1814}
1815
f8fa222c
L		 1816static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1817{
1818 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1819 struct hnae3_handle *h = hns3_get_handle(ndev);
0bfdf286 1820 struct hns3_enet_ring *tx_ring;
e511c97d 1821 struct napi_struct *napi;
f8fa222c
L		 1822 int timeout_queue = 0;
1823 int hw_head, hw_tail;
e511c97d
JS		 1824 int fbd_num, fbd_oft;
1825 int ebd_num, ebd_oft;
1826 int bd_num, bd_err;
1827 int ring_en, tc;
f8fa222c
L		 1828 int i;
1829
1830 /* Find the stopped queue the same way the stack does */
fa6c4084 1831 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 1832 struct netdev_queue *q;
1833 unsigned long trans_start;
1834
1835 q = netdev_get_tx_queue(ndev, i);
1836 trans_start = q->trans_start;
1837 if (netif_xmit_stopped(q) &&
1838 time_after(jiffies,
1839 (trans_start + ndev->watchdog_timeo))) {
1840 timeout_queue = i;
647522a5
YL		 1841 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1842 q->state,
1843 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L		 1844 break;
1845 }
1846 }
1847
1848 if (i == ndev->num_tx_queues) {
1849 netdev_info(ndev,
1850 "no netdev TX timeout queue found, timeout count: %llu\n",
1851 priv->tx_timeout_count);
1852 return false;
1853 }
1854
beab694a
JS		 1855 priv->tx_timeout_count++;
1856
5f06b903 1857 tx_ring = &priv->ring[timeout_queue];
e511c97d
JS		 1858 napi = &tx_ring->tqp_vector->napi;
1859
1860 netdev_info(ndev,
1861 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1862 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1863 tx_ring->next_to_clean, napi->state);
1864
1865 netdev_info(ndev,
20d06ca2 1866 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
e511c97d 1867 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
20d06ca2 1868 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
e511c97d
JS		 1869
1870 netdev_info(ndev,
f6061a05
YL		 1871 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
1872 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
e511c97d
JS		 1873 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1874
1875 /* When mac received many pause frames continuous, it's unable to send
1876 * packets, which may cause tx timeout
1877 */
615466ce
YM		 1878 if (h->ae_algo->ops->get_mac_stats) {
1879 struct hns3_mac_stats mac_stats;
e511c97d 1880
615466ce 1881 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
e511c97d 1882 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
615466ce 1883 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
e511c97d 1884 }
f8fa222c
L		 1885
1886 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1887 HNS3_RING_TX_RING_HEAD_REG);
1888 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1889 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 1890 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1891 HNS3_RING_TX_RING_FBDNUM_REG);
1892 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1893 HNS3_RING_TX_RING_OFFSET_REG);
1894 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1895 HNS3_RING_TX_RING_EBDNUM_REG);
1896 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1897 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1898 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1899 HNS3_RING_TX_RING_BD_NUM_REG);
1900 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1901 HNS3_RING_TX_RING_BD_ERR_REG);
1902 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1903 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1904
f8fa222c 1905 netdev_info(ndev,
e511c97d
JS		 1906 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1907 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 1908 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 1909 netdev_info(ndev,
1910 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1911 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 1912
1913 return true;
1914}
1915
0290bd29 1916static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
f8fa222c
L		 1917{
1918 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1919 struct hnae3_handle *h = priv->ae_handle;
1920
1921 if (!hns3_get_tx_timeo_queue_info(ndev))
1922 return;
1923
0742ed7c
HT		 1924 /* request the reset, and let the hclge to determine
1925 * which reset level should be done
1926 */
f8fa222c 1927 if (h->ae_algo->ops->reset_event)
6ae4e733 1928 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1929}
1930
d93ed94f
JS		 1931#ifdef CONFIG_RFS_ACCEL
1932static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1933 u16 rxq_index, u32 flow_id)
1934{
1935 struct hnae3_handle *h = hns3_get_handle(dev);
1936 struct flow_keys fkeys;
1937
1938 if (!h->ae_algo->ops->add_arfs_entry)
1939 return -EOPNOTSUPP;
1940
1941 if (skb->encapsulation)
1942 return -EPROTONOSUPPORT;
1943
1944 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1945 return -EPROTONOSUPPORT;
1946
1947 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1948 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1949 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1950 fkeys.basic.ip_proto != IPPROTO_UDP))
1951 return -EPROTONOSUPPORT;
1952
1953 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1954}
1955#endif
1956
6430f744
YM		 1957static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1958 struct ifla_vf_info *ivf)
1959{
1960 struct hnae3_handle *h = hns3_get_handle(ndev);
1961
1962 if (!h->ae_algo->ops->get_vf_config)
1963 return -EOPNOTSUPP;
1964
1965 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1966}
1967
1968static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1969 int link_state)
1970{
1971 struct hnae3_handle *h = hns3_get_handle(ndev);
1972
1973 if (!h->ae_algo->ops->set_vf_link_state)
1974 return -EOPNOTSUPP;
1975
1976 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1977}
1978
ee9e4424
YL		 1979static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1980 int min_tx_rate, int max_tx_rate)
1981{
1982 struct hnae3_handle *h = hns3_get_handle(ndev);
1983
1984 if (!h->ae_algo->ops->set_vf_rate)
1985 return -EOPNOTSUPP;
1986
1987 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1988 false);
1989}
1990
8e6de441
HT		 1991static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1992{
1993 struct hnae3_handle *h = hns3_get_handle(netdev);
1994
1995 if (!h->ae_algo->ops->set_vf_mac)
1996 return -EOPNOTSUPP;
1997
1998 if (is_multicast_ether_addr(mac)) {
1999 netdev_err(netdev,
2000 "Invalid MAC:%pM specified. Could not set MAC\n",
2001 mac);
2002 return -EINVAL;
2003 }
2004
2005 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2006}
2007
76ad4f0e
S		 2008static const struct net_device_ops hns3_nic_netdev_ops = {
2009 .ndo_open = hns3_nic_net_open,
2010 .ndo_stop = hns3_nic_net_stop,
2011 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 2012 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 2013 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 2014 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 2015 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e 2016 .ndo_set_features = hns3_nic_set_features,
2a7556bb 2017 .ndo_features_check = hns3_features_check,
76ad4f0e
S		 2018 .ndo_get_stats64 = hns3_nic_get_stats64,
2019 .ndo_setup_tc = hns3_nic_setup_tc,
2020 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 2021 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2022 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2023 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
22044f95 2024 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
e196ec75 2025 .ndo_set_vf_trust = hns3_set_vf_trust,
d93ed94f
JS		 2026#ifdef CONFIG_RFS_ACCEL
2027 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2028#endif
6430f744
YM		 2029 .ndo_get_vf_config = hns3_nic_get_vf_config,
2030 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
ee9e4424 2031 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
8e6de441 2032 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
76ad4f0e
S		 2033};
2034
97afd47b 2035bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 2036{
2037 u32 dev_id = pdev->device;
2038
2039 switch (dev_id) {
2040 case HNAE3_DEV_ID_GE:
2041 case HNAE3_DEV_ID_25GE:
2042 case HNAE3_DEV_ID_25GE_RDMA:
2043 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2044 case HNAE3_DEV_ID_50GE_RDMA:
2045 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2046 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2047 return true;
2048 case HNAE3_DEV_ID_100G_VF:
2049 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2050 return false;
2051 default:
adcf738b 2052 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2312e050
FL		 2053 dev_id);
2054 }
2055
2056 return false;
2057}
2058
2312e050
FL		 2059static void hns3_disable_sriov(struct pci_dev *pdev)
2060{
2061 /* If our VFs are assigned we cannot shut down SR-IOV
2062 * without causing issues, so just leave the hardware
2063 * available but disabled
2064 */
2065 if (pci_vfs_assigned(pdev)) {
2066 dev_warn(&pdev->dev,
2067 "disabling driver while VFs are assigned\n");
2068 return;
2069 }
2070
2071 pci_disable_sriov(pdev);
2072}
2073
d695964d
JS		 2074static void hns3_get_dev_capability(struct pci_dev *pdev,
2075 struct hnae3_ae_dev *ae_dev)
2076{
b26a6fea 2077 if (pdev->revision >= 0x21) {
d695964d 2078 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL		 2079 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2080 }
d695964d
JS		 2081}
2082
76ad4f0e
S		 2083/* hns3_probe - Device initialization routine
2084 * @pdev: PCI device information struct
2085 * @ent: entry in hns3_pci_tbl
2086 *
2087 * hns3_probe initializes a PF identified by a pci_dev structure.
2088 * The OS initialization, configuring of the PF private structure,
2089 * and a hardware reset occur.
2090 *
2091 * Returns 0 on success, negative on failure
2092 */
2093static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2094{
2095 struct hnae3_ae_dev *ae_dev;
2096 int ret;
2097
9b2f3477 2098 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
60df7e91
HT		 2099 if (!ae_dev)
2100 return -ENOMEM;
76ad4f0e
S		 2101
2102 ae_dev->pdev = pdev;
e92a0843 2103 ae_dev->flag = ent->driver_data;
d695964d 2104 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 2105 pci_set_drvdata(pdev, ae_dev);
2106
74354140 2107 ret = hnae3_register_ae_dev(ae_dev);
674a1357 2108 if (ret)
74354140 2109 pci_set_drvdata(pdev, NULL);
2312e050 2110
74354140 2111 return ret;
76ad4f0e
S		 2112}
2113
2114/* hns3_remove - Device removal routine
2115 * @pdev: PCI device information struct
2116 */
2117static void hns3_remove(struct pci_dev *pdev)
2118{
2119 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2120
2312e050
FL		 2121 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2122 hns3_disable_sriov(pdev);
2123
76ad4f0e 2124 hnae3_unregister_ae_dev(ae_dev);
ac864c23 2125 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 2126}
2127
fa8d82e8
PL		 2128/**
2129 * hns3_pci_sriov_configure
2130 * @pdev: pointer to a pci_dev structure
2131 * @num_vfs: number of VFs to allocate
2132 *
2133 * Enable or change the number of VFs. Called when the user updates the number
2134 * of VFs in sysfs.
2135 **/
743e1a84 2136static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 2137{
2138 int ret;
2139
2140 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2141 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2142 return -EINVAL;
2143 }
2144
2145 if (num_vfs) {
2146 ret = pci_enable_sriov(pdev, num_vfs);
2147 if (ret)
2148 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 2149 else
2150 return num_vfs;
fa8d82e8
PL		 2151 } else if (!pci_vfs_assigned(pdev)) {
2152 pci_disable_sriov(pdev);
2153 } else {
2154 dev_warn(&pdev->dev,
2155 "Unable to free VFs because some are assigned to VMs.\n");
2156 }
2157
2158 return 0;
2159}
2160
ce2c1d2e
YL		 2161static void hns3_shutdown(struct pci_dev *pdev)
2162{
2163 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2164
2165 hnae3_unregister_ae_dev(ae_dev);
ce2c1d2e
YL		 2166 pci_set_drvdata(pdev, NULL);
2167
2168 if (system_state == SYSTEM_POWER_OFF)
2169 pci_set_power_state(pdev, PCI_D3hot);
2170}
2171
5a9f0eac
SJ		 2172static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2173 pci_channel_state_t state)
2174{
2175 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2176 pci_ers_result_t ret;
2177
2178 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2179
2180 if (state == pci_channel_io_perm_failure)
2181 return PCI_ERS_RESULT_DISCONNECT;
2182
661262bc 2183 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 2184 dev_err(&pdev->dev,
661262bc 2185 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ		 2186 return PCI_ERS_RESULT_NONE;
2187 }
2188
381c356e
SJ		 2189 if (ae_dev->ops->handle_hw_ras_error)
2190 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 2191 else
2192 return PCI_ERS_RESULT_NONE;
2193
2194 return ret;
2195}
2196
6ae4e733
SJ		 2197static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2198{
2199 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 2200 const struct hnae3_ae_ops *ops;
123297b7 2201 enum hnae3_reset_type reset_type;
6ae4e733
SJ		 2202 struct device *dev = &pdev->dev;
2203
661262bc
WL		 2204 if (!ae_dev || !ae_dev->ops)
2205 return PCI_ERS_RESULT_NONE;
2206
ad9bf545 2207 ops = ae_dev->ops;
6ae4e733 2208 /* request the reset */
fa17c708
GH		 2209 if (ops->reset_event && ops->get_reset_level &&
2210 ops->set_default_reset_request) {
9d5e67d1 2211 if (ae_dev->hw_err_reset_req) {
123297b7
SJ		 2212 reset_type = ops->get_reset_level(ae_dev,
2213 &ae_dev->hw_err_reset_req);
2214 ops->set_default_reset_request(ae_dev, reset_type);
2215 dev_info(dev, "requesting reset due to PCI error\n");
2216 ops->reset_event(pdev, NULL);
2217 }
69b51bbb 2218
6ae4e733
SJ		 2219 return PCI_ERS_RESULT_RECOVERED;
2220 }
2221
2222 return PCI_ERS_RESULT_DISCONNECT;
2223}
2224
6b9a97ee
HT		 2225static void hns3_reset_prepare(struct pci_dev *pdev)
2226{
2227 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2228
8de91e92 2229 dev_info(&pdev->dev, "FLR prepare\n");
6b9a97ee
HT		 2230 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2231 ae_dev->ops->flr_prepare(ae_dev);
2232}
2233
2234static void hns3_reset_done(struct pci_dev *pdev)
2235{
2236 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2237
8de91e92 2238 dev_info(&pdev->dev, "FLR done\n");
6b9a97ee
HT		 2239 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2240 ae_dev->ops->flr_done(ae_dev);
2241}
2242
5a9f0eac
SJ		 2243static const struct pci_error_handlers hns3_err_handler = {
2244 .error_detected = hns3_error_detected,
6ae4e733 2245 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 2246 .reset_prepare = hns3_reset_prepare,
2247 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 2248};
2249
76ad4f0e
S		 2250static struct pci_driver hns3_driver = {
2251 .name = hns3_driver_name,
2252 .id_table = hns3_pci_tbl,
2253 .probe = hns3_probe,
2254 .remove = hns3_remove,
ce2c1d2e 2255 .shutdown = hns3_shutdown,
fa8d82e8 2256 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 2257 .err_handler = &hns3_err_handler,
76ad4f0e
S		 2258};
2259
2260/* set default feature to hns3 */
2261static void hns3_set_default_feature(struct net_device *netdev)
2262{
3e85af6a
PL		 2263 struct hnae3_handle *h = hns3_get_handle(netdev);
2264 struct pci_dev *pdev = h->pdev;
2265
76ad4f0e
S		 2266 netdev->priv_flags |= IFF_UNICAST_FLT;
2267
2268 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2269 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2270 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2271 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2272 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2273 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
76ad4f0e
S		 2274
2275 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2276
2277 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2278 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2279 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2280 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2281 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2282 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2283 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2284 NETIF_F_FRAGLIST;
76ad4f0e
S		 2285
2286 netdev->vlan_features |=
2287 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2288 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2289 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2290 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2291 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2292 NETIF_F_FRAGLIST;
76ad4f0e
S		 2293
2294 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 2295 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2296 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2297 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2298 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2299 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2300 NETIF_F_FRAGLIST;
3e85af6a 2301
c17852a8 2302 if (pdev->revision >= 0x21) {
77af09c6 2303 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2304 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 2305
2306 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2307 netdev->hw_features |= NETIF_F_NTUPLE;
2308 netdev->features |= NETIF_F_NTUPLE;
2309 }
2310 }
76ad4f0e
S		 2311}
2312
2313static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2314 struct hns3_desc_cb *cb)
2315{
dbba6da0 2316 unsigned int order = hns3_page_order(ring);
76ad4f0e
S		 2317 struct page *p;
2318
2319 p = dev_alloc_pages(order);
2320 if (!p)
2321 return -ENOMEM;
2322
2323 cb->priv = p;
2324 cb->page_offset = 0;
2325 cb->reuse_flag = 0;
2326 cb->buf = page_address(p);
dbba6da0 2327 cb->length = hns3_page_size(ring);
76ad4f0e 2328 cb->type = DESC_TYPE_PAGE;
aeda9bf8
YL		 2329 page_ref_add(p, USHRT_MAX - 1);
2330 cb->pagecnt_bias = USHRT_MAX;
76ad4f0e 2331
76ad4f0e
S		 2332 return 0;
2333}
2334
2335static void hns3_free_buffer(struct hns3_enet_ring *ring,
619ae331 2336 struct hns3_desc_cb *cb, int budget)
76ad4f0e
S		 2337{
2338 if (cb->type == DESC_TYPE_SKB)
619ae331 2339 napi_consume_skb(cb->priv, budget);
aeda9bf8
YL		 2340 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias)
2341 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
76ad4f0e
S		 2342 memset(cb, 0, sizeof(*cb));
2343}
2344
2345static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2346{
2347 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2348 cb->length, ring_to_dma_dir(ring));
2349
2211f4e1 2350 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 2351 return -EIO;
2352
2353 return 0;
2354}
2355
2356static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2357 struct hns3_desc_cb *cb)
2358{
74ef402e 2359 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
76ad4f0e
S		 2360 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2361 ring_to_dma_dir(ring));
bcdb12b7 2362 else if (cb->length)
76ad4f0e
S		 2363 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2364 ring_to_dma_dir(ring));
2365}
2366
2367static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2368{
2369 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2370 ring->desc[i].addr = 0;
2371}
2372
619ae331
YL		 2373static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
2374 int budget)
76ad4f0e
S		 2375{
2376 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2377
2378 if (!ring->desc_cb[i].dma)
2379 return;
2380
2381 hns3_buffer_detach(ring, i);
619ae331 2382 hns3_free_buffer(ring, cb, budget);
76ad4f0e
S		 2383}
2384
2385static void hns3_free_buffers(struct hns3_enet_ring *ring)
2386{
2387 int i;
2388
2389 for (i = 0; i < ring->desc_num; i++)
619ae331 2390 hns3_free_buffer_detach(ring, i, 0);
76ad4f0e
S		 2391}
2392
2393/* free desc along with its attached buffer */
2394static void hns3_free_desc(struct hns3_enet_ring *ring)
2395{
024cc792
HT		 2396 int size = ring->desc_num * sizeof(ring->desc[0]);
2397
76ad4f0e
S		 2398 hns3_free_buffers(ring);
2399
024cc792
HT		 2400 if (ring->desc) {
2401 dma_free_coherent(ring_to_dev(ring), size,
2402 ring->desc, ring->desc_dma_addr);
2403 ring->desc = NULL;
2404 }
76ad4f0e
S		 2405}
2406
2407static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2408{
2409 int size = ring->desc_num * sizeof(ring->desc[0]);
2410
750afb08
LC		 2411 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2412 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 2413 if (!ring->desc)
2414 return -ENOMEM;
2415
76ad4f0e
S		 2416 return 0;
2417}
2418
4d2cad32 2419static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
76ad4f0e
S		 2420 struct hns3_desc_cb *cb)
2421{
2422 int ret;
2423
2424 ret = hns3_alloc_buffer(ring, cb);
2425 if (ret)
2426 goto out;
2427
2428 ret = hns3_map_buffer(ring, cb);
2429 if (ret)
2430 goto out_with_buf;
2431
2432 return 0;
2433
2434out_with_buf:
619ae331 2435 hns3_free_buffer(ring, cb, 0);
76ad4f0e
S		 2436out:
2437 return ret;
2438}
2439
4d2cad32 2440static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
76ad4f0e 2441{
4d2cad32 2442 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2443
2444 if (ret)
2445 return ret;
2446
2447 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2448
2449 return 0;
2450}
2451
2452/* Allocate memory for raw pkg, and map with dma */
2453static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2454{
2455 int i, j, ret;
2456
2457 for (i = 0; i < ring->desc_num; i++) {
4d2cad32 2458 ret = hns3_alloc_and_attach_buffer(ring, i);
76ad4f0e
S		 2459 if (ret)
2460 goto out_buffer_fail;
2461 }
2462
2463 return 0;
2464
2465out_buffer_fail:
2466 for (j = i - 1; j >= 0; j--)
619ae331 2467 hns3_free_buffer_detach(ring, j, 0);
76ad4f0e
S		 2468 return ret;
2469}
2470
9b2f3477 2471/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S		 2472static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2473 struct hns3_desc_cb *res_cb)
2474{
b9077428 2475 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2476 ring->desc_cb[i] = *res_cb;
2477 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2478 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2479}
2480
2481static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2482{
2483 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL		 2484 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2485 ring->desc_cb[i].page_offset);
7d0b130c 2486 ring->desc[i].rx.bd_base_info = 0;
c2a2e127
BS		 2487
2488 dma_sync_single_for_device(ring_to_dev(ring),
2489 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
2490 hns3_buf_size(ring),
2491 DMA_FROM_DEVICE);
76ad4f0e
S		 2492}
2493
20d06ca2 2494static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
619ae331 2495 int *bytes, int *pkts, int budget)
76ad4f0e 2496{
20d06ca2
YL		 2497 /* pair with ring->last_to_use update in hns3_tx_doorbell(),
2498 * smp_store_release() is not used in hns3_tx_doorbell() because
2499 * the doorbell operation already have the needed barrier operation.
2500 */
2501 int ltu = smp_load_acquire(&ring->last_to_use);
26cda2f1
YL		 2502 int ntc = ring->next_to_clean;
2503 struct hns3_desc_cb *desc_cb;
20d06ca2
YL		 2504 bool reclaimed = false;
2505 struct hns3_desc *desc;
2506
2507 while (ltu != ntc) {
2508 desc = &ring->desc[ntc];
2509
2510 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
2511 BIT(HNS3_TXD_VLD_B))
2512 break;
76ad4f0e 2513
ce74370c
YL		 2514 desc_cb = &ring->desc_cb[ntc];
2515 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2516 (*bytes) += desc_cb->length;
2517 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
619ae331 2518 hns3_free_buffer_detach(ring, ntc, budget);
76ad4f0e 2519
ce74370c
YL		 2520 if (++ntc == ring->desc_num)
2521 ntc = 0;
2522
2523 /* Issue prefetch for next Tx descriptor */
2524 prefetch(&ring->desc_cb[ntc]);
20d06ca2 2525 reclaimed = true;
ce74370c 2526 }
26cda2f1 2527
20d06ca2
YL		 2528 if (unlikely(!reclaimed))
2529 return false;
2530
26cda2f1
YL		 2531 /* This smp_store_release() pairs with smp_load_acquire() in
2532 * ring_space called by hns3_nic_net_xmit.
2533 */
2534 smp_store_release(&ring->next_to_clean, ntc);
20d06ca2 2535 return true;
76ad4f0e
S		 2536}
2537
619ae331 2538void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
76ad4f0e 2539{
c8711956 2540 struct net_device *netdev = ring_to_netdev(ring);
7a810110 2541 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2542 struct netdev_queue *dev_queue;
2543 int bytes, pkts;
76ad4f0e
S		 2544
2545 bytes = 0;
2546 pkts = 0;
20d06ca2 2547
619ae331 2548 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
20d06ca2 2549 return;
76ad4f0e
S		 2550
2551 ring->tqp_vector->tx_group.total_bytes += bytes;
2552 ring->tqp_vector->tx_group.total_packets += pkts;
2553
2554 u64_stats_update_begin(&ring->syncp);
2555 ring->stats.tx_bytes += bytes;
2556 ring->stats.tx_pkts += pkts;
2557 u64_stats_update_end(&ring->syncp);
2558
2559 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2560 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2561
2a597eff 2562 if (unlikely(netif_carrier_ok(netdev) &&
8ae10cfb 2563 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
76ad4f0e
S		 2564 /* Make sure that anybody stopping the queue after this
2565 * sees the new next_to_clean.
2566 */
2567 smp_mb();
7a810110
JS		 2568 if (netif_tx_queue_stopped(dev_queue) &&
2569 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2570 netif_tx_wake_queue(dev_queue);
2571 ring->stats.restart_queue++;
2572 }
2573 }
76ad4f0e
S		 2574}
2575
2576static int hns3_desc_unused(struct hns3_enet_ring *ring)
2577{
2578 int ntc = ring->next_to_clean;
2579 int ntu = ring->next_to_use;
2580
2581 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2582}
2583
9b2f3477
WL		 2584static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2585 int cleand_count)
76ad4f0e
S		 2586{
2587 struct hns3_desc_cb *desc_cb;
2588 struct hns3_desc_cb res_cbs;
2589 int i, ret;
2590
2591 for (i = 0; i < cleand_count; i++) {
2592 desc_cb = &ring->desc_cb[ring->next_to_use];
2593 if (desc_cb->reuse_flag) {
2594 u64_stats_update_begin(&ring->syncp);
2595 ring->stats.reuse_pg_cnt++;
2596 u64_stats_update_end(&ring->syncp);
2597
2598 hns3_reuse_buffer(ring, ring->next_to_use);
2599 } else {
4d2cad32 2600 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
76ad4f0e
S		 2601 if (ret) {
2602 u64_stats_update_begin(&ring->syncp);
2603 ring->stats.sw_err_cnt++;
2604 u64_stats_update_end(&ring->syncp);
2605
c8711956 2606 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5
YL		 2607 "alloc rx buffer failed: %d\n",
2608 ret);
76ad4f0e
S		 2609 break;
2610 }
2611 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 2612
2613 u64_stats_update_begin(&ring->syncp);
2614 ring->stats.non_reuse_pg++;
2615 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 2616 }
2617
2618 ring_ptr_move_fw(ring, next_to_use);
2619 }
2620
48ee56fd 2621 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
76ad4f0e
S		 2622}
2623
08bb3857
YL		 2624static bool hns3_page_is_reusable(struct page *page)
2625{
2626 return page_to_nid(page) == numa_mem_id() &&
2627 !page_is_pfmemalloc(page);
2628}
2629
aeda9bf8
YL		 2630static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
2631{
2632 return (page_count(cb->priv) - cb->pagecnt_bias) == 1;
2633}
2634
76ad4f0e
S		 2635static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2636 struct hns3_enet_ring *ring, int pull_len,
2637 struct hns3_desc_cb *desc_cb)
2638{
389ca146
YL		 2639 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2640 int size = le16_to_cpu(desc->rx.size);
dbba6da0 2641 u32 truesize = hns3_buf_size(ring);
76ad4f0e 2642
aeda9bf8 2643 desc_cb->pagecnt_bias--;
76ad4f0e 2644 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2645 size - pull_len, truesize);
76ad4f0e 2646
389ca146
YL		 2647 /* Avoid re-using remote pages, or the stack is still using the page
2648 * when page_offset rollback to zero, flag default unreuse
2649 */
08bb3857 2650 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
aeda9bf8
YL		 2651 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) {
2652 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
76ad4f0e 2653 return;
aeda9bf8 2654 }
76ad4f0e
S		 2655
2656 /* Move offset up to the next cache line */
2657 desc_cb->page_offset += truesize;
2658
dbba6da0 2659 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
76ad4f0e 2660 desc_cb->reuse_flag = 1;
aeda9bf8 2661 } else if (hns3_can_reuse_page(desc_cb)) {
389ca146
YL		 2662 desc_cb->reuse_flag = 1;
2663 desc_cb->page_offset = 0;
aeda9bf8
YL		 2664 } else if (desc_cb->pagecnt_bias) {
2665 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
2666 return;
2667 }
2668
2669 if (unlikely(!desc_cb->pagecnt_bias)) {
2670 page_ref_add(desc_cb->priv, USHRT_MAX);
2671 desc_cb->pagecnt_bias = USHRT_MAX;
76ad4f0e
S		 2672 }
2673}
2674
e2ee1c5a 2675static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL		 2676{
2677 __be16 type = skb->protocol;
2678 struct tcphdr *th;
2679 int depth = 0;
2680
e2ee1c5a 2681 while (eth_type_vlan(type)) {
d474d88f
YL		 2682 struct vlan_hdr *vh;
2683
2684 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2685 return -EFAULT;
2686
2687 vh = (struct vlan_hdr *)(skb->data + depth);
2688 type = vh->h_vlan_encapsulated_proto;
2689 depth += VLAN_HLEN;
2690 }
2691
e2ee1c5a
YL		 2692 skb_set_network_header(skb, depth);
2693
d474d88f 2694 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL		 2695 const struct iphdr *iph = ip_hdr(skb);
2696
d474d88f 2697 depth += sizeof(struct iphdr);
e2ee1c5a
YL		 2698 skb_set_transport_header(skb, depth);
2699 th = tcp_hdr(skb);
2700 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2701 iph->daddr, 0);
d474d88f 2702 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL		 2703 const struct ipv6hdr *iph = ipv6_hdr(skb);
2704
d474d88f 2705 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL		 2706 skb_set_transport_header(skb, depth);
2707 th = tcp_hdr(skb);
2708 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2709 &iph->daddr, 0);
d474d88f 2710 } else {
b20d7fe5
YL		 2711 hns3_rl_err(skb->dev,
2712 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2713 be16_to_cpu(type), depth);
d474d88f
YL		 2714 return -EFAULT;
2715 }
2716
d474d88f
YL		 2717 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2718 if (th->cwr)
2719 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2720
e2ee1c5a
YL		 2721 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2722 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 2723
e2ee1c5a
YL		 2724 skb->csum_start = (unsigned char *)th - skb->head;
2725 skb->csum_offset = offsetof(struct tcphdr, check);
2726 skb->ip_summed = CHECKSUM_PARTIAL;
698a8954
YL		 2727
2728 trace_hns3_gro(skb);
2729
d474d88f
YL		 2730 return 0;
2731}
2732
76ad4f0e 2733static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
39c38824 2734 u32 l234info, u32 bd_base_info, u32 ol_info)
76ad4f0e 2735{
c8711956 2736 struct net_device *netdev = ring_to_netdev(ring);
76ad4f0e 2737 int l3_type, l4_type;
76ad4f0e 2738 int ol4_type;
76ad4f0e
S		 2739
2740 skb->ip_summed = CHECKSUM_NONE;
2741
2742 skb_checksum_none_assert(skb);
2743
2744 if (!(netdev->features & NETIF_F_RXCSUM))
2745 return;
2746
2747 /* check if hardware has done checksum */
e8149933 2748 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S		 2749 return;
2750
f4772dee
DC		 2751 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2752 BIT(HNS3_RXD_OL3E_B) |
e8149933 2753 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S		 2754 u64_stats_update_begin(&ring->syncp);
2755 ring->stats.l3l4_csum_err++;
2756 u64_stats_update_end(&ring->syncp);
2757
2758 return;
2759 }
2760
39c38824 2761 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 2762 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2763 switch (ol4_type) {
2764 case HNS3_OL4_TYPE_MAC_IN_UDP:
2765 case HNS3_OL4_TYPE_NVGRE:
2766 skb->csum_level = 1;
df561f66 2767 fallthrough;
76ad4f0e 2768 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 2769 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2770 HNS3_RXD_L3ID_S);
2771 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2772 HNS3_RXD_L4ID_S);
2773
76ad4f0e 2774 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2775 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2776 l3_type == HNS3_L3_TYPE_IPV6) &&
2777 (l4_type == HNS3_L4_TYPE_UDP ||
2778 l4_type == HNS3_L4_TYPE_TCP ||
2779 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2780 skb->ip_summed = CHECKSUM_UNNECESSARY;
2781 break;
fa7a4bd5
JS		 2782 default:
2783 break;
76ad4f0e
S		 2784 }
2785}
2786
d43e5aca
YL		 2787static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2788{
81ae0e04
PL		 2789 if (skb_has_frag_list(skb))
2790 napi_gro_flush(&ring->tqp_vector->napi, false);
2791
d43e5aca
YL		 2792 napi_gro_receive(&ring->tqp_vector->napi, skb);
2793}
2794
701a6d6a
JS		 2795static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2796 struct hns3_desc *desc, u32 l234info,
2797 u16 *vlan_tag)
5b5455a9 2798{
44e626f7 2799 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 2800 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL		 2801
2802 if (pdev->revision == 0x20) {
701a6d6a
JS		 2803 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2804 if (!(*vlan_tag & VLAN_VID_MASK))
2805 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2806
701a6d6a 2807 return (*vlan_tag != 0);
5b5455a9
PL		 2808 }
2809
2810#define HNS3_STRP_OUTER_VLAN 0x1
2811#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 2812#define HNS3_STRP_BOTH 0x3
5b5455a9 2813
44e626f7
JS		 2814 /* Hardware always insert VLAN tag into RX descriptor when
2815 * remove the tag from packet, driver needs to determine
2816 * reporting which tag to stack.
2817 */
e4e87715
PL		 2818 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2819 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2820 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 2821 if (handle->port_base_vlan_state !=
2822 HNAE3_PORT_BASE_VLAN_DISABLE)
2823 return false;
2824
701a6d6a
JS		 2825 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2826 return true;
5b5455a9 2827 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 2828 if (handle->port_base_vlan_state !=
2829 HNAE3_PORT_BASE_VLAN_DISABLE)
2830 return false;
2831
701a6d6a 2832 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 2833 return true;
2834 case HNS3_STRP_BOTH:
2835 if (handle->port_base_vlan_state ==
2836 HNAE3_PORT_BASE_VLAN_DISABLE)
2837 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2838 else
2839 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2840
701a6d6a 2841 return true;
5b5455a9 2842 default:
701a6d6a 2843 return false;
5b5455a9 2844 }
5b5455a9
PL		 2845}
2846
8c30e194
YL		 2847static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
2848{
2849 ring->desc[ring->next_to_clean].rx.bd_base_info &=
2850 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
2851 ring->next_to_clean += 1;
2852
2853 if (unlikely(ring->next_to_clean == ring->desc_num))
2854 ring->next_to_clean = 0;
2855}
2856
b9a8f883 2857static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL		 2858 unsigned char *va)
2859{
e5597095 2860 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
c8711956 2861 struct net_device *netdev = ring_to_netdev(ring);
e5597095
PL		 2862 struct sk_buff *skb;
2863
2864 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2865 skb = ring->skb;
2866 if (unlikely(!skb)) {
b20d7fe5 2867 hns3_rl_err(netdev, "alloc rx skb fail\n");
e5597095
PL		 2868
2869 u64_stats_update_begin(&ring->syncp);
2870 ring->stats.sw_err_cnt++;
2871 u64_stats_update_end(&ring->syncp);
2872
2873 return -ENOMEM;
2874 }
2875
698a8954 2876 trace_hns3_rx_desc(ring);
e5597095
PL		 2877 prefetchw(skb->data);
2878
2879 ring->pending_buf = 1;
81ae0e04
PL		 2880 ring->frag_num = 0;
2881 ring->tail_skb = NULL;
e5597095
PL		 2882 if (length <= HNS3_RX_HEAD_SIZE) {
2883 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2884
2885 /* We can reuse buffer as-is, just make sure it is local */
08bb3857 2886 if (likely(hns3_page_is_reusable(desc_cb->priv)))
e5597095
PL		 2887 desc_cb->reuse_flag = 1;
2888 else /* This page cannot be reused so discard it */
aeda9bf8
YL		 2889 __page_frag_cache_drain(desc_cb->priv,
2890 desc_cb->pagecnt_bias);
e5597095 2891
8c30e194 2892 hns3_rx_ring_move_fw(ring);
e5597095
PL		 2893 return 0;
2894 }
2895 u64_stats_update_begin(&ring->syncp);
2896 ring->stats.seg_pkt_cnt++;
2897 u64_stats_update_end(&ring->syncp);
2898
c43f1255 2899 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 2900 __skb_put(skb, ring->pull_len);
81ae0e04 2901 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095 2902 desc_cb);
8c30e194 2903 hns3_rx_ring_move_fw(ring);
e5597095 2904
b2598318 2905 return 0;
e5597095
PL		 2906}
2907
b2598318 2908static int hns3_add_frag(struct hns3_enet_ring *ring)
e5597095 2909{
d35bced8
YL		 2910 struct sk_buff *skb = ring->skb;
2911 struct sk_buff *head_skb = skb;
81ae0e04 2912 struct sk_buff *new_skb;
e5597095 2913 struct hns3_desc_cb *desc_cb;
b2598318 2914 struct hns3_desc *desc;
e5597095 2915 u32 bd_base_info;
e5597095 2916
b2598318 2917 do {
e5597095
PL		 2918 desc = &ring->desc[ring->next_to_clean];
2919 desc_cb = &ring->desc_cb[ring->next_to_clean];
2920 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 2921 /* make sure HW write desc complete */
2922 dma_rmb();
e8149933 2923 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 2924 return -ENXIO;
2925
81ae0e04 2926 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
7fda3a93 2927 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
81ae0e04 2928 if (unlikely(!new_skb)) {
c8711956 2929 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5 2930 "alloc rx fraglist skb fail\n");
81ae0e04
PL		 2931 return -ENXIO;
2932 }
2933 ring->frag_num = 0;
2934
2935 if (ring->tail_skb) {
2936 ring->tail_skb->next = new_skb;
2937 ring->tail_skb = new_skb;
2938 } else {
2939 skb_shinfo(skb)->frag_list = new_skb;
2940 ring->tail_skb = new_skb;
2941 }
2942 }
2943
2944 if (ring->tail_skb) {
dbba6da0 2945 head_skb->truesize += hns3_buf_size(ring);
81ae0e04
PL		 2946 head_skb->data_len += le16_to_cpu(desc->rx.size);
2947 head_skb->len += le16_to_cpu(desc->rx.size);
2948 skb = ring->tail_skb;
2949 }
2950
c2a2e127
BS		 2951 dma_sync_single_for_cpu(ring_to_dev(ring),
2952 desc_cb->dma + desc_cb->page_offset,
2953 hns3_buf_size(ring),
2954 DMA_FROM_DEVICE);
2955
81ae0e04 2956 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
698a8954 2957 trace_hns3_rx_desc(ring);
8c30e194 2958 hns3_rx_ring_move_fw(ring);
e5597095 2959 ring->pending_buf++;
b2598318 2960 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
e5597095
PL		 2961
2962 return 0;
2963}
2964
d474d88f
YL		 2965static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2966 struct sk_buff *skb, u32 l234info,
39c38824 2967 u32 bd_base_info, u32 ol_info)
a6d53b97 2968{
a6d53b97
PL		 2969 u32 l3_type;
2970
e2ee1c5a
YL		 2971 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2972 HNS3_RXD_GRO_SIZE_M,
2973 HNS3_RXD_GRO_SIZE_S);
a6d53b97 2974 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 2975 if (!skb_shinfo(skb)->gso_size) {
39c38824 2976 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
d474d88f
YL		 2977 return 0;
2978 }
a6d53b97 2979
e2ee1c5a
YL		 2980 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2981 HNS3_RXD_GRO_COUNT_M,
2982 HNS3_RXD_GRO_COUNT_S);
a6d53b97 2983
9b2f3477 2984 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
a6d53b97
PL		 2985 if (l3_type == HNS3_L3_TYPE_IPV4)
2986 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2987 else if (l3_type == HNS3_L3_TYPE_IPV6)
2988 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2989 else
d474d88f 2990 return -EFAULT;
a6d53b97 2991
e2ee1c5a 2992 return hns3_gro_complete(skb, l234info);
a6d53b97
PL		 2993}
2994
232fc64b 2995static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 2996 struct sk_buff *skb, u32 rss_hash)
232fc64b 2997{
232fc64b
PL		 2998 struct hnae3_handle *handle = ring->tqp->handle;
2999 enum pkt_hash_types rss_type;
3000
ea485867 3001 if (rss_hash)
232fc64b
PL		 3002 rss_type = handle->kinfo.rss_type;
3003 else
3004 rss_type = PKT_HASH_TYPE_NONE;
3005
ea485867 3006 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 3007}
3008
ea485867 3009static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e 3010{
c8711956 3011 struct net_device *netdev = ring_to_netdev(ring);
c376fa1a 3012 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 3013 u32 bd_base_info, l234info, ol_info;
ea485867 3014 struct hns3_desc *desc;
d474d88f 3015 unsigned int len;
ea485867
YL		 3016 int pre_ntc, ret;
3017
3018 /* bdinfo handled below is only valid on the last BD of the
3019 * current packet, and ring->next_to_clean indicates the first
3020 * descriptor of next packet, so need - 1 below.
3021 */
3022 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
3023 (ring->desc_num - 1);
3024 desc = &ring->desc[pre_ntc];
3025 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3026 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 3027 ol_info = le32_to_cpu(desc->rx.ol_info);
d474d88f
YL		 3028
3029 /* Based on hw strategy, the tag offloaded will be stored at
3030 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
3031 * in one layer tag case.
3032 */
3033 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3034 u16 vlan_tag;
3035
3036 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
3037 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3038 vlan_tag);
3039 }
3040
d474d88f
YL		 3041 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3042 BIT(HNS3_RXD_L2E_B))))) {
3043 u64_stats_update_begin(&ring->syncp);
3044 if (l234info & BIT(HNS3_RXD_L2E_B))
3045 ring->stats.l2_err++;
3046 else
3047 ring->stats.err_pkt_len++;
3048 u64_stats_update_end(&ring->syncp);
3049
3050 return -EFAULT;
3051 }
3052
3053 len = skb->len;
3054
3055 /* Do update ip stack process */
3056 skb->protocol = eth_type_trans(skb, netdev);
3057
3058 /* This is needed in order to enable forwarding support */
39c38824
YL		 3059 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3060 bd_base_info, ol_info);
d474d88f
YL		 3061 if (unlikely(ret)) {
3062 u64_stats_update_begin(&ring->syncp);
3063 ring->stats.rx_err_cnt++;
3064 u64_stats_update_end(&ring->syncp);
3065 return ret;
3066 }
3067
3068 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3069 HNS3_RXD_DMAC_S);
3070
3071 u64_stats_update_begin(&ring->syncp);
3072 ring->stats.rx_pkts++;
3073 ring->stats.rx_bytes += len;
3074
3075 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3076 ring->stats.rx_multicast++;
3077
3078 u64_stats_update_end(&ring->syncp);
3079
3080 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 3081
3082 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 3083 return 0;
3084}
3085
d35bced8 3086static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
d474d88f 3087{
e5597095 3088 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 3089 struct hns3_desc_cb *desc_cb;
3090 struct hns3_desc *desc;
b9a8f883 3091 unsigned int length;
76ad4f0e 3092 u32 bd_base_info;
e5597095 3093 int ret;
76ad4f0e
S		 3094
3095 desc = &ring->desc[ring->next_to_clean];
3096 desc_cb = &ring->desc_cb[ring->next_to_clean];
3097
3098 prefetch(desc);
3099
8c30e194
YL		 3100 if (!skb) {
3101 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e 3102
8c30e194
YL		 3103 /* Check valid BD */
3104 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3105 return -ENXIO;
3106
3107 dma_rmb();
3108 length = le16_to_cpu(desc->rx.size);
76ad4f0e 3109
cb0e3e61 3110 ring->va = desc_cb->buf + desc_cb->page_offset;
76ad4f0e 3111
c2a2e127
BS		 3112 dma_sync_single_for_cpu(ring_to_dev(ring),
3113 desc_cb->dma + desc_cb->page_offset,
3114 hns3_buf_size(ring),
3115 DMA_FROM_DEVICE);
c2a2e127 3116
8c30e194
YL		 3117 /* Prefetch first cache line of first page.
3118 * Idea is to cache few bytes of the header of the packet.
3119 * Our L1 Cache line size is 64B so need to prefetch twice to make
3120 * it 128B. But in actual we can have greater size of caches with
3121 * 128B Level 1 cache lines. In such a case, single fetch would
3122 * suffice to cache in the relevant part of the header.
3123 */
3124 net_prefetch(ring->va);
76ad4f0e 3125
e5597095 3126 ret = hns3_alloc_skb(ring, length, ring->va);
d35bced8 3127 skb = ring->skb;
76ad4f0e 3128
e5597095
PL		 3129 if (ret < 0) /* alloc buffer fail */
3130 return ret;
b2598318
YL		 3131 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3132 ret = hns3_add_frag(ring);
e5597095
PL		 3133 if (ret)
3134 return ret;
e5597095 3135 }
76ad4f0e 3136 } else {
b2598318 3137 ret = hns3_add_frag(ring);
e5597095
PL		 3138 if (ret)
3139 return ret;
b2598318 3140 }
76ad4f0e 3141
b2598318
YL		 3142 /* As the head data may be changed when GRO enable, copy
3143 * the head data in after other data rx completed
3144 */
3145 if (skb->len > HNS3_RX_HEAD_SIZE)
e5597095
PL		 3146 memcpy(skb->data, ring->va,
3147 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e 3148
ea485867 3149 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 3150 if (unlikely(ret)) {
76ad4f0e 3151 dev_kfree_skb_any(skb);
d474d88f 3152 return ret;
76ad4f0e
S		 3153 }
3154
d93ed94f 3155 skb_record_rx_queue(skb, ring->tqp->tqp_index);
76ad4f0e
S		 3156 return 0;
3157}
3158
9b2f3477
WL		 3159int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3160 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 3161{
3162#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
63380a1a 3163 int unused_count = hns3_desc_unused(ring);
a4ee7624 3164 int recv_pkts = 0;
8c30e194 3165 int err;
76ad4f0e 3166
63380a1a 3167 unused_count -= ring->pending_buf;
76ad4f0e 3168
8c30e194 3169 while (recv_pkts < budget) {
76ad4f0e 3170 /* Reuse or realloc buffers */
a4ee7624
YL		 3171 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3172 hns3_nic_alloc_rx_buffers(ring, unused_count);
e5597095
PL		 3173 unused_count = hns3_desc_unused(ring) -
3174 ring->pending_buf;
76ad4f0e
S		 3175 }
3176
3177 /* Poll one pkt */
d35bced8
YL		 3178 err = hns3_handle_rx_bd(ring);
3179 /* Do not get FE for the packet or failed to alloc skb */
3180 if (unlikely(!ring->skb || err == -ENXIO)) {
76ad4f0e 3181 goto out;
d35bced8
YL		 3182 } else if (likely(!err)) {
3183 rx_fn(ring, ring->skb);
3184 recv_pkts++;
76ad4f0e
S		 3185 }
3186
a4ee7624 3187 unused_count += ring->pending_buf;
e5597095
PL		 3188 ring->skb = NULL;
3189 ring->pending_buf = 0;
76ad4f0e
S		 3190 }
3191
3192out:
3193 /* Make all data has been write before submit */
a4ee7624
YL		 3194 if (unused_count > 0)
3195 hns3_nic_alloc_rx_buffers(ring, unused_count);
76ad4f0e
S		 3196
3197 return recv_pkts;
3198}
3199
4a43caf5 3200static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
76ad4f0e 3201{
4a43caf5
YL		 3202#define HNS3_RX_LOW_BYTE_RATE 10000
3203#define HNS3_RX_MID_BYTE_RATE 20000
3204#define HNS3_RX_ULTRA_PACKET_RATE 40
3205
76ad4f0e 3206 enum hns3_flow_level_range new_flow_level;
4a43caf5
YL		 3207 struct hns3_enet_tqp_vector *tqp_vector;
3208 int packets_per_msecs, bytes_per_msecs;
a95e1f86 3209 u32 time_passed_ms;
76ad4f0e 3210
4a43caf5 3211 tqp_vector = ring_group->ring->tqp_vector;
a95e1f86
FL		 3212 time_passed_ms =
3213 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
a95e1f86
FL		 3214 if (!time_passed_ms)
3215 return false;
3216
3217 do_div(ring_group->total_packets, time_passed_ms);
3218 packets_per_msecs = ring_group->total_packets;
3219
3220 do_div(ring_group->total_bytes, time_passed_ms);
3221 bytes_per_msecs = ring_group->total_bytes;
3222
4a43caf5 3223 new_flow_level = ring_group->coal.flow_level;
76ad4f0e 3224
4a43caf5
YL		 3225 /* Simple throttlerate management
3226 * 0-10MB/s lower (50000 ints/s)
3227 * 10-20MB/s middle (20000 ints/s)
3228 * 20-1249MB/s high (18000 ints/s)
3229 * > 40000pps ultra (8000 ints/s)
3230 */
76ad4f0e
S		 3231 switch (new_flow_level) {
3232 case HNS3_FLOW_LOW:
a95e1f86 3233 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 3234 new_flow_level = HNS3_FLOW_MID;
3235 break;
3236 case HNS3_FLOW_MID:
a95e1f86 3237 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 3238 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 3239 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 3240 new_flow_level = HNS3_FLOW_LOW;
3241 break;
3242 case HNS3_FLOW_HIGH:
3243 case HNS3_FLOW_ULTRA:
3244 default:
a95e1f86 3245 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 3246 new_flow_level = HNS3_FLOW_MID;
3247 break;
3248 }
3249
a95e1f86
FL		 3250 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3251 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 3252 new_flow_level = HNS3_FLOW_ULTRA;
3253
4a43caf5
YL		 3254 ring_group->total_bytes = 0;
3255 ring_group->total_packets = 0;
3256 ring_group->coal.flow_level = new_flow_level;
3257
3258 return true;
3259}
3260
3261static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3262{
3263 struct hns3_enet_tqp_vector *tqp_vector;
3264 u16 new_int_gl;
3265
3266 if (!ring_group->ring)
3267 return false;
3268
3269 tqp_vector = ring_group->ring->tqp_vector;
3270 if (!tqp_vector->last_jiffies)
3271 return false;
3272
3273 if (ring_group->total_packets == 0) {
3274 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3275 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3276 return true;
3277 }
3278
3279 if (!hns3_get_new_flow_lvl(ring_group))
3280 return false;
3281
3282 new_int_gl = ring_group->coal.int_gl;
3283 switch (ring_group->coal.flow_level) {
76ad4f0e
S		 3284 case HNS3_FLOW_LOW:
3285 new_int_gl = HNS3_INT_GL_50K;
3286 break;
3287 case HNS3_FLOW_MID:
3288 new_int_gl = HNS3_INT_GL_20K;
3289 break;
3290 case HNS3_FLOW_HIGH:
3291 new_int_gl = HNS3_INT_GL_18K;
3292 break;
3293 case HNS3_FLOW_ULTRA:
3294 new_int_gl = HNS3_INT_GL_8K;
3295 break;
3296 default:
3297 break;
3298 }
3299
9bc727a9
YL		 3300 if (new_int_gl != ring_group->coal.int_gl) {
3301 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 3302 return true;
3303 }
3304 return false;
3305}
3306
3307static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3308{
8b1ff1ea
FL		 3309 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3310 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3311 bool rx_update, tx_update;
3312
7445565c
PL		 3313 /* update param every 1000ms */
3314 if (time_before(jiffies,
3315 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3316 return;
cd9d187b 3317
9bc727a9 3318 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 3319 rx_update = hns3_get_new_int_gl(rx_group);
3320 if (rx_update)
3321 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3322 rx_group->coal.int_gl);
8b1ff1ea
FL		 3323 }
3324
9bc727a9 3325 if (tx_group->coal.gl_adapt_enable) {
9e50dc11 3326 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL		 3327 if (tx_update)
3328 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3329 tx_group->coal.int_gl);
76ad4f0e 3330 }
cd9d187b 3331
a95e1f86 3332 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 3333}
3334
3335static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3336{
ff0699e0 3337 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 3338 struct hns3_enet_ring *ring;
3339 int rx_pkt_total = 0;
3340
3341 struct hns3_enet_tqp_vector *tqp_vector =
3342 container_of(napi, struct hns3_enet_tqp_vector, napi);
3343 bool clean_complete = true;
ceca4a5e 3344 int rx_budget = budget;
76ad4f0e 3345
ff0699e0
HT		 3346 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3347 napi_complete(napi);
3348 return 0;
3349 }
3350
76ad4f0e
S		 3351 /* Since the actual Tx work is minimal, we can give the Tx a larger
3352 * budget and be more aggressive about cleaning up the Tx descriptors.
3353 */
799997a3 3354 hns3_for_each_ring(ring, tqp_vector->tx_group)
619ae331 3355 hns3_clean_tx_ring(ring, budget);
76ad4f0e
S		 3356
3357 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 3358 if (tqp_vector->num_tqps > 1)
3359 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 3360
3361 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 3362 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3363 hns3_rx_skb);
76ad4f0e
S		 3364
3365 if (rx_cleaned >= rx_budget)
3366 clean_complete = false;
3367
3368 rx_pkt_total += rx_cleaned;
3369 }
3370
3371 tqp_vector->rx_group.total_packets += rx_pkt_total;
3372
3373 if (!clean_complete)
3374 return budget;
3375
531eba0f
HT		 3376 if (napi_complete(napi) &&
3377 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 3378 hns3_update_new_int_gl(tqp_vector);
3379 hns3_mask_vector_irq(tqp_vector, 1);
3380 }
76ad4f0e
S		 3381
3382 return rx_pkt_total;
3383}
3384
3385static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3386 struct hnae3_ring_chain_node *head)
3387{
3388 struct pci_dev *pdev = tqp_vector->handle->pdev;
3389 struct hnae3_ring_chain_node *cur_chain = head;
3390 struct hnae3_ring_chain_node *chain;
3391 struct hns3_enet_ring *tx_ring;
3392 struct hns3_enet_ring *rx_ring;
3393
3394 tx_ring = tqp_vector->tx_group.ring;
3395 if (tx_ring) {
3396 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3397 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3398 HNAE3_RING_TYPE_TX);
3399 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3400 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 3401
3402 cur_chain->next = NULL;
3403
3404 while (tx_ring->next) {
3405 tx_ring = tx_ring->next;
3406
3407 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3408 GFP_KERNEL);
3409 if (!chain)
73b907a0 3410 goto err_free_chain;
76ad4f0e
S		 3411
3412 cur_chain->next = chain;
3413 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3414 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3415 HNAE3_RING_TYPE_TX);
3416 hnae3_set_field(chain->int_gl_idx,
3417 HNAE3_RING_GL_IDX_M,
3418 HNAE3_RING_GL_IDX_S,
3419 HNAE3_RING_GL_TX);
76ad4f0e
S		 3420
3421 cur_chain = chain;
3422 }
3423 }
3424
3425 rx_ring = tqp_vector->rx_group.ring;
3426 if (!tx_ring && rx_ring) {
3427 cur_chain->next = NULL;
3428 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3429 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3430 HNAE3_RING_TYPE_RX);
3431 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3432 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 3433
3434 rx_ring = rx_ring->next;
3435 }
3436
3437 while (rx_ring) {
3438 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3439 if (!chain)
73b907a0 3440 goto err_free_chain;
76ad4f0e
S		 3441
3442 cur_chain->next = chain;
3443 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3444 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3445 HNAE3_RING_TYPE_RX);
3446 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3447 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3448
76ad4f0e
S		 3449 cur_chain = chain;
3450
3451 rx_ring = rx_ring->next;
3452 }
3453
3454 return 0;
73b907a0
HT		 3455
3456err_free_chain:
3457 cur_chain = head->next;
3458 while (cur_chain) {
3459 chain = cur_chain->next;
cda69d24 3460 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 3461 cur_chain = chain;
3462 }
cda69d24 3463 head->next = NULL;
73b907a0
HT		 3464
3465 return -ENOMEM;
76ad4f0e
S		 3466}
3467
3468static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3469 struct hnae3_ring_chain_node *head)
3470{
3471 struct pci_dev *pdev = tqp_vector->handle->pdev;
3472 struct hnae3_ring_chain_node *chain_tmp, *chain;
3473
3474 chain = head->next;
3475
3476 while (chain) {
3477 chain_tmp = chain->next;
3478 devm_kfree(&pdev->dev, chain);
3479 chain = chain_tmp;
3480 }
3481}
3482
3483static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3484 struct hns3_enet_ring *ring)
3485{
3486 ring->next = group->ring;
3487 group->ring = ring;
3488
3489 group->count++;
3490}
3491
874bff0b
PL		 3492static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3493{
3494 struct pci_dev *pdev = priv->ae_handle->pdev;
3495 struct hns3_enet_tqp_vector *tqp_vector;
3496 int num_vectors = priv->vector_num;
3497 int numa_node;
3498 int vector_i;
3499
3500 numa_node = dev_to_node(&pdev->dev);
3501
3502 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3503 tqp_vector = &priv->tqp_vector[vector_i];
3504 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3505 &tqp_vector->affinity_mask);
3506 }
3507}
3508
76ad4f0e
S		 3509static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3510{
3511 struct hnae3_ring_chain_node vector_ring_chain;
3512 struct hnae3_handle *h = priv->ae_handle;
3513 struct hns3_enet_tqp_vector *tqp_vector;
9d8d5a36 3514 int ret;
ece4bf46 3515 int i;
76ad4f0e 3516
874bff0b
PL		 3517 hns3_nic_set_cpumask(priv);
3518
dd38c726
YL		 3519 for (i = 0; i < priv->vector_num; i++) {
3520 tqp_vector = &priv->tqp_vector[i];
3521 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3522 tqp_vector->num_tqps = 0;
3523 }
76ad4f0e 3524
dd38c726
YL		 3525 for (i = 0; i < h->kinfo.num_tqps; i++) {
3526 u16 vector_i = i % priv->vector_num;
3527 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3528
3529 tqp_vector = &priv->tqp_vector[vector_i];
3530
3531 hns3_add_ring_to_group(&tqp_vector->tx_group,
5f06b903 3532 &priv->ring[i]);
76ad4f0e
S		 3533
3534 hns3_add_ring_to_group(&tqp_vector->rx_group,
5f06b903 3535 &priv->ring[i + tqp_num]);
76ad4f0e 3536
5f06b903
YL		 3537 priv->ring[i].tqp_vector = tqp_vector;
3538 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
dd38c726 3539 tqp_vector->num_tqps++;
76ad4f0e
S		 3540 }
3541
dd38c726 3542 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3543 tqp_vector = &priv->tqp_vector[i];
3544
3545 tqp_vector->rx_group.total_bytes = 0;
3546 tqp_vector->rx_group.total_packets = 0;
3547 tqp_vector->tx_group.total_bytes = 0;
3548 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3549 tqp_vector->handle = h;
3550
3551 ret = hns3_get_vector_ring_chain(tqp_vector,
3552 &vector_ring_chain);
3553 if (ret)
cda69d24 3554 goto map_ring_fail;
76ad4f0e
S		 3555
3556 ret = h->ae_algo->ops->map_ring_to_vector(h,
3557 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3558
3559 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3560
dd38c726 3561 if (ret)
ece4bf46 3562 goto map_ring_fail;
dd38c726 3563
76ad4f0e
S		 3564 netif_napi_add(priv->netdev, &tqp_vector->napi,
3565 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3566 }
3567
dd38c726 3568 return 0;
ece4bf46
HT		 3569
3570map_ring_fail:
3571 while (i--)
3572 netif_napi_del(&priv->tqp_vector[i].napi);
3573
3574 return ret;
dd38c726
YL		 3575}
3576
3577static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3578{
75edb610
JS		 3579#define HNS3_VECTOR_PF_MAX_NUM 64
3580
dd38c726
YL		 3581 struct hnae3_handle *h = priv->ae_handle;
3582 struct hns3_enet_tqp_vector *tqp_vector;
3583 struct hnae3_vector_info *vector;
3584 struct pci_dev *pdev = h->pdev;
3585 u16 tqp_num = h->kinfo.num_tqps;
3586 u16 vector_num;
3587 int ret = 0;
3588 u16 i;
3589
3590 /* RSS size, cpu online and vector_num should be the same */
3591 /* Should consider 2p/4p later */
3592 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS		 3593 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3594
dd38c726
YL		 3595 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3596 GFP_KERNEL);
3597 if (!vector)
3598 return -ENOMEM;
3599
9b2f3477 3600 /* save the actual available vector number */
dd38c726
YL		 3601 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3602
3603 priv->vector_num = vector_num;
3604 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3605 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3606 GFP_KERNEL);
3607 if (!priv->tqp_vector) {
3608 ret = -ENOMEM;
3609 goto out;
3610 }
3611
3612 for (i = 0; i < priv->vector_num; i++) {
3613 tqp_vector = &priv->tqp_vector[i];
3614 tqp_vector->idx = i;
3615 tqp_vector->mask_addr = vector[i].io_addr;
3616 tqp_vector->vector_irq = vector[i].vector;
3617 hns3_vector_gl_rl_init(tqp_vector, priv);
3618 }
3619
76ad4f0e
S		 3620out:
3621 devm_kfree(&pdev->dev, vector);
3622 return ret;
3623}
3624
dd38c726
YL		 3625static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3626{
3627 group->ring = NULL;
3628 group->count = 0;
3629}
3630
e2152785 3631static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 3632{
3633 struct hnae3_ring_chain_node vector_ring_chain;
3634 struct hnae3_handle *h = priv->ae_handle;
3635 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3636 int i;
76ad4f0e
S		 3637
3638 for (i = 0; i < priv->vector_num; i++) {
3639 tqp_vector = &priv->tqp_vector[i];
3640
2c9dd668
HT		 3641 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3642 continue;
3643
ff7dfcdd
HT		 3644 /* Since the mapping can be overwritten, when fail to get the
3645 * chain between vector and ring, we should go on to deal with
3646 * the remaining options.
3647 */
3648 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3649 dev_warn(priv->dev, "failed to get ring chain\n");
76ad4f0e 3650
e2152785 3651 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3652 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3653
3654 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3655
dd38c726
YL		 3656 hns3_clear_ring_group(&tqp_vector->rx_group);
3657 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3658 netif_napi_del(&priv->tqp_vector[i].napi);
3659 }
dd38c726
YL		 3660}
3661
08a10068 3662static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
dd38c726
YL		 3663{
3664 struct hnae3_handle *h = priv->ae_handle;
3665 struct pci_dev *pdev = h->pdev;
3666 int i, ret;
3667
3668 for (i = 0; i < priv->vector_num; i++) {
3669 struct hns3_enet_tqp_vector *tqp_vector;
3670
3671 tqp_vector = &priv->tqp_vector[i];
3672 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3673 if (ret)
08a10068 3674 return;
dd38c726 3675 }
76ad4f0e 3676
dd38c726 3677 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3678}
3679
5f06b903
YL		 3680static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3681 unsigned int ring_type)
76ad4f0e 3682{
76ad4f0e 3683 int queue_num = priv->ae_handle->kinfo.num_tqps;
76ad4f0e 3684 struct hns3_enet_ring *ring;
c0425944 3685 int desc_num;
76ad4f0e 3686
76ad4f0e 3687 if (ring_type == HNAE3_RING_TYPE_TX) {
5f06b903 3688 ring = &priv->ring[q->tqp_index];
c0425944 3689 desc_num = priv->ae_handle->kinfo.num_tx_desc;
5f06b903 3690 ring->queue_index = q->tqp_index;
76ad4f0e 3691 } else {
5f06b903 3692 ring = &priv->ring[q->tqp_index + queue_num];
c0425944 3693 desc_num = priv->ae_handle->kinfo.num_rx_desc;
5f06b903 3694 ring->queue_index = q->tqp_index;
76ad4f0e
S		 3695 }
3696
e4e87715 3697 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3698
76ad4f0e
S		 3699 ring->tqp = q;
3700 ring->desc = NULL;
3701 ring->desc_cb = NULL;
3702 ring->dev = priv->dev;
3703 ring->desc_dma_addr = 0;
3704 ring->buf_size = q->buf_size;
2c9dd668 3705 ring->desc_num = desc_num;
76ad4f0e
S		 3706 ring->next_to_use = 0;
3707 ring->next_to_clean = 0;
20d06ca2 3708 ring->last_to_use = 0;
76ad4f0e
S		 3709}
3710
5f06b903
YL		 3711static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3712 struct hns3_nic_priv *priv)
76ad4f0e 3713{
5f06b903
YL		 3714 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3715 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
76ad4f0e
S		 3716}
3717
3718static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3719{
3720 struct hnae3_handle *h = priv->ae_handle;
3721 struct pci_dev *pdev = h->pdev;
5f06b903 3722 int i;
76ad4f0e 3723
5f06b903
YL		 3724 priv->ring = devm_kzalloc(&pdev->dev,
3725 array3_size(h->kinfo.num_tqps,
3726 sizeof(*priv->ring), 2),
3727 GFP_KERNEL);
3728 if (!priv->ring)
76ad4f0e
S		 3729 return -ENOMEM;
3730
5f06b903
YL		 3731 for (i = 0; i < h->kinfo.num_tqps; i++)
3732 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
76ad4f0e
S		 3733
3734 return 0;
76ad4f0e
S		 3735}
3736
09f2af64
PL		 3737static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3738{
5f06b903 3739 if (!priv->ring)
7b8f622e
HT		 3740 return;
3741
5f06b903
YL		 3742 devm_kfree(priv->dev, priv->ring);
3743 priv->ring = NULL;
09f2af64
PL		 3744}
3745
76ad4f0e
S		 3746static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3747{
3748 int ret;
3749
3750 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3751 return -EINVAL;
3752
77296bf6
YL		 3753 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3754 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 3755 if (!ring->desc_cb) {
3756 ret = -ENOMEM;
3757 goto out;
3758 }
3759
3760 ret = hns3_alloc_desc(ring);
3761 if (ret)
3762 goto out_with_desc_cb;
3763
3764 if (!HNAE3_IS_TX_RING(ring)) {
3765 ret = hns3_alloc_ring_buffers(ring);
3766 if (ret)
3767 goto out_with_desc;
3768 }
3769
3770 return 0;
3771
3772out_with_desc:
3773 hns3_free_desc(ring);
3774out_with_desc_cb:
77296bf6 3775 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3776 ring->desc_cb = NULL;
3777out:
3778 return ret;
3779}
3780
a723fb8e 3781void hns3_fini_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 3782{
3783 hns3_free_desc(ring);
77296bf6 3784 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3785 ring->desc_cb = NULL;
3786 ring->next_to_clean = 0;
3787 ring->next_to_use = 0;
20d06ca2 3788 ring->last_to_use = 0;
ac574b80
PL		 3789 ring->pending_buf = 0;
3790 if (ring->skb) {
3791 dev_kfree_skb_any(ring->skb);
3792 ring->skb = NULL;
3793 }
76ad4f0e
S		 3794}
3795
1db9b1bf 3796static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3797{
3798 int bd_size_type;
3799
3800 switch (buf_size) {
3801 case 512:
3802 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3803 break;
3804 case 1024:
3805 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3806 break;
3807 case 2048:
3808 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3809 break;
3810 case 4096:
3811 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3812 break;
3813 default:
3814 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3815 }
3816
3817 return bd_size_type;
3818}
3819
3820static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3821{
3822 dma_addr_t dma = ring->desc_dma_addr;
3823 struct hnae3_queue *q = ring->tqp;
3824
3825 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 3826 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S		 3827 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3828 (u32)((dma >> 31) >> 1));
3829
3830 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3831 hns3_buf_size2type(ring->buf_size));
3832 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3833 ring->desc_num / 8 - 1);
3834
3835 } else {
3836 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3837 (u32)dma);
3838 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3839 (u32)((dma >> 31) >> 1));
3840
76ad4f0e
S		 3841 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3842 ring->desc_num / 8 - 1);
3843 }
3844}
3845
1c772154
YL		 3846static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3847{
3848 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3849 int i;
3850
3851 for (i = 0; i < HNAE3_MAX_TC; i++) {
3852 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3853 int j;
3854
3855 if (!tc_info->enable)
3856 continue;
3857
3858 for (j = 0; j < tc_info->tqp_count; j++) {
3859 struct hnae3_queue *q;
3860
5f06b903 3861 q = priv->ring[tc_info->tqp_offset + j].tqp;
1c772154
YL		 3862 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3863 tc_info->tc);
3864 }
3865 }
3866}
3867
5668abda 3868int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3869{
3870 struct hnae3_handle *h = priv->ae_handle;
3871 int ring_num = h->kinfo.num_tqps * 2;
3872 int i, j;
3873 int ret;
3874
3875 for (i = 0; i < ring_num; i++) {
5f06b903 3876 ret = hns3_alloc_ring_memory(&priv->ring[i]);
76ad4f0e
S		 3877 if (ret) {
3878 dev_err(priv->dev,
3879 "Alloc ring memory fail! ret=%d\n", ret);
3880 goto out_when_alloc_ring_memory;
3881 }
3882
5f06b903 3883 u64_stats_init(&priv->ring[i].syncp);
76ad4f0e
S		 3884 }
3885
3886 return 0;
3887
3888out_when_alloc_ring_memory:
3889 for (j = i - 1; j >= 0; j--)
5f06b903 3890 hns3_fini_ring(&priv->ring[j]);
76ad4f0e
S		 3891
3892 return -ENOMEM;
3893}
3894
5668abda 3895int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3896{
3897 struct hnae3_handle *h = priv->ae_handle;
3898 int i;
3899
3900 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903
YL		 3901 hns3_fini_ring(&priv->ring[i]);
3902 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
76ad4f0e 3903 }
76ad4f0e
S		 3904 return 0;
3905}
3906
3907/* Set mac addr if it is configured. or leave it to the AE driver */
8e6de441 3908static int hns3_init_mac_addr(struct net_device *netdev)
76ad4f0e
S		 3909{
3910 struct hns3_nic_priv *priv = netdev_priv(netdev);
3911 struct hnae3_handle *h = priv->ae_handle;
3912 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3913 int ret = 0;
76ad4f0e 3914
8e6de441 3915 if (h->ae_algo->ops->get_mac_addr)
76ad4f0e 3916 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
76ad4f0e
S		 3917
3918 /* Check if the MAC address is valid, if not get a random one */
8e6de441 3919 if (!is_valid_ether_addr(mac_addr_temp)) {
76ad4f0e
S		 3920 eth_hw_addr_random(netdev);
3921 dev_warn(priv->dev, "using random MAC address %pM\n",
3922 netdev->dev_addr);
ee4bcd3b 3923 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
8e6de441
HT		 3924 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3925 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
ee4bcd3b
JS		 3926 } else {
3927 return 0;
76ad4f0e 3928 }
139e8792
L		 3929
3930 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3931 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3932
7fa6be4f 3933 return ret;
76ad4f0e
S		 3934}
3935
c8a8045b
HT		 3936static int hns3_init_phy(struct net_device *netdev)
3937{
3938 struct hnae3_handle *h = hns3_get_handle(netdev);
3939 int ret = 0;
3940
3941 if (h->ae_algo->ops->mac_connect_phy)
3942 ret = h->ae_algo->ops->mac_connect_phy(h);
3943
3944 return ret;
3945}
3946
3947static void hns3_uninit_phy(struct net_device *netdev)
3948{
3949 struct hnae3_handle *h = hns3_get_handle(netdev);
3950
3951 if (h->ae_algo->ops->mac_disconnect_phy)
3952 h->ae_algo->ops->mac_disconnect_phy(h);
3953}
3954
6871af29
JS		 3955static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3956{
3957 struct hnae3_handle *h = hns3_get_handle(netdev);
3958
3959 if (h->ae_algo->ops->del_all_fd_entries)
3960 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3961}
3962
a6d818e3
YL		 3963static int hns3_client_start(struct hnae3_handle *handle)
3964{
3965 if (!handle->ae_algo->ops->client_start)
3966 return 0;
3967
3968 return handle->ae_algo->ops->client_start(handle);
3969}
3970
3971static void hns3_client_stop(struct hnae3_handle *handle)
3972{
3973 if (!handle->ae_algo->ops->client_stop)
3974 return;
3975
3976 handle->ae_algo->ops->client_stop(handle);
3977}
3978
bb87be87
YL		 3979static void hns3_info_show(struct hns3_nic_priv *priv)
3980{
3981 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3982
3983 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
adcf738b
GL		 3984 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3985 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3986 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3987 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3988 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3989 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3990 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3991 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
bb87be87
YL		 3992}
3993
76ad4f0e
S		 3994static int hns3_client_init(struct hnae3_handle *handle)
3995{
3996 struct pci_dev *pdev = handle->pdev;
0d43bf45 3997 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3998 struct hns3_nic_priv *priv;
3999 struct net_device *netdev;
4000 int ret;
4001
0d43bf45
HT		 4002 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
4003 &max_rss_size);
4004 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 4005 if (!netdev)
4006 return -ENOMEM;
4007
4008 priv = netdev_priv(netdev);
4009 priv->dev = &pdev->dev;
4010 priv->netdev = netdev;
4011 priv->ae_handle = handle;
f8fa222c 4012 priv->tx_timeout_count = 0;
b7b585c2 4013 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 4014
bb87be87
YL		 4015 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
4016
76ad4f0e
S		 4017 handle->kinfo.netdev = netdev;
4018 handle->priv = (void *)priv;
4019
8e6de441 4020 hns3_init_mac_addr(netdev);
76ad4f0e
S		 4021
4022 hns3_set_default_feature(netdev);
4023
4024 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
4025 netdev->priv_flags |= IFF_UNICAST_FLT;
4026 netdev->netdev_ops = &hns3_nic_netdev_ops;
4027 SET_NETDEV_DEV(netdev, &pdev->dev);
4028 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 4029
4030 /* Carrier off reporting is important to ethtool even BEFORE open */
4031 netif_carrier_off(netdev);
4032
4033 ret = hns3_get_ring_config(priv);
4034 if (ret) {
4035 ret = -ENOMEM;
4036 goto out_get_ring_cfg;
4037 }
4038
dd38c726
YL		 4039 ret = hns3_nic_alloc_vector_data(priv);
4040 if (ret) {
4041 ret = -ENOMEM;
4042 goto out_alloc_vector_data;
4043 }
4044
76ad4f0e
S		 4045 ret = hns3_nic_init_vector_data(priv);
4046 if (ret) {
4047 ret = -ENOMEM;
4048 goto out_init_vector_data;
4049 }
4050
4051 ret = hns3_init_all_ring(priv);
4052 if (ret) {
4053 ret = -ENOMEM;
5f06b903 4054 goto out_init_ring;
76ad4f0e
S		 4055 }
4056
c8a8045b
HT		 4057 ret = hns3_init_phy(netdev);
4058 if (ret)
4059 goto out_init_phy;
4060
76ad4f0e
S		 4061 ret = register_netdev(netdev);
4062 if (ret) {
4063 dev_err(priv->dev, "probe register netdev fail!\n");
4064 goto out_reg_netdev_fail;
4065 }
4066
08a10068
YL		 4067 /* the device can work without cpu rmap, only aRFS needs it */
4068 ret = hns3_set_rx_cpu_rmap(netdev);
4069 if (ret)
4070 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4071
4072 ret = hns3_nic_init_irq(priv);
4073 if (ret) {
4074 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4075 hns3_free_rx_cpu_rmap(netdev);
4076 goto out_init_irq_fail;
4077 }
4078
a6d818e3
YL		 4079 ret = hns3_client_start(handle);
4080 if (ret) {
4081 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 4082 goto out_client_start;
a6d818e3
YL		 4083 }
4084
986743db
YL		 4085 hns3_dcbnl_setup(handle);
4086
b2292360 4087 hns3_dbg_init(handle);
4088
a0b43717 4089 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 4090 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 4091
814da63c
HT		 4092 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4093
bb87be87
YL		 4094 if (netif_msg_drv(handle))
4095 hns3_info_show(priv);
4096
76ad4f0e
S		 4097 return ret;
4098
18655128 4099out_client_start:
08a10068
YL		 4100 hns3_free_rx_cpu_rmap(netdev);
4101 hns3_nic_uninit_irq(priv);
4102out_init_irq_fail:
18655128 4103 unregister_netdev(netdev);
76ad4f0e 4104out_reg_netdev_fail:
c8a8045b
HT		 4105 hns3_uninit_phy(netdev);
4106out_init_phy:
4107 hns3_uninit_all_ring(priv);
5f06b903 4108out_init_ring:
e2152785 4109 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4110out_init_vector_data:
dd38c726
YL		 4111 hns3_nic_dealloc_vector_data(priv);
4112out_alloc_vector_data:
5f06b903 4113 priv->ring = NULL;
76ad4f0e
S		 4114out_get_ring_cfg:
4115 priv->ae_handle = NULL;
4116 free_netdev(netdev);
4117 return ret;
4118}
4119
4120static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4121{
4122 struct net_device *netdev = handle->kinfo.netdev;
4123 struct hns3_nic_priv *priv = netdev_priv(netdev);
4124 int ret;
4125
4126 if (netdev->reg_state != NETREG_UNINITIALIZED)
4127 unregister_netdev(netdev);
4128
eb32c896
HT		 4129 hns3_client_stop(handle);
4130
0d2f68c7
HT		 4131 hns3_uninit_phy(netdev);
4132
814da63c
HT		 4133 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4134 netdev_warn(netdev, "already uninitialized\n");
4135 goto out_netdev_free;
4136 }
4137
08a10068
YL		 4138 hns3_free_rx_cpu_rmap(netdev);
4139
4140 hns3_nic_uninit_irq(priv);
4141
dc5e6064
JS		 4142 hns3_del_all_fd_rules(netdev, true);
4143
f96315f2 4144 hns3_clear_all_ring(handle, true);
7b763f3f 4145
e2152785 4146 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4147
08a10068 4148 hns3_nic_dealloc_vector_data(priv);
dd38c726 4149
76ad4f0e
S		 4150 ret = hns3_uninit_all_ring(priv);
4151 if (ret)
4152 netdev_err(netdev, "uninit ring error\n");
4153
ec777890
YL		 4154 hns3_put_ring_config(priv);
4155
814da63c 4156out_netdev_free:
e22b5e72 4157 hns3_dbg_uninit(handle);
76ad4f0e
S		 4158 free_netdev(netdev);
4159}
4160
4161static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4162{
4163 struct net_device *netdev = handle->kinfo.netdev;
4164
4165 if (!netdev)
4166 return;
4167
4168 if (linkup) {
76ad4f0e 4169 netif_tx_wake_all_queues(netdev);
a7e90ee5 4170 netif_carrier_on(netdev);
bb87be87
YL		 4171 if (netif_msg_link(handle))
4172 netdev_info(netdev, "link up\n");
76ad4f0e
S		 4173 } else {
4174 netif_carrier_off(netdev);
4175 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 4176 if (netif_msg_link(handle))
4177 netdev_info(netdev, "link down\n");
76ad4f0e
S		 4178 }
4179}
4180
9df8f79a
YL		 4181static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4182{
4183 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4184 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL		 4185
4186 if (tc > HNAE3_MAX_TC)
4187 return -EINVAL;
4188
4189 if (!ndev)
4190 return -ENODEV;
4191
a1ef124e 4192 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL		 4193}
4194
beebca3a 4195static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 4196{
beebca3a 4197 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 4198 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
619ae331 4199 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
beebca3a
YL		 4200 ring_ptr_move_fw(ring, next_to_clean);
4201 }
f6061a05
YL		 4202
4203 ring->pending_buf = 0;
beebca3a
YL		 4204}
4205
7b763f3f
FL		 4206static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4207{
4208 struct hns3_desc_cb res_cbs;
4209 int ret;
4210
4211 while (ring->next_to_use != ring->next_to_clean) {
4212 /* When a buffer is not reused, it's memory has been
4213 * freed in hns3_handle_rx_bd or will be freed by
4214 * stack, so we need to replace the buffer here.
4215 */
4216 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4d2cad32 4217 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
7b763f3f
FL		 4218 if (ret) {
4219 u64_stats_update_begin(&ring->syncp);
4220 ring->stats.sw_err_cnt++;
4221 u64_stats_update_end(&ring->syncp);
4222 /* if alloc new buffer fail, exit directly
4223 * and reclear in up flow.
4224 */
c8711956 4225 netdev_warn(ring_to_netdev(ring),
7b763f3f
FL		 4226 "reserve buffer map failed, ret = %d\n",
4227 ret);
4228 return ret;
4229 }
9b2f3477 4230 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL		 4231 }
4232 ring_ptr_move_fw(ring, next_to_use);
4233 }
4234
cc5ff6e9
PL		 4235 /* Free the pending skb in rx ring */
4236 if (ring->skb) {
4237 dev_kfree_skb_any(ring->skb);
4238 ring->skb = NULL;
4239 ring->pending_buf = 0;
4240 }
4241
7b763f3f
FL		 4242 return 0;
4243}
4244
4245static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4246{
beebca3a
YL		 4247 while (ring->next_to_use != ring->next_to_clean) {
4248 /* When a buffer is not reused, it's memory has been
4249 * freed in hns3_handle_rx_bd or will be freed by
4250 * stack, so only need to unmap the buffer here.
4251 */
4252 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4253 hns3_unmap_buffer(ring,
4254 &ring->desc_cb[ring->next_to_use]);
4255 ring->desc_cb[ring->next_to_use].dma = 0;
4256 }
4257
4258 ring_ptr_move_fw(ring, next_to_use);
4259 }
bb6b94a8
L		 4260}
4261
f96315f2 4262static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L		 4263{
4264 struct net_device *ndev = h->kinfo.netdev;
4265 struct hns3_nic_priv *priv = netdev_priv(ndev);
4266 u32 i;
4267
4268 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L		 4269 struct hns3_enet_ring *ring;
4270
5f06b903 4271 ring = &priv->ring[i];
beebca3a 4272 hns3_clear_tx_ring(ring);
bb6b94a8 4273
5f06b903 4274 ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 4275 /* Continue to clear other rings even if clearing some
4276 * rings failed.
4277 */
f96315f2
HT		 4278 if (force)
4279 hns3_force_clear_rx_ring(ring);
4280 else
4281 hns3_clear_rx_ring(ring);
bb6b94a8
L		 4282 }
4283}
4284
7b763f3f
FL		 4285int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4286{
4287 struct net_device *ndev = h->kinfo.netdev;
4288 struct hns3_nic_priv *priv = netdev_priv(ndev);
4289 struct hns3_enet_ring *rx_ring;
4290 int i, j;
4291 int ret;
4292
4293 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 4294 ret = h->ae_algo->ops->reset_queue(h, i);
4295 if (ret)
4296 return ret;
4297
5f06b903 4298 hns3_init_ring_hw(&priv->ring[i]);
7b763f3f
FL		 4299
4300 /* We need to clear tx ring here because self test will
4301 * use the ring and will not run down before up
4302 */
5f06b903
YL		 4303 hns3_clear_tx_ring(&priv->ring[i]);
4304 priv->ring[i].next_to_clean = 0;
4305 priv->ring[i].next_to_use = 0;
20d06ca2 4306 priv->ring[i].last_to_use = 0;
7b763f3f 4307
5f06b903 4308 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 4309 hns3_init_ring_hw(rx_ring);
4310 ret = hns3_clear_rx_ring(rx_ring);
4311 if (ret)
4312 return ret;
4313
4314 /* We can not know the hardware head and tail when this
4315 * function is called in reset flow, so we reuse all desc.
4316 */
4317 for (j = 0; j < rx_ring->desc_num; j++)
4318 hns3_reuse_buffer(rx_ring, j);
4319
4320 rx_ring->next_to_clean = 0;
4321 rx_ring->next_to_use = 0;
4322 }
4323
1c772154
YL		 4324 hns3_init_tx_ring_tc(priv);
4325
7b763f3f
FL		 4326 return 0;
4327}
4328
e4fd7502
HT		 4329static void hns3_store_coal(struct hns3_nic_priv *priv)
4330{
4331 /* ethtool only support setting and querying one coal
46ee7350
GL		 4332 * configuration for now, so save the vector 0' coal
4333 * configuration here in order to restore it.
e4fd7502
HT		 4334 */
4335 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4336 sizeof(struct hns3_enet_coalesce));
4337 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4338 sizeof(struct hns3_enet_coalesce));
4339}
4340
4341static void hns3_restore_coal(struct hns3_nic_priv *priv)
4342{
4343 u16 vector_num = priv->vector_num;
4344 int i;
4345
4346 for (i = 0; i < vector_num; i++) {
4347 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4348 sizeof(struct hns3_enet_coalesce));
4349 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4350 sizeof(struct hns3_enet_coalesce));
4351 }
4352}
4353
bb6b94a8
L		 4354static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4355{
4356 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4357 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 4358 struct hns3_nic_priv *priv = netdev_priv(ndev);
4359
4360 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4361 return 0;
bb6b94a8
L		 4362
4363 if (!netif_running(ndev))
6b1385cc 4364 return 0;
bb6b94a8
L		 4365
4366 return hns3_nic_net_stop(ndev);
4367}
4368
4369static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4370{
4371 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4372 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4373 int ret = 0;
4374
e8884027
HT		 4375 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4376
bb6b94a8 4377 if (netif_running(kinfo->netdev)) {
e8884027 4378 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4379 if (ret) {
e8884027 4380 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 4381 netdev_err(kinfo->netdev,
9b2f3477 4382 "net up fail, ret=%d!\n", ret);
bb6b94a8
L		 4383 return ret;
4384 }
bb6b94a8
L		 4385 }
4386
4387 return ret;
4388}
4389
4390static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4391{
4392 struct net_device *netdev = handle->kinfo.netdev;
4393 struct hns3_nic_priv *priv = netdev_priv(netdev);
4394 int ret;
4395
bb6b94a8
L		 4396 /* Carrier off reporting is important to ethtool even BEFORE open */
4397 netif_carrier_off(netdev);
4398
2c9dd668 4399 ret = hns3_get_ring_config(priv);
862d969a
HT		 4400 if (ret)
4401 return ret;
4402
2c9dd668
HT		 4403 ret = hns3_nic_alloc_vector_data(priv);
4404 if (ret)
4405 goto err_put_ring;
4406
e4fd7502
HT		 4407 hns3_restore_coal(priv);
4408
bb6b94a8
L		 4409 ret = hns3_nic_init_vector_data(priv);
4410 if (ret)
862d969a 4411 goto err_dealloc_vector;
bb6b94a8
L		 4412
4413 ret = hns3_init_all_ring(priv);
862d969a
HT		 4414 if (ret)
4415 goto err_uninit_vector;
bb6b94a8 4416
08a10068
YL		 4417 /* the device can work without cpu rmap, only aRFS needs it */
4418 ret = hns3_set_rx_cpu_rmap(netdev);
4419 if (ret)
4420 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4421
4422 ret = hns3_nic_init_irq(priv);
4423 if (ret) {
4424 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4425 hns3_free_rx_cpu_rmap(netdev);
4426 goto err_init_irq_fail;
4427 }
4428
ee4bcd3b
JS		 4429 if (!hns3_is_phys_func(handle->pdev))
4430 hns3_init_mac_addr(netdev);
4431
cd513a69
HT		 4432 ret = hns3_client_start(handle);
4433 if (ret) {
4434 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
08a10068 4435 goto err_client_start_fail;
cd513a69
HT		 4436 }
4437
814da63c
HT		 4438 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4439
862d969a
HT		 4440 return ret;
4441
08a10068
YL		 4442err_client_start_fail:
4443 hns3_free_rx_cpu_rmap(netdev);
4444 hns3_nic_uninit_irq(priv);
4445err_init_irq_fail:
cd513a69 4446 hns3_uninit_all_ring(priv);
862d969a
HT		 4447err_uninit_vector:
4448 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 4449err_dealloc_vector:
4450 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 4451err_put_ring:
4452 hns3_put_ring_config(priv);
862d969a 4453
bb6b94a8
L		 4454 return ret;
4455}
4456
4457static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4458{
4459 struct net_device *netdev = handle->kinfo.netdev;
4460 struct hns3_nic_priv *priv = netdev_priv(netdev);
4461 int ret;
4462
1eeb3367 4463 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 4464 netdev_warn(netdev, "already uninitialized\n");
4465 return 0;
4466 }
4467
08a10068
YL		 4468 hns3_free_rx_cpu_rmap(netdev);
4469 hns3_nic_uninit_irq(priv);
f96315f2
HT		 4470 hns3_clear_all_ring(handle, true);
4471 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 4472
e2152785 4473 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4474
e4fd7502
HT		 4475 hns3_store_coal(priv);
4476
08a10068 4477 hns3_nic_dealloc_vector_data(priv);
862d969a 4478
bb6b94a8
L		 4479 ret = hns3_uninit_all_ring(priv);
4480 if (ret)
4481 netdev_err(netdev, "uninit ring error\n");
4482
2c9dd668 4483 hns3_put_ring_config(priv);
2c9dd668 4484
bb6b94a8
L		 4485 return ret;
4486}
4487
4488static int hns3_reset_notify(struct hnae3_handle *handle,
4489 enum hnae3_reset_notify_type type)
4490{
4491 int ret = 0;
4492
4493 switch (type) {
4494 case HNAE3_UP_CLIENT:
e1586241
SM		 4495 ret = hns3_reset_notify_up_enet(handle);
4496 break;
bb6b94a8
L		 4497 case HNAE3_DOWN_CLIENT:
4498 ret = hns3_reset_notify_down_enet(handle);
4499 break;
4500 case HNAE3_INIT_CLIENT:
4501 ret = hns3_reset_notify_init_enet(handle);
4502 break;
4503 case HNAE3_UNINIT_CLIENT:
4504 ret = hns3_reset_notify_uninit_enet(handle);
4505 break;
4506 default:
4507 break;
4508 }
4509
4510 return ret;
4511}
4512
3a5a5f06
PL		 4513static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4514 bool rxfh_configured)
4515{
4516 int ret;
4517
4518 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4519 rxfh_configured);
4520 if (ret) {
4521 dev_err(&handle->pdev->dev,
4522 "Change tqp num(%u) fail.\n", new_tqp_num);
4523 return ret;
4524 }
4525
4526 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4527 if (ret)
4528 return ret;
4529
4530 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4531 if (ret)
4532 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4533
4534 return ret;
4535}
4536
09f2af64
PL		 4537int hns3_set_channels(struct net_device *netdev,
4538 struct ethtool_channels *ch)
4539{
09f2af64
PL		 4540 struct hnae3_handle *h = hns3_get_handle(netdev);
4541 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4542 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 4543 u32 new_tqp_num = ch->combined_count;
4544 u16 org_tqp_num;
4545 int ret;
4546
44950d28
JS		 4547 if (hns3_nic_resetting(netdev))
4548 return -EBUSY;
4549
09f2af64
PL		 4550 if (ch->rx_count || ch->tx_count)
4551 return -EINVAL;
4552
678335a1 4553 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4554 new_tqp_num < 1) {
09f2af64 4555 dev_err(&netdev->dev,
adcf738b 4556 "Change tqps fail, the tqp range is from 1 to %u",
678335a1 4557 hns3_get_max_available_channels(h));
09f2af64
PL		 4558 return -EINVAL;
4559 }
4560
c78b5b6c 4561 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 4562 return 0;
4563
1c822948
YL		 4564 netif_dbg(h, drv, netdev,
4565 "set channels: tqp_num=%u, rxfh=%d\n",
4566 new_tqp_num, rxfh_configured);
4567
65749f73
HT		 4568 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4569 if (ret)
4570 return ret;
dd38c726 4571
65749f73
HT		 4572 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4573 if (ret)
4574 return ret;
09f2af64
PL		 4575
4576 org_tqp_num = h->kinfo.num_tqps;
3a5a5f06 4577 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4578 if (ret) {
3a5a5f06
PL		 4579 int ret1;
4580
4581 netdev_warn(netdev,
4582 "Change channels fail, revert to old value\n");
4583 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4584 if (ret1) {
4585 netdev_err(netdev,
4586 "revert to old channel fail\n");
4587 return ret1;
09f2af64 4588 }
3a5a5f06 4589
65749f73 4590 return ret;
3a5a5f06 4591 }
09f2af64 4592
3a5a5f06 4593 return 0;
09f2af64
PL		 4594}
4595
a83d2961
WL		 4596static const struct hns3_hw_error_info hns3_hw_err[] = {
4597 { .type = HNAE3_PPU_POISON_ERROR,
4598 .msg = "PPU poison" },
4599 { .type = HNAE3_CMDQ_ECC_ERROR,
4600 .msg = "IMP CMDQ error" },
4601 { .type = HNAE3_IMP_RD_POISON_ERROR,
4602 .msg = "IMP RD poison" },
4603};
4604
4605static void hns3_process_hw_error(struct hnae3_handle *handle,
4606 enum hnae3_hw_error_type type)
4607{
4608 int i;
4609
4610 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4611 if (hns3_hw_err[i].type == type) {
4612 dev_err(&handle->pdev->dev, "Detected %s!\n",
4613 hns3_hw_err[i].msg);
4614 break;
4615 }
4616 }
4617}
4618
1db9b1bf 4619static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4620 .init_instance = hns3_client_init,
4621 .uninit_instance = hns3_client_uninit,
4622 .link_status_change = hns3_link_status_change,
9df8f79a 4623 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4624 .reset_notify = hns3_reset_notify,
a83d2961 4625 .process_hw_error = hns3_process_hw_error,
76ad4f0e
S		 4626};
4627
4628/* hns3_init_module - Driver registration routine
4629 * hns3_init_module is the first routine called when the driver is
4630 * loaded. All it does is register with the PCI subsystem.
4631 */
4632static int __init hns3_init_module(void)
4633{
4634 int ret;
4635
4636 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4637 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4638
4639 client.type = HNAE3_CLIENT_KNIC;
cdc37385 4640 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
76ad4f0e
S		 4641 hns3_driver_name);
4642
4643 client.ops = &client_ops;
4644
13562d1f
XW		 4645 INIT_LIST_HEAD(&client.node);
4646
b2292360 4647 hns3_dbg_register_debugfs(hns3_driver_name);
4648
76ad4f0e
S		 4649 ret = hnae3_register_client(&client);
4650 if (ret)
b2292360 4651 goto err_reg_client;
76ad4f0e
S		 4652
4653 ret = pci_register_driver(&hns3_driver);
4654 if (ret)
b2292360 4655 goto err_reg_driver;
76ad4f0e
S		 4656
4657 return ret;
b2292360 4658
4659err_reg_driver:
4660 hnae3_unregister_client(&client);
4661err_reg_client:
4662 hns3_dbg_unregister_debugfs();
4663 return ret;
76ad4f0e
S		 4664}
4665module_init(hns3_init_module);
4666
4667/* hns3_exit_module - Driver exit cleanup routine
4668 * hns3_exit_module is called just before the driver is removed
4669 * from memory.
4670 */
4671static void __exit hns3_exit_module(void)
4672{
4673 pci_unregister_driver(&hns3_driver);
4674 hnae3_unregister_client(&client);
b2292360 4675 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4676}
4677module_exit(hns3_exit_module);
4678
4679MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4680MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4681MODULE_LICENSE("GPL");
4682MODULE_ALIAS("pci:hns-nic");
Linux 6.x block layer and io_uring tree(s)