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flow_dissector: handle no-skb use case
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
7#include <linux/if_vlan.h>
8#include <linux/ip.h>
9#include <linux/ipv6.h>
10#include <linux/module.h>
11#include <linux/pci.h>
6ae4e733 12#include <linux/aer.h>
76ad4f0e
S		 13#include <linux/skbuff.h>
14#include <linux/sctp.h>
15#include <linux/vermagic.h>
16#include <net/gre.h>
30d240df 17#include <net/pkt_cls.h>
a6d53b97 18#include <net/tcp.h>
76ad4f0e
S		 19#include <net/vxlan.h>
20
21#include "hnae3.h"
22#include "hns3_enet.h"
23
cde4ffad 24#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 25#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 26
7b763f3f
FL		 27static void hns3_clear_all_ring(struct hnae3_handle *h);
28static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
f05e2109 29static void hns3_remove_hw_addr(struct net_device *netdev);
7b763f3f 30
1db9b1bf 31static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 32const char hns3_driver_version[] = VERMAGIC_STRING;
33static const char hns3_driver_string[] =
34 "Hisilicon Ethernet Network Driver for Hip08 Family";
35static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
36static struct hnae3_client client;
37
bb87be87
YL		 38static int debug = -1;
39module_param(debug, int, 0);
40MODULE_PARM_DESC(debug, " Network interface message level setting");
41
42#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
43 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
44
76ad4f0e
S		 45/* hns3_pci_tbl - PCI Device ID Table
46 *
47 * Last entry must be all 0s
48 *
49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
50 * Class, Class Mask, private data (not used) }
51 */
52static const struct pci_device_id hns3_pci_tbl[] = {
53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
54 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 56 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 57 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 58 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 59 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 60 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 61 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 62 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 63 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 64 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 65 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
07acf909
JS		 66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
67 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 68 /* required last entry */
69 {0, }
70};
71MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
72
ef0c5009 73static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 74{
ef0c5009 75 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e
S		 76
77 napi_schedule(&tqp_vector->napi);
78
79 return IRQ_HANDLED;
80}
81
874bff0b
PL		 82/* This callback function is used to set affinity changes to the irq affinity
83 * masks when the irq_set_affinity_notifier function is used.
84 */
85static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
86 const cpumask_t *mask)
87{
88 struct hns3_enet_tqp_vector *tqp_vectors =
89 container_of(notify, struct hns3_enet_tqp_vector,
90 affinity_notify);
91
92 tqp_vectors->affinity_mask = *mask;
93}
94
95static void hns3_nic_irq_affinity_release(struct kref *ref)
96{
97}
98
76ad4f0e
S		 99static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
100{
101 struct hns3_enet_tqp_vector *tqp_vectors;
102 unsigned int i;
103
104 for (i = 0; i < priv->vector_num; i++) {
105 tqp_vectors = &priv->tqp_vector[i];
106
107 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
108 continue;
109
874bff0b
PL		 110 /* clear the affinity notifier and affinity mask */
111 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
112 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
113
76ad4f0e
S		 114 /* release the irq resource */
115 free_irq(tqp_vectors->vector_irq, tqp_vectors);
116 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
117 }
118}
119
120static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
121{
122 struct hns3_enet_tqp_vector *tqp_vectors;
123 int txrx_int_idx = 0;
124 int rx_int_idx = 0;
125 int tx_int_idx = 0;
126 unsigned int i;
127 int ret;
128
129 for (i = 0; i < priv->vector_num; i++) {
130 tqp_vectors = &priv->tqp_vector[i];
131
132 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
133 continue;
134
135 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
136 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
137 "%s-%s-%d", priv->netdev->name, "TxRx",
138 txrx_int_idx++);
139 txrx_int_idx++;
140 } else if (tqp_vectors->rx_group.ring) {
141 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
142 "%s-%s-%d", priv->netdev->name, "Rx",
143 rx_int_idx++);
144 } else if (tqp_vectors->tx_group.ring) {
145 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
146 "%s-%s-%d", priv->netdev->name, "Tx",
147 tx_int_idx++);
148 } else {
149 /* Skip this unused q_vector */
150 continue;
151 }
152
153 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
154
155 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
156 tqp_vectors->name,
157 tqp_vectors);
158 if (ret) {
159 netdev_err(priv->netdev, "request irq(%d) fail\n",
160 tqp_vectors->vector_irq);
161 return ret;
162 }
163
874bff0b
PL		 164 tqp_vectors->affinity_notify.notify =
165 hns3_nic_irq_affinity_notify;
166 tqp_vectors->affinity_notify.release =
167 hns3_nic_irq_affinity_release;
168 irq_set_affinity_notifier(tqp_vectors->vector_irq,
169 &tqp_vectors->affinity_notify);
170 irq_set_affinity_hint(tqp_vectors->vector_irq,
171 &tqp_vectors->affinity_mask);
172
76ad4f0e
S		 173 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
174 }
175
176 return 0;
177}
178
179static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
180 u32 mask_en)
181{
182 writel(mask_en, tqp_vector->mask_addr);
183}
184
185static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
186{
187 napi_enable(&tqp_vector->napi);
188
189 /* enable vector */
190 hns3_mask_vector_irq(tqp_vector, 1);
191}
192
193static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
194{
195 /* disable vector */
196 hns3_mask_vector_irq(tqp_vector, 0);
197
198 disable_irq(tqp_vector->vector_irq);
199 napi_disable(&tqp_vector->napi);
200}
201
434776a5
FL		 202void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
203 u32 rl_value)
76ad4f0e 204{
434776a5
FL		 205 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
206
76ad4f0e
S		 207 /* this defines the configuration for RL (Interrupt Rate Limiter).
208 * Rl defines rate of interrupts i.e. number of interrupts-per-second
209 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
210 */
434776a5 211
9bc727a9
YL		 212 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
213 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 214 /* According to the hardware, the range of rl_reg is
215 * 0-59 and the unit is 4.
216 */
217 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
218
219 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
220}
221
222void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
223 u32 gl_value)
224{
225 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
226
227 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
228}
229
230void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
231 u32 gl_value)
232{
233 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
234
235 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 236}
237
5fd4789a
FL		 238static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
239 struct hns3_nic_priv *priv)
76ad4f0e
S		 240{
241 /* initialize the configuration for interrupt coalescing.
242 * 1. GL (Interrupt Gap Limiter)
243 * 2. RL (Interrupt Rate Limiter)
244 */
245
5fd4789a 246 /* Default: enable interrupt coalescing self-adaptive and GL */
9bc727a9
YL		 247 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
248 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 249
9bc727a9
YL		 250 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
251 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 252
9bc727a9
YL		 253 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
254 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 255}
256
dd38c726
YL		 257static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
258 struct hns3_nic_priv *priv)
259{
260 struct hnae3_handle *h = priv->ae_handle;
261
262 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 263 tqp_vector->tx_group.coal.int_gl);
dd38c726 264 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 265 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 266 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
267}
268
9df8f79a
YL		 269static int hns3_nic_set_real_num_queue(struct net_device *netdev)
270{
9780cb97 271 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 272 struct hnae3_knic_private_info *kinfo = &h->kinfo;
273 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
a75a8efa
YL		 274 int i, ret;
275
276 if (kinfo->num_tc <= 1) {
277 netdev_reset_tc(netdev);
278 } else {
279 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
280 if (ret) {
281 netdev_err(netdev,
282 "netdev_set_num_tc fail, ret=%d!\n", ret);
283 return ret;
284 }
285
286 for (i = 0; i < HNAE3_MAX_TC; i++) {
287 if (!kinfo->tc_info[i].enable)
288 continue;
289
290 netdev_set_tc_queue(netdev,
291 kinfo->tc_info[i].tc,
292 kinfo->tc_info[i].tqp_count,
293 kinfo->tc_info[i].tqp_offset);
294 }
295 }
9df8f79a
YL		 296
297 ret = netif_set_real_num_tx_queues(netdev, queue_size);
298 if (ret) {
299 netdev_err(netdev,
300 "netif_set_real_num_tx_queues fail, ret=%d!\n",
301 ret);
302 return ret;
303 }
304
305 ret = netif_set_real_num_rx_queues(netdev, queue_size);
306 if (ret) {
307 netdev_err(netdev,
308 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
309 return ret;
310 }
311
312 return 0;
313}
314
678335a1
PL		 315static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
316{
0d43bf45 317 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 318
0d43bf45
HT		 319 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
320 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 321
0d43bf45 322 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 323}
324
8df0fa91
HT		 325static void hns3_tqp_enable(struct hnae3_queue *tqp)
326{
327 u32 rcb_reg;
328
329 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
330 rcb_reg |= BIT(HNS3_RING_EN_B);
331 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
332}
333
334static void hns3_tqp_disable(struct hnae3_queue *tqp)
335{
336 u32 rcb_reg;
337
338 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
339 rcb_reg &= ~BIT(HNS3_RING_EN_B);
340 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
341}
342
76ad4f0e
S		 343static int hns3_nic_net_up(struct net_device *netdev)
344{
345 struct hns3_nic_priv *priv = netdev_priv(netdev);
346 struct hnae3_handle *h = priv->ae_handle;
347 int i, j;
348 int ret;
349
7b763f3f
FL		 350 ret = hns3_nic_reset_all_ring(h);
351 if (ret)
352 return ret;
353
76ad4f0e
S		 354 /* get irq resource for all vectors */
355 ret = hns3_nic_init_irq(priv);
356 if (ret) {
357 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
358 return ret;
359 }
360
b7b585c2
JS		 361 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
362
76ad4f0e
S		 363 /* enable the vectors */
364 for (i = 0; i < priv->vector_num; i++)
365 hns3_vector_enable(&priv->tqp_vector[i]);
366
8df0fa91
HT		 367 /* enable rcb */
368 for (j = 0; j < h->kinfo.num_tqps; j++)
369 hns3_tqp_enable(h->kinfo.tqp[j]);
370
76ad4f0e
S		 371 /* start the ae_dev */
372 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
373 if (ret)
374 goto out_start_err;
375
376 return 0;
377
378out_start_err:
b7b585c2 379 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
8df0fa91
HT		 380 while (j--)
381 hns3_tqp_disable(h->kinfo.tqp[j]);
382
76ad4f0e
S		 383 for (j = i - 1; j >= 0; j--)
384 hns3_vector_disable(&priv->tqp_vector[j]);
385
386 hns3_nic_uninit_irq(priv);
387
388 return ret;
389}
390
2a73ac3e
YL		 391static void hns3_config_xps(struct hns3_nic_priv *priv)
392{
393 int i;
394
395 for (i = 0; i < priv->vector_num; i++) {
396 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
397 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
398
399 while (ring) {
400 int ret;
401
402 ret = netif_set_xps_queue(priv->netdev,
403 &tqp_vector->affinity_mask,
404 ring->tqp->tqp_index);
405 if (ret)
406 netdev_warn(priv->netdev,
407 "set xps queue failed: %d", ret);
408
409 ring = ring->next;
410 }
411 }
412}
413
76ad4f0e
S		 414static int hns3_nic_net_open(struct net_device *netdev)
415{
8cdb992f 416 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 417 struct hnae3_handle *h = hns3_get_handle(netdev);
418 struct hnae3_knic_private_info *kinfo;
419 int i, ret;
76ad4f0e 420
257e4f29
HT		 421 if (hns3_nic_resetting(netdev))
422 return -EBUSY;
423
76ad4f0e
S		 424 netif_carrier_off(netdev);
425
9df8f79a
YL		 426 ret = hns3_nic_set_real_num_queue(netdev);
427 if (ret)
76ad4f0e 428 return ret;
76ad4f0e
S		 429
430 ret = hns3_nic_net_up(netdev);
431 if (ret) {
432 netdev_err(netdev,
433 "hns net up fail, ret=%d!\n", ret);
434 return ret;
435 }
436
a75a8efa
YL		 437 kinfo = &h->kinfo;
438 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
439 netdev_set_prio_tc_map(netdev, i,
440 kinfo->prio_tc[i]);
441 }
442
8cdb992f
JS		 443 if (h->ae_algo->ops->set_timer_task)
444 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
445
2a73ac3e 446 hns3_config_xps(priv);
76ad4f0e
S		 447 return 0;
448}
449
450static void hns3_nic_net_down(struct net_device *netdev)
451{
452 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 453 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 454 const struct hnae3_ae_ops *ops;
455 int i;
456
7b763f3f
FL		 457 /* disable vectors */
458 for (i = 0; i < priv->vector_num; i++)
459 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 460
461 /* disable rcb */
462 for (i = 0; i < h->kinfo.num_tqps; i++)
463 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 464
76ad4f0e
S		 465 /* stop ae_dev */
466 ops = priv->ae_handle->ae_algo->ops;
467 if (ops->stop)
468 ops->stop(priv->ae_handle);
469
76ad4f0e
S		 470 /* free irq resources */
471 hns3_nic_uninit_irq(priv);
7b763f3f
FL		 472
473 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 474}
475
476static int hns3_nic_net_stop(struct net_device *netdev)
477{
ff0699e0 478 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 479 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 480
481 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
482 return 0;
483
8cdb992f
JS		 484 if (h->ae_algo->ops->set_timer_task)
485 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
486
76ad4f0e
S		 487 netif_tx_stop_all_queues(netdev);
488 netif_carrier_off(netdev);
489
490 hns3_nic_net_down(netdev);
491
492 return 0;
493}
494
76ad4f0e
S		 495static int hns3_nic_uc_sync(struct net_device *netdev,
496 const unsigned char *addr)
497{
9780cb97 498 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 499
500 if (h->ae_algo->ops->add_uc_addr)
501 return h->ae_algo->ops->add_uc_addr(h, addr);
502
503 return 0;
504}
505
506static int hns3_nic_uc_unsync(struct net_device *netdev,
507 const unsigned char *addr)
508{
9780cb97 509 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 510
511 if (h->ae_algo->ops->rm_uc_addr)
512 return h->ae_algo->ops->rm_uc_addr(h, addr);
513
514 return 0;
515}
516
517static int hns3_nic_mc_sync(struct net_device *netdev,
518 const unsigned char *addr)
519{
9780cb97 520 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 521
720a8478 522 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 523 return h->ae_algo->ops->add_mc_addr(h, addr);
524
525 return 0;
526}
527
528static int hns3_nic_mc_unsync(struct net_device *netdev,
529 const unsigned char *addr)
530{
9780cb97 531 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 532
720a8478 533 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 534 return h->ae_algo->ops->rm_mc_addr(h, addr);
535
536 return 0;
537}
538
c60edc17
JS		 539static u8 hns3_get_netdev_flags(struct net_device *netdev)
540{
541 u8 flags = 0;
542
543 if (netdev->flags & IFF_PROMISC) {
28673b33 544 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS		 545 } else {
546 flags |= HNAE3_VLAN_FLTR;
547 if (netdev->flags & IFF_ALLMULTI)
548 flags |= HNAE3_USER_MPE;
549 }
550
551 return flags;
552}
553
1db9b1bf 554static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 555{
9780cb97 556 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17
JS		 557 u8 new_flags;
558 int ret;
76ad4f0e 559
c60edc17
JS		 560 new_flags = hns3_get_netdev_flags(netdev);
561
562 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
563 if (ret) {
76ad4f0e 564 netdev_err(netdev, "sync uc address fail\n");
c60edc17
JS		 565 if (ret == -ENOSPC)
566 new_flags |= HNAE3_OVERFLOW_UPE;
567 }
568
40cca1c5 569 if (netdev->flags & IFF_MULTICAST) {
c60edc17
JS		 570 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
571 hns3_nic_mc_unsync);
572 if (ret) {
76ad4f0e 573 netdev_err(netdev, "sync mc address fail\n");
c60edc17
JS		 574 if (ret == -ENOSPC)
575 new_flags |= HNAE3_OVERFLOW_MPE;
576 }
577 }
578
c60edc17
JS		 579 /* User mode Promisc mode enable and vlan filtering is disabled to
580 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
581 * vlan fitering is enabled
582 */
583 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
584 h->netdev_flags = new_flags;
28673b33 585 hns3_update_promisc_mode(netdev, new_flags);
c60edc17
JS		 586}
587
7fa6be4f 588int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
c60edc17
JS		 589{
590 struct hns3_nic_priv *priv = netdev_priv(netdev);
591 struct hnae3_handle *h = priv->ae_handle;
592
593 if (h->ae_algo->ops->set_promisc_mode) {
7fa6be4f
HT		 594 return h->ae_algo->ops->set_promisc_mode(h,
595 promisc_flags & HNAE3_UPE,
596 promisc_flags & HNAE3_MPE);
c60edc17 597 }
7fa6be4f
HT		 598
599 return 0;
c60edc17
JS		 600}
601
602void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
603{
604 struct hns3_nic_priv *priv = netdev_priv(netdev);
605 struct hnae3_handle *h = priv->ae_handle;
606 bool last_state;
607
608 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
609 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
610 if (enable != last_state) {
611 netdev_info(netdev,
612 "%s vlan filter\n",
613 enable ? "enable" : "disable");
614 h->ae_algo->ops->enable_vlan_filter(h, enable);
615 }
40cca1c5 616 }
76ad4f0e
S		 617}
618
619static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
620 u16 *mss, u32 *type_cs_vlan_tso)
621{
622 u32 l4_offset, hdr_len;
623 union l3_hdr_info l3;
624 union l4_hdr_info l4;
625 u32 l4_paylen;
626 int ret;
627
628 if (!skb_is_gso(skb))
629 return 0;
630
631 ret = skb_cow_head(skb, 0);
0cccebac 632 if (unlikely(ret))
76ad4f0e
S		 633 return ret;
634
635 l3.hdr = skb_network_header(skb);
636 l4.hdr = skb_transport_header(skb);
637
638 /* Software should clear the IPv4's checksum field when tso is
639 * needed.
640 */
641 if (l3.v4->version == 4)
642 l3.v4->check = 0;
643
644 /* tunnel packet.*/
645 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
646 SKB_GSO_GRE_CSUM |
647 SKB_GSO_UDP_TUNNEL |
648 SKB_GSO_UDP_TUNNEL_CSUM)) {
649 if ((!(skb_shinfo(skb)->gso_type &
650 SKB_GSO_PARTIAL)) &&
651 (skb_shinfo(skb)->gso_type &
652 SKB_GSO_UDP_TUNNEL_CSUM)) {
653 /* Software should clear the udp's checksum
654 * field when tso is needed.
655 */
656 l4.udp->check = 0;
657 }
658 /* reset l3&l4 pointers from outer to inner headers */
659 l3.hdr = skb_inner_network_header(skb);
660 l4.hdr = skb_inner_transport_header(skb);
661
662 /* Software should clear the IPv4's checksum field when
663 * tso is needed.
664 */
665 if (l3.v4->version == 4)
666 l3.v4->check = 0;
667 }
668
669 /* normal or tunnel packet*/
670 l4_offset = l4.hdr - skb->data;
3fe13ed9 671 hdr_len = (l4.tcp->doff << 2) + l4_offset;
76ad4f0e
S		 672
673 /* remove payload length from inner pseudo checksum when tso*/
674 l4_paylen = skb->len - l4_offset;
675 csum_replace_by_diff(&l4.tcp->check,
676 (__force __wsum)htonl(l4_paylen));
677
678 /* find the txbd field values */
679 *paylen = skb->len - hdr_len;
cde4ffad 680 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 681
682 /* get MSS for TSO */
683 *mss = skb_shinfo(skb)->gso_size;
684
685 return 0;
686}
687
1898d4e4
S		 688static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
689 u8 *il4_proto)
76ad4f0e 690{
1a6e552d 691 union l3_hdr_info l3;
76ad4f0e
S		 692 unsigned char *l4_hdr;
693 unsigned char *exthdr;
694 u8 l4_proto_tmp;
695 __be16 frag_off;
696
697 /* find outer header point */
698 l3.hdr = skb_network_header(skb);
35f58fd7 699 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 700
701 if (skb->protocol == htons(ETH_P_IPV6)) {
702 exthdr = l3.hdr + sizeof(*l3.v6);
703 l4_proto_tmp = l3.v6->nexthdr;
704 if (l4_hdr != exthdr)
705 ipv6_skip_exthdr(skb, exthdr - skb->data,
706 &l4_proto_tmp, &frag_off);
707 } else if (skb->protocol == htons(ETH_P_IP)) {
708 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 709 } else {
710 return -EINVAL;
76ad4f0e
S		 711 }
712
713 *ol4_proto = l4_proto_tmp;
714
715 /* tunnel packet */
716 if (!skb->encapsulation) {
717 *il4_proto = 0;
1898d4e4 718 return 0;
76ad4f0e
S		 719 }
720
721 /* find inner header point */
722 l3.hdr = skb_inner_network_header(skb);
723 l4_hdr = skb_inner_transport_header(skb);
724
725 if (l3.v6->version == 6) {
726 exthdr = l3.hdr + sizeof(*l3.v6);
727 l4_proto_tmp = l3.v6->nexthdr;
728 if (l4_hdr != exthdr)
729 ipv6_skip_exthdr(skb, exthdr - skb->data,
730 &l4_proto_tmp, &frag_off);
731 } else if (l3.v4->version == 4) {
732 l4_proto_tmp = l3.v4->protocol;
733 }
734
735 *il4_proto = l4_proto_tmp;
1898d4e4
S		 736
737 return 0;
76ad4f0e
S		 738}
739
740static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
741 u8 il4_proto, u32 *type_cs_vlan_tso,
742 u32 *ol_type_vlan_len_msec)
743{
1a6e552d 744 union l3_hdr_info l3;
745 union l4_hdr_info l4;
76ad4f0e
S		 746 unsigned char *l2_hdr;
747 u8 l4_proto = ol4_proto;
748 u32 ol2_len;
749 u32 ol3_len;
750 u32 ol4_len;
751 u32 l2_len;
752 u32 l3_len;
753
754 l3.hdr = skb_network_header(skb);
755 l4.hdr = skb_transport_header(skb);
756
757 /* compute L2 header size for normal packet, defined in 2 Bytes */
758 l2_len = l3.hdr - skb->data;
cde4ffad 759 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 760
761 /* tunnel packet*/
762 if (skb->encapsulation) {
763 /* compute OL2 header size, defined in 2 Bytes */
764 ol2_len = l2_len;
cde4ffad
YL		 765 hns3_set_field(*ol_type_vlan_len_msec,
766 HNS3_TXD_L2LEN_S, ol2_len >> 1);
76ad4f0e
S		 767
768 /* compute OL3 header size, defined in 4 Bytes */
769 ol3_len = l4.hdr - l3.hdr;
cde4ffad
YL		 770 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S,
771 ol3_len >> 2);
76ad4f0e
S		 772
773 /* MAC in UDP, MAC in GRE (0x6558)*/
774 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
775 /* switch MAC header ptr from outer to inner header.*/
776 l2_hdr = skb_inner_mac_header(skb);
777
778 /* compute OL4 header size, defined in 4 Bytes. */
779 ol4_len = l2_hdr - l4.hdr;
cde4ffad
YL		 780 hns3_set_field(*ol_type_vlan_len_msec,
781 HNS3_TXD_L4LEN_S, ol4_len >> 2);
76ad4f0e
S		 782
783 /* switch IP header ptr from outer to inner header */
784 l3.hdr = skb_inner_network_header(skb);
785
786 /* compute inner l2 header size, defined in 2 Bytes. */
787 l2_len = l3.hdr - l2_hdr;
cde4ffad
YL		 788 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S,
789 l2_len >> 1);
76ad4f0e
S		 790 } else {
791 /* skb packet types not supported by hardware,
792 * txbd len fild doesn't be filled.
793 */
794 return;
795 }
796
797 /* switch L4 header pointer from outer to inner */
798 l4.hdr = skb_inner_transport_header(skb);
799
800 l4_proto = il4_proto;
801 }
802
803 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
804 l3_len = l4.hdr - l3.hdr;
cde4ffad 805 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e
S		 806
807 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
808 switch (l4_proto) {
809 case IPPROTO_TCP:
cde4ffad
YL		 810 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
811 l4.tcp->doff);
76ad4f0e
S		 812 break;
813 case IPPROTO_SCTP:
cde4ffad
YL		 814 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
815 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 816 break;
817 case IPPROTO_UDP:
cde4ffad
YL		 818 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
819 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 820 break;
821 default:
822 /* skb packet types not supported by hardware,
823 * txbd len fild doesn't be filled.
824 */
825 return;
826 }
827}
828
3db084d2
YL		 829/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
830 * and it is udp packet, which has a dest port as the IANA assigned.
831 * the hardware is expected to do the checksum offload, but the
832 * hardware will not do the checksum offload when udp dest port is
833 * 4789.
834 */
835static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
836{
1a6e552d 837 union l4_hdr_info l4;
3db084d2
YL		 838
839 l4.hdr = skb_transport_header(skb);
840
bea96410
MS		 841 if (!(!skb->encapsulation &&
842 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
3db084d2
YL		 843 return false;
844
845 skb_checksum_help(skb);
846
847 return true;
848}
849
76ad4f0e
S		 850static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
851 u8 il4_proto, u32 *type_cs_vlan_tso,
852 u32 *ol_type_vlan_len_msec)
853{
1a6e552d 854 union l3_hdr_info l3;
76ad4f0e
S		 855 u32 l4_proto = ol4_proto;
856
857 l3.hdr = skb_network_header(skb);
858
859 /* define OL3 type and tunnel type(OL4).*/
860 if (skb->encapsulation) {
861 /* define outer network header type.*/
862 if (skb->protocol == htons(ETH_P_IP)) {
863 if (skb_is_gso(skb))
cde4ffad
YL		 864 hns3_set_field(*ol_type_vlan_len_msec,
865 HNS3_TXD_OL3T_S,
866 HNS3_OL3T_IPV4_CSUM);
76ad4f0e 867 else
cde4ffad
YL		 868 hns3_set_field(*ol_type_vlan_len_msec,
869 HNS3_TXD_OL3T_S,
870 HNS3_OL3T_IPV4_NO_CSUM);
76ad4f0e
S		 871
872 } else if (skb->protocol == htons(ETH_P_IPV6)) {
cde4ffad
YL		 873 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
874 HNS3_OL3T_IPV6);
76ad4f0e
S		 875 }
876
877 /* define tunnel type(OL4).*/
878 switch (l4_proto) {
879 case IPPROTO_UDP:
cde4ffad
YL		 880 hns3_set_field(*ol_type_vlan_len_msec,
881 HNS3_TXD_TUNTYPE_S,
882 HNS3_TUN_MAC_IN_UDP);
76ad4f0e
S		 883 break;
884 case IPPROTO_GRE:
cde4ffad
YL		 885 hns3_set_field(*ol_type_vlan_len_msec,
886 HNS3_TXD_TUNTYPE_S,
887 HNS3_TUN_NVGRE);
76ad4f0e
S		 888 break;
889 default:
890 /* drop the skb tunnel packet if hardware don't support,
891 * because hardware can't calculate csum when TSO.
892 */
893 if (skb_is_gso(skb))
894 return -EDOM;
895
896 /* the stack computes the IP header already,
897 * driver calculate l4 checksum when not TSO.
898 */
899 skb_checksum_help(skb);
900 return 0;
901 }
902
903 l3.hdr = skb_inner_network_header(skb);
904 l4_proto = il4_proto;
905 }
906
907 if (l3.v4->version == 4) {
cde4ffad
YL		 908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
909 HNS3_L3T_IPV4);
76ad4f0e
S		 910
911 /* the stack computes the IP header already, the only time we
912 * need the hardware to recompute it is in the case of TSO.
913 */
914 if (skb_is_gso(skb))
cde4ffad 915 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 916 } else if (l3.v6->version == 6) {
cde4ffad
YL		 917 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
918 HNS3_L3T_IPV6);
76ad4f0e
S		 919 }
920
921 switch (l4_proto) {
922 case IPPROTO_TCP:
cde4ffad
YL		 923 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
924 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
925 HNS3_L4T_TCP);
76ad4f0e
S		 926 break;
927 case IPPROTO_UDP:
3db084d2
YL		 928 if (hns3_tunnel_csum_bug(skb))
929 break;
930
cde4ffad
YL		 931 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
932 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
933 HNS3_L4T_UDP);
76ad4f0e
S		 934 break;
935 case IPPROTO_SCTP:
cde4ffad
YL		 936 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
937 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
938 HNS3_L4T_SCTP);
76ad4f0e
S		 939 break;
940 default:
941 /* drop the skb tunnel packet if hardware don't support,
942 * because hardware can't calculate csum when TSO.
943 */
944 if (skb_is_gso(skb))
945 return -EDOM;
946
947 /* the stack computes the IP header already,
948 * driver calculate l4 checksum when not TSO.
949 */
950 skb_checksum_help(skb);
951 return 0;
952 }
953
954 return 0;
955}
956
957static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
958{
959 /* Config bd buffer end */
cde4ffad
YL		 960 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
961 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
76ad4f0e
S		 962}
963
9699cffe
PL		 964static int hns3_fill_desc_vtags(struct sk_buff *skb,
965 struct hns3_enet_ring *tx_ring,
966 u32 *inner_vlan_flag,
967 u32 *out_vlan_flag,
968 u16 *inner_vtag,
969 u16 *out_vtag)
970{
971#define HNS3_TX_VLAN_PRIO_SHIFT 13
972
44e626f7
JS		 973 struct hnae3_handle *handle = tx_ring->tqp->handle;
974
975 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
976 * header is allowed in skb, otherwise it will cause RAS error.
977 */
978 if (unlikely(skb_vlan_tagged_multi(skb) &&
979 handle->port_base_vlan_state ==
980 HNAE3_PORT_BASE_VLAN_ENABLE))
981 return -EINVAL;
982
9699cffe
PL		 983 if (skb->protocol == htons(ETH_P_8021Q) &&
984 !(tx_ring->tqp->handle->kinfo.netdev->features &
985 NETIF_F_HW_VLAN_CTAG_TX)) {
986 /* When HW VLAN acceleration is turned off, and the stack
987 * sets the protocol to 802.1q, the driver just need to
988 * set the protocol to the encapsulated ethertype.
989 */
990 skb->protocol = vlan_get_protocol(skb);
991 return 0;
992 }
993
994 if (skb_vlan_tag_present(skb)) {
995 u16 vlan_tag;
996
997 vlan_tag = skb_vlan_tag_get(skb);
998 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
999
1000 /* Based on hw strategy, use out_vtag in two layer tag case,
1001 * and use inner_vtag in one tag case.
1002 */
1003 if (skb->protocol == htons(ETH_P_8021Q)) {
44e626f7
JS		 1004 if (handle->port_base_vlan_state ==
1005 HNAE3_PORT_BASE_VLAN_DISABLE){
1006 hns3_set_field(*out_vlan_flag,
1007 HNS3_TXD_OVLAN_B, 1);
1008 *out_vtag = vlan_tag;
1009 } else {
1010 hns3_set_field(*inner_vlan_flag,
1011 HNS3_TXD_VLAN_B, 1);
1012 *inner_vtag = vlan_tag;
1013 }
9699cffe 1014 } else {
cde4ffad 1015 hns3_set_field(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
9699cffe
PL		 1016 *inner_vtag = vlan_tag;
1017 }
1018 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1019 struct vlan_ethhdr *vhdr;
1020 int rc;
1021
1022 rc = skb_cow_head(skb, 0);
0cccebac 1023 if (unlikely(rc < 0))
9699cffe
PL		 1024 return rc;
1025 vhdr = (struct vlan_ethhdr *)skb->data;
1026 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1027 << HNS3_TX_VLAN_PRIO_SHIFT);
1028 }
1029
1030 skb->protocol = vlan_get_protocol(skb);
1031 return 0;
1032}
1033
76ad4f0e 1034static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
5188f218 1035 int size, int frag_end, enum hns_desc_type type)
76ad4f0e
S		 1036{
1037 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1038 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1039 struct device *dev = ring_to_dev(ring);
5188f218 1040 struct skb_frag_struct *frag;
1e8a7977 1041 unsigned int frag_buf_num;
47e7b13b 1042 int k, sizeoflast;
5188f218 1043 dma_addr_t dma;
76ad4f0e 1044
76ad4f0e 1045 if (type == DESC_TYPE_SKB) {
47e7b13b
YL		 1046 struct sk_buff *skb = (struct sk_buff *)priv;
1047 u32 ol_type_vlan_len_msec = 0;
1048 u32 type_cs_vlan_tso = 0;
1049 u32 paylen = skb->len;
1050 u16 inner_vtag = 0;
1051 u16 out_vtag = 0;
1052 u16 mss = 0;
1053 int ret;
76ad4f0e 1054
9699cffe
PL		 1055 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1056 &ol_type_vlan_len_msec,
1057 &inner_vtag, &out_vtag);
1058 if (unlikely(ret))
1059 return ret;
1060
76ad4f0e 1061 if (skb->ip_summed == CHECKSUM_PARTIAL) {
47e7b13b
YL		 1062 u8 ol4_proto, il4_proto;
1063
76ad4f0e 1064 skb_reset_mac_len(skb);
76ad4f0e 1065
1898d4e4 1066 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
0cccebac 1067 if (unlikely(ret))
1898d4e4 1068 return ret;
76ad4f0e
S		 1069 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
1070 &type_cs_vlan_tso,
1071 &ol_type_vlan_len_msec);
1072 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
1073 &type_cs_vlan_tso,
1074 &ol_type_vlan_len_msec);
0cccebac 1075 if (unlikely(ret))
76ad4f0e
S		 1076 return ret;
1077
1078 ret = hns3_set_tso(skb, &paylen, &mss,
1079 &type_cs_vlan_tso);
0cccebac 1080 if (unlikely(ret))
76ad4f0e
S		 1081 return ret;
1082 }
1083
1084 /* Set txbd */
1085 desc->tx.ol_type_vlan_len_msec =
1086 cpu_to_le32(ol_type_vlan_len_msec);
1087 desc->tx.type_cs_vlan_tso_len =
1088 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 1089 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 1090 desc->tx.mss = cpu_to_le16(mss);
9699cffe
PL		 1091 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1092 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
5188f218
PL		 1093
1094 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1095 } else {
1096 frag = (struct skb_frag_struct *)priv;
1097 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1098 }
1099
0cccebac 1100 if (unlikely(dma_mapping_error(ring->dev, dma))) {
5188f218
PL		 1101 ring->stats.sw_err_cnt++;
1102 return -ENOMEM;
76ad4f0e
S		 1103 }
1104
bcdb12b7
FL		 1105 desc_cb->length = size;
1106
ceca4a5e
YL		 1107 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1108 u16 bdtp_fe_sc_vld_ra_ri = 0;
1109
1110 desc_cb->priv = priv;
1111 desc_cb->dma = dma;
1112 desc_cb->type = type;
1113 desc->addr = cpu_to_le64(dma);
1114 desc->tx.send_size = cpu_to_le16(size);
1115 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
1116 desc->tx.bdtp_fe_sc_vld_ra_ri =
1117 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1118
1119 ring_ptr_move_fw(ring, next_to_use);
1120 return 0;
1121 }
1122
5f543a54 1123 frag_buf_num = hns3_tx_bd_count(size);
3fe13ed9 1124 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1e8a7977
FL		 1125 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1126
1127 /* When frag size is bigger than hardware limit, split this frag */
1128 for (k = 0; k < frag_buf_num; k++) {
ceca4a5e
YL		 1129 u16 bdtp_fe_sc_vld_ra_ri = 0;
1130
1e8a7977
FL		 1131 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1132 desc_cb->priv = priv;
1e8a7977
FL		 1133 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1134 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1135 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1136
1137 /* now, fill the descriptor */
1138 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7
FL		 1139 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1140 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977
FL		 1141 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1142 frag_end && (k == frag_buf_num - 1) ?
1143 1 : 0);
1144 desc->tx.bdtp_fe_sc_vld_ra_ri =
1145 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1146
1147 /* move ring pointer to next.*/
1148 ring_ptr_move_fw(ring, next_to_use);
1149
1150 desc_cb = &ring->desc_cb[ring->next_to_use];
1151 desc = &ring->desc[ring->next_to_use];
1152 }
76ad4f0e
S		 1153
1154 return 0;
1155}
1156
76ad4f0e
S		 1157static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1158 struct hns3_enet_ring *ring)
1159{
1160 struct sk_buff *skb = *out_skb;
51e8439f 1161 struct sk_buff *new_skb = NULL;
76ad4f0e
S		 1162 struct skb_frag_struct *frag;
1163 int bdnum_for_frag;
1164 int frag_num;
1165 int buf_num;
1166 int size;
1167 int i;
1168
1169 size = skb_headlen(skb);
5f543a54 1170 buf_num = hns3_tx_bd_count(size);
76ad4f0e
S		 1171
1172 frag_num = skb_shinfo(skb)->nr_frags;
1173 for (i = 0; i < frag_num; i++) {
1174 frag = &skb_shinfo(skb)->frags[i];
1175 size = skb_frag_size(frag);
5f543a54 1176 bdnum_for_frag = hns3_tx_bd_count(size);
0cccebac 1177 if (unlikely(bdnum_for_frag > HNS3_MAX_BD_PER_FRAG))
76ad4f0e
S		 1178 return -ENOMEM;
1179
1180 buf_num += bdnum_for_frag;
1181 }
1182
51e8439f 1183 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) {
5f543a54 1184 buf_num = hns3_tx_bd_count(skb->len);
51e8439f
PL		 1185 if (ring_space(ring) < buf_num)
1186 return -EBUSY;
1187 /* manual split the send packet */
1188 new_skb = skb_copy(skb, GFP_ATOMIC);
1189 if (!new_skb)
1190 return -ENOMEM;
1191 dev_kfree_skb_any(skb);
1192 *out_skb = new_skb;
1193 }
1194
1195 if (unlikely(ring_space(ring) < buf_num))
76ad4f0e
S		 1196 return -EBUSY;
1197
1198 *bnum = buf_num;
1199 return 0;
1200}
1201
1202static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1203 struct hns3_enet_ring *ring)
1204{
1205 struct sk_buff *skb = *out_skb;
51e8439f 1206 struct sk_buff *new_skb = NULL;
76ad4f0e
S		 1207 int buf_num;
1208
1209 /* No. of segments (plus a header) */
1210 buf_num = skb_shinfo(skb)->nr_frags + 1;
1211
51e8439f 1212 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) {
5f543a54 1213 buf_num = hns3_tx_bd_count(skb->len);
51e8439f
PL		 1214 if (ring_space(ring) < buf_num)
1215 return -EBUSY;
1216 /* manual split the send packet */
1217 new_skb = skb_copy(skb, GFP_ATOMIC);
1218 if (!new_skb)
1219 return -ENOMEM;
1220 dev_kfree_skb_any(skb);
1221 *out_skb = new_skb;
1222 }
1223
932d1252 1224 if (unlikely(ring_space(ring) < buf_num))
76ad4f0e
S		 1225 return -EBUSY;
1226
1227 *bnum = buf_num;
1228
1229 return 0;
1230}
1231
ba3f808f 1232static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1233{
1234 struct device *dev = ring_to_dev(ring);
1235 unsigned int i;
1236
1237 for (i = 0; i < ring->desc_num; i++) {
1238 /* check if this is where we started */
1239 if (ring->next_to_use == next_to_use_orig)
1240 break;
1241
1242 /* unmap the descriptor dma address */
1243 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1244 dma_unmap_single(dev,
1245 ring->desc_cb[ring->next_to_use].dma,
1246 ring->desc_cb[ring->next_to_use].length,
1247 DMA_TO_DEVICE);
bcdb12b7 1248 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1249 dma_unmap_page(dev,
1250 ring->desc_cb[ring->next_to_use].dma,
1251 ring->desc_cb[ring->next_to_use].length,
1252 DMA_TO_DEVICE);
1253
bcdb12b7
FL		 1254 ring->desc_cb[ring->next_to_use].length = 0;
1255
76ad4f0e
S		 1256 /* rollback one */
1257 ring_ptr_move_bw(ring, next_to_use);
1258 }
1259}
1260
d43e5aca 1261netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1262{
1263 struct hns3_nic_priv *priv = netdev_priv(netdev);
1264 struct hns3_nic_ring_data *ring_data =
1265 &tx_ring_data(priv, skb->queue_mapping);
1266 struct hns3_enet_ring *ring = ring_data->ring;
76ad4f0e
S		 1267 struct netdev_queue *dev_queue;
1268 struct skb_frag_struct *frag;
1269 int next_to_use_head;
1270 int next_to_use_frag;
76ad4f0e
S		 1271 int buf_num;
1272 int seg_num;
1273 int size;
1274 int ret;
1275 int i;
1276
1277 /* Prefetch the data used later */
1278 prefetch(skb->data);
1279
1280 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1281 case -EBUSY:
1282 u64_stats_update_begin(&ring->syncp);
1283 ring->stats.tx_busy++;
1284 u64_stats_update_end(&ring->syncp);
1285
1286 goto out_net_tx_busy;
1287 case -ENOMEM:
1288 u64_stats_update_begin(&ring->syncp);
1289 ring->stats.sw_err_cnt++;
1290 u64_stats_update_end(&ring->syncp);
1291 netdev_err(netdev, "no memory to xmit!\n");
1292
1293 goto out_err_tx_ok;
1294 default:
1295 break;
1296 }
1297
1298 /* No. of segments (plus a header) */
1299 seg_num = skb_shinfo(skb)->nr_frags + 1;
1300 /* Fill the first part */
1301 size = skb_headlen(skb);
1302
1303 next_to_use_head = ring->next_to_use;
1304
d40fa7ee
YL		 1305 ret = hns3_fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1306 DESC_TYPE_SKB);
0cccebac 1307 if (unlikely(ret))
ba3f808f 1308 goto head_fill_err;
76ad4f0e
S		 1309
1310 next_to_use_frag = ring->next_to_use;
1311 /* Fill the fragments */
1312 for (i = 1; i < seg_num; i++) {
1313 frag = &skb_shinfo(skb)->frags[i - 1];
1314 size = skb_frag_size(frag);
5188f218 1315
d40fa7ee
YL		 1316 ret = hns3_fill_desc(ring, frag, size,
1317 seg_num - 1 == i ? 1 : 0,
1318 DESC_TYPE_PAGE);
76ad4f0e 1319
0cccebac 1320 if (unlikely(ret))
ba3f808f 1321 goto frag_fill_err;
76ad4f0e
S		 1322 }
1323
1324 /* Complete translate all packets */
1325 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1326 netdev_tx_sent_queue(dev_queue, skb->len);
1327
1328 wmb(); /* Commit all data before submit */
1329
e4e87715 1330 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1331
1332 return NETDEV_TX_OK;
1333
ba3f808f
FL		 1334frag_fill_err:
1335 hns3_clear_desc(ring, next_to_use_frag);
76ad4f0e 1336
ba3f808f
FL		 1337head_fill_err:
1338 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1339
1340out_err_tx_ok:
1341 dev_kfree_skb_any(skb);
1342 return NETDEV_TX_OK;
1343
1344out_net_tx_busy:
1345 netif_stop_subqueue(netdev, ring_data->queue_index);
1346 smp_mb(); /* Commit all data before submit */
1347
1348 return NETDEV_TX_BUSY;
1349}
1350
1351static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1352{
9780cb97 1353 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1354 struct sockaddr *mac_addr = p;
1355 int ret;
1356
1357 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1358 return -EADDRNOTAVAIL;
1359
5ec2a51e
JS		 1360 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1361 netdev_info(netdev, "already using mac address %pM\n",
1362 mac_addr->sa_data);
1363 return 0;
1364 }
1365
59098055 1366 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1367 if (ret) {
1368 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1369 return ret;
1370 }
1371
1372 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1373
1374 return 0;
1375}
1376
26483246
XW		 1377static int hns3_nic_do_ioctl(struct net_device *netdev,
1378 struct ifreq *ifr, int cmd)
1379{
1380 struct hnae3_handle *h = hns3_get_handle(netdev);
1381
1382 if (!netif_running(netdev))
1383 return -EINVAL;
1384
1385 if (!h->ae_algo->ops->do_ioctl)
1386 return -EOPNOTSUPP;
1387
1388 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1389}
1390
76ad4f0e
S		 1391static int hns3_nic_set_features(struct net_device *netdev,
1392 netdev_features_t features)
1393{
181d454b 1394 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1395 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1396 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1397 bool enable;
052ece6d 1398 int ret;
76ad4f0e 1399
181d454b 1400 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
0bbbf15d 1401 if (features & (NETIF_F_TSO | NETIF_F_TSO6))
181d454b 1402 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
0bbbf15d 1403 else
181d454b 1404 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 1405 }
1406
5c9f6b39 1407 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 1408 enable = !!(features & NETIF_F_GRO_HW);
1409 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 1410 if (ret)
1411 return ret;
1412 }
1413
bd368416
JS		 1414 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1415 h->ae_algo->ops->enable_vlan_filter) {
1731be4c
YL		 1416 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1417 h->ae_algo->ops->enable_vlan_filter(h, enable);
181d454b 1418 }
391b5e93 1419
bd368416
JS		 1420 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1421 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 1422 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1423 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 1424 if (ret)
1425 return ret;
1426 }
1427
c17852a8 1428 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 1429 enable = !!(features & NETIF_F_NTUPLE);
1430 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 1431 }
1432
76ad4f0e
S		 1433 netdev->features = features;
1434 return 0;
1435}
1436
6c88d9d7
PL		 1437static void hns3_nic_get_stats64(struct net_device *netdev,
1438 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1439{
1440 struct hns3_nic_priv *priv = netdev_priv(netdev);
1441 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1442 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1443 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 1444 u64 rx_length_errors = 0;
1445 u64 rx_crc_errors = 0;
1446 u64 rx_multicast = 0;
76ad4f0e 1447 unsigned int start;
d3ec4ef6
JS		 1448 u64 tx_errors = 0;
1449 u64 rx_errors = 0;
76ad4f0e
S		 1450 unsigned int idx;
1451 u64 tx_bytes = 0;
1452 u64 rx_bytes = 0;
1453 u64 tx_pkts = 0;
1454 u64 rx_pkts = 0;
d2a5dca8
JS		 1455 u64 tx_drop = 0;
1456 u64 rx_drop = 0;
76ad4f0e 1457
b875cc37
JS		 1458 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1459 return;
1460
c5f65480
JS		 1461 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1462
76ad4f0e
S		 1463 for (idx = 0; idx < queue_num; idx++) {
1464 /* fetch the tx stats */
1465 ring = priv->ring_data[idx].ring;
1466 do {
d36d36ce 1467 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1468 tx_bytes += ring->stats.tx_bytes;
1469 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1470 tx_drop += ring->stats.sw_err_cnt;
d3ec4ef6 1471 tx_errors += ring->stats.sw_err_cnt;
76ad4f0e
S		 1472 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1473
1474 /* fetch the rx stats */
1475 ring = priv->ring_data[idx + queue_num].ring;
1476 do {
d36d36ce 1477 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1478 rx_bytes += ring->stats.rx_bytes;
1479 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1480 rx_drop += ring->stats.non_vld_descs;
d2a5dca8 1481 rx_drop += ring->stats.l2_err;
d3ec4ef6
JS		 1482 rx_errors += ring->stats.non_vld_descs;
1483 rx_errors += ring->stats.l2_err;
1484 rx_crc_errors += ring->stats.l2_err;
1485 rx_crc_errors += ring->stats.l3l4_csum_err;
1486 rx_multicast += ring->stats.rx_multicast;
1487 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 1488 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1489 }
1490
1491 stats->tx_bytes = tx_bytes;
1492 stats->tx_packets = tx_pkts;
1493 stats->rx_bytes = rx_bytes;
1494 stats->rx_packets = rx_pkts;
1495
d3ec4ef6
JS		 1496 stats->rx_errors = rx_errors;
1497 stats->multicast = rx_multicast;
1498 stats->rx_length_errors = rx_length_errors;
1499 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 1500 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1501
d3ec4ef6
JS		 1502 stats->tx_errors = tx_errors;
1503 stats->rx_dropped = rx_drop;
1504 stats->tx_dropped = tx_drop;
76ad4f0e
S		 1505 stats->collisions = netdev->stats.collisions;
1506 stats->rx_over_errors = netdev->stats.rx_over_errors;
1507 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1508 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1509 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1510 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1511 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1512 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1513 stats->tx_window_errors = netdev->stats.tx_window_errors;
1514 stats->rx_compressed = netdev->stats.rx_compressed;
1515 stats->tx_compressed = netdev->stats.tx_compressed;
1516}
1517
30d240df 1518static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1519{
30d240df 1520 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1521 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1522 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1523 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1524 u8 tc = mqprio_qopt->qopt.num_tc;
1525 u16 mode = mqprio_qopt->mode;
1526 u8 hw = mqprio_qopt->qopt.hw;
76ad4f0e 1527
30d240df
YL		 1528 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1529 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1530 return -EOPNOTSUPP;
1531
76ad4f0e
S		 1532 if (tc > HNAE3_MAX_TC)
1533 return -EINVAL;
1534
76ad4f0e
S		 1535 if (!netdev)
1536 return -EINVAL;
1537
1cce5eb6 1538 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
30d240df 1539 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e
S		 1540}
1541
2572ac53 1542static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1543 void *type_data)
76ad4f0e 1544{
575ed7d3 1545 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1546 return -EOPNOTSUPP;
76ad4f0e 1547
30d240df 1548 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1549}
1550
1551static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1552 __be16 proto, u16 vid)
1553{
9780cb97 1554 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1555 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1556 int ret = -EIO;
1557
1558 if (h->ae_algo->ops->set_vlan_filter)
1559 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1560
681ec399
YL		 1561 if (!ret)
1562 set_bit(vid, priv->active_vlans);
1563
76ad4f0e
S		 1564 return ret;
1565}
1566
1567static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1568 __be16 proto, u16 vid)
1569{
9780cb97 1570 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1571 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1572 int ret = -EIO;
1573
1574 if (h->ae_algo->ops->set_vlan_filter)
1575 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1576
681ec399
YL		 1577 if (!ret)
1578 clear_bit(vid, priv->active_vlans);
1579
76ad4f0e
S		 1580 return ret;
1581}
1582
7fa6be4f 1583static int hns3_restore_vlan(struct net_device *netdev)
681ec399
YL		 1584{
1585 struct hns3_nic_priv *priv = netdev_priv(netdev);
7fa6be4f 1586 int ret = 0;
681ec399 1587 u16 vid;
681ec399
YL		 1588
1589 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1590 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
7fa6be4f
HT		 1591 if (ret) {
1592 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1593 vid, ret);
1594 return ret;
1595 }
681ec399 1596 }
7fa6be4f
HT		 1597
1598 return ret;
681ec399
YL		 1599}
1600
76ad4f0e
S		 1601static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1602 u8 qos, __be16 vlan_proto)
1603{
9780cb97 1604 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1605 int ret = -EIO;
1606
1607 if (h->ae_algo->ops->set_vf_vlan_filter)
1608 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1609 qos, vlan_proto);
1610
1611 return ret;
1612}
1613
a8e8b7ff
S		 1614static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1615{
9780cb97 1616 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1617 int ret;
1618
6ff7ed80
HT		 1619 if (hns3_nic_resetting(netdev))
1620 return -EBUSY;
1621
a8e8b7ff
S		 1622 if (!h->ae_algo->ops->set_mtu)
1623 return -EOPNOTSUPP;
1624
a8e8b7ff 1625 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1626 if (ret)
a8e8b7ff
S		 1627 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1628 ret);
93d8daf4
YL		 1629 else
1630 netdev->mtu = new_mtu;
5bad95a1 1631
a8e8b7ff
S		 1632 return ret;
1633}
1634
f8fa222c
L		 1635static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1636{
1637 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1638 struct hnae3_handle *h = hns3_get_handle(ndev);
f8fa222c 1639 struct hns3_enet_ring *tx_ring = NULL;
e511c97d 1640 struct napi_struct *napi;
f8fa222c
L		 1641 int timeout_queue = 0;
1642 int hw_head, hw_tail;
e511c97d
JS		 1643 int fbd_num, fbd_oft;
1644 int ebd_num, ebd_oft;
1645 int bd_num, bd_err;
1646 int ring_en, tc;
f8fa222c
L		 1647 int i;
1648
1649 /* Find the stopped queue the same way the stack does */
fa6c4084 1650 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 1651 struct netdev_queue *q;
1652 unsigned long trans_start;
1653
1654 q = netdev_get_tx_queue(ndev, i);
1655 trans_start = q->trans_start;
1656 if (netif_xmit_stopped(q) &&
1657 time_after(jiffies,
1658 (trans_start + ndev->watchdog_timeo))) {
1659 timeout_queue = i;
1660 break;
1661 }
1662 }
1663
1664 if (i == ndev->num_tx_queues) {
1665 netdev_info(ndev,
1666 "no netdev TX timeout queue found, timeout count: %llu\n",
1667 priv->tx_timeout_count);
1668 return false;
1669 }
1670
beab694a
JS		 1671 priv->tx_timeout_count++;
1672
f8fa222c 1673 tx_ring = priv->ring_data[timeout_queue].ring;
e511c97d
JS		 1674 napi = &tx_ring->tqp_vector->napi;
1675
1676 netdev_info(ndev,
1677 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1678 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1679 tx_ring->next_to_clean, napi->state);
1680
1681 netdev_info(ndev,
1682 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1683 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1684 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1685
1686 netdev_info(ndev,
1687 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1688 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1689 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1690
1691 /* When mac received many pause frames continuous, it's unable to send
1692 * packets, which may cause tx timeout
1693 */
1694 if (h->ae_algo->ops->update_stats &&
1695 h->ae_algo->ops->get_mac_pause_stats) {
1696 u64 tx_pause_cnt, rx_pause_cnt;
1697
1698 h->ae_algo->ops->update_stats(h, &ndev->stats);
1699 h->ae_algo->ops->get_mac_pause_stats(h, &tx_pause_cnt,
1700 &rx_pause_cnt);
1701 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1702 tx_pause_cnt, rx_pause_cnt);
1703 }
f8fa222c
L		 1704
1705 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1706 HNS3_RING_TX_RING_HEAD_REG);
1707 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1708 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 1709 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1710 HNS3_RING_TX_RING_FBDNUM_REG);
1711 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1712 HNS3_RING_TX_RING_OFFSET_REG);
1713 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1714 HNS3_RING_TX_RING_EBDNUM_REG);
1715 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1716 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1717 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1718 HNS3_RING_TX_RING_BD_NUM_REG);
1719 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1720 HNS3_RING_TX_RING_BD_ERR_REG);
1721 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1722 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1723
f8fa222c 1724 netdev_info(ndev,
e511c97d
JS		 1725 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1726 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 1727 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 1728 netdev_info(ndev,
1729 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1730 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 1731
1732 return true;
1733}
1734
1735static void hns3_nic_net_timeout(struct net_device *ndev)
1736{
1737 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1738 struct hnae3_handle *h = priv->ae_handle;
1739
1740 if (!hns3_get_tx_timeo_queue_info(ndev))
1741 return;
1742
0742ed7c
HT		 1743 /* request the reset, and let the hclge to determine
1744 * which reset level should be done
1745 */
f8fa222c 1746 if (h->ae_algo->ops->reset_event)
6ae4e733 1747 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1748}
1749
76ad4f0e
S		 1750static const struct net_device_ops hns3_nic_netdev_ops = {
1751 .ndo_open = hns3_nic_net_open,
1752 .ndo_stop = hns3_nic_net_stop,
1753 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1754 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1755 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1756 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1757 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1758 .ndo_set_features = hns3_nic_set_features,
1759 .ndo_get_stats64 = hns3_nic_get_stats64,
1760 .ndo_setup_tc = hns3_nic_setup_tc,
1761 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1762 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1763 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1764 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1765};
1766
97afd47b 1767bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 1768{
1769 u32 dev_id = pdev->device;
1770
1771 switch (dev_id) {
1772 case HNAE3_DEV_ID_GE:
1773 case HNAE3_DEV_ID_25GE:
1774 case HNAE3_DEV_ID_25GE_RDMA:
1775 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1776 case HNAE3_DEV_ID_50GE_RDMA:
1777 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1778 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1779 return true;
1780 case HNAE3_DEV_ID_100G_VF:
1781 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1782 return false;
1783 default:
1784 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1785 dev_id);
1786 }
1787
1788 return false;
1789}
1790
2312e050
FL		 1791static void hns3_disable_sriov(struct pci_dev *pdev)
1792{
1793 /* If our VFs are assigned we cannot shut down SR-IOV
1794 * without causing issues, so just leave the hardware
1795 * available but disabled
1796 */
1797 if (pci_vfs_assigned(pdev)) {
1798 dev_warn(&pdev->dev,
1799 "disabling driver while VFs are assigned\n");
1800 return;
1801 }
1802
1803 pci_disable_sriov(pdev);
1804}
1805
d695964d
JS		 1806static void hns3_get_dev_capability(struct pci_dev *pdev,
1807 struct hnae3_ae_dev *ae_dev)
1808{
b26a6fea 1809 if (pdev->revision >= 0x21) {
d695964d 1810 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL		 1811 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1812 }
d695964d
JS		 1813}
1814
76ad4f0e
S		 1815/* hns3_probe - Device initialization routine
1816 * @pdev: PCI device information struct
1817 * @ent: entry in hns3_pci_tbl
1818 *
1819 * hns3_probe initializes a PF identified by a pci_dev structure.
1820 * The OS initialization, configuring of the PF private structure,
1821 * and a hardware reset occur.
1822 *
1823 * Returns 0 on success, negative on failure
1824 */
1825static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1826{
1827 struct hnae3_ae_dev *ae_dev;
1828 int ret;
1829
1830 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1831 GFP_KERNEL);
1832 if (!ae_dev) {
1833 ret = -ENOMEM;
1834 return ret;
1835 }
1836
1837 ae_dev->pdev = pdev;
e92a0843 1838 ae_dev->flag = ent->driver_data;
76ad4f0e 1839 ae_dev->dev_type = HNAE3_DEV_KNIC;
6871af29 1840 ae_dev->reset_type = HNAE3_NONE_RESET;
d695964d 1841 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 1842 pci_set_drvdata(pdev, ae_dev);
1843
74354140
HT		 1844 ret = hnae3_register_ae_dev(ae_dev);
1845 if (ret) {
1846 devm_kfree(&pdev->dev, ae_dev);
1847 pci_set_drvdata(pdev, NULL);
1848 }
2312e050 1849
74354140 1850 return ret;
76ad4f0e
S		 1851}
1852
1853/* hns3_remove - Device removal routine
1854 * @pdev: PCI device information struct
1855 */
1856static void hns3_remove(struct pci_dev *pdev)
1857{
1858 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1859
2312e050
FL		 1860 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1861 hns3_disable_sriov(pdev);
1862
76ad4f0e 1863 hnae3_unregister_ae_dev(ae_dev);
ac864c23 1864 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 1865}
1866
fa8d82e8
PL		 1867/**
1868 * hns3_pci_sriov_configure
1869 * @pdev: pointer to a pci_dev structure
1870 * @num_vfs: number of VFs to allocate
1871 *
1872 * Enable or change the number of VFs. Called when the user updates the number
1873 * of VFs in sysfs.
1874 **/
743e1a84 1875static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 1876{
1877 int ret;
1878
1879 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1880 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1881 return -EINVAL;
1882 }
1883
1884 if (num_vfs) {
1885 ret = pci_enable_sriov(pdev, num_vfs);
1886 if (ret)
1887 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 1888 else
1889 return num_vfs;
fa8d82e8
PL		 1890 } else if (!pci_vfs_assigned(pdev)) {
1891 pci_disable_sriov(pdev);
1892 } else {
1893 dev_warn(&pdev->dev,
1894 "Unable to free VFs because some are assigned to VMs.\n");
1895 }
1896
1897 return 0;
1898}
1899
ce2c1d2e
YL		 1900static void hns3_shutdown(struct pci_dev *pdev)
1901{
1902 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1903
1904 hnae3_unregister_ae_dev(ae_dev);
1905 devm_kfree(&pdev->dev, ae_dev);
1906 pci_set_drvdata(pdev, NULL);
1907
1908 if (system_state == SYSTEM_POWER_OFF)
1909 pci_set_power_state(pdev, PCI_D3hot);
1910}
1911
5a9f0eac
SJ		 1912static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1913 pci_channel_state_t state)
1914{
1915 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1916 pci_ers_result_t ret;
1917
1918 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1919
1920 if (state == pci_channel_io_perm_failure)
1921 return PCI_ERS_RESULT_DISCONNECT;
1922
1923 if (!ae_dev) {
1924 dev_err(&pdev->dev,
1925 "Can't recover - error happened during device init\n");
1926 return PCI_ERS_RESULT_NONE;
1927 }
1928
381c356e
SJ		 1929 if (ae_dev->ops->handle_hw_ras_error)
1930 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 1931 else
1932 return PCI_ERS_RESULT_NONE;
1933
1934 return ret;
1935}
1936
6ae4e733
SJ		 1937static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1938{
1939 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1940 struct device *dev = &pdev->dev;
1941
1942 dev_info(dev, "requesting reset due to PCI error\n");
1943
1944 /* request the reset */
1945 if (ae_dev->ops->reset_event) {
69b51bbb
SJ		 1946 if (!ae_dev->override_pci_need_reset)
1947 ae_dev->ops->reset_event(pdev, NULL);
1948
6ae4e733
SJ		 1949 return PCI_ERS_RESULT_RECOVERED;
1950 }
1951
1952 return PCI_ERS_RESULT_DISCONNECT;
1953}
1954
6b9a97ee
HT		 1955static void hns3_reset_prepare(struct pci_dev *pdev)
1956{
1957 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1958
1959 dev_info(&pdev->dev, "hns3 flr prepare\n");
1960 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1961 ae_dev->ops->flr_prepare(ae_dev);
1962}
1963
1964static void hns3_reset_done(struct pci_dev *pdev)
1965{
1966 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1967
1968 dev_info(&pdev->dev, "hns3 flr done\n");
1969 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1970 ae_dev->ops->flr_done(ae_dev);
1971}
1972
5a9f0eac
SJ		 1973static const struct pci_error_handlers hns3_err_handler = {
1974 .error_detected = hns3_error_detected,
6ae4e733 1975 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 1976 .reset_prepare = hns3_reset_prepare,
1977 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 1978};
1979
76ad4f0e
S		 1980static struct pci_driver hns3_driver = {
1981 .name = hns3_driver_name,
1982 .id_table = hns3_pci_tbl,
1983 .probe = hns3_probe,
1984 .remove = hns3_remove,
ce2c1d2e 1985 .shutdown = hns3_shutdown,
fa8d82e8 1986 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 1987 .err_handler = &hns3_err_handler,
76ad4f0e
S		 1988};
1989
1990/* set default feature to hns3 */
1991static void hns3_set_default_feature(struct net_device *netdev)
1992{
3e85af6a
PL		 1993 struct hnae3_handle *h = hns3_get_handle(netdev);
1994 struct pci_dev *pdev = h->pdev;
1995
76ad4f0e
S		 1996 netdev->priv_flags |= IFF_UNICAST_FLT;
1997
1998 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1999 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2000 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2001 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2002 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 2003
2004 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
2005
2006 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2007
2008 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2009 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2010 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2011 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2012 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2013 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2014 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 2015
2016 netdev->vlan_features |=
2017 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2018 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2019 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2020 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2021 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 2022
2023 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 2024 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2025 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2026 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2027 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2028 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
3e85af6a 2029
c17852a8 2030 if (pdev->revision >= 0x21) {
77af09c6 2031 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2032 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 2033
2034 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2035 netdev->hw_features |= NETIF_F_NTUPLE;
2036 netdev->features |= NETIF_F_NTUPLE;
2037 }
2038 }
76ad4f0e
S		 2039}
2040
2041static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2042 struct hns3_desc_cb *cb)
2043{
e4e87715 2044 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 2045 struct page *p;
2046
2047 p = dev_alloc_pages(order);
2048 if (!p)
2049 return -ENOMEM;
2050
2051 cb->priv = p;
2052 cb->page_offset = 0;
2053 cb->reuse_flag = 0;
2054 cb->buf = page_address(p);
e4e87715 2055 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 2056 cb->type = DESC_TYPE_PAGE;
2057
76ad4f0e
S		 2058 return 0;
2059}
2060
2061static void hns3_free_buffer(struct hns3_enet_ring *ring,
2062 struct hns3_desc_cb *cb)
2063{
2064 if (cb->type == DESC_TYPE_SKB)
2065 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2066 else if (!HNAE3_IS_TX_RING(ring))
2067 put_page((struct page *)cb->priv);
2068 memset(cb, 0, sizeof(*cb));
2069}
2070
2071static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2072{
2073 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2074 cb->length, ring_to_dma_dir(ring));
2075
2211f4e1 2076 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 2077 return -EIO;
2078
2079 return 0;
2080}
2081
2082static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2083 struct hns3_desc_cb *cb)
2084{
2085 if (cb->type == DESC_TYPE_SKB)
2086 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2087 ring_to_dma_dir(ring));
bcdb12b7 2088 else if (cb->length)
76ad4f0e
S		 2089 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2090 ring_to_dma_dir(ring));
2091}
2092
2093static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2094{
2095 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2096 ring->desc[i].addr = 0;
2097}
2098
2099static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2100{
2101 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2102
2103 if (!ring->desc_cb[i].dma)
2104 return;
2105
2106 hns3_buffer_detach(ring, i);
2107 hns3_free_buffer(ring, cb);
2108}
2109
2110static void hns3_free_buffers(struct hns3_enet_ring *ring)
2111{
2112 int i;
2113
2114 for (i = 0; i < ring->desc_num; i++)
2115 hns3_free_buffer_detach(ring, i);
2116}
2117
2118/* free desc along with its attached buffer */
2119static void hns3_free_desc(struct hns3_enet_ring *ring)
2120{
024cc792
HT		 2121 int size = ring->desc_num * sizeof(ring->desc[0]);
2122
76ad4f0e
S		 2123 hns3_free_buffers(ring);
2124
024cc792
HT		 2125 if (ring->desc) {
2126 dma_free_coherent(ring_to_dev(ring), size,
2127 ring->desc, ring->desc_dma_addr);
2128 ring->desc = NULL;
2129 }
76ad4f0e
S		 2130}
2131
2132static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2133{
2134 int size = ring->desc_num * sizeof(ring->desc[0]);
2135
750afb08
LC		 2136 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2137 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 2138 if (!ring->desc)
2139 return -ENOMEM;
2140
76ad4f0e
S		 2141 return 0;
2142}
2143
2144static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2145 struct hns3_desc_cb *cb)
2146{
2147 int ret;
2148
2149 ret = hns3_alloc_buffer(ring, cb);
2150 if (ret)
2151 goto out;
2152
2153 ret = hns3_map_buffer(ring, cb);
2154 if (ret)
2155 goto out_with_buf;
2156
2157 return 0;
2158
2159out_with_buf:
564883bb 2160 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2161out:
2162 return ret;
2163}
2164
2165static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2166{
2167 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2168
2169 if (ret)
2170 return ret;
2171
2172 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2173
2174 return 0;
2175}
2176
2177/* Allocate memory for raw pkg, and map with dma */
2178static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2179{
2180 int i, j, ret;
2181
2182 for (i = 0; i < ring->desc_num; i++) {
2183 ret = hns3_alloc_buffer_attach(ring, i);
2184 if (ret)
2185 goto out_buffer_fail;
2186 }
2187
2188 return 0;
2189
2190out_buffer_fail:
2191 for (j = i - 1; j >= 0; j--)
2192 hns3_free_buffer_detach(ring, j);
2193 return ret;
2194}
2195
2196/* detach a in-used buffer and replace with a reserved one */
2197static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2198 struct hns3_desc_cb *res_cb)
2199{
b9077428 2200 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2201 ring->desc_cb[i] = *res_cb;
2202 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2203 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2204}
2205
2206static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2207{
2208 ring->desc_cb[i].reuse_flag = 0;
2209 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2210 + ring->desc_cb[i].page_offset);
7d0b130c 2211 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2212}
2213
2214static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
2215 int *pkts)
2216{
2217 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2218
2219 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2220 (*bytes) += desc_cb->length;
e4e87715 2221 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
76ad4f0e
S		 2222 hns3_free_buffer_detach(ring, ring->next_to_clean);
2223
2224 ring_ptr_move_fw(ring, next_to_clean);
2225}
2226
2227static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2228{
2229 int u = ring->next_to_use;
2230 int c = ring->next_to_clean;
2231
2232 if (unlikely(h > ring->desc_num))
2233 return 0;
2234
2235 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2236}
2237
799997a3 2238void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 2239{
2240 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
7a810110 2241 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2242 struct netdev_queue *dev_queue;
2243 int bytes, pkts;
2244 int head;
2245
2246 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2247 rmb(); /* Make sure head is ready before touch any data */
2248
2249 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2250 return; /* no data to poll */
76ad4f0e 2251
0e6084aa 2252 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 2253 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2254 ring->next_to_use, ring->next_to_clean);
2255
2256 u64_stats_update_begin(&ring->syncp);
2257 ring->stats.io_err_cnt++;
2258 u64_stats_update_end(&ring->syncp);
799997a3 2259 return;
76ad4f0e
S		 2260 }
2261
2262 bytes = 0;
2263 pkts = 0;
799997a3 2264 while (head != ring->next_to_clean) {
76ad4f0e
S		 2265 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
2266 /* Issue prefetch for next Tx descriptor */
2267 prefetch(&ring->desc_cb[ring->next_to_clean]);
76ad4f0e
S		 2268 }
2269
2270 ring->tqp_vector->tx_group.total_bytes += bytes;
2271 ring->tqp_vector->tx_group.total_packets += pkts;
2272
2273 u64_stats_update_begin(&ring->syncp);
2274 ring->stats.tx_bytes += bytes;
2275 ring->stats.tx_pkts += pkts;
2276 u64_stats_update_end(&ring->syncp);
2277
2278 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2279 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2280
2281 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2282 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2283 /* Make sure that anybody stopping the queue after this
2284 * sees the new next_to_clean.
2285 */
2286 smp_mb();
7a810110
JS		 2287 if (netif_tx_queue_stopped(dev_queue) &&
2288 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2289 netif_tx_wake_queue(dev_queue);
2290 ring->stats.restart_queue++;
2291 }
2292 }
76ad4f0e
S		 2293}
2294
2295static int hns3_desc_unused(struct hns3_enet_ring *ring)
2296{
2297 int ntc = ring->next_to_clean;
2298 int ntu = ring->next_to_use;
2299
2300 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2301}
2302
2303static void
2304hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2305{
2306 struct hns3_desc_cb *desc_cb;
2307 struct hns3_desc_cb res_cbs;
2308 int i, ret;
2309
2310 for (i = 0; i < cleand_count; i++) {
2311 desc_cb = &ring->desc_cb[ring->next_to_use];
2312 if (desc_cb->reuse_flag) {
2313 u64_stats_update_begin(&ring->syncp);
2314 ring->stats.reuse_pg_cnt++;
2315 u64_stats_update_end(&ring->syncp);
2316
2317 hns3_reuse_buffer(ring, ring->next_to_use);
2318 } else {
2319 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2320 if (ret) {
2321 u64_stats_update_begin(&ring->syncp);
2322 ring->stats.sw_err_cnt++;
2323 u64_stats_update_end(&ring->syncp);
2324
2325 netdev_err(ring->tqp->handle->kinfo.netdev,
2326 "hnae reserve buffer map failed.\n");
2327 break;
2328 }
2329 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2330 }
2331
2332 ring_ptr_move_fw(ring, next_to_use);
2333 }
2334
2335 wmb(); /* Make all data has been write before submit */
2336 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2337}
2338
76ad4f0e
S		 2339static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2340 struct hns3_enet_ring *ring, int pull_len,
2341 struct hns3_desc_cb *desc_cb)
2342{
2343 struct hns3_desc *desc;
583e7281
HT		 2344 u32 truesize;
2345 int size;
76ad4f0e
S		 2346 int last_offset;
2347 bool twobufs;
2348
2349 twobufs = ((PAGE_SIZE < 8192) &&
e4e87715 2350 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
76ad4f0e
S		 2351
2352 desc = &ring->desc[ring->next_to_clean];
2353 size = le16_to_cpu(desc->rx.size);
2354
e4e87715 2355 truesize = hnae3_buf_size(ring);
f8d291f0
PL		 2356
2357 if (!twobufs)
e4e87715 2358 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
76ad4f0e
S		 2359
2360 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2361 size - pull_len, truesize);
76ad4f0e
S		 2362
2363 /* Avoid re-using remote pages,flag default unreuse */
2364 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2365 return;
2366
2367 if (twobufs) {
2368 /* If we are only owner of page we can reuse it */
2369 if (likely(page_count(desc_cb->priv) == 1)) {
2370 /* Flip page offset to other buffer */
2371 desc_cb->page_offset ^= truesize;
2372
2373 desc_cb->reuse_flag = 1;
2374 /* bump ref count on page before it is given*/
2375 get_page(desc_cb->priv);
2376 }
2377 return;
2378 }
2379
2380 /* Move offset up to the next cache line */
2381 desc_cb->page_offset += truesize;
2382
2383 if (desc_cb->page_offset <= last_offset) {
2384 desc_cb->reuse_flag = 1;
2385 /* Bump ref count on page before it is given*/
2386 get_page(desc_cb->priv);
2387 }
2388}
2389
d474d88f
YL		 2390static int hns3_gro_complete(struct sk_buff *skb)
2391{
2392 __be16 type = skb->protocol;
2393 struct tcphdr *th;
2394 int depth = 0;
2395
2396 while (type == htons(ETH_P_8021Q)) {
2397 struct vlan_hdr *vh;
2398
2399 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2400 return -EFAULT;
2401
2402 vh = (struct vlan_hdr *)(skb->data + depth);
2403 type = vh->h_vlan_encapsulated_proto;
2404 depth += VLAN_HLEN;
2405 }
2406
2407 if (type == htons(ETH_P_IP)) {
2408 depth += sizeof(struct iphdr);
2409 } else if (type == htons(ETH_P_IPV6)) {
2410 depth += sizeof(struct ipv6hdr);
2411 } else {
2412 netdev_err(skb->dev,
2413 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2414 be16_to_cpu(type), depth);
2415 return -EFAULT;
2416 }
2417
2418 th = (struct tcphdr *)(skb->data + depth);
2419 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2420 if (th->cwr)
2421 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2422
2423 skb->ip_summed = CHECKSUM_UNNECESSARY;
2424
2425 return 0;
2426}
2427
76ad4f0e 2428static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
a4d2cdcb 2429 u32 l234info, u32 bd_base_info)
76ad4f0e
S		 2430{
2431 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2432 int l3_type, l4_type;
76ad4f0e 2433 int ol4_type;
76ad4f0e
S		 2434
2435 skb->ip_summed = CHECKSUM_NONE;
2436
2437 skb_checksum_none_assert(skb);
2438
2439 if (!(netdev->features & NETIF_F_RXCSUM))
2440 return;
2441
2442 /* check if hardware has done checksum */
e8149933 2443 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S		 2444 return;
2445
f4772dee
DC		 2446 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2447 BIT(HNS3_RXD_OL3E_B) |
e8149933 2448 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S		 2449 u64_stats_update_begin(&ring->syncp);
2450 ring->stats.l3l4_csum_err++;
2451 u64_stats_update_end(&ring->syncp);
2452
2453 return;
2454 }
2455
e4e87715
PL		 2456 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2457 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2458 switch (ol4_type) {
2459 case HNS3_OL4_TYPE_MAC_IN_UDP:
2460 case HNS3_OL4_TYPE_NVGRE:
2461 skb->csum_level = 1;
be44b3af 2462 /* fall through */
76ad4f0e 2463 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 2464 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2465 HNS3_RXD_L3ID_S);
2466 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2467 HNS3_RXD_L4ID_S);
2468
76ad4f0e 2469 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2470 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2471 l3_type == HNS3_L3_TYPE_IPV6) &&
2472 (l4_type == HNS3_L4_TYPE_UDP ||
2473 l4_type == HNS3_L4_TYPE_TCP ||
2474 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2475 skb->ip_summed = CHECKSUM_UNNECESSARY;
2476 break;
fa7a4bd5
JS		 2477 default:
2478 break;
76ad4f0e
S		 2479 }
2480}
2481
d43e5aca
YL		 2482static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2483{
81ae0e04
PL		 2484 if (skb_has_frag_list(skb))
2485 napi_gro_flush(&ring->tqp_vector->napi, false);
2486
d43e5aca
YL		 2487 napi_gro_receive(&ring->tqp_vector->napi, skb);
2488}
2489
701a6d6a
JS		 2490static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2491 struct hns3_desc *desc, u32 l234info,
2492 u16 *vlan_tag)
5b5455a9 2493{
44e626f7 2494 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 2495 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL		 2496
2497 if (pdev->revision == 0x20) {
701a6d6a
JS		 2498 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2499 if (!(*vlan_tag & VLAN_VID_MASK))
2500 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2501
701a6d6a 2502 return (*vlan_tag != 0);
5b5455a9
PL		 2503 }
2504
2505#define HNS3_STRP_OUTER_VLAN 0x1
2506#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 2507#define HNS3_STRP_BOTH 0x3
5b5455a9 2508
44e626f7
JS		 2509 /* Hardware always insert VLAN tag into RX descriptor when
2510 * remove the tag from packet, driver needs to determine
2511 * reporting which tag to stack.
2512 */
e4e87715
PL		 2513 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2514 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2515 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 2516 if (handle->port_base_vlan_state !=
2517 HNAE3_PORT_BASE_VLAN_DISABLE)
2518 return false;
2519
701a6d6a
JS		 2520 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2521 return true;
5b5455a9 2522 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 2523 if (handle->port_base_vlan_state !=
2524 HNAE3_PORT_BASE_VLAN_DISABLE)
2525 return false;
2526
701a6d6a 2527 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 2528 return true;
2529 case HNS3_STRP_BOTH:
2530 if (handle->port_base_vlan_state ==
2531 HNAE3_PORT_BASE_VLAN_DISABLE)
2532 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2533 else
2534 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2535
701a6d6a 2536 return true;
5b5455a9 2537 default:
701a6d6a 2538 return false;
5b5455a9 2539 }
5b5455a9
PL		 2540}
2541
e5597095
PL		 2542static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2543 unsigned char *va)
2544{
2545#define HNS3_NEED_ADD_FRAG 1
2546 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2547 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2548 struct sk_buff *skb;
2549
2550 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2551 skb = ring->skb;
2552 if (unlikely(!skb)) {
2553 netdev_err(netdev, "alloc rx skb fail\n");
2554
2555 u64_stats_update_begin(&ring->syncp);
2556 ring->stats.sw_err_cnt++;
2557 u64_stats_update_end(&ring->syncp);
2558
2559 return -ENOMEM;
2560 }
2561
2562 prefetchw(skb->data);
2563
2564 ring->pending_buf = 1;
81ae0e04
PL		 2565 ring->frag_num = 0;
2566 ring->tail_skb = NULL;
e5597095
PL		 2567 if (length <= HNS3_RX_HEAD_SIZE) {
2568 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2569
2570 /* We can reuse buffer as-is, just make sure it is local */
2571 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2572 desc_cb->reuse_flag = 1;
2573 else /* This page cannot be reused so discard it */
2574 put_page(desc_cb->priv);
2575
2576 ring_ptr_move_fw(ring, next_to_clean);
2577 return 0;
2578 }
2579 u64_stats_update_begin(&ring->syncp);
2580 ring->stats.seg_pkt_cnt++;
2581 u64_stats_update_end(&ring->syncp);
2582
2583 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2584 __skb_put(skb, ring->pull_len);
81ae0e04 2585 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL		 2586 desc_cb);
2587 ring_ptr_move_fw(ring, next_to_clean);
2588
2589 return HNS3_NEED_ADD_FRAG;
2590}
2591
2592static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2593 struct sk_buff **out_skb, bool pending)
2594{
2595 struct sk_buff *skb = *out_skb;
81ae0e04
PL		 2596 struct sk_buff *head_skb = *out_skb;
2597 struct sk_buff *new_skb;
e5597095
PL		 2598 struct hns3_desc_cb *desc_cb;
2599 struct hns3_desc *pre_desc;
2600 u32 bd_base_info;
2601 int pre_bd;
2602
2603 /* if there is pending bd, the SW param next_to_clean has moved
2604 * to next and the next is NULL
2605 */
2606 if (pending) {
2607 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2608 ring->desc_num;
2609 pre_desc = &ring->desc[pre_bd];
2610 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2611 } else {
2612 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2613 }
2614
e8149933 2615 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
e5597095
PL		 2616 desc = &ring->desc[ring->next_to_clean];
2617 desc_cb = &ring->desc_cb[ring->next_to_clean];
2618 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 2619 /* make sure HW write desc complete */
2620 dma_rmb();
e8149933 2621 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 2622 return -ENXIO;
2623
81ae0e04
PL		 2624 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2625 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2626 HNS3_RX_HEAD_SIZE);
2627 if (unlikely(!new_skb)) {
2628 netdev_err(ring->tqp->handle->kinfo.netdev,
2629 "alloc rx skb frag fail\n");
2630 return -ENXIO;
2631 }
2632 ring->frag_num = 0;
2633
2634 if (ring->tail_skb) {
2635 ring->tail_skb->next = new_skb;
2636 ring->tail_skb = new_skb;
2637 } else {
2638 skb_shinfo(skb)->frag_list = new_skb;
2639 ring->tail_skb = new_skb;
2640 }
2641 }
2642
2643 if (ring->tail_skb) {
2644 head_skb->truesize += hnae3_buf_size(ring);
2645 head_skb->data_len += le16_to_cpu(desc->rx.size);
2646 head_skb->len += le16_to_cpu(desc->rx.size);
2647 skb = ring->tail_skb;
2648 }
2649
2650 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
e5597095
PL		 2651 ring_ptr_move_fw(ring, next_to_clean);
2652 ring->pending_buf++;
2653 }
2654
2655 return 0;
2656}
2657
d474d88f
YL		 2658static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2659 struct sk_buff *skb, u32 l234info,
2660 u32 bd_base_info)
a6d53b97
PL		 2661{
2662 u16 gro_count;
2663 u32 l3_type;
2664
2665 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2666 HNS3_RXD_GRO_COUNT_S);
2667 /* if there is no HW GRO, do not set gro params */
d474d88f
YL		 2668 if (!gro_count) {
2669 hns3_rx_checksum(ring, skb, l234info, bd_base_info);
2670 return 0;
2671 }
a6d53b97 2672
a6d53b97
PL		 2673 NAPI_GRO_CB(skb)->count = gro_count;
2674
2675 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2676 HNS3_RXD_L3ID_S);
2677 if (l3_type == HNS3_L3_TYPE_IPV4)
2678 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2679 else if (l3_type == HNS3_L3_TYPE_IPV6)
2680 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2681 else
d474d88f 2682 return -EFAULT;
a6d53b97
PL		 2683
2684 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2685 HNS3_RXD_GRO_SIZE_M,
2686 HNS3_RXD_GRO_SIZE_S);
d474d88f
YL		 2687
2688 return hns3_gro_complete(skb);
a6d53b97
PL		 2689}
2690
232fc64b
PL		 2691static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2692 struct sk_buff *skb)
2693{
232fc64b
PL		 2694 struct hnae3_handle *handle = ring->tqp->handle;
2695 enum pkt_hash_types rss_type;
31a16f99
PL		 2696 struct hns3_desc *desc;
2697 int last_bd;
2698
2699 /* When driver handle the rss type, ring->next_to_clean indicates the
2700 * first descriptor of next packet, need -1 here.
2701 */
2702 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num;
2703 desc = &ring->desc[last_bd];
232fc64b
PL		 2704
2705 if (le32_to_cpu(desc->rx.rss_hash))
2706 rss_type = handle->kinfo.rss_type;
2707 else
2708 rss_type = PKT_HASH_TYPE_NONE;
2709
2710 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type);
2711}
2712
d474d88f
YL		 2713static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb,
2714 struct hns3_desc *desc)
76ad4f0e
S		 2715{
2716 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
d474d88f
YL		 2717 u32 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2718 u32 l234info = le32_to_cpu(desc->rx.l234_info);
c376fa1a 2719 enum hns3_pkt_l2t_type l2_frame_type;
d474d88f
YL		 2720 unsigned int len;
2721 int ret;
2722
2723 /* Based on hw strategy, the tag offloaded will be stored at
2724 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2725 * in one layer tag case.
2726 */
2727 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2728 u16 vlan_tag;
2729
2730 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2731 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2732 vlan_tag);
2733 }
2734
2735 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) {
2736 u64_stats_update_begin(&ring->syncp);
2737 ring->stats.non_vld_descs++;
2738 u64_stats_update_end(&ring->syncp);
2739
2740 return -EINVAL;
2741 }
2742
2743 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
2744 BIT(HNS3_RXD_L2E_B))))) {
2745 u64_stats_update_begin(&ring->syncp);
2746 if (l234info & BIT(HNS3_RXD_L2E_B))
2747 ring->stats.l2_err++;
2748 else
2749 ring->stats.err_pkt_len++;
2750 u64_stats_update_end(&ring->syncp);
2751
2752 return -EFAULT;
2753 }
2754
2755 len = skb->len;
2756
2757 /* Do update ip stack process */
2758 skb->protocol = eth_type_trans(skb, netdev);
2759
2760 /* This is needed in order to enable forwarding support */
2761 ret = hns3_set_gro_and_checksum(ring, skb, l234info, bd_base_info);
2762 if (unlikely(ret)) {
2763 u64_stats_update_begin(&ring->syncp);
2764 ring->stats.rx_err_cnt++;
2765 u64_stats_update_end(&ring->syncp);
2766 return ret;
2767 }
2768
2769 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
2770 HNS3_RXD_DMAC_S);
2771
2772 u64_stats_update_begin(&ring->syncp);
2773 ring->stats.rx_pkts++;
2774 ring->stats.rx_bytes += len;
2775
2776 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
2777 ring->stats.rx_multicast++;
2778
2779 u64_stats_update_end(&ring->syncp);
2780
2781 ring->tqp_vector->rx_group.total_bytes += len;
2782 return 0;
2783}
2784
2785static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2786 struct sk_buff **out_skb)
2787{
e5597095 2788 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 2789 struct hns3_desc_cb *desc_cb;
2790 struct hns3_desc *desc;
76ad4f0e 2791 u32 bd_base_info;
76ad4f0e 2792 int length;
e5597095 2793 int ret;
76ad4f0e
S		 2794
2795 desc = &ring->desc[ring->next_to_clean];
2796 desc_cb = &ring->desc_cb[ring->next_to_clean];
2797
2798 prefetch(desc);
2799
846fcc83 2800 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2801 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2802
2803 /* Check valid BD */
e8149933 2804 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
e5597095 2805 return -ENXIO;
76ad4f0e 2806
e5597095
PL		 2807 if (!skb)
2808 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S		 2809
2810 /* Prefetch first cache line of first page
2811 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2812 * line size is 64B so need to prefetch twice to make it 128B. But in
2813 * actual we can have greater size of caches with 128B Level 1 cache
2814 * lines. In such a case, single fetch would suffice to cache in the
2815 * relevant part of the header.
2816 */
e5597095 2817 prefetch(ring->va);
76ad4f0e 2818#if L1_CACHE_BYTES < 128
e5597095 2819 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S		 2820#endif
2821
e5597095
PL		 2822 if (!skb) {
2823 ret = hns3_alloc_skb(ring, length, ring->va);
2824 *out_skb = skb = ring->skb;
76ad4f0e 2825
e5597095
PL		 2826 if (ret < 0) /* alloc buffer fail */
2827 return ret;
2828 if (ret > 0) { /* need add frag */
2829 ret = hns3_add_frag(ring, desc, &skb, false);
2830 if (ret)
2831 return ret;
76ad4f0e 2832
e5597095
PL		 2833 /* As the head data may be changed when GRO enable, copy
2834 * the head data in after other data rx completed
2835 */
2836 memcpy(skb->data, ring->va,
2837 ALIGN(ring->pull_len, sizeof(long)));
2838 }
76ad4f0e 2839 } else {
e5597095
PL		 2840 ret = hns3_add_frag(ring, desc, &skb, true);
2841 if (ret)
2842 return ret;
76ad4f0e 2843
e5597095
PL		 2844 /* As the head data may be changed when GRO enable, copy
2845 * the head data in after other data rx completed
2846 */
2847 memcpy(skb->data, ring->va,
2848 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S		 2849 }
2850
d474d88f
YL		 2851 ret = hns3_handle_bdinfo(ring, skb, desc);
2852 if (unlikely(ret)) {
76ad4f0e 2853 dev_kfree_skb_any(skb);
d474d88f 2854 return ret;
76ad4f0e
S		 2855 }
2856
e5597095 2857 *out_skb = skb;
232fc64b
PL		 2858 hns3_set_rx_skb_rss_type(ring, skb);
2859
76ad4f0e
S		 2860 return 0;
2861}
2862
d43e5aca
YL		 2863int hns3_clean_rx_ring(
2864 struct hns3_enet_ring *ring, int budget,
2865 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2866{
2867#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
76ad4f0e 2868 int recv_pkts, recv_bds, clean_count, err;
e5597095
PL		 2869 int unused_count = hns3_desc_unused(ring) - ring->pending_buf;
2870 struct sk_buff *skb = ring->skb;
2871 int num;
76ad4f0e
S		 2872
2873 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2874 rmb(); /* Make sure num taken effect before the other data is touched */
2875
2876 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2877 num -= unused_count;
2878
2879 while (recv_pkts < budget && recv_bds < num) {
2880 /* Reuse or realloc buffers */
2881 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2882 hns3_nic_alloc_rx_buffers(ring,
2883 clean_count + unused_count);
2884 clean_count = 0;
e5597095
PL		 2885 unused_count = hns3_desc_unused(ring) -
2886 ring->pending_buf;
76ad4f0e
S		 2887 }
2888
2889 /* Poll one pkt */
e5597095 2890 err = hns3_handle_rx_bd(ring, &skb);
76ad4f0e
S		 2891 if (unlikely(!skb)) /* This fault cannot be repaired */
2892 goto out;
2893
e5597095
PL		 2894 if (err == -ENXIO) { /* Do not get FE for the packet */
2895 goto out;
2896 } else if (unlikely(err)) { /* Do jump the err */
2897 recv_bds += ring->pending_buf;
2898 clean_count += ring->pending_buf;
2899 ring->skb = NULL;
2900 ring->pending_buf = 0;
76ad4f0e
S		 2901 continue;
2902 }
2903
d43e5aca 2904 rx_fn(ring, skb);
e5597095
PL		 2905 recv_bds += ring->pending_buf;
2906 clean_count += ring->pending_buf;
2907 ring->skb = NULL;
2908 ring->pending_buf = 0;
76ad4f0e
S		 2909
2910 recv_pkts++;
2911 }
2912
2913out:
2914 /* Make all data has been write before submit */
2915 if (clean_count + unused_count > 0)
2916 hns3_nic_alloc_rx_buffers(ring,
2917 clean_count + unused_count);
2918
2919 return recv_pkts;
2920}
2921
2922static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2923{
a95e1f86
FL		 2924 struct hns3_enet_tqp_vector *tqp_vector =
2925 ring_group->ring->tqp_vector;
76ad4f0e 2926 enum hns3_flow_level_range new_flow_level;
a95e1f86
FL		 2927 int packets_per_msecs;
2928 int bytes_per_msecs;
2929 u32 time_passed_ms;
76ad4f0e 2930 u16 new_int_gl;
76ad4f0e 2931
6241e71e 2932 if (!tqp_vector->last_jiffies)
76ad4f0e
S		 2933 return false;
2934
2935 if (ring_group->total_packets == 0) {
9bc727a9
YL		 2936 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2937 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2938 return true;
2939 }
2940
2941 /* Simple throttlerate management
2942 * 0-10MB/s lower (50000 ints/s)
2943 * 10-20MB/s middle (20000 ints/s)
2944 * 20-1249MB/s high (18000 ints/s)
2945 * > 40000pps ultra (8000 ints/s)
2946 */
9bc727a9
YL		 2947 new_flow_level = ring_group->coal.flow_level;
2948 new_int_gl = ring_group->coal.int_gl;
a95e1f86
FL		 2949 time_passed_ms =
2950 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2951
2952 if (!time_passed_ms)
2953 return false;
2954
2955 do_div(ring_group->total_packets, time_passed_ms);
2956 packets_per_msecs = ring_group->total_packets;
2957
2958 do_div(ring_group->total_bytes, time_passed_ms);
2959 bytes_per_msecs = ring_group->total_bytes;
2960
2961#define HNS3_RX_LOW_BYTE_RATE 10000
2962#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2963
2964 switch (new_flow_level) {
2965 case HNS3_FLOW_LOW:
a95e1f86 2966 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2967 new_flow_level = HNS3_FLOW_MID;
2968 break;
2969 case HNS3_FLOW_MID:
a95e1f86 2970 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2971 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 2972 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2973 new_flow_level = HNS3_FLOW_LOW;
2974 break;
2975 case HNS3_FLOW_HIGH:
2976 case HNS3_FLOW_ULTRA:
2977 default:
a95e1f86 2978 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2979 new_flow_level = HNS3_FLOW_MID;
2980 break;
2981 }
2982
a95e1f86
FL		 2983#define HNS3_RX_ULTRA_PACKET_RATE 40
2984
2985 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2986 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2987 new_flow_level = HNS3_FLOW_ULTRA;
2988
2989 switch (new_flow_level) {
2990 case HNS3_FLOW_LOW:
2991 new_int_gl = HNS3_INT_GL_50K;
2992 break;
2993 case HNS3_FLOW_MID:
2994 new_int_gl = HNS3_INT_GL_20K;
2995 break;
2996 case HNS3_FLOW_HIGH:
2997 new_int_gl = HNS3_INT_GL_18K;
2998 break;
2999 case HNS3_FLOW_ULTRA:
3000 new_int_gl = HNS3_INT_GL_8K;
3001 break;
3002 default:
3003 break;
3004 }
3005
3006 ring_group->total_bytes = 0;
3007 ring_group->total_packets = 0;
9bc727a9
YL		 3008 ring_group->coal.flow_level = new_flow_level;
3009 if (new_int_gl != ring_group->coal.int_gl) {
3010 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 3011 return true;
3012 }
3013 return false;
3014}
3015
3016static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3017{
8b1ff1ea
FL		 3018 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3019 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3020 bool rx_update, tx_update;
3021
7445565c
PL		 3022 /* update param every 1000ms */
3023 if (time_before(jiffies,
3024 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3025 return;
cd9d187b 3026
9bc727a9 3027 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 3028 rx_update = hns3_get_new_int_gl(rx_group);
3029 if (rx_update)
3030 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3031 rx_group->coal.int_gl);
8b1ff1ea
FL		 3032 }
3033
9bc727a9 3034 if (tx_group->coal.gl_adapt_enable) {
9e50dc11 3035 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL		 3036 if (tx_update)
3037 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3038 tx_group->coal.int_gl);
76ad4f0e 3039 }
cd9d187b 3040
a95e1f86 3041 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 3042}
3043
3044static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3045{
ff0699e0 3046 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 3047 struct hns3_enet_ring *ring;
3048 int rx_pkt_total = 0;
3049
3050 struct hns3_enet_tqp_vector *tqp_vector =
3051 container_of(napi, struct hns3_enet_tqp_vector, napi);
3052 bool clean_complete = true;
ceca4a5e 3053 int rx_budget = budget;
76ad4f0e 3054
ff0699e0
HT		 3055 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3056 napi_complete(napi);
3057 return 0;
3058 }
3059
76ad4f0e
S		 3060 /* Since the actual Tx work is minimal, we can give the Tx a larger
3061 * budget and be more aggressive about cleaning up the Tx descriptors.
3062 */
799997a3
PL		 3063 hns3_for_each_ring(ring, tqp_vector->tx_group)
3064 hns3_clean_tx_ring(ring);
76ad4f0e
S		 3065
3066 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 3067 if (tqp_vector->num_tqps > 1)
3068 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 3069
3070 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 3071 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3072 hns3_rx_skb);
76ad4f0e
S		 3073
3074 if (rx_cleaned >= rx_budget)
3075 clean_complete = false;
3076
3077 rx_pkt_total += rx_cleaned;
3078 }
3079
3080 tqp_vector->rx_group.total_packets += rx_pkt_total;
3081
3082 if (!clean_complete)
3083 return budget;
3084
531eba0f
HT		 3085 if (napi_complete(napi) &&
3086 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 3087 hns3_update_new_int_gl(tqp_vector);
3088 hns3_mask_vector_irq(tqp_vector, 1);
3089 }
76ad4f0e
S		 3090
3091 return rx_pkt_total;
3092}
3093
3094static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3095 struct hnae3_ring_chain_node *head)
3096{
3097 struct pci_dev *pdev = tqp_vector->handle->pdev;
3098 struct hnae3_ring_chain_node *cur_chain = head;
3099 struct hnae3_ring_chain_node *chain;
3100 struct hns3_enet_ring *tx_ring;
3101 struct hns3_enet_ring *rx_ring;
3102
3103 tx_ring = tqp_vector->tx_group.ring;
3104 if (tx_ring) {
3105 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3106 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3107 HNAE3_RING_TYPE_TX);
3108 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3109 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 3110
3111 cur_chain->next = NULL;
3112
3113 while (tx_ring->next) {
3114 tx_ring = tx_ring->next;
3115
3116 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3117 GFP_KERNEL);
3118 if (!chain)
73b907a0 3119 goto err_free_chain;
76ad4f0e
S		 3120
3121 cur_chain->next = chain;
3122 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3123 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3124 HNAE3_RING_TYPE_TX);
3125 hnae3_set_field(chain->int_gl_idx,
3126 HNAE3_RING_GL_IDX_M,
3127 HNAE3_RING_GL_IDX_S,
3128 HNAE3_RING_GL_TX);
76ad4f0e
S		 3129
3130 cur_chain = chain;
3131 }
3132 }
3133
3134 rx_ring = tqp_vector->rx_group.ring;
3135 if (!tx_ring && rx_ring) {
3136 cur_chain->next = NULL;
3137 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3138 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3139 HNAE3_RING_TYPE_RX);
3140 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3141 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 3142
3143 rx_ring = rx_ring->next;
3144 }
3145
3146 while (rx_ring) {
3147 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3148 if (!chain)
73b907a0 3149 goto err_free_chain;
76ad4f0e
S		 3150
3151 cur_chain->next = chain;
3152 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3153 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3154 HNAE3_RING_TYPE_RX);
3155 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3156 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3157
76ad4f0e
S		 3158 cur_chain = chain;
3159
3160 rx_ring = rx_ring->next;
3161 }
3162
3163 return 0;
73b907a0
HT		 3164
3165err_free_chain:
3166 cur_chain = head->next;
3167 while (cur_chain) {
3168 chain = cur_chain->next;
cda69d24 3169 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 3170 cur_chain = chain;
3171 }
cda69d24 3172 head->next = NULL;
73b907a0
HT		 3173
3174 return -ENOMEM;
76ad4f0e
S		 3175}
3176
3177static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3178 struct hnae3_ring_chain_node *head)
3179{
3180 struct pci_dev *pdev = tqp_vector->handle->pdev;
3181 struct hnae3_ring_chain_node *chain_tmp, *chain;
3182
3183 chain = head->next;
3184
3185 while (chain) {
3186 chain_tmp = chain->next;
3187 devm_kfree(&pdev->dev, chain);
3188 chain = chain_tmp;
3189 }
3190}
3191
3192static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3193 struct hns3_enet_ring *ring)
3194{
3195 ring->next = group->ring;
3196 group->ring = ring;
3197
3198 group->count++;
3199}
3200
874bff0b
PL		 3201static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3202{
3203 struct pci_dev *pdev = priv->ae_handle->pdev;
3204 struct hns3_enet_tqp_vector *tqp_vector;
3205 int num_vectors = priv->vector_num;
3206 int numa_node;
3207 int vector_i;
3208
3209 numa_node = dev_to_node(&pdev->dev);
3210
3211 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3212 tqp_vector = &priv->tqp_vector[vector_i];
3213 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3214 &tqp_vector->affinity_mask);
3215 }
3216}
3217
76ad4f0e
S		 3218static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3219{
3220 struct hnae3_ring_chain_node vector_ring_chain;
3221 struct hnae3_handle *h = priv->ae_handle;
3222 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3223 int ret = 0;
ece4bf46 3224 int i;
76ad4f0e 3225
874bff0b
PL		 3226 hns3_nic_set_cpumask(priv);
3227
dd38c726
YL		 3228 for (i = 0; i < priv->vector_num; i++) {
3229 tqp_vector = &priv->tqp_vector[i];
3230 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3231 tqp_vector->num_tqps = 0;
3232 }
76ad4f0e 3233
dd38c726
YL		 3234 for (i = 0; i < h->kinfo.num_tqps; i++) {
3235 u16 vector_i = i % priv->vector_num;
3236 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3237
3238 tqp_vector = &priv->tqp_vector[vector_i];
3239
3240 hns3_add_ring_to_group(&tqp_vector->tx_group,
3241 priv->ring_data[i].ring);
3242
3243 hns3_add_ring_to_group(&tqp_vector->rx_group,
3244 priv->ring_data[i + tqp_num].ring);
3245
76ad4f0e
S		 3246 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3247 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
dd38c726 3248 tqp_vector->num_tqps++;
76ad4f0e
S		 3249 }
3250
dd38c726 3251 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3252 tqp_vector = &priv->tqp_vector[i];
3253
3254 tqp_vector->rx_group.total_bytes = 0;
3255 tqp_vector->rx_group.total_packets = 0;
3256 tqp_vector->tx_group.total_bytes = 0;
3257 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3258 tqp_vector->handle = h;
3259
3260 ret = hns3_get_vector_ring_chain(tqp_vector,
3261 &vector_ring_chain);
3262 if (ret)
cda69d24 3263 goto map_ring_fail;
76ad4f0e
S		 3264
3265 ret = h->ae_algo->ops->map_ring_to_vector(h,
3266 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3267
3268 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3269
dd38c726 3270 if (ret)
ece4bf46 3271 goto map_ring_fail;
dd38c726 3272
76ad4f0e
S		 3273 netif_napi_add(priv->netdev, &tqp_vector->napi,
3274 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3275 }
3276
dd38c726 3277 return 0;
ece4bf46
HT		 3278
3279map_ring_fail:
3280 while (i--)
3281 netif_napi_del(&priv->tqp_vector[i].napi);
3282
3283 return ret;
dd38c726
YL		 3284}
3285
3286static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3287{
75edb610
JS		 3288#define HNS3_VECTOR_PF_MAX_NUM 64
3289
dd38c726
YL		 3290 struct hnae3_handle *h = priv->ae_handle;
3291 struct hns3_enet_tqp_vector *tqp_vector;
3292 struct hnae3_vector_info *vector;
3293 struct pci_dev *pdev = h->pdev;
3294 u16 tqp_num = h->kinfo.num_tqps;
3295 u16 vector_num;
3296 int ret = 0;
3297 u16 i;
3298
3299 /* RSS size, cpu online and vector_num should be the same */
3300 /* Should consider 2p/4p later */
3301 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS		 3302 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3303
dd38c726
YL		 3304 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3305 GFP_KERNEL);
3306 if (!vector)
3307 return -ENOMEM;
3308
3309 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3310
3311 priv->vector_num = vector_num;
3312 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3313 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3314 GFP_KERNEL);
3315 if (!priv->tqp_vector) {
3316 ret = -ENOMEM;
3317 goto out;
3318 }
3319
3320 for (i = 0; i < priv->vector_num; i++) {
3321 tqp_vector = &priv->tqp_vector[i];
3322 tqp_vector->idx = i;
3323 tqp_vector->mask_addr = vector[i].io_addr;
3324 tqp_vector->vector_irq = vector[i].vector;
3325 hns3_vector_gl_rl_init(tqp_vector, priv);
3326 }
3327
76ad4f0e
S		 3328out:
3329 devm_kfree(&pdev->dev, vector);
3330 return ret;
3331}
3332
dd38c726
YL		 3333static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3334{
3335 group->ring = NULL;
3336 group->count = 0;
3337}
3338
e2152785 3339static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 3340{
3341 struct hnae3_ring_chain_node vector_ring_chain;
3342 struct hnae3_handle *h = priv->ae_handle;
3343 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3344 int i;
76ad4f0e
S		 3345
3346 for (i = 0; i < priv->vector_num; i++) {
3347 tqp_vector = &priv->tqp_vector[i];
3348
2c9dd668
HT		 3349 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3350 continue;
3351
e2152785 3352 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain);
76ad4f0e 3353
e2152785 3354 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3355 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3356
3357 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3358
ae6017a7
HT		 3359 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3360 irq_set_affinity_notifier(tqp_vector->vector_irq,
3361 NULL);
3362 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3363 free_irq(tqp_vector->vector_irq, tqp_vector);
3364 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S		 3365 }
3366
dd38c726
YL		 3367 hns3_clear_ring_group(&tqp_vector->rx_group);
3368 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3369 netif_napi_del(&priv->tqp_vector[i].napi);
3370 }
dd38c726
YL		 3371}
3372
3373static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3374{
3375 struct hnae3_handle *h = priv->ae_handle;
3376 struct pci_dev *pdev = h->pdev;
3377 int i, ret;
3378
3379 for (i = 0; i < priv->vector_num; i++) {
3380 struct hns3_enet_tqp_vector *tqp_vector;
3381
3382 tqp_vector = &priv->tqp_vector[i];
3383 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3384 if (ret)
3385 return ret;
3386 }
76ad4f0e 3387
dd38c726 3388 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3389 return 0;
3390}
3391
3392static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3393 int ring_type)
3394{
3395 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3396 int queue_num = priv->ae_handle->kinfo.num_tqps;
3397 struct pci_dev *pdev = priv->ae_handle->pdev;
3398 struct hns3_enet_ring *ring;
c0425944 3399 int desc_num;
76ad4f0e
S		 3400
3401 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3402 if (!ring)
3403 return -ENOMEM;
3404
3405 if (ring_type == HNAE3_RING_TYPE_TX) {
c0425944 3406 desc_num = priv->ae_handle->kinfo.num_tx_desc;
76ad4f0e 3407 ring_data[q->tqp_index].ring = ring;
66b44730 3408 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 3409 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3410 } else {
c0425944 3411 desc_num = priv->ae_handle->kinfo.num_rx_desc;
76ad4f0e 3412 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 3413 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 3414 ring->io_base = q->io_base;
3415 }
3416
e4e87715 3417 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3418
76ad4f0e
S		 3419 ring->tqp = q;
3420 ring->desc = NULL;
3421 ring->desc_cb = NULL;
3422 ring->dev = priv->dev;
3423 ring->desc_dma_addr = 0;
3424 ring->buf_size = q->buf_size;
2c9dd668 3425 ring->desc_num = desc_num;
76ad4f0e
S		 3426 ring->next_to_use = 0;
3427 ring->next_to_clean = 0;
3428
3429 return 0;
3430}
3431
3432static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3433 struct hns3_nic_priv *priv)
3434{
3435 int ret;
3436
3437 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3438 if (ret)
3439 return ret;
3440
3441 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
73b907a0
HT		 3442 if (ret) {
3443 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
76ad4f0e 3444 return ret;
73b907a0 3445 }
76ad4f0e
S		 3446
3447 return 0;
3448}
3449
3450static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3451{
3452 struct hnae3_handle *h = priv->ae_handle;
3453 struct pci_dev *pdev = h->pdev;
3454 int i, ret;
3455
a86854d0
KC		 3456 priv->ring_data = devm_kzalloc(&pdev->dev,
3457 array3_size(h->kinfo.num_tqps,
3458 sizeof(*priv->ring_data),
3459 2),
76ad4f0e
S		 3460 GFP_KERNEL);
3461 if (!priv->ring_data)
3462 return -ENOMEM;
3463
3464 for (i = 0; i < h->kinfo.num_tqps; i++) {
3465 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3466 if (ret)
3467 goto err;
3468 }
3469
3470 return 0;
3471err:
73b907a0
HT		 3472 while (i--) {
3473 devm_kfree(priv->dev, priv->ring_data[i].ring);
3474 devm_kfree(priv->dev,
3475 priv->ring_data[i + h->kinfo.num_tqps].ring);
3476 }
3477
76ad4f0e
S		 3478 devm_kfree(&pdev->dev, priv->ring_data);
3479 return ret;
3480}
3481
09f2af64
PL		 3482static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3483{
3484 struct hnae3_handle *h = priv->ae_handle;
3485 int i;
3486
3487 for (i = 0; i < h->kinfo.num_tqps; i++) {
3488 devm_kfree(priv->dev, priv->ring_data[i].ring);
3489 devm_kfree(priv->dev,
3490 priv->ring_data[i + h->kinfo.num_tqps].ring);
3491 }
3492 devm_kfree(priv->dev, priv->ring_data);
3493}
3494
76ad4f0e
S		 3495static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3496{
3497 int ret;
3498
3499 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3500 return -EINVAL;
3501
3502 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
3503 GFP_KERNEL);
3504 if (!ring->desc_cb) {
3505 ret = -ENOMEM;
3506 goto out;
3507 }
3508
3509 ret = hns3_alloc_desc(ring);
3510 if (ret)
3511 goto out_with_desc_cb;
3512
3513 if (!HNAE3_IS_TX_RING(ring)) {
3514 ret = hns3_alloc_ring_buffers(ring);
3515 if (ret)
3516 goto out_with_desc;
3517 }
3518
3519 return 0;
3520
3521out_with_desc:
3522 hns3_free_desc(ring);
3523out_with_desc_cb:
3524 kfree(ring->desc_cb);
3525 ring->desc_cb = NULL;
3526out:
3527 return ret;
3528}
3529
3530static void hns3_fini_ring(struct hns3_enet_ring *ring)
3531{
3532 hns3_free_desc(ring);
3533 kfree(ring->desc_cb);
3534 ring->desc_cb = NULL;
3535 ring->next_to_clean = 0;
3536 ring->next_to_use = 0;
ac574b80
PL		 3537 ring->pending_buf = 0;
3538 if (ring->skb) {
3539 dev_kfree_skb_any(ring->skb);
3540 ring->skb = NULL;
3541 }
76ad4f0e
S		 3542}
3543
1db9b1bf 3544static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3545{
3546 int bd_size_type;
3547
3548 switch (buf_size) {
3549 case 512:
3550 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3551 break;
3552 case 1024:
3553 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3554 break;
3555 case 2048:
3556 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3557 break;
3558 case 4096:
3559 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3560 break;
3561 default:
3562 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3563 }
3564
3565 return bd_size_type;
3566}
3567
3568static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3569{
3570 dma_addr_t dma = ring->desc_dma_addr;
3571 struct hnae3_queue *q = ring->tqp;
3572
3573 if (!HNAE3_IS_TX_RING(ring)) {
3574 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3575 (u32)dma);
3576 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3577 (u32)((dma >> 31) >> 1));
3578
3579 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3580 hns3_buf_size2type(ring->buf_size));
3581 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3582 ring->desc_num / 8 - 1);
3583
3584 } else {
3585 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3586 (u32)dma);
3587 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3588 (u32)((dma >> 31) >> 1));
3589
76ad4f0e
S		 3590 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3591 ring->desc_num / 8 - 1);
3592 }
3593}
3594
1c772154
YL		 3595static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3596{
3597 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3598 int i;
3599
3600 for (i = 0; i < HNAE3_MAX_TC; i++) {
3601 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3602 int j;
3603
3604 if (!tc_info->enable)
3605 continue;
3606
3607 for (j = 0; j < tc_info->tqp_count; j++) {
3608 struct hnae3_queue *q;
3609
3610 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3611 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3612 tc_info->tc);
3613 }
3614 }
3615}
3616
5668abda 3617int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3618{
3619 struct hnae3_handle *h = priv->ae_handle;
3620 int ring_num = h->kinfo.num_tqps * 2;
3621 int i, j;
3622 int ret;
3623
3624 for (i = 0; i < ring_num; i++) {
3625 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3626 if (ret) {
3627 dev_err(priv->dev,
3628 "Alloc ring memory fail! ret=%d\n", ret);
3629 goto out_when_alloc_ring_memory;
3630 }
3631
76ad4f0e
S		 3632 u64_stats_init(&priv->ring_data[i].ring->syncp);
3633 }
3634
3635 return 0;
3636
3637out_when_alloc_ring_memory:
3638 for (j = i - 1; j >= 0; j--)
ee83f776 3639 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3640
3641 return -ENOMEM;
3642}
3643
5668abda 3644int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3645{
3646 struct hnae3_handle *h = priv->ae_handle;
3647 int i;
3648
3649 for (i = 0; i < h->kinfo.num_tqps; i++) {
76ad4f0e
S		 3650 hns3_fini_ring(priv->ring_data[i].ring);
3651 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3652 }
76ad4f0e
S		 3653 return 0;
3654}
3655
3656/* Set mac addr if it is configured. or leave it to the AE driver */
7fa6be4f 3657static int hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3658{
3659 struct hns3_nic_priv *priv = netdev_priv(netdev);
3660 struct hnae3_handle *h = priv->ae_handle;
3661 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3662 int ret = 0;
76ad4f0e 3663
f09555ff 3664 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3665 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3666 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3667 }
3668
3669 /* Check if the MAC address is valid, if not get a random one */
3670 if (!is_valid_ether_addr(netdev->dev_addr)) {
3671 eth_hw_addr_random(netdev);
3672 dev_warn(priv->dev, "using random MAC address %pM\n",
3673 netdev->dev_addr);
76ad4f0e 3674 }
139e8792
L		 3675
3676 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3677 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3678
7fa6be4f 3679 return ret;
76ad4f0e
S		 3680}
3681
c8a8045b
HT		 3682static int hns3_init_phy(struct net_device *netdev)
3683{
3684 struct hnae3_handle *h = hns3_get_handle(netdev);
3685 int ret = 0;
3686
3687 if (h->ae_algo->ops->mac_connect_phy)
3688 ret = h->ae_algo->ops->mac_connect_phy(h);
3689
3690 return ret;
3691}
3692
3693static void hns3_uninit_phy(struct net_device *netdev)
3694{
3695 struct hnae3_handle *h = hns3_get_handle(netdev);
3696
3697 if (h->ae_algo->ops->mac_disconnect_phy)
3698 h->ae_algo->ops->mac_disconnect_phy(h);
3699}
3700
6871af29
JS		 3701static int hns3_restore_fd_rules(struct net_device *netdev)
3702{
3703 struct hnae3_handle *h = hns3_get_handle(netdev);
3704 int ret = 0;
3705
3706 if (h->ae_algo->ops->restore_fd_rules)
3707 ret = h->ae_algo->ops->restore_fd_rules(h);
3708
3709 return ret;
3710}
3711
3712static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3713{
3714 struct hnae3_handle *h = hns3_get_handle(netdev);
3715
3716 if (h->ae_algo->ops->del_all_fd_entries)
3717 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3718}
3719
76ad4f0e
S		 3720static void hns3_nic_set_priv_ops(struct net_device *netdev)
3721{
3722 struct hns3_nic_priv *priv = netdev_priv(netdev);
3723
3724 if ((netdev->features & NETIF_F_TSO) ||
0bbbf15d 3725 (netdev->features & NETIF_F_TSO6))
76ad4f0e 3726 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
0bbbf15d 3727 else
76ad4f0e 3728 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 3729}
3730
a6d818e3
YL		 3731static int hns3_client_start(struct hnae3_handle *handle)
3732{
3733 if (!handle->ae_algo->ops->client_start)
3734 return 0;
3735
3736 return handle->ae_algo->ops->client_start(handle);
3737}
3738
3739static void hns3_client_stop(struct hnae3_handle *handle)
3740{
3741 if (!handle->ae_algo->ops->client_stop)
3742 return;
3743
3744 handle->ae_algo->ops->client_stop(handle);
3745}
3746
bb87be87
YL		 3747static void hns3_info_show(struct hns3_nic_priv *priv)
3748{
3749 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3750
3751 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3752 dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps);
3753 dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size);
3754 dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size);
3755 dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len);
3756 dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc);
3757 dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc);
3758 dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc);
3759 dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu);
3760}
3761
76ad4f0e
S		 3762static int hns3_client_init(struct hnae3_handle *handle)
3763{
3764 struct pci_dev *pdev = handle->pdev;
0d43bf45 3765 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3766 struct hns3_nic_priv *priv;
3767 struct net_device *netdev;
3768 int ret;
3769
0d43bf45
HT		 3770 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3771 &max_rss_size);
3772 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3773 if (!netdev)
3774 return -ENOMEM;
3775
3776 priv = netdev_priv(netdev);
3777 priv->dev = &pdev->dev;
3778 priv->netdev = netdev;
3779 priv->ae_handle = handle;
f8fa222c 3780 priv->tx_timeout_count = 0;
b7b585c2 3781 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 3782
bb87be87
YL		 3783 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3784
76ad4f0e
S		 3785 handle->kinfo.netdev = netdev;
3786 handle->priv = (void *)priv;
3787
f09555ff 3788 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3789
3790 hns3_set_default_feature(netdev);
3791
3792 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3793 netdev->priv_flags |= IFF_UNICAST_FLT;
3794 netdev->netdev_ops = &hns3_nic_netdev_ops;
3795 SET_NETDEV_DEV(netdev, &pdev->dev);
3796 hns3_ethtool_set_ops(netdev);
3797 hns3_nic_set_priv_ops(netdev);
3798
3799 /* Carrier off reporting is important to ethtool even BEFORE open */
3800 netif_carrier_off(netdev);
3801
3802 ret = hns3_get_ring_config(priv);
3803 if (ret) {
3804 ret = -ENOMEM;
3805 goto out_get_ring_cfg;
3806 }
3807
dd38c726
YL		 3808 ret = hns3_nic_alloc_vector_data(priv);
3809 if (ret) {
3810 ret = -ENOMEM;
3811 goto out_alloc_vector_data;
3812 }
3813
76ad4f0e
S		 3814 ret = hns3_nic_init_vector_data(priv);
3815 if (ret) {
3816 ret = -ENOMEM;
3817 goto out_init_vector_data;
3818 }
3819
3820 ret = hns3_init_all_ring(priv);
3821 if (ret) {
3822 ret = -ENOMEM;
3823 goto out_init_ring_data;
3824 }
3825
c8a8045b
HT		 3826 ret = hns3_init_phy(netdev);
3827 if (ret)
3828 goto out_init_phy;
3829
76ad4f0e
S		 3830 ret = register_netdev(netdev);
3831 if (ret) {
3832 dev_err(priv->dev, "probe register netdev fail!\n");
3833 goto out_reg_netdev_fail;
3834 }
3835
a6d818e3
YL		 3836 ret = hns3_client_start(handle);
3837 if (ret) {
3838 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
18655128 3839 goto out_client_start;
a6d818e3
YL		 3840 }
3841
986743db
YL		 3842 hns3_dcbnl_setup(handle);
3843
b2292360 3844 hns3_dbg_init(handle);
3845
a0b43717 3846 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 3847 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 3848
814da63c
HT		 3849 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3850
bb87be87
YL		 3851 if (netif_msg_drv(handle))
3852 hns3_info_show(priv);
3853
76ad4f0e
S		 3854 return ret;
3855
18655128
HT		 3856out_client_start:
3857 unregister_netdev(netdev);
76ad4f0e 3858out_reg_netdev_fail:
c8a8045b
HT		 3859 hns3_uninit_phy(netdev);
3860out_init_phy:
3861 hns3_uninit_all_ring(priv);
76ad4f0e 3862out_init_ring_data:
e2152785 3863 hns3_nic_uninit_vector_data(priv);
76ad4f0e 3864out_init_vector_data:
dd38c726
YL		 3865 hns3_nic_dealloc_vector_data(priv);
3866out_alloc_vector_data:
3867 priv->ring_data = NULL;
76ad4f0e
S		 3868out_get_ring_cfg:
3869 priv->ae_handle = NULL;
3870 free_netdev(netdev);
3871 return ret;
3872}
3873
3874static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3875{
3876 struct net_device *netdev = handle->kinfo.netdev;
3877 struct hns3_nic_priv *priv = netdev_priv(netdev);
3878 int ret;
3879
f05e2109
JS		 3880 hns3_remove_hw_addr(netdev);
3881
76ad4f0e
S		 3882 if (netdev->reg_state != NETREG_UNINITIALIZED)
3883 unregister_netdev(netdev);
3884
eb32c896
HT		 3885 hns3_client_stop(handle);
3886
814da63c
HT		 3887 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3888 netdev_warn(netdev, "already uninitialized\n");
3889 goto out_netdev_free;
3890 }
3891
dc5e6064
JS		 3892 hns3_del_all_fd_rules(netdev, true);
3893
7b763f3f
FL		 3894 hns3_force_clear_all_rx_ring(handle);
3895
c8a8045b
HT		 3896 hns3_uninit_phy(netdev);
3897
e2152785 3898 hns3_nic_uninit_vector_data(priv);
76ad4f0e 3899
dd38c726
YL		 3900 ret = hns3_nic_dealloc_vector_data(priv);
3901 if (ret)
3902 netdev_err(netdev, "dealloc vector error\n");
3903
76ad4f0e
S		 3904 ret = hns3_uninit_all_ring(priv);
3905 if (ret)
3906 netdev_err(netdev, "uninit ring error\n");
3907
ec777890
YL		 3908 hns3_put_ring_config(priv);
3909
b2292360 3910 hns3_dbg_uninit(handle);
3911
76ad4f0e
S		 3912 priv->ring_data = NULL;
3913
814da63c 3914out_netdev_free:
76ad4f0e
S		 3915 free_netdev(netdev);
3916}
3917
3918static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3919{
3920 struct net_device *netdev = handle->kinfo.netdev;
3921
3922 if (!netdev)
3923 return;
3924
3925 if (linkup) {
3926 netif_carrier_on(netdev);
3927 netif_tx_wake_all_queues(netdev);
bb87be87
YL		 3928 if (netif_msg_link(handle))
3929 netdev_info(netdev, "link up\n");
76ad4f0e
S		 3930 } else {
3931 netif_carrier_off(netdev);
3932 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 3933 if (netif_msg_link(handle))
3934 netdev_info(netdev, "link down\n");
76ad4f0e
S		 3935 }
3936}
3937
9df8f79a
YL		 3938static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3939{
3940 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3941 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL		 3942
3943 if (tc > HNAE3_MAX_TC)
3944 return -EINVAL;
3945
3946 if (!ndev)
3947 return -ENODEV;
3948
a1ef124e 3949 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL		 3950}
3951
7fa6be4f 3952static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L		 3953{
3954 struct netdev_hw_addr_list *list;
3955 struct netdev_hw_addr *ha, *tmp;
7fa6be4f 3956 int ret = 0;
bb6b94a8 3957
389775a6 3958 netif_addr_lock_bh(ndev);
bb6b94a8
L		 3959 /* go through and sync uc_addr entries to the device */
3960 list = &ndev->uc;
7fa6be4f
HT		 3961 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3962 ret = hns3_nic_uc_sync(ndev, ha->addr);
3963 if (ret)
389775a6 3964 goto out;
7fa6be4f 3965 }
bb6b94a8
L		 3966
3967 /* go through and sync mc_addr entries to the device */
3968 list = &ndev->mc;
7fa6be4f
HT		 3969 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3970 ret = hns3_nic_mc_sync(ndev, ha->addr);
3971 if (ret)
389775a6 3972 goto out;
7fa6be4f
HT		 3973 }
3974
389775a6
JS		 3975out:
3976 netif_addr_unlock_bh(ndev);
7fa6be4f 3977 return ret;
bb6b94a8
L		 3978}
3979
f05e2109
JS		 3980static void hns3_remove_hw_addr(struct net_device *netdev)
3981{
3982 struct netdev_hw_addr_list *list;
3983 struct netdev_hw_addr *ha, *tmp;
3984
3985 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3986
389775a6 3987 netif_addr_lock_bh(netdev);
f05e2109
JS		 3988 /* go through and unsync uc_addr entries to the device */
3989 list = &netdev->uc;
3990 list_for_each_entry_safe(ha, tmp, &list->list, list)
3991 hns3_nic_uc_unsync(netdev, ha->addr);
3992
3993 /* go through and unsync mc_addr entries to the device */
3994 list = &netdev->mc;
3995 list_for_each_entry_safe(ha, tmp, &list->list, list)
3996 if (ha->refcount > 1)
3997 hns3_nic_mc_unsync(netdev, ha->addr);
389775a6
JS		 3998
3999 netif_addr_unlock_bh(netdev);
f05e2109
JS		 4000}
4001
beebca3a 4002static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 4003{
beebca3a 4004 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 4005 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL		 4006 hns3_free_buffer_detach(ring, ring->next_to_clean);
4007 ring_ptr_move_fw(ring, next_to_clean);
4008 }
4009}
4010
7b763f3f
FL		 4011static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4012{
4013 struct hns3_desc_cb res_cbs;
4014 int ret;
4015
4016 while (ring->next_to_use != ring->next_to_clean) {
4017 /* When a buffer is not reused, it's memory has been
4018 * freed in hns3_handle_rx_bd or will be freed by
4019 * stack, so we need to replace the buffer here.
4020 */
4021 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4022 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4023 if (ret) {
4024 u64_stats_update_begin(&ring->syncp);
4025 ring->stats.sw_err_cnt++;
4026 u64_stats_update_end(&ring->syncp);
4027 /* if alloc new buffer fail, exit directly
4028 * and reclear in up flow.
4029 */
4030 netdev_warn(ring->tqp->handle->kinfo.netdev,
4031 "reserve buffer map failed, ret = %d\n",
4032 ret);
4033 return ret;
4034 }
4035 hns3_replace_buffer(ring, ring->next_to_use,
4036 &res_cbs);
4037 }
4038 ring_ptr_move_fw(ring, next_to_use);
4039 }
4040
cc5ff6e9
PL		 4041 /* Free the pending skb in rx ring */
4042 if (ring->skb) {
4043 dev_kfree_skb_any(ring->skb);
4044 ring->skb = NULL;
4045 ring->pending_buf = 0;
4046 }
4047
7b763f3f
FL		 4048 return 0;
4049}
4050
4051static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4052{
beebca3a
YL		 4053 while (ring->next_to_use != ring->next_to_clean) {
4054 /* When a buffer is not reused, it's memory has been
4055 * freed in hns3_handle_rx_bd or will be freed by
4056 * stack, so only need to unmap the buffer here.
4057 */
4058 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4059 hns3_unmap_buffer(ring,
4060 &ring->desc_cb[ring->next_to_use]);
4061 ring->desc_cb[ring->next_to_use].dma = 0;
4062 }
4063
4064 ring_ptr_move_fw(ring, next_to_use);
4065 }
bb6b94a8
L		 4066}
4067
7b763f3f
FL		 4068static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
4069{
4070 struct net_device *ndev = h->kinfo.netdev;
4071 struct hns3_nic_priv *priv = netdev_priv(ndev);
4072 struct hns3_enet_ring *ring;
4073 u32 i;
4074
4075 for (i = 0; i < h->kinfo.num_tqps; i++) {
4076 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
4077 hns3_force_clear_rx_ring(ring);
4078 }
4079}
4080
bb6b94a8
L		 4081static void hns3_clear_all_ring(struct hnae3_handle *h)
4082{
4083 struct net_device *ndev = h->kinfo.netdev;
4084 struct hns3_nic_priv *priv = netdev_priv(ndev);
4085 u32 i;
4086
4087 for (i = 0; i < h->kinfo.num_tqps; i++) {
4088 struct netdev_queue *dev_queue;
4089 struct hns3_enet_ring *ring;
4090
4091 ring = priv->ring_data[i].ring;
beebca3a 4092 hns3_clear_tx_ring(ring);
bb6b94a8
L		 4093 dev_queue = netdev_get_tx_queue(ndev,
4094 priv->ring_data[i].queue_index);
4095 netdev_tx_reset_queue(dev_queue);
4096
4097 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
7b763f3f
FL		 4098 /* Continue to clear other rings even if clearing some
4099 * rings failed.
4100 */
beebca3a 4101 hns3_clear_rx_ring(ring);
bb6b94a8
L		 4102 }
4103}
4104
7b763f3f
FL		 4105int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4106{
4107 struct net_device *ndev = h->kinfo.netdev;
4108 struct hns3_nic_priv *priv = netdev_priv(ndev);
4109 struct hns3_enet_ring *rx_ring;
4110 int i, j;
4111 int ret;
4112
4113 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 4114 ret = h->ae_algo->ops->reset_queue(h, i);
4115 if (ret)
4116 return ret;
4117
7b763f3f
FL		 4118 hns3_init_ring_hw(priv->ring_data[i].ring);
4119
4120 /* We need to clear tx ring here because self test will
4121 * use the ring and will not run down before up
4122 */
4123 hns3_clear_tx_ring(priv->ring_data[i].ring);
4124 priv->ring_data[i].ring->next_to_clean = 0;
4125 priv->ring_data[i].ring->next_to_use = 0;
4126
4127 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
4128 hns3_init_ring_hw(rx_ring);
4129 ret = hns3_clear_rx_ring(rx_ring);
4130 if (ret)
4131 return ret;
4132
4133 /* We can not know the hardware head and tail when this
4134 * function is called in reset flow, so we reuse all desc.
4135 */
4136 for (j = 0; j < rx_ring->desc_num; j++)
4137 hns3_reuse_buffer(rx_ring, j);
4138
4139 rx_ring->next_to_clean = 0;
4140 rx_ring->next_to_use = 0;
4141 }
4142
1c772154
YL		 4143 hns3_init_tx_ring_tc(priv);
4144
7b763f3f
FL		 4145 return 0;
4146}
4147
e4fd7502
HT		 4148static void hns3_store_coal(struct hns3_nic_priv *priv)
4149{
4150 /* ethtool only support setting and querying one coal
4151 * configuation for now, so save the vector 0' coal
4152 * configuation here in order to restore it.
4153 */
4154 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4155 sizeof(struct hns3_enet_coalesce));
4156 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4157 sizeof(struct hns3_enet_coalesce));
4158}
4159
4160static void hns3_restore_coal(struct hns3_nic_priv *priv)
4161{
4162 u16 vector_num = priv->vector_num;
4163 int i;
4164
4165 for (i = 0; i < vector_num; i++) {
4166 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4167 sizeof(struct hns3_enet_coalesce));
4168 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4169 sizeof(struct hns3_enet_coalesce));
4170 }
4171}
4172
bb6b94a8
L		 4173static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4174{
7edff533 4175 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L		 4176 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4177 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 4178 struct hns3_nic_priv *priv = netdev_priv(ndev);
4179
4180 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4181 return 0;
bb6b94a8 4182
7edff533
HT		 4183 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4184 * from table space. Hence, for function reset software intervention is
4185 * required to delete the entries
4186 */
4187 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4188 hns3_remove_hw_addr(ndev);
4189 hns3_del_all_fd_rules(ndev, false);
4190 }
4191
bb6b94a8 4192 if (!netif_running(ndev))
6b1385cc 4193 return 0;
bb6b94a8
L		 4194
4195 return hns3_nic_net_stop(ndev);
4196}
4197
4198static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4199{
4200 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4201 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4202 int ret = 0;
4203
e8884027
HT		 4204 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4205
bb6b94a8 4206 if (netif_running(kinfo->netdev)) {
e8884027 4207 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4208 if (ret) {
e8884027 4209 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8
L		 4210 netdev_err(kinfo->netdev,
4211 "hns net up fail, ret=%d!\n", ret);
4212 return ret;
4213 }
bb6b94a8
L		 4214 }
4215
4216 return ret;
4217}
4218
4219static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4220{
4221 struct net_device *netdev = handle->kinfo.netdev;
4222 struct hns3_nic_priv *priv = netdev_priv(netdev);
4223 int ret;
4224
bb6b94a8
L		 4225 /* Carrier off reporting is important to ethtool even BEFORE open */
4226 netif_carrier_off(netdev);
4227
2c9dd668 4228 ret = hns3_get_ring_config(priv);
862d969a
HT		 4229 if (ret)
4230 return ret;
4231
2c9dd668
HT		 4232 ret = hns3_nic_alloc_vector_data(priv);
4233 if (ret)
4234 goto err_put_ring;
4235
e4fd7502
HT		 4236 hns3_restore_coal(priv);
4237
bb6b94a8
L		 4238 ret = hns3_nic_init_vector_data(priv);
4239 if (ret)
862d969a 4240 goto err_dealloc_vector;
bb6b94a8
L		 4241
4242 ret = hns3_init_all_ring(priv);
862d969a
HT		 4243 if (ret)
4244 goto err_uninit_vector;
bb6b94a8 4245
cd513a69
HT		 4246 ret = hns3_client_start(handle);
4247 if (ret) {
4248 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4249 goto err_uninit_ring;
4250 }
4251
814da63c
HT		 4252 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4253
862d969a
HT		 4254 return ret;
4255
cd513a69
HT		 4256err_uninit_ring:
4257 hns3_uninit_all_ring(priv);
862d969a
HT		 4258err_uninit_vector:
4259 hns3_nic_uninit_vector_data(priv);
4260 priv->ring_data = NULL;
4261err_dealloc_vector:
4262 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 4263err_put_ring:
4264 hns3_put_ring_config(priv);
4265 priv->ring_data = NULL;
862d969a 4266
bb6b94a8
L		 4267 return ret;
4268}
4269
1f609492
YL		 4270static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4271{
4272 struct net_device *netdev = handle->kinfo.netdev;
4273 bool vlan_filter_enable;
4274 int ret;
4275
4276 ret = hns3_init_mac_addr(netdev, false);
4277 if (ret)
4278 return ret;
4279
4280 ret = hns3_recover_hw_addr(netdev);
4281 if (ret)
4282 return ret;
4283
4284 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4285 if (ret)
4286 return ret;
4287
4288 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4289 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4290
4291 /* Hardware table is only clear when pf resets */
4292 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4293 ret = hns3_restore_vlan(netdev);
4294 if (ret)
4295 return ret;
4296 }
4297
4298 return hns3_restore_fd_rules(netdev);
4299}
4300
bb6b94a8
L		 4301static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4302{
4303 struct net_device *netdev = handle->kinfo.netdev;
4304 struct hns3_nic_priv *priv = netdev_priv(netdev);
4305 int ret;
4306
1eeb3367 4307 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 4308 netdev_warn(netdev, "already uninitialized\n");
4309 return 0;
4310 }
4311
7b763f3f 4312 hns3_force_clear_all_rx_ring(handle);
bb6b94a8 4313
e2152785 4314 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4315
e4fd7502
HT		 4316 hns3_store_coal(priv);
4317
862d969a
HT		 4318 ret = hns3_nic_dealloc_vector_data(priv);
4319 if (ret)
4320 netdev_err(netdev, "dealloc vector error\n");
4321
bb6b94a8
L		 4322 ret = hns3_uninit_all_ring(priv);
4323 if (ret)
4324 netdev_err(netdev, "uninit ring error\n");
4325
2c9dd668
HT		 4326 hns3_put_ring_config(priv);
4327 priv->ring_data = NULL;
4328
bb6b94a8
L		 4329 return ret;
4330}
4331
4332static int hns3_reset_notify(struct hnae3_handle *handle,
4333 enum hnae3_reset_notify_type type)
4334{
4335 int ret = 0;
4336
4337 switch (type) {
4338 case HNAE3_UP_CLIENT:
e1586241
SM		 4339 ret = hns3_reset_notify_up_enet(handle);
4340 break;
bb6b94a8
L		 4341 case HNAE3_DOWN_CLIENT:
4342 ret = hns3_reset_notify_down_enet(handle);
4343 break;
4344 case HNAE3_INIT_CLIENT:
4345 ret = hns3_reset_notify_init_enet(handle);
4346 break;
4347 case HNAE3_UNINIT_CLIENT:
4348 ret = hns3_reset_notify_uninit_enet(handle);
4349 break;
1f609492
YL		 4350 case HNAE3_RESTORE_CLIENT:
4351 ret = hns3_reset_notify_restore_enet(handle);
4352 break;
bb6b94a8
L		 4353 default:
4354 break;
4355 }
4356
4357 return ret;
4358}
4359
09f2af64
PL		 4360int hns3_set_channels(struct net_device *netdev,
4361 struct ethtool_channels *ch)
4362{
09f2af64
PL		 4363 struct hnae3_handle *h = hns3_get_handle(netdev);
4364 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4365 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 4366 u32 new_tqp_num = ch->combined_count;
4367 u16 org_tqp_num;
4368 int ret;
4369
4370 if (ch->rx_count || ch->tx_count)
4371 return -EINVAL;
4372
678335a1 4373 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4374 new_tqp_num < 1) {
09f2af64 4375 dev_err(&netdev->dev,
c78b5b6c 4376 "Change tqps fail, the tqp range is from 1 to %d",
678335a1 4377 hns3_get_max_available_channels(h));
09f2af64
PL		 4378 return -EINVAL;
4379 }
4380
c78b5b6c 4381 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 4382 return 0;
4383
65749f73
HT		 4384 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4385 if (ret)
4386 return ret;
dd38c726 4387
65749f73
HT		 4388 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4389 if (ret)
4390 return ret;
09f2af64
PL		 4391
4392 org_tqp_num = h->kinfo.num_tqps;
90c68a41 4393 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4394 if (ret) {
90c68a41
YL		 4395 ret = h->ae_algo->ops->set_channels(h, org_tqp_num,
4396 rxfh_configured);
09f2af64
PL		 4397 if (ret) {
4398 /* If revert to old tqp failed, fatal error occurred */
4399 dev_err(&netdev->dev,
4400 "Revert to old tqp num fail, ret=%d", ret);
4401 return ret;
4402 }
4403 dev_info(&netdev->dev,
4404 "Change tqp num fail, Revert to old tqp num");
4405 }
65749f73
HT		 4406 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT);
4407 if (ret)
4408 return ret;
09f2af64 4409
65749f73 4410 return hns3_reset_notify(h, HNAE3_UP_CLIENT);
09f2af64
PL		 4411}
4412
1db9b1bf 4413static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4414 .init_instance = hns3_client_init,
4415 .uninit_instance = hns3_client_uninit,
4416 .link_status_change = hns3_link_status_change,
9df8f79a 4417 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4418 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 4419};
4420
4421/* hns3_init_module - Driver registration routine
4422 * hns3_init_module is the first routine called when the driver is
4423 * loaded. All it does is register with the PCI subsystem.
4424 */
4425static int __init hns3_init_module(void)
4426{
4427 int ret;
4428
4429 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4430 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4431
4432 client.type = HNAE3_CLIENT_KNIC;
4433 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4434 hns3_driver_name);
4435
4436 client.ops = &client_ops;
4437
13562d1f
XW		 4438 INIT_LIST_HEAD(&client.node);
4439
b2292360 4440 hns3_dbg_register_debugfs(hns3_driver_name);
4441
76ad4f0e
S		 4442 ret = hnae3_register_client(&client);
4443 if (ret)
b2292360 4444 goto err_reg_client;
76ad4f0e
S		 4445
4446 ret = pci_register_driver(&hns3_driver);
4447 if (ret)
b2292360 4448 goto err_reg_driver;
76ad4f0e
S		 4449
4450 return ret;
b2292360 4451
4452err_reg_driver:
4453 hnae3_unregister_client(&client);
4454err_reg_client:
4455 hns3_dbg_unregister_debugfs();
4456 return ret;
76ad4f0e
S		 4457}
4458module_init(hns3_init_module);
4459
4460/* hns3_exit_module - Driver exit cleanup routine
4461 * hns3_exit_module is called just before the driver is removed
4462 * from memory.
4463 */
4464static void __exit hns3_exit_module(void)
4465{
4466 pci_unregister_driver(&hns3_driver);
4467 hnae3_unregister_client(&client);
b2292360 4468 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4469}
4470module_exit(hns3_exit_module);
4471
4472MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4473MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4474MODULE_LICENSE("GPL");
4475MODULE_ALIAS("pci:hns-nic");
3c7624d8 4476MODULE_VERSION(HNS3_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)