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net: hns3: fix bug of ethtool_ops.get_channels for VF
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
7#include <linux/if_vlan.h>
8#include <linux/ip.h>
9#include <linux/ipv6.h>
10#include <linux/module.h>
11#include <linux/pci.h>
6ae4e733 12#include <linux/aer.h>
76ad4f0e
S		 13#include <linux/skbuff.h>
14#include <linux/sctp.h>
15#include <linux/vermagic.h>
16#include <net/gre.h>
30d240df 17#include <net/pkt_cls.h>
a6d53b97 18#include <net/tcp.h>
76ad4f0e
S		 19#include <net/vxlan.h>
20
21#include "hnae3.h"
22#include "hns3_enet.h"
23
7b763f3f
FL		 24static void hns3_clear_all_ring(struct hnae3_handle *h);
25static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
f05e2109 26static void hns3_remove_hw_addr(struct net_device *netdev);
7b763f3f 27
1db9b1bf 28static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 29const char hns3_driver_version[] = VERMAGIC_STRING;
30static const char hns3_driver_string[] =
31 "Hisilicon Ethernet Network Driver for Hip08 Family";
32static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
33static struct hnae3_client client;
34
35/* hns3_pci_tbl - PCI Device ID Table
36 *
37 * Last entry must be all 0s
38 *
39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
40 * Class, Class Mask, private data (not used) }
41 */
42static const struct pci_device_id hns3_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
07acf909
JS		 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 58 /* required last entry */
59 {0, }
60};
61MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
62
ef0c5009 63static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 64{
ef0c5009 65 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e
S		 66
67 napi_schedule(&tqp_vector->napi);
68
69 return IRQ_HANDLED;
70}
71
874bff0b
PL		 72/* This callback function is used to set affinity changes to the irq affinity
73 * masks when the irq_set_affinity_notifier function is used.
74 */
75static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
76 const cpumask_t *mask)
77{
78 struct hns3_enet_tqp_vector *tqp_vectors =
79 container_of(notify, struct hns3_enet_tqp_vector,
80 affinity_notify);
81
82 tqp_vectors->affinity_mask = *mask;
83}
84
85static void hns3_nic_irq_affinity_release(struct kref *ref)
86{
87}
88
76ad4f0e
S		 89static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
90{
91 struct hns3_enet_tqp_vector *tqp_vectors;
92 unsigned int i;
93
94 for (i = 0; i < priv->vector_num; i++) {
95 tqp_vectors = &priv->tqp_vector[i];
96
97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
98 continue;
99
874bff0b
PL		 100 /* clear the affinity notifier and affinity mask */
101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
103
76ad4f0e
S		 104 /* release the irq resource */
105 free_irq(tqp_vectors->vector_irq, tqp_vectors);
106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
107 }
108}
109
110static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
111{
112 struct hns3_enet_tqp_vector *tqp_vectors;
113 int txrx_int_idx = 0;
114 int rx_int_idx = 0;
115 int tx_int_idx = 0;
116 unsigned int i;
117 int ret;
118
119 for (i = 0; i < priv->vector_num; i++) {
120 tqp_vectors = &priv->tqp_vector[i];
121
122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
123 continue;
124
125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "TxRx",
128 txrx_int_idx++);
129 txrx_int_idx++;
130 } else if (tqp_vectors->rx_group.ring) {
131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
132 "%s-%s-%d", priv->netdev->name, "Rx",
133 rx_int_idx++);
134 } else if (tqp_vectors->tx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Tx",
137 tx_int_idx++);
138 } else {
139 /* Skip this unused q_vector */
140 continue;
141 }
142
143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
144
145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
146 tqp_vectors->name,
147 tqp_vectors);
148 if (ret) {
149 netdev_err(priv->netdev, "request irq(%d) fail\n",
150 tqp_vectors->vector_irq);
151 return ret;
152 }
153
874bff0b
PL		 154 tqp_vectors->affinity_notify.notify =
155 hns3_nic_irq_affinity_notify;
156 tqp_vectors->affinity_notify.release =
157 hns3_nic_irq_affinity_release;
158 irq_set_affinity_notifier(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_notify);
160 irq_set_affinity_hint(tqp_vectors->vector_irq,
161 &tqp_vectors->affinity_mask);
162
76ad4f0e
S		 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
164 }
165
166 return 0;
167}
168
169static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
170 u32 mask_en)
171{
172 writel(mask_en, tqp_vector->mask_addr);
173}
174
175static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
176{
177 napi_enable(&tqp_vector->napi);
178
179 /* enable vector */
180 hns3_mask_vector_irq(tqp_vector, 1);
181}
182
183static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
184{
185 /* disable vector */
186 hns3_mask_vector_irq(tqp_vector, 0);
187
188 disable_irq(tqp_vector->vector_irq);
189 napi_disable(&tqp_vector->napi);
190}
191
434776a5
FL		 192void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
193 u32 rl_value)
76ad4f0e 194{
434776a5
FL		 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
196
76ad4f0e
S		 197 /* this defines the configuration for RL (Interrupt Rate Limiter).
198 * Rl defines rate of interrupts i.e. number of interrupts-per-second
199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
200 */
434776a5 201
9bc727a9
YL		 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
203 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 204 /* According to the hardware, the range of rl_reg is
205 * 0-59 and the unit is 4.
206 */
207 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
208
209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
210}
211
212void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
213 u32 gl_value)
214{
215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
216
217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
218}
219
220void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
221 u32 gl_value)
222{
223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
224
225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 226}
227
5fd4789a
FL		 228static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
229 struct hns3_nic_priv *priv)
76ad4f0e
S		 230{
231 /* initialize the configuration for interrupt coalescing.
232 * 1. GL (Interrupt Gap Limiter)
233 * 2. RL (Interrupt Rate Limiter)
234 */
235
5fd4789a 236 /* Default: enable interrupt coalescing self-adaptive and GL */
9bc727a9
YL		 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 239
9bc727a9
YL		 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 242
9bc727a9
YL		 243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 245}
246
dd38c726
YL		 247static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
248 struct hns3_nic_priv *priv)
249{
250 struct hnae3_handle *h = priv->ae_handle;
251
252 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 253 tqp_vector->tx_group.coal.int_gl);
dd38c726 254 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 255 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
257}
258
9df8f79a
YL		 259static int hns3_nic_set_real_num_queue(struct net_device *netdev)
260{
9780cb97 261 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 262 struct hnae3_knic_private_info *kinfo = &h->kinfo;
263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
a75a8efa
YL		 264 int i, ret;
265
266 if (kinfo->num_tc <= 1) {
267 netdev_reset_tc(netdev);
268 } else {
269 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
270 if (ret) {
271 netdev_err(netdev,
272 "netdev_set_num_tc fail, ret=%d!\n", ret);
273 return ret;
274 }
275
276 for (i = 0; i < HNAE3_MAX_TC; i++) {
277 if (!kinfo->tc_info[i].enable)
278 continue;
279
280 netdev_set_tc_queue(netdev,
281 kinfo->tc_info[i].tc,
282 kinfo->tc_info[i].tqp_count,
283 kinfo->tc_info[i].tqp_offset);
284 }
285 }
9df8f79a
YL		 286
287 ret = netif_set_real_num_tx_queues(netdev, queue_size);
288 if (ret) {
289 netdev_err(netdev,
290 "netif_set_real_num_tx_queues fail, ret=%d!\n",
291 ret);
292 return ret;
293 }
294
295 ret = netif_set_real_num_rx_queues(netdev, queue_size);
296 if (ret) {
297 netdev_err(netdev,
298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
299 return ret;
300 }
301
302 return 0;
303}
304
678335a1
PL		 305static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
306{
0d43bf45 307 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 308
0d43bf45
HT		 309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
310 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 311
0d43bf45 312 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 313}
314
8df0fa91
HT		 315static void hns3_tqp_enable(struct hnae3_queue *tqp)
316{
317 u32 rcb_reg;
318
319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
320 rcb_reg |= BIT(HNS3_RING_EN_B);
321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
322}
323
324static void hns3_tqp_disable(struct hnae3_queue *tqp)
325{
326 u32 rcb_reg;
327
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg &= ~BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
331}
332
76ad4f0e
S		 333static int hns3_nic_net_up(struct net_device *netdev)
334{
335 struct hns3_nic_priv *priv = netdev_priv(netdev);
336 struct hnae3_handle *h = priv->ae_handle;
337 int i, j;
338 int ret;
339
7b763f3f
FL		 340 ret = hns3_nic_reset_all_ring(h);
341 if (ret)
342 return ret;
343
76ad4f0e
S		 344 /* get irq resource for all vectors */
345 ret = hns3_nic_init_irq(priv);
346 if (ret) {
347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
348 return ret;
349 }
350
351 /* enable the vectors */
352 for (i = 0; i < priv->vector_num; i++)
353 hns3_vector_enable(&priv->tqp_vector[i]);
354
8df0fa91
HT		 355 /* enable rcb */
356 for (j = 0; j < h->kinfo.num_tqps; j++)
357 hns3_tqp_enable(h->kinfo.tqp[j]);
358
76ad4f0e
S		 359 /* start the ae_dev */
360 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
361 if (ret)
362 goto out_start_err;
363
b875cc37
JS		 364 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
365
76ad4f0e
S		 366 return 0;
367
368out_start_err:
8df0fa91
HT		 369 while (j--)
370 hns3_tqp_disable(h->kinfo.tqp[j]);
371
76ad4f0e
S		 372 for (j = i - 1; j >= 0; j--)
373 hns3_vector_disable(&priv->tqp_vector[j]);
374
375 hns3_nic_uninit_irq(priv);
376
377 return ret;
378}
379
380static int hns3_nic_net_open(struct net_device *netdev)
381{
8cdb992f 382 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 383 struct hnae3_handle *h = hns3_get_handle(netdev);
384 struct hnae3_knic_private_info *kinfo;
385 int i, ret;
76ad4f0e 386
257e4f29
HT		 387 if (hns3_nic_resetting(netdev))
388 return -EBUSY;
389
76ad4f0e
S		 390 netif_carrier_off(netdev);
391
9df8f79a
YL		 392 ret = hns3_nic_set_real_num_queue(netdev);
393 if (ret)
76ad4f0e 394 return ret;
76ad4f0e
S		 395
396 ret = hns3_nic_net_up(netdev);
397 if (ret) {
398 netdev_err(netdev,
399 "hns net up fail, ret=%d!\n", ret);
400 return ret;
401 }
402
a75a8efa
YL		 403 kinfo = &h->kinfo;
404 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
405 netdev_set_prio_tc_map(netdev, i,
406 kinfo->prio_tc[i]);
407 }
408
8cdb992f
JS		 409 if (h->ae_algo->ops->set_timer_task)
410 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
411
76ad4f0e
S		 412 return 0;
413}
414
415static void hns3_nic_net_down(struct net_device *netdev)
416{
417 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 418 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 419 const struct hnae3_ae_ops *ops;
420 int i;
421
7b763f3f
FL		 422 /* disable vectors */
423 for (i = 0; i < priv->vector_num; i++)
424 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 425
426 /* disable rcb */
427 for (i = 0; i < h->kinfo.num_tqps; i++)
428 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 429
76ad4f0e
S		 430 /* stop ae_dev */
431 ops = priv->ae_handle->ae_algo->ops;
432 if (ops->stop)
433 ops->stop(priv->ae_handle);
434
76ad4f0e
S		 435 /* free irq resources */
436 hns3_nic_uninit_irq(priv);
7b763f3f
FL		 437
438 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 439}
440
441static int hns3_nic_net_stop(struct net_device *netdev)
442{
ff0699e0 443 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 444 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 445
446 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
447 return 0;
448
8cdb992f
JS		 449 if (h->ae_algo->ops->set_timer_task)
450 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
451
76ad4f0e
S		 452 netif_tx_stop_all_queues(netdev);
453 netif_carrier_off(netdev);
454
455 hns3_nic_net_down(netdev);
456
457 return 0;
458}
459
76ad4f0e
S		 460static int hns3_nic_uc_sync(struct net_device *netdev,
461 const unsigned char *addr)
462{
9780cb97 463 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 464
465 if (h->ae_algo->ops->add_uc_addr)
466 return h->ae_algo->ops->add_uc_addr(h, addr);
467
468 return 0;
469}
470
471static int hns3_nic_uc_unsync(struct net_device *netdev,
472 const unsigned char *addr)
473{
9780cb97 474 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 475
476 if (h->ae_algo->ops->rm_uc_addr)
477 return h->ae_algo->ops->rm_uc_addr(h, addr);
478
479 return 0;
480}
481
482static int hns3_nic_mc_sync(struct net_device *netdev,
483 const unsigned char *addr)
484{
9780cb97 485 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 486
720a8478 487 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 488 return h->ae_algo->ops->add_mc_addr(h, addr);
489
490 return 0;
491}
492
493static int hns3_nic_mc_unsync(struct net_device *netdev,
494 const unsigned char *addr)
495{
9780cb97 496 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 497
720a8478 498 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 499 return h->ae_algo->ops->rm_mc_addr(h, addr);
500
501 return 0;
502}
503
c60edc17
JS		 504static u8 hns3_get_netdev_flags(struct net_device *netdev)
505{
506 u8 flags = 0;
507
508 if (netdev->flags & IFF_PROMISC) {
509 flags = HNAE3_USER_UPE | HNAE3_USER_MPE;
510 } else {
511 flags |= HNAE3_VLAN_FLTR;
512 if (netdev->flags & IFF_ALLMULTI)
513 flags |= HNAE3_USER_MPE;
514 }
515
516 return flags;
517}
518
1db9b1bf 519static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 520{
9780cb97 521 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17
JS		 522 u8 new_flags;
523 int ret;
76ad4f0e 524
c60edc17
JS		 525 new_flags = hns3_get_netdev_flags(netdev);
526
527 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
528 if (ret) {
76ad4f0e 529 netdev_err(netdev, "sync uc address fail\n");
c60edc17
JS		 530 if (ret == -ENOSPC)
531 new_flags |= HNAE3_OVERFLOW_UPE;
532 }
533
40cca1c5 534 if (netdev->flags & IFF_MULTICAST) {
c60edc17
JS		 535 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
536 hns3_nic_mc_unsync);
537 if (ret) {
76ad4f0e 538 netdev_err(netdev, "sync mc address fail\n");
c60edc17
JS		 539 if (ret == -ENOSPC)
540 new_flags |= HNAE3_OVERFLOW_MPE;
541 }
542 }
543
544 hns3_update_promisc_mode(netdev, new_flags);
545 /* User mode Promisc mode enable and vlan filtering is disabled to
546 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
547 * vlan fitering is enabled
548 */
549 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
550 h->netdev_flags = new_flags;
551}
552
7fa6be4f 553int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
c60edc17
JS		 554{
555 struct hns3_nic_priv *priv = netdev_priv(netdev);
556 struct hnae3_handle *h = priv->ae_handle;
557
558 if (h->ae_algo->ops->set_promisc_mode) {
7fa6be4f
HT		 559 return h->ae_algo->ops->set_promisc_mode(h,
560 promisc_flags & HNAE3_UPE,
561 promisc_flags & HNAE3_MPE);
c60edc17 562 }
7fa6be4f
HT		 563
564 return 0;
c60edc17
JS		 565}
566
567void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
568{
569 struct hns3_nic_priv *priv = netdev_priv(netdev);
570 struct hnae3_handle *h = priv->ae_handle;
571 bool last_state;
572
573 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
574 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
575 if (enable != last_state) {
576 netdev_info(netdev,
577 "%s vlan filter\n",
578 enable ? "enable" : "disable");
579 h->ae_algo->ops->enable_vlan_filter(h, enable);
580 }
40cca1c5 581 }
76ad4f0e
S		 582}
583
584static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
585 u16 *mss, u32 *type_cs_vlan_tso)
586{
587 u32 l4_offset, hdr_len;
588 union l3_hdr_info l3;
589 union l4_hdr_info l4;
590 u32 l4_paylen;
591 int ret;
592
593 if (!skb_is_gso(skb))
594 return 0;
595
596 ret = skb_cow_head(skb, 0);
597 if (ret)
598 return ret;
599
600 l3.hdr = skb_network_header(skb);
601 l4.hdr = skb_transport_header(skb);
602
603 /* Software should clear the IPv4's checksum field when tso is
604 * needed.
605 */
606 if (l3.v4->version == 4)
607 l3.v4->check = 0;
608
609 /* tunnel packet.*/
610 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
611 SKB_GSO_GRE_CSUM |
612 SKB_GSO_UDP_TUNNEL |
613 SKB_GSO_UDP_TUNNEL_CSUM)) {
614 if ((!(skb_shinfo(skb)->gso_type &
615 SKB_GSO_PARTIAL)) &&
616 (skb_shinfo(skb)->gso_type &
617 SKB_GSO_UDP_TUNNEL_CSUM)) {
618 /* Software should clear the udp's checksum
619 * field when tso is needed.
620 */
621 l4.udp->check = 0;
622 }
623 /* reset l3&l4 pointers from outer to inner headers */
624 l3.hdr = skb_inner_network_header(skb);
625 l4.hdr = skb_inner_transport_header(skb);
626
627 /* Software should clear the IPv4's checksum field when
628 * tso is needed.
629 */
630 if (l3.v4->version == 4)
631 l3.v4->check = 0;
632 }
633
634 /* normal or tunnel packet*/
635 l4_offset = l4.hdr - skb->data;
636 hdr_len = (l4.tcp->doff * 4) + l4_offset;
637
638 /* remove payload length from inner pseudo checksum when tso*/
639 l4_paylen = skb->len - l4_offset;
640 csum_replace_by_diff(&l4.tcp->check,
641 (__force __wsum)htonl(l4_paylen));
642
643 /* find the txbd field values */
644 *paylen = skb->len - hdr_len;
e4e87715
PL		 645 hnae3_set_bit(*type_cs_vlan_tso,
646 HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 647
648 /* get MSS for TSO */
649 *mss = skb_shinfo(skb)->gso_size;
650
651 return 0;
652}
653
1898d4e4
S		 654static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
655 u8 *il4_proto)
76ad4f0e
S		 656{
657 union {
658 struct iphdr *v4;
659 struct ipv6hdr *v6;
660 unsigned char *hdr;
661 } l3;
662 unsigned char *l4_hdr;
663 unsigned char *exthdr;
664 u8 l4_proto_tmp;
665 __be16 frag_off;
666
667 /* find outer header point */
668 l3.hdr = skb_network_header(skb);
35f58fd7 669 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 670
671 if (skb->protocol == htons(ETH_P_IPV6)) {
672 exthdr = l3.hdr + sizeof(*l3.v6);
673 l4_proto_tmp = l3.v6->nexthdr;
674 if (l4_hdr != exthdr)
675 ipv6_skip_exthdr(skb, exthdr - skb->data,
676 &l4_proto_tmp, &frag_off);
677 } else if (skb->protocol == htons(ETH_P_IP)) {
678 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 679 } else {
680 return -EINVAL;
76ad4f0e
S		 681 }
682
683 *ol4_proto = l4_proto_tmp;
684
685 /* tunnel packet */
686 if (!skb->encapsulation) {
687 *il4_proto = 0;
1898d4e4 688 return 0;
76ad4f0e
S		 689 }
690
691 /* find inner header point */
692 l3.hdr = skb_inner_network_header(skb);
693 l4_hdr = skb_inner_transport_header(skb);
694
695 if (l3.v6->version == 6) {
696 exthdr = l3.hdr + sizeof(*l3.v6);
697 l4_proto_tmp = l3.v6->nexthdr;
698 if (l4_hdr != exthdr)
699 ipv6_skip_exthdr(skb, exthdr - skb->data,
700 &l4_proto_tmp, &frag_off);
701 } else if (l3.v4->version == 4) {
702 l4_proto_tmp = l3.v4->protocol;
703 }
704
705 *il4_proto = l4_proto_tmp;
1898d4e4
S		 706
707 return 0;
76ad4f0e
S		 708}
709
710static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
711 u8 il4_proto, u32 *type_cs_vlan_tso,
712 u32 *ol_type_vlan_len_msec)
713{
714 union {
715 struct iphdr *v4;
716 struct ipv6hdr *v6;
717 unsigned char *hdr;
718 } l3;
719 union {
720 struct tcphdr *tcp;
721 struct udphdr *udp;
722 struct gre_base_hdr *gre;
723 unsigned char *hdr;
724 } l4;
725 unsigned char *l2_hdr;
726 u8 l4_proto = ol4_proto;
727 u32 ol2_len;
728 u32 ol3_len;
729 u32 ol4_len;
730 u32 l2_len;
731 u32 l3_len;
732
733 l3.hdr = skb_network_header(skb);
734 l4.hdr = skb_transport_header(skb);
735
736 /* compute L2 header size for normal packet, defined in 2 Bytes */
737 l2_len = l3.hdr - skb->data;
e4e87715
PL		 738 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
739 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 740
741 /* tunnel packet*/
742 if (skb->encapsulation) {
743 /* compute OL2 header size, defined in 2 Bytes */
744 ol2_len = l2_len;
e4e87715
PL		 745 hnae3_set_field(*ol_type_vlan_len_msec,
746 HNS3_TXD_L2LEN_M,
747 HNS3_TXD_L2LEN_S, ol2_len >> 1);
76ad4f0e
S		 748
749 /* compute OL3 header size, defined in 4 Bytes */
750 ol3_len = l4.hdr - l3.hdr;
e4e87715
PL		 751 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
752 HNS3_TXD_L3LEN_S, ol3_len >> 2);
76ad4f0e
S		 753
754 /* MAC in UDP, MAC in GRE (0x6558)*/
755 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
756 /* switch MAC header ptr from outer to inner header.*/
757 l2_hdr = skb_inner_mac_header(skb);
758
759 /* compute OL4 header size, defined in 4 Bytes. */
760 ol4_len = l2_hdr - l4.hdr;
e4e87715
PL		 761 hnae3_set_field(*ol_type_vlan_len_msec,
762 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
763 ol4_len >> 2);
76ad4f0e
S		 764
765 /* switch IP header ptr from outer to inner header */
766 l3.hdr = skb_inner_network_header(skb);
767
768 /* compute inner l2 header size, defined in 2 Bytes. */
769 l2_len = l3.hdr - l2_hdr;
e4e87715
PL		 770 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
771 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 772 } else {
773 /* skb packet types not supported by hardware,
774 * txbd len fild doesn't be filled.
775 */
776 return;
777 }
778
779 /* switch L4 header pointer from outer to inner */
780 l4.hdr = skb_inner_transport_header(skb);
781
782 l4_proto = il4_proto;
783 }
784
785 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
786 l3_len = l4.hdr - l3.hdr;
e4e87715
PL		 787 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
788 HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e
S		 789
790 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
791 switch (l4_proto) {
792 case IPPROTO_TCP:
e4e87715
PL		 793 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
794 HNS3_TXD_L4LEN_S, l4.tcp->doff);
76ad4f0e
S		 795 break;
796 case IPPROTO_SCTP:
e4e87715
PL		 797 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
798 HNS3_TXD_L4LEN_S,
799 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 800 break;
801 case IPPROTO_UDP:
e4e87715
PL		 802 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
803 HNS3_TXD_L4LEN_S,
804 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 805 break;
806 default:
807 /* skb packet types not supported by hardware,
808 * txbd len fild doesn't be filled.
809 */
810 return;
811 }
812}
813
3db084d2
YL		 814/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
815 * and it is udp packet, which has a dest port as the IANA assigned.
816 * the hardware is expected to do the checksum offload, but the
817 * hardware will not do the checksum offload when udp dest port is
818 * 4789.
819 */
820static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
821{
822#define IANA_VXLAN_PORT 4789
823 union {
824 struct tcphdr *tcp;
825 struct udphdr *udp;
826 struct gre_base_hdr *gre;
827 unsigned char *hdr;
828 } l4;
829
830 l4.hdr = skb_transport_header(skb);
831
832 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
833 return false;
834
835 skb_checksum_help(skb);
836
837 return true;
838}
839
76ad4f0e
S		 840static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
841 u8 il4_proto, u32 *type_cs_vlan_tso,
842 u32 *ol_type_vlan_len_msec)
843{
844 union {
845 struct iphdr *v4;
846 struct ipv6hdr *v6;
847 unsigned char *hdr;
848 } l3;
849 u32 l4_proto = ol4_proto;
850
851 l3.hdr = skb_network_header(skb);
852
853 /* define OL3 type and tunnel type(OL4).*/
854 if (skb->encapsulation) {
855 /* define outer network header type.*/
856 if (skb->protocol == htons(ETH_P_IP)) {
857 if (skb_is_gso(skb))
e4e87715
PL		 858 hnae3_set_field(*ol_type_vlan_len_msec,
859 HNS3_TXD_OL3T_M,
860 HNS3_TXD_OL3T_S,
861 HNS3_OL3T_IPV4_CSUM);
76ad4f0e 862 else
e4e87715
PL		 863 hnae3_set_field(*ol_type_vlan_len_msec,
864 HNS3_TXD_OL3T_M,
865 HNS3_TXD_OL3T_S,
866 HNS3_OL3T_IPV4_NO_CSUM);
76ad4f0e
S		 867
868 } else if (skb->protocol == htons(ETH_P_IPV6)) {
e4e87715
PL		 869 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
870 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
76ad4f0e
S		 871 }
872
873 /* define tunnel type(OL4).*/
874 switch (l4_proto) {
875 case IPPROTO_UDP:
e4e87715
PL		 876 hnae3_set_field(*ol_type_vlan_len_msec,
877 HNS3_TXD_TUNTYPE_M,
878 HNS3_TXD_TUNTYPE_S,
879 HNS3_TUN_MAC_IN_UDP);
76ad4f0e
S		 880 break;
881 case IPPROTO_GRE:
e4e87715
PL		 882 hnae3_set_field(*ol_type_vlan_len_msec,
883 HNS3_TXD_TUNTYPE_M,
884 HNS3_TXD_TUNTYPE_S,
885 HNS3_TUN_NVGRE);
76ad4f0e
S		 886 break;
887 default:
888 /* drop the skb tunnel packet if hardware don't support,
889 * because hardware can't calculate csum when TSO.
890 */
891 if (skb_is_gso(skb))
892 return -EDOM;
893
894 /* the stack computes the IP header already,
895 * driver calculate l4 checksum when not TSO.
896 */
897 skb_checksum_help(skb);
898 return 0;
899 }
900
901 l3.hdr = skb_inner_network_header(skb);
902 l4_proto = il4_proto;
903 }
904
905 if (l3.v4->version == 4) {
e4e87715
PL		 906 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
907 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
76ad4f0e
S		 908
909 /* the stack computes the IP header already, the only time we
910 * need the hardware to recompute it is in the case of TSO.
911 */
912 if (skb_is_gso(skb))
e4e87715 913 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 914 } else if (l3.v6->version == 6) {
e4e87715
PL		 915 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
916 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
76ad4f0e
S		 917 }
918
919 switch (l4_proto) {
920 case IPPROTO_TCP:
5c897197 921 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
e4e87715
PL		 922 hnae3_set_field(*type_cs_vlan_tso,
923 HNS3_TXD_L4T_M,
924 HNS3_TXD_L4T_S,
925 HNS3_L4T_TCP);
76ad4f0e
S		 926 break;
927 case IPPROTO_UDP:
3db084d2
YL		 928 if (hns3_tunnel_csum_bug(skb))
929 break;
930
5c897197 931 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
e4e87715
PL		 932 hnae3_set_field(*type_cs_vlan_tso,
933 HNS3_TXD_L4T_M,
934 HNS3_TXD_L4T_S,
935 HNS3_L4T_UDP);
76ad4f0e
S		 936 break;
937 case IPPROTO_SCTP:
5c897197 938 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
e4e87715
PL		 939 hnae3_set_field(*type_cs_vlan_tso,
940 HNS3_TXD_L4T_M,
941 HNS3_TXD_L4T_S,
942 HNS3_L4T_SCTP);
76ad4f0e
S		 943 break;
944 default:
945 /* drop the skb tunnel packet if hardware don't support,
946 * because hardware can't calculate csum when TSO.
947 */
948 if (skb_is_gso(skb))
949 return -EDOM;
950
951 /* the stack computes the IP header already,
952 * driver calculate l4 checksum when not TSO.
953 */
954 skb_checksum_help(skb);
955 return 0;
956 }
957
958 return 0;
959}
960
961static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
962{
963 /* Config bd buffer end */
e4e87715
PL		 964 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
965 HNS3_TXD_BDTYPE_S, 0);
966 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
967 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
968 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
76ad4f0e
S		 969}
970
9699cffe
PL		 971static int hns3_fill_desc_vtags(struct sk_buff *skb,
972 struct hns3_enet_ring *tx_ring,
973 u32 *inner_vlan_flag,
974 u32 *out_vlan_flag,
975 u16 *inner_vtag,
976 u16 *out_vtag)
977{
978#define HNS3_TX_VLAN_PRIO_SHIFT 13
979
980 if (skb->protocol == htons(ETH_P_8021Q) &&
981 !(tx_ring->tqp->handle->kinfo.netdev->features &
982 NETIF_F_HW_VLAN_CTAG_TX)) {
983 /* When HW VLAN acceleration is turned off, and the stack
984 * sets the protocol to 802.1q, the driver just need to
985 * set the protocol to the encapsulated ethertype.
986 */
987 skb->protocol = vlan_get_protocol(skb);
988 return 0;
989 }
990
991 if (skb_vlan_tag_present(skb)) {
992 u16 vlan_tag;
993
994 vlan_tag = skb_vlan_tag_get(skb);
995 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
996
997 /* Based on hw strategy, use out_vtag in two layer tag case,
998 * and use inner_vtag in one tag case.
999 */
1000 if (skb->protocol == htons(ETH_P_8021Q)) {
e4e87715 1001 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
9699cffe
PL		 1002 *out_vtag = vlan_tag;
1003 } else {
e4e87715 1004 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
9699cffe
PL		 1005 *inner_vtag = vlan_tag;
1006 }
1007 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1008 struct vlan_ethhdr *vhdr;
1009 int rc;
1010
1011 rc = skb_cow_head(skb, 0);
1012 if (rc < 0)
1013 return rc;
1014 vhdr = (struct vlan_ethhdr *)skb->data;
1015 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1016 << HNS3_TX_VLAN_PRIO_SHIFT);
1017 }
1018
1019 skb->protocol = vlan_get_protocol(skb);
1020 return 0;
1021}
1022
76ad4f0e 1023static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
5188f218 1024 int size, int frag_end, enum hns_desc_type type)
76ad4f0e
S		 1025{
1026 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1027 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1028 struct device *dev = ring_to_dev(ring);
76ad4f0e
S		 1029 u32 ol_type_vlan_len_msec = 0;
1030 u16 bdtp_fe_sc_vld_ra_ri = 0;
5188f218 1031 struct skb_frag_struct *frag;
1e8a7977 1032 unsigned int frag_buf_num;
76ad4f0e
S		 1033 u32 type_cs_vlan_tso = 0;
1034 struct sk_buff *skb;
9699cffe
PL		 1035 u16 inner_vtag = 0;
1036 u16 out_vtag = 0;
1e8a7977
FL		 1037 unsigned int k;
1038 int sizeoflast;
76ad4f0e 1039 u32 paylen = 0;
5188f218 1040 dma_addr_t dma;
76ad4f0e 1041 u16 mss = 0;
76ad4f0e
S		 1042 u8 ol4_proto;
1043 u8 il4_proto;
1044 int ret;
1045
76ad4f0e
S		 1046 if (type == DESC_TYPE_SKB) {
1047 skb = (struct sk_buff *)priv;
a90bb9a5 1048 paylen = skb->len;
76ad4f0e 1049
9699cffe
PL		 1050 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1051 &ol_type_vlan_len_msec,
1052 &inner_vtag, &out_vtag);
1053 if (unlikely(ret))
1054 return ret;
1055
76ad4f0e
S		 1056 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1057 skb_reset_mac_len(skb);
76ad4f0e 1058
1898d4e4
S		 1059 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1060 if (ret)
1061 return ret;
76ad4f0e
S		 1062 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
1063 &type_cs_vlan_tso,
1064 &ol_type_vlan_len_msec);
1065 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
1066 &type_cs_vlan_tso,
1067 &ol_type_vlan_len_msec);
1068 if (ret)
1069 return ret;
1070
1071 ret = hns3_set_tso(skb, &paylen, &mss,
1072 &type_cs_vlan_tso);
1073 if (ret)
1074 return ret;
1075 }
1076
1077 /* Set txbd */
1078 desc->tx.ol_type_vlan_len_msec =
1079 cpu_to_le32(ol_type_vlan_len_msec);
1080 desc->tx.type_cs_vlan_tso_len =
1081 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 1082 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 1083 desc->tx.mss = cpu_to_le16(mss);
9699cffe
PL		 1084 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1085 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
5188f218
PL		 1086
1087 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1088 } else {
1089 frag = (struct skb_frag_struct *)priv;
1090 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1091 }
1092
1093 if (dma_mapping_error(ring->dev, dma)) {
1094 ring->stats.sw_err_cnt++;
1095 return -ENOMEM;
76ad4f0e
S		 1096 }
1097
bcdb12b7
FL		 1098 desc_cb->length = size;
1099
1e8a7977
FL		 1100 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1101 sizeoflast = size % HNS3_MAX_BD_SIZE;
1102 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1103
1104 /* When frag size is bigger than hardware limit, split this frag */
1105 for (k = 0; k < frag_buf_num; k++) {
1106 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1107 desc_cb->priv = priv;
1e8a7977
FL		 1108 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1109 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1110 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1111
1112 /* now, fill the descriptor */
1113 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7
FL		 1114 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1115 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977
FL		 1116 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1117 frag_end && (k == frag_buf_num - 1) ?
1118 1 : 0);
1119 desc->tx.bdtp_fe_sc_vld_ra_ri =
1120 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1121
1122 /* move ring pointer to next.*/
1123 ring_ptr_move_fw(ring, next_to_use);
1124
1125 desc_cb = &ring->desc_cb[ring->next_to_use];
1126 desc = &ring->desc[ring->next_to_use];
1127 }
76ad4f0e
S		 1128
1129 return 0;
1130}
1131
76ad4f0e
S		 1132static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1133 struct hns3_enet_ring *ring)
1134{
1135 struct sk_buff *skb = *out_skb;
1136 struct skb_frag_struct *frag;
1137 int bdnum_for_frag;
1138 int frag_num;
1139 int buf_num;
1140 int size;
1141 int i;
1142
1143 size = skb_headlen(skb);
1144 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1145
1146 frag_num = skb_shinfo(skb)->nr_frags;
1147 for (i = 0; i < frag_num; i++) {
1148 frag = &skb_shinfo(skb)->frags[i];
1149 size = skb_frag_size(frag);
1150 bdnum_for_frag =
1151 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1152 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1153 return -ENOMEM;
1154
1155 buf_num += bdnum_for_frag;
1156 }
1157
1158 if (buf_num > ring_space(ring))
1159 return -EBUSY;
1160
1161 *bnum = buf_num;
1162 return 0;
1163}
1164
1165static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1166 struct hns3_enet_ring *ring)
1167{
1168 struct sk_buff *skb = *out_skb;
1169 int buf_num;
1170
1171 /* No. of segments (plus a header) */
1172 buf_num = skb_shinfo(skb)->nr_frags + 1;
1173
932d1252 1174 if (unlikely(ring_space(ring) < buf_num))
76ad4f0e
S		 1175 return -EBUSY;
1176
1177 *bnum = buf_num;
1178
1179 return 0;
1180}
1181
ba3f808f 1182static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1183{
1184 struct device *dev = ring_to_dev(ring);
1185 unsigned int i;
1186
1187 for (i = 0; i < ring->desc_num; i++) {
1188 /* check if this is where we started */
1189 if (ring->next_to_use == next_to_use_orig)
1190 break;
1191
1192 /* unmap the descriptor dma address */
1193 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1194 dma_unmap_single(dev,
1195 ring->desc_cb[ring->next_to_use].dma,
1196 ring->desc_cb[ring->next_to_use].length,
1197 DMA_TO_DEVICE);
bcdb12b7 1198 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1199 dma_unmap_page(dev,
1200 ring->desc_cb[ring->next_to_use].dma,
1201 ring->desc_cb[ring->next_to_use].length,
1202 DMA_TO_DEVICE);
1203
bcdb12b7
FL		 1204 ring->desc_cb[ring->next_to_use].length = 0;
1205
76ad4f0e
S		 1206 /* rollback one */
1207 ring_ptr_move_bw(ring, next_to_use);
1208 }
1209}
1210
d43e5aca 1211netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1212{
1213 struct hns3_nic_priv *priv = netdev_priv(netdev);
1214 struct hns3_nic_ring_data *ring_data =
1215 &tx_ring_data(priv, skb->queue_mapping);
1216 struct hns3_enet_ring *ring = ring_data->ring;
76ad4f0e
S		 1217 struct netdev_queue *dev_queue;
1218 struct skb_frag_struct *frag;
1219 int next_to_use_head;
1220 int next_to_use_frag;
76ad4f0e
S		 1221 int buf_num;
1222 int seg_num;
1223 int size;
1224 int ret;
1225 int i;
1226
1227 /* Prefetch the data used later */
1228 prefetch(skb->data);
1229
1230 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1231 case -EBUSY:
1232 u64_stats_update_begin(&ring->syncp);
1233 ring->stats.tx_busy++;
1234 u64_stats_update_end(&ring->syncp);
1235
1236 goto out_net_tx_busy;
1237 case -ENOMEM:
1238 u64_stats_update_begin(&ring->syncp);
1239 ring->stats.sw_err_cnt++;
1240 u64_stats_update_end(&ring->syncp);
1241 netdev_err(netdev, "no memory to xmit!\n");
1242
1243 goto out_err_tx_ok;
1244 default:
1245 break;
1246 }
1247
1248 /* No. of segments (plus a header) */
1249 seg_num = skb_shinfo(skb)->nr_frags + 1;
1250 /* Fill the first part */
1251 size = skb_headlen(skb);
1252
1253 next_to_use_head = ring->next_to_use;
1254
5188f218
PL		 1255 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1256 DESC_TYPE_SKB);
76ad4f0e 1257 if (ret)
ba3f808f 1258 goto head_fill_err;
76ad4f0e
S		 1259
1260 next_to_use_frag = ring->next_to_use;
1261 /* Fill the fragments */
1262 for (i = 1; i < seg_num; i++) {
1263 frag = &skb_shinfo(skb)->frags[i - 1];
1264 size = skb_frag_size(frag);
5188f218
PL		 1265
1266 ret = priv->ops.fill_desc(ring, frag, size,
1267 seg_num - 1 == i ? 1 : 0,
1268 DESC_TYPE_PAGE);
76ad4f0e
S		 1269
1270 if (ret)
ba3f808f 1271 goto frag_fill_err;
76ad4f0e
S		 1272 }
1273
1274 /* Complete translate all packets */
1275 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1276 netdev_tx_sent_queue(dev_queue, skb->len);
1277
1278 wmb(); /* Commit all data before submit */
1279
e4e87715 1280 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1281
1282 return NETDEV_TX_OK;
1283
ba3f808f
FL		 1284frag_fill_err:
1285 hns3_clear_desc(ring, next_to_use_frag);
76ad4f0e 1286
ba3f808f
FL		 1287head_fill_err:
1288 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1289
1290out_err_tx_ok:
1291 dev_kfree_skb_any(skb);
1292 return NETDEV_TX_OK;
1293
1294out_net_tx_busy:
1295 netif_stop_subqueue(netdev, ring_data->queue_index);
1296 smp_mb(); /* Commit all data before submit */
1297
1298 return NETDEV_TX_BUSY;
1299}
1300
1301static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1302{
9780cb97 1303 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1304 struct sockaddr *mac_addr = p;
1305 int ret;
1306
1307 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1308 return -EADDRNOTAVAIL;
1309
5ec2a51e
JS		 1310 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1311 netdev_info(netdev, "already using mac address %pM\n",
1312 mac_addr->sa_data);
1313 return 0;
1314 }
1315
59098055 1316 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1317 if (ret) {
1318 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1319 return ret;
1320 }
1321
1322 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1323
1324 return 0;
1325}
1326
26483246
XW		 1327static int hns3_nic_do_ioctl(struct net_device *netdev,
1328 struct ifreq *ifr, int cmd)
1329{
1330 struct hnae3_handle *h = hns3_get_handle(netdev);
1331
1332 if (!netif_running(netdev))
1333 return -EINVAL;
1334
1335 if (!h->ae_algo->ops->do_ioctl)
1336 return -EOPNOTSUPP;
1337
1338 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1339}
1340
76ad4f0e
S		 1341static int hns3_nic_set_features(struct net_device *netdev,
1342 netdev_features_t features)
1343{
181d454b 1344 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1345 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1346 struct hnae3_handle *h = priv->ae_handle;
052ece6d 1347 int ret;
76ad4f0e 1348
181d454b 1349 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
0bbbf15d 1350 if (features & (NETIF_F_TSO | NETIF_F_TSO6))
181d454b 1351 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
0bbbf15d 1352 else
181d454b 1353 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 1354 }
1355
5c9f6b39
PL		 1356 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1357 if (features & NETIF_F_GRO_HW)
1358 ret = h->ae_algo->ops->set_gro_en(h, true);
1359 else
1360 ret = h->ae_algo->ops->set_gro_en(h, false);
1361 if (ret)
1362 return ret;
1363 }
1364
bd368416
JS		 1365 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1366 h->ae_algo->ops->enable_vlan_filter) {
181d454b
JS		 1367 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1368 h->ae_algo->ops->enable_vlan_filter(h, true);
1369 else
1370 h->ae_algo->ops->enable_vlan_filter(h, false);
1371 }
391b5e93 1372
bd368416
JS		 1373 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1374 h->ae_algo->ops->enable_hw_strip_rxvtag) {
052ece6d
PL		 1375 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1376 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1377 else
1378 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1379
1380 if (ret)
1381 return ret;
1382 }
1383
c17852a8
JS		 1384 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1385 if (features & NETIF_F_NTUPLE)
1386 h->ae_algo->ops->enable_fd(h, true);
1387 else
1388 h->ae_algo->ops->enable_fd(h, false);
1389 }
1390
76ad4f0e
S		 1391 netdev->features = features;
1392 return 0;
1393}
1394
6c88d9d7
PL		 1395static void hns3_nic_get_stats64(struct net_device *netdev,
1396 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1397{
1398 struct hns3_nic_priv *priv = netdev_priv(netdev);
1399 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1400 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1401 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 1402 u64 rx_length_errors = 0;
1403 u64 rx_crc_errors = 0;
1404 u64 rx_multicast = 0;
76ad4f0e 1405 unsigned int start;
d3ec4ef6
JS		 1406 u64 tx_errors = 0;
1407 u64 rx_errors = 0;
76ad4f0e
S		 1408 unsigned int idx;
1409 u64 tx_bytes = 0;
1410 u64 rx_bytes = 0;
1411 u64 tx_pkts = 0;
1412 u64 rx_pkts = 0;
d2a5dca8
JS		 1413 u64 tx_drop = 0;
1414 u64 rx_drop = 0;
76ad4f0e 1415
b875cc37
JS		 1416 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1417 return;
1418
c5f65480
JS		 1419 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1420
76ad4f0e
S		 1421 for (idx = 0; idx < queue_num; idx++) {
1422 /* fetch the tx stats */
1423 ring = priv->ring_data[idx].ring;
1424 do {
d36d36ce 1425 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1426 tx_bytes += ring->stats.tx_bytes;
1427 tx_pkts += ring->stats.tx_pkts;
d2a5dca8
JS		 1428 tx_drop += ring->stats.tx_busy;
1429 tx_drop += ring->stats.sw_err_cnt;
d3ec4ef6
JS		 1430 tx_errors += ring->stats.tx_busy;
1431 tx_errors += ring->stats.sw_err_cnt;
76ad4f0e
S		 1432 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1433
1434 /* fetch the rx stats */
1435 ring = priv->ring_data[idx + queue_num].ring;
1436 do {
d36d36ce 1437 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1438 rx_bytes += ring->stats.rx_bytes;
1439 rx_pkts += ring->stats.rx_pkts;
d2a5dca8
JS		 1440 rx_drop += ring->stats.non_vld_descs;
1441 rx_drop += ring->stats.err_pkt_len;
1442 rx_drop += ring->stats.l2_err;
d3ec4ef6
JS		 1443 rx_errors += ring->stats.non_vld_descs;
1444 rx_errors += ring->stats.l2_err;
1445 rx_crc_errors += ring->stats.l2_err;
1446 rx_crc_errors += ring->stats.l3l4_csum_err;
1447 rx_multicast += ring->stats.rx_multicast;
1448 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 1449 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1450 }
1451
1452 stats->tx_bytes = tx_bytes;
1453 stats->tx_packets = tx_pkts;
1454 stats->rx_bytes = rx_bytes;
1455 stats->rx_packets = rx_pkts;
1456
d3ec4ef6
JS		 1457 stats->rx_errors = rx_errors;
1458 stats->multicast = rx_multicast;
1459 stats->rx_length_errors = rx_length_errors;
1460 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 1461 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1462
d3ec4ef6
JS		 1463 stats->tx_errors = tx_errors;
1464 stats->rx_dropped = rx_drop;
1465 stats->tx_dropped = tx_drop;
76ad4f0e
S		 1466 stats->collisions = netdev->stats.collisions;
1467 stats->rx_over_errors = netdev->stats.rx_over_errors;
1468 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1469 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1470 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1471 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1472 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1473 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1474 stats->tx_window_errors = netdev->stats.tx_window_errors;
1475 stats->rx_compressed = netdev->stats.rx_compressed;
1476 stats->tx_compressed = netdev->stats.tx_compressed;
1477}
1478
30d240df 1479static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1480{
30d240df 1481 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1482 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1483 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1484 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1485 u8 tc = mqprio_qopt->qopt.num_tc;
1486 u16 mode = mqprio_qopt->mode;
1487 u8 hw = mqprio_qopt->qopt.hw;
1488 bool if_running;
76ad4f0e
S		 1489 int ret;
1490
30d240df
YL		 1491 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1492 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1493 return -EOPNOTSUPP;
1494
76ad4f0e
S		 1495 if (tc > HNAE3_MAX_TC)
1496 return -EINVAL;
1497
76ad4f0e
S		 1498 if (!netdev)
1499 return -EINVAL;
1500
30d240df
YL		 1501 if_running = netif_running(netdev);
1502 if (if_running) {
1503 hns3_nic_net_stop(netdev);
1504 msleep(100);
76ad4f0e
S		 1505 }
1506
30d240df
YL		 1507 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1508 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e 1509 if (ret)
30d240df
YL		 1510 goto out;
1511
30d240df
YL		 1512 ret = hns3_nic_set_real_num_queue(netdev);
1513
1514out:
1515 if (if_running)
1516 hns3_nic_net_open(netdev);
1517
1518 return ret;
76ad4f0e
S		 1519}
1520
2572ac53 1521static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1522 void *type_data)
76ad4f0e 1523{
575ed7d3 1524 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1525 return -EOPNOTSUPP;
76ad4f0e 1526
30d240df 1527 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1528}
1529
1530static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1531 __be16 proto, u16 vid)
1532{
9780cb97 1533 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1534 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1535 int ret = -EIO;
1536
1537 if (h->ae_algo->ops->set_vlan_filter)
1538 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1539
681ec399
YL		 1540 if (!ret)
1541 set_bit(vid, priv->active_vlans);
1542
76ad4f0e
S		 1543 return ret;
1544}
1545
1546static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1547 __be16 proto, u16 vid)
1548{
9780cb97 1549 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1550 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1551 int ret = -EIO;
1552
1553 if (h->ae_algo->ops->set_vlan_filter)
1554 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1555
681ec399
YL		 1556 if (!ret)
1557 clear_bit(vid, priv->active_vlans);
1558
76ad4f0e
S		 1559 return ret;
1560}
1561
7fa6be4f 1562static int hns3_restore_vlan(struct net_device *netdev)
681ec399
YL		 1563{
1564 struct hns3_nic_priv *priv = netdev_priv(netdev);
7fa6be4f 1565 int ret = 0;
681ec399 1566 u16 vid;
681ec399
YL		 1567
1568 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1569 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
7fa6be4f
HT		 1570 if (ret) {
1571 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1572 vid, ret);
1573 return ret;
1574 }
681ec399 1575 }
7fa6be4f
HT		 1576
1577 return ret;
681ec399
YL		 1578}
1579
76ad4f0e
S		 1580static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1581 u8 qos, __be16 vlan_proto)
1582{
9780cb97 1583 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1584 int ret = -EIO;
1585
1586 if (h->ae_algo->ops->set_vf_vlan_filter)
1587 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1588 qos, vlan_proto);
1589
1590 return ret;
1591}
1592
a8e8b7ff
S		 1593static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1594{
9780cb97 1595 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1596 int ret;
1597
1598 if (!h->ae_algo->ops->set_mtu)
1599 return -EOPNOTSUPP;
1600
a8e8b7ff 1601 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1602 if (ret)
a8e8b7ff
S		 1603 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1604 ret);
93d8daf4
YL		 1605 else
1606 netdev->mtu = new_mtu;
5bad95a1 1607
a8e8b7ff
S		 1608 return ret;
1609}
1610
f8fa222c
L		 1611static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1612{
1613 struct hns3_nic_priv *priv = netdev_priv(ndev);
1614 struct hns3_enet_ring *tx_ring = NULL;
1615 int timeout_queue = 0;
1616 int hw_head, hw_tail;
1617 int i;
1618
1619 /* Find the stopped queue the same way the stack does */
1620 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1621 struct netdev_queue *q;
1622 unsigned long trans_start;
1623
1624 q = netdev_get_tx_queue(ndev, i);
1625 trans_start = q->trans_start;
1626 if (netif_xmit_stopped(q) &&
1627 time_after(jiffies,
1628 (trans_start + ndev->watchdog_timeo))) {
1629 timeout_queue = i;
1630 break;
1631 }
1632 }
1633
1634 if (i == ndev->num_tx_queues) {
1635 netdev_info(ndev,
1636 "no netdev TX timeout queue found, timeout count: %llu\n",
1637 priv->tx_timeout_count);
1638 return false;
1639 }
1640
1641 tx_ring = priv->ring_data[timeout_queue].ring;
1642
1643 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1644 HNS3_RING_TX_RING_HEAD_REG);
1645 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1646 HNS3_RING_TX_RING_TAIL_REG);
1647 netdev_info(ndev,
1648 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1649 priv->tx_timeout_count,
1650 timeout_queue,
1651 tx_ring->next_to_use,
1652 tx_ring->next_to_clean,
1653 hw_head,
1654 hw_tail,
1655 readl(tx_ring->tqp_vector->mask_addr));
1656
1657 return true;
1658}
1659
1660static void hns3_nic_net_timeout(struct net_device *ndev)
1661{
1662 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1663 struct hnae3_handle *h = priv->ae_handle;
1664
1665 if (!hns3_get_tx_timeo_queue_info(ndev))
1666 return;
1667
1668 priv->tx_timeout_count++;
1669
0742ed7c
HT		 1670 /* request the reset, and let the hclge to determine
1671 * which reset level should be done
1672 */
f8fa222c 1673 if (h->ae_algo->ops->reset_event)
6ae4e733 1674 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1675}
1676
76ad4f0e
S		 1677static const struct net_device_ops hns3_nic_netdev_ops = {
1678 .ndo_open = hns3_nic_net_open,
1679 .ndo_stop = hns3_nic_net_stop,
1680 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1681 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1682 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1683 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1684 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1685 .ndo_set_features = hns3_nic_set_features,
1686 .ndo_get_stats64 = hns3_nic_get_stats64,
1687 .ndo_setup_tc = hns3_nic_setup_tc,
1688 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1689 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1690 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1691 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1692};
1693
2312e050
FL		 1694static bool hns3_is_phys_func(struct pci_dev *pdev)
1695{
1696 u32 dev_id = pdev->device;
1697
1698 switch (dev_id) {
1699 case HNAE3_DEV_ID_GE:
1700 case HNAE3_DEV_ID_25GE:
1701 case HNAE3_DEV_ID_25GE_RDMA:
1702 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1703 case HNAE3_DEV_ID_50GE_RDMA:
1704 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1705 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1706 return true;
1707 case HNAE3_DEV_ID_100G_VF:
1708 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1709 return false;
1710 default:
1711 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1712 dev_id);
1713 }
1714
1715 return false;
1716}
1717
2312e050
FL		 1718static void hns3_disable_sriov(struct pci_dev *pdev)
1719{
1720 /* If our VFs are assigned we cannot shut down SR-IOV
1721 * without causing issues, so just leave the hardware
1722 * available but disabled
1723 */
1724 if (pci_vfs_assigned(pdev)) {
1725 dev_warn(&pdev->dev,
1726 "disabling driver while VFs are assigned\n");
1727 return;
1728 }
1729
1730 pci_disable_sriov(pdev);
1731}
1732
d695964d
JS		 1733static void hns3_get_dev_capability(struct pci_dev *pdev,
1734 struct hnae3_ae_dev *ae_dev)
1735{
b26a6fea 1736 if (pdev->revision >= 0x21) {
d695964d 1737 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL		 1738 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1739 }
d695964d
JS		 1740}
1741
76ad4f0e
S		 1742/* hns3_probe - Device initialization routine
1743 * @pdev: PCI device information struct
1744 * @ent: entry in hns3_pci_tbl
1745 *
1746 * hns3_probe initializes a PF identified by a pci_dev structure.
1747 * The OS initialization, configuring of the PF private structure,
1748 * and a hardware reset occur.
1749 *
1750 * Returns 0 on success, negative on failure
1751 */
1752static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1753{
1754 struct hnae3_ae_dev *ae_dev;
1755 int ret;
1756
1757 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1758 GFP_KERNEL);
1759 if (!ae_dev) {
1760 ret = -ENOMEM;
1761 return ret;
1762 }
1763
1764 ae_dev->pdev = pdev;
e92a0843 1765 ae_dev->flag = ent->driver_data;
76ad4f0e 1766 ae_dev->dev_type = HNAE3_DEV_KNIC;
6871af29 1767 ae_dev->reset_type = HNAE3_NONE_RESET;
d695964d 1768 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 1769 pci_set_drvdata(pdev, ae_dev);
1770
50fbc237 1771 hnae3_register_ae_dev(ae_dev);
2312e050 1772
2312e050 1773 return 0;
76ad4f0e
S		 1774}
1775
1776/* hns3_remove - Device removal routine
1777 * @pdev: PCI device information struct
1778 */
1779static void hns3_remove(struct pci_dev *pdev)
1780{
1781 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1782
2312e050
FL		 1783 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1784 hns3_disable_sriov(pdev);
1785
76ad4f0e 1786 hnae3_unregister_ae_dev(ae_dev);
76ad4f0e
S		 1787}
1788
fa8d82e8
PL		 1789/**
1790 * hns3_pci_sriov_configure
1791 * @pdev: pointer to a pci_dev structure
1792 * @num_vfs: number of VFs to allocate
1793 *
1794 * Enable or change the number of VFs. Called when the user updates the number
1795 * of VFs in sysfs.
1796 **/
743e1a84 1797static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 1798{
1799 int ret;
1800
1801 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1802 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1803 return -EINVAL;
1804 }
1805
1806 if (num_vfs) {
1807 ret = pci_enable_sriov(pdev, num_vfs);
1808 if (ret)
1809 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 1810 else
1811 return num_vfs;
fa8d82e8
PL		 1812 } else if (!pci_vfs_assigned(pdev)) {
1813 pci_disable_sriov(pdev);
1814 } else {
1815 dev_warn(&pdev->dev,
1816 "Unable to free VFs because some are assigned to VMs.\n");
1817 }
1818
1819 return 0;
1820}
1821
ce2c1d2e
YL		 1822static void hns3_shutdown(struct pci_dev *pdev)
1823{
1824 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1825
1826 hnae3_unregister_ae_dev(ae_dev);
1827 devm_kfree(&pdev->dev, ae_dev);
1828 pci_set_drvdata(pdev, NULL);
1829
1830 if (system_state == SYSTEM_POWER_OFF)
1831 pci_set_power_state(pdev, PCI_D3hot);
1832}
1833
5a9f0eac
SJ		 1834static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1835 pci_channel_state_t state)
1836{
1837 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1838 pci_ers_result_t ret;
1839
1840 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1841
1842 if (state == pci_channel_io_perm_failure)
1843 return PCI_ERS_RESULT_DISCONNECT;
1844
1845 if (!ae_dev) {
1846 dev_err(&pdev->dev,
1847 "Can't recover - error happened during device init\n");
1848 return PCI_ERS_RESULT_NONE;
1849 }
1850
381c356e
SJ		 1851 if (ae_dev->ops->handle_hw_ras_error)
1852 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 1853 else
1854 return PCI_ERS_RESULT_NONE;
1855
1856 return ret;
1857}
1858
6ae4e733
SJ		 1859static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1860{
1861 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1862 struct device *dev = &pdev->dev;
1863
1864 dev_info(dev, "requesting reset due to PCI error\n");
1865
1866 /* request the reset */
1867 if (ae_dev->ops->reset_event) {
1868 ae_dev->ops->reset_event(pdev, NULL);
1869 return PCI_ERS_RESULT_RECOVERED;
1870 }
1871
1872 return PCI_ERS_RESULT_DISCONNECT;
1873}
1874
6b9a97ee
HT		 1875static void hns3_reset_prepare(struct pci_dev *pdev)
1876{
1877 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1878
1879 dev_info(&pdev->dev, "hns3 flr prepare\n");
1880 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1881 ae_dev->ops->flr_prepare(ae_dev);
1882}
1883
1884static void hns3_reset_done(struct pci_dev *pdev)
1885{
1886 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1887
1888 dev_info(&pdev->dev, "hns3 flr done\n");
1889 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1890 ae_dev->ops->flr_done(ae_dev);
1891}
1892
5a9f0eac
SJ		 1893static const struct pci_error_handlers hns3_err_handler = {
1894 .error_detected = hns3_error_detected,
6ae4e733 1895 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 1896 .reset_prepare = hns3_reset_prepare,
1897 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 1898};
1899
76ad4f0e
S		 1900static struct pci_driver hns3_driver = {
1901 .name = hns3_driver_name,
1902 .id_table = hns3_pci_tbl,
1903 .probe = hns3_probe,
1904 .remove = hns3_remove,
ce2c1d2e 1905 .shutdown = hns3_shutdown,
fa8d82e8 1906 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 1907 .err_handler = &hns3_err_handler,
76ad4f0e
S		 1908};
1909
1910/* set default feature to hns3 */
1911static void hns3_set_default_feature(struct net_device *netdev)
1912{
3e85af6a
PL		 1913 struct hnae3_handle *h = hns3_get_handle(netdev);
1914 struct pci_dev *pdev = h->pdev;
1915
76ad4f0e
S		 1916 netdev->priv_flags |= IFF_UNICAST_FLT;
1917
1918 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1919 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1920 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1921 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1922 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1923
1924 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1925
1926 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1927
1928 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1929 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 1930 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1931 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1932 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1933 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1934 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1935
1936 netdev->vlan_features |=
1937 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1938 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1939 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1940 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1941 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1942
1943 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 1944 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1945 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1946 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1947 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1948 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
3e85af6a 1949
c17852a8 1950 if (pdev->revision >= 0x21) {
5c9f6b39
PL		 1951 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER |
1952 NETIF_F_GRO_HW;
1953 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 1954
1955 if (!(h->flags & HNAE3_SUPPORT_VF)) {
1956 netdev->hw_features |= NETIF_F_NTUPLE;
1957 netdev->features |= NETIF_F_NTUPLE;
1958 }
1959 }
76ad4f0e
S		 1960}
1961
1962static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1963 struct hns3_desc_cb *cb)
1964{
e4e87715 1965 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 1966 struct page *p;
1967
1968 p = dev_alloc_pages(order);
1969 if (!p)
1970 return -ENOMEM;
1971
1972 cb->priv = p;
1973 cb->page_offset = 0;
1974 cb->reuse_flag = 0;
1975 cb->buf = page_address(p);
e4e87715 1976 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 1977 cb->type = DESC_TYPE_PAGE;
1978
76ad4f0e
S		 1979 return 0;
1980}
1981
1982static void hns3_free_buffer(struct hns3_enet_ring *ring,
1983 struct hns3_desc_cb *cb)
1984{
1985 if (cb->type == DESC_TYPE_SKB)
1986 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1987 else if (!HNAE3_IS_TX_RING(ring))
1988 put_page((struct page *)cb->priv);
1989 memset(cb, 0, sizeof(*cb));
1990}
1991
1992static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1993{
1994 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1995 cb->length, ring_to_dma_dir(ring));
1996
2211f4e1 1997 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 1998 return -EIO;
1999
2000 return 0;
2001}
2002
2003static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2004 struct hns3_desc_cb *cb)
2005{
2006 if (cb->type == DESC_TYPE_SKB)
2007 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2008 ring_to_dma_dir(ring));
bcdb12b7 2009 else if (cb->length)
76ad4f0e
S		 2010 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2011 ring_to_dma_dir(ring));
2012}
2013
2014static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2015{
2016 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2017 ring->desc[i].addr = 0;
2018}
2019
2020static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2021{
2022 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2023
2024 if (!ring->desc_cb[i].dma)
2025 return;
2026
2027 hns3_buffer_detach(ring, i);
2028 hns3_free_buffer(ring, cb);
2029}
2030
2031static void hns3_free_buffers(struct hns3_enet_ring *ring)
2032{
2033 int i;
2034
2035 for (i = 0; i < ring->desc_num; i++)
2036 hns3_free_buffer_detach(ring, i);
2037}
2038
2039/* free desc along with its attached buffer */
2040static void hns3_free_desc(struct hns3_enet_ring *ring)
2041{
024cc792
HT		 2042 int size = ring->desc_num * sizeof(ring->desc[0]);
2043
76ad4f0e
S		 2044 hns3_free_buffers(ring);
2045
024cc792
HT		 2046 if (ring->desc) {
2047 dma_free_coherent(ring_to_dev(ring), size,
2048 ring->desc, ring->desc_dma_addr);
2049 ring->desc = NULL;
2050 }
76ad4f0e
S		 2051}
2052
2053static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2054{
2055 int size = ring->desc_num * sizeof(ring->desc[0]);
2056
750afb08
LC		 2057 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2058 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 2059 if (!ring->desc)
2060 return -ENOMEM;
2061
76ad4f0e
S		 2062 return 0;
2063}
2064
2065static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2066 struct hns3_desc_cb *cb)
2067{
2068 int ret;
2069
2070 ret = hns3_alloc_buffer(ring, cb);
2071 if (ret)
2072 goto out;
2073
2074 ret = hns3_map_buffer(ring, cb);
2075 if (ret)
2076 goto out_with_buf;
2077
2078 return 0;
2079
2080out_with_buf:
564883bb 2081 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2082out:
2083 return ret;
2084}
2085
2086static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2087{
2088 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2089
2090 if (ret)
2091 return ret;
2092
2093 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2094
2095 return 0;
2096}
2097
2098/* Allocate memory for raw pkg, and map with dma */
2099static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2100{
2101 int i, j, ret;
2102
2103 for (i = 0; i < ring->desc_num; i++) {
2104 ret = hns3_alloc_buffer_attach(ring, i);
2105 if (ret)
2106 goto out_buffer_fail;
2107 }
2108
2109 return 0;
2110
2111out_buffer_fail:
2112 for (j = i - 1; j >= 0; j--)
2113 hns3_free_buffer_detach(ring, j);
2114 return ret;
2115}
2116
2117/* detach a in-used buffer and replace with a reserved one */
2118static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2119 struct hns3_desc_cb *res_cb)
2120{
b9077428 2121 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2122 ring->desc_cb[i] = *res_cb;
2123 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2124 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2125}
2126
2127static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2128{
2129 ring->desc_cb[i].reuse_flag = 0;
2130 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2131 + ring->desc_cb[i].page_offset);
7d0b130c 2132 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2133}
2134
2135static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
2136 int *pkts)
2137{
2138 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2139
2140 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2141 (*bytes) += desc_cb->length;
e4e87715 2142 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
76ad4f0e
S		 2143 hns3_free_buffer_detach(ring, ring->next_to_clean);
2144
2145 ring_ptr_move_fw(ring, next_to_clean);
2146}
2147
2148static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2149{
2150 int u = ring->next_to_use;
2151 int c = ring->next_to_clean;
2152
2153 if (unlikely(h > ring->desc_num))
2154 return 0;
2155
2156 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2157}
2158
799997a3 2159void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 2160{
2161 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
7a810110 2162 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2163 struct netdev_queue *dev_queue;
2164 int bytes, pkts;
2165 int head;
2166
2167 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2168 rmb(); /* Make sure head is ready before touch any data */
2169
2170 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2171 return; /* no data to poll */
76ad4f0e 2172
0e6084aa 2173 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 2174 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2175 ring->next_to_use, ring->next_to_clean);
2176
2177 u64_stats_update_begin(&ring->syncp);
2178 ring->stats.io_err_cnt++;
2179 u64_stats_update_end(&ring->syncp);
799997a3 2180 return;
76ad4f0e
S		 2181 }
2182
2183 bytes = 0;
2184 pkts = 0;
799997a3 2185 while (head != ring->next_to_clean) {
76ad4f0e
S		 2186 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
2187 /* Issue prefetch for next Tx descriptor */
2188 prefetch(&ring->desc_cb[ring->next_to_clean]);
76ad4f0e
S		 2189 }
2190
2191 ring->tqp_vector->tx_group.total_bytes += bytes;
2192 ring->tqp_vector->tx_group.total_packets += pkts;
2193
2194 u64_stats_update_begin(&ring->syncp);
2195 ring->stats.tx_bytes += bytes;
2196 ring->stats.tx_pkts += pkts;
2197 u64_stats_update_end(&ring->syncp);
2198
2199 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2200 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2201
2202 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2203 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2204 /* Make sure that anybody stopping the queue after this
2205 * sees the new next_to_clean.
2206 */
2207 smp_mb();
7a810110
JS		 2208 if (netif_tx_queue_stopped(dev_queue) &&
2209 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2210 netif_tx_wake_queue(dev_queue);
2211 ring->stats.restart_queue++;
2212 }
2213 }
76ad4f0e
S		 2214}
2215
2216static int hns3_desc_unused(struct hns3_enet_ring *ring)
2217{
2218 int ntc = ring->next_to_clean;
2219 int ntu = ring->next_to_use;
2220
2221 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2222}
2223
2224static void
2225hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2226{
2227 struct hns3_desc_cb *desc_cb;
2228 struct hns3_desc_cb res_cbs;
2229 int i, ret;
2230
2231 for (i = 0; i < cleand_count; i++) {
2232 desc_cb = &ring->desc_cb[ring->next_to_use];
2233 if (desc_cb->reuse_flag) {
2234 u64_stats_update_begin(&ring->syncp);
2235 ring->stats.reuse_pg_cnt++;
2236 u64_stats_update_end(&ring->syncp);
2237
2238 hns3_reuse_buffer(ring, ring->next_to_use);
2239 } else {
2240 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2241 if (ret) {
2242 u64_stats_update_begin(&ring->syncp);
2243 ring->stats.sw_err_cnt++;
2244 u64_stats_update_end(&ring->syncp);
2245
2246 netdev_err(ring->tqp->handle->kinfo.netdev,
2247 "hnae reserve buffer map failed.\n");
2248 break;
2249 }
2250 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2251 }
2252
2253 ring_ptr_move_fw(ring, next_to_use);
2254 }
2255
2256 wmb(); /* Make all data has been write before submit */
2257 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2258}
2259
76ad4f0e
S		 2260static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2261 struct hns3_enet_ring *ring, int pull_len,
2262 struct hns3_desc_cb *desc_cb)
2263{
2264 struct hns3_desc *desc;
583e7281
HT		 2265 u32 truesize;
2266 int size;
76ad4f0e
S		 2267 int last_offset;
2268 bool twobufs;
2269
2270 twobufs = ((PAGE_SIZE < 8192) &&
e4e87715 2271 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
76ad4f0e
S		 2272
2273 desc = &ring->desc[ring->next_to_clean];
2274 size = le16_to_cpu(desc->rx.size);
2275
e4e87715 2276 truesize = hnae3_buf_size(ring);
f8d291f0
PL		 2277
2278 if (!twobufs)
e4e87715 2279 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
76ad4f0e
S		 2280
2281 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2282 size - pull_len, truesize);
76ad4f0e
S		 2283
2284 /* Avoid re-using remote pages,flag default unreuse */
2285 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2286 return;
2287
2288 if (twobufs) {
2289 /* If we are only owner of page we can reuse it */
2290 if (likely(page_count(desc_cb->priv) == 1)) {
2291 /* Flip page offset to other buffer */
2292 desc_cb->page_offset ^= truesize;
2293
2294 desc_cb->reuse_flag = 1;
2295 /* bump ref count on page before it is given*/
2296 get_page(desc_cb->priv);
2297 }
2298 return;
2299 }
2300
2301 /* Move offset up to the next cache line */
2302 desc_cb->page_offset += truesize;
2303
2304 if (desc_cb->page_offset <= last_offset) {
2305 desc_cb->reuse_flag = 1;
2306 /* Bump ref count on page before it is given*/
2307 get_page(desc_cb->priv);
2308 }
2309}
2310
2311static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2312 struct hns3_desc *desc)
2313{
2314 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2315 int l3_type, l4_type;
2316 u32 bd_base_info;
2317 int ol4_type;
2318 u32 l234info;
2319
2320 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2321 l234info = le32_to_cpu(desc->rx.l234_info);
2322
2323 skb->ip_summed = CHECKSUM_NONE;
2324
2325 skb_checksum_none_assert(skb);
2326
2327 if (!(netdev->features & NETIF_F_RXCSUM))
2328 return;
2329
a6d53b97
PL		 2330 /* We MUST enable hardware checksum before enabling hardware GRO */
2331 if (skb_shinfo(skb)->gso_size) {
2332 skb->ip_summed = CHECKSUM_UNNECESSARY;
2333 return;
2334 }
2335
76ad4f0e 2336 /* check if hardware has done checksum */
e4e87715 2337 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
76ad4f0e
S		 2338 return;
2339
e4e87715
PL		 2340 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2341 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2342 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2343 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
76ad4f0e
S		 2344 u64_stats_update_begin(&ring->syncp);
2345 ring->stats.l3l4_csum_err++;
2346 u64_stats_update_end(&ring->syncp);
2347
2348 return;
2349 }
2350
e4e87715
PL		 2351 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2352 HNS3_RXD_L3ID_S);
2353 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2354 HNS3_RXD_L4ID_S);
76ad4f0e 2355
e4e87715
PL		 2356 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2357 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2358 switch (ol4_type) {
2359 case HNS3_OL4_TYPE_MAC_IN_UDP:
2360 case HNS3_OL4_TYPE_NVGRE:
2361 skb->csum_level = 1;
be44b3af 2362 /* fall through */
76ad4f0e
S		 2363 case HNS3_OL4_TYPE_NO_TUN:
2364 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2365 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2366 l3_type == HNS3_L3_TYPE_IPV6) &&
2367 (l4_type == HNS3_L4_TYPE_UDP ||
2368 l4_type == HNS3_L4_TYPE_TCP ||
2369 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2370 skb->ip_summed = CHECKSUM_UNNECESSARY;
2371 break;
fa7a4bd5
JS		 2372 default:
2373 break;
76ad4f0e
S		 2374 }
2375}
2376
d43e5aca
YL		 2377static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2378{
81ae0e04
PL		 2379 if (skb_has_frag_list(skb))
2380 napi_gro_flush(&ring->tqp_vector->napi, false);
2381
d43e5aca
YL		 2382 napi_gro_receive(&ring->tqp_vector->napi, skb);
2383}
2384
701a6d6a
JS		 2385static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2386 struct hns3_desc *desc, u32 l234info,
2387 u16 *vlan_tag)
5b5455a9
PL		 2388{
2389 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL		 2390
2391 if (pdev->revision == 0x20) {
701a6d6a
JS		 2392 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2393 if (!(*vlan_tag & VLAN_VID_MASK))
2394 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2395
701a6d6a 2396 return (*vlan_tag != 0);
5b5455a9
PL		 2397 }
2398
2399#define HNS3_STRP_OUTER_VLAN 0x1
2400#define HNS3_STRP_INNER_VLAN 0x2
2401
e4e87715
PL		 2402 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2403 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2404 case HNS3_STRP_OUTER_VLAN:
701a6d6a
JS		 2405 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2406 return true;
5b5455a9 2407 case HNS3_STRP_INNER_VLAN:
701a6d6a
JS		 2408 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2409 return true;
5b5455a9 2410 default:
701a6d6a 2411 return false;
5b5455a9 2412 }
5b5455a9
PL		 2413}
2414
e5597095
PL		 2415static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2416 unsigned char *va)
2417{
2418#define HNS3_NEED_ADD_FRAG 1
2419 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2420 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2421 struct sk_buff *skb;
2422
2423 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2424 skb = ring->skb;
2425 if (unlikely(!skb)) {
2426 netdev_err(netdev, "alloc rx skb fail\n");
2427
2428 u64_stats_update_begin(&ring->syncp);
2429 ring->stats.sw_err_cnt++;
2430 u64_stats_update_end(&ring->syncp);
2431
2432 return -ENOMEM;
2433 }
2434
2435 prefetchw(skb->data);
2436
2437 ring->pending_buf = 1;
81ae0e04
PL		 2438 ring->frag_num = 0;
2439 ring->tail_skb = NULL;
e5597095
PL		 2440 if (length <= HNS3_RX_HEAD_SIZE) {
2441 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2442
2443 /* We can reuse buffer as-is, just make sure it is local */
2444 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2445 desc_cb->reuse_flag = 1;
2446 else /* This page cannot be reused so discard it */
2447 put_page(desc_cb->priv);
2448
2449 ring_ptr_move_fw(ring, next_to_clean);
2450 return 0;
2451 }
2452 u64_stats_update_begin(&ring->syncp);
2453 ring->stats.seg_pkt_cnt++;
2454 u64_stats_update_end(&ring->syncp);
2455
2456 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2457 __skb_put(skb, ring->pull_len);
81ae0e04 2458 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL		 2459 desc_cb);
2460 ring_ptr_move_fw(ring, next_to_clean);
2461
2462 return HNS3_NEED_ADD_FRAG;
2463}
2464
2465static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2466 struct sk_buff **out_skb, bool pending)
2467{
2468 struct sk_buff *skb = *out_skb;
81ae0e04
PL		 2469 struct sk_buff *head_skb = *out_skb;
2470 struct sk_buff *new_skb;
e5597095
PL		 2471 struct hns3_desc_cb *desc_cb;
2472 struct hns3_desc *pre_desc;
2473 u32 bd_base_info;
2474 int pre_bd;
2475
2476 /* if there is pending bd, the SW param next_to_clean has moved
2477 * to next and the next is NULL
2478 */
2479 if (pending) {
2480 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2481 ring->desc_num;
2482 pre_desc = &ring->desc[pre_bd];
2483 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2484 } else {
2485 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2486 }
2487
2488 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2489 desc = &ring->desc[ring->next_to_clean];
2490 desc_cb = &ring->desc_cb[ring->next_to_clean];
2491 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2492 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2493 return -ENXIO;
2494
81ae0e04
PL		 2495 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2496 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2497 HNS3_RX_HEAD_SIZE);
2498 if (unlikely(!new_skb)) {
2499 netdev_err(ring->tqp->handle->kinfo.netdev,
2500 "alloc rx skb frag fail\n");
2501 return -ENXIO;
2502 }
2503 ring->frag_num = 0;
2504
2505 if (ring->tail_skb) {
2506 ring->tail_skb->next = new_skb;
2507 ring->tail_skb = new_skb;
2508 } else {
2509 skb_shinfo(skb)->frag_list = new_skb;
2510 ring->tail_skb = new_skb;
2511 }
2512 }
2513
2514 if (ring->tail_skb) {
2515 head_skb->truesize += hnae3_buf_size(ring);
2516 head_skb->data_len += le16_to_cpu(desc->rx.size);
2517 head_skb->len += le16_to_cpu(desc->rx.size);
2518 skb = ring->tail_skb;
2519 }
2520
2521 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
e5597095
PL		 2522 ring_ptr_move_fw(ring, next_to_clean);
2523 ring->pending_buf++;
2524 }
2525
2526 return 0;
2527}
2528
a6d53b97
PL		 2529static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info,
2530 u32 bd_base_info)
2531{
2532 u16 gro_count;
2533 u32 l3_type;
2534
2535 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2536 HNS3_RXD_GRO_COUNT_S);
2537 /* if there is no HW GRO, do not set gro params */
2538 if (!gro_count)
2539 return;
2540
2541 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
2542 * to skb_shinfo(skb)->gso_segs
2543 */
2544 NAPI_GRO_CB(skb)->count = gro_count;
2545
2546 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2547 HNS3_RXD_L3ID_S);
2548 if (l3_type == HNS3_L3_TYPE_IPV4)
2549 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2550 else if (l3_type == HNS3_L3_TYPE_IPV6)
2551 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2552 else
2553 return;
2554
2555 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2556 HNS3_RXD_GRO_SIZE_M,
2557 HNS3_RXD_GRO_SIZE_S);
2558 if (skb_shinfo(skb)->gso_size)
2559 tcp_gro_complete(skb);
2560}
2561
232fc64b
PL		 2562static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2563 struct sk_buff *skb)
2564{
232fc64b
PL		 2565 struct hnae3_handle *handle = ring->tqp->handle;
2566 enum pkt_hash_types rss_type;
31a16f99
PL		 2567 struct hns3_desc *desc;
2568 int last_bd;
2569
2570 /* When driver handle the rss type, ring->next_to_clean indicates the
2571 * first descriptor of next packet, need -1 here.
2572 */
2573 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num;
2574 desc = &ring->desc[last_bd];
232fc64b
PL		 2575
2576 if (le32_to_cpu(desc->rx.rss_hash))
2577 rss_type = handle->kinfo.rss_type;
2578 else
2579 rss_type = PKT_HASH_TYPE_NONE;
2580
2581 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type);
2582}
2583
76ad4f0e 2584static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
e5597095 2585 struct sk_buff **out_skb)
76ad4f0e
S		 2586{
2587 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
c376fa1a 2588 enum hns3_pkt_l2t_type l2_frame_type;
e5597095 2589 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 2590 struct hns3_desc_cb *desc_cb;
2591 struct hns3_desc *desc;
76ad4f0e 2592 u32 bd_base_info;
76ad4f0e
S		 2593 u32 l234info;
2594 int length;
e5597095 2595 int ret;
76ad4f0e
S		 2596
2597 desc = &ring->desc[ring->next_to_clean];
2598 desc_cb = &ring->desc_cb[ring->next_to_clean];
2599
2600 prefetch(desc);
2601
846fcc83 2602 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2603 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2604
2605 /* Check valid BD */
e4e87715 2606 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
e5597095 2607 return -ENXIO;
76ad4f0e 2608
e5597095
PL		 2609 if (!skb)
2610 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S		 2611
2612 /* Prefetch first cache line of first page
2613 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2614 * line size is 64B so need to prefetch twice to make it 128B. But in
2615 * actual we can have greater size of caches with 128B Level 1 cache
2616 * lines. In such a case, single fetch would suffice to cache in the
2617 * relevant part of the header.
2618 */
e5597095 2619 prefetch(ring->va);
76ad4f0e 2620#if L1_CACHE_BYTES < 128
e5597095 2621 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S		 2622#endif
2623
e5597095
PL		 2624 if (!skb) {
2625 ret = hns3_alloc_skb(ring, length, ring->va);
2626 *out_skb = skb = ring->skb;
76ad4f0e 2627
e5597095
PL		 2628 if (ret < 0) /* alloc buffer fail */
2629 return ret;
2630 if (ret > 0) { /* need add frag */
2631 ret = hns3_add_frag(ring, desc, &skb, false);
2632 if (ret)
2633 return ret;
76ad4f0e 2634
e5597095
PL		 2635 /* As the head data may be changed when GRO enable, copy
2636 * the head data in after other data rx completed
2637 */
2638 memcpy(skb->data, ring->va,
2639 ALIGN(ring->pull_len, sizeof(long)));
2640 }
76ad4f0e 2641 } else {
e5597095
PL		 2642 ret = hns3_add_frag(ring, desc, &skb, true);
2643 if (ret)
2644 return ret;
76ad4f0e 2645
e5597095
PL		 2646 /* As the head data may be changed when GRO enable, copy
2647 * the head data in after other data rx completed
2648 */
2649 memcpy(skb->data, ring->va,
2650 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S		 2651 }
2652
5b5455a9 2653 l234info = le32_to_cpu(desc->rx.l234_info);
e5597095 2654 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
5b5455a9 2655
846fcc83
PL		 2656 /* Based on hw strategy, the tag offloaded will be stored at
2657 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2658 * in one layer tag case.
2659 */
2660 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2661 u16 vlan_tag;
2662
701a6d6a 2663 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
846fcc83
PL		 2664 __vlan_hwaccel_put_tag(skb,
2665 htons(ETH_P_8021Q),
2666 vlan_tag);
2667 }
2668
e4e87715 2669 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
76ad4f0e
S		 2670 u64_stats_update_begin(&ring->syncp);
2671 ring->stats.non_vld_descs++;
2672 u64_stats_update_end(&ring->syncp);
2673
2674 dev_kfree_skb_any(skb);
2675 return -EINVAL;
2676 }
2677
2678 if (unlikely((!desc->rx.pkt_len) ||
e4e87715 2679 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
76ad4f0e
S		 2680 u64_stats_update_begin(&ring->syncp);
2681 ring->stats.err_pkt_len++;
2682 u64_stats_update_end(&ring->syncp);
2683
2684 dev_kfree_skb_any(skb);
2685 return -EFAULT;
2686 }
2687
e4e87715 2688 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
76ad4f0e
S		 2689 u64_stats_update_begin(&ring->syncp);
2690 ring->stats.l2_err++;
2691 u64_stats_update_end(&ring->syncp);
2692
2693 dev_kfree_skb_any(skb);
2694 return -EFAULT;
2695 }
2696
c376fa1a
JS		 2697 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
2698 HNS3_RXD_DMAC_S);
76ad4f0e 2699 u64_stats_update_begin(&ring->syncp);
c376fa1a
JS		 2700 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
2701 ring->stats.rx_multicast++;
2702
76ad4f0e
S		 2703 ring->stats.rx_pkts++;
2704 ring->stats.rx_bytes += skb->len;
2705 u64_stats_update_end(&ring->syncp);
2706
2707 ring->tqp_vector->rx_group.total_bytes += skb->len;
2708
a6d53b97
PL		 2709 /* This is needed in order to enable forwarding support */
2710 hns3_set_gro_param(skb, l234info, bd_base_info);
2711
76ad4f0e 2712 hns3_rx_checksum(ring, skb, desc);
e5597095 2713 *out_skb = skb;
232fc64b
PL		 2714 hns3_set_rx_skb_rss_type(ring, skb);
2715
76ad4f0e
S		 2716 return 0;
2717}
2718
d43e5aca
YL		 2719int hns3_clean_rx_ring(
2720 struct hns3_enet_ring *ring, int budget,
2721 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2722{
2723#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2724 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2725 int recv_pkts, recv_bds, clean_count, err;
e5597095
PL		 2726 int unused_count = hns3_desc_unused(ring) - ring->pending_buf;
2727 struct sk_buff *skb = ring->skb;
2728 int num;
76ad4f0e
S		 2729
2730 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2731 rmb(); /* Make sure num taken effect before the other data is touched */
2732
2733 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2734 num -= unused_count;
2735
2736 while (recv_pkts < budget && recv_bds < num) {
2737 /* Reuse or realloc buffers */
2738 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2739 hns3_nic_alloc_rx_buffers(ring,
2740 clean_count + unused_count);
2741 clean_count = 0;
e5597095
PL		 2742 unused_count = hns3_desc_unused(ring) -
2743 ring->pending_buf;
76ad4f0e
S		 2744 }
2745
2746 /* Poll one pkt */
e5597095 2747 err = hns3_handle_rx_bd(ring, &skb);
76ad4f0e
S		 2748 if (unlikely(!skb)) /* This fault cannot be repaired */
2749 goto out;
2750
e5597095
PL		 2751 if (err == -ENXIO) { /* Do not get FE for the packet */
2752 goto out;
2753 } else if (unlikely(err)) { /* Do jump the err */
2754 recv_bds += ring->pending_buf;
2755 clean_count += ring->pending_buf;
2756 ring->skb = NULL;
2757 ring->pending_buf = 0;
76ad4f0e
S		 2758 continue;
2759 }
2760
2761 /* Do update ip stack process */
2762 skb->protocol = eth_type_trans(skb, netdev);
d43e5aca 2763 rx_fn(ring, skb);
e5597095
PL		 2764 recv_bds += ring->pending_buf;
2765 clean_count += ring->pending_buf;
2766 ring->skb = NULL;
2767 ring->pending_buf = 0;
76ad4f0e
S		 2768
2769 recv_pkts++;
2770 }
2771
2772out:
2773 /* Make all data has been write before submit */
2774 if (clean_count + unused_count > 0)
2775 hns3_nic_alloc_rx_buffers(ring,
2776 clean_count + unused_count);
2777
2778 return recv_pkts;
2779}
2780
2781static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2782{
a95e1f86
FL		 2783 struct hns3_enet_tqp_vector *tqp_vector =
2784 ring_group->ring->tqp_vector;
76ad4f0e 2785 enum hns3_flow_level_range new_flow_level;
a95e1f86
FL		 2786 int packets_per_msecs;
2787 int bytes_per_msecs;
2788 u32 time_passed_ms;
76ad4f0e 2789 u16 new_int_gl;
76ad4f0e 2790
a95e1f86 2791 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
76ad4f0e
S		 2792 return false;
2793
2794 if (ring_group->total_packets == 0) {
9bc727a9
YL		 2795 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2796 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2797 return true;
2798 }
2799
2800 /* Simple throttlerate management
2801 * 0-10MB/s lower (50000 ints/s)
2802 * 10-20MB/s middle (20000 ints/s)
2803 * 20-1249MB/s high (18000 ints/s)
2804 * > 40000pps ultra (8000 ints/s)
2805 */
9bc727a9
YL		 2806 new_flow_level = ring_group->coal.flow_level;
2807 new_int_gl = ring_group->coal.int_gl;
a95e1f86
FL		 2808 time_passed_ms =
2809 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2810
2811 if (!time_passed_ms)
2812 return false;
2813
2814 do_div(ring_group->total_packets, time_passed_ms);
2815 packets_per_msecs = ring_group->total_packets;
2816
2817 do_div(ring_group->total_bytes, time_passed_ms);
2818 bytes_per_msecs = ring_group->total_bytes;
2819
2820#define HNS3_RX_LOW_BYTE_RATE 10000
2821#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2822
2823 switch (new_flow_level) {
2824 case HNS3_FLOW_LOW:
a95e1f86 2825 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2826 new_flow_level = HNS3_FLOW_MID;
2827 break;
2828 case HNS3_FLOW_MID:
a95e1f86 2829 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2830 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 2831 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2832 new_flow_level = HNS3_FLOW_LOW;
2833 break;
2834 case HNS3_FLOW_HIGH:
2835 case HNS3_FLOW_ULTRA:
2836 default:
a95e1f86 2837 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2838 new_flow_level = HNS3_FLOW_MID;
2839 break;
2840 }
2841
a95e1f86
FL		 2842#define HNS3_RX_ULTRA_PACKET_RATE 40
2843
2844 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2845 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2846 new_flow_level = HNS3_FLOW_ULTRA;
2847
2848 switch (new_flow_level) {
2849 case HNS3_FLOW_LOW:
2850 new_int_gl = HNS3_INT_GL_50K;
2851 break;
2852 case HNS3_FLOW_MID:
2853 new_int_gl = HNS3_INT_GL_20K;
2854 break;
2855 case HNS3_FLOW_HIGH:
2856 new_int_gl = HNS3_INT_GL_18K;
2857 break;
2858 case HNS3_FLOW_ULTRA:
2859 new_int_gl = HNS3_INT_GL_8K;
2860 break;
2861 default:
2862 break;
2863 }
2864
2865 ring_group->total_bytes = 0;
2866 ring_group->total_packets = 0;
9bc727a9
YL		 2867 ring_group->coal.flow_level = new_flow_level;
2868 if (new_int_gl != ring_group->coal.int_gl) {
2869 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 2870 return true;
2871 }
2872 return false;
2873}
2874
2875static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2876{
8b1ff1ea
FL		 2877 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2878 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2879 bool rx_update, tx_update;
2880
7445565c
PL		 2881 /* update param every 1000ms */
2882 if (time_before(jiffies,
2883 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 2884 return;
cd9d187b 2885
9bc727a9 2886 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 2887 rx_update = hns3_get_new_int_gl(rx_group);
2888 if (rx_update)
2889 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 2890 rx_group->coal.int_gl);
8b1ff1ea
FL		 2891 }
2892
9bc727a9 2893 if (tx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 2894 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2895 if (tx_update)
2896 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 2897 tx_group->coal.int_gl);
76ad4f0e 2898 }
cd9d187b 2899
a95e1f86 2900 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 2901}
2902
2903static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2904{
ff0699e0 2905 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 2906 struct hns3_enet_ring *ring;
2907 int rx_pkt_total = 0;
2908
2909 struct hns3_enet_tqp_vector *tqp_vector =
2910 container_of(napi, struct hns3_enet_tqp_vector, napi);
2911 bool clean_complete = true;
2912 int rx_budget;
2913
ff0699e0
HT		 2914 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2915 napi_complete(napi);
2916 return 0;
2917 }
2918
76ad4f0e
S		 2919 /* Since the actual Tx work is minimal, we can give the Tx a larger
2920 * budget and be more aggressive about cleaning up the Tx descriptors.
2921 */
799997a3
PL		 2922 hns3_for_each_ring(ring, tqp_vector->tx_group)
2923 hns3_clean_tx_ring(ring);
76ad4f0e
S		 2924
2925 /* make sure rx ring budget not smaller than 1 */
2926 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2927
2928 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 2929 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2930 hns3_rx_skb);
76ad4f0e
S		 2931
2932 if (rx_cleaned >= rx_budget)
2933 clean_complete = false;
2934
2935 rx_pkt_total += rx_cleaned;
2936 }
2937
2938 tqp_vector->rx_group.total_packets += rx_pkt_total;
2939
2940 if (!clean_complete)
2941 return budget;
2942
531eba0f
HT		 2943 if (napi_complete(napi) &&
2944 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 2945 hns3_update_new_int_gl(tqp_vector);
2946 hns3_mask_vector_irq(tqp_vector, 1);
2947 }
76ad4f0e
S		 2948
2949 return rx_pkt_total;
2950}
2951
2952static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2953 struct hnae3_ring_chain_node *head)
2954{
2955 struct pci_dev *pdev = tqp_vector->handle->pdev;
2956 struct hnae3_ring_chain_node *cur_chain = head;
2957 struct hnae3_ring_chain_node *chain;
2958 struct hns3_enet_ring *tx_ring;
2959 struct hns3_enet_ring *rx_ring;
2960
2961 tx_ring = tqp_vector->tx_group.ring;
2962 if (tx_ring) {
2963 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 2964 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2965 HNAE3_RING_TYPE_TX);
2966 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2967 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 2968
2969 cur_chain->next = NULL;
2970
2971 while (tx_ring->next) {
2972 tx_ring = tx_ring->next;
2973
2974 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2975 GFP_KERNEL);
2976 if (!chain)
73b907a0 2977 goto err_free_chain;
76ad4f0e
S		 2978
2979 cur_chain->next = chain;
2980 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 2981 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2982 HNAE3_RING_TYPE_TX);
2983 hnae3_set_field(chain->int_gl_idx,
2984 HNAE3_RING_GL_IDX_M,
2985 HNAE3_RING_GL_IDX_S,
2986 HNAE3_RING_GL_TX);
76ad4f0e
S		 2987
2988 cur_chain = chain;
2989 }
2990 }
2991
2992 rx_ring = tqp_vector->rx_group.ring;
2993 if (!tx_ring && rx_ring) {
2994 cur_chain->next = NULL;
2995 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 2996 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2997 HNAE3_RING_TYPE_RX);
2998 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2999 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 3000
3001 rx_ring = rx_ring->next;
3002 }
3003
3004 while (rx_ring) {
3005 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3006 if (!chain)
73b907a0 3007 goto err_free_chain;
76ad4f0e
S		 3008
3009 cur_chain->next = chain;
3010 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3011 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3012 HNAE3_RING_TYPE_RX);
3013 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3014 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3015
76ad4f0e
S		 3016 cur_chain = chain;
3017
3018 rx_ring = rx_ring->next;
3019 }
3020
3021 return 0;
73b907a0
HT		 3022
3023err_free_chain:
3024 cur_chain = head->next;
3025 while (cur_chain) {
3026 chain = cur_chain->next;
cda69d24 3027 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 3028 cur_chain = chain;
3029 }
cda69d24 3030 head->next = NULL;
73b907a0
HT		 3031
3032 return -ENOMEM;
76ad4f0e
S		 3033}
3034
3035static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3036 struct hnae3_ring_chain_node *head)
3037{
3038 struct pci_dev *pdev = tqp_vector->handle->pdev;
3039 struct hnae3_ring_chain_node *chain_tmp, *chain;
3040
3041 chain = head->next;
3042
3043 while (chain) {
3044 chain_tmp = chain->next;
3045 devm_kfree(&pdev->dev, chain);
3046 chain = chain_tmp;
3047 }
3048}
3049
3050static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3051 struct hns3_enet_ring *ring)
3052{
3053 ring->next = group->ring;
3054 group->ring = ring;
3055
3056 group->count++;
3057}
3058
874bff0b
PL		 3059static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3060{
3061 struct pci_dev *pdev = priv->ae_handle->pdev;
3062 struct hns3_enet_tqp_vector *tqp_vector;
3063 int num_vectors = priv->vector_num;
3064 int numa_node;
3065 int vector_i;
3066
3067 numa_node = dev_to_node(&pdev->dev);
3068
3069 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3070 tqp_vector = &priv->tqp_vector[vector_i];
3071 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3072 &tqp_vector->affinity_mask);
3073 }
3074}
3075
76ad4f0e
S		 3076static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3077{
3078 struct hnae3_ring_chain_node vector_ring_chain;
3079 struct hnae3_handle *h = priv->ae_handle;
3080 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3081 int ret = 0;
ece4bf46 3082 int i;
76ad4f0e 3083
874bff0b
PL		 3084 hns3_nic_set_cpumask(priv);
3085
dd38c726
YL		 3086 for (i = 0; i < priv->vector_num; i++) {
3087 tqp_vector = &priv->tqp_vector[i];
3088 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3089 tqp_vector->num_tqps = 0;
3090 }
76ad4f0e 3091
dd38c726
YL		 3092 for (i = 0; i < h->kinfo.num_tqps; i++) {
3093 u16 vector_i = i % priv->vector_num;
3094 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3095
3096 tqp_vector = &priv->tqp_vector[vector_i];
3097
3098 hns3_add_ring_to_group(&tqp_vector->tx_group,
3099 priv->ring_data[i].ring);
3100
3101 hns3_add_ring_to_group(&tqp_vector->rx_group,
3102 priv->ring_data[i + tqp_num].ring);
3103
76ad4f0e
S		 3104 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3105 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
dd38c726 3106 tqp_vector->num_tqps++;
76ad4f0e
S		 3107 }
3108
dd38c726 3109 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3110 tqp_vector = &priv->tqp_vector[i];
3111
3112 tqp_vector->rx_group.total_bytes = 0;
3113 tqp_vector->rx_group.total_packets = 0;
3114 tqp_vector->tx_group.total_bytes = 0;
3115 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3116 tqp_vector->handle = h;
3117
3118 ret = hns3_get_vector_ring_chain(tqp_vector,
3119 &vector_ring_chain);
3120 if (ret)
cda69d24 3121 goto map_ring_fail;
76ad4f0e
S		 3122
3123 ret = h->ae_algo->ops->map_ring_to_vector(h,
3124 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3125
3126 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3127
dd38c726 3128 if (ret)
ece4bf46 3129 goto map_ring_fail;
dd38c726 3130
76ad4f0e
S		 3131 netif_napi_add(priv->netdev, &tqp_vector->napi,
3132 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3133 }
3134
dd38c726 3135 return 0;
ece4bf46
HT		 3136
3137map_ring_fail:
3138 while (i--)
3139 netif_napi_del(&priv->tqp_vector[i].napi);
3140
3141 return ret;
dd38c726
YL		 3142}
3143
3144static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3145{
75edb610
JS		 3146#define HNS3_VECTOR_PF_MAX_NUM 64
3147
dd38c726
YL		 3148 struct hnae3_handle *h = priv->ae_handle;
3149 struct hns3_enet_tqp_vector *tqp_vector;
3150 struct hnae3_vector_info *vector;
3151 struct pci_dev *pdev = h->pdev;
3152 u16 tqp_num = h->kinfo.num_tqps;
3153 u16 vector_num;
3154 int ret = 0;
3155 u16 i;
3156
3157 /* RSS size, cpu online and vector_num should be the same */
3158 /* Should consider 2p/4p later */
3159 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS		 3160 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3161
dd38c726
YL		 3162 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3163 GFP_KERNEL);
3164 if (!vector)
3165 return -ENOMEM;
3166
3167 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3168
3169 priv->vector_num = vector_num;
3170 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3171 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3172 GFP_KERNEL);
3173 if (!priv->tqp_vector) {
3174 ret = -ENOMEM;
3175 goto out;
3176 }
3177
3178 for (i = 0; i < priv->vector_num; i++) {
3179 tqp_vector = &priv->tqp_vector[i];
3180 tqp_vector->idx = i;
3181 tqp_vector->mask_addr = vector[i].io_addr;
3182 tqp_vector->vector_irq = vector[i].vector;
3183 hns3_vector_gl_rl_init(tqp_vector, priv);
3184 }
3185
76ad4f0e
S		 3186out:
3187 devm_kfree(&pdev->dev, vector);
3188 return ret;
3189}
3190
dd38c726
YL		 3191static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3192{
3193 group->ring = NULL;
3194 group->count = 0;
3195}
3196
76ad4f0e
S		 3197static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3198{
3199 struct hnae3_ring_chain_node vector_ring_chain;
3200 struct hnae3_handle *h = priv->ae_handle;
3201 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 3202 int i, ret;
3203
3204 for (i = 0; i < priv->vector_num; i++) {
3205 tqp_vector = &priv->tqp_vector[i];
3206
2c9dd668
HT		 3207 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3208 continue;
3209
76ad4f0e
S		 3210 ret = hns3_get_vector_ring_chain(tqp_vector,
3211 &vector_ring_chain);
3212 if (ret)
3213 return ret;
3214
3215 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
3216 tqp_vector->vector_irq, &vector_ring_chain);
3217 if (ret)
3218 return ret;
3219
3220 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3221
ae6017a7
HT		 3222 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3223 irq_set_affinity_notifier(tqp_vector->vector_irq,
3224 NULL);
3225 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3226 free_irq(tqp_vector->vector_irq, tqp_vector);
3227 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S		 3228 }
3229
dd38c726
YL		 3230 hns3_clear_ring_group(&tqp_vector->rx_group);
3231 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3232 netif_napi_del(&priv->tqp_vector[i].napi);
3233 }
3234
dd38c726
YL		 3235 return 0;
3236}
3237
3238static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3239{
3240 struct hnae3_handle *h = priv->ae_handle;
3241 struct pci_dev *pdev = h->pdev;
3242 int i, ret;
3243
3244 for (i = 0; i < priv->vector_num; i++) {
3245 struct hns3_enet_tqp_vector *tqp_vector;
3246
3247 tqp_vector = &priv->tqp_vector[i];
3248 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3249 if (ret)
3250 return ret;
3251 }
76ad4f0e 3252
dd38c726 3253 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3254 return 0;
3255}
3256
3257static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3258 int ring_type)
3259{
3260 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3261 int queue_num = priv->ae_handle->kinfo.num_tqps;
2c9dd668 3262 int desc_num = priv->ae_handle->kinfo.num_desc;
76ad4f0e
S		 3263 struct pci_dev *pdev = priv->ae_handle->pdev;
3264 struct hns3_enet_ring *ring;
3265
3266 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3267 if (!ring)
3268 return -ENOMEM;
3269
3270 if (ring_type == HNAE3_RING_TYPE_TX) {
3271 ring_data[q->tqp_index].ring = ring;
66b44730 3272 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 3273 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3274 } else {
3275 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 3276 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 3277 ring->io_base = q->io_base;
3278 }
3279
e4e87715 3280 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3281
76ad4f0e
S		 3282 ring->tqp = q;
3283 ring->desc = NULL;
3284 ring->desc_cb = NULL;
3285 ring->dev = priv->dev;
3286 ring->desc_dma_addr = 0;
3287 ring->buf_size = q->buf_size;
2c9dd668 3288 ring->desc_num = desc_num;
76ad4f0e
S		 3289 ring->next_to_use = 0;
3290 ring->next_to_clean = 0;
3291
3292 return 0;
3293}
3294
3295static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3296 struct hns3_nic_priv *priv)
3297{
3298 int ret;
3299
3300 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3301 if (ret)
3302 return ret;
3303
3304 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
73b907a0
HT		 3305 if (ret) {
3306 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
76ad4f0e 3307 return ret;
73b907a0 3308 }
76ad4f0e
S		 3309
3310 return 0;
3311}
3312
3313static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3314{
3315 struct hnae3_handle *h = priv->ae_handle;
3316 struct pci_dev *pdev = h->pdev;
3317 int i, ret;
3318
a86854d0
KC		 3319 priv->ring_data = devm_kzalloc(&pdev->dev,
3320 array3_size(h->kinfo.num_tqps,
3321 sizeof(*priv->ring_data),
3322 2),
76ad4f0e
S		 3323 GFP_KERNEL);
3324 if (!priv->ring_data)
3325 return -ENOMEM;
3326
3327 for (i = 0; i < h->kinfo.num_tqps; i++) {
3328 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3329 if (ret)
3330 goto err;
3331 }
3332
3333 return 0;
3334err:
73b907a0
HT		 3335 while (i--) {
3336 devm_kfree(priv->dev, priv->ring_data[i].ring);
3337 devm_kfree(priv->dev,
3338 priv->ring_data[i + h->kinfo.num_tqps].ring);
3339 }
3340
76ad4f0e
S		 3341 devm_kfree(&pdev->dev, priv->ring_data);
3342 return ret;
3343}
3344
09f2af64
PL		 3345static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3346{
3347 struct hnae3_handle *h = priv->ae_handle;
3348 int i;
3349
3350 for (i = 0; i < h->kinfo.num_tqps; i++) {
3351 devm_kfree(priv->dev, priv->ring_data[i].ring);
3352 devm_kfree(priv->dev,
3353 priv->ring_data[i + h->kinfo.num_tqps].ring);
3354 }
3355 devm_kfree(priv->dev, priv->ring_data);
3356}
3357
76ad4f0e
S		 3358static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3359{
3360 int ret;
3361
3362 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3363 return -EINVAL;
3364
3365 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
3366 GFP_KERNEL);
3367 if (!ring->desc_cb) {
3368 ret = -ENOMEM;
3369 goto out;
3370 }
3371
3372 ret = hns3_alloc_desc(ring);
3373 if (ret)
3374 goto out_with_desc_cb;
3375
3376 if (!HNAE3_IS_TX_RING(ring)) {
3377 ret = hns3_alloc_ring_buffers(ring);
3378 if (ret)
3379 goto out_with_desc;
3380 }
3381
3382 return 0;
3383
3384out_with_desc:
3385 hns3_free_desc(ring);
3386out_with_desc_cb:
3387 kfree(ring->desc_cb);
3388 ring->desc_cb = NULL;
3389out:
3390 return ret;
3391}
3392
3393static void hns3_fini_ring(struct hns3_enet_ring *ring)
3394{
3395 hns3_free_desc(ring);
3396 kfree(ring->desc_cb);
3397 ring->desc_cb = NULL;
3398 ring->next_to_clean = 0;
3399 ring->next_to_use = 0;
3400}
3401
1db9b1bf 3402static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3403{
3404 int bd_size_type;
3405
3406 switch (buf_size) {
3407 case 512:
3408 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3409 break;
3410 case 1024:
3411 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3412 break;
3413 case 2048:
3414 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3415 break;
3416 case 4096:
3417 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3418 break;
3419 default:
3420 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3421 }
3422
3423 return bd_size_type;
3424}
3425
3426static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3427{
3428 dma_addr_t dma = ring->desc_dma_addr;
3429 struct hnae3_queue *q = ring->tqp;
3430
3431 if (!HNAE3_IS_TX_RING(ring)) {
3432 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3433 (u32)dma);
3434 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3435 (u32)((dma >> 31) >> 1));
3436
3437 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3438 hns3_buf_size2type(ring->buf_size));
3439 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3440 ring->desc_num / 8 - 1);
3441
3442 } else {
3443 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3444 (u32)dma);
3445 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3446 (u32)((dma >> 31) >> 1));
3447
76ad4f0e
S		 3448 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3449 ring->desc_num / 8 - 1);
3450 }
3451}
3452
1c772154
YL		 3453static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3454{
3455 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3456 int i;
3457
3458 for (i = 0; i < HNAE3_MAX_TC; i++) {
3459 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3460 int j;
3461
3462 if (!tc_info->enable)
3463 continue;
3464
3465 for (j = 0; j < tc_info->tqp_count; j++) {
3466 struct hnae3_queue *q;
3467
3468 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3469 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3470 tc_info->tc);
3471 }
3472 }
3473}
3474
5668abda 3475int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3476{
3477 struct hnae3_handle *h = priv->ae_handle;
3478 int ring_num = h->kinfo.num_tqps * 2;
3479 int i, j;
3480 int ret;
3481
3482 for (i = 0; i < ring_num; i++) {
3483 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3484 if (ret) {
3485 dev_err(priv->dev,
3486 "Alloc ring memory fail! ret=%d\n", ret);
3487 goto out_when_alloc_ring_memory;
3488 }
3489
76ad4f0e
S		 3490 u64_stats_init(&priv->ring_data[i].ring->syncp);
3491 }
3492
3493 return 0;
3494
3495out_when_alloc_ring_memory:
3496 for (j = i - 1; j >= 0; j--)
ee83f776 3497 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3498
3499 return -ENOMEM;
3500}
3501
5668abda 3502int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3503{
3504 struct hnae3_handle *h = priv->ae_handle;
3505 int i;
3506
3507 for (i = 0; i < h->kinfo.num_tqps; i++) {
76ad4f0e
S		 3508 hns3_fini_ring(priv->ring_data[i].ring);
3509 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3510 }
76ad4f0e
S		 3511 return 0;
3512}
3513
3514/* Set mac addr if it is configured. or leave it to the AE driver */
7fa6be4f 3515static int hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3516{
3517 struct hns3_nic_priv *priv = netdev_priv(netdev);
3518 struct hnae3_handle *h = priv->ae_handle;
3519 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3520 int ret = 0;
76ad4f0e 3521
f09555ff 3522 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3523 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3524 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3525 }
3526
3527 /* Check if the MAC address is valid, if not get a random one */
3528 if (!is_valid_ether_addr(netdev->dev_addr)) {
3529 eth_hw_addr_random(netdev);
3530 dev_warn(priv->dev, "using random MAC address %pM\n",
3531 netdev->dev_addr);
76ad4f0e 3532 }
139e8792
L		 3533
3534 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3535 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3536
7fa6be4f 3537 return ret;
76ad4f0e
S		 3538}
3539
6871af29
JS		 3540static int hns3_restore_fd_rules(struct net_device *netdev)
3541{
3542 struct hnae3_handle *h = hns3_get_handle(netdev);
3543 int ret = 0;
3544
3545 if (h->ae_algo->ops->restore_fd_rules)
3546 ret = h->ae_algo->ops->restore_fd_rules(h);
3547
3548 return ret;
3549}
3550
3551static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3552{
3553 struct hnae3_handle *h = hns3_get_handle(netdev);
3554
3555 if (h->ae_algo->ops->del_all_fd_entries)
3556 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3557}
3558
76ad4f0e
S		 3559static void hns3_nic_set_priv_ops(struct net_device *netdev)
3560{
3561 struct hns3_nic_priv *priv = netdev_priv(netdev);
3562
0bbbf15d 3563 priv->ops.fill_desc = hns3_fill_desc;
76ad4f0e 3564 if ((netdev->features & NETIF_F_TSO) ||
0bbbf15d 3565 (netdev->features & NETIF_F_TSO6))
76ad4f0e 3566 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
0bbbf15d 3567 else
76ad4f0e 3568 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 3569}
3570
a6d818e3
YL		 3571static int hns3_client_start(struct hnae3_handle *handle)
3572{
3573 if (!handle->ae_algo->ops->client_start)
3574 return 0;
3575
3576 return handle->ae_algo->ops->client_start(handle);
3577}
3578
3579static void hns3_client_stop(struct hnae3_handle *handle)
3580{
3581 if (!handle->ae_algo->ops->client_stop)
3582 return;
3583
3584 handle->ae_algo->ops->client_stop(handle);
3585}
3586
76ad4f0e
S		 3587static int hns3_client_init(struct hnae3_handle *handle)
3588{
3589 struct pci_dev *pdev = handle->pdev;
0d43bf45 3590 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3591 struct hns3_nic_priv *priv;
3592 struct net_device *netdev;
3593 int ret;
3594
0d43bf45
HT		 3595 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3596 &max_rss_size);
3597 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3598 if (!netdev)
3599 return -ENOMEM;
3600
3601 priv = netdev_priv(netdev);
3602 priv->dev = &pdev->dev;
3603 priv->netdev = netdev;
3604 priv->ae_handle = handle;
f8fa222c 3605 priv->tx_timeout_count = 0;
76ad4f0e
S		 3606
3607 handle->kinfo.netdev = netdev;
3608 handle->priv = (void *)priv;
3609
f09555ff 3610 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3611
3612 hns3_set_default_feature(netdev);
3613
3614 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3615 netdev->priv_flags |= IFF_UNICAST_FLT;
3616 netdev->netdev_ops = &hns3_nic_netdev_ops;
3617 SET_NETDEV_DEV(netdev, &pdev->dev);
3618 hns3_ethtool_set_ops(netdev);
3619 hns3_nic_set_priv_ops(netdev);
3620
3621 /* Carrier off reporting is important to ethtool even BEFORE open */
3622 netif_carrier_off(netdev);
3623
3624 ret = hns3_get_ring_config(priv);
3625 if (ret) {
3626 ret = -ENOMEM;
3627 goto out_get_ring_cfg;
3628 }
3629
dd38c726
YL		 3630 ret = hns3_nic_alloc_vector_data(priv);
3631 if (ret) {
3632 ret = -ENOMEM;
3633 goto out_alloc_vector_data;
3634 }
3635
76ad4f0e
S		 3636 ret = hns3_nic_init_vector_data(priv);
3637 if (ret) {
3638 ret = -ENOMEM;
3639 goto out_init_vector_data;
3640 }
3641
3642 ret = hns3_init_all_ring(priv);
3643 if (ret) {
3644 ret = -ENOMEM;
3645 goto out_init_ring_data;
3646 }
3647
3648 ret = register_netdev(netdev);
3649 if (ret) {
3650 dev_err(priv->dev, "probe register netdev fail!\n");
3651 goto out_reg_netdev_fail;
3652 }
3653
a6d818e3
YL		 3654 ret = hns3_client_start(handle);
3655 if (ret) {
3656 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
3657 goto out_reg_netdev_fail;
3658 }
3659
986743db
YL		 3660 hns3_dcbnl_setup(handle);
3661
b2292360 3662 hns3_dbg_init(handle);
3663
a0b43717 3664 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 3665 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 3666
814da63c
HT		 3667 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3668
76ad4f0e
S		 3669 return ret;
3670
3671out_reg_netdev_fail:
3672out_init_ring_data:
3673 (void)hns3_nic_uninit_vector_data(priv);
76ad4f0e 3674out_init_vector_data:
dd38c726
YL		 3675 hns3_nic_dealloc_vector_data(priv);
3676out_alloc_vector_data:
3677 priv->ring_data = NULL;
76ad4f0e
S		 3678out_get_ring_cfg:
3679 priv->ae_handle = NULL;
3680 free_netdev(netdev);
3681 return ret;
3682}
3683
3684static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3685{
3686 struct net_device *netdev = handle->kinfo.netdev;
3687 struct hns3_nic_priv *priv = netdev_priv(netdev);
3688 int ret;
3689
a6d818e3
YL		 3690 hns3_client_stop(handle);
3691
f05e2109
JS		 3692 hns3_remove_hw_addr(netdev);
3693
76ad4f0e
S		 3694 if (netdev->reg_state != NETREG_UNINITIALIZED)
3695 unregister_netdev(netdev);
3696
814da63c
HT		 3697 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3698 netdev_warn(netdev, "already uninitialized\n");
3699 goto out_netdev_free;
3700 }
3701
dc5e6064
JS		 3702 hns3_del_all_fd_rules(netdev, true);
3703
7b763f3f
FL		 3704 hns3_force_clear_all_rx_ring(handle);
3705
76ad4f0e
S		 3706 ret = hns3_nic_uninit_vector_data(priv);
3707 if (ret)
3708 netdev_err(netdev, "uninit vector error\n");
3709
dd38c726
YL		 3710 ret = hns3_nic_dealloc_vector_data(priv);
3711 if (ret)
3712 netdev_err(netdev, "dealloc vector error\n");
3713
76ad4f0e
S		 3714 ret = hns3_uninit_all_ring(priv);
3715 if (ret)
3716 netdev_err(netdev, "uninit ring error\n");
3717
ec777890
YL		 3718 hns3_put_ring_config(priv);
3719
b2292360 3720 hns3_dbg_uninit(handle);
3721
76ad4f0e
S		 3722 priv->ring_data = NULL;
3723
814da63c 3724out_netdev_free:
76ad4f0e
S		 3725 free_netdev(netdev);
3726}
3727
3728static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3729{
3730 struct net_device *netdev = handle->kinfo.netdev;
3731
3732 if (!netdev)
3733 return;
3734
3735 if (linkup) {
3736 netif_carrier_on(netdev);
3737 netif_tx_wake_all_queues(netdev);
3738 netdev_info(netdev, "link up\n");
3739 } else {
3740 netif_carrier_off(netdev);
3741 netif_tx_stop_all_queues(netdev);
3742 netdev_info(netdev, "link down\n");
3743 }
3744}
3745
9df8f79a
YL		 3746static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3747{
3748 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3749 struct net_device *ndev = kinfo->netdev;
9df8f79a 3750 int ret;
9df8f79a
YL		 3751
3752 if (tc > HNAE3_MAX_TC)
3753 return -EINVAL;
3754
3755 if (!ndev)
3756 return -ENODEV;
3757
9df8f79a
YL		 3758 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3759 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3760 if (ret)
af013903 3761 return ret;
9df8f79a 3762
9df8f79a
YL		 3763 ret = hns3_nic_set_real_num_queue(ndev);
3764
9df8f79a
YL		 3765 return ret;
3766}
3767
7fa6be4f 3768static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L		 3769{
3770 struct netdev_hw_addr_list *list;
3771 struct netdev_hw_addr *ha, *tmp;
7fa6be4f 3772 int ret = 0;
bb6b94a8
L		 3773
3774 /* go through and sync uc_addr entries to the device */
3775 list = &ndev->uc;
7fa6be4f
HT		 3776 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3777 ret = hns3_nic_uc_sync(ndev, ha->addr);
3778 if (ret)
3779 return ret;
3780 }
bb6b94a8
L		 3781
3782 /* go through and sync mc_addr entries to the device */
3783 list = &ndev->mc;
7fa6be4f
HT		 3784 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3785 ret = hns3_nic_mc_sync(ndev, ha->addr);
3786 if (ret)
3787 return ret;
3788 }
3789
3790 return ret;
bb6b94a8
L		 3791}
3792
f05e2109
JS		 3793static void hns3_remove_hw_addr(struct net_device *netdev)
3794{
3795 struct netdev_hw_addr_list *list;
3796 struct netdev_hw_addr *ha, *tmp;
3797
3798 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3799
3800 /* go through and unsync uc_addr entries to the device */
3801 list = &netdev->uc;
3802 list_for_each_entry_safe(ha, tmp, &list->list, list)
3803 hns3_nic_uc_unsync(netdev, ha->addr);
3804
3805 /* go through and unsync mc_addr entries to the device */
3806 list = &netdev->mc;
3807 list_for_each_entry_safe(ha, tmp, &list->list, list)
3808 if (ha->refcount > 1)
3809 hns3_nic_mc_unsync(netdev, ha->addr);
3810}
3811
beebca3a 3812static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 3813{
beebca3a 3814 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 3815 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL		 3816 hns3_free_buffer_detach(ring, ring->next_to_clean);
3817 ring_ptr_move_fw(ring, next_to_clean);
3818 }
3819}
3820
7b763f3f
FL		 3821static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3822{
3823 struct hns3_desc_cb res_cbs;
3824 int ret;
3825
3826 while (ring->next_to_use != ring->next_to_clean) {
3827 /* When a buffer is not reused, it's memory has been
3828 * freed in hns3_handle_rx_bd or will be freed by
3829 * stack, so we need to replace the buffer here.
3830 */
3831 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3832 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3833 if (ret) {
3834 u64_stats_update_begin(&ring->syncp);
3835 ring->stats.sw_err_cnt++;
3836 u64_stats_update_end(&ring->syncp);
3837 /* if alloc new buffer fail, exit directly
3838 * and reclear in up flow.
3839 */
3840 netdev_warn(ring->tqp->handle->kinfo.netdev,
3841 "reserve buffer map failed, ret = %d\n",
3842 ret);
3843 return ret;
3844 }
3845 hns3_replace_buffer(ring, ring->next_to_use,
3846 &res_cbs);
3847 }
3848 ring_ptr_move_fw(ring, next_to_use);
3849 }
3850
3851 return 0;
3852}
3853
3854static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 3855{
beebca3a
YL		 3856 while (ring->next_to_use != ring->next_to_clean) {
3857 /* When a buffer is not reused, it's memory has been
3858 * freed in hns3_handle_rx_bd or will be freed by
3859 * stack, so only need to unmap the buffer here.
3860 */
3861 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3862 hns3_unmap_buffer(ring,
3863 &ring->desc_cb[ring->next_to_use]);
3864 ring->desc_cb[ring->next_to_use].dma = 0;
3865 }
3866
3867 ring_ptr_move_fw(ring, next_to_use);
3868 }
bb6b94a8
L		 3869}
3870
7b763f3f
FL		 3871static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3872{
3873 struct net_device *ndev = h->kinfo.netdev;
3874 struct hns3_nic_priv *priv = netdev_priv(ndev);
3875 struct hns3_enet_ring *ring;
3876 u32 i;
3877
3878 for (i = 0; i < h->kinfo.num_tqps; i++) {
3879 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3880 hns3_force_clear_rx_ring(ring);
3881 }
3882}
3883
bb6b94a8
L		 3884static void hns3_clear_all_ring(struct hnae3_handle *h)
3885{
3886 struct net_device *ndev = h->kinfo.netdev;
3887 struct hns3_nic_priv *priv = netdev_priv(ndev);
3888 u32 i;
3889
3890 for (i = 0; i < h->kinfo.num_tqps; i++) {
3891 struct netdev_queue *dev_queue;
3892 struct hns3_enet_ring *ring;
3893
3894 ring = priv->ring_data[i].ring;
beebca3a 3895 hns3_clear_tx_ring(ring);
bb6b94a8
L		 3896 dev_queue = netdev_get_tx_queue(ndev,
3897 priv->ring_data[i].queue_index);
3898 netdev_tx_reset_queue(dev_queue);
3899
3900 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
7b763f3f
FL		 3901 /* Continue to clear other rings even if clearing some
3902 * rings failed.
3903 */
beebca3a 3904 hns3_clear_rx_ring(ring);
bb6b94a8
L		 3905 }
3906}
3907
7b763f3f
FL		 3908int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3909{
3910 struct net_device *ndev = h->kinfo.netdev;
3911 struct hns3_nic_priv *priv = netdev_priv(ndev);
3912 struct hns3_enet_ring *rx_ring;
3913 int i, j;
3914 int ret;
3915
3916 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 3917 ret = h->ae_algo->ops->reset_queue(h, i);
3918 if (ret)
3919 return ret;
3920
7b763f3f
FL		 3921 hns3_init_ring_hw(priv->ring_data[i].ring);
3922
3923 /* We need to clear tx ring here because self test will
3924 * use the ring and will not run down before up
3925 */
3926 hns3_clear_tx_ring(priv->ring_data[i].ring);
3927 priv->ring_data[i].ring->next_to_clean = 0;
3928 priv->ring_data[i].ring->next_to_use = 0;
3929
3930 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3931 hns3_init_ring_hw(rx_ring);
3932 ret = hns3_clear_rx_ring(rx_ring);
3933 if (ret)
3934 return ret;
3935
3936 /* We can not know the hardware head and tail when this
3937 * function is called in reset flow, so we reuse all desc.
3938 */
3939 for (j = 0; j < rx_ring->desc_num; j++)
3940 hns3_reuse_buffer(rx_ring, j);
3941
3942 rx_ring->next_to_clean = 0;
3943 rx_ring->next_to_use = 0;
3944 }
3945
1c772154
YL		 3946 hns3_init_tx_ring_tc(priv);
3947
7b763f3f
FL		 3948 return 0;
3949}
3950
e4fd7502
HT		 3951static void hns3_store_coal(struct hns3_nic_priv *priv)
3952{
3953 /* ethtool only support setting and querying one coal
3954 * configuation for now, so save the vector 0' coal
3955 * configuation here in order to restore it.
3956 */
3957 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
3958 sizeof(struct hns3_enet_coalesce));
3959 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
3960 sizeof(struct hns3_enet_coalesce));
3961}
3962
3963static void hns3_restore_coal(struct hns3_nic_priv *priv)
3964{
3965 u16 vector_num = priv->vector_num;
3966 int i;
3967
3968 for (i = 0; i < vector_num; i++) {
3969 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
3970 sizeof(struct hns3_enet_coalesce));
3971 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
3972 sizeof(struct hns3_enet_coalesce));
3973 }
3974}
3975
bb6b94a8
L		 3976static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3977{
7edff533 3978 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L		 3979 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3980 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 3981 struct hns3_nic_priv *priv = netdev_priv(ndev);
3982
3983 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
3984 return 0;
bb6b94a8 3985
7edff533
HT		 3986 /* it is cumbersome for hardware to pick-and-choose entries for deletion
3987 * from table space. Hence, for function reset software intervention is
3988 * required to delete the entries
3989 */
3990 if (hns3_dev_ongoing_func_reset(ae_dev)) {
3991 hns3_remove_hw_addr(ndev);
3992 hns3_del_all_fd_rules(ndev, false);
3993 }
3994
bb6b94a8 3995 if (!netif_running(ndev))
6b1385cc 3996 return 0;
bb6b94a8
L		 3997
3998 return hns3_nic_net_stop(ndev);
3999}
4000
4001static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4002{
4003 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4004 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4005 int ret = 0;
4006
e8884027
HT		 4007 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4008
bb6b94a8 4009 if (netif_running(kinfo->netdev)) {
e8884027 4010 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4011 if (ret) {
e8884027 4012 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8
L		 4013 netdev_err(kinfo->netdev,
4014 "hns net up fail, ret=%d!\n", ret);
4015 return ret;
4016 }
bb6b94a8
L		 4017 }
4018
4019 return ret;
4020}
4021
4022static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4023{
4024 struct net_device *netdev = handle->kinfo.netdev;
4025 struct hns3_nic_priv *priv = netdev_priv(netdev);
4026 int ret;
4027
bb6b94a8
L		 4028 /* Carrier off reporting is important to ethtool even BEFORE open */
4029 netif_carrier_off(netdev);
4030
2c9dd668 4031 ret = hns3_get_ring_config(priv);
862d969a
HT		 4032 if (ret)
4033 return ret;
4034
2c9dd668
HT		 4035 ret = hns3_nic_alloc_vector_data(priv);
4036 if (ret)
4037 goto err_put_ring;
4038
e4fd7502
HT		 4039 hns3_restore_coal(priv);
4040
bb6b94a8
L		 4041 ret = hns3_nic_init_vector_data(priv);
4042 if (ret)
862d969a 4043 goto err_dealloc_vector;
bb6b94a8
L		 4044
4045 ret = hns3_init_all_ring(priv);
862d969a
HT		 4046 if (ret)
4047 goto err_uninit_vector;
bb6b94a8 4048
814da63c
HT		 4049 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4050
862d969a
HT		 4051 return ret;
4052
4053err_uninit_vector:
4054 hns3_nic_uninit_vector_data(priv);
4055 priv->ring_data = NULL;
4056err_dealloc_vector:
4057 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 4058err_put_ring:
4059 hns3_put_ring_config(priv);
4060 priv->ring_data = NULL;
862d969a 4061
bb6b94a8
L		 4062 return ret;
4063}
4064
1f609492
YL		 4065static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4066{
4067 struct net_device *netdev = handle->kinfo.netdev;
4068 bool vlan_filter_enable;
4069 int ret;
4070
4071 ret = hns3_init_mac_addr(netdev, false);
4072 if (ret)
4073 return ret;
4074
4075 ret = hns3_recover_hw_addr(netdev);
4076 if (ret)
4077 return ret;
4078
4079 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4080 if (ret)
4081 return ret;
4082
4083 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4084 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4085
4086 /* Hardware table is only clear when pf resets */
4087 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4088 ret = hns3_restore_vlan(netdev);
4089 if (ret)
4090 return ret;
4091 }
4092
4093 return hns3_restore_fd_rules(netdev);
4094}
4095
bb6b94a8
L		 4096static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4097{
4098 struct net_device *netdev = handle->kinfo.netdev;
4099 struct hns3_nic_priv *priv = netdev_priv(netdev);
4100 int ret;
4101
814da63c
HT		 4102 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4103 netdev_warn(netdev, "already uninitialized\n");
4104 return 0;
4105 }
4106
7b763f3f 4107 hns3_force_clear_all_rx_ring(handle);
bb6b94a8
L		 4108
4109 ret = hns3_nic_uninit_vector_data(priv);
4110 if (ret) {
4111 netdev_err(netdev, "uninit vector error\n");
4112 return ret;
4113 }
4114
e4fd7502
HT		 4115 hns3_store_coal(priv);
4116
862d969a
HT		 4117 ret = hns3_nic_dealloc_vector_data(priv);
4118 if (ret)
4119 netdev_err(netdev, "dealloc vector error\n");
4120
bb6b94a8
L		 4121 ret = hns3_uninit_all_ring(priv);
4122 if (ret)
4123 netdev_err(netdev, "uninit ring error\n");
4124
2c9dd668
HT		 4125 hns3_put_ring_config(priv);
4126 priv->ring_data = NULL;
4127
814da63c
HT		 4128 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
4129
bb6b94a8
L		 4130 return ret;
4131}
4132
4133static int hns3_reset_notify(struct hnae3_handle *handle,
4134 enum hnae3_reset_notify_type type)
4135{
4136 int ret = 0;
4137
4138 switch (type) {
4139 case HNAE3_UP_CLIENT:
e1586241
SM		 4140 ret = hns3_reset_notify_up_enet(handle);
4141 break;
bb6b94a8
L		 4142 case HNAE3_DOWN_CLIENT:
4143 ret = hns3_reset_notify_down_enet(handle);
4144 break;
4145 case HNAE3_INIT_CLIENT:
4146 ret = hns3_reset_notify_init_enet(handle);
4147 break;
4148 case HNAE3_UNINIT_CLIENT:
4149 ret = hns3_reset_notify_uninit_enet(handle);
4150 break;
1f609492
YL		 4151 case HNAE3_RESTORE_CLIENT:
4152 ret = hns3_reset_notify_restore_enet(handle);
4153 break;
bb6b94a8
L		 4154 default:
4155 break;
4156 }
4157
4158 return ret;
4159}
4160
09f2af64
PL		 4161int hns3_set_channels(struct net_device *netdev,
4162 struct ethtool_channels *ch)
4163{
09f2af64
PL		 4164 struct hnae3_handle *h = hns3_get_handle(netdev);
4165 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4166 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 4167 u32 new_tqp_num = ch->combined_count;
4168 u16 org_tqp_num;
4169 int ret;
4170
4171 if (ch->rx_count || ch->tx_count)
4172 return -EINVAL;
4173
678335a1 4174 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4175 new_tqp_num < 1) {
09f2af64 4176 dev_err(&netdev->dev,
c78b5b6c 4177 "Change tqps fail, the tqp range is from 1 to %d",
678335a1 4178 hns3_get_max_available_channels(h));
09f2af64
PL		 4179 return -EINVAL;
4180 }
4181
c78b5b6c 4182 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 4183 return 0;
4184
65749f73
HT		 4185 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4186 if (ret)
4187 return ret;
dd38c726 4188
65749f73
HT		 4189 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4190 if (ret)
4191 return ret;
09f2af64
PL		 4192
4193 org_tqp_num = h->kinfo.num_tqps;
90c68a41 4194 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4195 if (ret) {
90c68a41
YL		 4196 ret = h->ae_algo->ops->set_channels(h, org_tqp_num,
4197 rxfh_configured);
09f2af64
PL		 4198 if (ret) {
4199 /* If revert to old tqp failed, fatal error occurred */
4200 dev_err(&netdev->dev,
4201 "Revert to old tqp num fail, ret=%d", ret);
4202 return ret;
4203 }
4204 dev_info(&netdev->dev,
4205 "Change tqp num fail, Revert to old tqp num");
4206 }
65749f73
HT		 4207 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT);
4208 if (ret)
4209 return ret;
09f2af64 4210
65749f73 4211 return hns3_reset_notify(h, HNAE3_UP_CLIENT);
09f2af64
PL		 4212}
4213
1db9b1bf 4214static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4215 .init_instance = hns3_client_init,
4216 .uninit_instance = hns3_client_uninit,
4217 .link_status_change = hns3_link_status_change,
9df8f79a 4218 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4219 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 4220};
4221
4222/* hns3_init_module - Driver registration routine
4223 * hns3_init_module is the first routine called when the driver is
4224 * loaded. All it does is register with the PCI subsystem.
4225 */
4226static int __init hns3_init_module(void)
4227{
4228 int ret;
4229
4230 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4231 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4232
4233 client.type = HNAE3_CLIENT_KNIC;
4234 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4235 hns3_driver_name);
4236
4237 client.ops = &client_ops;
4238
13562d1f
XW		 4239 INIT_LIST_HEAD(&client.node);
4240
b2292360 4241 hns3_dbg_register_debugfs(hns3_driver_name);
4242
76ad4f0e
S		 4243 ret = hnae3_register_client(&client);
4244 if (ret)
b2292360 4245 goto err_reg_client;
76ad4f0e
S		 4246
4247 ret = pci_register_driver(&hns3_driver);
4248 if (ret)
b2292360 4249 goto err_reg_driver;
76ad4f0e
S		 4250
4251 return ret;
b2292360 4252
4253err_reg_driver:
4254 hnae3_unregister_client(&client);
4255err_reg_client:
4256 hns3_dbg_unregister_debugfs();
4257 return ret;
76ad4f0e
S		 4258}
4259module_init(hns3_init_module);
4260
4261/* hns3_exit_module - Driver exit cleanup routine
4262 * hns3_exit_module is called just before the driver is removed
4263 * from memory.
4264 */
4265static void __exit hns3_exit_module(void)
4266{
4267 pci_unregister_driver(&hns3_driver);
4268 hnae3_unregister_client(&client);
b2292360 4269 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4270}
4271module_exit(hns3_exit_module);
4272
4273MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4274MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4275MODULE_LICENSE("GPL");
4276MODULE_ALIAS("pci:hns-nic");
3c7624d8 4277MODULE_VERSION(HNS3_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)