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neighbor: Initialize protocol when new pneigh_entry are created
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
7#include <linux/if_vlan.h>
8#include <linux/ip.h>
9#include <linux/ipv6.h>
10#include <linux/module.h>
11#include <linux/pci.h>
6ae4e733 12#include <linux/aer.h>
76ad4f0e
S		 13#include <linux/skbuff.h>
14#include <linux/sctp.h>
15#include <linux/vermagic.h>
16#include <net/gre.h>
30d240df 17#include <net/pkt_cls.h>
a6d53b97 18#include <net/tcp.h>
76ad4f0e
S		 19#include <net/vxlan.h>
20
21#include "hnae3.h"
22#include "hns3_enet.h"
23
7b763f3f
FL		 24static void hns3_clear_all_ring(struct hnae3_handle *h);
25static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
f05e2109 26static void hns3_remove_hw_addr(struct net_device *netdev);
7b763f3f 27
1db9b1bf 28static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 29const char hns3_driver_version[] = VERMAGIC_STRING;
30static const char hns3_driver_string[] =
31 "Hisilicon Ethernet Network Driver for Hip08 Family";
32static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
33static struct hnae3_client client;
34
35/* hns3_pci_tbl - PCI Device ID Table
36 *
37 * Last entry must be all 0s
38 *
39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
40 * Class, Class Mask, private data (not used) }
41 */
42static const struct pci_device_id hns3_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
07acf909
JS		 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 58 /* required last entry */
59 {0, }
60};
61MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
62
ef0c5009 63static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 64{
ef0c5009 65 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e
S		 66
67 napi_schedule(&tqp_vector->napi);
68
69 return IRQ_HANDLED;
70}
71
874bff0b
PL		 72/* This callback function is used to set affinity changes to the irq affinity
73 * masks when the irq_set_affinity_notifier function is used.
74 */
75static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
76 const cpumask_t *mask)
77{
78 struct hns3_enet_tqp_vector *tqp_vectors =
79 container_of(notify, struct hns3_enet_tqp_vector,
80 affinity_notify);
81
82 tqp_vectors->affinity_mask = *mask;
83}
84
85static void hns3_nic_irq_affinity_release(struct kref *ref)
86{
87}
88
76ad4f0e
S		 89static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
90{
91 struct hns3_enet_tqp_vector *tqp_vectors;
92 unsigned int i;
93
94 for (i = 0; i < priv->vector_num; i++) {
95 tqp_vectors = &priv->tqp_vector[i];
96
97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
98 continue;
99
874bff0b
PL		 100 /* clear the affinity notifier and affinity mask */
101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
103
76ad4f0e
S		 104 /* release the irq resource */
105 free_irq(tqp_vectors->vector_irq, tqp_vectors);
106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
107 }
108}
109
110static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
111{
112 struct hns3_enet_tqp_vector *tqp_vectors;
113 int txrx_int_idx = 0;
114 int rx_int_idx = 0;
115 int tx_int_idx = 0;
116 unsigned int i;
117 int ret;
118
119 for (i = 0; i < priv->vector_num; i++) {
120 tqp_vectors = &priv->tqp_vector[i];
121
122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
123 continue;
124
125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "TxRx",
128 txrx_int_idx++);
129 txrx_int_idx++;
130 } else if (tqp_vectors->rx_group.ring) {
131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
132 "%s-%s-%d", priv->netdev->name, "Rx",
133 rx_int_idx++);
134 } else if (tqp_vectors->tx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Tx",
137 tx_int_idx++);
138 } else {
139 /* Skip this unused q_vector */
140 continue;
141 }
142
143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
144
145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
146 tqp_vectors->name,
147 tqp_vectors);
148 if (ret) {
149 netdev_err(priv->netdev, "request irq(%d) fail\n",
150 tqp_vectors->vector_irq);
151 return ret;
152 }
153
874bff0b
PL		 154 tqp_vectors->affinity_notify.notify =
155 hns3_nic_irq_affinity_notify;
156 tqp_vectors->affinity_notify.release =
157 hns3_nic_irq_affinity_release;
158 irq_set_affinity_notifier(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_notify);
160 irq_set_affinity_hint(tqp_vectors->vector_irq,
161 &tqp_vectors->affinity_mask);
162
76ad4f0e
S		 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
164 }
165
166 return 0;
167}
168
169static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
170 u32 mask_en)
171{
172 writel(mask_en, tqp_vector->mask_addr);
173}
174
175static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
176{
177 napi_enable(&tqp_vector->napi);
178
179 /* enable vector */
180 hns3_mask_vector_irq(tqp_vector, 1);
181}
182
183static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
184{
185 /* disable vector */
186 hns3_mask_vector_irq(tqp_vector, 0);
187
188 disable_irq(tqp_vector->vector_irq);
189 napi_disable(&tqp_vector->napi);
190}
191
434776a5
FL		 192void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
193 u32 rl_value)
76ad4f0e 194{
434776a5
FL		 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
196
76ad4f0e
S		 197 /* this defines the configuration for RL (Interrupt Rate Limiter).
198 * Rl defines rate of interrupts i.e. number of interrupts-per-second
199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
200 */
434776a5 201
9bc727a9
YL		 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
203 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 204 /* According to the hardware, the range of rl_reg is
205 * 0-59 and the unit is 4.
206 */
207 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
208
209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
210}
211
212void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
213 u32 gl_value)
214{
215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
216
217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
218}
219
220void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
221 u32 gl_value)
222{
223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
224
225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 226}
227
5fd4789a
FL		 228static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
229 struct hns3_nic_priv *priv)
76ad4f0e
S		 230{
231 /* initialize the configuration for interrupt coalescing.
232 * 1. GL (Interrupt Gap Limiter)
233 * 2. RL (Interrupt Rate Limiter)
234 */
235
5fd4789a 236 /* Default: enable interrupt coalescing self-adaptive and GL */
9bc727a9
YL		 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 239
9bc727a9
YL		 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 242
9bc727a9
YL		 243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 245}
246
dd38c726
YL		 247static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
248 struct hns3_nic_priv *priv)
249{
250 struct hnae3_handle *h = priv->ae_handle;
251
252 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 253 tqp_vector->tx_group.coal.int_gl);
dd38c726 254 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 255 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
257}
258
9df8f79a
YL		 259static int hns3_nic_set_real_num_queue(struct net_device *netdev)
260{
9780cb97 261 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 262 struct hnae3_knic_private_info *kinfo = &h->kinfo;
263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
a75a8efa
YL		 264 int i, ret;
265
266 if (kinfo->num_tc <= 1) {
267 netdev_reset_tc(netdev);
268 } else {
269 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
270 if (ret) {
271 netdev_err(netdev,
272 "netdev_set_num_tc fail, ret=%d!\n", ret);
273 return ret;
274 }
275
276 for (i = 0; i < HNAE3_MAX_TC; i++) {
277 if (!kinfo->tc_info[i].enable)
278 continue;
279
280 netdev_set_tc_queue(netdev,
281 kinfo->tc_info[i].tc,
282 kinfo->tc_info[i].tqp_count,
283 kinfo->tc_info[i].tqp_offset);
284 }
285 }
9df8f79a
YL		 286
287 ret = netif_set_real_num_tx_queues(netdev, queue_size);
288 if (ret) {
289 netdev_err(netdev,
290 "netif_set_real_num_tx_queues fail, ret=%d!\n",
291 ret);
292 return ret;
293 }
294
295 ret = netif_set_real_num_rx_queues(netdev, queue_size);
296 if (ret) {
297 netdev_err(netdev,
298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
299 return ret;
300 }
301
302 return 0;
303}
304
678335a1
PL		 305static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
306{
0d43bf45 307 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 308
0d43bf45
HT		 309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
310 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 311
0d43bf45 312 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 313}
314
8df0fa91
HT		 315static void hns3_tqp_enable(struct hnae3_queue *tqp)
316{
317 u32 rcb_reg;
318
319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
320 rcb_reg |= BIT(HNS3_RING_EN_B);
321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
322}
323
324static void hns3_tqp_disable(struct hnae3_queue *tqp)
325{
326 u32 rcb_reg;
327
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg &= ~BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
331}
332
76ad4f0e
S		 333static int hns3_nic_net_up(struct net_device *netdev)
334{
335 struct hns3_nic_priv *priv = netdev_priv(netdev);
336 struct hnae3_handle *h = priv->ae_handle;
337 int i, j;
338 int ret;
339
7b763f3f
FL		 340 ret = hns3_nic_reset_all_ring(h);
341 if (ret)
342 return ret;
343
76ad4f0e
S		 344 /* get irq resource for all vectors */
345 ret = hns3_nic_init_irq(priv);
346 if (ret) {
347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
348 return ret;
349 }
350
351 /* enable the vectors */
352 for (i = 0; i < priv->vector_num; i++)
353 hns3_vector_enable(&priv->tqp_vector[i]);
354
8df0fa91
HT		 355 /* enable rcb */
356 for (j = 0; j < h->kinfo.num_tqps; j++)
357 hns3_tqp_enable(h->kinfo.tqp[j]);
358
76ad4f0e
S		 359 /* start the ae_dev */
360 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
361 if (ret)
362 goto out_start_err;
363
b875cc37
JS		 364 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
365
76ad4f0e
S		 366 return 0;
367
368out_start_err:
8df0fa91
HT		 369 while (j--)
370 hns3_tqp_disable(h->kinfo.tqp[j]);
371
76ad4f0e
S		 372 for (j = i - 1; j >= 0; j--)
373 hns3_vector_disable(&priv->tqp_vector[j]);
374
375 hns3_nic_uninit_irq(priv);
376
377 return ret;
378}
379
380static int hns3_nic_net_open(struct net_device *netdev)
381{
a75a8efa
YL		 382 struct hnae3_handle *h = hns3_get_handle(netdev);
383 struct hnae3_knic_private_info *kinfo;
384 int i, ret;
76ad4f0e 385
257e4f29
HT		 386 if (hns3_nic_resetting(netdev))
387 return -EBUSY;
388
76ad4f0e
S		 389 netif_carrier_off(netdev);
390
9df8f79a
YL		 391 ret = hns3_nic_set_real_num_queue(netdev);
392 if (ret)
76ad4f0e 393 return ret;
76ad4f0e
S		 394
395 ret = hns3_nic_net_up(netdev);
396 if (ret) {
397 netdev_err(netdev,
398 "hns net up fail, ret=%d!\n", ret);
399 return ret;
400 }
401
a75a8efa
YL		 402 kinfo = &h->kinfo;
403 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
404 netdev_set_prio_tc_map(netdev, i,
405 kinfo->prio_tc[i]);
406 }
407
76ad4f0e
S		 408 return 0;
409}
410
411static void hns3_nic_net_down(struct net_device *netdev)
412{
413 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 414 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 415 const struct hnae3_ae_ops *ops;
416 int i;
417
7b763f3f
FL		 418 /* disable vectors */
419 for (i = 0; i < priv->vector_num; i++)
420 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 421
422 /* disable rcb */
423 for (i = 0; i < h->kinfo.num_tqps; i++)
424 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 425
76ad4f0e
S		 426 /* stop ae_dev */
427 ops = priv->ae_handle->ae_algo->ops;
428 if (ops->stop)
429 ops->stop(priv->ae_handle);
430
76ad4f0e
S		 431 /* free irq resources */
432 hns3_nic_uninit_irq(priv);
7b763f3f
FL		 433
434 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 435}
436
437static int hns3_nic_net_stop(struct net_device *netdev)
438{
ff0699e0
HT		 439 struct hns3_nic_priv *priv = netdev_priv(netdev);
440
441 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
442 return 0;
443
76ad4f0e
S		 444 netif_tx_stop_all_queues(netdev);
445 netif_carrier_off(netdev);
446
447 hns3_nic_net_down(netdev);
448
449 return 0;
450}
451
76ad4f0e
S		 452static int hns3_nic_uc_sync(struct net_device *netdev,
453 const unsigned char *addr)
454{
9780cb97 455 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 456
457 if (h->ae_algo->ops->add_uc_addr)
458 return h->ae_algo->ops->add_uc_addr(h, addr);
459
460 return 0;
461}
462
463static int hns3_nic_uc_unsync(struct net_device *netdev,
464 const unsigned char *addr)
465{
9780cb97 466 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 467
468 if (h->ae_algo->ops->rm_uc_addr)
469 return h->ae_algo->ops->rm_uc_addr(h, addr);
470
471 return 0;
472}
473
474static int hns3_nic_mc_sync(struct net_device *netdev,
475 const unsigned char *addr)
476{
9780cb97 477 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 478
720a8478 479 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 480 return h->ae_algo->ops->add_mc_addr(h, addr);
481
482 return 0;
483}
484
485static int hns3_nic_mc_unsync(struct net_device *netdev,
486 const unsigned char *addr)
487{
9780cb97 488 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 489
720a8478 490 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 491 return h->ae_algo->ops->rm_mc_addr(h, addr);
492
493 return 0;
494}
495
c60edc17
JS		 496static u8 hns3_get_netdev_flags(struct net_device *netdev)
497{
498 u8 flags = 0;
499
500 if (netdev->flags & IFF_PROMISC) {
501 flags = HNAE3_USER_UPE | HNAE3_USER_MPE;
502 } else {
503 flags |= HNAE3_VLAN_FLTR;
504 if (netdev->flags & IFF_ALLMULTI)
505 flags |= HNAE3_USER_MPE;
506 }
507
508 return flags;
509}
510
1db9b1bf 511static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 512{
9780cb97 513 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17
JS		 514 u8 new_flags;
515 int ret;
76ad4f0e 516
c60edc17
JS		 517 new_flags = hns3_get_netdev_flags(netdev);
518
519 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
520 if (ret) {
76ad4f0e 521 netdev_err(netdev, "sync uc address fail\n");
c60edc17
JS		 522 if (ret == -ENOSPC)
523 new_flags |= HNAE3_OVERFLOW_UPE;
524 }
525
40cca1c5 526 if (netdev->flags & IFF_MULTICAST) {
c60edc17
JS		 527 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
528 hns3_nic_mc_unsync);
529 if (ret) {
76ad4f0e 530 netdev_err(netdev, "sync mc address fail\n");
c60edc17
JS		 531 if (ret == -ENOSPC)
532 new_flags |= HNAE3_OVERFLOW_MPE;
533 }
534 }
535
536 hns3_update_promisc_mode(netdev, new_flags);
537 /* User mode Promisc mode enable and vlan filtering is disabled to
538 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
539 * vlan fitering is enabled
540 */
541 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
542 h->netdev_flags = new_flags;
543}
544
7fa6be4f 545int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
c60edc17
JS		 546{
547 struct hns3_nic_priv *priv = netdev_priv(netdev);
548 struct hnae3_handle *h = priv->ae_handle;
549
550 if (h->ae_algo->ops->set_promisc_mode) {
7fa6be4f
HT		 551 return h->ae_algo->ops->set_promisc_mode(h,
552 promisc_flags & HNAE3_UPE,
553 promisc_flags & HNAE3_MPE);
c60edc17 554 }
7fa6be4f
HT		 555
556 return 0;
c60edc17
JS		 557}
558
559void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
560{
561 struct hns3_nic_priv *priv = netdev_priv(netdev);
562 struct hnae3_handle *h = priv->ae_handle;
563 bool last_state;
564
565 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
566 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
567 if (enable != last_state) {
568 netdev_info(netdev,
569 "%s vlan filter\n",
570 enable ? "enable" : "disable");
571 h->ae_algo->ops->enable_vlan_filter(h, enable);
572 }
40cca1c5 573 }
76ad4f0e
S		 574}
575
576static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
577 u16 *mss, u32 *type_cs_vlan_tso)
578{
579 u32 l4_offset, hdr_len;
580 union l3_hdr_info l3;
581 union l4_hdr_info l4;
582 u32 l4_paylen;
583 int ret;
584
585 if (!skb_is_gso(skb))
586 return 0;
587
588 ret = skb_cow_head(skb, 0);
589 if (ret)
590 return ret;
591
592 l3.hdr = skb_network_header(skb);
593 l4.hdr = skb_transport_header(skb);
594
595 /* Software should clear the IPv4's checksum field when tso is
596 * needed.
597 */
598 if (l3.v4->version == 4)
599 l3.v4->check = 0;
600
601 /* tunnel packet.*/
602 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
603 SKB_GSO_GRE_CSUM |
604 SKB_GSO_UDP_TUNNEL |
605 SKB_GSO_UDP_TUNNEL_CSUM)) {
606 if ((!(skb_shinfo(skb)->gso_type &
607 SKB_GSO_PARTIAL)) &&
608 (skb_shinfo(skb)->gso_type &
609 SKB_GSO_UDP_TUNNEL_CSUM)) {
610 /* Software should clear the udp's checksum
611 * field when tso is needed.
612 */
613 l4.udp->check = 0;
614 }
615 /* reset l3&l4 pointers from outer to inner headers */
616 l3.hdr = skb_inner_network_header(skb);
617 l4.hdr = skb_inner_transport_header(skb);
618
619 /* Software should clear the IPv4's checksum field when
620 * tso is needed.
621 */
622 if (l3.v4->version == 4)
623 l3.v4->check = 0;
624 }
625
626 /* normal or tunnel packet*/
627 l4_offset = l4.hdr - skb->data;
628 hdr_len = (l4.tcp->doff * 4) + l4_offset;
629
630 /* remove payload length from inner pseudo checksum when tso*/
631 l4_paylen = skb->len - l4_offset;
632 csum_replace_by_diff(&l4.tcp->check,
633 (__force __wsum)htonl(l4_paylen));
634
635 /* find the txbd field values */
636 *paylen = skb->len - hdr_len;
e4e87715
PL		 637 hnae3_set_bit(*type_cs_vlan_tso,
638 HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 639
640 /* get MSS for TSO */
641 *mss = skb_shinfo(skb)->gso_size;
642
643 return 0;
644}
645
1898d4e4
S		 646static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
647 u8 *il4_proto)
76ad4f0e
S		 648{
649 union {
650 struct iphdr *v4;
651 struct ipv6hdr *v6;
652 unsigned char *hdr;
653 } l3;
654 unsigned char *l4_hdr;
655 unsigned char *exthdr;
656 u8 l4_proto_tmp;
657 __be16 frag_off;
658
659 /* find outer header point */
660 l3.hdr = skb_network_header(skb);
35f58fd7 661 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 662
663 if (skb->protocol == htons(ETH_P_IPV6)) {
664 exthdr = l3.hdr + sizeof(*l3.v6);
665 l4_proto_tmp = l3.v6->nexthdr;
666 if (l4_hdr != exthdr)
667 ipv6_skip_exthdr(skb, exthdr - skb->data,
668 &l4_proto_tmp, &frag_off);
669 } else if (skb->protocol == htons(ETH_P_IP)) {
670 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 671 } else {
672 return -EINVAL;
76ad4f0e
S		 673 }
674
675 *ol4_proto = l4_proto_tmp;
676
677 /* tunnel packet */
678 if (!skb->encapsulation) {
679 *il4_proto = 0;
1898d4e4 680 return 0;
76ad4f0e
S		 681 }
682
683 /* find inner header point */
684 l3.hdr = skb_inner_network_header(skb);
685 l4_hdr = skb_inner_transport_header(skb);
686
687 if (l3.v6->version == 6) {
688 exthdr = l3.hdr + sizeof(*l3.v6);
689 l4_proto_tmp = l3.v6->nexthdr;
690 if (l4_hdr != exthdr)
691 ipv6_skip_exthdr(skb, exthdr - skb->data,
692 &l4_proto_tmp, &frag_off);
693 } else if (l3.v4->version == 4) {
694 l4_proto_tmp = l3.v4->protocol;
695 }
696
697 *il4_proto = l4_proto_tmp;
1898d4e4
S		 698
699 return 0;
76ad4f0e
S		 700}
701
702static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
703 u8 il4_proto, u32 *type_cs_vlan_tso,
704 u32 *ol_type_vlan_len_msec)
705{
706 union {
707 struct iphdr *v4;
708 struct ipv6hdr *v6;
709 unsigned char *hdr;
710 } l3;
711 union {
712 struct tcphdr *tcp;
713 struct udphdr *udp;
714 struct gre_base_hdr *gre;
715 unsigned char *hdr;
716 } l4;
717 unsigned char *l2_hdr;
718 u8 l4_proto = ol4_proto;
719 u32 ol2_len;
720 u32 ol3_len;
721 u32 ol4_len;
722 u32 l2_len;
723 u32 l3_len;
724
725 l3.hdr = skb_network_header(skb);
726 l4.hdr = skb_transport_header(skb);
727
728 /* compute L2 header size for normal packet, defined in 2 Bytes */
729 l2_len = l3.hdr - skb->data;
e4e87715
PL		 730 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
731 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 732
733 /* tunnel packet*/
734 if (skb->encapsulation) {
735 /* compute OL2 header size, defined in 2 Bytes */
736 ol2_len = l2_len;
e4e87715
PL		 737 hnae3_set_field(*ol_type_vlan_len_msec,
738 HNS3_TXD_L2LEN_M,
739 HNS3_TXD_L2LEN_S, ol2_len >> 1);
76ad4f0e
S		 740
741 /* compute OL3 header size, defined in 4 Bytes */
742 ol3_len = l4.hdr - l3.hdr;
e4e87715
PL		 743 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
744 HNS3_TXD_L3LEN_S, ol3_len >> 2);
76ad4f0e
S		 745
746 /* MAC in UDP, MAC in GRE (0x6558)*/
747 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
748 /* switch MAC header ptr from outer to inner header.*/
749 l2_hdr = skb_inner_mac_header(skb);
750
751 /* compute OL4 header size, defined in 4 Bytes. */
752 ol4_len = l2_hdr - l4.hdr;
e4e87715
PL		 753 hnae3_set_field(*ol_type_vlan_len_msec,
754 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
755 ol4_len >> 2);
76ad4f0e
S		 756
757 /* switch IP header ptr from outer to inner header */
758 l3.hdr = skb_inner_network_header(skb);
759
760 /* compute inner l2 header size, defined in 2 Bytes. */
761 l2_len = l3.hdr - l2_hdr;
e4e87715
PL		 762 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
763 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 764 } else {
765 /* skb packet types not supported by hardware,
766 * txbd len fild doesn't be filled.
767 */
768 return;
769 }
770
771 /* switch L4 header pointer from outer to inner */
772 l4.hdr = skb_inner_transport_header(skb);
773
774 l4_proto = il4_proto;
775 }
776
777 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
778 l3_len = l4.hdr - l3.hdr;
e4e87715
PL		 779 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
780 HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e
S		 781
782 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
783 switch (l4_proto) {
784 case IPPROTO_TCP:
e4e87715
PL		 785 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
786 HNS3_TXD_L4LEN_S, l4.tcp->doff);
76ad4f0e
S		 787 break;
788 case IPPROTO_SCTP:
e4e87715
PL		 789 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
790 HNS3_TXD_L4LEN_S,
791 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 792 break;
793 case IPPROTO_UDP:
e4e87715
PL		 794 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
795 HNS3_TXD_L4LEN_S,
796 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 797 break;
798 default:
799 /* skb packet types not supported by hardware,
800 * txbd len fild doesn't be filled.
801 */
802 return;
803 }
804}
805
3db084d2
YL		 806/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
807 * and it is udp packet, which has a dest port as the IANA assigned.
808 * the hardware is expected to do the checksum offload, but the
809 * hardware will not do the checksum offload when udp dest port is
810 * 4789.
811 */
812static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
813{
814#define IANA_VXLAN_PORT 4789
815 union {
816 struct tcphdr *tcp;
817 struct udphdr *udp;
818 struct gre_base_hdr *gre;
819 unsigned char *hdr;
820 } l4;
821
822 l4.hdr = skb_transport_header(skb);
823
824 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
825 return false;
826
827 skb_checksum_help(skb);
828
829 return true;
830}
831
76ad4f0e
S		 832static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
833 u8 il4_proto, u32 *type_cs_vlan_tso,
834 u32 *ol_type_vlan_len_msec)
835{
836 union {
837 struct iphdr *v4;
838 struct ipv6hdr *v6;
839 unsigned char *hdr;
840 } l3;
841 u32 l4_proto = ol4_proto;
842
843 l3.hdr = skb_network_header(skb);
844
845 /* define OL3 type and tunnel type(OL4).*/
846 if (skb->encapsulation) {
847 /* define outer network header type.*/
848 if (skb->protocol == htons(ETH_P_IP)) {
849 if (skb_is_gso(skb))
e4e87715
PL		 850 hnae3_set_field(*ol_type_vlan_len_msec,
851 HNS3_TXD_OL3T_M,
852 HNS3_TXD_OL3T_S,
853 HNS3_OL3T_IPV4_CSUM);
76ad4f0e 854 else
e4e87715
PL		 855 hnae3_set_field(*ol_type_vlan_len_msec,
856 HNS3_TXD_OL3T_M,
857 HNS3_TXD_OL3T_S,
858 HNS3_OL3T_IPV4_NO_CSUM);
76ad4f0e
S		 859
860 } else if (skb->protocol == htons(ETH_P_IPV6)) {
e4e87715
PL		 861 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
862 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
76ad4f0e
S		 863 }
864
865 /* define tunnel type(OL4).*/
866 switch (l4_proto) {
867 case IPPROTO_UDP:
e4e87715
PL		 868 hnae3_set_field(*ol_type_vlan_len_msec,
869 HNS3_TXD_TUNTYPE_M,
870 HNS3_TXD_TUNTYPE_S,
871 HNS3_TUN_MAC_IN_UDP);
76ad4f0e
S		 872 break;
873 case IPPROTO_GRE:
e4e87715
PL		 874 hnae3_set_field(*ol_type_vlan_len_msec,
875 HNS3_TXD_TUNTYPE_M,
876 HNS3_TXD_TUNTYPE_S,
877 HNS3_TUN_NVGRE);
76ad4f0e
S		 878 break;
879 default:
880 /* drop the skb tunnel packet if hardware don't support,
881 * because hardware can't calculate csum when TSO.
882 */
883 if (skb_is_gso(skb))
884 return -EDOM;
885
886 /* the stack computes the IP header already,
887 * driver calculate l4 checksum when not TSO.
888 */
889 skb_checksum_help(skb);
890 return 0;
891 }
892
893 l3.hdr = skb_inner_network_header(skb);
894 l4_proto = il4_proto;
895 }
896
897 if (l3.v4->version == 4) {
e4e87715
PL		 898 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
899 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
76ad4f0e
S		 900
901 /* the stack computes the IP header already, the only time we
902 * need the hardware to recompute it is in the case of TSO.
903 */
904 if (skb_is_gso(skb))
e4e87715 905 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 906 } else if (l3.v6->version == 6) {
e4e87715
PL		 907 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
908 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
76ad4f0e
S		 909 }
910
911 switch (l4_proto) {
912 case IPPROTO_TCP:
5c897197 913 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
e4e87715
PL		 914 hnae3_set_field(*type_cs_vlan_tso,
915 HNS3_TXD_L4T_M,
916 HNS3_TXD_L4T_S,
917 HNS3_L4T_TCP);
76ad4f0e
S		 918 break;
919 case IPPROTO_UDP:
3db084d2
YL		 920 if (hns3_tunnel_csum_bug(skb))
921 break;
922
5c897197 923 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
e4e87715
PL		 924 hnae3_set_field(*type_cs_vlan_tso,
925 HNS3_TXD_L4T_M,
926 HNS3_TXD_L4T_S,
927 HNS3_L4T_UDP);
76ad4f0e
S		 928 break;
929 case IPPROTO_SCTP:
5c897197 930 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
e4e87715
PL		 931 hnae3_set_field(*type_cs_vlan_tso,
932 HNS3_TXD_L4T_M,
933 HNS3_TXD_L4T_S,
934 HNS3_L4T_SCTP);
76ad4f0e
S		 935 break;
936 default:
937 /* drop the skb tunnel packet if hardware don't support,
938 * because hardware can't calculate csum when TSO.
939 */
940 if (skb_is_gso(skb))
941 return -EDOM;
942
943 /* the stack computes the IP header already,
944 * driver calculate l4 checksum when not TSO.
945 */
946 skb_checksum_help(skb);
947 return 0;
948 }
949
950 return 0;
951}
952
953static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
954{
955 /* Config bd buffer end */
e4e87715
PL		 956 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
957 HNS3_TXD_BDTYPE_S, 0);
958 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
959 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
960 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
76ad4f0e
S		 961}
962
9699cffe
PL		 963static int hns3_fill_desc_vtags(struct sk_buff *skb,
964 struct hns3_enet_ring *tx_ring,
965 u32 *inner_vlan_flag,
966 u32 *out_vlan_flag,
967 u16 *inner_vtag,
968 u16 *out_vtag)
969{
970#define HNS3_TX_VLAN_PRIO_SHIFT 13
971
972 if (skb->protocol == htons(ETH_P_8021Q) &&
973 !(tx_ring->tqp->handle->kinfo.netdev->features &
974 NETIF_F_HW_VLAN_CTAG_TX)) {
975 /* When HW VLAN acceleration is turned off, and the stack
976 * sets the protocol to 802.1q, the driver just need to
977 * set the protocol to the encapsulated ethertype.
978 */
979 skb->protocol = vlan_get_protocol(skb);
980 return 0;
981 }
982
983 if (skb_vlan_tag_present(skb)) {
984 u16 vlan_tag;
985
986 vlan_tag = skb_vlan_tag_get(skb);
987 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
988
989 /* Based on hw strategy, use out_vtag in two layer tag case,
990 * and use inner_vtag in one tag case.
991 */
992 if (skb->protocol == htons(ETH_P_8021Q)) {
e4e87715 993 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
9699cffe
PL		 994 *out_vtag = vlan_tag;
995 } else {
e4e87715 996 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
9699cffe
PL		 997 *inner_vtag = vlan_tag;
998 }
999 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1000 struct vlan_ethhdr *vhdr;
1001 int rc;
1002
1003 rc = skb_cow_head(skb, 0);
1004 if (rc < 0)
1005 return rc;
1006 vhdr = (struct vlan_ethhdr *)skb->data;
1007 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1008 << HNS3_TX_VLAN_PRIO_SHIFT);
1009 }
1010
1011 skb->protocol = vlan_get_protocol(skb);
1012 return 0;
1013}
1014
76ad4f0e 1015static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
5188f218 1016 int size, int frag_end, enum hns_desc_type type)
76ad4f0e
S		 1017{
1018 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1019 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1020 struct device *dev = ring_to_dev(ring);
76ad4f0e
S		 1021 u32 ol_type_vlan_len_msec = 0;
1022 u16 bdtp_fe_sc_vld_ra_ri = 0;
5188f218 1023 struct skb_frag_struct *frag;
1e8a7977 1024 unsigned int frag_buf_num;
76ad4f0e
S		 1025 u32 type_cs_vlan_tso = 0;
1026 struct sk_buff *skb;
9699cffe
PL		 1027 u16 inner_vtag = 0;
1028 u16 out_vtag = 0;
1e8a7977
FL		 1029 unsigned int k;
1030 int sizeoflast;
76ad4f0e 1031 u32 paylen = 0;
5188f218 1032 dma_addr_t dma;
76ad4f0e 1033 u16 mss = 0;
76ad4f0e
S		 1034 u8 ol4_proto;
1035 u8 il4_proto;
1036 int ret;
1037
76ad4f0e
S		 1038 if (type == DESC_TYPE_SKB) {
1039 skb = (struct sk_buff *)priv;
a90bb9a5 1040 paylen = skb->len;
76ad4f0e 1041
9699cffe
PL		 1042 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1043 &ol_type_vlan_len_msec,
1044 &inner_vtag, &out_vtag);
1045 if (unlikely(ret))
1046 return ret;
1047
76ad4f0e
S		 1048 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1049 skb_reset_mac_len(skb);
76ad4f0e 1050
1898d4e4
S		 1051 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1052 if (ret)
1053 return ret;
76ad4f0e
S		 1054 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
1055 &type_cs_vlan_tso,
1056 &ol_type_vlan_len_msec);
1057 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
1058 &type_cs_vlan_tso,
1059 &ol_type_vlan_len_msec);
1060 if (ret)
1061 return ret;
1062
1063 ret = hns3_set_tso(skb, &paylen, &mss,
1064 &type_cs_vlan_tso);
1065 if (ret)
1066 return ret;
1067 }
1068
1069 /* Set txbd */
1070 desc->tx.ol_type_vlan_len_msec =
1071 cpu_to_le32(ol_type_vlan_len_msec);
1072 desc->tx.type_cs_vlan_tso_len =
1073 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 1074 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 1075 desc->tx.mss = cpu_to_le16(mss);
9699cffe
PL		 1076 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1077 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
5188f218
PL		 1078
1079 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1080 } else {
1081 frag = (struct skb_frag_struct *)priv;
1082 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1083 }
1084
1085 if (dma_mapping_error(ring->dev, dma)) {
1086 ring->stats.sw_err_cnt++;
1087 return -ENOMEM;
76ad4f0e
S		 1088 }
1089
bcdb12b7
FL		 1090 desc_cb->length = size;
1091
1e8a7977
FL		 1092 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1093 sizeoflast = size % HNS3_MAX_BD_SIZE;
1094 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1095
1096 /* When frag size is bigger than hardware limit, split this frag */
1097 for (k = 0; k < frag_buf_num; k++) {
1098 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1099 desc_cb->priv = priv;
1e8a7977
FL		 1100 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1101 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1102 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1103
1104 /* now, fill the descriptor */
1105 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7
FL		 1106 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1107 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977
FL		 1108 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1109 frag_end && (k == frag_buf_num - 1) ?
1110 1 : 0);
1111 desc->tx.bdtp_fe_sc_vld_ra_ri =
1112 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1113
1114 /* move ring pointer to next.*/
1115 ring_ptr_move_fw(ring, next_to_use);
1116
1117 desc_cb = &ring->desc_cb[ring->next_to_use];
1118 desc = &ring->desc[ring->next_to_use];
1119 }
76ad4f0e
S		 1120
1121 return 0;
1122}
1123
76ad4f0e
S		 1124static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1125 struct hns3_enet_ring *ring)
1126{
1127 struct sk_buff *skb = *out_skb;
1128 struct skb_frag_struct *frag;
1129 int bdnum_for_frag;
1130 int frag_num;
1131 int buf_num;
1132 int size;
1133 int i;
1134
1135 size = skb_headlen(skb);
1136 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1137
1138 frag_num = skb_shinfo(skb)->nr_frags;
1139 for (i = 0; i < frag_num; i++) {
1140 frag = &skb_shinfo(skb)->frags[i];
1141 size = skb_frag_size(frag);
1142 bdnum_for_frag =
1143 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1144 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1145 return -ENOMEM;
1146
1147 buf_num += bdnum_for_frag;
1148 }
1149
1150 if (buf_num > ring_space(ring))
1151 return -EBUSY;
1152
1153 *bnum = buf_num;
1154 return 0;
1155}
1156
1157static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1158 struct hns3_enet_ring *ring)
1159{
1160 struct sk_buff *skb = *out_skb;
1161 int buf_num;
1162
1163 /* No. of segments (plus a header) */
1164 buf_num = skb_shinfo(skb)->nr_frags + 1;
1165
932d1252 1166 if (unlikely(ring_space(ring) < buf_num))
76ad4f0e
S		 1167 return -EBUSY;
1168
1169 *bnum = buf_num;
1170
1171 return 0;
1172}
1173
ba3f808f 1174static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1175{
1176 struct device *dev = ring_to_dev(ring);
1177 unsigned int i;
1178
1179 for (i = 0; i < ring->desc_num; i++) {
1180 /* check if this is where we started */
1181 if (ring->next_to_use == next_to_use_orig)
1182 break;
1183
1184 /* unmap the descriptor dma address */
1185 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1186 dma_unmap_single(dev,
1187 ring->desc_cb[ring->next_to_use].dma,
1188 ring->desc_cb[ring->next_to_use].length,
1189 DMA_TO_DEVICE);
bcdb12b7 1190 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1191 dma_unmap_page(dev,
1192 ring->desc_cb[ring->next_to_use].dma,
1193 ring->desc_cb[ring->next_to_use].length,
1194 DMA_TO_DEVICE);
1195
bcdb12b7
FL		 1196 ring->desc_cb[ring->next_to_use].length = 0;
1197
76ad4f0e
S		 1198 /* rollback one */
1199 ring_ptr_move_bw(ring, next_to_use);
1200 }
1201}
1202
d43e5aca 1203netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1204{
1205 struct hns3_nic_priv *priv = netdev_priv(netdev);
1206 struct hns3_nic_ring_data *ring_data =
1207 &tx_ring_data(priv, skb->queue_mapping);
1208 struct hns3_enet_ring *ring = ring_data->ring;
76ad4f0e
S		 1209 struct netdev_queue *dev_queue;
1210 struct skb_frag_struct *frag;
1211 int next_to_use_head;
1212 int next_to_use_frag;
76ad4f0e
S		 1213 int buf_num;
1214 int seg_num;
1215 int size;
1216 int ret;
1217 int i;
1218
1219 /* Prefetch the data used later */
1220 prefetch(skb->data);
1221
1222 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1223 case -EBUSY:
1224 u64_stats_update_begin(&ring->syncp);
1225 ring->stats.tx_busy++;
1226 u64_stats_update_end(&ring->syncp);
1227
1228 goto out_net_tx_busy;
1229 case -ENOMEM:
1230 u64_stats_update_begin(&ring->syncp);
1231 ring->stats.sw_err_cnt++;
1232 u64_stats_update_end(&ring->syncp);
1233 netdev_err(netdev, "no memory to xmit!\n");
1234
1235 goto out_err_tx_ok;
1236 default:
1237 break;
1238 }
1239
1240 /* No. of segments (plus a header) */
1241 seg_num = skb_shinfo(skb)->nr_frags + 1;
1242 /* Fill the first part */
1243 size = skb_headlen(skb);
1244
1245 next_to_use_head = ring->next_to_use;
1246
5188f218
PL		 1247 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1248 DESC_TYPE_SKB);
76ad4f0e 1249 if (ret)
ba3f808f 1250 goto head_fill_err;
76ad4f0e
S		 1251
1252 next_to_use_frag = ring->next_to_use;
1253 /* Fill the fragments */
1254 for (i = 1; i < seg_num; i++) {
1255 frag = &skb_shinfo(skb)->frags[i - 1];
1256 size = skb_frag_size(frag);
5188f218
PL		 1257
1258 ret = priv->ops.fill_desc(ring, frag, size,
1259 seg_num - 1 == i ? 1 : 0,
1260 DESC_TYPE_PAGE);
76ad4f0e
S		 1261
1262 if (ret)
ba3f808f 1263 goto frag_fill_err;
76ad4f0e
S		 1264 }
1265
1266 /* Complete translate all packets */
1267 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1268 netdev_tx_sent_queue(dev_queue, skb->len);
1269
1270 wmb(); /* Commit all data before submit */
1271
e4e87715 1272 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1273
1274 return NETDEV_TX_OK;
1275
ba3f808f
FL		 1276frag_fill_err:
1277 hns3_clear_desc(ring, next_to_use_frag);
76ad4f0e 1278
ba3f808f
FL		 1279head_fill_err:
1280 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1281
1282out_err_tx_ok:
1283 dev_kfree_skb_any(skb);
1284 return NETDEV_TX_OK;
1285
1286out_net_tx_busy:
1287 netif_stop_subqueue(netdev, ring_data->queue_index);
1288 smp_mb(); /* Commit all data before submit */
1289
1290 return NETDEV_TX_BUSY;
1291}
1292
1293static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1294{
9780cb97 1295 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1296 struct sockaddr *mac_addr = p;
1297 int ret;
1298
1299 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1300 return -EADDRNOTAVAIL;
1301
5ec2a51e
JS		 1302 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1303 netdev_info(netdev, "already using mac address %pM\n",
1304 mac_addr->sa_data);
1305 return 0;
1306 }
1307
59098055 1308 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1309 if (ret) {
1310 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1311 return ret;
1312 }
1313
1314 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1315
1316 return 0;
1317}
1318
26483246
XW		 1319static int hns3_nic_do_ioctl(struct net_device *netdev,
1320 struct ifreq *ifr, int cmd)
1321{
1322 struct hnae3_handle *h = hns3_get_handle(netdev);
1323
1324 if (!netif_running(netdev))
1325 return -EINVAL;
1326
1327 if (!h->ae_algo->ops->do_ioctl)
1328 return -EOPNOTSUPP;
1329
1330 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1331}
1332
76ad4f0e
S		 1333static int hns3_nic_set_features(struct net_device *netdev,
1334 netdev_features_t features)
1335{
181d454b 1336 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1337 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1338 struct hnae3_handle *h = priv->ae_handle;
052ece6d 1339 int ret;
76ad4f0e 1340
181d454b 1341 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
0bbbf15d 1342 if (features & (NETIF_F_TSO | NETIF_F_TSO6))
181d454b 1343 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
0bbbf15d 1344 else
181d454b 1345 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 1346 }
1347
5c9f6b39
PL		 1348 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1349 if (features & NETIF_F_GRO_HW)
1350 ret = h->ae_algo->ops->set_gro_en(h, true);
1351 else
1352 ret = h->ae_algo->ops->set_gro_en(h, false);
1353 if (ret)
1354 return ret;
1355 }
1356
bd368416
JS		 1357 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1358 h->ae_algo->ops->enable_vlan_filter) {
181d454b
JS		 1359 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1360 h->ae_algo->ops->enable_vlan_filter(h, true);
1361 else
1362 h->ae_algo->ops->enable_vlan_filter(h, false);
1363 }
391b5e93 1364
bd368416
JS		 1365 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1366 h->ae_algo->ops->enable_hw_strip_rxvtag) {
052ece6d
PL		 1367 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1368 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1369 else
1370 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1371
1372 if (ret)
1373 return ret;
1374 }
1375
c17852a8
JS		 1376 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1377 if (features & NETIF_F_NTUPLE)
1378 h->ae_algo->ops->enable_fd(h, true);
1379 else
1380 h->ae_algo->ops->enable_fd(h, false);
1381 }
1382
76ad4f0e
S		 1383 netdev->features = features;
1384 return 0;
1385}
1386
6c88d9d7
PL		 1387static void hns3_nic_get_stats64(struct net_device *netdev,
1388 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1389{
1390 struct hns3_nic_priv *priv = netdev_priv(netdev);
1391 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1392 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e
S		 1393 struct hns3_enet_ring *ring;
1394 unsigned int start;
1395 unsigned int idx;
1396 u64 tx_bytes = 0;
1397 u64 rx_bytes = 0;
1398 u64 tx_pkts = 0;
1399 u64 rx_pkts = 0;
d2a5dca8
JS		 1400 u64 tx_drop = 0;
1401 u64 rx_drop = 0;
76ad4f0e 1402
b875cc37
JS		 1403 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1404 return;
1405
c5f65480
JS		 1406 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1407
76ad4f0e
S		 1408 for (idx = 0; idx < queue_num; idx++) {
1409 /* fetch the tx stats */
1410 ring = priv->ring_data[idx].ring;
1411 do {
d36d36ce 1412 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1413 tx_bytes += ring->stats.tx_bytes;
1414 tx_pkts += ring->stats.tx_pkts;
d2a5dca8
JS		 1415 tx_drop += ring->stats.tx_busy;
1416 tx_drop += ring->stats.sw_err_cnt;
76ad4f0e
S		 1417 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1418
1419 /* fetch the rx stats */
1420 ring = priv->ring_data[idx + queue_num].ring;
1421 do {
d36d36ce 1422 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1423 rx_bytes += ring->stats.rx_bytes;
1424 rx_pkts += ring->stats.rx_pkts;
d2a5dca8
JS		 1425 rx_drop += ring->stats.non_vld_descs;
1426 rx_drop += ring->stats.err_pkt_len;
1427 rx_drop += ring->stats.l2_err;
76ad4f0e
S		 1428 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1429 }
1430
1431 stats->tx_bytes = tx_bytes;
1432 stats->tx_packets = tx_pkts;
1433 stats->rx_bytes = rx_bytes;
1434 stats->rx_packets = rx_pkts;
1435
1436 stats->rx_errors = netdev->stats.rx_errors;
1437 stats->multicast = netdev->stats.multicast;
1438 stats->rx_length_errors = netdev->stats.rx_length_errors;
1439 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1440 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1441
1442 stats->tx_errors = netdev->stats.tx_errors;
d2a5dca8
JS		 1443 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1444 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
76ad4f0e
S		 1445 stats->collisions = netdev->stats.collisions;
1446 stats->rx_over_errors = netdev->stats.rx_over_errors;
1447 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1448 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1449 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1450 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1451 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1452 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1453 stats->tx_window_errors = netdev->stats.tx_window_errors;
1454 stats->rx_compressed = netdev->stats.rx_compressed;
1455 stats->tx_compressed = netdev->stats.tx_compressed;
1456}
1457
30d240df 1458static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1459{
30d240df 1460 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1461 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1462 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1463 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1464 u8 tc = mqprio_qopt->qopt.num_tc;
1465 u16 mode = mqprio_qopt->mode;
1466 u8 hw = mqprio_qopt->qopt.hw;
1467 bool if_running;
76ad4f0e
S		 1468 int ret;
1469
30d240df
YL		 1470 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1471 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1472 return -EOPNOTSUPP;
1473
76ad4f0e
S		 1474 if (tc > HNAE3_MAX_TC)
1475 return -EINVAL;
1476
76ad4f0e
S		 1477 if (!netdev)
1478 return -EINVAL;
1479
30d240df
YL		 1480 if_running = netif_running(netdev);
1481 if (if_running) {
1482 hns3_nic_net_stop(netdev);
1483 msleep(100);
76ad4f0e
S		 1484 }
1485
30d240df
YL		 1486 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1487 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e 1488 if (ret)
30d240df
YL		 1489 goto out;
1490
30d240df
YL		 1491 ret = hns3_nic_set_real_num_queue(netdev);
1492
1493out:
1494 if (if_running)
1495 hns3_nic_net_open(netdev);
1496
1497 return ret;
76ad4f0e
S		 1498}
1499
2572ac53 1500static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1501 void *type_data)
76ad4f0e 1502{
575ed7d3 1503 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1504 return -EOPNOTSUPP;
76ad4f0e 1505
30d240df 1506 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1507}
1508
1509static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1510 __be16 proto, u16 vid)
1511{
9780cb97 1512 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1513 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1514 int ret = -EIO;
1515
1516 if (h->ae_algo->ops->set_vlan_filter)
1517 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1518
681ec399
YL		 1519 if (!ret)
1520 set_bit(vid, priv->active_vlans);
1521
76ad4f0e
S		 1522 return ret;
1523}
1524
1525static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1526 __be16 proto, u16 vid)
1527{
9780cb97 1528 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1529 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1530 int ret = -EIO;
1531
1532 if (h->ae_algo->ops->set_vlan_filter)
1533 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1534
681ec399
YL		 1535 if (!ret)
1536 clear_bit(vid, priv->active_vlans);
1537
76ad4f0e
S		 1538 return ret;
1539}
1540
7fa6be4f 1541static int hns3_restore_vlan(struct net_device *netdev)
681ec399
YL		 1542{
1543 struct hns3_nic_priv *priv = netdev_priv(netdev);
7fa6be4f 1544 int ret = 0;
681ec399 1545 u16 vid;
681ec399
YL		 1546
1547 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1548 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
7fa6be4f
HT		 1549 if (ret) {
1550 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1551 vid, ret);
1552 return ret;
1553 }
681ec399 1554 }
7fa6be4f
HT		 1555
1556 return ret;
681ec399
YL		 1557}
1558
76ad4f0e
S		 1559static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1560 u8 qos, __be16 vlan_proto)
1561{
9780cb97 1562 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1563 int ret = -EIO;
1564
1565 if (h->ae_algo->ops->set_vf_vlan_filter)
1566 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1567 qos, vlan_proto);
1568
1569 return ret;
1570}
1571
a8e8b7ff
S		 1572static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1573{
9780cb97 1574 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1575 int ret;
1576
1577 if (!h->ae_algo->ops->set_mtu)
1578 return -EOPNOTSUPP;
1579
a8e8b7ff 1580 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1581 if (ret)
a8e8b7ff
S		 1582 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1583 ret);
93d8daf4
YL		 1584 else
1585 netdev->mtu = new_mtu;
5bad95a1 1586
a8e8b7ff
S		 1587 return ret;
1588}
1589
f8fa222c
L		 1590static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1591{
1592 struct hns3_nic_priv *priv = netdev_priv(ndev);
1593 struct hns3_enet_ring *tx_ring = NULL;
1594 int timeout_queue = 0;
1595 int hw_head, hw_tail;
1596 int i;
1597
1598 /* Find the stopped queue the same way the stack does */
1599 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1600 struct netdev_queue *q;
1601 unsigned long trans_start;
1602
1603 q = netdev_get_tx_queue(ndev, i);
1604 trans_start = q->trans_start;
1605 if (netif_xmit_stopped(q) &&
1606 time_after(jiffies,
1607 (trans_start + ndev->watchdog_timeo))) {
1608 timeout_queue = i;
1609 break;
1610 }
1611 }
1612
1613 if (i == ndev->num_tx_queues) {
1614 netdev_info(ndev,
1615 "no netdev TX timeout queue found, timeout count: %llu\n",
1616 priv->tx_timeout_count);
1617 return false;
1618 }
1619
1620 tx_ring = priv->ring_data[timeout_queue].ring;
1621
1622 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1623 HNS3_RING_TX_RING_HEAD_REG);
1624 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1625 HNS3_RING_TX_RING_TAIL_REG);
1626 netdev_info(ndev,
1627 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1628 priv->tx_timeout_count,
1629 timeout_queue,
1630 tx_ring->next_to_use,
1631 tx_ring->next_to_clean,
1632 hw_head,
1633 hw_tail,
1634 readl(tx_ring->tqp_vector->mask_addr));
1635
1636 return true;
1637}
1638
1639static void hns3_nic_net_timeout(struct net_device *ndev)
1640{
1641 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1642 struct hnae3_handle *h = priv->ae_handle;
1643
1644 if (!hns3_get_tx_timeo_queue_info(ndev))
1645 return;
1646
1647 priv->tx_timeout_count++;
1648
0742ed7c
HT		 1649 /* request the reset, and let the hclge to determine
1650 * which reset level should be done
1651 */
f8fa222c 1652 if (h->ae_algo->ops->reset_event)
6ae4e733 1653 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1654}
1655
76ad4f0e
S		 1656static const struct net_device_ops hns3_nic_netdev_ops = {
1657 .ndo_open = hns3_nic_net_open,
1658 .ndo_stop = hns3_nic_net_stop,
1659 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1660 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1661 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1662 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1663 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1664 .ndo_set_features = hns3_nic_set_features,
1665 .ndo_get_stats64 = hns3_nic_get_stats64,
1666 .ndo_setup_tc = hns3_nic_setup_tc,
1667 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1668 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1669 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1670 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1671};
1672
2312e050
FL		 1673static bool hns3_is_phys_func(struct pci_dev *pdev)
1674{
1675 u32 dev_id = pdev->device;
1676
1677 switch (dev_id) {
1678 case HNAE3_DEV_ID_GE:
1679 case HNAE3_DEV_ID_25GE:
1680 case HNAE3_DEV_ID_25GE_RDMA:
1681 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1682 case HNAE3_DEV_ID_50GE_RDMA:
1683 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1684 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1685 return true;
1686 case HNAE3_DEV_ID_100G_VF:
1687 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1688 return false;
1689 default:
1690 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1691 dev_id);
1692 }
1693
1694 return false;
1695}
1696
2312e050
FL		 1697static void hns3_disable_sriov(struct pci_dev *pdev)
1698{
1699 /* If our VFs are assigned we cannot shut down SR-IOV
1700 * without causing issues, so just leave the hardware
1701 * available but disabled
1702 */
1703 if (pci_vfs_assigned(pdev)) {
1704 dev_warn(&pdev->dev,
1705 "disabling driver while VFs are assigned\n");
1706 return;
1707 }
1708
1709 pci_disable_sriov(pdev);
1710}
1711
d695964d
JS		 1712static void hns3_get_dev_capability(struct pci_dev *pdev,
1713 struct hnae3_ae_dev *ae_dev)
1714{
b26a6fea 1715 if (pdev->revision >= 0x21) {
d695964d 1716 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL		 1717 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1718 }
d695964d
JS		 1719}
1720
76ad4f0e
S		 1721/* hns3_probe - Device initialization routine
1722 * @pdev: PCI device information struct
1723 * @ent: entry in hns3_pci_tbl
1724 *
1725 * hns3_probe initializes a PF identified by a pci_dev structure.
1726 * The OS initialization, configuring of the PF private structure,
1727 * and a hardware reset occur.
1728 *
1729 * Returns 0 on success, negative on failure
1730 */
1731static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1732{
1733 struct hnae3_ae_dev *ae_dev;
1734 int ret;
1735
1736 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1737 GFP_KERNEL);
1738 if (!ae_dev) {
1739 ret = -ENOMEM;
1740 return ret;
1741 }
1742
1743 ae_dev->pdev = pdev;
e92a0843 1744 ae_dev->flag = ent->driver_data;
76ad4f0e 1745 ae_dev->dev_type = HNAE3_DEV_KNIC;
6871af29 1746 ae_dev->reset_type = HNAE3_NONE_RESET;
d695964d 1747 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 1748 pci_set_drvdata(pdev, ae_dev);
1749
50fbc237 1750 hnae3_register_ae_dev(ae_dev);
2312e050 1751
2312e050 1752 return 0;
76ad4f0e
S		 1753}
1754
1755/* hns3_remove - Device removal routine
1756 * @pdev: PCI device information struct
1757 */
1758static void hns3_remove(struct pci_dev *pdev)
1759{
1760 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1761
2312e050
FL		 1762 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1763 hns3_disable_sriov(pdev);
1764
76ad4f0e 1765 hnae3_unregister_ae_dev(ae_dev);
76ad4f0e
S		 1766}
1767
fa8d82e8
PL		 1768/**
1769 * hns3_pci_sriov_configure
1770 * @pdev: pointer to a pci_dev structure
1771 * @num_vfs: number of VFs to allocate
1772 *
1773 * Enable or change the number of VFs. Called when the user updates the number
1774 * of VFs in sysfs.
1775 **/
743e1a84 1776static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 1777{
1778 int ret;
1779
1780 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1781 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1782 return -EINVAL;
1783 }
1784
1785 if (num_vfs) {
1786 ret = pci_enable_sriov(pdev, num_vfs);
1787 if (ret)
1788 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 1789 else
1790 return num_vfs;
fa8d82e8
PL		 1791 } else if (!pci_vfs_assigned(pdev)) {
1792 pci_disable_sriov(pdev);
1793 } else {
1794 dev_warn(&pdev->dev,
1795 "Unable to free VFs because some are assigned to VMs.\n");
1796 }
1797
1798 return 0;
1799}
1800
ce2c1d2e
YL		 1801static void hns3_shutdown(struct pci_dev *pdev)
1802{
1803 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1804
1805 hnae3_unregister_ae_dev(ae_dev);
1806 devm_kfree(&pdev->dev, ae_dev);
1807 pci_set_drvdata(pdev, NULL);
1808
1809 if (system_state == SYSTEM_POWER_OFF)
1810 pci_set_power_state(pdev, PCI_D3hot);
1811}
1812
5a9f0eac
SJ		 1813static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1814 pci_channel_state_t state)
1815{
1816 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1817 pci_ers_result_t ret;
1818
1819 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1820
1821 if (state == pci_channel_io_perm_failure)
1822 return PCI_ERS_RESULT_DISCONNECT;
1823
1824 if (!ae_dev) {
1825 dev_err(&pdev->dev,
1826 "Can't recover - error happened during device init\n");
1827 return PCI_ERS_RESULT_NONE;
1828 }
1829
381c356e
SJ		 1830 if (ae_dev->ops->handle_hw_ras_error)
1831 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 1832 else
1833 return PCI_ERS_RESULT_NONE;
1834
1835 return ret;
1836}
1837
6ae4e733
SJ		 1838static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1839{
1840 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1841 struct device *dev = &pdev->dev;
1842
1843 dev_info(dev, "requesting reset due to PCI error\n");
1844
1845 /* request the reset */
1846 if (ae_dev->ops->reset_event) {
1847 ae_dev->ops->reset_event(pdev, NULL);
1848 return PCI_ERS_RESULT_RECOVERED;
1849 }
1850
1851 return PCI_ERS_RESULT_DISCONNECT;
1852}
1853
6b9a97ee
HT		 1854static void hns3_reset_prepare(struct pci_dev *pdev)
1855{
1856 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1857
1858 dev_info(&pdev->dev, "hns3 flr prepare\n");
1859 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1860 ae_dev->ops->flr_prepare(ae_dev);
1861}
1862
1863static void hns3_reset_done(struct pci_dev *pdev)
1864{
1865 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1866
1867 dev_info(&pdev->dev, "hns3 flr done\n");
1868 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1869 ae_dev->ops->flr_done(ae_dev);
1870}
1871
5a9f0eac
SJ		 1872static const struct pci_error_handlers hns3_err_handler = {
1873 .error_detected = hns3_error_detected,
6ae4e733 1874 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 1875 .reset_prepare = hns3_reset_prepare,
1876 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 1877};
1878
76ad4f0e
S		 1879static struct pci_driver hns3_driver = {
1880 .name = hns3_driver_name,
1881 .id_table = hns3_pci_tbl,
1882 .probe = hns3_probe,
1883 .remove = hns3_remove,
ce2c1d2e 1884 .shutdown = hns3_shutdown,
fa8d82e8 1885 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 1886 .err_handler = &hns3_err_handler,
76ad4f0e
S		 1887};
1888
1889/* set default feature to hns3 */
1890static void hns3_set_default_feature(struct net_device *netdev)
1891{
3e85af6a
PL		 1892 struct hnae3_handle *h = hns3_get_handle(netdev);
1893 struct pci_dev *pdev = h->pdev;
1894
76ad4f0e
S		 1895 netdev->priv_flags |= IFF_UNICAST_FLT;
1896
1897 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1898 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1899 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1900 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1901 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1902
1903 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1904
1905 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1906
1907 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1908 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 1909 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1910 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1911 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1912 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1913 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1914
1915 netdev->vlan_features |=
1916 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1917 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1918 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1919 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1920 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1921
1922 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 1923 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1924 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1925 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1926 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1927 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
3e85af6a 1928
c17852a8 1929 if (pdev->revision >= 0x21) {
5c9f6b39
PL		 1930 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER |
1931 NETIF_F_GRO_HW;
1932 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 1933
1934 if (!(h->flags & HNAE3_SUPPORT_VF)) {
1935 netdev->hw_features |= NETIF_F_NTUPLE;
1936 netdev->features |= NETIF_F_NTUPLE;
1937 }
1938 }
76ad4f0e
S		 1939}
1940
1941static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1942 struct hns3_desc_cb *cb)
1943{
e4e87715 1944 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 1945 struct page *p;
1946
1947 p = dev_alloc_pages(order);
1948 if (!p)
1949 return -ENOMEM;
1950
1951 cb->priv = p;
1952 cb->page_offset = 0;
1953 cb->reuse_flag = 0;
1954 cb->buf = page_address(p);
e4e87715 1955 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 1956 cb->type = DESC_TYPE_PAGE;
1957
76ad4f0e
S		 1958 return 0;
1959}
1960
1961static void hns3_free_buffer(struct hns3_enet_ring *ring,
1962 struct hns3_desc_cb *cb)
1963{
1964 if (cb->type == DESC_TYPE_SKB)
1965 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1966 else if (!HNAE3_IS_TX_RING(ring))
1967 put_page((struct page *)cb->priv);
1968 memset(cb, 0, sizeof(*cb));
1969}
1970
1971static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1972{
1973 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1974 cb->length, ring_to_dma_dir(ring));
1975
2211f4e1 1976 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 1977 return -EIO;
1978
1979 return 0;
1980}
1981
1982static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1983 struct hns3_desc_cb *cb)
1984{
1985 if (cb->type == DESC_TYPE_SKB)
1986 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1987 ring_to_dma_dir(ring));
bcdb12b7 1988 else if (cb->length)
76ad4f0e
S		 1989 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1990 ring_to_dma_dir(ring));
1991}
1992
1993static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1994{
1995 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1996 ring->desc[i].addr = 0;
1997}
1998
1999static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2000{
2001 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2002
2003 if (!ring->desc_cb[i].dma)
2004 return;
2005
2006 hns3_buffer_detach(ring, i);
2007 hns3_free_buffer(ring, cb);
2008}
2009
2010static void hns3_free_buffers(struct hns3_enet_ring *ring)
2011{
2012 int i;
2013
2014 for (i = 0; i < ring->desc_num; i++)
2015 hns3_free_buffer_detach(ring, i);
2016}
2017
2018/* free desc along with its attached buffer */
2019static void hns3_free_desc(struct hns3_enet_ring *ring)
2020{
024cc792
HT		 2021 int size = ring->desc_num * sizeof(ring->desc[0]);
2022
76ad4f0e
S		 2023 hns3_free_buffers(ring);
2024
024cc792
HT		 2025 if (ring->desc) {
2026 dma_free_coherent(ring_to_dev(ring), size,
2027 ring->desc, ring->desc_dma_addr);
2028 ring->desc = NULL;
2029 }
76ad4f0e
S		 2030}
2031
2032static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2033{
2034 int size = ring->desc_num * sizeof(ring->desc[0]);
2035
024cc792
HT		 2036 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size,
2037 &ring->desc_dma_addr,
2038 GFP_KERNEL);
76ad4f0e
S		 2039 if (!ring->desc)
2040 return -ENOMEM;
2041
76ad4f0e
S		 2042 return 0;
2043}
2044
2045static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2046 struct hns3_desc_cb *cb)
2047{
2048 int ret;
2049
2050 ret = hns3_alloc_buffer(ring, cb);
2051 if (ret)
2052 goto out;
2053
2054 ret = hns3_map_buffer(ring, cb);
2055 if (ret)
2056 goto out_with_buf;
2057
2058 return 0;
2059
2060out_with_buf:
564883bb 2061 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2062out:
2063 return ret;
2064}
2065
2066static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2067{
2068 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2069
2070 if (ret)
2071 return ret;
2072
2073 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2074
2075 return 0;
2076}
2077
2078/* Allocate memory for raw pkg, and map with dma */
2079static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2080{
2081 int i, j, ret;
2082
2083 for (i = 0; i < ring->desc_num; i++) {
2084 ret = hns3_alloc_buffer_attach(ring, i);
2085 if (ret)
2086 goto out_buffer_fail;
2087 }
2088
2089 return 0;
2090
2091out_buffer_fail:
2092 for (j = i - 1; j >= 0; j--)
2093 hns3_free_buffer_detach(ring, j);
2094 return ret;
2095}
2096
2097/* detach a in-used buffer and replace with a reserved one */
2098static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2099 struct hns3_desc_cb *res_cb)
2100{
b9077428 2101 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2102 ring->desc_cb[i] = *res_cb;
2103 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2104 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2105}
2106
2107static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2108{
2109 ring->desc_cb[i].reuse_flag = 0;
2110 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2111 + ring->desc_cb[i].page_offset);
7d0b130c 2112 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2113}
2114
2115static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
2116 int *pkts)
2117{
2118 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2119
2120 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2121 (*bytes) += desc_cb->length;
e4e87715 2122 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
76ad4f0e
S		 2123 hns3_free_buffer_detach(ring, ring->next_to_clean);
2124
2125 ring_ptr_move_fw(ring, next_to_clean);
2126}
2127
2128static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2129{
2130 int u = ring->next_to_use;
2131 int c = ring->next_to_clean;
2132
2133 if (unlikely(h > ring->desc_num))
2134 return 0;
2135
2136 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2137}
2138
799997a3 2139void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 2140{
2141 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
7a810110 2142 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2143 struct netdev_queue *dev_queue;
2144 int bytes, pkts;
2145 int head;
2146
2147 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2148 rmb(); /* Make sure head is ready before touch any data */
2149
2150 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2151 return; /* no data to poll */
76ad4f0e 2152
0e6084aa 2153 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 2154 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2155 ring->next_to_use, ring->next_to_clean);
2156
2157 u64_stats_update_begin(&ring->syncp);
2158 ring->stats.io_err_cnt++;
2159 u64_stats_update_end(&ring->syncp);
799997a3 2160 return;
76ad4f0e
S		 2161 }
2162
2163 bytes = 0;
2164 pkts = 0;
799997a3 2165 while (head != ring->next_to_clean) {
76ad4f0e
S		 2166 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
2167 /* Issue prefetch for next Tx descriptor */
2168 prefetch(&ring->desc_cb[ring->next_to_clean]);
76ad4f0e
S		 2169 }
2170
2171 ring->tqp_vector->tx_group.total_bytes += bytes;
2172 ring->tqp_vector->tx_group.total_packets += pkts;
2173
2174 u64_stats_update_begin(&ring->syncp);
2175 ring->stats.tx_bytes += bytes;
2176 ring->stats.tx_pkts += pkts;
2177 u64_stats_update_end(&ring->syncp);
2178
2179 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2180 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2181
2182 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2183 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2184 /* Make sure that anybody stopping the queue after this
2185 * sees the new next_to_clean.
2186 */
2187 smp_mb();
7a810110
JS		 2188 if (netif_tx_queue_stopped(dev_queue) &&
2189 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2190 netif_tx_wake_queue(dev_queue);
2191 ring->stats.restart_queue++;
2192 }
2193 }
76ad4f0e
S		 2194}
2195
2196static int hns3_desc_unused(struct hns3_enet_ring *ring)
2197{
2198 int ntc = ring->next_to_clean;
2199 int ntu = ring->next_to_use;
2200
2201 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2202}
2203
2204static void
2205hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2206{
2207 struct hns3_desc_cb *desc_cb;
2208 struct hns3_desc_cb res_cbs;
2209 int i, ret;
2210
2211 for (i = 0; i < cleand_count; i++) {
2212 desc_cb = &ring->desc_cb[ring->next_to_use];
2213 if (desc_cb->reuse_flag) {
2214 u64_stats_update_begin(&ring->syncp);
2215 ring->stats.reuse_pg_cnt++;
2216 u64_stats_update_end(&ring->syncp);
2217
2218 hns3_reuse_buffer(ring, ring->next_to_use);
2219 } else {
2220 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2221 if (ret) {
2222 u64_stats_update_begin(&ring->syncp);
2223 ring->stats.sw_err_cnt++;
2224 u64_stats_update_end(&ring->syncp);
2225
2226 netdev_err(ring->tqp->handle->kinfo.netdev,
2227 "hnae reserve buffer map failed.\n");
2228 break;
2229 }
2230 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2231 }
2232
2233 ring_ptr_move_fw(ring, next_to_use);
2234 }
2235
2236 wmb(); /* Make all data has been write before submit */
2237 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2238}
2239
76ad4f0e
S		 2240static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2241 struct hns3_enet_ring *ring, int pull_len,
2242 struct hns3_desc_cb *desc_cb)
2243{
2244 struct hns3_desc *desc;
583e7281
HT		 2245 u32 truesize;
2246 int size;
76ad4f0e
S		 2247 int last_offset;
2248 bool twobufs;
2249
2250 twobufs = ((PAGE_SIZE < 8192) &&
e4e87715 2251 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
76ad4f0e
S		 2252
2253 desc = &ring->desc[ring->next_to_clean];
2254 size = le16_to_cpu(desc->rx.size);
2255
e4e87715 2256 truesize = hnae3_buf_size(ring);
f8d291f0
PL		 2257
2258 if (!twobufs)
e4e87715 2259 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
76ad4f0e
S		 2260
2261 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2262 size - pull_len, truesize);
76ad4f0e
S		 2263
2264 /* Avoid re-using remote pages,flag default unreuse */
2265 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2266 return;
2267
2268 if (twobufs) {
2269 /* If we are only owner of page we can reuse it */
2270 if (likely(page_count(desc_cb->priv) == 1)) {
2271 /* Flip page offset to other buffer */
2272 desc_cb->page_offset ^= truesize;
2273
2274 desc_cb->reuse_flag = 1;
2275 /* bump ref count on page before it is given*/
2276 get_page(desc_cb->priv);
2277 }
2278 return;
2279 }
2280
2281 /* Move offset up to the next cache line */
2282 desc_cb->page_offset += truesize;
2283
2284 if (desc_cb->page_offset <= last_offset) {
2285 desc_cb->reuse_flag = 1;
2286 /* Bump ref count on page before it is given*/
2287 get_page(desc_cb->priv);
2288 }
2289}
2290
2291static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2292 struct hns3_desc *desc)
2293{
2294 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2295 int l3_type, l4_type;
2296 u32 bd_base_info;
2297 int ol4_type;
2298 u32 l234info;
2299
2300 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2301 l234info = le32_to_cpu(desc->rx.l234_info);
2302
2303 skb->ip_summed = CHECKSUM_NONE;
2304
2305 skb_checksum_none_assert(skb);
2306
2307 if (!(netdev->features & NETIF_F_RXCSUM))
2308 return;
2309
a6d53b97
PL		 2310 /* We MUST enable hardware checksum before enabling hardware GRO */
2311 if (skb_shinfo(skb)->gso_size) {
2312 skb->ip_summed = CHECKSUM_UNNECESSARY;
2313 return;
2314 }
2315
76ad4f0e 2316 /* check if hardware has done checksum */
e4e87715 2317 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
76ad4f0e
S		 2318 return;
2319
e4e87715
PL		 2320 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2321 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2322 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2323 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
76ad4f0e
S		 2324 u64_stats_update_begin(&ring->syncp);
2325 ring->stats.l3l4_csum_err++;
2326 u64_stats_update_end(&ring->syncp);
2327
2328 return;
2329 }
2330
e4e87715
PL		 2331 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2332 HNS3_RXD_L3ID_S);
2333 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2334 HNS3_RXD_L4ID_S);
76ad4f0e 2335
e4e87715
PL		 2336 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2337 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2338 switch (ol4_type) {
2339 case HNS3_OL4_TYPE_MAC_IN_UDP:
2340 case HNS3_OL4_TYPE_NVGRE:
2341 skb->csum_level = 1;
be44b3af 2342 /* fall through */
76ad4f0e
S		 2343 case HNS3_OL4_TYPE_NO_TUN:
2344 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2345 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2346 l3_type == HNS3_L3_TYPE_IPV6) &&
2347 (l4_type == HNS3_L4_TYPE_UDP ||
2348 l4_type == HNS3_L4_TYPE_TCP ||
2349 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2350 skb->ip_summed = CHECKSUM_UNNECESSARY;
2351 break;
fa7a4bd5
JS		 2352 default:
2353 break;
76ad4f0e
S		 2354 }
2355}
2356
d43e5aca
YL		 2357static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2358{
81ae0e04
PL		 2359 if (skb_has_frag_list(skb))
2360 napi_gro_flush(&ring->tqp_vector->napi, false);
2361
d43e5aca
YL		 2362 napi_gro_receive(&ring->tqp_vector->napi, skb);
2363}
2364
701a6d6a
JS		 2365static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2366 struct hns3_desc *desc, u32 l234info,
2367 u16 *vlan_tag)
5b5455a9
PL		 2368{
2369 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL		 2370
2371 if (pdev->revision == 0x20) {
701a6d6a
JS		 2372 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2373 if (!(*vlan_tag & VLAN_VID_MASK))
2374 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2375
701a6d6a 2376 return (*vlan_tag != 0);
5b5455a9
PL		 2377 }
2378
2379#define HNS3_STRP_OUTER_VLAN 0x1
2380#define HNS3_STRP_INNER_VLAN 0x2
2381
e4e87715
PL		 2382 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2383 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2384 case HNS3_STRP_OUTER_VLAN:
701a6d6a
JS		 2385 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2386 return true;
5b5455a9 2387 case HNS3_STRP_INNER_VLAN:
701a6d6a
JS		 2388 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2389 return true;
5b5455a9 2390 default:
701a6d6a 2391 return false;
5b5455a9 2392 }
5b5455a9
PL		 2393}
2394
e5597095
PL		 2395static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2396 unsigned char *va)
2397{
2398#define HNS3_NEED_ADD_FRAG 1
2399 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2400 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2401 struct sk_buff *skb;
2402
2403 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2404 skb = ring->skb;
2405 if (unlikely(!skb)) {
2406 netdev_err(netdev, "alloc rx skb fail\n");
2407
2408 u64_stats_update_begin(&ring->syncp);
2409 ring->stats.sw_err_cnt++;
2410 u64_stats_update_end(&ring->syncp);
2411
2412 return -ENOMEM;
2413 }
2414
2415 prefetchw(skb->data);
2416
2417 ring->pending_buf = 1;
81ae0e04
PL		 2418 ring->frag_num = 0;
2419 ring->tail_skb = NULL;
e5597095
PL		 2420 if (length <= HNS3_RX_HEAD_SIZE) {
2421 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2422
2423 /* We can reuse buffer as-is, just make sure it is local */
2424 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2425 desc_cb->reuse_flag = 1;
2426 else /* This page cannot be reused so discard it */
2427 put_page(desc_cb->priv);
2428
2429 ring_ptr_move_fw(ring, next_to_clean);
2430 return 0;
2431 }
2432 u64_stats_update_begin(&ring->syncp);
2433 ring->stats.seg_pkt_cnt++;
2434 u64_stats_update_end(&ring->syncp);
2435
2436 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2437 __skb_put(skb, ring->pull_len);
81ae0e04 2438 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL		 2439 desc_cb);
2440 ring_ptr_move_fw(ring, next_to_clean);
2441
2442 return HNS3_NEED_ADD_FRAG;
2443}
2444
2445static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2446 struct sk_buff **out_skb, bool pending)
2447{
2448 struct sk_buff *skb = *out_skb;
81ae0e04
PL		 2449 struct sk_buff *head_skb = *out_skb;
2450 struct sk_buff *new_skb;
e5597095
PL		 2451 struct hns3_desc_cb *desc_cb;
2452 struct hns3_desc *pre_desc;
2453 u32 bd_base_info;
2454 int pre_bd;
2455
2456 /* if there is pending bd, the SW param next_to_clean has moved
2457 * to next and the next is NULL
2458 */
2459 if (pending) {
2460 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2461 ring->desc_num;
2462 pre_desc = &ring->desc[pre_bd];
2463 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2464 } else {
2465 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2466 }
2467
2468 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2469 desc = &ring->desc[ring->next_to_clean];
2470 desc_cb = &ring->desc_cb[ring->next_to_clean];
2471 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2472 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2473 return -ENXIO;
2474
81ae0e04
PL		 2475 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2476 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2477 HNS3_RX_HEAD_SIZE);
2478 if (unlikely(!new_skb)) {
2479 netdev_err(ring->tqp->handle->kinfo.netdev,
2480 "alloc rx skb frag fail\n");
2481 return -ENXIO;
2482 }
2483 ring->frag_num = 0;
2484
2485 if (ring->tail_skb) {
2486 ring->tail_skb->next = new_skb;
2487 ring->tail_skb = new_skb;
2488 } else {
2489 skb_shinfo(skb)->frag_list = new_skb;
2490 ring->tail_skb = new_skb;
2491 }
2492 }
2493
2494 if (ring->tail_skb) {
2495 head_skb->truesize += hnae3_buf_size(ring);
2496 head_skb->data_len += le16_to_cpu(desc->rx.size);
2497 head_skb->len += le16_to_cpu(desc->rx.size);
2498 skb = ring->tail_skb;
2499 }
2500
2501 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
e5597095
PL		 2502 ring_ptr_move_fw(ring, next_to_clean);
2503 ring->pending_buf++;
2504 }
2505
2506 return 0;
2507}
2508
a6d53b97
PL		 2509static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info,
2510 u32 bd_base_info)
2511{
2512 u16 gro_count;
2513 u32 l3_type;
2514
2515 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2516 HNS3_RXD_GRO_COUNT_S);
2517 /* if there is no HW GRO, do not set gro params */
2518 if (!gro_count)
2519 return;
2520
2521 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
2522 * to skb_shinfo(skb)->gso_segs
2523 */
2524 NAPI_GRO_CB(skb)->count = gro_count;
2525
2526 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2527 HNS3_RXD_L3ID_S);
2528 if (l3_type == HNS3_L3_TYPE_IPV4)
2529 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2530 else if (l3_type == HNS3_L3_TYPE_IPV6)
2531 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2532 else
2533 return;
2534
2535 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2536 HNS3_RXD_GRO_SIZE_M,
2537 HNS3_RXD_GRO_SIZE_S);
2538 if (skb_shinfo(skb)->gso_size)
2539 tcp_gro_complete(skb);
2540}
2541
232fc64b
PL		 2542static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2543 struct sk_buff *skb)
2544{
2545 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2546 struct hnae3_handle *handle = ring->tqp->handle;
2547 enum pkt_hash_types rss_type;
2548
2549 if (le32_to_cpu(desc->rx.rss_hash))
2550 rss_type = handle->kinfo.rss_type;
2551 else
2552 rss_type = PKT_HASH_TYPE_NONE;
2553
2554 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type);
2555}
2556
76ad4f0e 2557static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
e5597095 2558 struct sk_buff **out_skb)
76ad4f0e
S		 2559{
2560 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
e5597095 2561 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 2562 struct hns3_desc_cb *desc_cb;
2563 struct hns3_desc *desc;
76ad4f0e 2564 u32 bd_base_info;
76ad4f0e
S		 2565 u32 l234info;
2566 int length;
e5597095 2567 int ret;
76ad4f0e
S		 2568
2569 desc = &ring->desc[ring->next_to_clean];
2570 desc_cb = &ring->desc_cb[ring->next_to_clean];
2571
2572 prefetch(desc);
2573
846fcc83 2574 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2575 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2576
2577 /* Check valid BD */
e4e87715 2578 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
e5597095 2579 return -ENXIO;
76ad4f0e 2580
e5597095
PL		 2581 if (!skb)
2582 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S		 2583
2584 /* Prefetch first cache line of first page
2585 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2586 * line size is 64B so need to prefetch twice to make it 128B. But in
2587 * actual we can have greater size of caches with 128B Level 1 cache
2588 * lines. In such a case, single fetch would suffice to cache in the
2589 * relevant part of the header.
2590 */
e5597095 2591 prefetch(ring->va);
76ad4f0e 2592#if L1_CACHE_BYTES < 128
e5597095 2593 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S		 2594#endif
2595
e5597095
PL		 2596 if (!skb) {
2597 ret = hns3_alloc_skb(ring, length, ring->va);
2598 *out_skb = skb = ring->skb;
76ad4f0e 2599
e5597095
PL		 2600 if (ret < 0) /* alloc buffer fail */
2601 return ret;
2602 if (ret > 0) { /* need add frag */
2603 ret = hns3_add_frag(ring, desc, &skb, false);
2604 if (ret)
2605 return ret;
76ad4f0e 2606
e5597095
PL		 2607 /* As the head data may be changed when GRO enable, copy
2608 * the head data in after other data rx completed
2609 */
2610 memcpy(skb->data, ring->va,
2611 ALIGN(ring->pull_len, sizeof(long)));
2612 }
76ad4f0e 2613 } else {
e5597095
PL		 2614 ret = hns3_add_frag(ring, desc, &skb, true);
2615 if (ret)
2616 return ret;
76ad4f0e 2617
e5597095
PL		 2618 /* As the head data may be changed when GRO enable, copy
2619 * the head data in after other data rx completed
2620 */
2621 memcpy(skb->data, ring->va,
2622 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S		 2623 }
2624
5b5455a9 2625 l234info = le32_to_cpu(desc->rx.l234_info);
e5597095 2626 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
5b5455a9 2627
846fcc83
PL		 2628 /* Based on hw strategy, the tag offloaded will be stored at
2629 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2630 * in one layer tag case.
2631 */
2632 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2633 u16 vlan_tag;
2634
701a6d6a 2635 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
846fcc83
PL		 2636 __vlan_hwaccel_put_tag(skb,
2637 htons(ETH_P_8021Q),
2638 vlan_tag);
2639 }
2640
e4e87715 2641 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
76ad4f0e
S		 2642 u64_stats_update_begin(&ring->syncp);
2643 ring->stats.non_vld_descs++;
2644 u64_stats_update_end(&ring->syncp);
2645
2646 dev_kfree_skb_any(skb);
2647 return -EINVAL;
2648 }
2649
2650 if (unlikely((!desc->rx.pkt_len) ||
e4e87715 2651 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
76ad4f0e
S		 2652 u64_stats_update_begin(&ring->syncp);
2653 ring->stats.err_pkt_len++;
2654 u64_stats_update_end(&ring->syncp);
2655
2656 dev_kfree_skb_any(skb);
2657 return -EFAULT;
2658 }
2659
e4e87715 2660 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
76ad4f0e
S		 2661 u64_stats_update_begin(&ring->syncp);
2662 ring->stats.l2_err++;
2663 u64_stats_update_end(&ring->syncp);
2664
2665 dev_kfree_skb_any(skb);
2666 return -EFAULT;
2667 }
2668
2669 u64_stats_update_begin(&ring->syncp);
2670 ring->stats.rx_pkts++;
2671 ring->stats.rx_bytes += skb->len;
2672 u64_stats_update_end(&ring->syncp);
2673
2674 ring->tqp_vector->rx_group.total_bytes += skb->len;
2675
a6d53b97
PL		 2676 /* This is needed in order to enable forwarding support */
2677 hns3_set_gro_param(skb, l234info, bd_base_info);
2678
76ad4f0e 2679 hns3_rx_checksum(ring, skb, desc);
e5597095 2680 *out_skb = skb;
232fc64b
PL		 2681 hns3_set_rx_skb_rss_type(ring, skb);
2682
76ad4f0e
S		 2683 return 0;
2684}
2685
d43e5aca
YL		 2686int hns3_clean_rx_ring(
2687 struct hns3_enet_ring *ring, int budget,
2688 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2689{
2690#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2691 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2692 int recv_pkts, recv_bds, clean_count, err;
e5597095
PL		 2693 int unused_count = hns3_desc_unused(ring) - ring->pending_buf;
2694 struct sk_buff *skb = ring->skb;
2695 int num;
76ad4f0e
S		 2696
2697 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2698 rmb(); /* Make sure num taken effect before the other data is touched */
2699
2700 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2701 num -= unused_count;
2702
2703 while (recv_pkts < budget && recv_bds < num) {
2704 /* Reuse or realloc buffers */
2705 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2706 hns3_nic_alloc_rx_buffers(ring,
2707 clean_count + unused_count);
2708 clean_count = 0;
e5597095
PL		 2709 unused_count = hns3_desc_unused(ring) -
2710 ring->pending_buf;
76ad4f0e
S		 2711 }
2712
2713 /* Poll one pkt */
e5597095 2714 err = hns3_handle_rx_bd(ring, &skb);
76ad4f0e
S		 2715 if (unlikely(!skb)) /* This fault cannot be repaired */
2716 goto out;
2717
e5597095
PL		 2718 if (err == -ENXIO) { /* Do not get FE for the packet */
2719 goto out;
2720 } else if (unlikely(err)) { /* Do jump the err */
2721 recv_bds += ring->pending_buf;
2722 clean_count += ring->pending_buf;
2723 ring->skb = NULL;
2724 ring->pending_buf = 0;
76ad4f0e
S		 2725 continue;
2726 }
2727
2728 /* Do update ip stack process */
2729 skb->protocol = eth_type_trans(skb, netdev);
d43e5aca 2730 rx_fn(ring, skb);
e5597095
PL		 2731 recv_bds += ring->pending_buf;
2732 clean_count += ring->pending_buf;
2733 ring->skb = NULL;
2734 ring->pending_buf = 0;
76ad4f0e
S		 2735
2736 recv_pkts++;
2737 }
2738
2739out:
2740 /* Make all data has been write before submit */
2741 if (clean_count + unused_count > 0)
2742 hns3_nic_alloc_rx_buffers(ring,
2743 clean_count + unused_count);
2744
2745 return recv_pkts;
2746}
2747
2748static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2749{
a95e1f86
FL		 2750 struct hns3_enet_tqp_vector *tqp_vector =
2751 ring_group->ring->tqp_vector;
76ad4f0e 2752 enum hns3_flow_level_range new_flow_level;
a95e1f86
FL		 2753 int packets_per_msecs;
2754 int bytes_per_msecs;
2755 u32 time_passed_ms;
76ad4f0e 2756 u16 new_int_gl;
76ad4f0e 2757
a95e1f86 2758 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
76ad4f0e
S		 2759 return false;
2760
2761 if (ring_group->total_packets == 0) {
9bc727a9
YL		 2762 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2763 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2764 return true;
2765 }
2766
2767 /* Simple throttlerate management
2768 * 0-10MB/s lower (50000 ints/s)
2769 * 10-20MB/s middle (20000 ints/s)
2770 * 20-1249MB/s high (18000 ints/s)
2771 * > 40000pps ultra (8000 ints/s)
2772 */
9bc727a9
YL		 2773 new_flow_level = ring_group->coal.flow_level;
2774 new_int_gl = ring_group->coal.int_gl;
a95e1f86
FL		 2775 time_passed_ms =
2776 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2777
2778 if (!time_passed_ms)
2779 return false;
2780
2781 do_div(ring_group->total_packets, time_passed_ms);
2782 packets_per_msecs = ring_group->total_packets;
2783
2784 do_div(ring_group->total_bytes, time_passed_ms);
2785 bytes_per_msecs = ring_group->total_bytes;
2786
2787#define HNS3_RX_LOW_BYTE_RATE 10000
2788#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2789
2790 switch (new_flow_level) {
2791 case HNS3_FLOW_LOW:
a95e1f86 2792 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2793 new_flow_level = HNS3_FLOW_MID;
2794 break;
2795 case HNS3_FLOW_MID:
a95e1f86 2796 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2797 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 2798 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2799 new_flow_level = HNS3_FLOW_LOW;
2800 break;
2801 case HNS3_FLOW_HIGH:
2802 case HNS3_FLOW_ULTRA:
2803 default:
a95e1f86 2804 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2805 new_flow_level = HNS3_FLOW_MID;
2806 break;
2807 }
2808
a95e1f86
FL		 2809#define HNS3_RX_ULTRA_PACKET_RATE 40
2810
2811 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2812 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2813 new_flow_level = HNS3_FLOW_ULTRA;
2814
2815 switch (new_flow_level) {
2816 case HNS3_FLOW_LOW:
2817 new_int_gl = HNS3_INT_GL_50K;
2818 break;
2819 case HNS3_FLOW_MID:
2820 new_int_gl = HNS3_INT_GL_20K;
2821 break;
2822 case HNS3_FLOW_HIGH:
2823 new_int_gl = HNS3_INT_GL_18K;
2824 break;
2825 case HNS3_FLOW_ULTRA:
2826 new_int_gl = HNS3_INT_GL_8K;
2827 break;
2828 default:
2829 break;
2830 }
2831
2832 ring_group->total_bytes = 0;
2833 ring_group->total_packets = 0;
9bc727a9
YL		 2834 ring_group->coal.flow_level = new_flow_level;
2835 if (new_int_gl != ring_group->coal.int_gl) {
2836 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 2837 return true;
2838 }
2839 return false;
2840}
2841
2842static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2843{
8b1ff1ea
FL		 2844 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2845 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2846 bool rx_update, tx_update;
2847
7445565c
PL		 2848 /* update param every 1000ms */
2849 if (time_before(jiffies,
2850 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 2851 return;
cd9d187b 2852
9bc727a9 2853 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 2854 rx_update = hns3_get_new_int_gl(rx_group);
2855 if (rx_update)
2856 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 2857 rx_group->coal.int_gl);
8b1ff1ea
FL		 2858 }
2859
9bc727a9 2860 if (tx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 2861 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2862 if (tx_update)
2863 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 2864 tx_group->coal.int_gl);
76ad4f0e 2865 }
cd9d187b 2866
a95e1f86 2867 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 2868}
2869
2870static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2871{
ff0699e0 2872 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 2873 struct hns3_enet_ring *ring;
2874 int rx_pkt_total = 0;
2875
2876 struct hns3_enet_tqp_vector *tqp_vector =
2877 container_of(napi, struct hns3_enet_tqp_vector, napi);
2878 bool clean_complete = true;
2879 int rx_budget;
2880
ff0699e0
HT		 2881 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2882 napi_complete(napi);
2883 return 0;
2884 }
2885
76ad4f0e
S		 2886 /* Since the actual Tx work is minimal, we can give the Tx a larger
2887 * budget and be more aggressive about cleaning up the Tx descriptors.
2888 */
799997a3
PL		 2889 hns3_for_each_ring(ring, tqp_vector->tx_group)
2890 hns3_clean_tx_ring(ring);
76ad4f0e
S		 2891
2892 /* make sure rx ring budget not smaller than 1 */
2893 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2894
2895 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 2896 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2897 hns3_rx_skb);
76ad4f0e
S		 2898
2899 if (rx_cleaned >= rx_budget)
2900 clean_complete = false;
2901
2902 rx_pkt_total += rx_cleaned;
2903 }
2904
2905 tqp_vector->rx_group.total_packets += rx_pkt_total;
2906
2907 if (!clean_complete)
2908 return budget;
2909
531eba0f
HT		 2910 if (napi_complete(napi) &&
2911 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 2912 hns3_update_new_int_gl(tqp_vector);
2913 hns3_mask_vector_irq(tqp_vector, 1);
2914 }
76ad4f0e
S		 2915
2916 return rx_pkt_total;
2917}
2918
2919static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2920 struct hnae3_ring_chain_node *head)
2921{
2922 struct pci_dev *pdev = tqp_vector->handle->pdev;
2923 struct hnae3_ring_chain_node *cur_chain = head;
2924 struct hnae3_ring_chain_node *chain;
2925 struct hns3_enet_ring *tx_ring;
2926 struct hns3_enet_ring *rx_ring;
2927
2928 tx_ring = tqp_vector->tx_group.ring;
2929 if (tx_ring) {
2930 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 2931 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2932 HNAE3_RING_TYPE_TX);
2933 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2934 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 2935
2936 cur_chain->next = NULL;
2937
2938 while (tx_ring->next) {
2939 tx_ring = tx_ring->next;
2940
2941 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2942 GFP_KERNEL);
2943 if (!chain)
73b907a0 2944 goto err_free_chain;
76ad4f0e
S		 2945
2946 cur_chain->next = chain;
2947 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 2948 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2949 HNAE3_RING_TYPE_TX);
2950 hnae3_set_field(chain->int_gl_idx,
2951 HNAE3_RING_GL_IDX_M,
2952 HNAE3_RING_GL_IDX_S,
2953 HNAE3_RING_GL_TX);
76ad4f0e
S		 2954
2955 cur_chain = chain;
2956 }
2957 }
2958
2959 rx_ring = tqp_vector->rx_group.ring;
2960 if (!tx_ring && rx_ring) {
2961 cur_chain->next = NULL;
2962 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 2963 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2964 HNAE3_RING_TYPE_RX);
2965 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2966 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 2967
2968 rx_ring = rx_ring->next;
2969 }
2970
2971 while (rx_ring) {
2972 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2973 if (!chain)
73b907a0 2974 goto err_free_chain;
76ad4f0e
S		 2975
2976 cur_chain->next = chain;
2977 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 2978 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2979 HNAE3_RING_TYPE_RX);
2980 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2981 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 2982
76ad4f0e
S		 2983 cur_chain = chain;
2984
2985 rx_ring = rx_ring->next;
2986 }
2987
2988 return 0;
73b907a0
HT		 2989
2990err_free_chain:
2991 cur_chain = head->next;
2992 while (cur_chain) {
2993 chain = cur_chain->next;
cda69d24 2994 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 2995 cur_chain = chain;
2996 }
cda69d24 2997 head->next = NULL;
73b907a0
HT		 2998
2999 return -ENOMEM;
76ad4f0e
S		 3000}
3001
3002static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3003 struct hnae3_ring_chain_node *head)
3004{
3005 struct pci_dev *pdev = tqp_vector->handle->pdev;
3006 struct hnae3_ring_chain_node *chain_tmp, *chain;
3007
3008 chain = head->next;
3009
3010 while (chain) {
3011 chain_tmp = chain->next;
3012 devm_kfree(&pdev->dev, chain);
3013 chain = chain_tmp;
3014 }
3015}
3016
3017static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3018 struct hns3_enet_ring *ring)
3019{
3020 ring->next = group->ring;
3021 group->ring = ring;
3022
3023 group->count++;
3024}
3025
874bff0b
PL		 3026static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3027{
3028 struct pci_dev *pdev = priv->ae_handle->pdev;
3029 struct hns3_enet_tqp_vector *tqp_vector;
3030 int num_vectors = priv->vector_num;
3031 int numa_node;
3032 int vector_i;
3033
3034 numa_node = dev_to_node(&pdev->dev);
3035
3036 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3037 tqp_vector = &priv->tqp_vector[vector_i];
3038 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3039 &tqp_vector->affinity_mask);
3040 }
3041}
3042
76ad4f0e
S		 3043static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3044{
3045 struct hnae3_ring_chain_node vector_ring_chain;
3046 struct hnae3_handle *h = priv->ae_handle;
3047 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3048 int ret = 0;
ece4bf46 3049 int i;
76ad4f0e 3050
874bff0b
PL		 3051 hns3_nic_set_cpumask(priv);
3052
dd38c726
YL		 3053 for (i = 0; i < priv->vector_num; i++) {
3054 tqp_vector = &priv->tqp_vector[i];
3055 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3056 tqp_vector->num_tqps = 0;
3057 }
76ad4f0e 3058
dd38c726
YL		 3059 for (i = 0; i < h->kinfo.num_tqps; i++) {
3060 u16 vector_i = i % priv->vector_num;
3061 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3062
3063 tqp_vector = &priv->tqp_vector[vector_i];
3064
3065 hns3_add_ring_to_group(&tqp_vector->tx_group,
3066 priv->ring_data[i].ring);
3067
3068 hns3_add_ring_to_group(&tqp_vector->rx_group,
3069 priv->ring_data[i + tqp_num].ring);
3070
76ad4f0e
S		 3071 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3072 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
dd38c726 3073 tqp_vector->num_tqps++;
76ad4f0e
S		 3074 }
3075
dd38c726 3076 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3077 tqp_vector = &priv->tqp_vector[i];
3078
3079 tqp_vector->rx_group.total_bytes = 0;
3080 tqp_vector->rx_group.total_packets = 0;
3081 tqp_vector->tx_group.total_bytes = 0;
3082 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3083 tqp_vector->handle = h;
3084
3085 ret = hns3_get_vector_ring_chain(tqp_vector,
3086 &vector_ring_chain);
3087 if (ret)
cda69d24 3088 goto map_ring_fail;
76ad4f0e
S		 3089
3090 ret = h->ae_algo->ops->map_ring_to_vector(h,
3091 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3092
3093 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3094
dd38c726 3095 if (ret)
ece4bf46 3096 goto map_ring_fail;
dd38c726 3097
76ad4f0e
S		 3098 netif_napi_add(priv->netdev, &tqp_vector->napi,
3099 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3100 }
3101
dd38c726 3102 return 0;
ece4bf46
HT		 3103
3104map_ring_fail:
3105 while (i--)
3106 netif_napi_del(&priv->tqp_vector[i].napi);
3107
3108 return ret;
dd38c726
YL		 3109}
3110
3111static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3112{
3113 struct hnae3_handle *h = priv->ae_handle;
3114 struct hns3_enet_tqp_vector *tqp_vector;
3115 struct hnae3_vector_info *vector;
3116 struct pci_dev *pdev = h->pdev;
3117 u16 tqp_num = h->kinfo.num_tqps;
3118 u16 vector_num;
3119 int ret = 0;
3120 u16 i;
3121
3122 /* RSS size, cpu online and vector_num should be the same */
3123 /* Should consider 2p/4p later */
3124 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3125 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3126 GFP_KERNEL);
3127 if (!vector)
3128 return -ENOMEM;
3129
3130 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3131
3132 priv->vector_num = vector_num;
3133 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3134 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3135 GFP_KERNEL);
3136 if (!priv->tqp_vector) {
3137 ret = -ENOMEM;
3138 goto out;
3139 }
3140
3141 for (i = 0; i < priv->vector_num; i++) {
3142 tqp_vector = &priv->tqp_vector[i];
3143 tqp_vector->idx = i;
3144 tqp_vector->mask_addr = vector[i].io_addr;
3145 tqp_vector->vector_irq = vector[i].vector;
3146 hns3_vector_gl_rl_init(tqp_vector, priv);
3147 }
3148
76ad4f0e
S		 3149out:
3150 devm_kfree(&pdev->dev, vector);
3151 return ret;
3152}
3153
dd38c726
YL		 3154static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3155{
3156 group->ring = NULL;
3157 group->count = 0;
3158}
3159
76ad4f0e
S		 3160static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3161{
3162 struct hnae3_ring_chain_node vector_ring_chain;
3163 struct hnae3_handle *h = priv->ae_handle;
3164 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 3165 int i, ret;
3166
3167 for (i = 0; i < priv->vector_num; i++) {
3168 tqp_vector = &priv->tqp_vector[i];
3169
3170 ret = hns3_get_vector_ring_chain(tqp_vector,
3171 &vector_ring_chain);
3172 if (ret)
3173 return ret;
3174
3175 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
3176 tqp_vector->vector_irq, &vector_ring_chain);
3177 if (ret)
3178 return ret;
3179
3180 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3181
ae6017a7
HT		 3182 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3183 irq_set_affinity_notifier(tqp_vector->vector_irq,
3184 NULL);
3185 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3186 free_irq(tqp_vector->vector_irq, tqp_vector);
3187 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S		 3188 }
3189
3190 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
dd38c726
YL		 3191 hns3_clear_ring_group(&tqp_vector->rx_group);
3192 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3193 netif_napi_del(&priv->tqp_vector[i].napi);
3194 }
3195
dd38c726
YL		 3196 return 0;
3197}
3198
3199static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3200{
3201 struct hnae3_handle *h = priv->ae_handle;
3202 struct pci_dev *pdev = h->pdev;
3203 int i, ret;
3204
3205 for (i = 0; i < priv->vector_num; i++) {
3206 struct hns3_enet_tqp_vector *tqp_vector;
3207
3208 tqp_vector = &priv->tqp_vector[i];
3209 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3210 if (ret)
3211 return ret;
3212 }
76ad4f0e 3213
dd38c726 3214 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3215 return 0;
3216}
3217
3218static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3219 int ring_type)
3220{
3221 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3222 int queue_num = priv->ae_handle->kinfo.num_tqps;
3223 struct pci_dev *pdev = priv->ae_handle->pdev;
3224 struct hns3_enet_ring *ring;
3225
3226 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3227 if (!ring)
3228 return -ENOMEM;
3229
3230 if (ring_type == HNAE3_RING_TYPE_TX) {
3231 ring_data[q->tqp_index].ring = ring;
66b44730 3232 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 3233 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3234 } else {
3235 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 3236 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 3237 ring->io_base = q->io_base;
3238 }
3239
e4e87715 3240 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3241
76ad4f0e
S		 3242 ring->tqp = q;
3243 ring->desc = NULL;
3244 ring->desc_cb = NULL;
3245 ring->dev = priv->dev;
3246 ring->desc_dma_addr = 0;
3247 ring->buf_size = q->buf_size;
3248 ring->desc_num = q->desc_num;
3249 ring->next_to_use = 0;
3250 ring->next_to_clean = 0;
3251
3252 return 0;
3253}
3254
3255static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3256 struct hns3_nic_priv *priv)
3257{
3258 int ret;
3259
3260 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3261 if (ret)
3262 return ret;
3263
3264 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
73b907a0
HT		 3265 if (ret) {
3266 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
76ad4f0e 3267 return ret;
73b907a0 3268 }
76ad4f0e
S		 3269
3270 return 0;
3271}
3272
3273static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3274{
3275 struct hnae3_handle *h = priv->ae_handle;
3276 struct pci_dev *pdev = h->pdev;
3277 int i, ret;
3278
a86854d0
KC		 3279 priv->ring_data = devm_kzalloc(&pdev->dev,
3280 array3_size(h->kinfo.num_tqps,
3281 sizeof(*priv->ring_data),
3282 2),
76ad4f0e
S		 3283 GFP_KERNEL);
3284 if (!priv->ring_data)
3285 return -ENOMEM;
3286
3287 for (i = 0; i < h->kinfo.num_tqps; i++) {
3288 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3289 if (ret)
3290 goto err;
3291 }
3292
3293 return 0;
3294err:
73b907a0
HT		 3295 while (i--) {
3296 devm_kfree(priv->dev, priv->ring_data[i].ring);
3297 devm_kfree(priv->dev,
3298 priv->ring_data[i + h->kinfo.num_tqps].ring);
3299 }
3300
76ad4f0e
S		 3301 devm_kfree(&pdev->dev, priv->ring_data);
3302 return ret;
3303}
3304
09f2af64
PL		 3305static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3306{
3307 struct hnae3_handle *h = priv->ae_handle;
3308 int i;
3309
3310 for (i = 0; i < h->kinfo.num_tqps; i++) {
3311 devm_kfree(priv->dev, priv->ring_data[i].ring);
3312 devm_kfree(priv->dev,
3313 priv->ring_data[i + h->kinfo.num_tqps].ring);
3314 }
3315 devm_kfree(priv->dev, priv->ring_data);
3316}
3317
76ad4f0e
S		 3318static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3319{
3320 int ret;
3321
3322 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3323 return -EINVAL;
3324
3325 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
3326 GFP_KERNEL);
3327 if (!ring->desc_cb) {
3328 ret = -ENOMEM;
3329 goto out;
3330 }
3331
3332 ret = hns3_alloc_desc(ring);
3333 if (ret)
3334 goto out_with_desc_cb;
3335
3336 if (!HNAE3_IS_TX_RING(ring)) {
3337 ret = hns3_alloc_ring_buffers(ring);
3338 if (ret)
3339 goto out_with_desc;
3340 }
3341
3342 return 0;
3343
3344out_with_desc:
3345 hns3_free_desc(ring);
3346out_with_desc_cb:
3347 kfree(ring->desc_cb);
3348 ring->desc_cb = NULL;
3349out:
3350 return ret;
3351}
3352
3353static void hns3_fini_ring(struct hns3_enet_ring *ring)
3354{
3355 hns3_free_desc(ring);
3356 kfree(ring->desc_cb);
3357 ring->desc_cb = NULL;
3358 ring->next_to_clean = 0;
3359 ring->next_to_use = 0;
3360}
3361
1db9b1bf 3362static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3363{
3364 int bd_size_type;
3365
3366 switch (buf_size) {
3367 case 512:
3368 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3369 break;
3370 case 1024:
3371 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3372 break;
3373 case 2048:
3374 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3375 break;
3376 case 4096:
3377 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3378 break;
3379 default:
3380 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3381 }
3382
3383 return bd_size_type;
3384}
3385
3386static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3387{
3388 dma_addr_t dma = ring->desc_dma_addr;
3389 struct hnae3_queue *q = ring->tqp;
3390
3391 if (!HNAE3_IS_TX_RING(ring)) {
3392 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3393 (u32)dma);
3394 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3395 (u32)((dma >> 31) >> 1));
3396
3397 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3398 hns3_buf_size2type(ring->buf_size));
3399 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3400 ring->desc_num / 8 - 1);
3401
3402 } else {
3403 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3404 (u32)dma);
3405 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3406 (u32)((dma >> 31) >> 1));
3407
76ad4f0e
S		 3408 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3409 ring->desc_num / 8 - 1);
3410 }
3411}
3412
1c772154
YL		 3413static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3414{
3415 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3416 int i;
3417
3418 for (i = 0; i < HNAE3_MAX_TC; i++) {
3419 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3420 int j;
3421
3422 if (!tc_info->enable)
3423 continue;
3424
3425 for (j = 0; j < tc_info->tqp_count; j++) {
3426 struct hnae3_queue *q;
3427
3428 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3429 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3430 tc_info->tc);
3431 }
3432 }
3433}
3434
5668abda 3435int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3436{
3437 struct hnae3_handle *h = priv->ae_handle;
3438 int ring_num = h->kinfo.num_tqps * 2;
3439 int i, j;
3440 int ret;
3441
3442 for (i = 0; i < ring_num; i++) {
3443 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3444 if (ret) {
3445 dev_err(priv->dev,
3446 "Alloc ring memory fail! ret=%d\n", ret);
3447 goto out_when_alloc_ring_memory;
3448 }
3449
76ad4f0e
S		 3450 u64_stats_init(&priv->ring_data[i].ring->syncp);
3451 }
3452
3453 return 0;
3454
3455out_when_alloc_ring_memory:
3456 for (j = i - 1; j >= 0; j--)
ee83f776 3457 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3458
3459 return -ENOMEM;
3460}
3461
5668abda 3462int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3463{
3464 struct hnae3_handle *h = priv->ae_handle;
3465 int i;
3466
3467 for (i = 0; i < h->kinfo.num_tqps; i++) {
76ad4f0e
S		 3468 hns3_fini_ring(priv->ring_data[i].ring);
3469 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3470 }
76ad4f0e
S		 3471 return 0;
3472}
3473
3474/* Set mac addr if it is configured. or leave it to the AE driver */
7fa6be4f 3475static int hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3476{
3477 struct hns3_nic_priv *priv = netdev_priv(netdev);
3478 struct hnae3_handle *h = priv->ae_handle;
3479 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3480 int ret = 0;
76ad4f0e 3481
f09555ff 3482 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3483 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3484 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3485 }
3486
3487 /* Check if the MAC address is valid, if not get a random one */
3488 if (!is_valid_ether_addr(netdev->dev_addr)) {
3489 eth_hw_addr_random(netdev);
3490 dev_warn(priv->dev, "using random MAC address %pM\n",
3491 netdev->dev_addr);
76ad4f0e 3492 }
139e8792
L		 3493
3494 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3495 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3496
7fa6be4f 3497 return ret;
76ad4f0e
S		 3498}
3499
6871af29
JS		 3500static int hns3_restore_fd_rules(struct net_device *netdev)
3501{
3502 struct hnae3_handle *h = hns3_get_handle(netdev);
3503 int ret = 0;
3504
3505 if (h->ae_algo->ops->restore_fd_rules)
3506 ret = h->ae_algo->ops->restore_fd_rules(h);
3507
3508 return ret;
3509}
3510
3511static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3512{
3513 struct hnae3_handle *h = hns3_get_handle(netdev);
3514
3515 if (h->ae_algo->ops->del_all_fd_entries)
3516 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3517}
3518
76ad4f0e
S		 3519static void hns3_nic_set_priv_ops(struct net_device *netdev)
3520{
3521 struct hns3_nic_priv *priv = netdev_priv(netdev);
3522
0bbbf15d 3523 priv->ops.fill_desc = hns3_fill_desc;
76ad4f0e 3524 if ((netdev->features & NETIF_F_TSO) ||
0bbbf15d 3525 (netdev->features & NETIF_F_TSO6))
76ad4f0e 3526 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
0bbbf15d 3527 else
76ad4f0e 3528 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 3529}
3530
a6d818e3
YL		 3531static int hns3_client_start(struct hnae3_handle *handle)
3532{
3533 if (!handle->ae_algo->ops->client_start)
3534 return 0;
3535
3536 return handle->ae_algo->ops->client_start(handle);
3537}
3538
3539static void hns3_client_stop(struct hnae3_handle *handle)
3540{
3541 if (!handle->ae_algo->ops->client_stop)
3542 return;
3543
3544 handle->ae_algo->ops->client_stop(handle);
3545}
3546
76ad4f0e
S		 3547static int hns3_client_init(struct hnae3_handle *handle)
3548{
3549 struct pci_dev *pdev = handle->pdev;
0d43bf45 3550 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3551 struct hns3_nic_priv *priv;
3552 struct net_device *netdev;
3553 int ret;
3554
0d43bf45
HT		 3555 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3556 &max_rss_size);
3557 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3558 if (!netdev)
3559 return -ENOMEM;
3560
3561 priv = netdev_priv(netdev);
3562 priv->dev = &pdev->dev;
3563 priv->netdev = netdev;
3564 priv->ae_handle = handle;
f8fa222c 3565 priv->tx_timeout_count = 0;
76ad4f0e
S		 3566
3567 handle->kinfo.netdev = netdev;
3568 handle->priv = (void *)priv;
3569
f09555ff 3570 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3571
3572 hns3_set_default_feature(netdev);
3573
3574 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3575 netdev->priv_flags |= IFF_UNICAST_FLT;
3576 netdev->netdev_ops = &hns3_nic_netdev_ops;
3577 SET_NETDEV_DEV(netdev, &pdev->dev);
3578 hns3_ethtool_set_ops(netdev);
3579 hns3_nic_set_priv_ops(netdev);
3580
3581 /* Carrier off reporting is important to ethtool even BEFORE open */
3582 netif_carrier_off(netdev);
3583
3584 ret = hns3_get_ring_config(priv);
3585 if (ret) {
3586 ret = -ENOMEM;
3587 goto out_get_ring_cfg;
3588 }
3589
dd38c726
YL		 3590 ret = hns3_nic_alloc_vector_data(priv);
3591 if (ret) {
3592 ret = -ENOMEM;
3593 goto out_alloc_vector_data;
3594 }
3595
76ad4f0e
S		 3596 ret = hns3_nic_init_vector_data(priv);
3597 if (ret) {
3598 ret = -ENOMEM;
3599 goto out_init_vector_data;
3600 }
3601
3602 ret = hns3_init_all_ring(priv);
3603 if (ret) {
3604 ret = -ENOMEM;
3605 goto out_init_ring_data;
3606 }
3607
3608 ret = register_netdev(netdev);
3609 if (ret) {
3610 dev_err(priv->dev, "probe register netdev fail!\n");
3611 goto out_reg_netdev_fail;
3612 }
3613
a6d818e3
YL		 3614 ret = hns3_client_start(handle);
3615 if (ret) {
3616 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
3617 goto out_reg_netdev_fail;
3618 }
3619
986743db
YL		 3620 hns3_dcbnl_setup(handle);
3621
b2292360 3622 hns3_dbg_init(handle);
3623
a0b43717 3624 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 3625 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 3626
814da63c
HT		 3627 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3628
76ad4f0e
S		 3629 return ret;
3630
3631out_reg_netdev_fail:
3632out_init_ring_data:
3633 (void)hns3_nic_uninit_vector_data(priv);
76ad4f0e 3634out_init_vector_data:
dd38c726
YL		 3635 hns3_nic_dealloc_vector_data(priv);
3636out_alloc_vector_data:
3637 priv->ring_data = NULL;
76ad4f0e
S		 3638out_get_ring_cfg:
3639 priv->ae_handle = NULL;
3640 free_netdev(netdev);
3641 return ret;
3642}
3643
3644static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3645{
3646 struct net_device *netdev = handle->kinfo.netdev;
3647 struct hns3_nic_priv *priv = netdev_priv(netdev);
3648 int ret;
3649
a6d818e3
YL		 3650 hns3_client_stop(handle);
3651
f05e2109
JS		 3652 hns3_remove_hw_addr(netdev);
3653
76ad4f0e
S		 3654 if (netdev->reg_state != NETREG_UNINITIALIZED)
3655 unregister_netdev(netdev);
3656
814da63c
HT		 3657 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3658 netdev_warn(netdev, "already uninitialized\n");
3659 goto out_netdev_free;
3660 }
3661
dc5e6064
JS		 3662 hns3_del_all_fd_rules(netdev, true);
3663
7b763f3f
FL		 3664 hns3_force_clear_all_rx_ring(handle);
3665
76ad4f0e
S		 3666 ret = hns3_nic_uninit_vector_data(priv);
3667 if (ret)
3668 netdev_err(netdev, "uninit vector error\n");
3669
dd38c726
YL		 3670 ret = hns3_nic_dealloc_vector_data(priv);
3671 if (ret)
3672 netdev_err(netdev, "dealloc vector error\n");
3673
76ad4f0e
S		 3674 ret = hns3_uninit_all_ring(priv);
3675 if (ret)
3676 netdev_err(netdev, "uninit ring error\n");
3677
ec777890
YL		 3678 hns3_put_ring_config(priv);
3679
b2292360 3680 hns3_dbg_uninit(handle);
3681
76ad4f0e
S		 3682 priv->ring_data = NULL;
3683
814da63c 3684out_netdev_free:
76ad4f0e
S		 3685 free_netdev(netdev);
3686}
3687
3688static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3689{
3690 struct net_device *netdev = handle->kinfo.netdev;
3691
3692 if (!netdev)
3693 return;
3694
3695 if (linkup) {
3696 netif_carrier_on(netdev);
3697 netif_tx_wake_all_queues(netdev);
3698 netdev_info(netdev, "link up\n");
3699 } else {
3700 netif_carrier_off(netdev);
3701 netif_tx_stop_all_queues(netdev);
3702 netdev_info(netdev, "link down\n");
3703 }
3704}
3705
9df8f79a
YL		 3706static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3707{
3708 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3709 struct net_device *ndev = kinfo->netdev;
075cfdd6 3710 bool if_running;
9df8f79a 3711 int ret;
9df8f79a
YL		 3712
3713 if (tc > HNAE3_MAX_TC)
3714 return -EINVAL;
3715
3716 if (!ndev)
3717 return -ENODEV;
3718
075cfdd6
CIK		 3719 if_running = netif_running(ndev);
3720
9df8f79a
YL		 3721 if (if_running) {
3722 (void)hns3_nic_net_stop(ndev);
3723 msleep(100);
3724 }
3725
3726 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3727 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3728 if (ret)
3729 goto err_out;
3730
9df8f79a
YL		 3731 ret = hns3_nic_set_real_num_queue(ndev);
3732
3733err_out:
3734 if (if_running)
3735 (void)hns3_nic_net_open(ndev);
3736
3737 return ret;
3738}
3739
7fa6be4f 3740static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L		 3741{
3742 struct netdev_hw_addr_list *list;
3743 struct netdev_hw_addr *ha, *tmp;
7fa6be4f 3744 int ret = 0;
bb6b94a8
L		 3745
3746 /* go through and sync uc_addr entries to the device */
3747 list = &ndev->uc;
7fa6be4f
HT		 3748 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3749 ret = hns3_nic_uc_sync(ndev, ha->addr);
3750 if (ret)
3751 return ret;
3752 }
bb6b94a8
L		 3753
3754 /* go through and sync mc_addr entries to the device */
3755 list = &ndev->mc;
7fa6be4f
HT		 3756 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3757 ret = hns3_nic_mc_sync(ndev, ha->addr);
3758 if (ret)
3759 return ret;
3760 }
3761
3762 return ret;
bb6b94a8
L		 3763}
3764
f05e2109
JS		 3765static void hns3_remove_hw_addr(struct net_device *netdev)
3766{
3767 struct netdev_hw_addr_list *list;
3768 struct netdev_hw_addr *ha, *tmp;
3769
3770 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3771
3772 /* go through and unsync uc_addr entries to the device */
3773 list = &netdev->uc;
3774 list_for_each_entry_safe(ha, tmp, &list->list, list)
3775 hns3_nic_uc_unsync(netdev, ha->addr);
3776
3777 /* go through and unsync mc_addr entries to the device */
3778 list = &netdev->mc;
3779 list_for_each_entry_safe(ha, tmp, &list->list, list)
3780 if (ha->refcount > 1)
3781 hns3_nic_mc_unsync(netdev, ha->addr);
3782}
3783
beebca3a 3784static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 3785{
beebca3a 3786 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 3787 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL		 3788 hns3_free_buffer_detach(ring, ring->next_to_clean);
3789 ring_ptr_move_fw(ring, next_to_clean);
3790 }
3791}
3792
7b763f3f
FL		 3793static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3794{
3795 struct hns3_desc_cb res_cbs;
3796 int ret;
3797
3798 while (ring->next_to_use != ring->next_to_clean) {
3799 /* When a buffer is not reused, it's memory has been
3800 * freed in hns3_handle_rx_bd or will be freed by
3801 * stack, so we need to replace the buffer here.
3802 */
3803 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3804 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3805 if (ret) {
3806 u64_stats_update_begin(&ring->syncp);
3807 ring->stats.sw_err_cnt++;
3808 u64_stats_update_end(&ring->syncp);
3809 /* if alloc new buffer fail, exit directly
3810 * and reclear in up flow.
3811 */
3812 netdev_warn(ring->tqp->handle->kinfo.netdev,
3813 "reserve buffer map failed, ret = %d\n",
3814 ret);
3815 return ret;
3816 }
3817 hns3_replace_buffer(ring, ring->next_to_use,
3818 &res_cbs);
3819 }
3820 ring_ptr_move_fw(ring, next_to_use);
3821 }
3822
3823 return 0;
3824}
3825
3826static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 3827{
beebca3a
YL		 3828 while (ring->next_to_use != ring->next_to_clean) {
3829 /* When a buffer is not reused, it's memory has been
3830 * freed in hns3_handle_rx_bd or will be freed by
3831 * stack, so only need to unmap the buffer here.
3832 */
3833 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3834 hns3_unmap_buffer(ring,
3835 &ring->desc_cb[ring->next_to_use]);
3836 ring->desc_cb[ring->next_to_use].dma = 0;
3837 }
3838
3839 ring_ptr_move_fw(ring, next_to_use);
3840 }
bb6b94a8
L		 3841}
3842
7b763f3f
FL		 3843static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3844{
3845 struct net_device *ndev = h->kinfo.netdev;
3846 struct hns3_nic_priv *priv = netdev_priv(ndev);
3847 struct hns3_enet_ring *ring;
3848 u32 i;
3849
3850 for (i = 0; i < h->kinfo.num_tqps; i++) {
3851 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3852 hns3_force_clear_rx_ring(ring);
3853 }
3854}
3855
bb6b94a8
L		 3856static void hns3_clear_all_ring(struct hnae3_handle *h)
3857{
3858 struct net_device *ndev = h->kinfo.netdev;
3859 struct hns3_nic_priv *priv = netdev_priv(ndev);
3860 u32 i;
3861
3862 for (i = 0; i < h->kinfo.num_tqps; i++) {
3863 struct netdev_queue *dev_queue;
3864 struct hns3_enet_ring *ring;
3865
3866 ring = priv->ring_data[i].ring;
beebca3a 3867 hns3_clear_tx_ring(ring);
bb6b94a8
L		 3868 dev_queue = netdev_get_tx_queue(ndev,
3869 priv->ring_data[i].queue_index);
3870 netdev_tx_reset_queue(dev_queue);
3871
3872 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
7b763f3f
FL		 3873 /* Continue to clear other rings even if clearing some
3874 * rings failed.
3875 */
beebca3a 3876 hns3_clear_rx_ring(ring);
bb6b94a8
L		 3877 }
3878}
3879
7b763f3f
FL		 3880int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3881{
3882 struct net_device *ndev = h->kinfo.netdev;
3883 struct hns3_nic_priv *priv = netdev_priv(ndev);
3884 struct hns3_enet_ring *rx_ring;
3885 int i, j;
3886 int ret;
3887
3888 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 3889 ret = h->ae_algo->ops->reset_queue(h, i);
3890 if (ret)
3891 return ret;
3892
7b763f3f
FL		 3893 hns3_init_ring_hw(priv->ring_data[i].ring);
3894
3895 /* We need to clear tx ring here because self test will
3896 * use the ring and will not run down before up
3897 */
3898 hns3_clear_tx_ring(priv->ring_data[i].ring);
3899 priv->ring_data[i].ring->next_to_clean = 0;
3900 priv->ring_data[i].ring->next_to_use = 0;
3901
3902 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3903 hns3_init_ring_hw(rx_ring);
3904 ret = hns3_clear_rx_ring(rx_ring);
3905 if (ret)
3906 return ret;
3907
3908 /* We can not know the hardware head and tail when this
3909 * function is called in reset flow, so we reuse all desc.
3910 */
3911 for (j = 0; j < rx_ring->desc_num; j++)
3912 hns3_reuse_buffer(rx_ring, j);
3913
3914 rx_ring->next_to_clean = 0;
3915 rx_ring->next_to_use = 0;
3916 }
3917
1c772154
YL		 3918 hns3_init_tx_ring_tc(priv);
3919
7b763f3f
FL		 3920 return 0;
3921}
3922
e4fd7502
HT		 3923static void hns3_store_coal(struct hns3_nic_priv *priv)
3924{
3925 /* ethtool only support setting and querying one coal
3926 * configuation for now, so save the vector 0' coal
3927 * configuation here in order to restore it.
3928 */
3929 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
3930 sizeof(struct hns3_enet_coalesce));
3931 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
3932 sizeof(struct hns3_enet_coalesce));
3933}
3934
3935static void hns3_restore_coal(struct hns3_nic_priv *priv)
3936{
3937 u16 vector_num = priv->vector_num;
3938 int i;
3939
3940 for (i = 0; i < vector_num; i++) {
3941 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
3942 sizeof(struct hns3_enet_coalesce));
3943 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
3944 sizeof(struct hns3_enet_coalesce));
3945 }
3946}
3947
bb6b94a8
L		 3948static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3949{
7edff533 3950 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L		 3951 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3952 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 3953 struct hns3_nic_priv *priv = netdev_priv(ndev);
3954
3955 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
3956 return 0;
bb6b94a8 3957
7edff533
HT		 3958 /* it is cumbersome for hardware to pick-and-choose entries for deletion
3959 * from table space. Hence, for function reset software intervention is
3960 * required to delete the entries
3961 */
3962 if (hns3_dev_ongoing_func_reset(ae_dev)) {
3963 hns3_remove_hw_addr(ndev);
3964 hns3_del_all_fd_rules(ndev, false);
3965 }
3966
bb6b94a8 3967 if (!netif_running(ndev))
6b1385cc 3968 return 0;
bb6b94a8
L		 3969
3970 return hns3_nic_net_stop(ndev);
3971}
3972
3973static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3974{
3975 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 3976 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 3977 int ret = 0;
3978
3979 if (netif_running(kinfo->netdev)) {
3980 ret = hns3_nic_net_up(kinfo->netdev);
3981 if (ret) {
3982 netdev_err(kinfo->netdev,
3983 "hns net up fail, ret=%d!\n", ret);
3984 return ret;
3985 }
bb6b94a8
L		 3986 }
3987
257e4f29
HT		 3988 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
3989
bb6b94a8
L		 3990 return ret;
3991}
3992
3993static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
3994{
3995 struct net_device *netdev = handle->kinfo.netdev;
3996 struct hns3_nic_priv *priv = netdev_priv(netdev);
7325523a 3997 bool vlan_filter_enable;
bb6b94a8
L		 3998 int ret;
3999
7fa6be4f
HT		 4000 ret = hns3_init_mac_addr(netdev, false);
4001 if (ret)
4002 return ret;
4003
4004 ret = hns3_recover_hw_addr(netdev);
4005 if (ret)
4006 return ret;
4007
4008 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4009 if (ret)
4010 return ret;
4011
7325523a
JS		 4012 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4013 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4014
681ec399 4015 /* Hardware table is only clear when pf resets */
7fa6be4f
HT		 4016 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4017 ret = hns3_restore_vlan(netdev);
e12c2252
HT		 4018 if (ret)
4019 return ret;
7fa6be4f 4020 }
681ec399 4021
7fa6be4f
HT		 4022 ret = hns3_restore_fd_rules(netdev);
4023 if (ret)
4024 return ret;
6871af29 4025
bb6b94a8
L		 4026 /* Carrier off reporting is important to ethtool even BEFORE open */
4027 netif_carrier_off(netdev);
4028
862d969a
HT		 4029 ret = hns3_nic_alloc_vector_data(priv);
4030 if (ret)
4031 return ret;
4032
e4fd7502
HT		 4033 hns3_restore_coal(priv);
4034
bb6b94a8
L		 4035 ret = hns3_nic_init_vector_data(priv);
4036 if (ret)
862d969a 4037 goto err_dealloc_vector;
bb6b94a8
L		 4038
4039 ret = hns3_init_all_ring(priv);
862d969a
HT		 4040 if (ret)
4041 goto err_uninit_vector;
bb6b94a8 4042
814da63c
HT		 4043 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4044
862d969a
HT		 4045 return ret;
4046
4047err_uninit_vector:
4048 hns3_nic_uninit_vector_data(priv);
4049 priv->ring_data = NULL;
4050err_dealloc_vector:
4051 hns3_nic_dealloc_vector_data(priv);
4052
bb6b94a8
L		 4053 return ret;
4054}
4055
4056static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4057{
4058 struct net_device *netdev = handle->kinfo.netdev;
4059 struct hns3_nic_priv *priv = netdev_priv(netdev);
4060 int ret;
4061
814da63c
HT		 4062 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4063 netdev_warn(netdev, "already uninitialized\n");
4064 return 0;
4065 }
4066
7b763f3f 4067 hns3_force_clear_all_rx_ring(handle);
bb6b94a8
L		 4068
4069 ret = hns3_nic_uninit_vector_data(priv);
4070 if (ret) {
4071 netdev_err(netdev, "uninit vector error\n");
4072 return ret;
4073 }
4074
e4fd7502
HT		 4075 hns3_store_coal(priv);
4076
862d969a
HT		 4077 ret = hns3_nic_dealloc_vector_data(priv);
4078 if (ret)
4079 netdev_err(netdev, "dealloc vector error\n");
4080
bb6b94a8
L		 4081 ret = hns3_uninit_all_ring(priv);
4082 if (ret)
4083 netdev_err(netdev, "uninit ring error\n");
4084
814da63c
HT		 4085 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
4086
bb6b94a8
L		 4087 return ret;
4088}
4089
4090static int hns3_reset_notify(struct hnae3_handle *handle,
4091 enum hnae3_reset_notify_type type)
4092{
4093 int ret = 0;
4094
4095 switch (type) {
4096 case HNAE3_UP_CLIENT:
e1586241
SM		 4097 ret = hns3_reset_notify_up_enet(handle);
4098 break;
bb6b94a8
L		 4099 case HNAE3_DOWN_CLIENT:
4100 ret = hns3_reset_notify_down_enet(handle);
4101 break;
4102 case HNAE3_INIT_CLIENT:
4103 ret = hns3_reset_notify_init_enet(handle);
4104 break;
4105 case HNAE3_UNINIT_CLIENT:
4106 ret = hns3_reset_notify_uninit_enet(handle);
4107 break;
4108 default:
4109 break;
4110 }
4111
4112 return ret;
4113}
4114
e4fd7502 4115static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num)
09f2af64
PL		 4116{
4117 struct hns3_nic_priv *priv = netdev_priv(netdev);
4118 struct hnae3_handle *h = hns3_get_handle(netdev);
4119 int ret;
4120
4121 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
4122 if (ret)
4123 return ret;
4124
4125 ret = hns3_get_ring_config(priv);
4126 if (ret)
4127 return ret;
4128
dd38c726
YL		 4129 ret = hns3_nic_alloc_vector_data(priv);
4130 if (ret)
4131 goto err_alloc_vector;
4132
e4fd7502 4133 hns3_restore_coal(priv);
7a242b23 4134
09f2af64
PL		 4135 ret = hns3_nic_init_vector_data(priv);
4136 if (ret)
4137 goto err_uninit_vector;
4138
4139 ret = hns3_init_all_ring(priv);
4140 if (ret)
4141 goto err_put_ring;
4142
4143 return 0;
4144
4145err_put_ring:
4146 hns3_put_ring_config(priv);
4147err_uninit_vector:
4148 hns3_nic_uninit_vector_data(priv);
dd38c726
YL		 4149err_alloc_vector:
4150 hns3_nic_dealloc_vector_data(priv);
09f2af64
PL		 4151 return ret;
4152}
4153
4154static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
4155{
4156 return (new_tqp_num / num_tc) * num_tc;
4157}
4158
4159int hns3_set_channels(struct net_device *netdev,
4160 struct ethtool_channels *ch)
4161{
4162 struct hns3_nic_priv *priv = netdev_priv(netdev);
4163 struct hnae3_handle *h = hns3_get_handle(netdev);
4164 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4165 bool if_running = netif_running(netdev);
4166 u32 new_tqp_num = ch->combined_count;
4167 u16 org_tqp_num;
4168 int ret;
4169
4170 if (ch->rx_count || ch->tx_count)
4171 return -EINVAL;
4172
678335a1 4173 if (new_tqp_num > hns3_get_max_available_channels(h) ||
09f2af64
PL		 4174 new_tqp_num < kinfo->num_tc) {
4175 dev_err(&netdev->dev,
4176 "Change tqps fail, the tqp range is from %d to %d",
4177 kinfo->num_tc,
678335a1 4178 hns3_get_max_available_channels(h));
09f2af64
PL		 4179 return -EINVAL;
4180 }
4181
4182 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
4183 if (kinfo->num_tqps == new_tqp_num)
4184 return 0;
4185
4186 if (if_running)
20e4bf98 4187 hns3_nic_net_stop(netdev);
09f2af64 4188
09f2af64
PL		 4189 ret = hns3_nic_uninit_vector_data(priv);
4190 if (ret) {
4191 dev_err(&netdev->dev,
4192 "Unbind vector with tqp fail, nothing is changed");
4193 goto open_netdev;
4194 }
4195
e4fd7502 4196 hns3_store_coal(priv);
7a242b23 4197
dd38c726
YL		 4198 hns3_nic_dealloc_vector_data(priv);
4199
09f2af64 4200 hns3_uninit_all_ring(priv);
ec777890 4201 hns3_put_ring_config(priv);
09f2af64
PL		 4202
4203 org_tqp_num = h->kinfo.num_tqps;
e4fd7502 4204 ret = hns3_modify_tqp_num(netdev, new_tqp_num);
09f2af64 4205 if (ret) {
e4fd7502 4206 ret = hns3_modify_tqp_num(netdev, org_tqp_num);
09f2af64
PL		 4207 if (ret) {
4208 /* If revert to old tqp failed, fatal error occurred */
4209 dev_err(&netdev->dev,
4210 "Revert to old tqp num fail, ret=%d", ret);
4211 return ret;
4212 }
4213 dev_info(&netdev->dev,
4214 "Change tqp num fail, Revert to old tqp num");
4215 }
4216
4217open_netdev:
4218 if (if_running)
20e4bf98 4219 hns3_nic_net_open(netdev);
09f2af64
PL		 4220
4221 return ret;
4222}
4223
1db9b1bf 4224static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4225 .init_instance = hns3_client_init,
4226 .uninit_instance = hns3_client_uninit,
4227 .link_status_change = hns3_link_status_change,
9df8f79a 4228 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4229 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 4230};
4231
4232/* hns3_init_module - Driver registration routine
4233 * hns3_init_module is the first routine called when the driver is
4234 * loaded. All it does is register with the PCI subsystem.
4235 */
4236static int __init hns3_init_module(void)
4237{
4238 int ret;
4239
4240 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4241 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4242
4243 client.type = HNAE3_CLIENT_KNIC;
4244 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4245 hns3_driver_name);
4246
4247 client.ops = &client_ops;
4248
13562d1f
XW		 4249 INIT_LIST_HEAD(&client.node);
4250
b2292360 4251 hns3_dbg_register_debugfs(hns3_driver_name);
4252
76ad4f0e
S		 4253 ret = hnae3_register_client(&client);
4254 if (ret)
b2292360 4255 goto err_reg_client;
76ad4f0e
S		 4256
4257 ret = pci_register_driver(&hns3_driver);
4258 if (ret)
b2292360 4259 goto err_reg_driver;
76ad4f0e
S		 4260
4261 return ret;
b2292360 4262
4263err_reg_driver:
4264 hnae3_unregister_client(&client);
4265err_reg_client:
4266 hns3_dbg_unregister_debugfs();
4267 return ret;
76ad4f0e
S		 4268}
4269module_init(hns3_init_module);
4270
4271/* hns3_exit_module - Driver exit cleanup routine
4272 * hns3_exit_module is called just before the driver is removed
4273 * from memory.
4274 */
4275static void __exit hns3_exit_module(void)
4276{
4277 pci_unregister_driver(&hns3_driver);
4278 hnae3_unregister_client(&client);
b2292360 4279 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4280}
4281module_exit(hns3_exit_module);
4282
4283MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4284MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4285MODULE_LICENSE("GPL");
4286MODULE_ALIAS("pci:hns-nic");
3c7624d8 4287MODULE_VERSION(HNS3_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)