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net: hns3: support dma_map_sg() for multi frags skb
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e 10#include <linux/if_vlan.h>
e99a308d 11#include <linux/irq.h>
76ad4f0e
S		 12#include <linux/ip.h>
13#include <linux/ipv6.h>
14#include <linux/module.h>
15#include <linux/pci.h>
6ae4e733 16#include <linux/aer.h>
76ad4f0e
S		 17#include <linux/skbuff.h>
18#include <linux/sctp.h>
76ad4f0e 19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
76ad4f0e 23#include <net/vxlan.h>
a156998f 24#include <net/geneve.h>
76ad4f0e
S		 25
26#include "hnae3.h"
27#include "hns3_enet.h"
698a8954
YL		 28/* All hns3 tracepoints are defined by the include below, which
29 * must be included exactly once across the whole kernel with
30 * CREATE_TRACE_POINTS defined
31 */
32#define CREATE_TRACE_POINTS
33#include "hns3_trace.h"
76ad4f0e 34
9393eb50 35#define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
5f543a54 36#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 37
b20d7fe5
YL		 38#define hns3_rl_err(fmt, ...) \
39 do { \
40 if (net_ratelimit()) \
41 netdev_err(fmt, ##__VA_ARGS__); \
42 } while (0)
43
f96315f2 44static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
7b763f3f 45
1db9b1bf 46static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 47static const char hns3_driver_string[] =
48 "Hisilicon Ethernet Network Driver for Hip08 Family";
49static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
50static struct hnae3_client client;
51
bb87be87
YL		 52static int debug = -1;
53module_param(debug, int, 0);
54MODULE_PARM_DESC(debug, " Network interface message level setting");
55
907676b1
YL		 56static unsigned int tx_spare_buf_size;
57module_param(tx_spare_buf_size, uint, 0400);
58MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer");
59
7459775e
YL		 60static unsigned int tx_sgl = 1;
61module_param(tx_sgl, uint, 0600);
62MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
63
64#define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
65 sizeof(struct sg_table))
66#define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM),\
67 dma_get_cache_alignment())
68
bb87be87
YL		 69#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
70 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
71
eb977d99
YL		 72#define HNS3_INNER_VLAN_TAG 1
73#define HNS3_OUTER_VLAN_TAG 2
74
36c67349
YL		 75#define HNS3_MIN_TX_LEN 33U
76
76ad4f0e
S		 77/* hns3_pci_tbl - PCI Device ID Table
78 *
79 * Last entry must be all 0s
80 *
81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
82 * Class, Class Mask, private data (not used) }
83 */
84static const struct pci_device_id hns3_pci_tbl[] = {
85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 90 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
ae6f010c
GH		 97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
c155e22b
GH		 99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
07acf909 101 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 102 /* required last entry */
103 {0, }
104};
105MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
106
79664077
HT		 107#define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \
108 { ptype, \
109 l, \
110 CHECKSUM_##s, \
111 HNS3_L3_TYPE_##t, \
112 1 }
113
114#define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
115 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 }
116
117static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
118 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
119 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP),
120 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP),
121 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP),
122 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL),
123 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL),
124 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL),
125 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM),
126 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL),
127 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
128 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
129 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
130 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
131 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
134 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL),
135 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4),
136 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4),
137 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4),
138 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4),
139 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4),
140 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4),
141 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4),
142 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4),
143 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4),
144 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
145 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
146 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
147 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL),
148 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL),
149 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4),
150 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4),
151 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4),
152 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4),
153 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4),
154 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4),
155 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4),
156 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
157 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6),
158 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6),
159 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6),
160 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6),
161 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6),
162 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6),
163 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6),
164 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
165 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
166 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
167 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
168 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
229 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6),
230 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6),
231 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6),
232 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6),
233 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6),
234 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6),
235 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6),
236 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6),
237 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6),
238 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
239 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
240 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
241 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL),
242 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL),
243 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4),
244 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4),
245 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4),
246 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4),
247 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4),
248 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4),
249 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4),
250 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
251 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6),
252 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6),
253 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6),
254 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6),
255 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6),
256 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6),
257 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6),
258 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
259 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
260 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
261 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
262 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
374};
375
376#define HNS3_INVALID_PTYPE \
377 ARRAY_SIZE(hns3_rx_ptype_tbl)
378
ef0c5009 379static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 380{
ef0c5009 381 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 382
fb00331b 383 napi_schedule_irqoff(&tqp_vector->napi);
307ea4ce 384 tqp_vector->event_cnt++;
76ad4f0e
S		 385
386 return IRQ_HANDLED;
387}
388
389static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
390{
391 struct hns3_enet_tqp_vector *tqp_vectors;
392 unsigned int i;
393
394 for (i = 0; i < priv->vector_num; i++) {
395 tqp_vectors = &priv->tqp_vector[i];
396
397 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
398 continue;
399
ffab9691 400 /* clear the affinity mask */
874bff0b
PL		 401 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
402
76ad4f0e
S		 403 /* release the irq resource */
404 free_irq(tqp_vectors->vector_irq, tqp_vectors);
405 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
406 }
407}
408
409static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
410{
411 struct hns3_enet_tqp_vector *tqp_vectors;
412 int txrx_int_idx = 0;
413 int rx_int_idx = 0;
414 int tx_int_idx = 0;
415 unsigned int i;
416 int ret;
417
418 for (i = 0; i < priv->vector_num; i++) {
419 tqp_vectors = &priv->tqp_vector[i];
420
421 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
422 continue;
423
424 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
5bffde62
YL		 425 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
426 "%s-%s-%s-%d", hns3_driver_name,
427 pci_name(priv->ae_handle->pdev),
428 "TxRx", txrx_int_idx++);
76ad4f0e
S		 429 txrx_int_idx++;
430 } else if (tqp_vectors->rx_group.ring) {
5bffde62
YL		 431 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
432 "%s-%s-%s-%d", hns3_driver_name,
433 pci_name(priv->ae_handle->pdev),
434 "Rx", rx_int_idx++);
76ad4f0e 435 } else if (tqp_vectors->tx_group.ring) {
5bffde62
YL		 436 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
437 "%s-%s-%s-%d", hns3_driver_name,
438 pci_name(priv->ae_handle->pdev),
439 "Tx", tx_int_idx++);
76ad4f0e
S		 440 } else {
441 /* Skip this unused q_vector */
442 continue;
443 }
444
445 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
446
e99a308d 447 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
76ad4f0e 448 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 449 tqp_vectors->name, tqp_vectors);
76ad4f0e
S		 450 if (ret) {
451 netdev_err(priv->netdev, "request irq(%d) fail\n",
452 tqp_vectors->vector_irq);
d547ecdc 453 hns3_nic_uninit_irq(priv);
76ad4f0e
S		 454 return ret;
455 }
456
874bff0b
PL		 457 irq_set_affinity_hint(tqp_vectors->vector_irq,
458 &tqp_vectors->affinity_mask);
459
76ad4f0e
S		 460 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
461 }
462
463 return 0;
464}
465
466static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
467 u32 mask_en)
468{
469 writel(mask_en, tqp_vector->mask_addr);
470}
471
472static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
473{
474 napi_enable(&tqp_vector->napi);
08a10068 475 enable_irq(tqp_vector->vector_irq);
76ad4f0e
S		 476
477 /* enable vector */
478 hns3_mask_vector_irq(tqp_vector, 1);
479}
480
481static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
482{
483 /* disable vector */
484 hns3_mask_vector_irq(tqp_vector, 0);
485
486 disable_irq(tqp_vector->vector_irq);
487 napi_disable(&tqp_vector->napi);
307ea4ce
HT		 488 cancel_work_sync(&tqp_vector->rx_group.dim.work);
489 cancel_work_sync(&tqp_vector->tx_group.dim.work);
76ad4f0e
S		 490}
491
434776a5
FL		 492void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
493 u32 rl_value)
76ad4f0e 494{
434776a5
FL		 495 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
496
76ad4f0e
S		 497 /* this defines the configuration for RL (Interrupt Rate Limiter).
498 * Rl defines rate of interrupts i.e. number of interrupts-per-second
499 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
500 */
de25bcc4
HT		 501 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
502 !tqp_vector->rx_group.coal.adapt_enable)
434776a5
FL		 503 /* According to the hardware, the range of rl_reg is
504 * 0-59 and the unit is 4.
505 */
506 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
507
508 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
509}
510
511void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
512 u32 gl_value)
513{
5ac84b02 514 u32 new_val;
434776a5 515
5ac84b02
HT		 516 if (tqp_vector->rx_group.coal.unit_1us)
517 new_val = gl_value | HNS3_INT_GL_1US;
518 else
519 new_val = hns3_gl_usec_to_reg(gl_value);
520
521 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
434776a5
FL		 522}
523
524void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
525 u32 gl_value)
526{
5ac84b02
HT		 527 u32 new_val;
528
529 if (tqp_vector->tx_group.coal.unit_1us)
530 new_val = gl_value | HNS3_INT_GL_1US;
531 else
532 new_val = hns3_gl_usec_to_reg(gl_value);
434776a5 533
5ac84b02 534 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 535}
536
91bfae25
HT		 537void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
538 u32 ql_value)
76ad4f0e 539{
91bfae25
HT		 540 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
541}
542
543void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
544 u32 ql_value)
545{
546 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
547}
548
549static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
550 struct hns3_nic_priv *priv)
551{
552 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
553 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
554 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
73a13d8d
HT		 555 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
556 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
91bfae25 557
73a13d8d
HT		 558 tx_coal->adapt_enable = ptx_coal->adapt_enable;
559 rx_coal->adapt_enable = prx_coal->adapt_enable;
91bfae25 560
73a13d8d
HT		 561 tx_coal->int_gl = ptx_coal->int_gl;
562 rx_coal->int_gl = prx_coal->int_gl;
5fd4789a 563
73a13d8d
HT		 564 rx_coal->flow_level = prx_coal->flow_level;
565 tx_coal->flow_level = ptx_coal->flow_level;
5fd4789a 566
5ac84b02
HT		 567 /* device version above V3(include V3), GL can configure 1us
568 * unit, so uses 1us unit.
569 */
570 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
571 tx_coal->unit_1us = 1;
572 rx_coal->unit_1us = 1;
573 }
574
91bfae25
HT		 575 if (ae_dev->dev_specs.int_ql_max) {
576 tx_coal->ql_enable = 1;
577 rx_coal->ql_enable = 1;
578 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
579 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
73a13d8d
HT		 580 tx_coal->int_ql = ptx_coal->int_ql;
581 rx_coal->int_ql = prx_coal->int_ql;
91bfae25 582 }
76ad4f0e
S		 583}
584
91bfae25
HT		 585static void
586hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
587 struct hns3_nic_priv *priv)
dd38c726 588{
91bfae25
HT		 589 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
590 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
dd38c726
YL		 591 struct hnae3_handle *h = priv->ae_handle;
592
91bfae25
HT		 593 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
594 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
dd38c726 595 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
91bfae25
HT		 596
597 if (tx_coal->ql_enable)
598 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
599
600 if (rx_coal->ql_enable)
601 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
dd38c726
YL		 602}
603
9df8f79a
YL		 604static int hns3_nic_set_real_num_queue(struct net_device *netdev)
605{
9780cb97 606 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a 607 struct hnae3_knic_private_info *kinfo = &h->kinfo;
35244430 608 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5a5c9091 609 unsigned int queue_size = kinfo->num_tqps;
a75a8efa
YL		 610 int i, ret;
611
5a5c9091 612 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
a75a8efa
YL		 613 netdev_reset_tc(netdev);
614 } else {
35244430 615 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
a75a8efa
YL		 616 if (ret) {
617 netdev_err(netdev,
618 "netdev_set_num_tc fail, ret=%d!\n", ret);
619 return ret;
620 }
621
622 for (i = 0; i < HNAE3_MAX_TC; i++) {
35244430 623 if (!test_bit(i, &tc_info->tc_en))
a75a8efa
YL		 624 continue;
625
35244430
JS		 626 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
627 tc_info->tqp_offset[i]);
a75a8efa
YL		 628 }
629 }
9df8f79a
YL		 630
631 ret = netif_set_real_num_tx_queues(netdev, queue_size);
632 if (ret) {
633 netdev_err(netdev,
9b2f3477 634 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL		 635 return ret;
636 }
637
638 ret = netif_set_real_num_rx_queues(netdev, queue_size);
639 if (ret) {
640 netdev_err(netdev,
641 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
642 return ret;
643 }
644
645 return 0;
646}
647
77e91848 648u16 hns3_get_max_available_channels(struct hnae3_handle *h)
678335a1 649{
0d43bf45 650 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 651
0d43bf45 652 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
35244430 653 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
678335a1 654
0d43bf45 655 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 656}
657
8df0fa91
HT		 658static void hns3_tqp_enable(struct hnae3_queue *tqp)
659{
660 u32 rcb_reg;
661
662 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
663 rcb_reg |= BIT(HNS3_RING_EN_B);
664 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
665}
666
667static void hns3_tqp_disable(struct hnae3_queue *tqp)
668{
669 u32 rcb_reg;
670
671 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
672 rcb_reg &= ~BIT(HNS3_RING_EN_B);
673 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
674}
675
ffab9691
JS		 676static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
677{
678#ifdef CONFIG_RFS_ACCEL
679 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
680 netdev->rx_cpu_rmap = NULL;
681#endif
682}
683
684static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
685{
686#ifdef CONFIG_RFS_ACCEL
687 struct hns3_nic_priv *priv = netdev_priv(netdev);
688 struct hns3_enet_tqp_vector *tqp_vector;
689 int i, ret;
690
691 if (!netdev->rx_cpu_rmap) {
692 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
693 if (!netdev->rx_cpu_rmap)
694 return -ENOMEM;
695 }
696
697 for (i = 0; i < priv->vector_num; i++) {
698 tqp_vector = &priv->tqp_vector[i];
699 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
700 tqp_vector->vector_irq);
701 if (ret) {
702 hns3_free_rx_cpu_rmap(netdev);
703 return ret;
704 }
705 }
706#endif
707 return 0;
708}
709
76ad4f0e
S		 710static int hns3_nic_net_up(struct net_device *netdev)
711{
712 struct hns3_nic_priv *priv = netdev_priv(netdev);
713 struct hnae3_handle *h = priv->ae_handle;
714 int i, j;
715 int ret;
716
7b763f3f
FL		 717 ret = hns3_nic_reset_all_ring(h);
718 if (ret)
719 return ret;
720
b7b585c2
JS		 721 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
722
76ad4f0e
S		 723 /* enable the vectors */
724 for (i = 0; i < priv->vector_num; i++)
725 hns3_vector_enable(&priv->tqp_vector[i]);
726
8df0fa91
HT		 727 /* enable rcb */
728 for (j = 0; j < h->kinfo.num_tqps; j++)
729 hns3_tqp_enable(h->kinfo.tqp[j]);
730
76ad4f0e
S		 731 /* start the ae_dev */
732 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
08a10068
YL		 733 if (ret) {
734 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
735 while (j--)
736 hns3_tqp_disable(h->kinfo.tqp[j]);
8df0fa91 737
08a10068
YL		 738 for (j = i - 1; j >= 0; j--)
739 hns3_vector_disable(&priv->tqp_vector[j]);
740 }
76ad4f0e 741
76ad4f0e
S		 742 return ret;
743}
744
2a73ac3e
YL		 745static void hns3_config_xps(struct hns3_nic_priv *priv)
746{
747 int i;
748
749 for (i = 0; i < priv->vector_num; i++) {
750 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
751 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
752
753 while (ring) {
754 int ret;
755
756 ret = netif_set_xps_queue(priv->netdev,
757 &tqp_vector->affinity_mask,
758 ring->tqp->tqp_index);
759 if (ret)
760 netdev_warn(priv->netdev,
761 "set xps queue failed: %d", ret);
762
763 ring = ring->next;
764 }
765 }
766}
767
76ad4f0e
S		 768static int hns3_nic_net_open(struct net_device *netdev)
769{
8cdb992f 770 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 771 struct hnae3_handle *h = hns3_get_handle(netdev);
772 struct hnae3_knic_private_info *kinfo;
773 int i, ret;
76ad4f0e 774
257e4f29
HT		 775 if (hns3_nic_resetting(netdev))
776 return -EBUSY;
777
76ad4f0e
S		 778 netif_carrier_off(netdev);
779
9df8f79a
YL		 780 ret = hns3_nic_set_real_num_queue(netdev);
781 if (ret)
76ad4f0e 782 return ret;
76ad4f0e
S		 783
784 ret = hns3_nic_net_up(netdev);
785 if (ret) {
9b2f3477 786 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S		 787 return ret;
788 }
789
a75a8efa 790 kinfo = &h->kinfo;
9b2f3477 791 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
35244430 792 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
a75a8efa 793
8cdb992f
JS		 794 if (h->ae_algo->ops->set_timer_task)
795 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
796
2a73ac3e 797 hns3_config_xps(priv);
1c822948
YL		 798
799 netif_dbg(h, drv, netdev, "net open\n");
800
76ad4f0e
S		 801 return 0;
802}
803
f96315f2
HT		 804static void hns3_reset_tx_queue(struct hnae3_handle *h)
805{
806 struct net_device *ndev = h->kinfo.netdev;
807 struct hns3_nic_priv *priv = netdev_priv(ndev);
808 struct netdev_queue *dev_queue;
809 u32 i;
810
811 for (i = 0; i < h->kinfo.num_tqps; i++) {
812 dev_queue = netdev_get_tx_queue(ndev,
5f06b903 813 priv->ring[i].queue_index);
f96315f2
HT		 814 netdev_tx_reset_queue(dev_queue);
815 }
816}
817
76ad4f0e
S		 818static void hns3_nic_net_down(struct net_device *netdev)
819{
820 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 821 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 822 const struct hnae3_ae_ops *ops;
823 int i;
824
7b763f3f
FL		 825 /* disable vectors */
826 for (i = 0; i < priv->vector_num; i++)
827 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 828
829 /* disable rcb */
830 for (i = 0; i < h->kinfo.num_tqps; i++)
831 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 832
76ad4f0e
S		 833 /* stop ae_dev */
834 ops = priv->ae_handle->ae_algo->ops;
835 if (ops->stop)
836 ops->stop(priv->ae_handle);
837
3a30964a
YL		 838 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
839 * during reset process, because driver may not be able
840 * to disable the ring through firmware when downing the netdev.
841 */
842 if (!hns3_nic_resetting(netdev))
f96315f2
HT		 843 hns3_clear_all_ring(priv->ae_handle, false);
844
845 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S		 846}
847
848static int hns3_nic_net_stop(struct net_device *netdev)
849{
ff0699e0 850 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 851 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 852
853 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
854 return 0;
855
1c822948
YL		 856 netif_dbg(h, drv, netdev, "net stop\n");
857
8cdb992f
JS		 858 if (h->ae_algo->ops->set_timer_task)
859 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
860
76ad4f0e 861 netif_carrier_off(netdev);
b416e872 862 netif_tx_disable(netdev);
76ad4f0e
S		 863
864 hns3_nic_net_down(netdev);
865
866 return 0;
867}
868
76ad4f0e
S		 869static int hns3_nic_uc_sync(struct net_device *netdev,
870 const unsigned char *addr)
871{
9780cb97 872 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 873
874 if (h->ae_algo->ops->add_uc_addr)
875 return h->ae_algo->ops->add_uc_addr(h, addr);
876
877 return 0;
878}
879
880static int hns3_nic_uc_unsync(struct net_device *netdev,
881 const unsigned char *addr)
882{
9780cb97 883 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 884
ee4bcd3b
JS		 885 /* need ignore the request of removing device address, because
886 * we store the device address and other addresses of uc list
887 * in the function's mac filter list.
888 */
889 if (ether_addr_equal(addr, netdev->dev_addr))
890 return 0;
891
76ad4f0e
S		 892 if (h->ae_algo->ops->rm_uc_addr)
893 return h->ae_algo->ops->rm_uc_addr(h, addr);
894
895 return 0;
896}
897
898static int hns3_nic_mc_sync(struct net_device *netdev,
899 const unsigned char *addr)
900{
9780cb97 901 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 902
720a8478 903 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 904 return h->ae_algo->ops->add_mc_addr(h, addr);
905
906 return 0;
907}
908
909static int hns3_nic_mc_unsync(struct net_device *netdev,
910 const unsigned char *addr)
911{
9780cb97 912 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 913
720a8478 914 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 915 return h->ae_algo->ops->rm_mc_addr(h, addr);
916
917 return 0;
918}
919
c60edc17
JS		 920static u8 hns3_get_netdev_flags(struct net_device *netdev)
921{
922 u8 flags = 0;
923
2ba30662 924 if (netdev->flags & IFF_PROMISC)
28673b33 925 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
2ba30662
JS		 926 else if (netdev->flags & IFF_ALLMULTI)
927 flags = HNAE3_USER_MPE;
c60edc17
JS		 928
929 return flags;
930}
931
1db9b1bf 932static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 933{
9780cb97 934 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17 935 u8 new_flags;
76ad4f0e 936
c60edc17
JS		 937 new_flags = hns3_get_netdev_flags(netdev);
938
c631c696
JS		 939 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
940 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
c60edc17 941
c60edc17 942 /* User mode Promisc mode enable and vlan filtering is disabled to
c631c696 943 * let all packets in.
c60edc17 944 */
c60edc17 945 h->netdev_flags = new_flags;
c631c696
JS		 946 hns3_request_update_promisc_mode(h);
947}
948
949void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
950{
951 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
952
953 if (ops->request_update_promisc_mode)
954 ops->request_update_promisc_mode(handle);
c60edc17
JS		 955}
956
907676b1
YL		 957static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
958{
959 struct hns3_tx_spare *tx_spare = ring->tx_spare;
960 u32 ntc, ntu;
961
962 /* This smp_load_acquire() pairs with smp_store_release() in
963 * hns3_tx_spare_update() called in tx desc cleaning process.
964 */
965 ntc = smp_load_acquire(&tx_spare->last_to_clean);
966 ntu = tx_spare->next_to_use;
967
968 if (ntc > ntu)
969 return ntc - ntu - 1;
970
971 /* The free tx buffer is divided into two part, so pick the
972 * larger one.
973 */
974 return (ntc > (tx_spare->len - ntu) ? ntc :
975 (tx_spare->len - ntu)) - 1;
976}
977
978static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
979{
980 struct hns3_tx_spare *tx_spare = ring->tx_spare;
981
982 if (!tx_spare ||
983 tx_spare->last_to_clean == tx_spare->next_to_clean)
984 return;
985
986 /* This smp_store_release() pairs with smp_load_acquire() in
987 * hns3_tx_spare_space() called in xmit process.
988 */
989 smp_store_release(&tx_spare->last_to_clean,
990 tx_spare->next_to_clean);
991}
992
993static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
994 struct sk_buff *skb,
995 u32 space)
996{
997 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
998 skb_headlen(skb);
999
1000 if (len > ring->tx_copybreak)
1001 return false;
1002
1003 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1004 u64_stats_update_begin(&ring->syncp);
1005 ring->stats.tx_spare_full++;
1006 u64_stats_update_end(&ring->syncp);
1007 return false;
1008 }
1009
1010 return true;
1011}
1012
7459775e
YL		 1013static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1014 struct sk_buff *skb,
1015 u32 space)
1016{
1017 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1018 (!skb_has_frag_list(skb) &&
1019 skb_shinfo(skb)->nr_frags < tx_sgl))
1020 return false;
1021
1022 if (space < HNS3_MAX_SGL_SIZE) {
1023 u64_stats_update_begin(&ring->syncp);
1024 ring->stats.tx_spare_full++;
1025 u64_stats_update_end(&ring->syncp);
1026 return false;
1027 }
1028
1029 return true;
1030}
1031
907676b1
YL		 1032static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1033{
1034 struct hns3_tx_spare *tx_spare;
1035 struct page *page;
1a00197b 1036 u32 alloc_size;
907676b1
YL		 1037 dma_addr_t dma;
1038 int order;
1039
1a00197b
HT		 1040 alloc_size = tx_spare_buf_size ? tx_spare_buf_size :
1041 ring->tqp->handle->kinfo.tx_spare_buf_size;
1042 if (!alloc_size)
907676b1
YL		 1043 return;
1044
1a00197b 1045 order = get_order(alloc_size);
907676b1
YL		 1046 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1047 GFP_KERNEL);
1048 if (!tx_spare) {
1049 /* The driver still work without the tx spare buffer */
1050 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1051 return;
1052 }
1053
1054 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1055 GFP_KERNEL, order);
1056 if (!page) {
1057 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1058 devm_kfree(ring_to_dev(ring), tx_spare);
1059 return;
1060 }
1061
1062 dma = dma_map_page(ring_to_dev(ring), page, 0,
1063 PAGE_SIZE << order, DMA_TO_DEVICE);
1064 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1065 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1066 put_page(page);
1067 devm_kfree(ring_to_dev(ring), tx_spare);
1068 return;
1069 }
1070
1071 tx_spare->dma = dma;
1072 tx_spare->buf = page_address(page);
1073 tx_spare->len = PAGE_SIZE << order;
1074 ring->tx_spare = tx_spare;
1075}
1076
1077/* Use hns3_tx_spare_space() to make sure there is enough buffer
1078 * before calling below function to allocate tx buffer.
1079 */
1080static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1081 unsigned int size, dma_addr_t *dma,
1082 u32 *cb_len)
1083{
1084 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1085 u32 ntu = tx_spare->next_to_use;
1086
1087 size = ALIGN(size, dma_get_cache_alignment());
1088 *cb_len = size;
1089
1090 /* Tx spare buffer wraps back here because the end of
1091 * freed tx buffer is not enough.
1092 */
1093 if (ntu + size > tx_spare->len) {
1094 *cb_len += (tx_spare->len - ntu);
1095 ntu = 0;
1096 }
1097
1098 tx_spare->next_to_use = ntu + size;
1099 if (tx_spare->next_to_use == tx_spare->len)
1100 tx_spare->next_to_use = 0;
1101
1102 *dma = tx_spare->dma + ntu;
1103
1104 return tx_spare->buf + ntu;
1105}
1106
1107static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1108{
1109 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1110
1111 if (len > tx_spare->next_to_use) {
1112 len -= tx_spare->next_to_use;
1113 tx_spare->next_to_use = tx_spare->len - len;
1114 } else {
1115 tx_spare->next_to_use -= len;
1116 }
1117}
1118
1119static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1120 struct hns3_desc_cb *cb)
1121{
1122 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1123 u32 ntc = tx_spare->next_to_clean;
1124 u32 len = cb->length;
1125
1126 tx_spare->next_to_clean += len;
1127
1128 if (tx_spare->next_to_clean >= tx_spare->len) {
1129 tx_spare->next_to_clean -= tx_spare->len;
1130
1131 if (tx_spare->next_to_clean) {
1132 ntc = 0;
1133 len = tx_spare->next_to_clean;
1134 }
1135 }
1136
1137 /* This tx spare buffer is only really reclaimed after calling
1138 * hns3_tx_spare_update(), so it is still safe to use the info in
7459775e
YL		 1139 * the tx buffer to do the dma sync or sg unmapping after
1140 * tx_spare->next_to_clean is moved forword.
907676b1
YL		 1141 */
1142 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1143 dma_addr_t dma = tx_spare->dma + ntc;
1144
1145 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1146 DMA_TO_DEVICE);
7459775e
YL		 1147 } else {
1148 struct sg_table *sgt = tx_spare->buf + ntc;
1149
1150 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1151 DMA_TO_DEVICE);
907676b1
YL		 1152 }
1153}
1154
3e281621 1155static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
811c0830 1156 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
76ad4f0e
S		 1157{
1158 u32 l4_offset, hdr_len;
1159 union l3_hdr_info l3;
1160 union l4_hdr_info l4;
1161 u32 l4_paylen;
1162 int ret;
1163
1164 if (!skb_is_gso(skb))
1165 return 0;
1166
1167 ret = skb_cow_head(skb, 0);
8ae10cfb 1168 if (unlikely(ret < 0))
76ad4f0e
S		 1169 return ret;
1170
1171 l3.hdr = skb_network_header(skb);
1172 l4.hdr = skb_transport_header(skb);
1173
1174 /* Software should clear the IPv4's checksum field when tso is
1175 * needed.
1176 */
1177 if (l3.v4->version == 4)
1178 l3.v4->check = 0;
1179
9b2f3477 1180 /* tunnel packet */
76ad4f0e
S		 1181 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1182 SKB_GSO_GRE_CSUM |
3e281621
HT		 1183 SKB_GSO_UDP_TUNNEL |
1184 SKB_GSO_UDP_TUNNEL_CSUM)) {
76ad4f0e
S		 1185 /* reset l3&l4 pointers from outer to inner headers */
1186 l3.hdr = skb_inner_network_header(skb);
1187 l4.hdr = skb_inner_transport_header(skb);
1188
1189 /* Software should clear the IPv4's checksum field when
1190 * tso is needed.
1191 */
1192 if (l3.v4->version == 4)
1193 l3.v4->check = 0;
1194 }
1195
9b2f3477 1196 /* normal or tunnel packet */
76ad4f0e 1197 l4_offset = l4.hdr - skb->data;
76ad4f0e 1198
9b2f3477 1199 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e 1200 l4_paylen = skb->len - l4_offset;
0692cfe9
HT		 1201
1202 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1203 hdr_len = sizeof(*l4.udp) + l4_offset;
1204 csum_replace_by_diff(&l4.udp->check,
1205 (__force __wsum)htonl(l4_paylen));
1206 } else {
1207 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1208 csum_replace_by_diff(&l4.tcp->check,
1209 (__force __wsum)htonl(l4_paylen));
1210 }
76ad4f0e 1211
811c0830
YL		 1212 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1213
76ad4f0e 1214 /* find the txbd field values */
3e281621 1215 *paylen_fdop_ol4cs = skb->len - hdr_len;
cde4ffad 1216 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e 1217
3e281621
HT		 1218 /* offload outer UDP header checksum */
1219 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1220 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1221
76ad4f0e
S		 1222 /* get MSS for TSO */
1223 *mss = skb_shinfo(skb)->gso_size;
1224
698a8954
YL		 1225 trace_hns3_tso(skb);
1226
76ad4f0e
S		 1227 return 0;
1228}
1229
1898d4e4
S		 1230static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1231 u8 *il4_proto)
76ad4f0e 1232{
1a6e552d 1233 union l3_hdr_info l3;
76ad4f0e
S		 1234 unsigned char *l4_hdr;
1235 unsigned char *exthdr;
1236 u8 l4_proto_tmp;
1237 __be16 frag_off;
1238
1239 /* find outer header point */
1240 l3.hdr = skb_network_header(skb);
35f58fd7 1241 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 1242
1243 if (skb->protocol == htons(ETH_P_IPV6)) {
1244 exthdr = l3.hdr + sizeof(*l3.v6);
1245 l4_proto_tmp = l3.v6->nexthdr;
1246 if (l4_hdr != exthdr)
1247 ipv6_skip_exthdr(skb, exthdr - skb->data,
1248 &l4_proto_tmp, &frag_off);
1249 } else if (skb->protocol == htons(ETH_P_IP)) {
1250 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 1251 } else {
1252 return -EINVAL;
76ad4f0e
S		 1253 }
1254
1255 *ol4_proto = l4_proto_tmp;
1256
1257 /* tunnel packet */
1258 if (!skb->encapsulation) {
1259 *il4_proto = 0;
1898d4e4 1260 return 0;
76ad4f0e
S		 1261 }
1262
1263 /* find inner header point */
1264 l3.hdr = skb_inner_network_header(skb);
1265 l4_hdr = skb_inner_transport_header(skb);
1266
1267 if (l3.v6->version == 6) {
1268 exthdr = l3.hdr + sizeof(*l3.v6);
1269 l4_proto_tmp = l3.v6->nexthdr;
1270 if (l4_hdr != exthdr)
1271 ipv6_skip_exthdr(skb, exthdr - skb->data,
1272 &l4_proto_tmp, &frag_off);
1273 } else if (l3.v4->version == 4) {
1274 l4_proto_tmp = l3.v4->protocol;
1275 }
1276
1277 *il4_proto = l4_proto_tmp;
1898d4e4
S		 1278
1279 return 0;
76ad4f0e
S		 1280}
1281
3db084d2
YL		 1282/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1283 * and it is udp packet, which has a dest port as the IANA assigned.
1284 * the hardware is expected to do the checksum offload, but the
1285 * hardware will not do the checksum offload when udp dest port is
905416f1 1286 * 4789, 4790 or 6081.
3db084d2
YL		 1287 */
1288static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1289{
ade36cce
HT		 1290 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1291 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1a6e552d 1292 union l4_hdr_info l4;
3db084d2 1293
ade36cce
HT		 1294 /* device version above V3(include V3), the hardware can
1295 * do this checksum offload.
1296 */
1297 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1298 return false;
1299
3db084d2
YL		 1300 l4.hdr = skb_transport_header(skb);
1301
bea96410 1302 if (!(!skb->encapsulation &&
a156998f 1303 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
905416f1
HC		 1304 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1305 l4.udp->dest == htons(4790))))
3db084d2
YL		 1306 return false;
1307
3db084d2
YL		 1308 return true;
1309}
1310
757cd1e4
YL		 1311static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1312 u32 *ol_type_vlan_len_msec)
76ad4f0e 1313{
757cd1e4
YL		 1314 u32 l2_len, l3_len, l4_len;
1315 unsigned char *il2_hdr;
1a6e552d 1316 union l3_hdr_info l3;
757cd1e4 1317 union l4_hdr_info l4;
76ad4f0e
S		 1318
1319 l3.hdr = skb_network_header(skb);
757cd1e4 1320 l4.hdr = skb_transport_header(skb);
76ad4f0e 1321
757cd1e4
YL		 1322 /* compute OL2 header size, defined in 2 Bytes */
1323 l2_len = l3.hdr - skb->data;
1324 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1325
1326 /* compute OL3 header size, defined in 4 Bytes */
1327 l3_len = l4.hdr - l3.hdr;
1328 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 1329
757cd1e4 1330 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 1331 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL		 1332 l4_len = il2_hdr - l4.hdr;
1333 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1334
1335 /* define outer network header type */
1336 if (skb->protocol == htons(ETH_P_IP)) {
1337 if (skb_is_gso(skb))
cde4ffad 1338 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 1339 HNS3_TXD_OL3T_S,
1340 HNS3_OL3T_IPV4_CSUM);
1341 else
cde4ffad 1342 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 1343 HNS3_TXD_OL3T_S,
1344 HNS3_OL3T_IPV4_NO_CSUM);
757cd1e4
YL		 1345 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1346 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1347 HNS3_OL3T_IPV6);
1348 }
1349
1350 if (ol4_proto == IPPROTO_UDP)
1351 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1352 HNS3_TUN_MAC_IN_UDP);
1353 else if (ol4_proto == IPPROTO_GRE)
1354 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1355 HNS3_TUN_NVGRE);
1356}
1357
1358static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1359 u8 il4_proto, u32 *type_cs_vlan_tso,
1360 u32 *ol_type_vlan_len_msec)
1361{
c264ed44 1362 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 1363 u32 l4_proto = ol4_proto;
1364 union l4_hdr_info l4;
1365 union l3_hdr_info l3;
1366 u32 l2_len, l3_len;
1367
1368 l4.hdr = skb_transport_header(skb);
1369 l3.hdr = skb_network_header(skb);
1370
1371 /* handle encapsulation skb */
1372 if (skb->encapsulation) {
1373 /* If this is a not UDP/GRE encapsulation skb */
1374 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 1375 /* drop the skb tunnel packet if hardware don't support,
1376 * because hardware can't calculate csum when TSO.
1377 */
1378 if (skb_is_gso(skb))
1379 return -EDOM;
1380
1381 /* the stack computes the IP header already,
1382 * driver calculate l4 checksum when not TSO.
1383 */
9bb5a495 1384 return skb_checksum_help(skb);
76ad4f0e
S		 1385 }
1386
757cd1e4
YL		 1387 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1388
1389 /* switch to inner header */
1390 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 1391 l3.hdr = skb_inner_network_header(skb);
757cd1e4 1392 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 1393 l4_proto = il4_proto;
1394 }
1395
1396 if (l3.v4->version == 4) {
cde4ffad
YL		 1397 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1398 HNS3_L3T_IPV4);
76ad4f0e
S		 1399
1400 /* the stack computes the IP header already, the only time we
1401 * need the hardware to recompute it is in the case of TSO.
1402 */
1403 if (skb_is_gso(skb))
cde4ffad 1404 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 1405 } else if (l3.v6->version == 6) {
cde4ffad
YL		 1406 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1407 HNS3_L3T_IPV6);
76ad4f0e
S		 1408 }
1409
757cd1e4
YL		 1410 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1411 l2_len = l3.hdr - l2_hdr;
1412 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1413
1414 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1415 l3_len = l4.hdr - l3.hdr;
1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1417
1418 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 1419 switch (l4_proto) {
1420 case IPPROTO_TCP:
cde4ffad
YL		 1421 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1422 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1423 HNS3_L4T_TCP);
757cd1e4
YL		 1424 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1425 l4.tcp->doff);
76ad4f0e
S		 1426 break;
1427 case IPPROTO_UDP:
3db084d2 1428 if (hns3_tunnel_csum_bug(skb))
9bb5a495 1429 return skb_checksum_help(skb);
3db084d2 1430
cde4ffad
YL		 1431 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1432 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1433 HNS3_L4T_UDP);
757cd1e4
YL		 1434 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1435 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 1436 break;
1437 case IPPROTO_SCTP:
cde4ffad
YL		 1438 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1439 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1440 HNS3_L4T_SCTP);
757cd1e4
YL		 1441 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1442 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 1443 break;
1444 default:
1445 /* drop the skb tunnel packet if hardware don't support,
1446 * because hardware can't calculate csum when TSO.
1447 */
1448 if (skb_is_gso(skb))
1449 return -EDOM;
1450
1451 /* the stack computes the IP header already,
1452 * driver calculate l4 checksum when not TSO.
1453 */
9bb5a495 1454 return skb_checksum_help(skb);
76ad4f0e
S		 1455 }
1456
1457 return 0;
1458}
1459
eb977d99
YL		 1460static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1461 struct sk_buff *skb)
9699cffe 1462{
44e626f7 1463 struct hnae3_handle *handle = tx_ring->tqp->handle;
592b0179 1464 struct hnae3_ae_dev *ae_dev;
eb977d99
YL		 1465 struct vlan_ethhdr *vhdr;
1466 int rc;
1467
1468 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1469 skb_vlan_tag_present(skb)))
1470 return 0;
44e626f7 1471
592b0179
GL		 1472 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1473 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1474 * will cause RAS error.
44e626f7 1475 */
592b0179 1476 ae_dev = pci_get_drvdata(handle->pdev);
44e626f7 1477 if (unlikely(skb_vlan_tagged_multi(skb) &&
592b0179 1478 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
44e626f7
JS		 1479 handle->port_base_vlan_state ==
1480 HNAE3_PORT_BASE_VLAN_ENABLE))
1481 return -EINVAL;
1482
9699cffe 1483 if (skb->protocol == htons(ETH_P_8021Q) &&
eb977d99 1484 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
9699cffe
PL		 1485 /* When HW VLAN acceleration is turned off, and the stack
1486 * sets the protocol to 802.1q, the driver just need to
1487 * set the protocol to the encapsulated ethertype.
1488 */
1489 skb->protocol = vlan_get_protocol(skb);
1490 return 0;
1491 }
1492
1493 if (skb_vlan_tag_present(skb)) {
9699cffe
PL		 1494 /* Based on hw strategy, use out_vtag in two layer tag case,
1495 * and use inner_vtag in one tag case.
1496 */
eb977d99
YL		 1497 if (skb->protocol == htons(ETH_P_8021Q) &&
1498 handle->port_base_vlan_state ==
1499 HNAE3_PORT_BASE_VLAN_DISABLE)
1500 rc = HNS3_OUTER_VLAN_TAG;
1501 else
1502 rc = HNS3_INNER_VLAN_TAG;
1503
1504 skb->protocol = vlan_get_protocol(skb);
1505 return rc;
9699cffe
PL		 1506 }
1507
eb977d99
YL		 1508 rc = skb_cow_head(skb, 0);
1509 if (unlikely(rc < 0))
1510 return rc;
1511
1512 vhdr = (struct vlan_ethhdr *)skb->data;
1513 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1514 & VLAN_PRIO_MASK);
1515
9699cffe
PL		 1516 skb->protocol = vlan_get_protocol(skb);
1517 return 0;
1518}
1519
66d52f3b
HT		 1520/* check if the hardware is capable of checksum offloading */
1521static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1522{
1523 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1524
1525 /* Kindly note, due to backward compatibility of the TX descriptor,
1526 * HW checksum of the non-IP packets and GSO packets is handled at
1527 * different place in the following code
1528 */
b9046e88 1529 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
66d52f3b
HT		 1530 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1531 return false;
1532
1533 return true;
1534}
1535
eb977d99 1536static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
811c0830
YL		 1537 struct sk_buff *skb, struct hns3_desc *desc,
1538 struct hns3_desc_cb *desc_cb)
eb977d99
YL		 1539{
1540 u32 ol_type_vlan_len_msec = 0;
3e281621 1541 u32 paylen_ol4cs = skb->len;
eb977d99 1542 u32 type_cs_vlan_tso = 0;
66d52f3b 1543 u16 mss_hw_csum = 0;
eb977d99
YL		 1544 u16 inner_vtag = 0;
1545 u16 out_vtag = 0;
eb977d99
YL		 1546 int ret;
1547
1548 ret = hns3_handle_vtags(ring, skb);
1549 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1550 u64_stats_update_begin(&ring->syncp);
1551 ring->stats.tx_vlan_err++;
1552 u64_stats_update_end(&ring->syncp);
eb977d99
YL		 1553 return ret;
1554 } else if (ret == HNS3_INNER_VLAN_TAG) {
1555 inner_vtag = skb_vlan_tag_get(skb);
1556 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1557 VLAN_PRIO_MASK;
1558 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1559 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1560 out_vtag = skb_vlan_tag_get(skb);
1561 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1562 VLAN_PRIO_MASK;
1563 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1564 1);
1565 }
1566
811c0830
YL		 1567 desc_cb->send_bytes = skb->len;
1568
eb977d99
YL		 1569 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1570 u8 ol4_proto, il4_proto;
1571
66d52f3b
HT		 1572 if (hns3_check_hw_tx_csum(skb)) {
1573 /* set checksum start and offset, defined in 2 Bytes */
1574 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1575 skb_checksum_start_offset(skb) >> 1);
1576 hns3_set_field(ol_type_vlan_len_msec,
1577 HNS3_TXD_CSUM_OFFSET_S,
1578 skb->csum_offset >> 1);
1579 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1580 goto out_hw_tx_csum;
1581 }
1582
eb977d99
YL		 1583 skb_reset_mac_len(skb);
1584
1585 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
8ae10cfb 1586 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1587 u64_stats_update_begin(&ring->syncp);
1588 ring->stats.tx_l4_proto_err++;
1589 u64_stats_update_end(&ring->syncp);
eb977d99 1590 return ret;
b20d7fe5 1591 }
eb977d99
YL		 1592
1593 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1594 &type_cs_vlan_tso,
1595 &ol_type_vlan_len_msec);
8ae10cfb 1596 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1597 u64_stats_update_begin(&ring->syncp);
1598 ring->stats.tx_l2l3l4_err++;
1599 u64_stats_update_end(&ring->syncp);
eb977d99 1600 return ret;
b20d7fe5 1601 }
eb977d99 1602
3e281621 1603 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum,
811c0830 1604 &type_cs_vlan_tso, &desc_cb->send_bytes);
8ae10cfb 1605 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1606 u64_stats_update_begin(&ring->syncp);
1607 ring->stats.tx_tso_err++;
1608 u64_stats_update_end(&ring->syncp);
eb977d99 1609 return ret;
b20d7fe5 1610 }
eb977d99
YL		 1611 }
1612
66d52f3b 1613out_hw_tx_csum:
eb977d99
YL		 1614 /* Set txbd */
1615 desc->tx.ol_type_vlan_len_msec =
1616 cpu_to_le32(ol_type_vlan_len_msec);
1617 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
3e281621 1618 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs);
66d52f3b 1619 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum);
eb977d99
YL		 1620 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1621 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1622
1623 return 0;
1624}
1625
8677d78c
YL		 1626static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1627 unsigned int size)
76ad4f0e 1628{
8ae10cfb
YL		 1629#define HNS3_LIKELY_BD_NUM 1
1630
76ad4f0e 1631 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1e8a7977 1632 unsigned int frag_buf_num;
47e7b13b 1633 int k, sizeoflast;
bcdb12b7 1634
ceca4a5e 1635 if (likely(size <= HNS3_MAX_BD_SIZE)) {
ceca4a5e
YL		 1636 desc->addr = cpu_to_le64(dma);
1637 desc->tx.send_size = cpu_to_le16(size);
ceca4a5e 1638 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1639 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
ceca4a5e 1640
698a8954 1641 trace_hns3_tx_desc(ring, ring->next_to_use);
ceca4a5e 1642 ring_ptr_move_fw(ring, next_to_use);
8ae10cfb 1643 return HNS3_LIKELY_BD_NUM;
ceca4a5e
YL		 1644 }
1645
5f543a54 1646 frag_buf_num = hns3_tx_bd_count(size);
48ae74c9 1647 sizeoflast = size % HNS3_MAX_BD_SIZE;
1e8a7977
FL		 1648 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1649
1650 /* When frag size is bigger than hardware limit, split this frag */
1651 for (k = 0; k < frag_buf_num; k++) {
1e8a7977
FL		 1652 /* now, fill the descriptor */
1653 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1654 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1655 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977 1656 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1657 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1e8a7977 1658
698a8954 1659 trace_hns3_tx_desc(ring, ring->next_to_use);
9b2f3477 1660 /* move ring pointer to next */
1e8a7977
FL		 1661 ring_ptr_move_fw(ring, next_to_use);
1662
1e8a7977
FL		 1663 desc = &ring->desc[ring->next_to_use];
1664 }
76ad4f0e 1665
8ae10cfb 1666 return frag_buf_num;
76ad4f0e
S		 1667}
1668
8677d78c
YL		 1669static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1670 unsigned int type)
1671{
1672 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1673 struct device *dev = ring_to_dev(ring);
1674 unsigned int size;
1675 dma_addr_t dma;
1676
1677 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1678 struct sk_buff *skb = (struct sk_buff *)priv;
1679
1680 size = skb_headlen(skb);
1681 if (!size)
1682 return 0;
1683
1684 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
907676b1
YL		 1685 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1686 /* Head data has been filled in hns3_handle_tx_bounce(),
1687 * just return 0 here.
1688 */
1689 return 0;
8677d78c
YL		 1690 } else {
1691 skb_frag_t *frag = (skb_frag_t *)priv;
1692
1693 size = skb_frag_size(frag);
1694 if (!size)
1695 return 0;
1696
1697 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1698 }
1699
1700 if (unlikely(dma_mapping_error(dev, dma))) {
1701 u64_stats_update_begin(&ring->syncp);
1702 ring->stats.sw_err_cnt++;
1703 u64_stats_update_end(&ring->syncp);
1704 return -ENOMEM;
1705 }
1706
1707 desc_cb->priv = priv;
1708 desc_cb->length = size;
1709 desc_cb->dma = dma;
1710 desc_cb->type = type;
1711
1712 return hns3_fill_desc(ring, dma, size);
1713}
1714
8ae10cfb
YL		 1715static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1716 unsigned int bd_num)
76ad4f0e 1717{
8ae10cfb 1718 unsigned int size;
42611b70 1719 int i;
76ad4f0e 1720
8ae10cfb
YL		 1721 size = skb_headlen(skb);
1722 while (size > HNS3_MAX_BD_SIZE) {
1723 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1724 size -= HNS3_MAX_BD_SIZE;
1725
1726 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1727 return bd_num;
1728 }
76ad4f0e 1729
8ae10cfb
YL		 1730 if (size) {
1731 bd_size[bd_num++] = size;
1732 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1733 return bd_num;
1734 }
76ad4f0e 1735
3d5f3741 1736 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
d7840976 1737 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8ae10cfb
YL		 1738 size = skb_frag_size(frag);
1739 if (!size)
1740 continue;
1741
1742 while (size > HNS3_MAX_BD_SIZE) {
1743 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1744 size -= HNS3_MAX_BD_SIZE;
1745
1746 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1747 return bd_num;
1748 }
1749
1750 bd_size[bd_num++] = size;
1751 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1752 return bd_num;
1753 }
1754
1755 return bd_num;
1756}
1757
fd665b3d 1758static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
d5d5e019
YL		 1759 u8 max_non_tso_bd_num, unsigned int bd_num,
1760 unsigned int recursion_level)
8ae10cfb 1761{
d5d5e019
YL		 1762#define HNS3_MAX_RECURSION_LEVEL 24
1763
8ae10cfb 1764 struct sk_buff *frag_skb;
8ae10cfb
YL		 1765
1766 /* If the total len is within the max bd limit */
d5d5e019
YL		 1767 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1768 !skb_has_frag_list(skb) &&
fd665b3d 1769 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
8ae10cfb
YL		 1770 return skb_shinfo(skb)->nr_frags + 1U;
1771
d5d5e019
YL		 1772 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1773 return UINT_MAX;
8ae10cfb
YL		 1774
1775 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
8ae10cfb
YL		 1776 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1777 return bd_num;
1778
1779 skb_walk_frags(skb, frag_skb) {
d5d5e019
YL		 1780 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1781 bd_num, recursion_level + 1);
8ae10cfb
YL		 1782 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1783 return bd_num;
3d5f3741 1784 }
76ad4f0e 1785
3d5f3741 1786 return bd_num;
76ad4f0e
S		 1787}
1788
db4970aa
YL		 1789static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1790{
1791 if (!skb->encapsulation)
1792 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1793
1794 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1795}
1796
fd665b3d
HT		 1797/* HW need every continuous max_non_tso_bd_num buffer data to be larger
1798 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1799 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1800 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1801 * than MSS except the last max_non_tso_bd_num - 1 frags.
db4970aa 1802 */
8ae10cfb 1803static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
fd665b3d 1804 unsigned int bd_num, u8 max_non_tso_bd_num)
db4970aa 1805{
db4970aa
YL		 1806 unsigned int tot_len = 0;
1807 int i;
1808
fd665b3d 1809 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
8ae10cfb 1810 tot_len += bd_size[i];
db4970aa 1811
fd665b3d
HT		 1812 /* ensure the first max_non_tso_bd_num frags is greater than
1813 * mss + header
1814 */
1815 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
8ae10cfb 1816 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
db4970aa
YL		 1817 return true;
1818
fd665b3d
HT		 1819 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1820 * than mss except the last one.
8ae10cfb 1821 */
fd665b3d 1822 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
8ae10cfb 1823 tot_len -= bd_size[i];
fd665b3d 1824 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
db4970aa
YL		 1825
1826 if (tot_len < skb_shinfo(skb)->gso_size)
1827 return true;
1828 }
1829
1830 return false;
1831}
1832
698a8954
YL		 1833void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1834{
9d8d5a36 1835 int i;
698a8954
YL		 1836
1837 for (i = 0; i < MAX_SKB_FRAGS; i++)
1838 size[i] = skb_frag_size(&shinfo->frags[i]);
1839}
1840
d5d5e019
YL		 1841static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1842 struct sk_buff *skb,
1843 u8 max_non_tso_bd_num,
1844 unsigned int bd_num)
1845{
1846 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1847 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1848 */
1849 if (bd_num == UINT_MAX) {
1850 u64_stats_update_begin(&ring->syncp);
1851 ring->stats.over_max_recursion++;
1852 u64_stats_update_end(&ring->syncp);
1853 return -ENOMEM;
1854 }
1855
1856 /* The skb->len has exceeded the hw limitation, linearization
1857 * will not help.
1858 */
1859 if (skb->len > HNS3_MAX_TSO_SIZE ||
1860 (!skb_is_gso(skb) && skb->len >
1861 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) {
1862 u64_stats_update_begin(&ring->syncp);
1863 ring->stats.hw_limitation++;
1864 u64_stats_update_end(&ring->syncp);
1865 return -ENOMEM;
1866 }
1867
1868 if (__skb_linearize(skb)) {
1869 u64_stats_update_begin(&ring->syncp);
1870 ring->stats.sw_err_cnt++;
1871 u64_stats_update_end(&ring->syncp);
1872 return -ENOMEM;
1873 }
1874
1875 return 0;
1876}
1877
3d5f3741 1878static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
2a597eff 1879 struct net_device *netdev,
d1a37ded 1880 struct sk_buff *skb)
76ad4f0e 1881{
2a597eff 1882 struct hns3_nic_priv *priv = netdev_priv(netdev);
fd665b3d 1883 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
8ae10cfb 1884 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
42611b70 1885 unsigned int bd_num;
76ad4f0e 1886
d5d5e019 1887 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
fd665b3d 1888 if (unlikely(bd_num > max_non_tso_bd_num)) {
8ae10cfb 1889 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
fd665b3d
HT		 1890 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1891 max_non_tso_bd_num)) {
6ad595bc 1892 trace_hns3_over_max_bd(skb);
db4970aa 1893 goto out;
698a8954 1894 }
db4970aa 1895
d5d5e019
YL		 1896 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num,
1897 bd_num))
51e8439f 1898 return -ENOMEM;
3d5f3741 1899
d1a37ded 1900 bd_num = hns3_tx_bd_count(skb->len);
42611b70 1901
3d5f3741
YL		 1902 u64_stats_update_begin(&ring->syncp);
1903 ring->stats.tx_copy++;
1904 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1905 }
1906
db4970aa 1907out:
2a597eff
YL		 1908 if (likely(ring_space(ring) >= bd_num))
1909 return bd_num;
76ad4f0e 1910
2a597eff
YL		 1911 netif_stop_subqueue(netdev, ring->queue_index);
1912 smp_mb(); /* Memory barrier before checking ring_space */
1913
1914 /* Start queue in case hns3_clean_tx_ring has just made room
1915 * available and has not seen the queue stopped state performed
1916 * by netif_stop_subqueue above.
1917 */
1918 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1919 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1920 netif_start_subqueue(netdev, ring->queue_index);
1921 return bd_num;
1922 }
1923
d5d5e019
YL		 1924 u64_stats_update_begin(&ring->syncp);
1925 ring->stats.tx_busy++;
1926 u64_stats_update_end(&ring->syncp);
1927
2a597eff 1928 return -EBUSY;
76ad4f0e
S		 1929}
1930
ba3f808f 1931static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1932{
1933 struct device *dev = ring_to_dev(ring);
1934 unsigned int i;
1935
1936 for (i = 0; i < ring->desc_num; i++) {
8ceca59f 1937 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
26f1ccdf 1938 struct hns3_desc_cb *desc_cb;
8ceca59f
YL		 1939
1940 memset(desc, 0, sizeof(*desc));
1941
76ad4f0e
S		 1942 /* check if this is where we started */
1943 if (ring->next_to_use == next_to_use_orig)
1944 break;
1945
aa9d22dd
YL		 1946 /* rollback one */
1947 ring_ptr_move_bw(ring, next_to_use);
1948
26f1ccdf
YL		 1949 desc_cb = &ring->desc_cb[ring->next_to_use];
1950
1951 if (!desc_cb->dma)
8ceca59f
YL		 1952 continue;
1953
76ad4f0e 1954 /* unmap the descriptor dma address */
26f1ccdf
YL		 1955 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
1956 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
1957 DMA_TO_DEVICE);
907676b1
YL		 1958 else if (desc_cb->type &
1959 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
1960 hns3_tx_spare_rollback(ring, desc_cb->length);
26f1ccdf
YL		 1961 else if (desc_cb->length)
1962 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
76ad4f0e
S		 1963 DMA_TO_DEVICE);
1964
26f1ccdf
YL		 1965 desc_cb->length = 0;
1966 desc_cb->dma = 0;
1967 desc_cb->type = DESC_TYPE_UNKNOWN;
76ad4f0e
S		 1968 }
1969}
1970
8ae10cfb 1971static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
26f1ccdf 1972 struct sk_buff *skb, unsigned int type)
8ae10cfb 1973{
d5d5e019 1974 struct sk_buff *frag_skb;
8ae10cfb
YL		 1975 int i, ret, bd_num = 0;
1976
8677d78c
YL		 1977 ret = hns3_map_and_fill_desc(ring, skb, type);
1978 if (unlikely(ret < 0))
1979 return ret;
8ae10cfb 1980
8677d78c 1981 bd_num += ret;
8ae10cfb
YL		 1982
1983 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1984 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1985
8677d78c 1986 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
8ae10cfb
YL		 1987 if (unlikely(ret < 0))
1988 return ret;
1989
1990 bd_num += ret;
1991 }
1992
d5d5e019
YL		 1993 skb_walk_frags(skb, frag_skb) {
1994 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1995 DESC_TYPE_FRAGLIST_SKB);
1996 if (unlikely(ret < 0))
1997 return ret;
1998
1999 bd_num += ret;
2000 }
2001
8ae10cfb
YL		 2002 return bd_num;
2003}
2004
f6061a05
YL		 2005static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2006 bool doorbell)
2007{
2008 ring->pending_buf += num;
2009
2010 if (!doorbell) {
2011 u64_stats_update_begin(&ring->syncp);
2012 ring->stats.tx_more++;
2013 u64_stats_update_end(&ring->syncp);
2014 return;
2015 }
2016
2017 if (!ring->pending_buf)
2018 return;
2019
48ee56fd
YL		 2020 writel(ring->pending_buf,
2021 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
f6061a05 2022 ring->pending_buf = 0;
20d06ca2 2023 WRITE_ONCE(ring->last_to_use, ring->next_to_use);
f6061a05
YL		 2024}
2025
0bf5eb78
HT		 2026static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2027 struct hns3_desc *desc)
2028{
2029 struct hnae3_handle *h = hns3_get_handle(netdev);
2030
2031 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2032 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2033 return;
2034
2035 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2036}
2037
907676b1
YL		 2038static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2039 struct sk_buff *skb)
2040{
2041 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2042 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2043 unsigned int size = skb_headlen(skb);
2044 dma_addr_t dma;
2045 int bd_num = 0;
2046 u32 cb_len;
2047 void *buf;
2048 int ret;
2049
2050 if (skb->len <= ring->tx_copybreak) {
2051 size = skb->len;
2052 type = DESC_TYPE_BOUNCE_ALL;
2053 }
2054
2055 /* hns3_can_use_tx_bounce() is called to ensure the below
2056 * function can always return the tx buffer.
2057 */
2058 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2059
2060 ret = skb_copy_bits(skb, 0, buf, size);
2061 if (unlikely(ret < 0)) {
2062 hns3_tx_spare_rollback(ring, cb_len);
2063 u64_stats_update_begin(&ring->syncp);
2064 ring->stats.copy_bits_err++;
2065 u64_stats_update_end(&ring->syncp);
2066 return ret;
2067 }
2068
2069 desc_cb->priv = skb;
2070 desc_cb->length = cb_len;
2071 desc_cb->dma = dma;
2072 desc_cb->type = type;
2073
2074 bd_num += hns3_fill_desc(ring, dma, size);
2075
2076 if (type == DESC_TYPE_BOUNCE_HEAD) {
2077 ret = hns3_fill_skb_to_desc(ring, skb,
2078 DESC_TYPE_BOUNCE_HEAD);
2079 if (unlikely(ret < 0))
2080 return ret;
2081
2082 bd_num += ret;
2083 }
2084
2085 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2086 DMA_TO_DEVICE);
2087
2088 u64_stats_update_begin(&ring->syncp);
2089 ring->stats.tx_bounce++;
2090 u64_stats_update_end(&ring->syncp);
2091 return bd_num;
2092}
2093
7459775e
YL		 2094static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2095 struct sk_buff *skb)
2096{
2097 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2098 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2099 struct sg_table *sgt;
2100 int i, bd_num = 0;
2101 dma_addr_t dma;
2102 u32 cb_len;
2103 int nents;
2104
2105 if (skb_has_frag_list(skb))
2106 nfrag = HNS3_MAX_TSO_BD_NUM;
2107
2108 /* hns3_can_use_tx_sgl() is called to ensure the below
2109 * function can always return the tx buffer.
2110 */
2111 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2112 &dma, &cb_len);
2113
2114 /* scatterlist follows by the sg table */
2115 sgt->sgl = (struct scatterlist *)(sgt + 1);
2116 sg_init_table(sgt->sgl, nfrag);
2117 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2118 if (unlikely(nents < 0)) {
2119 hns3_tx_spare_rollback(ring, cb_len);
2120 u64_stats_update_begin(&ring->syncp);
2121 ring->stats.skb2sgl_err++;
2122 u64_stats_update_end(&ring->syncp);
2123 return -ENOMEM;
2124 }
2125
2126 sgt->orig_nents = nents;
2127 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2128 DMA_TO_DEVICE);
2129 if (unlikely(!sgt->nents)) {
2130 hns3_tx_spare_rollback(ring, cb_len);
2131 u64_stats_update_begin(&ring->syncp);
2132 ring->stats.map_sg_err++;
2133 u64_stats_update_end(&ring->syncp);
2134 return -ENOMEM;
2135 }
2136
2137 desc_cb->priv = skb;
2138 desc_cb->length = cb_len;
2139 desc_cb->dma = dma;
2140 desc_cb->type = DESC_TYPE_SGL_SKB;
2141
2142 for (i = 0; i < sgt->nents; i++)
2143 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2144 sg_dma_len(sgt->sgl + i));
2145
2146 u64_stats_update_begin(&ring->syncp);
2147 ring->stats.tx_sgl++;
2148 u64_stats_update_end(&ring->syncp);
2149
2150 return bd_num;
2151}
2152
907676b1
YL		 2153static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2154 struct sk_buff *skb)
2155{
2156 u32 space;
2157
2158 if (!ring->tx_spare)
2159 goto out;
2160
2161 space = hns3_tx_spare_space(ring);
2162
7459775e
YL		 2163 if (hns3_can_use_tx_sgl(ring, skb, space))
2164 return hns3_handle_tx_sgl(ring, skb);
2165
907676b1
YL		 2166 if (hns3_can_use_tx_bounce(ring, skb, space))
2167 return hns3_handle_tx_bounce(ring, skb);
2168
2169out:
2170 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2171}
2172
d43e5aca 2173netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 2174{
2175 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f06b903 2176 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
811c0830 2177 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
76ad4f0e 2178 struct netdev_queue *dev_queue;
8ae10cfb 2179 int pre_ntu, next_to_use_head;
f6061a05 2180 bool doorbell;
76ad4f0e 2181 int ret;
76ad4f0e 2182
36c67349 2183 /* Hardware can only handle short frames above 32 bytes */
f6061a05
YL		 2184 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2185 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
97b9e5c1
YL		 2186
2187 u64_stats_update_begin(&ring->syncp);
2188 ring->stats.sw_err_cnt++;
2189 u64_stats_update_end(&ring->syncp);
2190
36c67349 2191 return NETDEV_TX_OK;
f6061a05 2192 }
36c67349 2193
76ad4f0e
S		 2194 /* Prefetch the data used later */
2195 prefetch(skb->data);
2196
d1a37ded 2197 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
8ae10cfb
YL		 2198 if (unlikely(ret <= 0)) {
2199 if (ret == -EBUSY) {
f6061a05 2200 hns3_tx_doorbell(ring, 0, true);
2a597eff 2201 return NETDEV_TX_BUSY;
3d5f3741 2202 }
76ad4f0e 2203
8ae10cfb 2204 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
76ad4f0e 2205 goto out_err_tx_ok;
76ad4f0e
S		 2206 }
2207
76ad4f0e
S		 2208 next_to_use_head = ring->next_to_use;
2209
811c0830
YL		 2210 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2211 desc_cb);
cfdaeba5
YL		 2212 if (unlikely(ret < 0))
2213 goto fill_err;
2214
d5d5e019
YL		 2215 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2216 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2217 * need to be notified to the hw.
2218 */
907676b1 2219 ret = hns3_handle_desc_filling(ring, skb);
d5d5e019 2220 if (unlikely(ret <= 0))
aa9d22dd 2221 goto fill_err;
76ad4f0e 2222
8ae10cfb
YL		 2223 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2224 (ring->desc_num - 1);
0bf5eb78
HT		 2225
2226 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2227 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2228
8ae10cfb
YL		 2229 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2230 cpu_to_le16(BIT(HNS3_TXD_FE_B));
698a8954 2231 trace_hns3_tx_desc(ring, pre_ntu);
76ad4f0e 2232
0bf5eb78
HT		 2233 skb_tx_timestamp(skb);
2234
76ad4f0e 2235 /* Complete translate all packets */
5f06b903 2236 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
811c0830 2237 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
f6061a05 2238 netdev_xmit_more());
d5d5e019 2239 hns3_tx_doorbell(ring, ret, doorbell);
76ad4f0e
S		 2240
2241 return NETDEV_TX_OK;
2242
aa9d22dd 2243fill_err:
ba3f808f 2244 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 2245
2246out_err_tx_ok:
2247 dev_kfree_skb_any(skb);
f6061a05 2248 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
76ad4f0e 2249 return NETDEV_TX_OK;
76ad4f0e
S		 2250}
2251
2252static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2253{
9780cb97 2254 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2255 struct sockaddr *mac_addr = p;
2256 int ret;
2257
2258 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2259 return -EADDRNOTAVAIL;
2260
5ec2a51e
JS		 2261 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2262 netdev_info(netdev, "already using mac address %pM\n",
2263 mac_addr->sa_data);
2264 return 0;
2265 }
2266
8e6de441
HT		 2267 /* For VF device, if there is a perm_addr, then the user will not
2268 * be allowed to change the address.
2269 */
2270 if (!hns3_is_phys_func(h->pdev) &&
2271 !is_zero_ether_addr(netdev->perm_addr)) {
2272 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
2273 netdev->perm_addr, mac_addr->sa_data);
2274 return -EPERM;
2275 }
2276
59098055 2277 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 2278 if (ret) {
2279 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2280 return ret;
2281 }
2282
2283 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
2284
2285 return 0;
2286}
2287
26483246
XW		 2288static int hns3_nic_do_ioctl(struct net_device *netdev,
2289 struct ifreq *ifr, int cmd)
2290{
2291 struct hnae3_handle *h = hns3_get_handle(netdev);
2292
2293 if (!netif_running(netdev))
2294 return -EINVAL;
2295
2296 if (!h->ae_algo->ops->do_ioctl)
2297 return -EOPNOTSUPP;
2298
2299 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2300}
2301
76ad4f0e
S		 2302static int hns3_nic_set_features(struct net_device *netdev,
2303 netdev_features_t features)
2304{
181d454b 2305 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 2306 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 2307 struct hnae3_handle *h = priv->ae_handle;
1731be4c 2308 bool enable;
052ece6d 2309 int ret;
76ad4f0e 2310
5c9f6b39 2311 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 2312 enable = !!(features & NETIF_F_GRO_HW);
2313 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 2314 if (ret)
2315 return ret;
2316 }
2317
bd368416
JS		 2318 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2319 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 2320 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2321 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 2322 if (ret)
2323 return ret;
2324 }
2325
c17852a8 2326 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 2327 enable = !!(features & NETIF_F_NTUPLE);
2328 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 2329 }
2330
0205ec04
JS		 2331 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2332 h->ae_algo->ops->cls_flower_active(h)) {
2333 netdev_err(netdev,
2334 "there are offloaded TC filters active, cannot disable HW TC offload");
2335 return -EINVAL;
2336 }
2337
2ba30662
JS		 2338 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2339 h->ae_algo->ops->enable_vlan_filter) {
2340 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2341 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2342 if (ret)
2343 return ret;
2344 }
2345
76ad4f0e
S		 2346 netdev->features = features;
2347 return 0;
2348}
2349
2a7556bb
YL		 2350static netdev_features_t hns3_features_check(struct sk_buff *skb,
2351 struct net_device *dev,
2352 netdev_features_t features)
2353{
2354#define HNS3_MAX_HDR_LEN 480U
2355#define HNS3_MAX_L4_HDR_LEN 60U
2356
2357 size_t len;
2358
2359 if (skb->ip_summed != CHECKSUM_PARTIAL)
2360 return features;
2361
2362 if (skb->encapsulation)
2363 len = skb_inner_transport_header(skb) - skb->data;
2364 else
2365 len = skb_transport_header(skb) - skb->data;
2366
2367 /* Assume L4 is 60 byte as TCP is the only protocol with a
2368 * a flexible value, and it's max len is 60 bytes.
2369 */
2370 len += HNS3_MAX_L4_HDR_LEN;
2371
2372 /* Hardware only supports checksum on the skb with a max header
2373 * len of 480 bytes.
2374 */
2375 if (len > HNS3_MAX_HDR_LEN)
2376 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2377
2378 return features;
2379}
2380
6c88d9d7
PL		 2381static void hns3_nic_get_stats64(struct net_device *netdev,
2382 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 2383{
2384 struct hns3_nic_priv *priv = netdev_priv(netdev);
2385 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 2386 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 2387 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 2388 u64 rx_length_errors = 0;
2389 u64 rx_crc_errors = 0;
2390 u64 rx_multicast = 0;
76ad4f0e 2391 unsigned int start;
d3ec4ef6
JS		 2392 u64 tx_errors = 0;
2393 u64 rx_errors = 0;
76ad4f0e
S		 2394 unsigned int idx;
2395 u64 tx_bytes = 0;
2396 u64 rx_bytes = 0;
2397 u64 tx_pkts = 0;
2398 u64 rx_pkts = 0;
d2a5dca8
JS		 2399 u64 tx_drop = 0;
2400 u64 rx_drop = 0;
76ad4f0e 2401
b875cc37
JS		 2402 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2403 return;
2404
c5f65480
JS		 2405 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
2406
76ad4f0e
S		 2407 for (idx = 0; idx < queue_num; idx++) {
2408 /* fetch the tx stats */
5f06b903 2409 ring = &priv->ring[idx];
76ad4f0e 2410 do {
d36d36ce 2411 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 2412 tx_bytes += ring->stats.tx_bytes;
2413 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 2414 tx_drop += ring->stats.sw_err_cnt;
b20d7fe5
YL		 2415 tx_drop += ring->stats.tx_vlan_err;
2416 tx_drop += ring->stats.tx_l4_proto_err;
2417 tx_drop += ring->stats.tx_l2l3l4_err;
2418 tx_drop += ring->stats.tx_tso_err;
d5d5e019
YL		 2419 tx_drop += ring->stats.over_max_recursion;
2420 tx_drop += ring->stats.hw_limitation;
907676b1 2421 tx_drop += ring->stats.copy_bits_err;
7459775e
YL		 2422 tx_drop += ring->stats.skb2sgl_err;
2423 tx_drop += ring->stats.map_sg_err;
d3ec4ef6 2424 tx_errors += ring->stats.sw_err_cnt;
b20d7fe5
YL		 2425 tx_errors += ring->stats.tx_vlan_err;
2426 tx_errors += ring->stats.tx_l4_proto_err;
2427 tx_errors += ring->stats.tx_l2l3l4_err;
2428 tx_errors += ring->stats.tx_tso_err;
d5d5e019
YL		 2429 tx_errors += ring->stats.over_max_recursion;
2430 tx_errors += ring->stats.hw_limitation;
907676b1 2431 tx_errors += ring->stats.copy_bits_err;
7459775e
YL		 2432 tx_errors += ring->stats.skb2sgl_err;
2433 tx_errors += ring->stats.map_sg_err;
76ad4f0e
S		 2434 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2435
2436 /* fetch the rx stats */
5f06b903 2437 ring = &priv->ring[idx + queue_num];
76ad4f0e 2438 do {
d36d36ce 2439 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 2440 rx_bytes += ring->stats.rx_bytes;
2441 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 2442 rx_drop += ring->stats.l2_err;
d3ec4ef6 2443 rx_errors += ring->stats.l2_err;
8b552079 2444 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 2445 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS		 2446 rx_multicast += ring->stats.rx_multicast;
2447 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 2448 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2449 }
2450
2451 stats->tx_bytes = tx_bytes;
2452 stats->tx_packets = tx_pkts;
2453 stats->rx_bytes = rx_bytes;
2454 stats->rx_packets = rx_pkts;
2455
d3ec4ef6
JS		 2456 stats->rx_errors = rx_errors;
2457 stats->multicast = rx_multicast;
2458 stats->rx_length_errors = rx_length_errors;
2459 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 2460 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2461
d3ec4ef6
JS		 2462 stats->tx_errors = tx_errors;
2463 stats->rx_dropped = rx_drop;
2464 stats->tx_dropped = tx_drop;
76ad4f0e
S		 2465 stats->collisions = netdev->stats.collisions;
2466 stats->rx_over_errors = netdev->stats.rx_over_errors;
2467 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2468 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2469 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2470 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2471 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2472 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2473 stats->tx_window_errors = netdev->stats.tx_window_errors;
2474 stats->rx_compressed = netdev->stats.rx_compressed;
2475 stats->tx_compressed = netdev->stats.tx_compressed;
2476}
2477
30d240df 2478static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 2479{
30d240df 2480 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
75718800 2481 struct hnae3_knic_private_info *kinfo;
30d240df
YL		 2482 u8 tc = mqprio_qopt->qopt.num_tc;
2483 u16 mode = mqprio_qopt->mode;
2484 u8 hw = mqprio_qopt->qopt.hw;
75718800 2485 struct hnae3_handle *h;
76ad4f0e 2486
30d240df
YL		 2487 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2488 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2489 return -EOPNOTSUPP;
2490
76ad4f0e
S		 2491 if (tc > HNAE3_MAX_TC)
2492 return -EINVAL;
2493
76ad4f0e
S		 2494 if (!netdev)
2495 return -EINVAL;
2496
75718800
YL		 2497 h = hns3_get_handle(netdev);
2498 kinfo = &h->kinfo;
2499
1c822948
YL		 2500 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2501
1cce5eb6 2502 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
5a5c9091 2503 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
76ad4f0e
S		 2504}
2505
0205ec04
JS		 2506static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2507 struct flow_cls_offload *flow)
2508{
2509 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2510 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2511
2512 switch (flow->command) {
2513 case FLOW_CLS_REPLACE:
2514 if (h->ae_algo->ops->add_cls_flower)
2515 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2516 break;
2517 case FLOW_CLS_DESTROY:
2518 if (h->ae_algo->ops->del_cls_flower)
2519 return h->ae_algo->ops->del_cls_flower(h, flow);
2520 break;
2521 default:
2522 break;
2523 }
2524
2525 return -EOPNOTSUPP;
2526}
2527
2528static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2529 void *cb_priv)
2530{
2531 struct hns3_nic_priv *priv = cb_priv;
2532
2533 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2534 return -EOPNOTSUPP;
2535
2536 switch (type) {
2537 case TC_SETUP_CLSFLOWER:
2538 return hns3_setup_tc_cls_flower(priv, type_data);
2539 default:
2540 return -EOPNOTSUPP;
2541 }
2542}
2543
2544static LIST_HEAD(hns3_block_cb_list);
2545
2572ac53 2546static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 2547 void *type_data)
76ad4f0e 2548{
0205ec04
JS		 2549 struct hns3_nic_priv *priv = netdev_priv(dev);
2550 int ret;
2551
2552 switch (type) {
2553 case TC_SETUP_QDISC_MQPRIO:
2554 ret = hns3_setup_tc(dev, type_data);
2555 break;
2556 case TC_SETUP_BLOCK:
2557 ret = flow_block_cb_setup_simple(type_data,
2558 &hns3_block_cb_list,
2559 hns3_setup_tc_block_cb,
2560 priv, priv, true);
2561 break;
2562 default:
38cf0426 2563 return -EOPNOTSUPP;
0205ec04 2564 }
76ad4f0e 2565
0205ec04 2566 return ret;
76ad4f0e
S		 2567}
2568
2569static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2570 __be16 proto, u16 vid)
2571{
9780cb97 2572 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2573 int ret = -EIO;
2574
2575 if (h->ae_algo->ops->set_vlan_filter)
2576 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2577
2578 return ret;
2579}
2580
2581static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2582 __be16 proto, u16 vid)
2583{
9780cb97 2584 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2585 int ret = -EIO;
2586
2587 if (h->ae_algo->ops->set_vlan_filter)
2588 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2589
7fa6be4f 2590 return ret;
681ec399
YL		 2591}
2592
76ad4f0e
S		 2593static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2594 u8 qos, __be16 vlan_proto)
2595{
9780cb97 2596 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2597 int ret = -EIO;
2598
1c822948 2599 netif_dbg(h, drv, netdev,
39edaf24
GL		 2600 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2601 vf, vlan, qos, ntohs(vlan_proto));
1c822948 2602
76ad4f0e
S		 2603 if (h->ae_algo->ops->set_vf_vlan_filter)
2604 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 2605 qos, vlan_proto);
76ad4f0e
S		 2606
2607 return ret;
2608}
2609
22044f95
JS		 2610static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2611{
2612 struct hnae3_handle *handle = hns3_get_handle(netdev);
2613
2614 if (hns3_nic_resetting(netdev))
2615 return -EBUSY;
2616
2617 if (!handle->ae_algo->ops->set_vf_spoofchk)
2618 return -EOPNOTSUPP;
2619
2620 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2621}
2622
e196ec75
JS		 2623static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2624{
2625 struct hnae3_handle *handle = hns3_get_handle(netdev);
2626
2627 if (!handle->ae_algo->ops->set_vf_trust)
2628 return -EOPNOTSUPP;
2629
2630 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2631}
2632
a8e8b7ff
S		 2633static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2634{
9780cb97 2635 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 2636 int ret;
2637
6ff7ed80
HT		 2638 if (hns3_nic_resetting(netdev))
2639 return -EBUSY;
2640
a8e8b7ff
S		 2641 if (!h->ae_algo->ops->set_mtu)
2642 return -EOPNOTSUPP;
2643
1c822948
YL		 2644 netif_dbg(h, drv, netdev,
2645 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2646
a8e8b7ff 2647 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 2648 if (ret)
a8e8b7ff
S		 2649 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2650 ret);
93d8daf4
YL		 2651 else
2652 netdev->mtu = new_mtu;
5bad95a1 2653
a8e8b7ff
S		 2654 return ret;
2655}
2656
f8fa222c
L		 2657static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2658{
2659 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 2660 struct hnae3_handle *h = hns3_get_handle(ndev);
0bfdf286 2661 struct hns3_enet_ring *tx_ring;
e511c97d 2662 struct napi_struct *napi;
f8fa222c
L		 2663 int timeout_queue = 0;
2664 int hw_head, hw_tail;
e511c97d
JS		 2665 int fbd_num, fbd_oft;
2666 int ebd_num, ebd_oft;
2667 int bd_num, bd_err;
2668 int ring_en, tc;
f8fa222c
L		 2669 int i;
2670
2671 /* Find the stopped queue the same way the stack does */
fa6c4084 2672 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 2673 struct netdev_queue *q;
2674 unsigned long trans_start;
2675
2676 q = netdev_get_tx_queue(ndev, i);
2677 trans_start = q->trans_start;
2678 if (netif_xmit_stopped(q) &&
2679 time_after(jiffies,
2680 (trans_start + ndev->watchdog_timeo))) {
2681 timeout_queue = i;
647522a5
YL		 2682 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2683 q->state,
2684 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L		 2685 break;
2686 }
2687 }
2688
2689 if (i == ndev->num_tx_queues) {
2690 netdev_info(ndev,
2691 "no netdev TX timeout queue found, timeout count: %llu\n",
2692 priv->tx_timeout_count);
2693 return false;
2694 }
2695
beab694a
JS		 2696 priv->tx_timeout_count++;
2697
5f06b903 2698 tx_ring = &priv->ring[timeout_queue];
e511c97d
JS		 2699 napi = &tx_ring->tqp_vector->napi;
2700
2701 netdev_info(ndev,
2702 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2703 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2704 tx_ring->next_to_clean, napi->state);
2705
2706 netdev_info(ndev,
20d06ca2 2707 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
e511c97d 2708 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
20d06ca2 2709 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
e511c97d
JS		 2710
2711 netdev_info(ndev,
f6061a05
YL		 2712 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2713 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
e511c97d
JS		 2714 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2715
2716 /* When mac received many pause frames continuous, it's unable to send
2717 * packets, which may cause tx timeout
2718 */
615466ce
YM		 2719 if (h->ae_algo->ops->get_mac_stats) {
2720 struct hns3_mac_stats mac_stats;
e511c97d 2721
615466ce 2722 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
e511c97d 2723 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
615466ce 2724 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
e511c97d 2725 }
f8fa222c
L		 2726
2727 hw_head = readl_relaxed(tx_ring->tqp->io_base +
2728 HNS3_RING_TX_RING_HEAD_REG);
2729 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
2730 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 2731 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
2732 HNS3_RING_TX_RING_FBDNUM_REG);
2733 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
2734 HNS3_RING_TX_RING_OFFSET_REG);
2735 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
2736 HNS3_RING_TX_RING_EBDNUM_REG);
2737 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
2738 HNS3_RING_TX_RING_EBD_OFFSET_REG);
2739 bd_num = readl_relaxed(tx_ring->tqp->io_base +
2740 HNS3_RING_TX_RING_BD_NUM_REG);
2741 bd_err = readl_relaxed(tx_ring->tqp->io_base +
2742 HNS3_RING_TX_RING_BD_ERR_REG);
2743 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
2744 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
2745
f8fa222c 2746 netdev_info(ndev,
e511c97d
JS		 2747 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2748 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 2749 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 2750 netdev_info(ndev,
2751 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2752 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 2753
2754 return true;
2755}
2756
0290bd29 2757static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
f8fa222c
L		 2758{
2759 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 2760 struct hnae3_handle *h = priv->ae_handle;
2761
2762 if (!hns3_get_tx_timeo_queue_info(ndev))
2763 return;
2764
0742ed7c
HT		 2765 /* request the reset, and let the hclge to determine
2766 * which reset level should be done
2767 */
f8fa222c 2768 if (h->ae_algo->ops->reset_event)
6ae4e733 2769 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 2770}
2771
d93ed94f
JS		 2772#ifdef CONFIG_RFS_ACCEL
2773static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2774 u16 rxq_index, u32 flow_id)
2775{
2776 struct hnae3_handle *h = hns3_get_handle(dev);
2777 struct flow_keys fkeys;
2778
2779 if (!h->ae_algo->ops->add_arfs_entry)
2780 return -EOPNOTSUPP;
2781
2782 if (skb->encapsulation)
2783 return -EPROTONOSUPPORT;
2784
2785 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2786 return -EPROTONOSUPPORT;
2787
2788 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2789 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2790 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2791 fkeys.basic.ip_proto != IPPROTO_UDP))
2792 return -EPROTONOSUPPORT;
2793
2794 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2795}
2796#endif
2797
6430f744
YM		 2798static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2799 struct ifla_vf_info *ivf)
2800{
2801 struct hnae3_handle *h = hns3_get_handle(ndev);
2802
2803 if (!h->ae_algo->ops->get_vf_config)
2804 return -EOPNOTSUPP;
2805
2806 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2807}
2808
2809static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2810 int link_state)
2811{
2812 struct hnae3_handle *h = hns3_get_handle(ndev);
2813
2814 if (!h->ae_algo->ops->set_vf_link_state)
2815 return -EOPNOTSUPP;
2816
2817 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2818}
2819
ee9e4424
YL		 2820static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2821 int min_tx_rate, int max_tx_rate)
2822{
2823 struct hnae3_handle *h = hns3_get_handle(ndev);
2824
2825 if (!h->ae_algo->ops->set_vf_rate)
2826 return -EOPNOTSUPP;
2827
2828 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2829 false);
2830}
2831
8e6de441
HT		 2832static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2833{
2834 struct hnae3_handle *h = hns3_get_handle(netdev);
2835
2836 if (!h->ae_algo->ops->set_vf_mac)
2837 return -EOPNOTSUPP;
2838
2839 if (is_multicast_ether_addr(mac)) {
2840 netdev_err(netdev,
2841 "Invalid MAC:%pM specified. Could not set MAC\n",
2842 mac);
2843 return -EINVAL;
2844 }
2845
2846 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2847}
2848
76ad4f0e
S		 2849static const struct net_device_ops hns3_nic_netdev_ops = {
2850 .ndo_open = hns3_nic_net_open,
2851 .ndo_stop = hns3_nic_net_stop,
2852 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 2853 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 2854 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 2855 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 2856 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e 2857 .ndo_set_features = hns3_nic_set_features,
2a7556bb 2858 .ndo_features_check = hns3_features_check,
76ad4f0e
S		 2859 .ndo_get_stats64 = hns3_nic_get_stats64,
2860 .ndo_setup_tc = hns3_nic_setup_tc,
2861 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 2862 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2863 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2864 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
22044f95 2865 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
e196ec75 2866 .ndo_set_vf_trust = hns3_set_vf_trust,
d93ed94f
JS		 2867#ifdef CONFIG_RFS_ACCEL
2868 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2869#endif
6430f744
YM		 2870 .ndo_get_vf_config = hns3_nic_get_vf_config,
2871 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
ee9e4424 2872 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
8e6de441 2873 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
76ad4f0e
S		 2874};
2875
97afd47b 2876bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 2877{
2878 u32 dev_id = pdev->device;
2879
2880 switch (dev_id) {
2881 case HNAE3_DEV_ID_GE:
2882 case HNAE3_DEV_ID_25GE:
2883 case HNAE3_DEV_ID_25GE_RDMA:
2884 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2885 case HNAE3_DEV_ID_50GE_RDMA:
2886 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2887 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
ae6f010c 2888 case HNAE3_DEV_ID_200G_RDMA:
2312e050 2889 return true;
c155e22b
GH		 2890 case HNAE3_DEV_ID_VF:
2891 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
2312e050
FL		 2892 return false;
2893 default:
adcf738b 2894 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2312e050
FL		 2895 dev_id);
2896 }
2897
2898 return false;
2899}
2900
2312e050
FL		 2901static void hns3_disable_sriov(struct pci_dev *pdev)
2902{
2903 /* If our VFs are assigned we cannot shut down SR-IOV
2904 * without causing issues, so just leave the hardware
2905 * available but disabled
2906 */
2907 if (pci_vfs_assigned(pdev)) {
2908 dev_warn(&pdev->dev,
2909 "disabling driver while VFs are assigned\n");
2910 return;
2911 }
2912
2913 pci_disable_sriov(pdev);
2914}
2915
76ad4f0e
S		 2916/* hns3_probe - Device initialization routine
2917 * @pdev: PCI device information struct
2918 * @ent: entry in hns3_pci_tbl
2919 *
2920 * hns3_probe initializes a PF identified by a pci_dev structure.
2921 * The OS initialization, configuring of the PF private structure,
2922 * and a hardware reset occur.
2923 *
2924 * Returns 0 on success, negative on failure
2925 */
2926static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2927{
2928 struct hnae3_ae_dev *ae_dev;
2929 int ret;
2930
9b2f3477 2931 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
60df7e91
HT		 2932 if (!ae_dev)
2933 return -ENOMEM;
76ad4f0e
S		 2934
2935 ae_dev->pdev = pdev;
e92a0843 2936 ae_dev->flag = ent->driver_data;
76ad4f0e
S		 2937 pci_set_drvdata(pdev, ae_dev);
2938
74354140 2939 ret = hnae3_register_ae_dev(ae_dev);
674a1357 2940 if (ret)
74354140 2941 pci_set_drvdata(pdev, NULL);
2312e050 2942
74354140 2943 return ret;
76ad4f0e
S		 2944}
2945
2946/* hns3_remove - Device removal routine
2947 * @pdev: PCI device information struct
2948 */
2949static void hns3_remove(struct pci_dev *pdev)
2950{
2951 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2952
2312e050
FL		 2953 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2954 hns3_disable_sriov(pdev);
2955
76ad4f0e 2956 hnae3_unregister_ae_dev(ae_dev);
ac864c23 2957 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 2958}
2959
fa8d82e8
PL		 2960/**
2961 * hns3_pci_sriov_configure
2962 * @pdev: pointer to a pci_dev structure
2963 * @num_vfs: number of VFs to allocate
2964 *
2965 * Enable or change the number of VFs. Called when the user updates the number
2966 * of VFs in sysfs.
2967 **/
743e1a84 2968static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 2969{
2970 int ret;
2971
2972 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2973 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2974 return -EINVAL;
2975 }
2976
2977 if (num_vfs) {
2978 ret = pci_enable_sriov(pdev, num_vfs);
2979 if (ret)
2980 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 2981 else
2982 return num_vfs;
fa8d82e8
PL		 2983 } else if (!pci_vfs_assigned(pdev)) {
2984 pci_disable_sriov(pdev);
2985 } else {
2986 dev_warn(&pdev->dev,
2987 "Unable to free VFs because some are assigned to VMs.\n");
2988 }
2989
2990 return 0;
2991}
2992
ce2c1d2e
YL		 2993static void hns3_shutdown(struct pci_dev *pdev)
2994{
2995 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2996
2997 hnae3_unregister_ae_dev(ae_dev);
ce2c1d2e
YL		 2998 pci_set_drvdata(pdev, NULL);
2999
3000 if (system_state == SYSTEM_POWER_OFF)
3001 pci_set_power_state(pdev, PCI_D3hot);
3002}
3003
715c58e9
JZ		 3004static int __maybe_unused hns3_suspend(struct device *dev)
3005{
3006 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3007
d0494135 3008 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
715c58e9 3009 dev_info(dev, "Begin to suspend.\n");
d0494135 3010 if (ae_dev->ops && ae_dev->ops->reset_prepare)
715c58e9
JZ		 3011 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3012 }
3013
3014 return 0;
3015}
3016
3017static int __maybe_unused hns3_resume(struct device *dev)
3018{
3019 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3020
d0494135 3021 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
715c58e9 3022 dev_info(dev, "Begin to resume.\n");
d0494135 3023 if (ae_dev->ops && ae_dev->ops->reset_done)
715c58e9
JZ		 3024 ae_dev->ops->reset_done(ae_dev);
3025 }
3026
3027 return 0;
3028}
3029
5a9f0eac
SJ		 3030static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3031 pci_channel_state_t state)
3032{
3033 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3034 pci_ers_result_t ret;
3035
c5aaf176 3036 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
5a9f0eac
SJ		 3037
3038 if (state == pci_channel_io_perm_failure)
3039 return PCI_ERS_RESULT_DISCONNECT;
3040
661262bc 3041 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 3042 dev_err(&pdev->dev,
661262bc 3043 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ		 3044 return PCI_ERS_RESULT_NONE;
3045 }
3046
381c356e
SJ		 3047 if (ae_dev->ops->handle_hw_ras_error)
3048 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 3049 else
3050 return PCI_ERS_RESULT_NONE;
3051
3052 return ret;
3053}
3054
6ae4e733
SJ		 3055static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3056{
3057 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 3058 const struct hnae3_ae_ops *ops;
123297b7 3059 enum hnae3_reset_type reset_type;
6ae4e733
SJ		 3060 struct device *dev = &pdev->dev;
3061
661262bc
WL		 3062 if (!ae_dev || !ae_dev->ops)
3063 return PCI_ERS_RESULT_NONE;
3064
ad9bf545 3065 ops = ae_dev->ops;
6ae4e733 3066 /* request the reset */
fa17c708
GH		 3067 if (ops->reset_event && ops->get_reset_level &&
3068 ops->set_default_reset_request) {
9d5e67d1 3069 if (ae_dev->hw_err_reset_req) {
123297b7
SJ		 3070 reset_type = ops->get_reset_level(ae_dev,
3071 &ae_dev->hw_err_reset_req);
3072 ops->set_default_reset_request(ae_dev, reset_type);
3073 dev_info(dev, "requesting reset due to PCI error\n");
3074 ops->reset_event(pdev, NULL);
3075 }
69b51bbb 3076
6ae4e733
SJ		 3077 return PCI_ERS_RESULT_RECOVERED;
3078 }
3079
3080 return PCI_ERS_RESULT_DISCONNECT;
3081}
3082
6b9a97ee
HT		 3083static void hns3_reset_prepare(struct pci_dev *pdev)
3084{
3085 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3086
8de91e92 3087 dev_info(&pdev->dev, "FLR prepare\n");
bb1890d5
JZ		 3088 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3089 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
6b9a97ee
HT		 3090}
3091
3092static void hns3_reset_done(struct pci_dev *pdev)
3093{
3094 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3095
8de91e92 3096 dev_info(&pdev->dev, "FLR done\n");
bb1890d5
JZ		 3097 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3098 ae_dev->ops->reset_done(ae_dev);
6b9a97ee
HT		 3099}
3100
5a9f0eac
SJ		 3101static const struct pci_error_handlers hns3_err_handler = {
3102 .error_detected = hns3_error_detected,
6ae4e733 3103 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 3104 .reset_prepare = hns3_reset_prepare,
3105 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 3106};
3107
715c58e9
JZ		 3108static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3109
76ad4f0e
S		 3110static struct pci_driver hns3_driver = {
3111 .name = hns3_driver_name,
3112 .id_table = hns3_pci_tbl,
3113 .probe = hns3_probe,
3114 .remove = hns3_remove,
ce2c1d2e 3115 .shutdown = hns3_shutdown,
715c58e9 3116 .driver.pm = &hns3_pm_ops,
fa8d82e8 3117 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 3118 .err_handler = &hns3_err_handler,
76ad4f0e
S		 3119};
3120
3121/* set default feature to hns3 */
3122static void hns3_set_default_feature(struct net_device *netdev)
3123{
3e85af6a
PL		 3124 struct hnae3_handle *h = hns3_get_handle(netdev);
3125 struct pci_dev *pdev = h->pdev;
295ba232 3126 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3e85af6a 3127
76ad4f0e
S		 3128 netdev->priv_flags |= IFF_UNICAST_FLT;
3129
66d52f3b 3130 netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
76ad4f0e
S		 3131 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3132 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 3133 NETIF_F_SCTP_CRC | NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
76ad4f0e
S		 3134
3135 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
3136
66d52f3b 3137 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 3138 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 3139 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3140 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3141 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 3142 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
76ad4f0e 3143
66d52f3b 3144 netdev->vlan_features |= NETIF_F_RXCSUM |
76ad4f0e
S		 3145 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
3146 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3147 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 3148 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
76ad4f0e 3149
66d52f3b
HT		 3150 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3151 NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 3152 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3153 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3154 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 3155 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3e85af6a 3156
295ba232 3157 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
77af09c6 3158 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 3159 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 3160
3161 if (!(h->flags & HNAE3_SUPPORT_VF)) {
3162 netdev->hw_features |= NETIF_F_NTUPLE;
3163 netdev->features |= NETIF_F_NTUPLE;
3164 }
3165 }
0692cfe9
HT		 3166
3167 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) {
3168 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
3169 netdev->features |= NETIF_F_GSO_UDP_L4;
3170 netdev->vlan_features |= NETIF_F_GSO_UDP_L4;
3171 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4;
3172 }
66d52f3b
HT		 3173
3174 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) {
3175 netdev->hw_features |= NETIF_F_HW_CSUM;
3176 netdev->features |= NETIF_F_HW_CSUM;
3177 netdev->vlan_features |= NETIF_F_HW_CSUM;
3178 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
3179 } else {
3180 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3181 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3182 netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3183 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3184 }
3e281621
HT		 3185
3186 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) {
3187 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3188 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3189 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3190 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3191 }
0205ec04
JS		 3192
3193 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) {
3194 netdev->hw_features |= NETIF_F_HW_TC;
3195 netdev->features |= NETIF_F_HW_TC;
3196 }
2ba30662
JS		 3197
3198 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3199 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
76ad4f0e
S		 3200}
3201
3202static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3203 struct hns3_desc_cb *cb)
3204{
dbba6da0 3205 unsigned int order = hns3_page_order(ring);
76ad4f0e
S		 3206 struct page *p;
3207
3208 p = dev_alloc_pages(order);
3209 if (!p)
3210 return -ENOMEM;
3211
3212 cb->priv = p;
3213 cb->page_offset = 0;
3214 cb->reuse_flag = 0;
3215 cb->buf = page_address(p);
dbba6da0 3216 cb->length = hns3_page_size(ring);
76ad4f0e 3217 cb->type = DESC_TYPE_PAGE;
aeda9bf8
YL		 3218 page_ref_add(p, USHRT_MAX - 1);
3219 cb->pagecnt_bias = USHRT_MAX;
76ad4f0e 3220
76ad4f0e
S		 3221 return 0;
3222}
3223
3224static void hns3_free_buffer(struct hns3_enet_ring *ring,
619ae331 3225 struct hns3_desc_cb *cb, int budget)
76ad4f0e 3226{
907676b1 3227 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
7459775e 3228 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
619ae331 3229 napi_consume_skb(cb->priv, budget);
aeda9bf8
YL		 3230 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias)
3231 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
76ad4f0e
S		 3232 memset(cb, 0, sizeof(*cb));
3233}
3234
3235static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3236{
3237 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3238 cb->length, ring_to_dma_dir(ring));
3239
2211f4e1 3240 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 3241 return -EIO;
3242
3243 return 0;
3244}
3245
3246static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3247 struct hns3_desc_cb *cb)
3248{
26f1ccdf 3249 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
76ad4f0e
S		 3250 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3251 ring_to_dma_dir(ring));
907676b1 3252 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
76ad4f0e
S		 3253 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3254 ring_to_dma_dir(ring));
7459775e
YL		 3255 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3256 DESC_TYPE_SGL_SKB))
907676b1 3257 hns3_tx_spare_reclaim_cb(ring, cb);
76ad4f0e
S		 3258}
3259
3260static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3261{
3262 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3263 ring->desc[i].addr = 0;
3264}
3265
619ae331
YL		 3266static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3267 int budget)
76ad4f0e
S		 3268{
3269 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3270
3271 if (!ring->desc_cb[i].dma)
3272 return;
3273
3274 hns3_buffer_detach(ring, i);
619ae331 3275 hns3_free_buffer(ring, cb, budget);
76ad4f0e
S		 3276}
3277
3278static void hns3_free_buffers(struct hns3_enet_ring *ring)
3279{
3280 int i;
3281
3282 for (i = 0; i < ring->desc_num; i++)
619ae331 3283 hns3_free_buffer_detach(ring, i, 0);
76ad4f0e
S		 3284}
3285
3286/* free desc along with its attached buffer */
3287static void hns3_free_desc(struct hns3_enet_ring *ring)
3288{
024cc792
HT		 3289 int size = ring->desc_num * sizeof(ring->desc[0]);
3290
76ad4f0e
S		 3291 hns3_free_buffers(ring);
3292
024cc792
HT		 3293 if (ring->desc) {
3294 dma_free_coherent(ring_to_dev(ring), size,
3295 ring->desc, ring->desc_dma_addr);
3296 ring->desc = NULL;
3297 }
76ad4f0e
S		 3298}
3299
3300static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3301{
3302 int size = ring->desc_num * sizeof(ring->desc[0]);
3303
750afb08
LC		 3304 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3305 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 3306 if (!ring->desc)
3307 return -ENOMEM;
3308
76ad4f0e
S		 3309 return 0;
3310}
3311
4d2cad32 3312static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
76ad4f0e
S		 3313 struct hns3_desc_cb *cb)
3314{
3315 int ret;
3316
3317 ret = hns3_alloc_buffer(ring, cb);
3318 if (ret)
3319 goto out;
3320
3321 ret = hns3_map_buffer(ring, cb);
3322 if (ret)
3323 goto out_with_buf;
3324
3325 return 0;
3326
3327out_with_buf:
619ae331 3328 hns3_free_buffer(ring, cb, 0);
76ad4f0e
S		 3329out:
3330 return ret;
3331}
3332
4d2cad32 3333static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
76ad4f0e 3334{
4d2cad32 3335 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 3336
3337 if (ret)
3338 return ret;
3339
3340 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
3341
3342 return 0;
3343}
3344
3345/* Allocate memory for raw pkg, and map with dma */
3346static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3347{
3348 int i, j, ret;
3349
3350 for (i = 0; i < ring->desc_num; i++) {
4d2cad32 3351 ret = hns3_alloc_and_attach_buffer(ring, i);
76ad4f0e
S		 3352 if (ret)
3353 goto out_buffer_fail;
3354 }
3355
3356 return 0;
3357
3358out_buffer_fail:
3359 for (j = i - 1; j >= 0; j--)
619ae331 3360 hns3_free_buffer_detach(ring, j, 0);
76ad4f0e
S		 3361 return ret;
3362}
3363
9b2f3477 3364/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S		 3365static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3366 struct hns3_desc_cb *res_cb)
3367{
b9077428 3368 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 3369 ring->desc_cb[i] = *res_cb;
3370 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 3371 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 3372}
3373
3374static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3375{
3376 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL		 3377 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3378 ring->desc_cb[i].page_offset);
7d0b130c 3379 ring->desc[i].rx.bd_base_info = 0;
c2a2e127
BS		 3380
3381 dma_sync_single_for_device(ring_to_dev(ring),
3382 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3383 hns3_buf_size(ring),
3384 DMA_FROM_DEVICE);
76ad4f0e
S		 3385}
3386
20d06ca2 3387static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
619ae331 3388 int *bytes, int *pkts, int budget)
76ad4f0e 3389{
20d06ca2
YL		 3390 /* pair with ring->last_to_use update in hns3_tx_doorbell(),
3391 * smp_store_release() is not used in hns3_tx_doorbell() because
3392 * the doorbell operation already have the needed barrier operation.
3393 */
3394 int ltu = smp_load_acquire(&ring->last_to_use);
26cda2f1
YL		 3395 int ntc = ring->next_to_clean;
3396 struct hns3_desc_cb *desc_cb;
20d06ca2
YL		 3397 bool reclaimed = false;
3398 struct hns3_desc *desc;
3399
3400 while (ltu != ntc) {
3401 desc = &ring->desc[ntc];
3402
3403 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3404 BIT(HNS3_TXD_VLD_B))
3405 break;
76ad4f0e 3406
ce74370c 3407 desc_cb = &ring->desc_cb[ntc];
811c0830 3408
907676b1 3409 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
7459775e
YL		 3410 DESC_TYPE_BOUNCE_HEAD |
3411 DESC_TYPE_SGL_SKB)) {
811c0830
YL		 3412 (*pkts)++;
3413 (*bytes) += desc_cb->send_bytes;
3414 }
3415
ce74370c 3416 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
619ae331 3417 hns3_free_buffer_detach(ring, ntc, budget);
76ad4f0e 3418
ce74370c
YL		 3419 if (++ntc == ring->desc_num)
3420 ntc = 0;
3421
3422 /* Issue prefetch for next Tx descriptor */
3423 prefetch(&ring->desc_cb[ntc]);
20d06ca2 3424 reclaimed = true;
ce74370c 3425 }
26cda2f1 3426
20d06ca2
YL		 3427 if (unlikely(!reclaimed))
3428 return false;
3429
26cda2f1
YL		 3430 /* This smp_store_release() pairs with smp_load_acquire() in
3431 * ring_space called by hns3_nic_net_xmit.
3432 */
3433 smp_store_release(&ring->next_to_clean, ntc);
907676b1
YL		 3434
3435 hns3_tx_spare_update(ring);
3436
20d06ca2 3437 return true;
76ad4f0e
S		 3438}
3439
619ae331 3440void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
76ad4f0e 3441{
c8711956 3442 struct net_device *netdev = ring_to_netdev(ring);
7a810110 3443 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 3444 struct netdev_queue *dev_queue;
3445 int bytes, pkts;
76ad4f0e
S		 3446
3447 bytes = 0;
3448 pkts = 0;
20d06ca2 3449
619ae331 3450 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
20d06ca2 3451 return;
76ad4f0e
S		 3452
3453 ring->tqp_vector->tx_group.total_bytes += bytes;
3454 ring->tqp_vector->tx_group.total_packets += pkts;
3455
3456 u64_stats_update_begin(&ring->syncp);
3457 ring->stats.tx_bytes += bytes;
3458 ring->stats.tx_pkts += pkts;
3459 u64_stats_update_end(&ring->syncp);
3460
3461 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3462 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3463
2a597eff 3464 if (unlikely(netif_carrier_ok(netdev) &&
8ae10cfb 3465 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
76ad4f0e
S		 3466 /* Make sure that anybody stopping the queue after this
3467 * sees the new next_to_clean.
3468 */
3469 smp_mb();
7a810110
JS		 3470 if (netif_tx_queue_stopped(dev_queue) &&
3471 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 3472 netif_tx_wake_queue(dev_queue);
3473 ring->stats.restart_queue++;
3474 }
3475 }
76ad4f0e
S		 3476}
3477
3478static int hns3_desc_unused(struct hns3_enet_ring *ring)
3479{
3480 int ntc = ring->next_to_clean;
3481 int ntu = ring->next_to_use;
3482
3483 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3484}
3485
9b2f3477
WL		 3486static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3487 int cleand_count)
76ad4f0e
S		 3488{
3489 struct hns3_desc_cb *desc_cb;
3490 struct hns3_desc_cb res_cbs;
3491 int i, ret;
3492
3493 for (i = 0; i < cleand_count; i++) {
3494 desc_cb = &ring->desc_cb[ring->next_to_use];
3495 if (desc_cb->reuse_flag) {
3496 u64_stats_update_begin(&ring->syncp);
3497 ring->stats.reuse_pg_cnt++;
3498 u64_stats_update_end(&ring->syncp);
3499
3500 hns3_reuse_buffer(ring, ring->next_to_use);
3501 } else {
4d2cad32 3502 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
76ad4f0e
S		 3503 if (ret) {
3504 u64_stats_update_begin(&ring->syncp);
3505 ring->stats.sw_err_cnt++;
3506 u64_stats_update_end(&ring->syncp);
3507
c8711956 3508 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5
YL		 3509 "alloc rx buffer failed: %d\n",
3510 ret);
76ad4f0e
S		 3511 break;
3512 }
3513 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 3514
3515 u64_stats_update_begin(&ring->syncp);
3516 ring->stats.non_reuse_pg++;
3517 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 3518 }
3519
3520 ring_ptr_move_fw(ring, next_to_use);
3521 }
3522
48ee56fd 3523 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
76ad4f0e
S		 3524}
3525
aeda9bf8
YL		 3526static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3527{
3528 return (page_count(cb->priv) - cb->pagecnt_bias) == 1;
3529}
3530
76ad4f0e
S		 3531static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3532 struct hns3_enet_ring *ring, int pull_len,
3533 struct hns3_desc_cb *desc_cb)
3534{
389ca146
YL		 3535 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3536 int size = le16_to_cpu(desc->rx.size);
dbba6da0 3537 u32 truesize = hns3_buf_size(ring);
76ad4f0e 3538
aeda9bf8 3539 desc_cb->pagecnt_bias--;
76ad4f0e 3540 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 3541 size - pull_len, truesize);
76ad4f0e 3542
a79afa78
AL		 3543 /* Avoid re-using remote and pfmemalloc pages, or the stack is still
3544 * using the page when page_offset rollback to zero, flag default
3545 * unreuse
389ca146 3546 */
a79afa78 3547 if (!dev_page_is_reusable(desc_cb->priv) ||
aeda9bf8
YL		 3548 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) {
3549 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
76ad4f0e 3550 return;
aeda9bf8 3551 }
76ad4f0e
S		 3552
3553 /* Move offset up to the next cache line */
3554 desc_cb->page_offset += truesize;
3555
dbba6da0 3556 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
76ad4f0e 3557 desc_cb->reuse_flag = 1;
aeda9bf8 3558 } else if (hns3_can_reuse_page(desc_cb)) {
389ca146
YL		 3559 desc_cb->reuse_flag = 1;
3560 desc_cb->page_offset = 0;
aeda9bf8
YL		 3561 } else if (desc_cb->pagecnt_bias) {
3562 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3563 return;
3564 }
3565
3566 if (unlikely(!desc_cb->pagecnt_bias)) {
3567 page_ref_add(desc_cb->priv, USHRT_MAX);
3568 desc_cb->pagecnt_bias = USHRT_MAX;
76ad4f0e
S		 3569 }
3570}
3571
e2ee1c5a 3572static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL		 3573{
3574 __be16 type = skb->protocol;
3575 struct tcphdr *th;
3576 int depth = 0;
3577
e2ee1c5a 3578 while (eth_type_vlan(type)) {
d474d88f
YL		 3579 struct vlan_hdr *vh;
3580
3581 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3582 return -EFAULT;
3583
3584 vh = (struct vlan_hdr *)(skb->data + depth);
3585 type = vh->h_vlan_encapsulated_proto;
3586 depth += VLAN_HLEN;
3587 }
3588
e2ee1c5a
YL		 3589 skb_set_network_header(skb, depth);
3590
d474d88f 3591 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL		 3592 const struct iphdr *iph = ip_hdr(skb);
3593
d474d88f 3594 depth += sizeof(struct iphdr);
e2ee1c5a
YL		 3595 skb_set_transport_header(skb, depth);
3596 th = tcp_hdr(skb);
3597 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3598 iph->daddr, 0);
d474d88f 3599 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL		 3600 const struct ipv6hdr *iph = ipv6_hdr(skb);
3601
d474d88f 3602 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL		 3603 skb_set_transport_header(skb, depth);
3604 th = tcp_hdr(skb);
3605 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3606 &iph->daddr, 0);
d474d88f 3607 } else {
b20d7fe5
YL		 3608 hns3_rl_err(skb->dev,
3609 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3610 be16_to_cpu(type), depth);
d474d88f
YL		 3611 return -EFAULT;
3612 }
3613
d474d88f
YL		 3614 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3615 if (th->cwr)
3616 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3617
e2ee1c5a
YL		 3618 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3619 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 3620
e2ee1c5a
YL		 3621 skb->csum_start = (unsigned char *)th - skb->head;
3622 skb->csum_offset = offsetof(struct tcphdr, check);
3623 skb->ip_summed = CHECKSUM_PARTIAL;
698a8954
YL		 3624
3625 trace_hns3_gro(skb);
3626
d474d88f
YL		 3627 return 0;
3628}
3629
1ddc028a
HT		 3630static bool hns3_checksum_complete(struct hns3_enet_ring *ring,
3631 struct sk_buff *skb, u32 ptype, u16 csum)
4b2fe769 3632{
1ddc028a
HT		 3633 if (ptype == HNS3_INVALID_PTYPE ||
3634 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3635 return false;
4b2fe769
HT		 3636
3637 u64_stats_update_begin(&ring->syncp);
3638 ring->stats.csum_complete++;
3639 u64_stats_update_end(&ring->syncp);
3640 skb->ip_summed = CHECKSUM_COMPLETE;
1ddc028a
HT		 3641 skb->csum = csum_unfold((__force __sum16)csum);
3642
3643 return true;
4b2fe769
HT		 3644}
3645
79664077
HT		 3646static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3647 u32 ol_info, u32 ptype)
76ad4f0e 3648{
76ad4f0e 3649 int l3_type, l4_type;
76ad4f0e 3650 int ol4_type;
76ad4f0e 3651
79664077
HT		 3652 if (ptype != HNS3_INVALID_PTYPE) {
3653 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3654 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
76ad4f0e
S		 3655
3656 return;
3657 }
3658
39c38824 3659 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 3660 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 3661 switch (ol4_type) {
3662 case HNS3_OL4_TYPE_MAC_IN_UDP:
3663 case HNS3_OL4_TYPE_NVGRE:
3664 skb->csum_level = 1;
df561f66 3665 fallthrough;
76ad4f0e 3666 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 3667 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3668 HNS3_RXD_L3ID_S);
3669 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3670 HNS3_RXD_L4ID_S);
76ad4f0e 3671 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 3672 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3673 l3_type == HNS3_L3_TYPE_IPV6) &&
3674 (l4_type == HNS3_L4_TYPE_UDP ||
3675 l4_type == HNS3_L4_TYPE_TCP ||
3676 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 3677 skb->ip_summed = CHECKSUM_UNNECESSARY;
3678 break;
fa7a4bd5
JS		 3679 default:
3680 break;
76ad4f0e
S		 3681 }
3682}
3683
79664077 3684static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
1ddc028a
HT		 3685 u32 l234info, u32 bd_base_info, u32 ol_info,
3686 u16 csum)
79664077
HT		 3687{
3688 struct net_device *netdev = ring_to_netdev(ring);
3689 struct hns3_nic_priv *priv = netdev_priv(netdev);
3690 u32 ptype = HNS3_INVALID_PTYPE;
3691
3692 skb->ip_summed = CHECKSUM_NONE;
3693
3694 skb_checksum_none_assert(skb);
3695
3696 if (!(netdev->features & NETIF_F_RXCSUM))
3697 return;
3698
3699 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3700 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3701 HNS3_RXD_PTYPE_S);
3702
1ddc028a 3703 if (hns3_checksum_complete(ring, skb, ptype, csum))
79664077 3704 return;
79664077
HT		 3705
3706 /* check if hardware has done checksum */
3707 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3708 return;
3709
3710 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3711 BIT(HNS3_RXD_OL3E_B) |
3712 BIT(HNS3_RXD_OL4E_B)))) {
3713 u64_stats_update_begin(&ring->syncp);
3714 ring->stats.l3l4_csum_err++;
3715 u64_stats_update_end(&ring->syncp);
3716
3717 return;
3718 }
3719
3720 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3721}
3722
d43e5aca
YL		 3723static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3724{
81ae0e04
PL		 3725 if (skb_has_frag_list(skb))
3726 napi_gro_flush(&ring->tqp_vector->napi, false);
3727
d43e5aca
YL		 3728 napi_gro_receive(&ring->tqp_vector->napi, skb);
3729}
3730
701a6d6a
JS		 3731static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3732 struct hns3_desc *desc, u32 l234info,
3733 u16 *vlan_tag)
5b5455a9 3734{
44e626f7 3735 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 3736 struct pci_dev *pdev = ring->tqp->handle->pdev;
295ba232 3737 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5b5455a9 3738
295ba232 3739 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
701a6d6a
JS		 3740 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3741 if (!(*vlan_tag & VLAN_VID_MASK))
3742 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 3743
701a6d6a 3744 return (*vlan_tag != 0);
5b5455a9
PL		 3745 }
3746
3747#define HNS3_STRP_OUTER_VLAN 0x1
3748#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 3749#define HNS3_STRP_BOTH 0x3
5b5455a9 3750
44e626f7
JS		 3751 /* Hardware always insert VLAN tag into RX descriptor when
3752 * remove the tag from packet, driver needs to determine
3753 * reporting which tag to stack.
3754 */
e4e87715
PL		 3755 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3756 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 3757 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 3758 if (handle->port_base_vlan_state !=
3759 HNAE3_PORT_BASE_VLAN_DISABLE)
3760 return false;
3761
701a6d6a
JS		 3762 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3763 return true;
5b5455a9 3764 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 3765 if (handle->port_base_vlan_state !=
3766 HNAE3_PORT_BASE_VLAN_DISABLE)
3767 return false;
3768
701a6d6a 3769 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 3770 return true;
3771 case HNS3_STRP_BOTH:
3772 if (handle->port_base_vlan_state ==
3773 HNAE3_PORT_BASE_VLAN_DISABLE)
3774 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3775 else
3776 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3777
701a6d6a 3778 return true;
5b5455a9 3779 default:
701a6d6a 3780 return false;
5b5455a9 3781 }
5b5455a9
PL		 3782}
3783
8c30e194
YL		 3784static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
3785{
3786 ring->desc[ring->next_to_clean].rx.bd_base_info &=
3787 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
3788 ring->next_to_clean += 1;
3789
3790 if (unlikely(ring->next_to_clean == ring->desc_num))
3791 ring->next_to_clean = 0;
3792}
3793
b9a8f883 3794static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL		 3795 unsigned char *va)
3796{
e5597095 3797 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
c8711956 3798 struct net_device *netdev = ring_to_netdev(ring);
e5597095
PL		 3799 struct sk_buff *skb;
3800
3801 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
3802 skb = ring->skb;
3803 if (unlikely(!skb)) {
b20d7fe5 3804 hns3_rl_err(netdev, "alloc rx skb fail\n");
e5597095
PL		 3805
3806 u64_stats_update_begin(&ring->syncp);
3807 ring->stats.sw_err_cnt++;
3808 u64_stats_update_end(&ring->syncp);
3809
3810 return -ENOMEM;
3811 }
3812
698a8954 3813 trace_hns3_rx_desc(ring);
e5597095
PL		 3814 prefetchw(skb->data);
3815
3816 ring->pending_buf = 1;
81ae0e04
PL		 3817 ring->frag_num = 0;
3818 ring->tail_skb = NULL;
e5597095
PL		 3819 if (length <= HNS3_RX_HEAD_SIZE) {
3820 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
3821
a79afa78
AL		 3822 /* We can reuse buffer as-is, just make sure it is reusable */
3823 if (dev_page_is_reusable(desc_cb->priv))
e5597095
PL		 3824 desc_cb->reuse_flag = 1;
3825 else /* This page cannot be reused so discard it */
aeda9bf8
YL		 3826 __page_frag_cache_drain(desc_cb->priv,
3827 desc_cb->pagecnt_bias);
e5597095 3828
8c30e194 3829 hns3_rx_ring_move_fw(ring);
e5597095
PL		 3830 return 0;
3831 }
3832 u64_stats_update_begin(&ring->syncp);
3833 ring->stats.seg_pkt_cnt++;
3834 u64_stats_update_end(&ring->syncp);
3835
c43f1255 3836 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 3837 __skb_put(skb, ring->pull_len);
81ae0e04 3838 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095 3839 desc_cb);
8c30e194 3840 hns3_rx_ring_move_fw(ring);
e5597095 3841
b2598318 3842 return 0;
e5597095
PL		 3843}
3844
b2598318 3845static int hns3_add_frag(struct hns3_enet_ring *ring)
e5597095 3846{
d35bced8
YL		 3847 struct sk_buff *skb = ring->skb;
3848 struct sk_buff *head_skb = skb;
81ae0e04 3849 struct sk_buff *new_skb;
e5597095 3850 struct hns3_desc_cb *desc_cb;
b2598318 3851 struct hns3_desc *desc;
e5597095 3852 u32 bd_base_info;
e5597095 3853
b2598318 3854 do {
e5597095
PL		 3855 desc = &ring->desc[ring->next_to_clean];
3856 desc_cb = &ring->desc_cb[ring->next_to_clean];
3857 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 3858 /* make sure HW write desc complete */
3859 dma_rmb();
e8149933 3860 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 3861 return -ENXIO;
3862
81ae0e04 3863 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
7fda3a93 3864 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
81ae0e04 3865 if (unlikely(!new_skb)) {
c8711956 3866 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5 3867 "alloc rx fraglist skb fail\n");
81ae0e04
PL		 3868 return -ENXIO;
3869 }
3870 ring->frag_num = 0;
3871
3872 if (ring->tail_skb) {
3873 ring->tail_skb->next = new_skb;
3874 ring->tail_skb = new_skb;
3875 } else {
3876 skb_shinfo(skb)->frag_list = new_skb;
3877 ring->tail_skb = new_skb;
3878 }
3879 }
3880
3881 if (ring->tail_skb) {
dbba6da0 3882 head_skb->truesize += hns3_buf_size(ring);
81ae0e04
PL		 3883 head_skb->data_len += le16_to_cpu(desc->rx.size);
3884 head_skb->len += le16_to_cpu(desc->rx.size);
3885 skb = ring->tail_skb;
3886 }
3887
c2a2e127
BS		 3888 dma_sync_single_for_cpu(ring_to_dev(ring),
3889 desc_cb->dma + desc_cb->page_offset,
3890 hns3_buf_size(ring),
3891 DMA_FROM_DEVICE);
3892
81ae0e04 3893 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
698a8954 3894 trace_hns3_rx_desc(ring);
8c30e194 3895 hns3_rx_ring_move_fw(ring);
e5597095 3896 ring->pending_buf++;
b2598318 3897 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
e5597095
PL		 3898
3899 return 0;
3900}
3901
d474d88f
YL		 3902static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
3903 struct sk_buff *skb, u32 l234info,
1ddc028a 3904 u32 bd_base_info, u32 ol_info, u16 csum)
a6d53b97 3905{
79664077
HT		 3906 struct net_device *netdev = ring_to_netdev(ring);
3907 struct hns3_nic_priv *priv = netdev_priv(netdev);
a6d53b97
PL		 3908 u32 l3_type;
3909
e2ee1c5a
YL		 3910 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
3911 HNS3_RXD_GRO_SIZE_M,
3912 HNS3_RXD_GRO_SIZE_S);
a6d53b97 3913 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 3914 if (!skb_shinfo(skb)->gso_size) {
1ddc028a
HT		 3915 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
3916 csum);
d474d88f
YL		 3917 return 0;
3918 }
a6d53b97 3919
e2ee1c5a
YL		 3920 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
3921 HNS3_RXD_GRO_COUNT_M,
3922 HNS3_RXD_GRO_COUNT_S);
a6d53b97 3923
79664077
HT		 3924 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
3925 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3926 HNS3_RXD_PTYPE_S);
3927
3928 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
3929 } else {
3930 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3931 HNS3_RXD_L3ID_S);
3932 }
3933
a6d53b97
PL		 3934 if (l3_type == HNS3_L3_TYPE_IPV4)
3935 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
3936 else if (l3_type == HNS3_L3_TYPE_IPV6)
3937 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
3938 else
d474d88f 3939 return -EFAULT;
a6d53b97 3940
e2ee1c5a 3941 return hns3_gro_complete(skb, l234info);
a6d53b97
PL		 3942}
3943
232fc64b 3944static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 3945 struct sk_buff *skb, u32 rss_hash)
232fc64b 3946{
232fc64b
PL		 3947 struct hnae3_handle *handle = ring->tqp->handle;
3948 enum pkt_hash_types rss_type;
3949
ea485867 3950 if (rss_hash)
232fc64b
PL		 3951 rss_type = handle->kinfo.rss_type;
3952 else
3953 rss_type = PKT_HASH_TYPE_NONE;
3954
ea485867 3955 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 3956}
3957
ea485867 3958static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e 3959{
c8711956 3960 struct net_device *netdev = ring_to_netdev(ring);
c376fa1a 3961 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 3962 u32 bd_base_info, l234info, ol_info;
ea485867 3963 struct hns3_desc *desc;
d474d88f 3964 unsigned int len;
ea485867 3965 int pre_ntc, ret;
1ddc028a 3966 u16 csum;
ea485867
YL		 3967
3968 /* bdinfo handled below is only valid on the last BD of the
3969 * current packet, and ring->next_to_clean indicates the first
3970 * descriptor of next packet, so need - 1 below.
3971 */
3972 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
3973 (ring->desc_num - 1);
3974 desc = &ring->desc[pre_ntc];
3975 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3976 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 3977 ol_info = le32_to_cpu(desc->rx.ol_info);
1ddc028a 3978 csum = le16_to_cpu(desc->csum);
d474d88f 3979
0bf5eb78
HT		 3980 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
3981 struct hnae3_handle *h = hns3_get_handle(netdev);
3982 u32 nsec = le32_to_cpu(desc->ts_nsec);
3983 u32 sec = le32_to_cpu(desc->ts_sec);
3984
3985 if (h->ae_algo->ops->get_rx_hwts)
3986 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
3987 }
3988
d474d88f
YL		 3989 /* Based on hw strategy, the tag offloaded will be stored at
3990 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
3991 * in one layer tag case.
3992 */
3993 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3994 u16 vlan_tag;
3995
3996 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
3997 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3998 vlan_tag);
3999 }
4000
d474d88f
YL		 4001 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4002 BIT(HNS3_RXD_L2E_B))))) {
4003 u64_stats_update_begin(&ring->syncp);
4004 if (l234info & BIT(HNS3_RXD_L2E_B))
4005 ring->stats.l2_err++;
4006 else
4007 ring->stats.err_pkt_len++;
4008 u64_stats_update_end(&ring->syncp);
4009
4010 return -EFAULT;
4011 }
4012
4013 len = skb->len;
4014
4015 /* Do update ip stack process */
4016 skb->protocol = eth_type_trans(skb, netdev);
4017
4018 /* This is needed in order to enable forwarding support */
39c38824 4019 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
1ddc028a 4020 bd_base_info, ol_info, csum);
d474d88f
YL		 4021 if (unlikely(ret)) {
4022 u64_stats_update_begin(&ring->syncp);
4023 ring->stats.rx_err_cnt++;
4024 u64_stats_update_end(&ring->syncp);
4025 return ret;
4026 }
4027
4028 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4029 HNS3_RXD_DMAC_S);
4030
4031 u64_stats_update_begin(&ring->syncp);
4032 ring->stats.rx_pkts++;
4033 ring->stats.rx_bytes += len;
4034
4035 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4036 ring->stats.rx_multicast++;
4037
4038 u64_stats_update_end(&ring->syncp);
4039
4040 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 4041
4042 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 4043 return 0;
4044}
4045
d35bced8 4046static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
d474d88f 4047{
e5597095 4048 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 4049 struct hns3_desc_cb *desc_cb;
4050 struct hns3_desc *desc;
b9a8f883 4051 unsigned int length;
76ad4f0e 4052 u32 bd_base_info;
e5597095 4053 int ret;
76ad4f0e
S		 4054
4055 desc = &ring->desc[ring->next_to_clean];
4056 desc_cb = &ring->desc_cb[ring->next_to_clean];
4057
4058 prefetch(desc);
4059
8c30e194
YL		 4060 if (!skb) {
4061 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
8c30e194
YL		 4062 /* Check valid BD */
4063 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4064 return -ENXIO;
4065
4066 dma_rmb();
4067 length = le16_to_cpu(desc->rx.size);
76ad4f0e 4068
cb0e3e61 4069 ring->va = desc_cb->buf + desc_cb->page_offset;
76ad4f0e 4070
c2a2e127
BS		 4071 dma_sync_single_for_cpu(ring_to_dev(ring),
4072 desc_cb->dma + desc_cb->page_offset,
4073 hns3_buf_size(ring),
4074 DMA_FROM_DEVICE);
c2a2e127 4075
8c30e194
YL		 4076 /* Prefetch first cache line of first page.
4077 * Idea is to cache few bytes of the header of the packet.
4078 * Our L1 Cache line size is 64B so need to prefetch twice to make
4079 * it 128B. But in actual we can have greater size of caches with
4080 * 128B Level 1 cache lines. In such a case, single fetch would
4081 * suffice to cache in the relevant part of the header.
4082 */
4083 net_prefetch(ring->va);
76ad4f0e 4084
e5597095 4085 ret = hns3_alloc_skb(ring, length, ring->va);
d35bced8 4086 skb = ring->skb;
76ad4f0e 4087
e5597095
PL		 4088 if (ret < 0) /* alloc buffer fail */
4089 return ret;
b2598318
YL		 4090 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4091 ret = hns3_add_frag(ring);
e5597095
PL		 4092 if (ret)
4093 return ret;
e5597095 4094 }
76ad4f0e 4095 } else {
b2598318 4096 ret = hns3_add_frag(ring);
e5597095
PL		 4097 if (ret)
4098 return ret;
b2598318 4099 }
76ad4f0e 4100
b2598318
YL		 4101 /* As the head data may be changed when GRO enable, copy
4102 * the head data in after other data rx completed
4103 */
4104 if (skb->len > HNS3_RX_HEAD_SIZE)
e5597095
PL		 4105 memcpy(skb->data, ring->va,
4106 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e 4107
ea485867 4108 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 4109 if (unlikely(ret)) {
76ad4f0e 4110 dev_kfree_skb_any(skb);
d474d88f 4111 return ret;
76ad4f0e
S		 4112 }
4113
d93ed94f 4114 skb_record_rx_queue(skb, ring->tqp->tqp_index);
76ad4f0e
S		 4115 return 0;
4116}
4117
9b2f3477
WL		 4118int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4119 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 4120{
4121#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
63380a1a 4122 int unused_count = hns3_desc_unused(ring);
a4ee7624 4123 int recv_pkts = 0;
8c30e194 4124 int err;
76ad4f0e 4125
63380a1a 4126 unused_count -= ring->pending_buf;
76ad4f0e 4127
8c30e194 4128 while (recv_pkts < budget) {
76ad4f0e 4129 /* Reuse or realloc buffers */
a4ee7624
YL		 4130 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4131 hns3_nic_alloc_rx_buffers(ring, unused_count);
e5597095
PL		 4132 unused_count = hns3_desc_unused(ring) -
4133 ring->pending_buf;
76ad4f0e
S		 4134 }
4135
4136 /* Poll one pkt */
d35bced8
YL		 4137 err = hns3_handle_rx_bd(ring);
4138 /* Do not get FE for the packet or failed to alloc skb */
4139 if (unlikely(!ring->skb || err == -ENXIO)) {
76ad4f0e 4140 goto out;
d35bced8
YL		 4141 } else if (likely(!err)) {
4142 rx_fn(ring, ring->skb);
4143 recv_pkts++;
76ad4f0e
S		 4144 }
4145
a4ee7624 4146 unused_count += ring->pending_buf;
e5597095
PL		 4147 ring->skb = NULL;
4148 ring->pending_buf = 0;
76ad4f0e
S		 4149 }
4150
4151out:
4152 /* Make all data has been write before submit */
a4ee7624
YL		 4153 if (unused_count > 0)
4154 hns3_nic_alloc_rx_buffers(ring, unused_count);
76ad4f0e
S		 4155
4156 return recv_pkts;
4157}
4158
307ea4ce 4159static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
76ad4f0e 4160{
307ea4ce
HT		 4161 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4162 struct dim_sample sample = {};
4a43caf5 4163
307ea4ce
HT		 4164 if (!rx_group->coal.adapt_enable)
4165 return;
76ad4f0e 4166
307ea4ce
HT		 4167 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4168 rx_group->total_bytes, &sample);
4169 net_dim(&rx_group->dim, sample);
76ad4f0e
S		 4170}
4171
307ea4ce 4172static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
76ad4f0e 4173{
8b1ff1ea 4174 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
307ea4ce 4175 struct dim_sample sample = {};
8b1ff1ea 4176
307ea4ce 4177 if (!tx_group->coal.adapt_enable)
cd9d187b 4178 return;
cd9d187b 4179
307ea4ce
HT		 4180 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4181 tx_group->total_bytes, &sample);
4182 net_dim(&tx_group->dim, sample);
76ad4f0e
S		 4183}
4184
4185static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4186{
ff0699e0 4187 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 4188 struct hns3_enet_ring *ring;
4189 int rx_pkt_total = 0;
4190
4191 struct hns3_enet_tqp_vector *tqp_vector =
4192 container_of(napi, struct hns3_enet_tqp_vector, napi);
4193 bool clean_complete = true;
ceca4a5e 4194 int rx_budget = budget;
76ad4f0e 4195
ff0699e0
HT		 4196 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4197 napi_complete(napi);
4198 return 0;
4199 }
4200
76ad4f0e
S		 4201 /* Since the actual Tx work is minimal, we can give the Tx a larger
4202 * budget and be more aggressive about cleaning up the Tx descriptors.
4203 */
799997a3 4204 hns3_for_each_ring(ring, tqp_vector->tx_group)
619ae331 4205 hns3_clean_tx_ring(ring, budget);
76ad4f0e
S		 4206
4207 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 4208 if (tqp_vector->num_tqps > 1)
4209 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 4210
4211 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 4212 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4213 hns3_rx_skb);
76ad4f0e
S		 4214 if (rx_cleaned >= rx_budget)
4215 clean_complete = false;
4216
4217 rx_pkt_total += rx_cleaned;
4218 }
4219
4220 tqp_vector->rx_group.total_packets += rx_pkt_total;
4221
4222 if (!clean_complete)
4223 return budget;
4224
531eba0f
HT		 4225 if (napi_complete(napi) &&
4226 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
307ea4ce
HT		 4227 hns3_update_rx_int_coalesce(tqp_vector);
4228 hns3_update_tx_int_coalesce(tqp_vector);
4229
ff0699e0
HT		 4230 hns3_mask_vector_irq(tqp_vector, 1);
4231 }
76ad4f0e
S		 4232
4233 return rx_pkt_total;
4234}
4235
4236static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4237 struct hnae3_ring_chain_node *head)
4238{
4239 struct pci_dev *pdev = tqp_vector->handle->pdev;
4240 struct hnae3_ring_chain_node *cur_chain = head;
4241 struct hnae3_ring_chain_node *chain;
4242 struct hns3_enet_ring *tx_ring;
4243 struct hns3_enet_ring *rx_ring;
4244
4245 tx_ring = tqp_vector->tx_group.ring;
4246 if (tx_ring) {
4247 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 4248 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4249 HNAE3_RING_TYPE_TX);
4250 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4251 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 4252
4253 cur_chain->next = NULL;
4254
4255 while (tx_ring->next) {
4256 tx_ring = tx_ring->next;
4257
4258 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
4259 GFP_KERNEL);
4260 if (!chain)
73b907a0 4261 goto err_free_chain;
76ad4f0e
S		 4262
4263 cur_chain->next = chain;
4264 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 4265 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4266 HNAE3_RING_TYPE_TX);
4267 hnae3_set_field(chain->int_gl_idx,
4268 HNAE3_RING_GL_IDX_M,
4269 HNAE3_RING_GL_IDX_S,
4270 HNAE3_RING_GL_TX);
76ad4f0e
S		 4271
4272 cur_chain = chain;
4273 }
4274 }
4275
4276 rx_ring = tqp_vector->rx_group.ring;
4277 if (!tx_ring && rx_ring) {
4278 cur_chain->next = NULL;
4279 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 4280 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4281 HNAE3_RING_TYPE_RX);
4282 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4283 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 4284
4285 rx_ring = rx_ring->next;
4286 }
4287
4288 while (rx_ring) {
4289 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4290 if (!chain)
73b907a0 4291 goto err_free_chain;
76ad4f0e
S		 4292
4293 cur_chain->next = chain;
4294 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 4295 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4296 HNAE3_RING_TYPE_RX);
4297 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4298 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 4299
76ad4f0e
S		 4300 cur_chain = chain;
4301
4302 rx_ring = rx_ring->next;
4303 }
4304
4305 return 0;
73b907a0
HT		 4306
4307err_free_chain:
4308 cur_chain = head->next;
4309 while (cur_chain) {
4310 chain = cur_chain->next;
cda69d24 4311 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 4312 cur_chain = chain;
4313 }
cda69d24 4314 head->next = NULL;
73b907a0
HT		 4315
4316 return -ENOMEM;
76ad4f0e
S		 4317}
4318
4319static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4320 struct hnae3_ring_chain_node *head)
4321{
4322 struct pci_dev *pdev = tqp_vector->handle->pdev;
4323 struct hnae3_ring_chain_node *chain_tmp, *chain;
4324
4325 chain = head->next;
4326
4327 while (chain) {
4328 chain_tmp = chain->next;
4329 devm_kfree(&pdev->dev, chain);
4330 chain = chain_tmp;
4331 }
4332}
4333
4334static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4335 struct hns3_enet_ring *ring)
4336{
4337 ring->next = group->ring;
4338 group->ring = ring;
4339
4340 group->count++;
4341}
4342
874bff0b
PL		 4343static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4344{
4345 struct pci_dev *pdev = priv->ae_handle->pdev;
4346 struct hns3_enet_tqp_vector *tqp_vector;
4347 int num_vectors = priv->vector_num;
4348 int numa_node;
4349 int vector_i;
4350
4351 numa_node = dev_to_node(&pdev->dev);
4352
4353 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4354 tqp_vector = &priv->tqp_vector[vector_i];
4355 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4356 &tqp_vector->affinity_mask);
4357 }
4358}
4359
307ea4ce
HT		 4360static void hns3_rx_dim_work(struct work_struct *work)
4361{
4362 struct dim *dim = container_of(work, struct dim, work);
4363 struct hns3_enet_ring_group *group = container_of(dim,
4364 struct hns3_enet_ring_group, dim);
4365 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4366 struct dim_cq_moder cur_moder =
4367 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4368
4369 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4370 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4371
4372 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4373 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4374 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4375 }
4376
4377 dim->state = DIM_START_MEASURE;
4378}
4379
4380static void hns3_tx_dim_work(struct work_struct *work)
4381{
4382 struct dim *dim = container_of(work, struct dim, work);
4383 struct hns3_enet_ring_group *group = container_of(dim,
4384 struct hns3_enet_ring_group, dim);
4385 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4386 struct dim_cq_moder cur_moder =
4387 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4388
4389 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4390 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4391
4392 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4393 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4394 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4395 }
4396
4397 dim->state = DIM_START_MEASURE;
4398}
4399
4400static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4401{
4402 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4403 tqp_vector->rx_group.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4404 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4405 tqp_vector->tx_group.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4406}
4407
76ad4f0e
S		 4408static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4409{
76ad4f0e
S		 4410 struct hnae3_handle *h = priv->ae_handle;
4411 struct hns3_enet_tqp_vector *tqp_vector;
9d8d5a36 4412 int ret;
ece4bf46 4413 int i;
76ad4f0e 4414
874bff0b
PL		 4415 hns3_nic_set_cpumask(priv);
4416
dd38c726
YL		 4417 for (i = 0; i < priv->vector_num; i++) {
4418 tqp_vector = &priv->tqp_vector[i];
91bfae25 4419 hns3_vector_coalesce_init_hw(tqp_vector, priv);
dd38c726 4420 tqp_vector->num_tqps = 0;
307ea4ce 4421 hns3_nic_init_dim(tqp_vector);
dd38c726 4422 }
76ad4f0e 4423
dd38c726
YL		 4424 for (i = 0; i < h->kinfo.num_tqps; i++) {
4425 u16 vector_i = i % priv->vector_num;
4426 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 4427
4428 tqp_vector = &priv->tqp_vector[vector_i];
4429
4430 hns3_add_ring_to_group(&tqp_vector->tx_group,
5f06b903 4431 &priv->ring[i]);
76ad4f0e
S		 4432
4433 hns3_add_ring_to_group(&tqp_vector->rx_group,
5f06b903 4434 &priv->ring[i + tqp_num]);
76ad4f0e 4435
5f06b903
YL		 4436 priv->ring[i].tqp_vector = tqp_vector;
4437 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
dd38c726 4438 tqp_vector->num_tqps++;
76ad4f0e
S		 4439 }
4440
dd38c726 4441 for (i = 0; i < priv->vector_num; i++) {
d392ecd1
SM		 4442 struct hnae3_ring_chain_node vector_ring_chain;
4443
76ad4f0e
S		 4444 tqp_vector = &priv->tqp_vector[i];
4445
4446 tqp_vector->rx_group.total_bytes = 0;
4447 tqp_vector->rx_group.total_packets = 0;
4448 tqp_vector->tx_group.total_bytes = 0;
4449 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 4450 tqp_vector->handle = h;
4451
4452 ret = hns3_get_vector_ring_chain(tqp_vector,
4453 &vector_ring_chain);
4454 if (ret)
cda69d24 4455 goto map_ring_fail;
76ad4f0e
S		 4456
4457 ret = h->ae_algo->ops->map_ring_to_vector(h,
4458 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 4459
4460 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4461
dd38c726 4462 if (ret)
ece4bf46 4463 goto map_ring_fail;
dd38c726 4464
76ad4f0e
S		 4465 netif_napi_add(priv->netdev, &tqp_vector->napi,
4466 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
4467 }
4468
dd38c726 4469 return 0;
ece4bf46
HT		 4470
4471map_ring_fail:
4472 while (i--)
4473 netif_napi_del(&priv->tqp_vector[i].napi);
4474
4475 return ret;
dd38c726
YL		 4476}
4477
73a13d8d
HT		 4478static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4479{
4480 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4481 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4482 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4483
4484 /* initialize the configuration for interrupt coalescing.
4485 * 1. GL (Interrupt Gap Limiter)
4486 * 2. RL (Interrupt Rate Limiter)
4487 * 3. QL (Interrupt Quantity Limiter)
4488 *
4489 * Default: enable interrupt coalescing self-adaptive and GL
4490 */
4491 tx_coal->adapt_enable = 1;
4492 rx_coal->adapt_enable = 1;
4493
4494 tx_coal->int_gl = HNS3_INT_GL_50K;
4495 rx_coal->int_gl = HNS3_INT_GL_50K;
4496
4497 rx_coal->flow_level = HNS3_FLOW_LOW;
4498 tx_coal->flow_level = HNS3_FLOW_LOW;
4499
4500 if (ae_dev->dev_specs.int_ql_max) {
4501 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4502 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4503 }
4504}
4505
dd38c726
YL		 4506static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4507{
4508 struct hnae3_handle *h = priv->ae_handle;
4509 struct hns3_enet_tqp_vector *tqp_vector;
4510 struct hnae3_vector_info *vector;
4511 struct pci_dev *pdev = h->pdev;
4512 u16 tqp_num = h->kinfo.num_tqps;
4513 u16 vector_num;
4514 int ret = 0;
4515 u16 i;
4516
4517 /* RSS size, cpu online and vector_num should be the same */
4518 /* Should consider 2p/4p later */
4519 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610 4520
dd38c726
YL		 4521 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4522 GFP_KERNEL);
4523 if (!vector)
4524 return -ENOMEM;
4525
9b2f3477 4526 /* save the actual available vector number */
dd38c726
YL		 4527 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4528
4529 priv->vector_num = vector_num;
4530 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4531 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4532 GFP_KERNEL);
4533 if (!priv->tqp_vector) {
4534 ret = -ENOMEM;
4535 goto out;
4536 }
4537
4538 for (i = 0; i < priv->vector_num; i++) {
4539 tqp_vector = &priv->tqp_vector[i];
4540 tqp_vector->idx = i;
4541 tqp_vector->mask_addr = vector[i].io_addr;
4542 tqp_vector->vector_irq = vector[i].vector;
91bfae25 4543 hns3_vector_coalesce_init(tqp_vector, priv);
dd38c726
YL		 4544 }
4545
76ad4f0e
S		 4546out:
4547 devm_kfree(&pdev->dev, vector);
4548 return ret;
4549}
4550
dd38c726
YL		 4551static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4552{
4553 group->ring = NULL;
4554 group->count = 0;
4555}
4556
e2152785 4557static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 4558{
4559 struct hnae3_ring_chain_node vector_ring_chain;
4560 struct hnae3_handle *h = priv->ae_handle;
4561 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 4562 int i;
76ad4f0e
S		 4563
4564 for (i = 0; i < priv->vector_num; i++) {
4565 tqp_vector = &priv->tqp_vector[i];
4566
2c9dd668
HT		 4567 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4568 continue;
4569
ff7dfcdd
HT		 4570 /* Since the mapping can be overwritten, when fail to get the
4571 * chain between vector and ring, we should go on to deal with
4572 * the remaining options.
4573 */
4574 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
4575 dev_warn(priv->dev, "failed to get ring chain\n");
76ad4f0e 4576
e2152785 4577 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 4578 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 4579
4580 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4581
dd38c726
YL		 4582 hns3_clear_ring_group(&tqp_vector->rx_group);
4583 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 4584 netif_napi_del(&priv->tqp_vector[i].napi);
4585 }
dd38c726
YL		 4586}
4587
08a10068 4588static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
dd38c726
YL		 4589{
4590 struct hnae3_handle *h = priv->ae_handle;
4591 struct pci_dev *pdev = h->pdev;
4592 int i, ret;
4593
4594 for (i = 0; i < priv->vector_num; i++) {
4595 struct hns3_enet_tqp_vector *tqp_vector;
4596
4597 tqp_vector = &priv->tqp_vector[i];
4598 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4599 if (ret)
08a10068 4600 return;
dd38c726 4601 }
76ad4f0e 4602
dd38c726 4603 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 4604}
4605
5f06b903
YL		 4606static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4607 unsigned int ring_type)
76ad4f0e 4608{
76ad4f0e 4609 int queue_num = priv->ae_handle->kinfo.num_tqps;
76ad4f0e 4610 struct hns3_enet_ring *ring;
c0425944 4611 int desc_num;
76ad4f0e 4612
76ad4f0e 4613 if (ring_type == HNAE3_RING_TYPE_TX) {
5f06b903 4614 ring = &priv->ring[q->tqp_index];
c0425944 4615 desc_num = priv->ae_handle->kinfo.num_tx_desc;
5f06b903 4616 ring->queue_index = q->tqp_index;
907676b1
YL		 4617 ring->tx_copybreak = priv->tx_copybreak;
4618 ring->last_to_use = 0;
76ad4f0e 4619 } else {
5f06b903 4620 ring = &priv->ring[q->tqp_index + queue_num];
c0425944 4621 desc_num = priv->ae_handle->kinfo.num_rx_desc;
5f06b903 4622 ring->queue_index = q->tqp_index;
76ad4f0e
S		 4623 }
4624
e4e87715 4625 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 4626
76ad4f0e
S		 4627 ring->tqp = q;
4628 ring->desc = NULL;
4629 ring->desc_cb = NULL;
4630 ring->dev = priv->dev;
4631 ring->desc_dma_addr = 0;
4632 ring->buf_size = q->buf_size;
2c9dd668 4633 ring->desc_num = desc_num;
76ad4f0e
S		 4634 ring->next_to_use = 0;
4635 ring->next_to_clean = 0;
76ad4f0e
S		 4636}
4637
5f06b903
YL		 4638static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4639 struct hns3_nic_priv *priv)
76ad4f0e 4640{
5f06b903
YL		 4641 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4642 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
76ad4f0e
S		 4643}
4644
4645static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4646{
4647 struct hnae3_handle *h = priv->ae_handle;
4648 struct pci_dev *pdev = h->pdev;
5f06b903 4649 int i;
76ad4f0e 4650
5f06b903
YL		 4651 priv->ring = devm_kzalloc(&pdev->dev,
4652 array3_size(h->kinfo.num_tqps,
4653 sizeof(*priv->ring), 2),
4654 GFP_KERNEL);
4655 if (!priv->ring)
76ad4f0e
S		 4656 return -ENOMEM;
4657
5f06b903
YL		 4658 for (i = 0; i < h->kinfo.num_tqps; i++)
4659 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
76ad4f0e
S		 4660
4661 return 0;
76ad4f0e
S		 4662}
4663
09f2af64
PL		 4664static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4665{
5f06b903 4666 if (!priv->ring)
7b8f622e
HT		 4667 return;
4668
5f06b903
YL		 4669 devm_kfree(priv->dev, priv->ring);
4670 priv->ring = NULL;
09f2af64
PL		 4671}
4672
76ad4f0e
S		 4673static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4674{
4675 int ret;
4676
4677 if (ring->desc_num <= 0 || ring->buf_size <= 0)
4678 return -EINVAL;
4679
77296bf6
YL		 4680 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4681 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 4682 if (!ring->desc_cb) {
4683 ret = -ENOMEM;
4684 goto out;
4685 }
4686
4687 ret = hns3_alloc_desc(ring);
4688 if (ret)
4689 goto out_with_desc_cb;
4690
4691 if (!HNAE3_IS_TX_RING(ring)) {
4692 ret = hns3_alloc_ring_buffers(ring);
4693 if (ret)
4694 goto out_with_desc;
907676b1
YL		 4695 } else {
4696 hns3_init_tx_spare_buffer(ring);
76ad4f0e
S		 4697 }
4698
4699 return 0;
4700
4701out_with_desc:
4702 hns3_free_desc(ring);
4703out_with_desc_cb:
77296bf6 4704 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 4705 ring->desc_cb = NULL;
4706out:
4707 return ret;
4708}
4709
a723fb8e 4710void hns3_fini_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 4711{
4712 hns3_free_desc(ring);
77296bf6 4713 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 4714 ring->desc_cb = NULL;
4715 ring->next_to_clean = 0;
4716 ring->next_to_use = 0;
20d06ca2 4717 ring->last_to_use = 0;
ac574b80 4718 ring->pending_buf = 0;
907676b1 4719 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
ac574b80
PL		 4720 dev_kfree_skb_any(ring->skb);
4721 ring->skb = NULL;
907676b1
YL		 4722 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
4723 struct hns3_tx_spare *tx_spare = ring->tx_spare;
4724
4725 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
4726 DMA_TO_DEVICE);
4727 free_pages((unsigned long)tx_spare->buf,
4728 get_order(tx_spare->len));
4729 devm_kfree(ring_to_dev(ring), tx_spare);
4730 ring->tx_spare = NULL;
ac574b80 4731 }
76ad4f0e
S		 4732}
4733
1db9b1bf 4734static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 4735{
4736 int bd_size_type;
4737
4738 switch (buf_size) {
4739 case 512:
4740 bd_size_type = HNS3_BD_SIZE_512_TYPE;
4741 break;
4742 case 1024:
4743 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
4744 break;
4745 case 2048:
4746 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4747 break;
4748 case 4096:
4749 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
4750 break;
4751 default:
4752 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4753 }
4754
4755 return bd_size_type;
4756}
4757
4758static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
4759{
4760 dma_addr_t dma = ring->desc_dma_addr;
4761 struct hnae3_queue *q = ring->tqp;
4762
4763 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 4764 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S		 4765 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
4766 (u32)((dma >> 31) >> 1));
4767
4768 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
4769 hns3_buf_size2type(ring->buf_size));
4770 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
4771 ring->desc_num / 8 - 1);
76ad4f0e
S		 4772 } else {
4773 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
4774 (u32)dma);
4775 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
4776 (u32)((dma >> 31) >> 1));
4777
76ad4f0e
S		 4778 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
4779 ring->desc_num / 8 - 1);
4780 }
4781}
4782
1c772154
YL		 4783static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
4784{
4785 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
35244430 4786 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
1c772154
YL		 4787 int i;
4788
4789 for (i = 0; i < HNAE3_MAX_TC; i++) {
1c772154
YL		 4790 int j;
4791
35244430 4792 if (!test_bit(i, &tc_info->tc_en))
1c772154
YL		 4793 continue;
4794
35244430 4795 for (j = 0; j < tc_info->tqp_count[i]; j++) {
1c772154
YL		 4796 struct hnae3_queue *q;
4797
35244430
JS		 4798 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
4799 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
1c772154
YL		 4800 }
4801 }
4802}
4803
5668abda 4804int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 4805{
4806 struct hnae3_handle *h = priv->ae_handle;
4807 int ring_num = h->kinfo.num_tqps * 2;
4808 int i, j;
4809 int ret;
4810
4811 for (i = 0; i < ring_num; i++) {
5f06b903 4812 ret = hns3_alloc_ring_memory(&priv->ring[i]);
76ad4f0e
S		 4813 if (ret) {
4814 dev_err(priv->dev,
4815 "Alloc ring memory fail! ret=%d\n", ret);
4816 goto out_when_alloc_ring_memory;
4817 }
4818
5f06b903 4819 u64_stats_init(&priv->ring[i].syncp);
76ad4f0e
S		 4820 }
4821
4822 return 0;
4823
4824out_when_alloc_ring_memory:
4825 for (j = i - 1; j >= 0; j--)
5f06b903 4826 hns3_fini_ring(&priv->ring[j]);
76ad4f0e
S		 4827
4828 return -ENOMEM;
4829}
4830
64749c9c 4831static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 4832{
4833 struct hnae3_handle *h = priv->ae_handle;
4834 int i;
4835
4836 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903
YL		 4837 hns3_fini_ring(&priv->ring[i]);
4838 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
76ad4f0e 4839 }
76ad4f0e
S		 4840}
4841
4842/* Set mac addr if it is configured. or leave it to the AE driver */
8e6de441 4843static int hns3_init_mac_addr(struct net_device *netdev)
76ad4f0e
S		 4844{
4845 struct hns3_nic_priv *priv = netdev_priv(netdev);
4846 struct hnae3_handle *h = priv->ae_handle;
4847 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 4848 int ret = 0;
76ad4f0e 4849
8e6de441 4850 if (h->ae_algo->ops->get_mac_addr)
76ad4f0e 4851 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
76ad4f0e
S		 4852
4853 /* Check if the MAC address is valid, if not get a random one */
8e6de441 4854 if (!is_valid_ether_addr(mac_addr_temp)) {
76ad4f0e
S		 4855 eth_hw_addr_random(netdev);
4856 dev_warn(priv->dev, "using random MAC address %pM\n",
4857 netdev->dev_addr);
ee4bcd3b 4858 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
8e6de441
HT		 4859 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
4860 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
ee4bcd3b
JS		 4861 } else {
4862 return 0;
76ad4f0e 4863 }
139e8792
L		 4864
4865 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 4866 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 4867
7fa6be4f 4868 return ret;
76ad4f0e
S		 4869}
4870
c8a8045b
HT		 4871static int hns3_init_phy(struct net_device *netdev)
4872{
4873 struct hnae3_handle *h = hns3_get_handle(netdev);
4874 int ret = 0;
4875
4876 if (h->ae_algo->ops->mac_connect_phy)
4877 ret = h->ae_algo->ops->mac_connect_phy(h);
4878
4879 return ret;
4880}
4881
4882static void hns3_uninit_phy(struct net_device *netdev)
4883{
4884 struct hnae3_handle *h = hns3_get_handle(netdev);
4885
4886 if (h->ae_algo->ops->mac_disconnect_phy)
4887 h->ae_algo->ops->mac_disconnect_phy(h);
4888}
4889
a6d818e3
YL		 4890static int hns3_client_start(struct hnae3_handle *handle)
4891{
4892 if (!handle->ae_algo->ops->client_start)
4893 return 0;
4894
4895 return handle->ae_algo->ops->client_start(handle);
4896}
4897
4898static void hns3_client_stop(struct hnae3_handle *handle)
4899{
4900 if (!handle->ae_algo->ops->client_stop)
4901 return;
4902
4903 handle->ae_algo->ops->client_stop(handle);
4904}
4905
bb87be87
YL		 4906static void hns3_info_show(struct hns3_nic_priv *priv)
4907{
4908 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
4909
4910 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
adcf738b
GL		 4911 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
4912 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
4913 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
4914 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
4915 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
4916 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
35244430
JS		 4917 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
4918 kinfo->tc_info.num_tc);
adcf738b 4919 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
bb87be87
YL		 4920}
4921
76ad4f0e
S		 4922static int hns3_client_init(struct hnae3_handle *handle)
4923{
4924 struct pci_dev *pdev = handle->pdev;
fd665b3d 4925 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
0d43bf45 4926 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 4927 struct hns3_nic_priv *priv;
4928 struct net_device *netdev;
4929 int ret;
4930
0d43bf45
HT		 4931 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
4932 &max_rss_size);
4933 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 4934 if (!netdev)
4935 return -ENOMEM;
4936
4937 priv = netdev_priv(netdev);
4938 priv->dev = &pdev->dev;
4939 priv->netdev = netdev;
4940 priv->ae_handle = handle;
f8fa222c 4941 priv->tx_timeout_count = 0;
fd665b3d 4942 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
b7b585c2 4943 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 4944
bb87be87
YL		 4945 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
4946
76ad4f0e
S		 4947 handle->kinfo.netdev = netdev;
4948 handle->priv = (void *)priv;
4949
8e6de441 4950 hns3_init_mac_addr(netdev);
76ad4f0e
S		 4951
4952 hns3_set_default_feature(netdev);
4953
4954 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
4955 netdev->priv_flags |= IFF_UNICAST_FLT;
4956 netdev->netdev_ops = &hns3_nic_netdev_ops;
4957 SET_NETDEV_DEV(netdev, &pdev->dev);
4958 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 4959
4960 /* Carrier off reporting is important to ethtool even BEFORE open */
4961 netif_carrier_off(netdev);
4962
4963 ret = hns3_get_ring_config(priv);
4964 if (ret) {
4965 ret = -ENOMEM;
4966 goto out_get_ring_cfg;
4967 }
4968
73a13d8d
HT		 4969 hns3_nic_init_coal_cfg(priv);
4970
dd38c726
YL		 4971 ret = hns3_nic_alloc_vector_data(priv);
4972 if (ret) {
4973 ret = -ENOMEM;
4974 goto out_alloc_vector_data;
4975 }
4976
76ad4f0e
S		 4977 ret = hns3_nic_init_vector_data(priv);
4978 if (ret) {
4979 ret = -ENOMEM;
4980 goto out_init_vector_data;
4981 }
4982
4983 ret = hns3_init_all_ring(priv);
4984 if (ret) {
4985 ret = -ENOMEM;
5f06b903 4986 goto out_init_ring;
76ad4f0e
S		 4987 }
4988
c8a8045b
HT		 4989 ret = hns3_init_phy(netdev);
4990 if (ret)
4991 goto out_init_phy;
4992
08a10068
YL		 4993 /* the device can work without cpu rmap, only aRFS needs it */
4994 ret = hns3_set_rx_cpu_rmap(netdev);
4995 if (ret)
4996 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4997
4998 ret = hns3_nic_init_irq(priv);
4999 if (ret) {
5000 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5001 hns3_free_rx_cpu_rmap(netdev);
5002 goto out_init_irq_fail;
5003 }
5004
a6d818e3
YL		 5005 ret = hns3_client_start(handle);
5006 if (ret) {
5007 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 5008 goto out_client_start;
a6d818e3
YL		 5009 }
5010
986743db
YL		 5011 hns3_dcbnl_setup(handle);
5012
5e69ea7e
YM		 5013 ret = hns3_dbg_init(handle);
5014 if (ret) {
5015 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5016 ret);
5017 goto out_client_start;
5018 }
b2292360 5019
e070c8b9 5020 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
a8e8b7ff 5021
66d52f3b
HT		 5022 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5023 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5024
79664077
HT		 5025 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5026 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5027
814da63c
HT		 5028 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5029
5e7414cd
JS		 5030 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5031 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5032
a289a7e5
JS		 5033 ret = register_netdev(netdev);
5034 if (ret) {
5035 dev_err(priv->dev, "probe register netdev fail!\n");
5036 goto out_reg_netdev_fail;
5037 }
5038
bb87be87
YL		 5039 if (netif_msg_drv(handle))
5040 hns3_info_show(priv);
5041
76ad4f0e
S		 5042 return ret;
5043
a289a7e5
JS		 5044out_reg_netdev_fail:
5045 hns3_dbg_uninit(handle);
18655128 5046out_client_start:
08a10068
YL		 5047 hns3_free_rx_cpu_rmap(netdev);
5048 hns3_nic_uninit_irq(priv);
5049out_init_irq_fail:
c8a8045b
HT		 5050 hns3_uninit_phy(netdev);
5051out_init_phy:
5052 hns3_uninit_all_ring(priv);
5f06b903 5053out_init_ring:
e2152785 5054 hns3_nic_uninit_vector_data(priv);
76ad4f0e 5055out_init_vector_data:
dd38c726
YL		 5056 hns3_nic_dealloc_vector_data(priv);
5057out_alloc_vector_data:
5f06b903 5058 priv->ring = NULL;
76ad4f0e
S		 5059out_get_ring_cfg:
5060 priv->ae_handle = NULL;
5061 free_netdev(netdev);
5062 return ret;
5063}
5064
5065static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5066{
5067 struct net_device *netdev = handle->kinfo.netdev;
5068 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 5069
5070 if (netdev->reg_state != NETREG_UNINITIALIZED)
5071 unregister_netdev(netdev);
5072
eb32c896
HT		 5073 hns3_client_stop(handle);
5074
0d2f68c7
HT		 5075 hns3_uninit_phy(netdev);
5076
814da63c
HT		 5077 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5078 netdev_warn(netdev, "already uninitialized\n");
5079 goto out_netdev_free;
5080 }
5081
08a10068
YL		 5082 hns3_free_rx_cpu_rmap(netdev);
5083
5084 hns3_nic_uninit_irq(priv);
5085
f96315f2 5086 hns3_clear_all_ring(handle, true);
7b763f3f 5087
e2152785 5088 hns3_nic_uninit_vector_data(priv);
76ad4f0e 5089
08a10068 5090 hns3_nic_dealloc_vector_data(priv);
dd38c726 5091
64749c9c 5092 hns3_uninit_all_ring(priv);
76ad4f0e 5093
ec777890
YL		 5094 hns3_put_ring_config(priv);
5095
814da63c 5096out_netdev_free:
e22b5e72 5097 hns3_dbg_uninit(handle);
76ad4f0e
S		 5098 free_netdev(netdev);
5099}
5100
5101static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5102{
5103 struct net_device *netdev = handle->kinfo.netdev;
5104
5105 if (!netdev)
5106 return;
5107
5108 if (linkup) {
76ad4f0e 5109 netif_tx_wake_all_queues(netdev);
a7e90ee5 5110 netif_carrier_on(netdev);
bb87be87
YL		 5111 if (netif_msg_link(handle))
5112 netdev_info(netdev, "link up\n");
76ad4f0e
S		 5113 } else {
5114 netif_carrier_off(netdev);
5115 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 5116 if (netif_msg_link(handle))
5117 netdev_info(netdev, "link down\n");
76ad4f0e
S		 5118 }
5119}
5120
beebca3a 5121static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 5122{
beebca3a 5123 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 5124 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
619ae331 5125 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
beebca3a
YL		 5126 ring_ptr_move_fw(ring, next_to_clean);
5127 }
f6061a05
YL		 5128
5129 ring->pending_buf = 0;
beebca3a
YL		 5130}
5131
7b763f3f
FL		 5132static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5133{
5134 struct hns3_desc_cb res_cbs;
5135 int ret;
5136
5137 while (ring->next_to_use != ring->next_to_clean) {
5138 /* When a buffer is not reused, it's memory has been
5139 * freed in hns3_handle_rx_bd or will be freed by
5140 * stack, so we need to replace the buffer here.
5141 */
5142 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4d2cad32 5143 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
7b763f3f
FL		 5144 if (ret) {
5145 u64_stats_update_begin(&ring->syncp);
5146 ring->stats.sw_err_cnt++;
5147 u64_stats_update_end(&ring->syncp);
5148 /* if alloc new buffer fail, exit directly
5149 * and reclear in up flow.
5150 */
c8711956 5151 netdev_warn(ring_to_netdev(ring),
7b763f3f
FL		 5152 "reserve buffer map failed, ret = %d\n",
5153 ret);
5154 return ret;
5155 }
9b2f3477 5156 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL		 5157 }
5158 ring_ptr_move_fw(ring, next_to_use);
5159 }
5160
cc5ff6e9
PL		 5161 /* Free the pending skb in rx ring */
5162 if (ring->skb) {
5163 dev_kfree_skb_any(ring->skb);
5164 ring->skb = NULL;
5165 ring->pending_buf = 0;
5166 }
5167
7b763f3f
FL		 5168 return 0;
5169}
5170
5171static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 5172{
beebca3a
YL		 5173 while (ring->next_to_use != ring->next_to_clean) {
5174 /* When a buffer is not reused, it's memory has been
5175 * freed in hns3_handle_rx_bd or will be freed by
5176 * stack, so only need to unmap the buffer here.
5177 */
5178 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5179 hns3_unmap_buffer(ring,
5180 &ring->desc_cb[ring->next_to_use]);
5181 ring->desc_cb[ring->next_to_use].dma = 0;
5182 }
5183
5184 ring_ptr_move_fw(ring, next_to_use);
5185 }
bb6b94a8
L		 5186}
5187
f96315f2 5188static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L		 5189{
5190 struct net_device *ndev = h->kinfo.netdev;
5191 struct hns3_nic_priv *priv = netdev_priv(ndev);
5192 u32 i;
5193
5194 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L		 5195 struct hns3_enet_ring *ring;
5196
5f06b903 5197 ring = &priv->ring[i];
beebca3a 5198 hns3_clear_tx_ring(ring);
bb6b94a8 5199
5f06b903 5200 ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 5201 /* Continue to clear other rings even if clearing some
5202 * rings failed.
5203 */
f96315f2
HT		 5204 if (force)
5205 hns3_force_clear_rx_ring(ring);
5206 else
5207 hns3_clear_rx_ring(ring);
bb6b94a8
L		 5208 }
5209}
5210
7b763f3f
FL		 5211int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5212{
5213 struct net_device *ndev = h->kinfo.netdev;
5214 struct hns3_nic_priv *priv = netdev_priv(ndev);
5215 struct hns3_enet_ring *rx_ring;
5216 int i, j;
5217 int ret;
5218
8fa86551
YM		 5219 ret = h->ae_algo->ops->reset_queue(h);
5220 if (ret)
5221 return ret;
7fa6be4f 5222
8fa86551 5223 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903 5224 hns3_init_ring_hw(&priv->ring[i]);
7b763f3f
FL		 5225
5226 /* We need to clear tx ring here because self test will
5227 * use the ring and will not run down before up
5228 */
5f06b903
YL		 5229 hns3_clear_tx_ring(&priv->ring[i]);
5230 priv->ring[i].next_to_clean = 0;
5231 priv->ring[i].next_to_use = 0;
20d06ca2 5232 priv->ring[i].last_to_use = 0;
7b763f3f 5233
5f06b903 5234 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 5235 hns3_init_ring_hw(rx_ring);
5236 ret = hns3_clear_rx_ring(rx_ring);
5237 if (ret)
5238 return ret;
5239
5240 /* We can not know the hardware head and tail when this
5241 * function is called in reset flow, so we reuse all desc.
5242 */
5243 for (j = 0; j < rx_ring->desc_num; j++)
5244 hns3_reuse_buffer(rx_ring, j);
5245
5246 rx_ring->next_to_clean = 0;
5247 rx_ring->next_to_use = 0;
5248 }
5249
1c772154
YL		 5250 hns3_init_tx_ring_tc(priv);
5251
7b763f3f
FL		 5252 return 0;
5253}
5254
bb6b94a8
L		 5255static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5256{
5257 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5258 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 5259 struct hns3_nic_priv *priv = netdev_priv(ndev);
5260
5261 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5262 return 0;
bb6b94a8
L		 5263
5264 if (!netif_running(ndev))
6b1385cc 5265 return 0;
bb6b94a8
L		 5266
5267 return hns3_nic_net_stop(ndev);
5268}
5269
5270static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5271{
5272 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 5273 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 5274 int ret = 0;
5275
b4047aac
JS		 5276 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5277 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5278 return -EFAULT;
5279 }
5280
e8884027
HT		 5281 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5282
bb6b94a8 5283 if (netif_running(kinfo->netdev)) {
e8884027 5284 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 5285 if (ret) {
e8884027 5286 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 5287 netdev_err(kinfo->netdev,
9b2f3477 5288 "net up fail, ret=%d!\n", ret);
bb6b94a8
L		 5289 return ret;
5290 }
bb6b94a8
L		 5291 }
5292
5293 return ret;
5294}
5295
5296static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5297{
5298 struct net_device *netdev = handle->kinfo.netdev;
5299 struct hns3_nic_priv *priv = netdev_priv(netdev);
5300 int ret;
5301
bb6b94a8
L		 5302 /* Carrier off reporting is important to ethtool even BEFORE open */
5303 netif_carrier_off(netdev);
5304
2c9dd668 5305 ret = hns3_get_ring_config(priv);
862d969a
HT		 5306 if (ret)
5307 return ret;
5308
2c9dd668
HT		 5309 ret = hns3_nic_alloc_vector_data(priv);
5310 if (ret)
5311 goto err_put_ring;
5312
bb6b94a8
L		 5313 ret = hns3_nic_init_vector_data(priv);
5314 if (ret)
862d969a 5315 goto err_dealloc_vector;
bb6b94a8
L		 5316
5317 ret = hns3_init_all_ring(priv);
862d969a
HT		 5318 if (ret)
5319 goto err_uninit_vector;
bb6b94a8 5320
08a10068
YL		 5321 /* the device can work without cpu rmap, only aRFS needs it */
5322 ret = hns3_set_rx_cpu_rmap(netdev);
5323 if (ret)
5324 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5325
5326 ret = hns3_nic_init_irq(priv);
5327 if (ret) {
5328 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5329 hns3_free_rx_cpu_rmap(netdev);
5330 goto err_init_irq_fail;
5331 }
5332
ee4bcd3b
JS		 5333 if (!hns3_is_phys_func(handle->pdev))
5334 hns3_init_mac_addr(netdev);
5335
cd513a69
HT		 5336 ret = hns3_client_start(handle);
5337 if (ret) {
5338 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
08a10068 5339 goto err_client_start_fail;
cd513a69
HT		 5340 }
5341
814da63c
HT		 5342 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5343
862d969a
HT		 5344 return ret;
5345
08a10068
YL		 5346err_client_start_fail:
5347 hns3_free_rx_cpu_rmap(netdev);
5348 hns3_nic_uninit_irq(priv);
5349err_init_irq_fail:
cd513a69 5350 hns3_uninit_all_ring(priv);
862d969a
HT		 5351err_uninit_vector:
5352 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 5353err_dealloc_vector:
5354 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 5355err_put_ring:
5356 hns3_put_ring_config(priv);
862d969a 5357
bb6b94a8
L		 5358 return ret;
5359}
5360
5361static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5362{
5363 struct net_device *netdev = handle->kinfo.netdev;
5364 struct hns3_nic_priv *priv = netdev_priv(netdev);
bb6b94a8 5365
1eeb3367 5366 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 5367 netdev_warn(netdev, "already uninitialized\n");
5368 return 0;
5369 }
5370
08a10068
YL		 5371 hns3_free_rx_cpu_rmap(netdev);
5372 hns3_nic_uninit_irq(priv);
f96315f2
HT		 5373 hns3_clear_all_ring(handle, true);
5374 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 5375
e2152785 5376 hns3_nic_uninit_vector_data(priv);
bb6b94a8 5377
08a10068 5378 hns3_nic_dealloc_vector_data(priv);
862d969a 5379
64749c9c 5380 hns3_uninit_all_ring(priv);
bb6b94a8 5381
2c9dd668 5382 hns3_put_ring_config(priv);
2c9dd668 5383
205238f4 5384 return 0;
bb6b94a8
L		 5385}
5386
5387static int hns3_reset_notify(struct hnae3_handle *handle,
5388 enum hnae3_reset_notify_type type)
5389{
5390 int ret = 0;
5391
5392 switch (type) {
5393 case HNAE3_UP_CLIENT:
e1586241
SM		 5394 ret = hns3_reset_notify_up_enet(handle);
5395 break;
bb6b94a8
L		 5396 case HNAE3_DOWN_CLIENT:
5397 ret = hns3_reset_notify_down_enet(handle);
5398 break;
5399 case HNAE3_INIT_CLIENT:
5400 ret = hns3_reset_notify_init_enet(handle);
5401 break;
5402 case HNAE3_UNINIT_CLIENT:
5403 ret = hns3_reset_notify_uninit_enet(handle);
5404 break;
5405 default:
5406 break;
5407 }
5408
5409 return ret;
5410}
5411
3a5a5f06
PL		 5412static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5413 bool rxfh_configured)
5414{
5415 int ret;
5416
5417 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5418 rxfh_configured);
5419 if (ret) {
5420 dev_err(&handle->pdev->dev,
5421 "Change tqp num(%u) fail.\n", new_tqp_num);
5422 return ret;
5423 }
5424
5425 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5426 if (ret)
5427 return ret;
5428
5429 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5430 if (ret)
5431 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5432
5433 return ret;
5434}
5435
09f2af64
PL		 5436int hns3_set_channels(struct net_device *netdev,
5437 struct ethtool_channels *ch)
5438{
09f2af64
PL		 5439 struct hnae3_handle *h = hns3_get_handle(netdev);
5440 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 5441 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 5442 u32 new_tqp_num = ch->combined_count;
5443 u16 org_tqp_num;
5444 int ret;
5445
44950d28
JS		 5446 if (hns3_nic_resetting(netdev))
5447 return -EBUSY;
5448
09f2af64
PL		 5449 if (ch->rx_count || ch->tx_count)
5450 return -EINVAL;
5451
5a5c9091
JS		 5452 if (kinfo->tc_info.mqprio_active) {
5453 dev_err(&netdev->dev,
5454 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5455 return -EINVAL;
5456 }
5457
678335a1 5458 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 5459 new_tqp_num < 1) {
09f2af64 5460 dev_err(&netdev->dev,
adcf738b 5461 "Change tqps fail, the tqp range is from 1 to %u",
678335a1 5462 hns3_get_max_available_channels(h));
09f2af64
PL		 5463 return -EINVAL;
5464 }
5465
c78b5b6c 5466 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 5467 return 0;
5468
1c822948
YL		 5469 netif_dbg(h, drv, netdev,
5470 "set channels: tqp_num=%u, rxfh=%d\n",
5471 new_tqp_num, rxfh_configured);
5472
65749f73
HT		 5473 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5474 if (ret)
5475 return ret;
dd38c726 5476
65749f73
HT		 5477 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5478 if (ret)
5479 return ret;
09f2af64
PL		 5480
5481 org_tqp_num = h->kinfo.num_tqps;
3a5a5f06 5482 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 5483 if (ret) {
3a5a5f06
PL		 5484 int ret1;
5485
5486 netdev_warn(netdev,
5487 "Change channels fail, revert to old value\n");
5488 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5489 if (ret1) {
5490 netdev_err(netdev,
5491 "revert to old channel fail\n");
5492 return ret1;
09f2af64 5493 }
3a5a5f06 5494
65749f73 5495 return ret;
3a5a5f06 5496 }
09f2af64 5497
3a5a5f06 5498 return 0;
09f2af64
PL		 5499}
5500
a83d2961
WL		 5501static const struct hns3_hw_error_info hns3_hw_err[] = {
5502 { .type = HNAE3_PPU_POISON_ERROR,
5503 .msg = "PPU poison" },
5504 { .type = HNAE3_CMDQ_ECC_ERROR,
5505 .msg = "IMP CMDQ error" },
5506 { .type = HNAE3_IMP_RD_POISON_ERROR,
5507 .msg = "IMP RD poison" },
6cd131dd
YM		 5508 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5509 .msg = "ROCEE AXI RESP error" },
a83d2961
WL		 5510};
5511
5512static void hns3_process_hw_error(struct hnae3_handle *handle,
5513 enum hnae3_hw_error_type type)
5514{
5515 int i;
5516
5517 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5518 if (hns3_hw_err[i].type == type) {
5519 dev_err(&handle->pdev->dev, "Detected %s!\n",
5520 hns3_hw_err[i].msg);
5521 break;
5522 }
5523 }
5524}
5525
1db9b1bf 5526static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 5527 .init_instance = hns3_client_init,
5528 .uninit_instance = hns3_client_uninit,
5529 .link_status_change = hns3_link_status_change,
bb6b94a8 5530 .reset_notify = hns3_reset_notify,
a83d2961 5531 .process_hw_error = hns3_process_hw_error,
76ad4f0e
S		 5532};
5533
5534/* hns3_init_module - Driver registration routine
5535 * hns3_init_module is the first routine called when the driver is
5536 * loaded. All it does is register with the PCI subsystem.
5537 */
5538static int __init hns3_init_module(void)
5539{
5540 int ret;
5541
5542 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5543 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5544
5545 client.type = HNAE3_CLIENT_KNIC;
cdc37385 5546 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
76ad4f0e
S		 5547 hns3_driver_name);
5548
5549 client.ops = &client_ops;
5550
13562d1f
XW		 5551 INIT_LIST_HEAD(&client.node);
5552
b2292360 5553 hns3_dbg_register_debugfs(hns3_driver_name);
5554
76ad4f0e
S		 5555 ret = hnae3_register_client(&client);
5556 if (ret)
b2292360 5557 goto err_reg_client;
76ad4f0e
S		 5558
5559 ret = pci_register_driver(&hns3_driver);
5560 if (ret)
b2292360 5561 goto err_reg_driver;
76ad4f0e
S		 5562
5563 return ret;
b2292360 5564
5565err_reg_driver:
5566 hnae3_unregister_client(&client);
5567err_reg_client:
5568 hns3_dbg_unregister_debugfs();
5569 return ret;
76ad4f0e
S		 5570}
5571module_init(hns3_init_module);
5572
5573/* hns3_exit_module - Driver exit cleanup routine
5574 * hns3_exit_module is called just before the driver is removed
5575 * from memory.
5576 */
5577static void __exit hns3_exit_module(void)
5578{
5579 pci_unregister_driver(&hns3_driver);
5580 hnae3_unregister_client(&client);
b2292360 5581 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 5582}
5583module_exit(hns3_exit_module);
5584
5585MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
5586MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5587MODULE_LICENSE("GPL");
5588MODULE_ALIAS("pci:hns-nic");
Linux 6.x block layer and io_uring tree(s)