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net: hns3: fix for not calculating TX BD send size correctly
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e
S		 10#include <linux/if_vlan.h>
11#include <linux/ip.h>
12#include <linux/ipv6.h>
13#include <linux/module.h>
14#include <linux/pci.h>
6ae4e733 15#include <linux/aer.h>
76ad4f0e
S		 16#include <linux/skbuff.h>
17#include <linux/sctp.h>
76ad4f0e 18#include <net/gre.h>
e2ee1c5a 19#include <net/ip6_checksum.h>
30d240df 20#include <net/pkt_cls.h>
a6d53b97 21#include <net/tcp.h>
76ad4f0e
S		 22#include <net/vxlan.h>
23
24#include "hnae3.h"
25#include "hns3_enet.h"
698a8954
YL		 26/* All hns3 tracepoints are defined by the include below, which
27 * must be included exactly once across the whole kernel with
28 * CREATE_TRACE_POINTS defined
29 */
30#define CREATE_TRACE_POINTS
31#include "hns3_trace.h"
76ad4f0e 32
cde4ffad 33#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 34#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 35
b20d7fe5
YL		 36#define hns3_rl_err(fmt, ...) \
37 do { \
38 if (net_ratelimit()) \
39 netdev_err(fmt, ##__VA_ARGS__); \
40 } while (0)
41
f96315f2 42static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
7b763f3f 43
1db9b1bf 44static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 45static const char hns3_driver_string[] =
46 "Hisilicon Ethernet Network Driver for Hip08 Family";
47static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
48static struct hnae3_client client;
49
bb87be87
YL		 50static int debug = -1;
51module_param(debug, int, 0);
52MODULE_PARM_DESC(debug, " Network interface message level setting");
53
54#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
55 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
56
eb977d99
YL		 57#define HNS3_INNER_VLAN_TAG 1
58#define HNS3_OUTER_VLAN_TAG 2
59
36c67349
YL		 60#define HNS3_MIN_TX_LEN 33U
61
76ad4f0e
S		 62/* hns3_pci_tbl - PCI Device ID Table
63 *
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static const struct pci_device_id hns3_pci_tbl[] = {
70 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 73 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
07acf909
JS		 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
84 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 85 /* required last entry */
86 {0, }
87};
88MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
89
ef0c5009 90static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 91{
ef0c5009 92 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 93
fb00331b 94 napi_schedule_irqoff(&tqp_vector->napi);
76ad4f0e
S		 95
96 return IRQ_HANDLED;
97}
98
99static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
100{
101 struct hns3_enet_tqp_vector *tqp_vectors;
102 unsigned int i;
103
104 for (i = 0; i < priv->vector_num; i++) {
105 tqp_vectors = &priv->tqp_vector[i];
106
107 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
108 continue;
109
ffab9691 110 /* clear the affinity mask */
874bff0b
PL		 111 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
112
76ad4f0e
S		 113 /* release the irq resource */
114 free_irq(tqp_vectors->vector_irq, tqp_vectors);
115 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
116 }
117}
118
119static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
120{
121 struct hns3_enet_tqp_vector *tqp_vectors;
122 int txrx_int_idx = 0;
123 int rx_int_idx = 0;
124 int tx_int_idx = 0;
125 unsigned int i;
126 int ret;
127
128 for (i = 0; i < priv->vector_num; i++) {
129 tqp_vectors = &priv->tqp_vector[i];
130
131 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
132 continue;
133
134 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
5bffde62
YL		 135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
136 "%s-%s-%s-%d", hns3_driver_name,
137 pci_name(priv->ae_handle->pdev),
138 "TxRx", txrx_int_idx++);
76ad4f0e
S		 139 txrx_int_idx++;
140 } else if (tqp_vectors->rx_group.ring) {
5bffde62
YL		 141 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
142 "%s-%s-%s-%d", hns3_driver_name,
143 pci_name(priv->ae_handle->pdev),
144 "Rx", rx_int_idx++);
76ad4f0e 145 } else if (tqp_vectors->tx_group.ring) {
5bffde62
YL		 146 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
147 "%s-%s-%s-%d", hns3_driver_name,
148 pci_name(priv->ae_handle->pdev),
149 "Tx", tx_int_idx++);
76ad4f0e
S		 150 } else {
151 /* Skip this unused q_vector */
152 continue;
153 }
154
155 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
156
157 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 158 tqp_vectors->name, tqp_vectors);
76ad4f0e
S		 159 if (ret) {
160 netdev_err(priv->netdev, "request irq(%d) fail\n",
161 tqp_vectors->vector_irq);
d547ecdc 162 hns3_nic_uninit_irq(priv);
76ad4f0e
S		 163 return ret;
164 }
165
08a10068
YL		 166 disable_irq(tqp_vectors->vector_irq);
167
874bff0b
PL		 168 irq_set_affinity_hint(tqp_vectors->vector_irq,
169 &tqp_vectors->affinity_mask);
170
76ad4f0e
S		 171 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
172 }
173
174 return 0;
175}
176
177static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
178 u32 mask_en)
179{
180 writel(mask_en, tqp_vector->mask_addr);
181}
182
183static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
184{
185 napi_enable(&tqp_vector->napi);
08a10068 186 enable_irq(tqp_vector->vector_irq);
76ad4f0e
S		 187
188 /* enable vector */
189 hns3_mask_vector_irq(tqp_vector, 1);
190}
191
192static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
193{
194 /* disable vector */
195 hns3_mask_vector_irq(tqp_vector, 0);
196
197 disable_irq(tqp_vector->vector_irq);
198 napi_disable(&tqp_vector->napi);
199}
200
434776a5
FL		 201void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
202 u32 rl_value)
76ad4f0e 203{
434776a5
FL		 204 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
205
76ad4f0e
S		 206 /* this defines the configuration for RL (Interrupt Rate Limiter).
207 * Rl defines rate of interrupts i.e. number of interrupts-per-second
208 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
209 */
434776a5 210
9bc727a9
YL		 211 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
212 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 213 /* According to the hardware, the range of rl_reg is
214 * 0-59 and the unit is 4.
215 */
216 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
217
218 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
219}
220
221void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
222 u32 gl_value)
223{
224 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
225
226 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
227}
228
229void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
230 u32 gl_value)
231{
232 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
233
234 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 235}
236
5fd4789a
FL		 237static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
238 struct hns3_nic_priv *priv)
76ad4f0e
S		 239{
240 /* initialize the configuration for interrupt coalescing.
241 * 1. GL (Interrupt Gap Limiter)
242 * 2. RL (Interrupt Rate Limiter)
46ee7350
GL		 243 *
244 * Default: enable interrupt coalescing self-adaptive and GL
76ad4f0e 245 */
9bc727a9
YL		 246 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
247 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 248
9bc727a9
YL		 249 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
250 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 251
9bc727a9
YL		 252 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
253 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 254}
255
dd38c726
YL		 256static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
257 struct hns3_nic_priv *priv)
258{
259 struct hnae3_handle *h = priv->ae_handle;
260
261 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 262 tqp_vector->tx_group.coal.int_gl);
dd38c726 263 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 264 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 265 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
266}
267
9df8f79a
YL		 268static int hns3_nic_set_real_num_queue(struct net_device *netdev)
269{
9780cb97 270 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 271 struct hnae3_knic_private_info *kinfo = &h->kinfo;
272 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
a75a8efa
YL		 273 int i, ret;
274
275 if (kinfo->num_tc <= 1) {
276 netdev_reset_tc(netdev);
277 } else {
278 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
279 if (ret) {
280 netdev_err(netdev,
281 "netdev_set_num_tc fail, ret=%d!\n", ret);
282 return ret;
283 }
284
285 for (i = 0; i < HNAE3_MAX_TC; i++) {
286 if (!kinfo->tc_info[i].enable)
287 continue;
288
289 netdev_set_tc_queue(netdev,
290 kinfo->tc_info[i].tc,
291 kinfo->tc_info[i].tqp_count,
292 kinfo->tc_info[i].tqp_offset);
293 }
294 }
9df8f79a
YL		 295
296 ret = netif_set_real_num_tx_queues(netdev, queue_size);
297 if (ret) {
298 netdev_err(netdev,
9b2f3477 299 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL		 300 return ret;
301 }
302
303 ret = netif_set_real_num_rx_queues(netdev, queue_size);
304 if (ret) {
305 netdev_err(netdev,
306 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
307 return ret;
308 }
309
310 return 0;
311}
312
678335a1
PL		 313static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
314{
0d43bf45 315 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 316
0d43bf45
HT		 317 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
318 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 319
0d43bf45 320 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 321}
322
8df0fa91
HT		 323static void hns3_tqp_enable(struct hnae3_queue *tqp)
324{
325 u32 rcb_reg;
326
327 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
328 rcb_reg |= BIT(HNS3_RING_EN_B);
329 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
330}
331
332static void hns3_tqp_disable(struct hnae3_queue *tqp)
333{
334 u32 rcb_reg;
335
336 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
337 rcb_reg &= ~BIT(HNS3_RING_EN_B);
338 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
339}
340
ffab9691
JS		 341static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
342{
343#ifdef CONFIG_RFS_ACCEL
344 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
345 netdev->rx_cpu_rmap = NULL;
346#endif
347}
348
349static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
350{
351#ifdef CONFIG_RFS_ACCEL
352 struct hns3_nic_priv *priv = netdev_priv(netdev);
353 struct hns3_enet_tqp_vector *tqp_vector;
354 int i, ret;
355
356 if (!netdev->rx_cpu_rmap) {
357 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
358 if (!netdev->rx_cpu_rmap)
359 return -ENOMEM;
360 }
361
362 for (i = 0; i < priv->vector_num; i++) {
363 tqp_vector = &priv->tqp_vector[i];
364 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
365 tqp_vector->vector_irq);
366 if (ret) {
367 hns3_free_rx_cpu_rmap(netdev);
368 return ret;
369 }
370 }
371#endif
372 return 0;
373}
374
76ad4f0e
S		 375static int hns3_nic_net_up(struct net_device *netdev)
376{
377 struct hns3_nic_priv *priv = netdev_priv(netdev);
378 struct hnae3_handle *h = priv->ae_handle;
379 int i, j;
380 int ret;
381
7b763f3f
FL		 382 ret = hns3_nic_reset_all_ring(h);
383 if (ret)
384 return ret;
385
b7b585c2
JS		 386 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
387
76ad4f0e
S		 388 /* enable the vectors */
389 for (i = 0; i < priv->vector_num; i++)
390 hns3_vector_enable(&priv->tqp_vector[i]);
391
8df0fa91
HT		 392 /* enable rcb */
393 for (j = 0; j < h->kinfo.num_tqps; j++)
394 hns3_tqp_enable(h->kinfo.tqp[j]);
395
76ad4f0e
S		 396 /* start the ae_dev */
397 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
08a10068
YL		 398 if (ret) {
399 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
400 while (j--)
401 hns3_tqp_disable(h->kinfo.tqp[j]);
8df0fa91 402
08a10068
YL		 403 for (j = i - 1; j >= 0; j--)
404 hns3_vector_disable(&priv->tqp_vector[j]);
405 }
76ad4f0e 406
76ad4f0e
S		 407 return ret;
408}
409
2a73ac3e
YL		 410static void hns3_config_xps(struct hns3_nic_priv *priv)
411{
412 int i;
413
414 for (i = 0; i < priv->vector_num; i++) {
415 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
416 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
417
418 while (ring) {
419 int ret;
420
421 ret = netif_set_xps_queue(priv->netdev,
422 &tqp_vector->affinity_mask,
423 ring->tqp->tqp_index);
424 if (ret)
425 netdev_warn(priv->netdev,
426 "set xps queue failed: %d", ret);
427
428 ring = ring->next;
429 }
430 }
431}
432
76ad4f0e
S		 433static int hns3_nic_net_open(struct net_device *netdev)
434{
8cdb992f 435 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 436 struct hnae3_handle *h = hns3_get_handle(netdev);
437 struct hnae3_knic_private_info *kinfo;
438 int i, ret;
76ad4f0e 439
257e4f29
HT		 440 if (hns3_nic_resetting(netdev))
441 return -EBUSY;
442
76ad4f0e
S		 443 netif_carrier_off(netdev);
444
9df8f79a
YL		 445 ret = hns3_nic_set_real_num_queue(netdev);
446 if (ret)
76ad4f0e 447 return ret;
76ad4f0e
S		 448
449 ret = hns3_nic_net_up(netdev);
450 if (ret) {
9b2f3477 451 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S		 452 return ret;
453 }
454
a75a8efa 455 kinfo = &h->kinfo;
9b2f3477
WL		 456 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
457 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
a75a8efa 458
8cdb992f
JS		 459 if (h->ae_algo->ops->set_timer_task)
460 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
461
2a73ac3e 462 hns3_config_xps(priv);
1c822948
YL		 463
464 netif_dbg(h, drv, netdev, "net open\n");
465
76ad4f0e
S		 466 return 0;
467}
468
f96315f2
HT		 469static void hns3_reset_tx_queue(struct hnae3_handle *h)
470{
471 struct net_device *ndev = h->kinfo.netdev;
472 struct hns3_nic_priv *priv = netdev_priv(ndev);
473 struct netdev_queue *dev_queue;
474 u32 i;
475
476 for (i = 0; i < h->kinfo.num_tqps; i++) {
477 dev_queue = netdev_get_tx_queue(ndev,
5f06b903 478 priv->ring[i].queue_index);
f96315f2
HT		 479 netdev_tx_reset_queue(dev_queue);
480 }
481}
482
76ad4f0e
S		 483static void hns3_nic_net_down(struct net_device *netdev)
484{
485 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 486 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 487 const struct hnae3_ae_ops *ops;
488 int i;
489
7b763f3f
FL		 490 /* disable vectors */
491 for (i = 0; i < priv->vector_num; i++)
492 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 493
494 /* disable rcb */
495 for (i = 0; i < h->kinfo.num_tqps; i++)
496 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 497
76ad4f0e
S		 498 /* stop ae_dev */
499 ops = priv->ae_handle->ae_algo->ops;
500 if (ops->stop)
501 ops->stop(priv->ae_handle);
502
3a30964a
YL		 503 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
504 * during reset process, because driver may not be able
505 * to disable the ring through firmware when downing the netdev.
506 */
507 if (!hns3_nic_resetting(netdev))
f96315f2
HT		 508 hns3_clear_all_ring(priv->ae_handle, false);
509
510 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S		 511}
512
513static int hns3_nic_net_stop(struct net_device *netdev)
514{
ff0699e0 515 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 516 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 517
518 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
519 return 0;
520
1c822948
YL		 521 netif_dbg(h, drv, netdev, "net stop\n");
522
8cdb992f
JS		 523 if (h->ae_algo->ops->set_timer_task)
524 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
525
76ad4f0e
S		 526 netif_tx_stop_all_queues(netdev);
527 netif_carrier_off(netdev);
528
529 hns3_nic_net_down(netdev);
530
531 return 0;
532}
533
76ad4f0e
S		 534static int hns3_nic_uc_sync(struct net_device *netdev,
535 const unsigned char *addr)
536{
9780cb97 537 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 538
539 if (h->ae_algo->ops->add_uc_addr)
540 return h->ae_algo->ops->add_uc_addr(h, addr);
541
542 return 0;
543}
544
545static int hns3_nic_uc_unsync(struct net_device *netdev,
546 const unsigned char *addr)
547{
9780cb97 548 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 549
ee4bcd3b
JS		 550 /* need ignore the request of removing device address, because
551 * we store the device address and other addresses of uc list
552 * in the function's mac filter list.
553 */
554 if (ether_addr_equal(addr, netdev->dev_addr))
555 return 0;
556
76ad4f0e
S		 557 if (h->ae_algo->ops->rm_uc_addr)
558 return h->ae_algo->ops->rm_uc_addr(h, addr);
559
560 return 0;
561}
562
563static int hns3_nic_mc_sync(struct net_device *netdev,
564 const unsigned char *addr)
565{
9780cb97 566 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 567
720a8478 568 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 569 return h->ae_algo->ops->add_mc_addr(h, addr);
570
571 return 0;
572}
573
574static int hns3_nic_mc_unsync(struct net_device *netdev,
575 const unsigned char *addr)
576{
9780cb97 577 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 578
720a8478 579 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 580 return h->ae_algo->ops->rm_mc_addr(h, addr);
581
582 return 0;
583}
584
c60edc17
JS		 585static u8 hns3_get_netdev_flags(struct net_device *netdev)
586{
587 u8 flags = 0;
588
589 if (netdev->flags & IFF_PROMISC) {
28673b33 590 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS		 591 } else {
592 flags |= HNAE3_VLAN_FLTR;
593 if (netdev->flags & IFF_ALLMULTI)
594 flags |= HNAE3_USER_MPE;
595 }
596
597 return flags;
598}
599
1db9b1bf 600static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 601{
9780cb97 602 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17 603 u8 new_flags;
76ad4f0e 604
c60edc17
JS		 605 new_flags = hns3_get_netdev_flags(netdev);
606
c631c696
JS		 607 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
608 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
c60edc17 609
c60edc17 610 /* User mode Promisc mode enable and vlan filtering is disabled to
c631c696 611 * let all packets in.
c60edc17 612 */
c60edc17 613 h->netdev_flags = new_flags;
c631c696
JS		 614 hns3_request_update_promisc_mode(h);
615}
616
617void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
618{
619 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
620
621 if (ops->request_update_promisc_mode)
622 ops->request_update_promisc_mode(handle);
c60edc17
JS		 623}
624
7fa6be4f 625int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
c60edc17
JS		 626{
627 struct hns3_nic_priv *priv = netdev_priv(netdev);
628 struct hnae3_handle *h = priv->ae_handle;
629
630 if (h->ae_algo->ops->set_promisc_mode) {
7fa6be4f
HT		 631 return h->ae_algo->ops->set_promisc_mode(h,
632 promisc_flags & HNAE3_UPE,
633 promisc_flags & HNAE3_MPE);
c60edc17 634 }
7fa6be4f
HT		 635
636 return 0;
c60edc17
JS		 637}
638
639void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
640{
641 struct hns3_nic_priv *priv = netdev_priv(netdev);
642 struct hnae3_handle *h = priv->ae_handle;
643 bool last_state;
644
645 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
646 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
647 if (enable != last_state) {
648 netdev_info(netdev,
649 "%s vlan filter\n",
650 enable ? "enable" : "disable");
651 h->ae_algo->ops->enable_vlan_filter(h, enable);
652 }
40cca1c5 653 }
76ad4f0e
S		 654}
655
656static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
657 u16 *mss, u32 *type_cs_vlan_tso)
658{
659 u32 l4_offset, hdr_len;
660 union l3_hdr_info l3;
661 union l4_hdr_info l4;
662 u32 l4_paylen;
663 int ret;
664
665 if (!skb_is_gso(skb))
666 return 0;
667
668 ret = skb_cow_head(skb, 0);
8ae10cfb 669 if (unlikely(ret < 0))
76ad4f0e
S		 670 return ret;
671
672 l3.hdr = skb_network_header(skb);
673 l4.hdr = skb_transport_header(skb);
674
675 /* Software should clear the IPv4's checksum field when tso is
676 * needed.
677 */
678 if (l3.v4->version == 4)
679 l3.v4->check = 0;
680
9b2f3477 681 /* tunnel packet */
76ad4f0e
S		 682 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
683 SKB_GSO_GRE_CSUM |
684 SKB_GSO_UDP_TUNNEL |
685 SKB_GSO_UDP_TUNNEL_CSUM)) {
686 if ((!(skb_shinfo(skb)->gso_type &
687 SKB_GSO_PARTIAL)) &&
688 (skb_shinfo(skb)->gso_type &
689 SKB_GSO_UDP_TUNNEL_CSUM)) {
690 /* Software should clear the udp's checksum
691 * field when tso is needed.
692 */
693 l4.udp->check = 0;
694 }
695 /* reset l3&l4 pointers from outer to inner headers */
696 l3.hdr = skb_inner_network_header(skb);
697 l4.hdr = skb_inner_transport_header(skb);
698
699 /* Software should clear the IPv4's checksum field when
700 * tso is needed.
701 */
702 if (l3.v4->version == 4)
703 l3.v4->check = 0;
704 }
705
9b2f3477 706 /* normal or tunnel packet */
76ad4f0e 707 l4_offset = l4.hdr - skb->data;
3fe13ed9 708 hdr_len = (l4.tcp->doff << 2) + l4_offset;
76ad4f0e 709
9b2f3477 710 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e
S		 711 l4_paylen = skb->len - l4_offset;
712 csum_replace_by_diff(&l4.tcp->check,
713 (__force __wsum)htonl(l4_paylen));
714
715 /* find the txbd field values */
716 *paylen = skb->len - hdr_len;
cde4ffad 717 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 718
719 /* get MSS for TSO */
720 *mss = skb_shinfo(skb)->gso_size;
721
698a8954
YL		 722 trace_hns3_tso(skb);
723
76ad4f0e
S		 724 return 0;
725}
726
1898d4e4
S		 727static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
728 u8 *il4_proto)
76ad4f0e 729{
1a6e552d 730 union l3_hdr_info l3;
76ad4f0e
S		 731 unsigned char *l4_hdr;
732 unsigned char *exthdr;
733 u8 l4_proto_tmp;
734 __be16 frag_off;
735
736 /* find outer header point */
737 l3.hdr = skb_network_header(skb);
35f58fd7 738 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 739
740 if (skb->protocol == htons(ETH_P_IPV6)) {
741 exthdr = l3.hdr + sizeof(*l3.v6);
742 l4_proto_tmp = l3.v6->nexthdr;
743 if (l4_hdr != exthdr)
744 ipv6_skip_exthdr(skb, exthdr - skb->data,
745 &l4_proto_tmp, &frag_off);
746 } else if (skb->protocol == htons(ETH_P_IP)) {
747 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 748 } else {
749 return -EINVAL;
76ad4f0e
S		 750 }
751
752 *ol4_proto = l4_proto_tmp;
753
754 /* tunnel packet */
755 if (!skb->encapsulation) {
756 *il4_proto = 0;
1898d4e4 757 return 0;
76ad4f0e
S		 758 }
759
760 /* find inner header point */
761 l3.hdr = skb_inner_network_header(skb);
762 l4_hdr = skb_inner_transport_header(skb);
763
764 if (l3.v6->version == 6) {
765 exthdr = l3.hdr + sizeof(*l3.v6);
766 l4_proto_tmp = l3.v6->nexthdr;
767 if (l4_hdr != exthdr)
768 ipv6_skip_exthdr(skb, exthdr - skb->data,
769 &l4_proto_tmp, &frag_off);
770 } else if (l3.v4->version == 4) {
771 l4_proto_tmp = l3.v4->protocol;
772 }
773
774 *il4_proto = l4_proto_tmp;
1898d4e4
S		 775
776 return 0;
76ad4f0e
S		 777}
778
3db084d2
YL		 779/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
780 * and it is udp packet, which has a dest port as the IANA assigned.
781 * the hardware is expected to do the checksum offload, but the
782 * hardware will not do the checksum offload when udp dest port is
783 * 4789.
784 */
785static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
786{
1a6e552d 787 union l4_hdr_info l4;
3db084d2
YL		 788
789 l4.hdr = skb_transport_header(skb);
790
bea96410
MS		 791 if (!(!skb->encapsulation &&
792 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
3db084d2
YL		 793 return false;
794
795 skb_checksum_help(skb);
796
797 return true;
798}
799
757cd1e4
YL		 800static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
801 u32 *ol_type_vlan_len_msec)
76ad4f0e 802{
757cd1e4
YL		 803 u32 l2_len, l3_len, l4_len;
804 unsigned char *il2_hdr;
1a6e552d 805 union l3_hdr_info l3;
757cd1e4 806 union l4_hdr_info l4;
76ad4f0e
S		 807
808 l3.hdr = skb_network_header(skb);
757cd1e4 809 l4.hdr = skb_transport_header(skb);
76ad4f0e 810
757cd1e4
YL		 811 /* compute OL2 header size, defined in 2 Bytes */
812 l2_len = l3.hdr - skb->data;
813 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
814
815 /* compute OL3 header size, defined in 4 Bytes */
816 l3_len = l4.hdr - l3.hdr;
817 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 818
757cd1e4 819 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 820 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL		 821 l4_len = il2_hdr - l4.hdr;
822 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
823
824 /* define outer network header type */
825 if (skb->protocol == htons(ETH_P_IP)) {
826 if (skb_is_gso(skb))
cde4ffad 827 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 828 HNS3_TXD_OL3T_S,
829 HNS3_OL3T_IPV4_CSUM);
830 else
cde4ffad 831 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 832 HNS3_TXD_OL3T_S,
833 HNS3_OL3T_IPV4_NO_CSUM);
834
835 } else if (skb->protocol == htons(ETH_P_IPV6)) {
836 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
837 HNS3_OL3T_IPV6);
838 }
839
840 if (ol4_proto == IPPROTO_UDP)
841 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
842 HNS3_TUN_MAC_IN_UDP);
843 else if (ol4_proto == IPPROTO_GRE)
844 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
845 HNS3_TUN_NVGRE);
846}
847
848static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
849 u8 il4_proto, u32 *type_cs_vlan_tso,
850 u32 *ol_type_vlan_len_msec)
851{
c264ed44 852 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 853 u32 l4_proto = ol4_proto;
854 union l4_hdr_info l4;
855 union l3_hdr_info l3;
856 u32 l2_len, l3_len;
857
858 l4.hdr = skb_transport_header(skb);
859 l3.hdr = skb_network_header(skb);
860
861 /* handle encapsulation skb */
862 if (skb->encapsulation) {
863 /* If this is a not UDP/GRE encapsulation skb */
864 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 865 /* drop the skb tunnel packet if hardware don't support,
866 * because hardware can't calculate csum when TSO.
867 */
868 if (skb_is_gso(skb))
869 return -EDOM;
870
871 /* the stack computes the IP header already,
872 * driver calculate l4 checksum when not TSO.
873 */
874 skb_checksum_help(skb);
875 return 0;
876 }
877
757cd1e4
YL		 878 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
879
880 /* switch to inner header */
881 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 882 l3.hdr = skb_inner_network_header(skb);
757cd1e4 883 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 884 l4_proto = il4_proto;
885 }
886
887 if (l3.v4->version == 4) {
cde4ffad
YL		 888 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
889 HNS3_L3T_IPV4);
76ad4f0e
S		 890
891 /* the stack computes the IP header already, the only time we
892 * need the hardware to recompute it is in the case of TSO.
893 */
894 if (skb_is_gso(skb))
cde4ffad 895 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 896 } else if (l3.v6->version == 6) {
cde4ffad
YL		 897 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
898 HNS3_L3T_IPV6);
76ad4f0e
S		 899 }
900
757cd1e4
YL		 901 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
902 l2_len = l3.hdr - l2_hdr;
903 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
904
905 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
906 l3_len = l4.hdr - l3.hdr;
907 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
908
909 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 910 switch (l4_proto) {
911 case IPPROTO_TCP:
cde4ffad
YL		 912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
913 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
914 HNS3_L4T_TCP);
757cd1e4
YL		 915 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
916 l4.tcp->doff);
76ad4f0e
S		 917 break;
918 case IPPROTO_UDP:
3db084d2
YL		 919 if (hns3_tunnel_csum_bug(skb))
920 break;
921
cde4ffad
YL		 922 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
923 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
924 HNS3_L4T_UDP);
757cd1e4
YL		 925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
926 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 927 break;
928 case IPPROTO_SCTP:
cde4ffad
YL		 929 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
931 HNS3_L4T_SCTP);
757cd1e4
YL		 932 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
933 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 934 break;
935 default:
936 /* drop the skb tunnel packet if hardware don't support,
937 * because hardware can't calculate csum when TSO.
938 */
939 if (skb_is_gso(skb))
940 return -EDOM;
941
942 /* the stack computes the IP header already,
943 * driver calculate l4 checksum when not TSO.
944 */
945 skb_checksum_help(skb);
946 return 0;
947 }
948
949 return 0;
950}
951
eb977d99
YL		 952static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
953 struct sk_buff *skb)
9699cffe 954{
44e626f7 955 struct hnae3_handle *handle = tx_ring->tqp->handle;
eb977d99
YL		 956 struct vlan_ethhdr *vhdr;
957 int rc;
958
959 if (!(skb->protocol == htons(ETH_P_8021Q) ||
960 skb_vlan_tag_present(skb)))
961 return 0;
44e626f7
JS		 962
963 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
964 * header is allowed in skb, otherwise it will cause RAS error.
965 */
966 if (unlikely(skb_vlan_tagged_multi(skb) &&
967 handle->port_base_vlan_state ==
968 HNAE3_PORT_BASE_VLAN_ENABLE))
969 return -EINVAL;
970
9699cffe 971 if (skb->protocol == htons(ETH_P_8021Q) &&
eb977d99 972 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
9699cffe
PL		 973 /* When HW VLAN acceleration is turned off, and the stack
974 * sets the protocol to 802.1q, the driver just need to
975 * set the protocol to the encapsulated ethertype.
976 */
977 skb->protocol = vlan_get_protocol(skb);
978 return 0;
979 }
980
981 if (skb_vlan_tag_present(skb)) {
9699cffe
PL		 982 /* Based on hw strategy, use out_vtag in two layer tag case,
983 * and use inner_vtag in one tag case.
984 */
eb977d99
YL		 985 if (skb->protocol == htons(ETH_P_8021Q) &&
986 handle->port_base_vlan_state ==
987 HNAE3_PORT_BASE_VLAN_DISABLE)
988 rc = HNS3_OUTER_VLAN_TAG;
989 else
990 rc = HNS3_INNER_VLAN_TAG;
991
992 skb->protocol = vlan_get_protocol(skb);
993 return rc;
9699cffe
PL		 994 }
995
eb977d99
YL		 996 rc = skb_cow_head(skb, 0);
997 if (unlikely(rc < 0))
998 return rc;
999
1000 vhdr = (struct vlan_ethhdr *)skb->data;
1001 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1002 & VLAN_PRIO_MASK);
1003
9699cffe
PL		 1004 skb->protocol = vlan_get_protocol(skb);
1005 return 0;
1006}
1007
eb977d99
YL		 1008static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1009 struct sk_buff *skb, struct hns3_desc *desc)
1010{
1011 u32 ol_type_vlan_len_msec = 0;
1012 u32 type_cs_vlan_tso = 0;
1013 u32 paylen = skb->len;
1014 u16 inner_vtag = 0;
1015 u16 out_vtag = 0;
1016 u16 mss = 0;
1017 int ret;
1018
1019 ret = hns3_handle_vtags(ring, skb);
1020 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1021 u64_stats_update_begin(&ring->syncp);
1022 ring->stats.tx_vlan_err++;
1023 u64_stats_update_end(&ring->syncp);
eb977d99
YL		 1024 return ret;
1025 } else if (ret == HNS3_INNER_VLAN_TAG) {
1026 inner_vtag = skb_vlan_tag_get(skb);
1027 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1028 VLAN_PRIO_MASK;
1029 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1030 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1031 out_vtag = skb_vlan_tag_get(skb);
1032 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1033 VLAN_PRIO_MASK;
1034 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1035 1);
1036 }
1037
1038 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1039 u8 ol4_proto, il4_proto;
1040
1041 skb_reset_mac_len(skb);
1042
1043 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
8ae10cfb 1044 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1045 u64_stats_update_begin(&ring->syncp);
1046 ring->stats.tx_l4_proto_err++;
1047 u64_stats_update_end(&ring->syncp);
eb977d99 1048 return ret;
b20d7fe5 1049 }
eb977d99
YL		 1050
1051 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1052 &type_cs_vlan_tso,
1053 &ol_type_vlan_len_msec);
8ae10cfb 1054 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1055 u64_stats_update_begin(&ring->syncp);
1056 ring->stats.tx_l2l3l4_err++;
1057 u64_stats_update_end(&ring->syncp);
eb977d99 1058 return ret;
b20d7fe5 1059 }
eb977d99
YL		 1060
1061 ret = hns3_set_tso(skb, &paylen, &mss,
1062 &type_cs_vlan_tso);
8ae10cfb 1063 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1064 u64_stats_update_begin(&ring->syncp);
1065 ring->stats.tx_tso_err++;
1066 u64_stats_update_end(&ring->syncp);
eb977d99 1067 return ret;
b20d7fe5 1068 }
eb977d99
YL		 1069 }
1070
1071 /* Set txbd */
1072 desc->tx.ol_type_vlan_len_msec =
1073 cpu_to_le32(ol_type_vlan_len_msec);
1074 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1075 desc->tx.paylen = cpu_to_le32(paylen);
1076 desc->tx.mss = cpu_to_le16(mss);
1077 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1078 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1079
1080 return 0;
1081}
1082
76ad4f0e 1083static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
8ae10cfb 1084 unsigned int size, enum hns_desc_type type)
76ad4f0e 1085{
8ae10cfb
YL		 1086#define HNS3_LIKELY_BD_NUM 1
1087
76ad4f0e
S		 1088 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1089 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1090 struct device *dev = ring_to_dev(ring);
d7840976 1091 skb_frag_t *frag;
1e8a7977 1092 unsigned int frag_buf_num;
47e7b13b 1093 int k, sizeoflast;
5188f218 1094 dma_addr_t dma;
76ad4f0e 1095
76ad4f0e 1096 if (type == DESC_TYPE_SKB) {
47e7b13b 1097 struct sk_buff *skb = (struct sk_buff *)priv;
47e7b13b 1098 int ret;
76ad4f0e 1099
eb977d99 1100 ret = hns3_fill_skb_desc(ring, skb, desc);
8ae10cfb 1101 if (unlikely(ret < 0))
9699cffe
PL		 1102 return ret;
1103
74ef402e
HT		 1104 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1105 } else if (type == DESC_TYPE_FRAGLIST_SKB) {
1106 struct sk_buff *skb = (struct sk_buff *)priv;
1107
5188f218
PL		 1108 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1109 } else {
d7840976 1110 frag = (skb_frag_t *)priv;
5188f218
PL		 1111 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1112 }
1113
845e0d1d 1114 if (unlikely(dma_mapping_error(dev, dma))) {
b20d7fe5 1115 u64_stats_update_begin(&ring->syncp);
5188f218 1116 ring->stats.sw_err_cnt++;
b20d7fe5 1117 u64_stats_update_end(&ring->syncp);
5188f218 1118 return -ENOMEM;
76ad4f0e
S		 1119 }
1120
0ec3b6a7 1121 desc_cb->priv = priv;
bcdb12b7 1122 desc_cb->length = size;
0ec3b6a7
YL		 1123 desc_cb->dma = dma;
1124 desc_cb->type = type;
bcdb12b7 1125
ceca4a5e 1126 if (likely(size <= HNS3_MAX_BD_SIZE)) {
ceca4a5e
YL		 1127 desc->addr = cpu_to_le64(dma);
1128 desc->tx.send_size = cpu_to_le16(size);
ceca4a5e 1129 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1130 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
ceca4a5e 1131
698a8954 1132 trace_hns3_tx_desc(ring, ring->next_to_use);
ceca4a5e 1133 ring_ptr_move_fw(ring, next_to_use);
8ae10cfb 1134 return HNS3_LIKELY_BD_NUM;
ceca4a5e
YL		 1135 }
1136
5f543a54 1137 frag_buf_num = hns3_tx_bd_count(size);
48ae74c9 1138 sizeoflast = size % HNS3_MAX_BD_SIZE;
1e8a7977
FL		 1139 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1140
1141 /* When frag size is bigger than hardware limit, split this frag */
1142 for (k = 0; k < frag_buf_num; k++) {
1e8a7977
FL		 1143 /* now, fill the descriptor */
1144 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1145 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1146 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977 1147 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1148 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1e8a7977 1149
698a8954 1150 trace_hns3_tx_desc(ring, ring->next_to_use);
9b2f3477 1151 /* move ring pointer to next */
1e8a7977
FL		 1152 ring_ptr_move_fw(ring, next_to_use);
1153
1e8a7977
FL		 1154 desc = &ring->desc[ring->next_to_use];
1155 }
76ad4f0e 1156
8ae10cfb 1157 return frag_buf_num;
76ad4f0e
S		 1158}
1159
8ae10cfb
YL		 1160static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1161 unsigned int bd_num)
76ad4f0e 1162{
8ae10cfb 1163 unsigned int size;
42611b70 1164 int i;
76ad4f0e 1165
8ae10cfb
YL		 1166 size = skb_headlen(skb);
1167 while (size > HNS3_MAX_BD_SIZE) {
1168 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1169 size -= HNS3_MAX_BD_SIZE;
1170
1171 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1172 return bd_num;
1173 }
76ad4f0e 1174
8ae10cfb
YL		 1175 if (size) {
1176 bd_size[bd_num++] = size;
1177 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1178 return bd_num;
1179 }
76ad4f0e 1180
3d5f3741 1181 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
d7840976 1182 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8ae10cfb
YL		 1183 size = skb_frag_size(frag);
1184 if (!size)
1185 continue;
1186
1187 while (size > HNS3_MAX_BD_SIZE) {
1188 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1189 size -= HNS3_MAX_BD_SIZE;
1190
1191 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1192 return bd_num;
1193 }
1194
1195 bd_size[bd_num++] = size;
1196 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1197 return bd_num;
1198 }
1199
1200 return bd_num;
1201}
1202
1203static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1204{
1205 struct sk_buff *frag_skb;
1206 unsigned int bd_num = 0;
1207
1208 /* If the total len is within the max bd limit */
1209 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1210 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1211 return skb_shinfo(skb)->nr_frags + 1U;
1212
1213 /* The below case will always be linearized, return
1214 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1215 */
1216 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1217 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1218 return HNS3_MAX_TSO_BD_NUM + 1U;
1219
1220 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1221
1222 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1223 return bd_num;
1224
1225 skb_walk_frags(skb, frag_skb) {
1226 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1227 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1228 return bd_num;
3d5f3741 1229 }
76ad4f0e 1230
3d5f3741 1231 return bd_num;
76ad4f0e
S		 1232}
1233
db4970aa
YL		 1234static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1235{
1236 if (!skb->encapsulation)
1237 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1238
1239 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1240}
1241
1242/* HW need every continuous 8 buffer data to be larger than MSS,
1243 * we simplify it by ensuring skb_headlen + the first continuous
1244 * 7 frags to to be larger than gso header len + mss, and the remaining
1245 * continuous 7 frags to be larger than MSS except the last 7 frags.
1246 */
8ae10cfb
YL		 1247static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1248 unsigned int bd_num)
db4970aa 1249{
db4970aa
YL		 1250 unsigned int tot_len = 0;
1251 int i;
1252
8ae10cfb
YL		 1253 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1254 tot_len += bd_size[i];
db4970aa 1255
8ae10cfb
YL		 1256 /* ensure the first 8 frags is greater than mss + header */
1257 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1258 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
db4970aa
YL		 1259 return true;
1260
8ae10cfb
YL		 1261 /* ensure every continuous 7 buffer is greater than mss
1262 * except the last one.
1263 */
1264 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1265 tot_len -= bd_size[i];
1266 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
db4970aa
YL		 1267
1268 if (tot_len < skb_shinfo(skb)->gso_size)
1269 return true;
1270 }
1271
1272 return false;
1273}
1274
698a8954
YL		 1275void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1276{
1277 int i = 0;
1278
1279 for (i = 0; i < MAX_SKB_FRAGS; i++)
1280 size[i] = skb_frag_size(&shinfo->frags[i]);
1281}
1282
3d5f3741 1283static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
2a597eff 1284 struct net_device *netdev,
d1a37ded 1285 struct sk_buff *skb)
76ad4f0e 1286{
2a597eff 1287 struct hns3_nic_priv *priv = netdev_priv(netdev);
8ae10cfb 1288 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
42611b70 1289 unsigned int bd_num;
76ad4f0e 1290
8ae10cfb
YL		 1291 bd_num = hns3_tx_bd_num(skb, bd_size);
1292 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
8ae10cfb 1293 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
698a8954
YL		 1294 !hns3_skb_need_linearized(skb, bd_size, bd_num)) {
1295 trace_hns3_over_8bd(skb);
db4970aa 1296 goto out;
698a8954 1297 }
db4970aa 1298
d1a37ded 1299 if (__skb_linearize(skb))
51e8439f 1300 return -ENOMEM;
3d5f3741 1301
d1a37ded
YL		 1302 bd_num = hns3_tx_bd_count(skb->len);
1303 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1304 (!skb_is_gso(skb) &&
698a8954
YL		 1305 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1306 trace_hns3_over_8bd(skb);
42611b70 1307 return -ENOMEM;
698a8954 1308 }
42611b70 1309
3d5f3741
YL		 1310 u64_stats_update_begin(&ring->syncp);
1311 ring->stats.tx_copy++;
1312 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1313 }
1314
db4970aa 1315out:
2a597eff
YL		 1316 if (likely(ring_space(ring) >= bd_num))
1317 return bd_num;
76ad4f0e 1318
2a597eff
YL		 1319 netif_stop_subqueue(netdev, ring->queue_index);
1320 smp_mb(); /* Memory barrier before checking ring_space */
1321
1322 /* Start queue in case hns3_clean_tx_ring has just made room
1323 * available and has not seen the queue stopped state performed
1324 * by netif_stop_subqueue above.
1325 */
1326 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1327 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1328 netif_start_subqueue(netdev, ring->queue_index);
1329 return bd_num;
1330 }
1331
1332 return -EBUSY;
76ad4f0e
S		 1333}
1334
ba3f808f 1335static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1336{
1337 struct device *dev = ring_to_dev(ring);
1338 unsigned int i;
1339
1340 for (i = 0; i < ring->desc_num; i++) {
1341 /* check if this is where we started */
1342 if (ring->next_to_use == next_to_use_orig)
1343 break;
1344
aa9d22dd
YL		 1345 /* rollback one */
1346 ring_ptr_move_bw(ring, next_to_use);
1347
76ad4f0e 1348 /* unmap the descriptor dma address */
74ef402e
HT		 1349 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
1350 ring->desc_cb[ring->next_to_use].type ==
1351 DESC_TYPE_FRAGLIST_SKB)
76ad4f0e
S		 1352 dma_unmap_single(dev,
1353 ring->desc_cb[ring->next_to_use].dma,
1354 ring->desc_cb[ring->next_to_use].length,
1355 DMA_TO_DEVICE);
bcdb12b7 1356 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1357 dma_unmap_page(dev,
1358 ring->desc_cb[ring->next_to_use].dma,
1359 ring->desc_cb[ring->next_to_use].length,
1360 DMA_TO_DEVICE);
1361
bcdb12b7 1362 ring->desc_cb[ring->next_to_use].length = 0;
aa9d22dd 1363 ring->desc_cb[ring->next_to_use].dma = 0;
76ad4f0e
S		 1364 }
1365}
1366
8ae10cfb
YL		 1367static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1368 struct sk_buff *skb, enum hns_desc_type type)
1369{
1370 unsigned int size = skb_headlen(skb);
1371 int i, ret, bd_num = 0;
1372
1373 if (size) {
1374 ret = hns3_fill_desc(ring, skb, size, type);
1375 if (unlikely(ret < 0))
1376 return ret;
1377
1378 bd_num += ret;
1379 }
1380
1381 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1382 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1383
1384 size = skb_frag_size(frag);
1385 if (!size)
1386 continue;
1387
1388 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1389 if (unlikely(ret < 0))
1390 return ret;
1391
1392 bd_num += ret;
1393 }
1394
1395 return bd_num;
1396}
1397
d43e5aca 1398netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1399{
1400 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f06b903 1401 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
76ad4f0e 1402 struct netdev_queue *dev_queue;
8ae10cfb
YL		 1403 int pre_ntu, next_to_use_head;
1404 struct sk_buff *frag_skb;
1405 int bd_num = 0;
76ad4f0e 1406 int ret;
76ad4f0e 1407
36c67349
YL		 1408 /* Hardware can only handle short frames above 32 bytes */
1409 if (skb_put_padto(skb, HNS3_MIN_TX_LEN))
1410 return NETDEV_TX_OK;
1411
76ad4f0e
S		 1412 /* Prefetch the data used later */
1413 prefetch(skb->data);
1414
d1a37ded 1415 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
8ae10cfb
YL		 1416 if (unlikely(ret <= 0)) {
1417 if (ret == -EBUSY) {
3d5f3741
YL		 1418 u64_stats_update_begin(&ring->syncp);
1419 ring->stats.tx_busy++;
1420 u64_stats_update_end(&ring->syncp);
2a597eff 1421 return NETDEV_TX_BUSY;
8ae10cfb 1422 } else if (ret == -ENOMEM) {
3d5f3741
YL		 1423 u64_stats_update_begin(&ring->syncp);
1424 ring->stats.sw_err_cnt++;
1425 u64_stats_update_end(&ring->syncp);
1426 }
76ad4f0e 1427
8ae10cfb 1428 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
76ad4f0e 1429 goto out_err_tx_ok;
76ad4f0e
S		 1430 }
1431
76ad4f0e
S		 1432 next_to_use_head = ring->next_to_use;
1433
8ae10cfb
YL		 1434 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1435 if (unlikely(ret < 0))
aa9d22dd 1436 goto fill_err;
76ad4f0e 1437
8ae10cfb 1438 bd_num += ret;
5188f218 1439
8ae10cfb 1440 skb_walk_frags(skb, frag_skb) {
74ef402e
HT		 1441 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1442 DESC_TYPE_FRAGLIST_SKB);
8ae10cfb 1443 if (unlikely(ret < 0))
aa9d22dd 1444 goto fill_err;
8ae10cfb
YL		 1445
1446 bd_num += ret;
76ad4f0e 1447 }
5c6cfd30 1448
8ae10cfb
YL		 1449 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1450 (ring->desc_num - 1);
1451 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1452 cpu_to_le16(BIT(HNS3_TXD_FE_B));
698a8954 1453 trace_hns3_tx_desc(ring, pre_ntu);
76ad4f0e
S		 1454
1455 /* Complete translate all packets */
5f06b903 1456 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
76ad4f0e
S		 1457 netdev_tx_sent_queue(dev_queue, skb->len);
1458
1459 wmb(); /* Commit all data before submit */
1460
8ae10cfb 1461 hnae3_queue_xmit(ring->tqp, bd_num);
76ad4f0e
S		 1462
1463 return NETDEV_TX_OK;
1464
aa9d22dd 1465fill_err:
ba3f808f 1466 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1467
1468out_err_tx_ok:
1469 dev_kfree_skb_any(skb);
1470 return NETDEV_TX_OK;
76ad4f0e
S		 1471}
1472
1473static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1474{
9780cb97 1475 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1476 struct sockaddr *mac_addr = p;
1477 int ret;
1478
1479 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1480 return -EADDRNOTAVAIL;
1481
5ec2a51e
JS		 1482 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1483 netdev_info(netdev, "already using mac address %pM\n",
1484 mac_addr->sa_data);
1485 return 0;
1486 }
1487
8e6de441
HT		 1488 /* For VF device, if there is a perm_addr, then the user will not
1489 * be allowed to change the address.
1490 */
1491 if (!hns3_is_phys_func(h->pdev) &&
1492 !is_zero_ether_addr(netdev->perm_addr)) {
1493 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1494 netdev->perm_addr, mac_addr->sa_data);
1495 return -EPERM;
1496 }
1497
59098055 1498 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1499 if (ret) {
1500 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1501 return ret;
1502 }
1503
1504 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1505
1506 return 0;
1507}
1508
26483246
XW		 1509static int hns3_nic_do_ioctl(struct net_device *netdev,
1510 struct ifreq *ifr, int cmd)
1511{
1512 struct hnae3_handle *h = hns3_get_handle(netdev);
1513
1514 if (!netif_running(netdev))
1515 return -EINVAL;
1516
1517 if (!h->ae_algo->ops->do_ioctl)
1518 return -EOPNOTSUPP;
1519
1520 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1521}
1522
76ad4f0e
S		 1523static int hns3_nic_set_features(struct net_device *netdev,
1524 netdev_features_t features)
1525{
181d454b 1526 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1527 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1528 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1529 bool enable;
052ece6d 1530 int ret;
76ad4f0e 1531
5c9f6b39 1532 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 1533 enable = !!(features & NETIF_F_GRO_HW);
1534 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 1535 if (ret)
1536 return ret;
1537 }
1538
bd368416
JS		 1539 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1540 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 1541 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1542 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 1543 if (ret)
1544 return ret;
1545 }
1546
c17852a8 1547 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 1548 enable = !!(features & NETIF_F_NTUPLE);
1549 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 1550 }
1551
76ad4f0e
S		 1552 netdev->features = features;
1553 return 0;
1554}
1555
2a7556bb
YL		 1556static netdev_features_t hns3_features_check(struct sk_buff *skb,
1557 struct net_device *dev,
1558 netdev_features_t features)
1559{
1560#define HNS3_MAX_HDR_LEN 480U
1561#define HNS3_MAX_L4_HDR_LEN 60U
1562
1563 size_t len;
1564
1565 if (skb->ip_summed != CHECKSUM_PARTIAL)
1566 return features;
1567
1568 if (skb->encapsulation)
1569 len = skb_inner_transport_header(skb) - skb->data;
1570 else
1571 len = skb_transport_header(skb) - skb->data;
1572
1573 /* Assume L4 is 60 byte as TCP is the only protocol with a
1574 * a flexible value, and it's max len is 60 bytes.
1575 */
1576 len += HNS3_MAX_L4_HDR_LEN;
1577
1578 /* Hardware only supports checksum on the skb with a max header
1579 * len of 480 bytes.
1580 */
1581 if (len > HNS3_MAX_HDR_LEN)
1582 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1583
1584 return features;
1585}
1586
6c88d9d7
PL		 1587static void hns3_nic_get_stats64(struct net_device *netdev,
1588 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1589{
1590 struct hns3_nic_priv *priv = netdev_priv(netdev);
1591 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1592 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1593 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 1594 u64 rx_length_errors = 0;
1595 u64 rx_crc_errors = 0;
1596 u64 rx_multicast = 0;
76ad4f0e 1597 unsigned int start;
d3ec4ef6
JS		 1598 u64 tx_errors = 0;
1599 u64 rx_errors = 0;
76ad4f0e
S		 1600 unsigned int idx;
1601 u64 tx_bytes = 0;
1602 u64 rx_bytes = 0;
1603 u64 tx_pkts = 0;
1604 u64 rx_pkts = 0;
d2a5dca8
JS		 1605 u64 tx_drop = 0;
1606 u64 rx_drop = 0;
76ad4f0e 1607
b875cc37
JS		 1608 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1609 return;
1610
c5f65480
JS		 1611 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1612
76ad4f0e
S		 1613 for (idx = 0; idx < queue_num; idx++) {
1614 /* fetch the tx stats */
5f06b903 1615 ring = &priv->ring[idx];
76ad4f0e 1616 do {
d36d36ce 1617 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1618 tx_bytes += ring->stats.tx_bytes;
1619 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1620 tx_drop += ring->stats.sw_err_cnt;
b20d7fe5
YL		 1621 tx_drop += ring->stats.tx_vlan_err;
1622 tx_drop += ring->stats.tx_l4_proto_err;
1623 tx_drop += ring->stats.tx_l2l3l4_err;
1624 tx_drop += ring->stats.tx_tso_err;
d3ec4ef6 1625 tx_errors += ring->stats.sw_err_cnt;
b20d7fe5
YL		 1626 tx_errors += ring->stats.tx_vlan_err;
1627 tx_errors += ring->stats.tx_l4_proto_err;
1628 tx_errors += ring->stats.tx_l2l3l4_err;
1629 tx_errors += ring->stats.tx_tso_err;
76ad4f0e
S		 1630 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1631
1632 /* fetch the rx stats */
5f06b903 1633 ring = &priv->ring[idx + queue_num];
76ad4f0e 1634 do {
d36d36ce 1635 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1636 rx_bytes += ring->stats.rx_bytes;
1637 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1638 rx_drop += ring->stats.l2_err;
d3ec4ef6 1639 rx_errors += ring->stats.l2_err;
8b552079 1640 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 1641 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS		 1642 rx_multicast += ring->stats.rx_multicast;
1643 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 1644 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1645 }
1646
1647 stats->tx_bytes = tx_bytes;
1648 stats->tx_packets = tx_pkts;
1649 stats->rx_bytes = rx_bytes;
1650 stats->rx_packets = rx_pkts;
1651
d3ec4ef6
JS		 1652 stats->rx_errors = rx_errors;
1653 stats->multicast = rx_multicast;
1654 stats->rx_length_errors = rx_length_errors;
1655 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 1656 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1657
d3ec4ef6
JS		 1658 stats->tx_errors = tx_errors;
1659 stats->rx_dropped = rx_drop;
1660 stats->tx_dropped = tx_drop;
76ad4f0e
S		 1661 stats->collisions = netdev->stats.collisions;
1662 stats->rx_over_errors = netdev->stats.rx_over_errors;
1663 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1664 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1665 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1666 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1667 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1668 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1669 stats->tx_window_errors = netdev->stats.tx_window_errors;
1670 stats->rx_compressed = netdev->stats.rx_compressed;
1671 stats->tx_compressed = netdev->stats.tx_compressed;
1672}
1673
30d240df 1674static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1675{
30d240df 1676 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
30d240df 1677 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
75718800 1678 struct hnae3_knic_private_info *kinfo;
30d240df
YL		 1679 u8 tc = mqprio_qopt->qopt.num_tc;
1680 u16 mode = mqprio_qopt->mode;
1681 u8 hw = mqprio_qopt->qopt.hw;
75718800 1682 struct hnae3_handle *h;
76ad4f0e 1683
30d240df
YL		 1684 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1685 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1686 return -EOPNOTSUPP;
1687
76ad4f0e
S		 1688 if (tc > HNAE3_MAX_TC)
1689 return -EINVAL;
1690
76ad4f0e
S		 1691 if (!netdev)
1692 return -EINVAL;
1693
75718800
YL		 1694 h = hns3_get_handle(netdev);
1695 kinfo = &h->kinfo;
1696
1c822948
YL		 1697 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1698
1cce5eb6 1699 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
5eb01ddf 1700 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
76ad4f0e
S		 1701}
1702
2572ac53 1703static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1704 void *type_data)
76ad4f0e 1705{
575ed7d3 1706 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1707 return -EOPNOTSUPP;
76ad4f0e 1708
30d240df 1709 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1710}
1711
1712static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1713 __be16 proto, u16 vid)
1714{
9780cb97 1715 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1716 int ret = -EIO;
1717
1718 if (h->ae_algo->ops->set_vlan_filter)
1719 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1720
1721 return ret;
1722}
1723
1724static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1725 __be16 proto, u16 vid)
1726{
9780cb97 1727 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1728 int ret = -EIO;
1729
1730 if (h->ae_algo->ops->set_vlan_filter)
1731 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1732
7fa6be4f 1733 return ret;
681ec399
YL		 1734}
1735
76ad4f0e
S		 1736static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1737 u8 qos, __be16 vlan_proto)
1738{
9780cb97 1739 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1740 int ret = -EIO;
1741
1c822948 1742 netif_dbg(h, drv, netdev,
39edaf24
GL		 1743 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1744 vf, vlan, qos, ntohs(vlan_proto));
1c822948 1745
76ad4f0e
S		 1746 if (h->ae_algo->ops->set_vf_vlan_filter)
1747 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 1748 qos, vlan_proto);
76ad4f0e
S		 1749
1750 return ret;
1751}
1752
22044f95
JS		 1753static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1754{
1755 struct hnae3_handle *handle = hns3_get_handle(netdev);
1756
1757 if (hns3_nic_resetting(netdev))
1758 return -EBUSY;
1759
1760 if (!handle->ae_algo->ops->set_vf_spoofchk)
1761 return -EOPNOTSUPP;
1762
1763 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1764}
1765
e196ec75
JS		 1766static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1767{
1768 struct hnae3_handle *handle = hns3_get_handle(netdev);
1769
1770 if (!handle->ae_algo->ops->set_vf_trust)
1771 return -EOPNOTSUPP;
1772
1773 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1774}
1775
a8e8b7ff
S		 1776static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1777{
9780cb97 1778 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1779 int ret;
1780
6ff7ed80
HT		 1781 if (hns3_nic_resetting(netdev))
1782 return -EBUSY;
1783
a8e8b7ff
S		 1784 if (!h->ae_algo->ops->set_mtu)
1785 return -EOPNOTSUPP;
1786
1c822948
YL		 1787 netif_dbg(h, drv, netdev,
1788 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1789
a8e8b7ff 1790 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1791 if (ret)
a8e8b7ff
S		 1792 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1793 ret);
93d8daf4
YL		 1794 else
1795 netdev->mtu = new_mtu;
5bad95a1 1796
a8e8b7ff
S		 1797 return ret;
1798}
1799
f8fa222c
L		 1800static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1801{
1802 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1803 struct hnae3_handle *h = hns3_get_handle(ndev);
0bfdf286 1804 struct hns3_enet_ring *tx_ring;
e511c97d 1805 struct napi_struct *napi;
f8fa222c
L		 1806 int timeout_queue = 0;
1807 int hw_head, hw_tail;
e511c97d
JS		 1808 int fbd_num, fbd_oft;
1809 int ebd_num, ebd_oft;
1810 int bd_num, bd_err;
1811 int ring_en, tc;
f8fa222c
L		 1812 int i;
1813
1814 /* Find the stopped queue the same way the stack does */
fa6c4084 1815 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 1816 struct netdev_queue *q;
1817 unsigned long trans_start;
1818
1819 q = netdev_get_tx_queue(ndev, i);
1820 trans_start = q->trans_start;
1821 if (netif_xmit_stopped(q) &&
1822 time_after(jiffies,
1823 (trans_start + ndev->watchdog_timeo))) {
1824 timeout_queue = i;
647522a5
YL		 1825 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1826 q->state,
1827 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L		 1828 break;
1829 }
1830 }
1831
1832 if (i == ndev->num_tx_queues) {
1833 netdev_info(ndev,
1834 "no netdev TX timeout queue found, timeout count: %llu\n",
1835 priv->tx_timeout_count);
1836 return false;
1837 }
1838
beab694a
JS		 1839 priv->tx_timeout_count++;
1840
5f06b903 1841 tx_ring = &priv->ring[timeout_queue];
e511c97d
JS		 1842 napi = &tx_ring->tqp_vector->napi;
1843
1844 netdev_info(ndev,
1845 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1846 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1847 tx_ring->next_to_clean, napi->state);
1848
1849 netdev_info(ndev,
1850 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1851 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1852 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1853
1854 netdev_info(ndev,
1855 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1856 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1857 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1858
1859 /* When mac received many pause frames continuous, it's unable to send
1860 * packets, which may cause tx timeout
1861 */
615466ce
YM		 1862 if (h->ae_algo->ops->get_mac_stats) {
1863 struct hns3_mac_stats mac_stats;
e511c97d 1864
615466ce 1865 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
e511c97d 1866 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
615466ce 1867 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
e511c97d 1868 }
f8fa222c
L		 1869
1870 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1871 HNS3_RING_TX_RING_HEAD_REG);
1872 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1873 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 1874 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1875 HNS3_RING_TX_RING_FBDNUM_REG);
1876 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1877 HNS3_RING_TX_RING_OFFSET_REG);
1878 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1879 HNS3_RING_TX_RING_EBDNUM_REG);
1880 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1881 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1882 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1883 HNS3_RING_TX_RING_BD_NUM_REG);
1884 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1885 HNS3_RING_TX_RING_BD_ERR_REG);
1886 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1887 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1888
f8fa222c 1889 netdev_info(ndev,
e511c97d
JS		 1890 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1891 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 1892 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 1893 netdev_info(ndev,
1894 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1895 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 1896
1897 return true;
1898}
1899
0290bd29 1900static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
f8fa222c
L		 1901{
1902 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1903 struct hnae3_handle *h = priv->ae_handle;
1904
1905 if (!hns3_get_tx_timeo_queue_info(ndev))
1906 return;
1907
0742ed7c
HT		 1908 /* request the reset, and let the hclge to determine
1909 * which reset level should be done
1910 */
f8fa222c 1911 if (h->ae_algo->ops->reset_event)
6ae4e733 1912 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1913}
1914
d93ed94f
JS		 1915#ifdef CONFIG_RFS_ACCEL
1916static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1917 u16 rxq_index, u32 flow_id)
1918{
1919 struct hnae3_handle *h = hns3_get_handle(dev);
1920 struct flow_keys fkeys;
1921
1922 if (!h->ae_algo->ops->add_arfs_entry)
1923 return -EOPNOTSUPP;
1924
1925 if (skb->encapsulation)
1926 return -EPROTONOSUPPORT;
1927
1928 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1929 return -EPROTONOSUPPORT;
1930
1931 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1932 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1933 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1934 fkeys.basic.ip_proto != IPPROTO_UDP))
1935 return -EPROTONOSUPPORT;
1936
1937 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1938}
1939#endif
1940
6430f744
YM		 1941static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1942 struct ifla_vf_info *ivf)
1943{
1944 struct hnae3_handle *h = hns3_get_handle(ndev);
1945
1946 if (!h->ae_algo->ops->get_vf_config)
1947 return -EOPNOTSUPP;
1948
1949 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1950}
1951
1952static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1953 int link_state)
1954{
1955 struct hnae3_handle *h = hns3_get_handle(ndev);
1956
1957 if (!h->ae_algo->ops->set_vf_link_state)
1958 return -EOPNOTSUPP;
1959
1960 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1961}
1962
ee9e4424
YL		 1963static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1964 int min_tx_rate, int max_tx_rate)
1965{
1966 struct hnae3_handle *h = hns3_get_handle(ndev);
1967
1968 if (!h->ae_algo->ops->set_vf_rate)
1969 return -EOPNOTSUPP;
1970
1971 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1972 false);
1973}
1974
8e6de441
HT		 1975static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1976{
1977 struct hnae3_handle *h = hns3_get_handle(netdev);
1978
1979 if (!h->ae_algo->ops->set_vf_mac)
1980 return -EOPNOTSUPP;
1981
1982 if (is_multicast_ether_addr(mac)) {
1983 netdev_err(netdev,
1984 "Invalid MAC:%pM specified. Could not set MAC\n",
1985 mac);
1986 return -EINVAL;
1987 }
1988
1989 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
1990}
1991
76ad4f0e
S		 1992static const struct net_device_ops hns3_nic_netdev_ops = {
1993 .ndo_open = hns3_nic_net_open,
1994 .ndo_stop = hns3_nic_net_stop,
1995 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1996 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1997 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1998 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1999 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e 2000 .ndo_set_features = hns3_nic_set_features,
2a7556bb 2001 .ndo_features_check = hns3_features_check,
76ad4f0e
S		 2002 .ndo_get_stats64 = hns3_nic_get_stats64,
2003 .ndo_setup_tc = hns3_nic_setup_tc,
2004 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 2005 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2006 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2007 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
22044f95 2008 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
e196ec75 2009 .ndo_set_vf_trust = hns3_set_vf_trust,
d93ed94f
JS		 2010#ifdef CONFIG_RFS_ACCEL
2011 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2012#endif
6430f744
YM		 2013 .ndo_get_vf_config = hns3_nic_get_vf_config,
2014 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
ee9e4424 2015 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
8e6de441 2016 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
76ad4f0e
S		 2017};
2018
97afd47b 2019bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 2020{
2021 u32 dev_id = pdev->device;
2022
2023 switch (dev_id) {
2024 case HNAE3_DEV_ID_GE:
2025 case HNAE3_DEV_ID_25GE:
2026 case HNAE3_DEV_ID_25GE_RDMA:
2027 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2028 case HNAE3_DEV_ID_50GE_RDMA:
2029 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2030 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2031 return true;
2032 case HNAE3_DEV_ID_100G_VF:
2033 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2034 return false;
2035 default:
adcf738b 2036 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2312e050
FL		 2037 dev_id);
2038 }
2039
2040 return false;
2041}
2042
2312e050
FL		 2043static void hns3_disable_sriov(struct pci_dev *pdev)
2044{
2045 /* If our VFs are assigned we cannot shut down SR-IOV
2046 * without causing issues, so just leave the hardware
2047 * available but disabled
2048 */
2049 if (pci_vfs_assigned(pdev)) {
2050 dev_warn(&pdev->dev,
2051 "disabling driver while VFs are assigned\n");
2052 return;
2053 }
2054
2055 pci_disable_sriov(pdev);
2056}
2057
d695964d
JS		 2058static void hns3_get_dev_capability(struct pci_dev *pdev,
2059 struct hnae3_ae_dev *ae_dev)
2060{
b26a6fea 2061 if (pdev->revision >= 0x21) {
d695964d 2062 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL		 2063 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2064 }
d695964d
JS		 2065}
2066
76ad4f0e
S		 2067/* hns3_probe - Device initialization routine
2068 * @pdev: PCI device information struct
2069 * @ent: entry in hns3_pci_tbl
2070 *
2071 * hns3_probe initializes a PF identified by a pci_dev structure.
2072 * The OS initialization, configuring of the PF private structure,
2073 * and a hardware reset occur.
2074 *
2075 * Returns 0 on success, negative on failure
2076 */
2077static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2078{
2079 struct hnae3_ae_dev *ae_dev;
2080 int ret;
2081
9b2f3477 2082 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
60df7e91
HT		 2083 if (!ae_dev)
2084 return -ENOMEM;
76ad4f0e
S		 2085
2086 ae_dev->pdev = pdev;
e92a0843 2087 ae_dev->flag = ent->driver_data;
d695964d 2088 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 2089 pci_set_drvdata(pdev, ae_dev);
2090
74354140
HT		 2091 ret = hnae3_register_ae_dev(ae_dev);
2092 if (ret) {
2093 devm_kfree(&pdev->dev, ae_dev);
2094 pci_set_drvdata(pdev, NULL);
2095 }
2312e050 2096
74354140 2097 return ret;
76ad4f0e
S		 2098}
2099
2100/* hns3_remove - Device removal routine
2101 * @pdev: PCI device information struct
2102 */
2103static void hns3_remove(struct pci_dev *pdev)
2104{
2105 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2106
2312e050
FL		 2107 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2108 hns3_disable_sriov(pdev);
2109
76ad4f0e 2110 hnae3_unregister_ae_dev(ae_dev);
ac864c23 2111 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 2112}
2113
fa8d82e8
PL		 2114/**
2115 * hns3_pci_sriov_configure
2116 * @pdev: pointer to a pci_dev structure
2117 * @num_vfs: number of VFs to allocate
2118 *
2119 * Enable or change the number of VFs. Called when the user updates the number
2120 * of VFs in sysfs.
2121 **/
743e1a84 2122static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 2123{
2124 int ret;
2125
2126 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2127 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2128 return -EINVAL;
2129 }
2130
2131 if (num_vfs) {
2132 ret = pci_enable_sriov(pdev, num_vfs);
2133 if (ret)
2134 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 2135 else
2136 return num_vfs;
fa8d82e8
PL		 2137 } else if (!pci_vfs_assigned(pdev)) {
2138 pci_disable_sriov(pdev);
2139 } else {
2140 dev_warn(&pdev->dev,
2141 "Unable to free VFs because some are assigned to VMs.\n");
2142 }
2143
2144 return 0;
2145}
2146
ce2c1d2e
YL		 2147static void hns3_shutdown(struct pci_dev *pdev)
2148{
2149 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2150
2151 hnae3_unregister_ae_dev(ae_dev);
2152 devm_kfree(&pdev->dev, ae_dev);
2153 pci_set_drvdata(pdev, NULL);
2154
2155 if (system_state == SYSTEM_POWER_OFF)
2156 pci_set_power_state(pdev, PCI_D3hot);
2157}
2158
5a9f0eac
SJ		 2159static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2160 pci_channel_state_t state)
2161{
2162 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2163 pci_ers_result_t ret;
2164
2165 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2166
2167 if (state == pci_channel_io_perm_failure)
2168 return PCI_ERS_RESULT_DISCONNECT;
2169
661262bc 2170 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 2171 dev_err(&pdev->dev,
661262bc 2172 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ		 2173 return PCI_ERS_RESULT_NONE;
2174 }
2175
381c356e
SJ		 2176 if (ae_dev->ops->handle_hw_ras_error)
2177 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 2178 else
2179 return PCI_ERS_RESULT_NONE;
2180
2181 return ret;
2182}
2183
6ae4e733
SJ		 2184static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2185{
2186 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 2187 const struct hnae3_ae_ops *ops;
123297b7 2188 enum hnae3_reset_type reset_type;
6ae4e733
SJ		 2189 struct device *dev = &pdev->dev;
2190
661262bc
WL		 2191 if (!ae_dev || !ae_dev->ops)
2192 return PCI_ERS_RESULT_NONE;
2193
ad9bf545 2194 ops = ae_dev->ops;
6ae4e733 2195 /* request the reset */
fa17c708
GH		 2196 if (ops->reset_event && ops->get_reset_level &&
2197 ops->set_default_reset_request) {
9d5e67d1 2198 if (ae_dev->hw_err_reset_req) {
123297b7
SJ		 2199 reset_type = ops->get_reset_level(ae_dev,
2200 &ae_dev->hw_err_reset_req);
2201 ops->set_default_reset_request(ae_dev, reset_type);
2202 dev_info(dev, "requesting reset due to PCI error\n");
2203 ops->reset_event(pdev, NULL);
2204 }
69b51bbb 2205
6ae4e733
SJ		 2206 return PCI_ERS_RESULT_RECOVERED;
2207 }
2208
2209 return PCI_ERS_RESULT_DISCONNECT;
2210}
2211
6b9a97ee
HT		 2212static void hns3_reset_prepare(struct pci_dev *pdev)
2213{
2214 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2215
8de91e92 2216 dev_info(&pdev->dev, "FLR prepare\n");
6b9a97ee
HT		 2217 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2218 ae_dev->ops->flr_prepare(ae_dev);
2219}
2220
2221static void hns3_reset_done(struct pci_dev *pdev)
2222{
2223 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2224
8de91e92 2225 dev_info(&pdev->dev, "FLR done\n");
6b9a97ee
HT		 2226 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2227 ae_dev->ops->flr_done(ae_dev);
2228}
2229
5a9f0eac
SJ		 2230static const struct pci_error_handlers hns3_err_handler = {
2231 .error_detected = hns3_error_detected,
6ae4e733 2232 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 2233 .reset_prepare = hns3_reset_prepare,
2234 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 2235};
2236
76ad4f0e
S		 2237static struct pci_driver hns3_driver = {
2238 .name = hns3_driver_name,
2239 .id_table = hns3_pci_tbl,
2240 .probe = hns3_probe,
2241 .remove = hns3_remove,
ce2c1d2e 2242 .shutdown = hns3_shutdown,
fa8d82e8 2243 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 2244 .err_handler = &hns3_err_handler,
76ad4f0e
S		 2245};
2246
2247/* set default feature to hns3 */
2248static void hns3_set_default_feature(struct net_device *netdev)
2249{
3e85af6a
PL		 2250 struct hnae3_handle *h = hns3_get_handle(netdev);
2251 struct pci_dev *pdev = h->pdev;
2252
76ad4f0e
S		 2253 netdev->priv_flags |= IFF_UNICAST_FLT;
2254
2255 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2256 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2257 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2258 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2259 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2260 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
76ad4f0e
S		 2261
2262 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2263
2264 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2265 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2266 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2267 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2268 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2269 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2270 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2271 NETIF_F_FRAGLIST;
76ad4f0e
S		 2272
2273 netdev->vlan_features |=
2274 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2275 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2276 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2277 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2278 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2279 NETIF_F_FRAGLIST;
76ad4f0e
S		 2280
2281 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 2282 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2283 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2284 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2285 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL		 2286 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2287 NETIF_F_FRAGLIST;
3e85af6a 2288
c17852a8 2289 if (pdev->revision >= 0x21) {
77af09c6 2290 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2291 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 2292
2293 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2294 netdev->hw_features |= NETIF_F_NTUPLE;
2295 netdev->features |= NETIF_F_NTUPLE;
2296 }
2297 }
76ad4f0e
S		 2298}
2299
2300static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2301 struct hns3_desc_cb *cb)
2302{
dbba6da0 2303 unsigned int order = hns3_page_order(ring);
76ad4f0e
S		 2304 struct page *p;
2305
2306 p = dev_alloc_pages(order);
2307 if (!p)
2308 return -ENOMEM;
2309
2310 cb->priv = p;
2311 cb->page_offset = 0;
2312 cb->reuse_flag = 0;
2313 cb->buf = page_address(p);
dbba6da0 2314 cb->length = hns3_page_size(ring);
76ad4f0e
S		 2315 cb->type = DESC_TYPE_PAGE;
2316
76ad4f0e
S		 2317 return 0;
2318}
2319
2320static void hns3_free_buffer(struct hns3_enet_ring *ring,
2321 struct hns3_desc_cb *cb)
2322{
2323 if (cb->type == DESC_TYPE_SKB)
2324 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2325 else if (!HNAE3_IS_TX_RING(ring))
2326 put_page((struct page *)cb->priv);
2327 memset(cb, 0, sizeof(*cb));
2328}
2329
2330static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2331{
2332 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2333 cb->length, ring_to_dma_dir(ring));
2334
2211f4e1 2335 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 2336 return -EIO;
2337
2338 return 0;
2339}
2340
2341static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2342 struct hns3_desc_cb *cb)
2343{
74ef402e 2344 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
76ad4f0e
S		 2345 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2346 ring_to_dma_dir(ring));
bcdb12b7 2347 else if (cb->length)
76ad4f0e
S		 2348 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2349 ring_to_dma_dir(ring));
2350}
2351
2352static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2353{
2354 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2355 ring->desc[i].addr = 0;
2356}
2357
2358static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2359{
2360 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2361
2362 if (!ring->desc_cb[i].dma)
2363 return;
2364
2365 hns3_buffer_detach(ring, i);
2366 hns3_free_buffer(ring, cb);
2367}
2368
2369static void hns3_free_buffers(struct hns3_enet_ring *ring)
2370{
2371 int i;
2372
2373 for (i = 0; i < ring->desc_num; i++)
2374 hns3_free_buffer_detach(ring, i);
2375}
2376
2377/* free desc along with its attached buffer */
2378static void hns3_free_desc(struct hns3_enet_ring *ring)
2379{
024cc792
HT		 2380 int size = ring->desc_num * sizeof(ring->desc[0]);
2381
76ad4f0e
S		 2382 hns3_free_buffers(ring);
2383
024cc792
HT		 2384 if (ring->desc) {
2385 dma_free_coherent(ring_to_dev(ring), size,
2386 ring->desc, ring->desc_dma_addr);
2387 ring->desc = NULL;
2388 }
76ad4f0e
S		 2389}
2390
2391static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2392{
2393 int size = ring->desc_num * sizeof(ring->desc[0]);
2394
750afb08
LC		 2395 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2396 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 2397 if (!ring->desc)
2398 return -ENOMEM;
2399
76ad4f0e
S		 2400 return 0;
2401}
2402
2403static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2404 struct hns3_desc_cb *cb)
2405{
2406 int ret;
2407
2408 ret = hns3_alloc_buffer(ring, cb);
2409 if (ret)
2410 goto out;
2411
2412 ret = hns3_map_buffer(ring, cb);
2413 if (ret)
2414 goto out_with_buf;
2415
2416 return 0;
2417
2418out_with_buf:
564883bb 2419 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2420out:
2421 return ret;
2422}
2423
2424static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2425{
2426 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2427
2428 if (ret)
2429 return ret;
2430
2431 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2432
2433 return 0;
2434}
2435
2436/* Allocate memory for raw pkg, and map with dma */
2437static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2438{
2439 int i, j, ret;
2440
2441 for (i = 0; i < ring->desc_num; i++) {
2442 ret = hns3_alloc_buffer_attach(ring, i);
2443 if (ret)
2444 goto out_buffer_fail;
2445 }
2446
2447 return 0;
2448
2449out_buffer_fail:
2450 for (j = i - 1; j >= 0; j--)
2451 hns3_free_buffer_detach(ring, j);
2452 return ret;
2453}
2454
9b2f3477 2455/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S		 2456static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2457 struct hns3_desc_cb *res_cb)
2458{
b9077428 2459 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2460 ring->desc_cb[i] = *res_cb;
2461 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2462 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2463}
2464
2465static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2466{
2467 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL		 2468 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2469 ring->desc_cb[i].page_offset);
7d0b130c 2470 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2471}
2472
ce74370c
YL		 2473static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2474 int *bytes, int *pkts)
76ad4f0e 2475{
26cda2f1
YL		 2476 int ntc = ring->next_to_clean;
2477 struct hns3_desc_cb *desc_cb;
76ad4f0e 2478
ce74370c
YL		 2479 while (head != ntc) {
2480 desc_cb = &ring->desc_cb[ntc];
2481 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2482 (*bytes) += desc_cb->length;
2483 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2484 hns3_free_buffer_detach(ring, ntc);
76ad4f0e 2485
ce74370c
YL		 2486 if (++ntc == ring->desc_num)
2487 ntc = 0;
2488
2489 /* Issue prefetch for next Tx descriptor */
2490 prefetch(&ring->desc_cb[ntc]);
2491 }
26cda2f1
YL		 2492
2493 /* This smp_store_release() pairs with smp_load_acquire() in
2494 * ring_space called by hns3_nic_net_xmit.
2495 */
2496 smp_store_release(&ring->next_to_clean, ntc);
76ad4f0e
S		 2497}
2498
2499static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2500{
2501 int u = ring->next_to_use;
2502 int c = ring->next_to_clean;
2503
2504 if (unlikely(h > ring->desc_num))
2505 return 0;
2506
2507 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2508}
2509
799997a3 2510void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e 2511{
c8711956 2512 struct net_device *netdev = ring_to_netdev(ring);
7a810110 2513 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2514 struct netdev_queue *dev_queue;
2515 int bytes, pkts;
2516 int head;
2517
2518 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
76ad4f0e
S		 2519
2520 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2521 return; /* no data to poll */
76ad4f0e 2522
88b7c58c
YL		 2523 rmb(); /* Make sure head is ready before touch any data */
2524
0e6084aa 2525 if (unlikely(!is_valid_clean_head(ring, head))) {
09783d44
YL		 2526 hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head,
2527 ring->next_to_use, ring->next_to_clean);
76ad4f0e
S		 2528
2529 u64_stats_update_begin(&ring->syncp);
2530 ring->stats.io_err_cnt++;
2531 u64_stats_update_end(&ring->syncp);
799997a3 2532 return;
76ad4f0e
S		 2533 }
2534
2535 bytes = 0;
2536 pkts = 0;
ce74370c 2537 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
76ad4f0e
S		 2538
2539 ring->tqp_vector->tx_group.total_bytes += bytes;
2540 ring->tqp_vector->tx_group.total_packets += pkts;
2541
2542 u64_stats_update_begin(&ring->syncp);
2543 ring->stats.tx_bytes += bytes;
2544 ring->stats.tx_pkts += pkts;
2545 u64_stats_update_end(&ring->syncp);
2546
2547 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2548 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2549
2a597eff 2550 if (unlikely(netif_carrier_ok(netdev) &&
8ae10cfb 2551 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
76ad4f0e
S		 2552 /* Make sure that anybody stopping the queue after this
2553 * sees the new next_to_clean.
2554 */
2555 smp_mb();
7a810110
JS		 2556 if (netif_tx_queue_stopped(dev_queue) &&
2557 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2558 netif_tx_wake_queue(dev_queue);
2559 ring->stats.restart_queue++;
2560 }
2561 }
76ad4f0e
S		 2562}
2563
2564static int hns3_desc_unused(struct hns3_enet_ring *ring)
2565{
2566 int ntc = ring->next_to_clean;
2567 int ntu = ring->next_to_use;
2568
2569 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2570}
2571
9b2f3477
WL		 2572static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2573 int cleand_count)
76ad4f0e
S		 2574{
2575 struct hns3_desc_cb *desc_cb;
2576 struct hns3_desc_cb res_cbs;
2577 int i, ret;
2578
2579 for (i = 0; i < cleand_count; i++) {
2580 desc_cb = &ring->desc_cb[ring->next_to_use];
2581 if (desc_cb->reuse_flag) {
2582 u64_stats_update_begin(&ring->syncp);
2583 ring->stats.reuse_pg_cnt++;
2584 u64_stats_update_end(&ring->syncp);
2585
2586 hns3_reuse_buffer(ring, ring->next_to_use);
2587 } else {
2588 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2589 if (ret) {
2590 u64_stats_update_begin(&ring->syncp);
2591 ring->stats.sw_err_cnt++;
2592 u64_stats_update_end(&ring->syncp);
2593
c8711956 2594 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5
YL		 2595 "alloc rx buffer failed: %d\n",
2596 ret);
76ad4f0e
S		 2597 break;
2598 }
2599 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 2600
2601 u64_stats_update_begin(&ring->syncp);
2602 ring->stats.non_reuse_pg++;
2603 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 2604 }
2605
2606 ring_ptr_move_fw(ring, next_to_use);
2607 }
2608
2609 wmb(); /* Make all data has been write before submit */
2610 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2611}
2612
08bb3857
YL		 2613static bool hns3_page_is_reusable(struct page *page)
2614{
2615 return page_to_nid(page) == numa_mem_id() &&
2616 !page_is_pfmemalloc(page);
2617}
2618
76ad4f0e
S		 2619static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2620 struct hns3_enet_ring *ring, int pull_len,
2621 struct hns3_desc_cb *desc_cb)
2622{
389ca146
YL		 2623 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2624 int size = le16_to_cpu(desc->rx.size);
dbba6da0 2625 u32 truesize = hns3_buf_size(ring);
76ad4f0e
S		 2626
2627 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2628 size - pull_len, truesize);
76ad4f0e 2629
389ca146
YL		 2630 /* Avoid re-using remote pages, or the stack is still using the page
2631 * when page_offset rollback to zero, flag default unreuse
2632 */
08bb3857 2633 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
389ca146 2634 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
76ad4f0e 2635 return;
76ad4f0e
S		 2636
2637 /* Move offset up to the next cache line */
2638 desc_cb->page_offset += truesize;
2639
dbba6da0 2640 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
76ad4f0e 2641 desc_cb->reuse_flag = 1;
9b2f3477 2642 /* Bump ref count on page before it is given */
76ad4f0e 2643 get_page(desc_cb->priv);
389ca146
YL		 2644 } else if (page_count(desc_cb->priv) == 1) {
2645 desc_cb->reuse_flag = 1;
2646 desc_cb->page_offset = 0;
2647 get_page(desc_cb->priv);
76ad4f0e
S		 2648 }
2649}
2650
e2ee1c5a 2651static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL		 2652{
2653 __be16 type = skb->protocol;
2654 struct tcphdr *th;
2655 int depth = 0;
2656
e2ee1c5a 2657 while (eth_type_vlan(type)) {
d474d88f
YL		 2658 struct vlan_hdr *vh;
2659
2660 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2661 return -EFAULT;
2662
2663 vh = (struct vlan_hdr *)(skb->data + depth);
2664 type = vh->h_vlan_encapsulated_proto;
2665 depth += VLAN_HLEN;
2666 }
2667
e2ee1c5a
YL		 2668 skb_set_network_header(skb, depth);
2669
d474d88f 2670 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL		 2671 const struct iphdr *iph = ip_hdr(skb);
2672
d474d88f 2673 depth += sizeof(struct iphdr);
e2ee1c5a
YL		 2674 skb_set_transport_header(skb, depth);
2675 th = tcp_hdr(skb);
2676 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2677 iph->daddr, 0);
d474d88f 2678 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL		 2679 const struct ipv6hdr *iph = ipv6_hdr(skb);
2680
d474d88f 2681 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL		 2682 skb_set_transport_header(skb, depth);
2683 th = tcp_hdr(skb);
2684 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2685 &iph->daddr, 0);
d474d88f 2686 } else {
b20d7fe5
YL		 2687 hns3_rl_err(skb->dev,
2688 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2689 be16_to_cpu(type), depth);
d474d88f
YL		 2690 return -EFAULT;
2691 }
2692
d474d88f
YL		 2693 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2694 if (th->cwr)
2695 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2696
e2ee1c5a
YL		 2697 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2698 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 2699
e2ee1c5a
YL		 2700 skb->csum_start = (unsigned char *)th - skb->head;
2701 skb->csum_offset = offsetof(struct tcphdr, check);
2702 skb->ip_summed = CHECKSUM_PARTIAL;
698a8954
YL		 2703
2704 trace_hns3_gro(skb);
2705
d474d88f
YL		 2706 return 0;
2707}
2708
76ad4f0e 2709static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
39c38824 2710 u32 l234info, u32 bd_base_info, u32 ol_info)
76ad4f0e 2711{
c8711956 2712 struct net_device *netdev = ring_to_netdev(ring);
76ad4f0e 2713 int l3_type, l4_type;
76ad4f0e 2714 int ol4_type;
76ad4f0e
S		 2715
2716 skb->ip_summed = CHECKSUM_NONE;
2717
2718 skb_checksum_none_assert(skb);
2719
2720 if (!(netdev->features & NETIF_F_RXCSUM))
2721 return;
2722
2723 /* check if hardware has done checksum */
e8149933 2724 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S		 2725 return;
2726
f4772dee
DC		 2727 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2728 BIT(HNS3_RXD_OL3E_B) |
e8149933 2729 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S		 2730 u64_stats_update_begin(&ring->syncp);
2731 ring->stats.l3l4_csum_err++;
2732 u64_stats_update_end(&ring->syncp);
2733
2734 return;
2735 }
2736
39c38824 2737 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 2738 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2739 switch (ol4_type) {
2740 case HNS3_OL4_TYPE_MAC_IN_UDP:
2741 case HNS3_OL4_TYPE_NVGRE:
2742 skb->csum_level = 1;
be44b3af 2743 /* fall through */
76ad4f0e 2744 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 2745 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2746 HNS3_RXD_L3ID_S);
2747 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2748 HNS3_RXD_L4ID_S);
2749
76ad4f0e 2750 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2751 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2752 l3_type == HNS3_L3_TYPE_IPV6) &&
2753 (l4_type == HNS3_L4_TYPE_UDP ||
2754 l4_type == HNS3_L4_TYPE_TCP ||
2755 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2756 skb->ip_summed = CHECKSUM_UNNECESSARY;
2757 break;
fa7a4bd5
JS		 2758 default:
2759 break;
76ad4f0e
S		 2760 }
2761}
2762
d43e5aca
YL		 2763static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2764{
81ae0e04
PL		 2765 if (skb_has_frag_list(skb))
2766 napi_gro_flush(&ring->tqp_vector->napi, false);
2767
d43e5aca
YL		 2768 napi_gro_receive(&ring->tqp_vector->napi, skb);
2769}
2770
701a6d6a
JS		 2771static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2772 struct hns3_desc *desc, u32 l234info,
2773 u16 *vlan_tag)
5b5455a9 2774{
44e626f7 2775 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 2776 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL		 2777
2778 if (pdev->revision == 0x20) {
701a6d6a
JS		 2779 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2780 if (!(*vlan_tag & VLAN_VID_MASK))
2781 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2782
701a6d6a 2783 return (*vlan_tag != 0);
5b5455a9
PL		 2784 }
2785
2786#define HNS3_STRP_OUTER_VLAN 0x1
2787#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 2788#define HNS3_STRP_BOTH 0x3
5b5455a9 2789
44e626f7
JS		 2790 /* Hardware always insert VLAN tag into RX descriptor when
2791 * remove the tag from packet, driver needs to determine
2792 * reporting which tag to stack.
2793 */
e4e87715
PL		 2794 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2795 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2796 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 2797 if (handle->port_base_vlan_state !=
2798 HNAE3_PORT_BASE_VLAN_DISABLE)
2799 return false;
2800
701a6d6a
JS		 2801 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2802 return true;
5b5455a9 2803 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 2804 if (handle->port_base_vlan_state !=
2805 HNAE3_PORT_BASE_VLAN_DISABLE)
2806 return false;
2807
701a6d6a 2808 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 2809 return true;
2810 case HNS3_STRP_BOTH:
2811 if (handle->port_base_vlan_state ==
2812 HNAE3_PORT_BASE_VLAN_DISABLE)
2813 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2814 else
2815 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2816
701a6d6a 2817 return true;
5b5455a9 2818 default:
701a6d6a 2819 return false;
5b5455a9 2820 }
5b5455a9
PL		 2821}
2822
b9a8f883 2823static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL		 2824 unsigned char *va)
2825{
e5597095 2826 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
c8711956 2827 struct net_device *netdev = ring_to_netdev(ring);
e5597095
PL		 2828 struct sk_buff *skb;
2829
2830 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2831 skb = ring->skb;
2832 if (unlikely(!skb)) {
b20d7fe5 2833 hns3_rl_err(netdev, "alloc rx skb fail\n");
e5597095
PL		 2834
2835 u64_stats_update_begin(&ring->syncp);
2836 ring->stats.sw_err_cnt++;
2837 u64_stats_update_end(&ring->syncp);
2838
2839 return -ENOMEM;
2840 }
2841
698a8954 2842 trace_hns3_rx_desc(ring);
e5597095
PL		 2843 prefetchw(skb->data);
2844
2845 ring->pending_buf = 1;
81ae0e04
PL		 2846 ring->frag_num = 0;
2847 ring->tail_skb = NULL;
e5597095
PL		 2848 if (length <= HNS3_RX_HEAD_SIZE) {
2849 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2850
2851 /* We can reuse buffer as-is, just make sure it is local */
08bb3857 2852 if (likely(hns3_page_is_reusable(desc_cb->priv)))
e5597095
PL		 2853 desc_cb->reuse_flag = 1;
2854 else /* This page cannot be reused so discard it */
2855 put_page(desc_cb->priv);
2856
2857 ring_ptr_move_fw(ring, next_to_clean);
2858 return 0;
2859 }
2860 u64_stats_update_begin(&ring->syncp);
2861 ring->stats.seg_pkt_cnt++;
2862 u64_stats_update_end(&ring->syncp);
2863
c43f1255 2864 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 2865 __skb_put(skb, ring->pull_len);
81ae0e04 2866 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL		 2867 desc_cb);
2868 ring_ptr_move_fw(ring, next_to_clean);
2869
b2598318 2870 return 0;
e5597095
PL		 2871}
2872
b2598318 2873static int hns3_add_frag(struct hns3_enet_ring *ring)
e5597095 2874{
d35bced8
YL		 2875 struct sk_buff *skb = ring->skb;
2876 struct sk_buff *head_skb = skb;
81ae0e04 2877 struct sk_buff *new_skb;
e5597095 2878 struct hns3_desc_cb *desc_cb;
b2598318 2879 struct hns3_desc *desc;
e5597095 2880 u32 bd_base_info;
e5597095 2881
b2598318 2882 do {
e5597095
PL		 2883 desc = &ring->desc[ring->next_to_clean];
2884 desc_cb = &ring->desc_cb[ring->next_to_clean];
2885 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 2886 /* make sure HW write desc complete */
2887 dma_rmb();
e8149933 2888 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 2889 return -ENXIO;
2890
81ae0e04 2891 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
7fda3a93 2892 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
81ae0e04 2893 if (unlikely(!new_skb)) {
c8711956 2894 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5 2895 "alloc rx fraglist skb fail\n");
81ae0e04
PL		 2896 return -ENXIO;
2897 }
2898 ring->frag_num = 0;
2899
2900 if (ring->tail_skb) {
2901 ring->tail_skb->next = new_skb;
2902 ring->tail_skb = new_skb;
2903 } else {
2904 skb_shinfo(skb)->frag_list = new_skb;
2905 ring->tail_skb = new_skb;
2906 }
2907 }
2908
2909 if (ring->tail_skb) {
dbba6da0 2910 head_skb->truesize += hns3_buf_size(ring);
81ae0e04
PL		 2911 head_skb->data_len += le16_to_cpu(desc->rx.size);
2912 head_skb->len += le16_to_cpu(desc->rx.size);
2913 skb = ring->tail_skb;
2914 }
2915
2916 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
698a8954 2917 trace_hns3_rx_desc(ring);
e5597095
PL		 2918 ring_ptr_move_fw(ring, next_to_clean);
2919 ring->pending_buf++;
b2598318 2920 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
e5597095
PL		 2921
2922 return 0;
2923}
2924
d474d88f
YL		 2925static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2926 struct sk_buff *skb, u32 l234info,
39c38824 2927 u32 bd_base_info, u32 ol_info)
a6d53b97 2928{
a6d53b97
PL		 2929 u32 l3_type;
2930
e2ee1c5a
YL		 2931 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2932 HNS3_RXD_GRO_SIZE_M,
2933 HNS3_RXD_GRO_SIZE_S);
a6d53b97 2934 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 2935 if (!skb_shinfo(skb)->gso_size) {
39c38824 2936 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
d474d88f
YL		 2937 return 0;
2938 }
a6d53b97 2939
e2ee1c5a
YL		 2940 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2941 HNS3_RXD_GRO_COUNT_M,
2942 HNS3_RXD_GRO_COUNT_S);
a6d53b97 2943
9b2f3477 2944 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
a6d53b97
PL		 2945 if (l3_type == HNS3_L3_TYPE_IPV4)
2946 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2947 else if (l3_type == HNS3_L3_TYPE_IPV6)
2948 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2949 else
d474d88f 2950 return -EFAULT;
a6d53b97 2951
e2ee1c5a 2952 return hns3_gro_complete(skb, l234info);
a6d53b97
PL		 2953}
2954
232fc64b 2955static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 2956 struct sk_buff *skb, u32 rss_hash)
232fc64b 2957{
232fc64b
PL		 2958 struct hnae3_handle *handle = ring->tqp->handle;
2959 enum pkt_hash_types rss_type;
2960
ea485867 2961 if (rss_hash)
232fc64b
PL		 2962 rss_type = handle->kinfo.rss_type;
2963 else
2964 rss_type = PKT_HASH_TYPE_NONE;
2965
ea485867 2966 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 2967}
2968
ea485867 2969static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e 2970{
c8711956 2971 struct net_device *netdev = ring_to_netdev(ring);
c376fa1a 2972 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 2973 u32 bd_base_info, l234info, ol_info;
ea485867 2974 struct hns3_desc *desc;
d474d88f 2975 unsigned int len;
ea485867
YL		 2976 int pre_ntc, ret;
2977
2978 /* bdinfo handled below is only valid on the last BD of the
2979 * current packet, and ring->next_to_clean indicates the first
2980 * descriptor of next packet, so need - 1 below.
2981 */
2982 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2983 (ring->desc_num - 1);
2984 desc = &ring->desc[pre_ntc];
2985 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2986 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 2987 ol_info = le32_to_cpu(desc->rx.ol_info);
d474d88f
YL		 2988
2989 /* Based on hw strategy, the tag offloaded will be stored at
2990 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2991 * in one layer tag case.
2992 */
2993 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2994 u16 vlan_tag;
2995
2996 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2997 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2998 vlan_tag);
2999 }
3000
d474d88f
YL		 3001 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3002 BIT(HNS3_RXD_L2E_B))))) {
3003 u64_stats_update_begin(&ring->syncp);
3004 if (l234info & BIT(HNS3_RXD_L2E_B))
3005 ring->stats.l2_err++;
3006 else
3007 ring->stats.err_pkt_len++;
3008 u64_stats_update_end(&ring->syncp);
3009
3010 return -EFAULT;
3011 }
3012
3013 len = skb->len;
3014
3015 /* Do update ip stack process */
3016 skb->protocol = eth_type_trans(skb, netdev);
3017
3018 /* This is needed in order to enable forwarding support */
39c38824
YL		 3019 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3020 bd_base_info, ol_info);
d474d88f
YL		 3021 if (unlikely(ret)) {
3022 u64_stats_update_begin(&ring->syncp);
3023 ring->stats.rx_err_cnt++;
3024 u64_stats_update_end(&ring->syncp);
3025 return ret;
3026 }
3027
3028 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3029 HNS3_RXD_DMAC_S);
3030
3031 u64_stats_update_begin(&ring->syncp);
3032 ring->stats.rx_pkts++;
3033 ring->stats.rx_bytes += len;
3034
3035 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3036 ring->stats.rx_multicast++;
3037
3038 u64_stats_update_end(&ring->syncp);
3039
3040 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 3041
3042 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 3043 return 0;
3044}
3045
d35bced8 3046static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
d474d88f 3047{
e5597095 3048 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 3049 struct hns3_desc_cb *desc_cb;
3050 struct hns3_desc *desc;
b9a8f883 3051 unsigned int length;
76ad4f0e 3052 u32 bd_base_info;
e5597095 3053 int ret;
76ad4f0e
S		 3054
3055 desc = &ring->desc[ring->next_to_clean];
3056 desc_cb = &ring->desc_cb[ring->next_to_clean];
3057
3058 prefetch(desc);
3059
846fcc83 3060 length = le16_to_cpu(desc->rx.size);
76ad4f0e 3061 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 3062
3063 /* Check valid BD */
e8149933 3064 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
e5597095 3065 return -ENXIO;
76ad4f0e 3066
e5597095
PL		 3067 if (!skb)
3068 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S		 3069
3070 /* Prefetch first cache line of first page
3071 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3072 * line size is 64B so need to prefetch twice to make it 128B. But in
3073 * actual we can have greater size of caches with 128B Level 1 cache
3074 * lines. In such a case, single fetch would suffice to cache in the
3075 * relevant part of the header.
3076 */
e5597095 3077 prefetch(ring->va);
76ad4f0e 3078#if L1_CACHE_BYTES < 128
e5597095 3079 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S		 3080#endif
3081
e5597095
PL		 3082 if (!skb) {
3083 ret = hns3_alloc_skb(ring, length, ring->va);
d35bced8 3084 skb = ring->skb;
76ad4f0e 3085
e5597095
PL		 3086 if (ret < 0) /* alloc buffer fail */
3087 return ret;
b2598318
YL		 3088 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3089 ret = hns3_add_frag(ring);
e5597095
PL		 3090 if (ret)
3091 return ret;
e5597095 3092 }
76ad4f0e 3093 } else {
b2598318 3094 ret = hns3_add_frag(ring);
e5597095
PL		 3095 if (ret)
3096 return ret;
b2598318 3097 }
76ad4f0e 3098
b2598318
YL		 3099 /* As the head data may be changed when GRO enable, copy
3100 * the head data in after other data rx completed
3101 */
3102 if (skb->len > HNS3_RX_HEAD_SIZE)
e5597095
PL		 3103 memcpy(skb->data, ring->va,
3104 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e 3105
ea485867 3106 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 3107 if (unlikely(ret)) {
76ad4f0e 3108 dev_kfree_skb_any(skb);
d474d88f 3109 return ret;
76ad4f0e
S		 3110 }
3111
d93ed94f 3112 skb_record_rx_queue(skb, ring->tqp->tqp_index);
76ad4f0e
S		 3113 return 0;
3114}
3115
9b2f3477
WL		 3116int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3117 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 3118{
3119#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
63380a1a 3120 int unused_count = hns3_desc_unused(ring);
a4ee7624
YL		 3121 int recv_pkts = 0;
3122 int recv_bds = 0;
3123 int err, num;
76ad4f0e
S		 3124
3125 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
76ad4f0e 3126 num -= unused_count;
63380a1a 3127 unused_count -= ring->pending_buf;
76ad4f0e 3128
88b7c58c
YL		 3129 if (num <= 0)
3130 goto out;
3131
3132 rmb(); /* Make sure num taken effect before the other data is touched */
3133
76ad4f0e
S		 3134 while (recv_pkts < budget && recv_bds < num) {
3135 /* Reuse or realloc buffers */
a4ee7624
YL		 3136 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3137 hns3_nic_alloc_rx_buffers(ring, unused_count);
e5597095
PL		 3138 unused_count = hns3_desc_unused(ring) -
3139 ring->pending_buf;
76ad4f0e
S		 3140 }
3141
3142 /* Poll one pkt */
d35bced8
YL		 3143 err = hns3_handle_rx_bd(ring);
3144 /* Do not get FE for the packet or failed to alloc skb */
3145 if (unlikely(!ring->skb || err == -ENXIO)) {
76ad4f0e 3146 goto out;
d35bced8
YL		 3147 } else if (likely(!err)) {
3148 rx_fn(ring, ring->skb);
3149 recv_pkts++;
76ad4f0e
S		 3150 }
3151
e5597095 3152 recv_bds += ring->pending_buf;
a4ee7624 3153 unused_count += ring->pending_buf;
e5597095
PL		 3154 ring->skb = NULL;
3155 ring->pending_buf = 0;
76ad4f0e
S		 3156 }
3157
3158out:
3159 /* Make all data has been write before submit */
a4ee7624
YL		 3160 if (unused_count > 0)
3161 hns3_nic_alloc_rx_buffers(ring, unused_count);
76ad4f0e
S		 3162
3163 return recv_pkts;
3164}
3165
4a43caf5 3166static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
76ad4f0e 3167{
4a43caf5
YL		 3168#define HNS3_RX_LOW_BYTE_RATE 10000
3169#define HNS3_RX_MID_BYTE_RATE 20000
3170#define HNS3_RX_ULTRA_PACKET_RATE 40
3171
76ad4f0e 3172 enum hns3_flow_level_range new_flow_level;
4a43caf5
YL		 3173 struct hns3_enet_tqp_vector *tqp_vector;
3174 int packets_per_msecs, bytes_per_msecs;
a95e1f86 3175 u32 time_passed_ms;
76ad4f0e 3176
4a43caf5 3177 tqp_vector = ring_group->ring->tqp_vector;
a95e1f86
FL		 3178 time_passed_ms =
3179 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
a95e1f86
FL		 3180 if (!time_passed_ms)
3181 return false;
3182
3183 do_div(ring_group->total_packets, time_passed_ms);
3184 packets_per_msecs = ring_group->total_packets;
3185
3186 do_div(ring_group->total_bytes, time_passed_ms);
3187 bytes_per_msecs = ring_group->total_bytes;
3188
4a43caf5 3189 new_flow_level = ring_group->coal.flow_level;
76ad4f0e 3190
4a43caf5
YL		 3191 /* Simple throttlerate management
3192 * 0-10MB/s lower (50000 ints/s)
3193 * 10-20MB/s middle (20000 ints/s)
3194 * 20-1249MB/s high (18000 ints/s)
3195 * > 40000pps ultra (8000 ints/s)
3196 */
76ad4f0e
S		 3197 switch (new_flow_level) {
3198 case HNS3_FLOW_LOW:
a95e1f86 3199 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 3200 new_flow_level = HNS3_FLOW_MID;
3201 break;
3202 case HNS3_FLOW_MID:
a95e1f86 3203 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 3204 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 3205 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 3206 new_flow_level = HNS3_FLOW_LOW;
3207 break;
3208 case HNS3_FLOW_HIGH:
3209 case HNS3_FLOW_ULTRA:
3210 default:
a95e1f86 3211 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 3212 new_flow_level = HNS3_FLOW_MID;
3213 break;
3214 }
3215
a95e1f86
FL		 3216 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3217 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 3218 new_flow_level = HNS3_FLOW_ULTRA;
3219
4a43caf5
YL		 3220 ring_group->total_bytes = 0;
3221 ring_group->total_packets = 0;
3222 ring_group->coal.flow_level = new_flow_level;
3223
3224 return true;
3225}
3226
3227static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3228{
3229 struct hns3_enet_tqp_vector *tqp_vector;
3230 u16 new_int_gl;
3231
3232 if (!ring_group->ring)
3233 return false;
3234
3235 tqp_vector = ring_group->ring->tqp_vector;
3236 if (!tqp_vector->last_jiffies)
3237 return false;
3238
3239 if (ring_group->total_packets == 0) {
3240 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3241 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3242 return true;
3243 }
3244
3245 if (!hns3_get_new_flow_lvl(ring_group))
3246 return false;
3247
3248 new_int_gl = ring_group->coal.int_gl;
3249 switch (ring_group->coal.flow_level) {
76ad4f0e
S		 3250 case HNS3_FLOW_LOW:
3251 new_int_gl = HNS3_INT_GL_50K;
3252 break;
3253 case HNS3_FLOW_MID:
3254 new_int_gl = HNS3_INT_GL_20K;
3255 break;
3256 case HNS3_FLOW_HIGH:
3257 new_int_gl = HNS3_INT_GL_18K;
3258 break;
3259 case HNS3_FLOW_ULTRA:
3260 new_int_gl = HNS3_INT_GL_8K;
3261 break;
3262 default:
3263 break;
3264 }
3265
9bc727a9
YL		 3266 if (new_int_gl != ring_group->coal.int_gl) {
3267 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 3268 return true;
3269 }
3270 return false;
3271}
3272
3273static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3274{
8b1ff1ea
FL		 3275 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3276 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3277 bool rx_update, tx_update;
3278
7445565c
PL		 3279 /* update param every 1000ms */
3280 if (time_before(jiffies,
3281 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3282 return;
cd9d187b 3283
9bc727a9 3284 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 3285 rx_update = hns3_get_new_int_gl(rx_group);
3286 if (rx_update)
3287 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3288 rx_group->coal.int_gl);
8b1ff1ea
FL		 3289 }
3290
9bc727a9 3291 if (tx_group->coal.gl_adapt_enable) {
9e50dc11 3292 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL		 3293 if (tx_update)
3294 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3295 tx_group->coal.int_gl);
76ad4f0e 3296 }
cd9d187b 3297
a95e1f86 3298 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 3299}
3300
3301static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3302{
ff0699e0 3303 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 3304 struct hns3_enet_ring *ring;
3305 int rx_pkt_total = 0;
3306
3307 struct hns3_enet_tqp_vector *tqp_vector =
3308 container_of(napi, struct hns3_enet_tqp_vector, napi);
3309 bool clean_complete = true;
ceca4a5e 3310 int rx_budget = budget;
76ad4f0e 3311
ff0699e0
HT		 3312 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3313 napi_complete(napi);
3314 return 0;
3315 }
3316
76ad4f0e
S		 3317 /* Since the actual Tx work is minimal, we can give the Tx a larger
3318 * budget and be more aggressive about cleaning up the Tx descriptors.
3319 */
799997a3
PL		 3320 hns3_for_each_ring(ring, tqp_vector->tx_group)
3321 hns3_clean_tx_ring(ring);
76ad4f0e
S		 3322
3323 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 3324 if (tqp_vector->num_tqps > 1)
3325 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 3326
3327 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 3328 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3329 hns3_rx_skb);
76ad4f0e
S		 3330
3331 if (rx_cleaned >= rx_budget)
3332 clean_complete = false;
3333
3334 rx_pkt_total += rx_cleaned;
3335 }
3336
3337 tqp_vector->rx_group.total_packets += rx_pkt_total;
3338
3339 if (!clean_complete)
3340 return budget;
3341
531eba0f
HT		 3342 if (napi_complete(napi) &&
3343 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 3344 hns3_update_new_int_gl(tqp_vector);
3345 hns3_mask_vector_irq(tqp_vector, 1);
3346 }
76ad4f0e
S		 3347
3348 return rx_pkt_total;
3349}
3350
3351static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3352 struct hnae3_ring_chain_node *head)
3353{
3354 struct pci_dev *pdev = tqp_vector->handle->pdev;
3355 struct hnae3_ring_chain_node *cur_chain = head;
3356 struct hnae3_ring_chain_node *chain;
3357 struct hns3_enet_ring *tx_ring;
3358 struct hns3_enet_ring *rx_ring;
3359
3360 tx_ring = tqp_vector->tx_group.ring;
3361 if (tx_ring) {
3362 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3363 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3364 HNAE3_RING_TYPE_TX);
3365 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3366 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 3367
3368 cur_chain->next = NULL;
3369
3370 while (tx_ring->next) {
3371 tx_ring = tx_ring->next;
3372
3373 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3374 GFP_KERNEL);
3375 if (!chain)
73b907a0 3376 goto err_free_chain;
76ad4f0e
S		 3377
3378 cur_chain->next = chain;
3379 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3380 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3381 HNAE3_RING_TYPE_TX);
3382 hnae3_set_field(chain->int_gl_idx,
3383 HNAE3_RING_GL_IDX_M,
3384 HNAE3_RING_GL_IDX_S,
3385 HNAE3_RING_GL_TX);
76ad4f0e
S		 3386
3387 cur_chain = chain;
3388 }
3389 }
3390
3391 rx_ring = tqp_vector->rx_group.ring;
3392 if (!tx_ring && rx_ring) {
3393 cur_chain->next = NULL;
3394 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3395 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3396 HNAE3_RING_TYPE_RX);
3397 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3398 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 3399
3400 rx_ring = rx_ring->next;
3401 }
3402
3403 while (rx_ring) {
3404 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3405 if (!chain)
73b907a0 3406 goto err_free_chain;
76ad4f0e
S		 3407
3408 cur_chain->next = chain;
3409 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3410 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3411 HNAE3_RING_TYPE_RX);
3412 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3413 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3414
76ad4f0e
S		 3415 cur_chain = chain;
3416
3417 rx_ring = rx_ring->next;
3418 }
3419
3420 return 0;
73b907a0
HT		 3421
3422err_free_chain:
3423 cur_chain = head->next;
3424 while (cur_chain) {
3425 chain = cur_chain->next;
cda69d24 3426 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 3427 cur_chain = chain;
3428 }
cda69d24 3429 head->next = NULL;
73b907a0
HT		 3430
3431 return -ENOMEM;
76ad4f0e
S		 3432}
3433
3434static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3435 struct hnae3_ring_chain_node *head)
3436{
3437 struct pci_dev *pdev = tqp_vector->handle->pdev;
3438 struct hnae3_ring_chain_node *chain_tmp, *chain;
3439
3440 chain = head->next;
3441
3442 while (chain) {
3443 chain_tmp = chain->next;
3444 devm_kfree(&pdev->dev, chain);
3445 chain = chain_tmp;
3446 }
3447}
3448
3449static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3450 struct hns3_enet_ring *ring)
3451{
3452 ring->next = group->ring;
3453 group->ring = ring;
3454
3455 group->count++;
3456}
3457
874bff0b
PL		 3458static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3459{
3460 struct pci_dev *pdev = priv->ae_handle->pdev;
3461 struct hns3_enet_tqp_vector *tqp_vector;
3462 int num_vectors = priv->vector_num;
3463 int numa_node;
3464 int vector_i;
3465
3466 numa_node = dev_to_node(&pdev->dev);
3467
3468 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3469 tqp_vector = &priv->tqp_vector[vector_i];
3470 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3471 &tqp_vector->affinity_mask);
3472 }
3473}
3474
76ad4f0e
S		 3475static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3476{
3477 struct hnae3_ring_chain_node vector_ring_chain;
3478 struct hnae3_handle *h = priv->ae_handle;
3479 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3480 int ret = 0;
ece4bf46 3481 int i;
76ad4f0e 3482
874bff0b
PL		 3483 hns3_nic_set_cpumask(priv);
3484
dd38c726
YL		 3485 for (i = 0; i < priv->vector_num; i++) {
3486 tqp_vector = &priv->tqp_vector[i];
3487 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3488 tqp_vector->num_tqps = 0;
3489 }
76ad4f0e 3490
dd38c726
YL		 3491 for (i = 0; i < h->kinfo.num_tqps; i++) {
3492 u16 vector_i = i % priv->vector_num;
3493 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3494
3495 tqp_vector = &priv->tqp_vector[vector_i];
3496
3497 hns3_add_ring_to_group(&tqp_vector->tx_group,
5f06b903 3498 &priv->ring[i]);
76ad4f0e
S		 3499
3500 hns3_add_ring_to_group(&tqp_vector->rx_group,
5f06b903 3501 &priv->ring[i + tqp_num]);
76ad4f0e 3502
5f06b903
YL		 3503 priv->ring[i].tqp_vector = tqp_vector;
3504 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
dd38c726 3505 tqp_vector->num_tqps++;
76ad4f0e
S		 3506 }
3507
dd38c726 3508 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3509 tqp_vector = &priv->tqp_vector[i];
3510
3511 tqp_vector->rx_group.total_bytes = 0;
3512 tqp_vector->rx_group.total_packets = 0;
3513 tqp_vector->tx_group.total_bytes = 0;
3514 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3515 tqp_vector->handle = h;
3516
3517 ret = hns3_get_vector_ring_chain(tqp_vector,
3518 &vector_ring_chain);
3519 if (ret)
cda69d24 3520 goto map_ring_fail;
76ad4f0e
S		 3521
3522 ret = h->ae_algo->ops->map_ring_to_vector(h,
3523 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3524
3525 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3526
dd38c726 3527 if (ret)
ece4bf46 3528 goto map_ring_fail;
dd38c726 3529
76ad4f0e
S		 3530 netif_napi_add(priv->netdev, &tqp_vector->napi,
3531 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3532 }
3533
dd38c726 3534 return 0;
ece4bf46
HT		 3535
3536map_ring_fail:
3537 while (i--)
3538 netif_napi_del(&priv->tqp_vector[i].napi);
3539
3540 return ret;
dd38c726
YL		 3541}
3542
3543static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3544{
75edb610
JS		 3545#define HNS3_VECTOR_PF_MAX_NUM 64
3546
dd38c726
YL		 3547 struct hnae3_handle *h = priv->ae_handle;
3548 struct hns3_enet_tqp_vector *tqp_vector;
3549 struct hnae3_vector_info *vector;
3550 struct pci_dev *pdev = h->pdev;
3551 u16 tqp_num = h->kinfo.num_tqps;
3552 u16 vector_num;
3553 int ret = 0;
3554 u16 i;
3555
3556 /* RSS size, cpu online and vector_num should be the same */
3557 /* Should consider 2p/4p later */
3558 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS		 3559 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3560
dd38c726
YL		 3561 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3562 GFP_KERNEL);
3563 if (!vector)
3564 return -ENOMEM;
3565
9b2f3477 3566 /* save the actual available vector number */
dd38c726
YL		 3567 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3568
3569 priv->vector_num = vector_num;
3570 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3571 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3572 GFP_KERNEL);
3573 if (!priv->tqp_vector) {
3574 ret = -ENOMEM;
3575 goto out;
3576 }
3577
3578 for (i = 0; i < priv->vector_num; i++) {
3579 tqp_vector = &priv->tqp_vector[i];
3580 tqp_vector->idx = i;
3581 tqp_vector->mask_addr = vector[i].io_addr;
3582 tqp_vector->vector_irq = vector[i].vector;
3583 hns3_vector_gl_rl_init(tqp_vector, priv);
3584 }
3585
76ad4f0e
S		 3586out:
3587 devm_kfree(&pdev->dev, vector);
3588 return ret;
3589}
3590
dd38c726
YL		 3591static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3592{
3593 group->ring = NULL;
3594 group->count = 0;
3595}
3596
e2152785 3597static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 3598{
3599 struct hnae3_ring_chain_node vector_ring_chain;
3600 struct hnae3_handle *h = priv->ae_handle;
3601 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3602 int i;
76ad4f0e
S		 3603
3604 for (i = 0; i < priv->vector_num; i++) {
3605 tqp_vector = &priv->tqp_vector[i];
3606
2c9dd668
HT		 3607 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3608 continue;
3609
ff7dfcdd
HT		 3610 /* Since the mapping can be overwritten, when fail to get the
3611 * chain between vector and ring, we should go on to deal with
3612 * the remaining options.
3613 */
3614 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3615 dev_warn(priv->dev, "failed to get ring chain\n");
76ad4f0e 3616
e2152785 3617 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3618 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3619
3620 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3621
dd38c726
YL		 3622 hns3_clear_ring_group(&tqp_vector->rx_group);
3623 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3624 netif_napi_del(&priv->tqp_vector[i].napi);
3625 }
dd38c726
YL		 3626}
3627
08a10068 3628static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
dd38c726
YL		 3629{
3630 struct hnae3_handle *h = priv->ae_handle;
3631 struct pci_dev *pdev = h->pdev;
3632 int i, ret;
3633
3634 for (i = 0; i < priv->vector_num; i++) {
3635 struct hns3_enet_tqp_vector *tqp_vector;
3636
3637 tqp_vector = &priv->tqp_vector[i];
3638 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3639 if (ret)
08a10068 3640 return;
dd38c726 3641 }
76ad4f0e 3642
dd38c726 3643 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3644}
3645
5f06b903
YL		 3646static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3647 unsigned int ring_type)
76ad4f0e 3648{
76ad4f0e 3649 int queue_num = priv->ae_handle->kinfo.num_tqps;
76ad4f0e 3650 struct hns3_enet_ring *ring;
c0425944 3651 int desc_num;
76ad4f0e 3652
76ad4f0e 3653 if (ring_type == HNAE3_RING_TYPE_TX) {
5f06b903 3654 ring = &priv->ring[q->tqp_index];
c0425944 3655 desc_num = priv->ae_handle->kinfo.num_tx_desc;
5f06b903 3656 ring->queue_index = q->tqp_index;
76ad4f0e
S		 3657 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3658 } else {
5f06b903 3659 ring = &priv->ring[q->tqp_index + queue_num];
c0425944 3660 desc_num = priv->ae_handle->kinfo.num_rx_desc;
5f06b903 3661 ring->queue_index = q->tqp_index;
76ad4f0e
S		 3662 ring->io_base = q->io_base;
3663 }
3664
e4e87715 3665 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3666
76ad4f0e
S		 3667 ring->tqp = q;
3668 ring->desc = NULL;
3669 ring->desc_cb = NULL;
3670 ring->dev = priv->dev;
3671 ring->desc_dma_addr = 0;
3672 ring->buf_size = q->buf_size;
2c9dd668 3673 ring->desc_num = desc_num;
76ad4f0e
S		 3674 ring->next_to_use = 0;
3675 ring->next_to_clean = 0;
76ad4f0e
S		 3676}
3677
5f06b903
YL		 3678static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3679 struct hns3_nic_priv *priv)
76ad4f0e 3680{
5f06b903
YL		 3681 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3682 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
76ad4f0e
S		 3683}
3684
3685static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3686{
3687 struct hnae3_handle *h = priv->ae_handle;
3688 struct pci_dev *pdev = h->pdev;
5f06b903 3689 int i;
76ad4f0e 3690
5f06b903
YL		 3691 priv->ring = devm_kzalloc(&pdev->dev,
3692 array3_size(h->kinfo.num_tqps,
3693 sizeof(*priv->ring), 2),
3694 GFP_KERNEL);
3695 if (!priv->ring)
76ad4f0e
S		 3696 return -ENOMEM;
3697
5f06b903
YL		 3698 for (i = 0; i < h->kinfo.num_tqps; i++)
3699 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
76ad4f0e
S		 3700
3701 return 0;
76ad4f0e
S		 3702}
3703
09f2af64
PL		 3704static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3705{
5f06b903 3706 if (!priv->ring)
7b8f622e
HT		 3707 return;
3708
5f06b903
YL		 3709 devm_kfree(priv->dev, priv->ring);
3710 priv->ring = NULL;
09f2af64
PL		 3711}
3712
76ad4f0e
S		 3713static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3714{
3715 int ret;
3716
3717 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3718 return -EINVAL;
3719
77296bf6
YL		 3720 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3721 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 3722 if (!ring->desc_cb) {
3723 ret = -ENOMEM;
3724 goto out;
3725 }
3726
3727 ret = hns3_alloc_desc(ring);
3728 if (ret)
3729 goto out_with_desc_cb;
3730
3731 if (!HNAE3_IS_TX_RING(ring)) {
3732 ret = hns3_alloc_ring_buffers(ring);
3733 if (ret)
3734 goto out_with_desc;
3735 }
3736
3737 return 0;
3738
3739out_with_desc:
3740 hns3_free_desc(ring);
3741out_with_desc_cb:
77296bf6 3742 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3743 ring->desc_cb = NULL;
3744out:
3745 return ret;
3746}
3747
a723fb8e 3748void hns3_fini_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 3749{
3750 hns3_free_desc(ring);
77296bf6 3751 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3752 ring->desc_cb = NULL;
3753 ring->next_to_clean = 0;
3754 ring->next_to_use = 0;
ac574b80
PL		 3755 ring->pending_buf = 0;
3756 if (ring->skb) {
3757 dev_kfree_skb_any(ring->skb);
3758 ring->skb = NULL;
3759 }
76ad4f0e
S		 3760}
3761
1db9b1bf 3762static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3763{
3764 int bd_size_type;
3765
3766 switch (buf_size) {
3767 case 512:
3768 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3769 break;
3770 case 1024:
3771 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3772 break;
3773 case 2048:
3774 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3775 break;
3776 case 4096:
3777 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3778 break;
3779 default:
3780 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3781 }
3782
3783 return bd_size_type;
3784}
3785
3786static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3787{
3788 dma_addr_t dma = ring->desc_dma_addr;
3789 struct hnae3_queue *q = ring->tqp;
3790
3791 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 3792 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S		 3793 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3794 (u32)((dma >> 31) >> 1));
3795
3796 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3797 hns3_buf_size2type(ring->buf_size));
3798 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3799 ring->desc_num / 8 - 1);
3800
3801 } else {
3802 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3803 (u32)dma);
3804 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3805 (u32)((dma >> 31) >> 1));
3806
76ad4f0e
S		 3807 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3808 ring->desc_num / 8 - 1);
3809 }
3810}
3811
1c772154
YL		 3812static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3813{
3814 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3815 int i;
3816
3817 for (i = 0; i < HNAE3_MAX_TC; i++) {
3818 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3819 int j;
3820
3821 if (!tc_info->enable)
3822 continue;
3823
3824 for (j = 0; j < tc_info->tqp_count; j++) {
3825 struct hnae3_queue *q;
3826
5f06b903 3827 q = priv->ring[tc_info->tqp_offset + j].tqp;
1c772154
YL		 3828 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3829 tc_info->tc);
3830 }
3831 }
3832}
3833
5668abda 3834int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3835{
3836 struct hnae3_handle *h = priv->ae_handle;
3837 int ring_num = h->kinfo.num_tqps * 2;
3838 int i, j;
3839 int ret;
3840
3841 for (i = 0; i < ring_num; i++) {
5f06b903 3842 ret = hns3_alloc_ring_memory(&priv->ring[i]);
76ad4f0e
S		 3843 if (ret) {
3844 dev_err(priv->dev,
3845 "Alloc ring memory fail! ret=%d\n", ret);
3846 goto out_when_alloc_ring_memory;
3847 }
3848
5f06b903 3849 u64_stats_init(&priv->ring[i].syncp);
76ad4f0e
S		 3850 }
3851
3852 return 0;
3853
3854out_when_alloc_ring_memory:
3855 for (j = i - 1; j >= 0; j--)
5f06b903 3856 hns3_fini_ring(&priv->ring[j]);
76ad4f0e
S		 3857
3858 return -ENOMEM;
3859}
3860
5668abda 3861int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3862{
3863 struct hnae3_handle *h = priv->ae_handle;
3864 int i;
3865
3866 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903
YL		 3867 hns3_fini_ring(&priv->ring[i]);
3868 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
76ad4f0e 3869 }
76ad4f0e
S		 3870 return 0;
3871}
3872
3873/* Set mac addr if it is configured. or leave it to the AE driver */
8e6de441 3874static int hns3_init_mac_addr(struct net_device *netdev)
76ad4f0e
S		 3875{
3876 struct hns3_nic_priv *priv = netdev_priv(netdev);
3877 struct hnae3_handle *h = priv->ae_handle;
3878 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3879 int ret = 0;
76ad4f0e 3880
8e6de441 3881 if (h->ae_algo->ops->get_mac_addr)
76ad4f0e 3882 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
76ad4f0e
S		 3883
3884 /* Check if the MAC address is valid, if not get a random one */
8e6de441 3885 if (!is_valid_ether_addr(mac_addr_temp)) {
76ad4f0e
S		 3886 eth_hw_addr_random(netdev);
3887 dev_warn(priv->dev, "using random MAC address %pM\n",
3888 netdev->dev_addr);
ee4bcd3b 3889 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
8e6de441
HT		 3890 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3891 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
ee4bcd3b
JS		 3892 } else {
3893 return 0;
76ad4f0e 3894 }
139e8792
L		 3895
3896 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3897 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3898
7fa6be4f 3899 return ret;
76ad4f0e
S		 3900}
3901
c8a8045b
HT		 3902static int hns3_init_phy(struct net_device *netdev)
3903{
3904 struct hnae3_handle *h = hns3_get_handle(netdev);
3905 int ret = 0;
3906
3907 if (h->ae_algo->ops->mac_connect_phy)
3908 ret = h->ae_algo->ops->mac_connect_phy(h);
3909
3910 return ret;
3911}
3912
3913static void hns3_uninit_phy(struct net_device *netdev)
3914{
3915 struct hnae3_handle *h = hns3_get_handle(netdev);
3916
3917 if (h->ae_algo->ops->mac_disconnect_phy)
3918 h->ae_algo->ops->mac_disconnect_phy(h);
3919}
3920
6871af29
JS		 3921static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3922{
3923 struct hnae3_handle *h = hns3_get_handle(netdev);
3924
3925 if (h->ae_algo->ops->del_all_fd_entries)
3926 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3927}
3928
a6d818e3
YL		 3929static int hns3_client_start(struct hnae3_handle *handle)
3930{
3931 if (!handle->ae_algo->ops->client_start)
3932 return 0;
3933
3934 return handle->ae_algo->ops->client_start(handle);
3935}
3936
3937static void hns3_client_stop(struct hnae3_handle *handle)
3938{
3939 if (!handle->ae_algo->ops->client_stop)
3940 return;
3941
3942 handle->ae_algo->ops->client_stop(handle);
3943}
3944
bb87be87
YL		 3945static void hns3_info_show(struct hns3_nic_priv *priv)
3946{
3947 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3948
3949 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
adcf738b
GL		 3950 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3951 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3952 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3953 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3954 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3955 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3956 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3957 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
bb87be87
YL		 3958}
3959
76ad4f0e
S		 3960static int hns3_client_init(struct hnae3_handle *handle)
3961{
3962 struct pci_dev *pdev = handle->pdev;
0d43bf45 3963 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3964 struct hns3_nic_priv *priv;
3965 struct net_device *netdev;
3966 int ret;
3967
0d43bf45
HT		 3968 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3969 &max_rss_size);
3970 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3971 if (!netdev)
3972 return -ENOMEM;
3973
3974 priv = netdev_priv(netdev);
3975 priv->dev = &pdev->dev;
3976 priv->netdev = netdev;
3977 priv->ae_handle = handle;
f8fa222c 3978 priv->tx_timeout_count = 0;
b7b585c2 3979 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 3980
bb87be87
YL		 3981 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3982
76ad4f0e
S		 3983 handle->kinfo.netdev = netdev;
3984 handle->priv = (void *)priv;
3985
8e6de441 3986 hns3_init_mac_addr(netdev);
76ad4f0e
S		 3987
3988 hns3_set_default_feature(netdev);
3989
3990 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3991 netdev->priv_flags |= IFF_UNICAST_FLT;
3992 netdev->netdev_ops = &hns3_nic_netdev_ops;
3993 SET_NETDEV_DEV(netdev, &pdev->dev);
3994 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 3995
3996 /* Carrier off reporting is important to ethtool even BEFORE open */
3997 netif_carrier_off(netdev);
3998
3999 ret = hns3_get_ring_config(priv);
4000 if (ret) {
4001 ret = -ENOMEM;
4002 goto out_get_ring_cfg;
4003 }
4004
dd38c726
YL		 4005 ret = hns3_nic_alloc_vector_data(priv);
4006 if (ret) {
4007 ret = -ENOMEM;
4008 goto out_alloc_vector_data;
4009 }
4010
76ad4f0e
S		 4011 ret = hns3_nic_init_vector_data(priv);
4012 if (ret) {
4013 ret = -ENOMEM;
4014 goto out_init_vector_data;
4015 }
4016
4017 ret = hns3_init_all_ring(priv);
4018 if (ret) {
4019 ret = -ENOMEM;
5f06b903 4020 goto out_init_ring;
76ad4f0e
S		 4021 }
4022
c8a8045b
HT		 4023 ret = hns3_init_phy(netdev);
4024 if (ret)
4025 goto out_init_phy;
4026
76ad4f0e
S		 4027 ret = register_netdev(netdev);
4028 if (ret) {
4029 dev_err(priv->dev, "probe register netdev fail!\n");
4030 goto out_reg_netdev_fail;
4031 }
4032
08a10068
YL		 4033 /* the device can work without cpu rmap, only aRFS needs it */
4034 ret = hns3_set_rx_cpu_rmap(netdev);
4035 if (ret)
4036 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4037
4038 ret = hns3_nic_init_irq(priv);
4039 if (ret) {
4040 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4041 hns3_free_rx_cpu_rmap(netdev);
4042 goto out_init_irq_fail;
4043 }
4044
a6d818e3
YL		 4045 ret = hns3_client_start(handle);
4046 if (ret) {
4047 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 4048 goto out_client_start;
a6d818e3
YL		 4049 }
4050
986743db
YL		 4051 hns3_dcbnl_setup(handle);
4052
b2292360 4053 hns3_dbg_init(handle);
4054
a0b43717 4055 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 4056 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 4057
814da63c
HT		 4058 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4059
bb87be87
YL		 4060 if (netif_msg_drv(handle))
4061 hns3_info_show(priv);
4062
76ad4f0e
S		 4063 return ret;
4064
18655128 4065out_client_start:
08a10068
YL		 4066 hns3_free_rx_cpu_rmap(netdev);
4067 hns3_nic_uninit_irq(priv);
4068out_init_irq_fail:
18655128 4069 unregister_netdev(netdev);
76ad4f0e 4070out_reg_netdev_fail:
c8a8045b
HT		 4071 hns3_uninit_phy(netdev);
4072out_init_phy:
4073 hns3_uninit_all_ring(priv);
5f06b903 4074out_init_ring:
e2152785 4075 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4076out_init_vector_data:
dd38c726
YL		 4077 hns3_nic_dealloc_vector_data(priv);
4078out_alloc_vector_data:
5f06b903 4079 priv->ring = NULL;
76ad4f0e
S		 4080out_get_ring_cfg:
4081 priv->ae_handle = NULL;
4082 free_netdev(netdev);
4083 return ret;
4084}
4085
4086static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4087{
4088 struct net_device *netdev = handle->kinfo.netdev;
4089 struct hns3_nic_priv *priv = netdev_priv(netdev);
4090 int ret;
4091
4092 if (netdev->reg_state != NETREG_UNINITIALIZED)
4093 unregister_netdev(netdev);
4094
eb32c896
HT		 4095 hns3_client_stop(handle);
4096
0d2f68c7
HT		 4097 hns3_uninit_phy(netdev);
4098
814da63c
HT		 4099 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4100 netdev_warn(netdev, "already uninitialized\n");
4101 goto out_netdev_free;
4102 }
4103
08a10068
YL		 4104 hns3_free_rx_cpu_rmap(netdev);
4105
4106 hns3_nic_uninit_irq(priv);
4107
dc5e6064
JS		 4108 hns3_del_all_fd_rules(netdev, true);
4109
f96315f2 4110 hns3_clear_all_ring(handle, true);
7b763f3f 4111
e2152785 4112 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4113
08a10068 4114 hns3_nic_dealloc_vector_data(priv);
dd38c726 4115
76ad4f0e
S		 4116 ret = hns3_uninit_all_ring(priv);
4117 if (ret)
4118 netdev_err(netdev, "uninit ring error\n");
4119
ec777890
YL		 4120 hns3_put_ring_config(priv);
4121
814da63c 4122out_netdev_free:
e22b5e72 4123 hns3_dbg_uninit(handle);
76ad4f0e
S		 4124 free_netdev(netdev);
4125}
4126
4127static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4128{
4129 struct net_device *netdev = handle->kinfo.netdev;
4130
4131 if (!netdev)
4132 return;
4133
4134 if (linkup) {
4135 netif_carrier_on(netdev);
4136 netif_tx_wake_all_queues(netdev);
bb87be87
YL		 4137 if (netif_msg_link(handle))
4138 netdev_info(netdev, "link up\n");
76ad4f0e
S		 4139 } else {
4140 netif_carrier_off(netdev);
4141 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 4142 if (netif_msg_link(handle))
4143 netdev_info(netdev, "link down\n");
76ad4f0e
S		 4144 }
4145}
4146
9df8f79a
YL		 4147static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4148{
4149 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4150 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL		 4151
4152 if (tc > HNAE3_MAX_TC)
4153 return -EINVAL;
4154
4155 if (!ndev)
4156 return -ENODEV;
4157
a1ef124e 4158 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL		 4159}
4160
beebca3a 4161static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 4162{
beebca3a 4163 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 4164 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL		 4165 hns3_free_buffer_detach(ring, ring->next_to_clean);
4166 ring_ptr_move_fw(ring, next_to_clean);
4167 }
4168}
4169
7b763f3f
FL		 4170static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4171{
4172 struct hns3_desc_cb res_cbs;
4173 int ret;
4174
4175 while (ring->next_to_use != ring->next_to_clean) {
4176 /* When a buffer is not reused, it's memory has been
4177 * freed in hns3_handle_rx_bd or will be freed by
4178 * stack, so we need to replace the buffer here.
4179 */
4180 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4181 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4182 if (ret) {
4183 u64_stats_update_begin(&ring->syncp);
4184 ring->stats.sw_err_cnt++;
4185 u64_stats_update_end(&ring->syncp);
4186 /* if alloc new buffer fail, exit directly
4187 * and reclear in up flow.
4188 */
c8711956 4189 netdev_warn(ring_to_netdev(ring),
7b763f3f
FL		 4190 "reserve buffer map failed, ret = %d\n",
4191 ret);
4192 return ret;
4193 }
9b2f3477 4194 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL		 4195 }
4196 ring_ptr_move_fw(ring, next_to_use);
4197 }
4198
cc5ff6e9
PL		 4199 /* Free the pending skb in rx ring */
4200 if (ring->skb) {
4201 dev_kfree_skb_any(ring->skb);
4202 ring->skb = NULL;
4203 ring->pending_buf = 0;
4204 }
4205
7b763f3f
FL		 4206 return 0;
4207}
4208
4209static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4210{
beebca3a
YL		 4211 while (ring->next_to_use != ring->next_to_clean) {
4212 /* When a buffer is not reused, it's memory has been
4213 * freed in hns3_handle_rx_bd or will be freed by
4214 * stack, so only need to unmap the buffer here.
4215 */
4216 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4217 hns3_unmap_buffer(ring,
4218 &ring->desc_cb[ring->next_to_use]);
4219 ring->desc_cb[ring->next_to_use].dma = 0;
4220 }
4221
4222 ring_ptr_move_fw(ring, next_to_use);
4223 }
bb6b94a8
L		 4224}
4225
f96315f2 4226static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L		 4227{
4228 struct net_device *ndev = h->kinfo.netdev;
4229 struct hns3_nic_priv *priv = netdev_priv(ndev);
4230 u32 i;
4231
4232 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L		 4233 struct hns3_enet_ring *ring;
4234
5f06b903 4235 ring = &priv->ring[i];
beebca3a 4236 hns3_clear_tx_ring(ring);
bb6b94a8 4237
5f06b903 4238 ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 4239 /* Continue to clear other rings even if clearing some
4240 * rings failed.
4241 */
f96315f2
HT		 4242 if (force)
4243 hns3_force_clear_rx_ring(ring);
4244 else
4245 hns3_clear_rx_ring(ring);
bb6b94a8
L		 4246 }
4247}
4248
7b763f3f
FL		 4249int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4250{
4251 struct net_device *ndev = h->kinfo.netdev;
4252 struct hns3_nic_priv *priv = netdev_priv(ndev);
4253 struct hns3_enet_ring *rx_ring;
4254 int i, j;
4255 int ret;
4256
4257 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 4258 ret = h->ae_algo->ops->reset_queue(h, i);
4259 if (ret)
4260 return ret;
4261
5f06b903 4262 hns3_init_ring_hw(&priv->ring[i]);
7b763f3f
FL		 4263
4264 /* We need to clear tx ring here because self test will
4265 * use the ring and will not run down before up
4266 */
5f06b903
YL		 4267 hns3_clear_tx_ring(&priv->ring[i]);
4268 priv->ring[i].next_to_clean = 0;
4269 priv->ring[i].next_to_use = 0;
7b763f3f 4270
5f06b903 4271 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 4272 hns3_init_ring_hw(rx_ring);
4273 ret = hns3_clear_rx_ring(rx_ring);
4274 if (ret)
4275 return ret;
4276
4277 /* We can not know the hardware head and tail when this
4278 * function is called in reset flow, so we reuse all desc.
4279 */
4280 for (j = 0; j < rx_ring->desc_num; j++)
4281 hns3_reuse_buffer(rx_ring, j);
4282
4283 rx_ring->next_to_clean = 0;
4284 rx_ring->next_to_use = 0;
4285 }
4286
1c772154
YL		 4287 hns3_init_tx_ring_tc(priv);
4288
7b763f3f
FL		 4289 return 0;
4290}
4291
e4fd7502
HT		 4292static void hns3_store_coal(struct hns3_nic_priv *priv)
4293{
4294 /* ethtool only support setting and querying one coal
46ee7350
GL		 4295 * configuration for now, so save the vector 0' coal
4296 * configuration here in order to restore it.
e4fd7502
HT		 4297 */
4298 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4299 sizeof(struct hns3_enet_coalesce));
4300 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4301 sizeof(struct hns3_enet_coalesce));
4302}
4303
4304static void hns3_restore_coal(struct hns3_nic_priv *priv)
4305{
4306 u16 vector_num = priv->vector_num;
4307 int i;
4308
4309 for (i = 0; i < vector_num; i++) {
4310 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4311 sizeof(struct hns3_enet_coalesce));
4312 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4313 sizeof(struct hns3_enet_coalesce));
4314 }
4315}
4316
bb6b94a8
L		 4317static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4318{
4319 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4320 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 4321 struct hns3_nic_priv *priv = netdev_priv(ndev);
4322
4323 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4324 return 0;
bb6b94a8
L		 4325
4326 if (!netif_running(ndev))
6b1385cc 4327 return 0;
bb6b94a8
L		 4328
4329 return hns3_nic_net_stop(ndev);
4330}
4331
4332static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4333{
4334 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4335 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4336 int ret = 0;
4337
e8884027
HT		 4338 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4339
bb6b94a8 4340 if (netif_running(kinfo->netdev)) {
e8884027 4341 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4342 if (ret) {
e8884027 4343 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 4344 netdev_err(kinfo->netdev,
9b2f3477 4345 "net up fail, ret=%d!\n", ret);
bb6b94a8
L		 4346 return ret;
4347 }
bb6b94a8
L		 4348 }
4349
4350 return ret;
4351}
4352
4353static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4354{
4355 struct net_device *netdev = handle->kinfo.netdev;
4356 struct hns3_nic_priv *priv = netdev_priv(netdev);
4357 int ret;
4358
bb6b94a8
L		 4359 /* Carrier off reporting is important to ethtool even BEFORE open */
4360 netif_carrier_off(netdev);
4361
2c9dd668 4362 ret = hns3_get_ring_config(priv);
862d969a
HT		 4363 if (ret)
4364 return ret;
4365
2c9dd668
HT		 4366 ret = hns3_nic_alloc_vector_data(priv);
4367 if (ret)
4368 goto err_put_ring;
4369
e4fd7502
HT		 4370 hns3_restore_coal(priv);
4371
bb6b94a8
L		 4372 ret = hns3_nic_init_vector_data(priv);
4373 if (ret)
862d969a 4374 goto err_dealloc_vector;
bb6b94a8
L		 4375
4376 ret = hns3_init_all_ring(priv);
862d969a
HT		 4377 if (ret)
4378 goto err_uninit_vector;
bb6b94a8 4379
08a10068
YL		 4380 /* the device can work without cpu rmap, only aRFS needs it */
4381 ret = hns3_set_rx_cpu_rmap(netdev);
4382 if (ret)
4383 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4384
4385 ret = hns3_nic_init_irq(priv);
4386 if (ret) {
4387 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4388 hns3_free_rx_cpu_rmap(netdev);
4389 goto err_init_irq_fail;
4390 }
4391
ee4bcd3b
JS		 4392 if (!hns3_is_phys_func(handle->pdev))
4393 hns3_init_mac_addr(netdev);
4394
cd513a69
HT		 4395 ret = hns3_client_start(handle);
4396 if (ret) {
4397 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
08a10068 4398 goto err_client_start_fail;
cd513a69
HT		 4399 }
4400
814da63c
HT		 4401 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4402
862d969a
HT		 4403 return ret;
4404
08a10068
YL		 4405err_client_start_fail:
4406 hns3_free_rx_cpu_rmap(netdev);
4407 hns3_nic_uninit_irq(priv);
4408err_init_irq_fail:
cd513a69 4409 hns3_uninit_all_ring(priv);
862d969a
HT		 4410err_uninit_vector:
4411 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 4412err_dealloc_vector:
4413 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 4414err_put_ring:
4415 hns3_put_ring_config(priv);
862d969a 4416
bb6b94a8
L		 4417 return ret;
4418}
4419
4420static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4421{
4422 struct net_device *netdev = handle->kinfo.netdev;
4423 struct hns3_nic_priv *priv = netdev_priv(netdev);
4424 int ret;
4425
1eeb3367 4426 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 4427 netdev_warn(netdev, "already uninitialized\n");
4428 return 0;
4429 }
4430
08a10068
YL		 4431 hns3_free_rx_cpu_rmap(netdev);
4432 hns3_nic_uninit_irq(priv);
f96315f2
HT		 4433 hns3_clear_all_ring(handle, true);
4434 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 4435
e2152785 4436 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4437
e4fd7502
HT		 4438 hns3_store_coal(priv);
4439
08a10068 4440 hns3_nic_dealloc_vector_data(priv);
862d969a 4441
bb6b94a8
L		 4442 ret = hns3_uninit_all_ring(priv);
4443 if (ret)
4444 netdev_err(netdev, "uninit ring error\n");
4445
2c9dd668 4446 hns3_put_ring_config(priv);
2c9dd668 4447
bb6b94a8
L		 4448 return ret;
4449}
4450
4451static int hns3_reset_notify(struct hnae3_handle *handle,
4452 enum hnae3_reset_notify_type type)
4453{
4454 int ret = 0;
4455
4456 switch (type) {
4457 case HNAE3_UP_CLIENT:
e1586241
SM		 4458 ret = hns3_reset_notify_up_enet(handle);
4459 break;
bb6b94a8
L		 4460 case HNAE3_DOWN_CLIENT:
4461 ret = hns3_reset_notify_down_enet(handle);
4462 break;
4463 case HNAE3_INIT_CLIENT:
4464 ret = hns3_reset_notify_init_enet(handle);
4465 break;
4466 case HNAE3_UNINIT_CLIENT:
4467 ret = hns3_reset_notify_uninit_enet(handle);
4468 break;
4469 default:
4470 break;
4471 }
4472
4473 return ret;
4474}
4475
3a5a5f06
PL		 4476static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4477 bool rxfh_configured)
4478{
4479 int ret;
4480
4481 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4482 rxfh_configured);
4483 if (ret) {
4484 dev_err(&handle->pdev->dev,
4485 "Change tqp num(%u) fail.\n", new_tqp_num);
4486 return ret;
4487 }
4488
4489 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4490 if (ret)
4491 return ret;
4492
4493 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4494 if (ret)
4495 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4496
4497 return ret;
4498}
4499
09f2af64
PL		 4500int hns3_set_channels(struct net_device *netdev,
4501 struct ethtool_channels *ch)
4502{
09f2af64
PL		 4503 struct hnae3_handle *h = hns3_get_handle(netdev);
4504 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4505 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 4506 u32 new_tqp_num = ch->combined_count;
4507 u16 org_tqp_num;
4508 int ret;
4509
44950d28
JS		 4510 if (hns3_nic_resetting(netdev))
4511 return -EBUSY;
4512
09f2af64
PL		 4513 if (ch->rx_count || ch->tx_count)
4514 return -EINVAL;
4515
678335a1 4516 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4517 new_tqp_num < 1) {
09f2af64 4518 dev_err(&netdev->dev,
adcf738b 4519 "Change tqps fail, the tqp range is from 1 to %u",
678335a1 4520 hns3_get_max_available_channels(h));
09f2af64
PL		 4521 return -EINVAL;
4522 }
4523
c78b5b6c 4524 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 4525 return 0;
4526
1c822948
YL		 4527 netif_dbg(h, drv, netdev,
4528 "set channels: tqp_num=%u, rxfh=%d\n",
4529 new_tqp_num, rxfh_configured);
4530
65749f73
HT		 4531 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4532 if (ret)
4533 return ret;
dd38c726 4534
65749f73
HT		 4535 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4536 if (ret)
4537 return ret;
09f2af64
PL		 4538
4539 org_tqp_num = h->kinfo.num_tqps;
3a5a5f06 4540 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4541 if (ret) {
3a5a5f06
PL		 4542 int ret1;
4543
4544 netdev_warn(netdev,
4545 "Change channels fail, revert to old value\n");
4546 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4547 if (ret1) {
4548 netdev_err(netdev,
4549 "revert to old channel fail\n");
4550 return ret1;
09f2af64 4551 }
3a5a5f06 4552
65749f73 4553 return ret;
3a5a5f06 4554 }
09f2af64 4555
3a5a5f06 4556 return 0;
09f2af64
PL		 4557}
4558
a83d2961
WL		 4559static const struct hns3_hw_error_info hns3_hw_err[] = {
4560 { .type = HNAE3_PPU_POISON_ERROR,
4561 .msg = "PPU poison" },
4562 { .type = HNAE3_CMDQ_ECC_ERROR,
4563 .msg = "IMP CMDQ error" },
4564 { .type = HNAE3_IMP_RD_POISON_ERROR,
4565 .msg = "IMP RD poison" },
4566};
4567
4568static void hns3_process_hw_error(struct hnae3_handle *handle,
4569 enum hnae3_hw_error_type type)
4570{
4571 int i;
4572
4573 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4574 if (hns3_hw_err[i].type == type) {
4575 dev_err(&handle->pdev->dev, "Detected %s!\n",
4576 hns3_hw_err[i].msg);
4577 break;
4578 }
4579 }
4580}
4581
1db9b1bf 4582static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4583 .init_instance = hns3_client_init,
4584 .uninit_instance = hns3_client_uninit,
4585 .link_status_change = hns3_link_status_change,
9df8f79a 4586 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4587 .reset_notify = hns3_reset_notify,
a83d2961 4588 .process_hw_error = hns3_process_hw_error,
76ad4f0e
S		 4589};
4590
4591/* hns3_init_module - Driver registration routine
4592 * hns3_init_module is the first routine called when the driver is
4593 * loaded. All it does is register with the PCI subsystem.
4594 */
4595static int __init hns3_init_module(void)
4596{
4597 int ret;
4598
4599 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4600 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4601
4602 client.type = HNAE3_CLIENT_KNIC;
cdc37385 4603 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
76ad4f0e
S		 4604 hns3_driver_name);
4605
4606 client.ops = &client_ops;
4607
13562d1f
XW		 4608 INIT_LIST_HEAD(&client.node);
4609
b2292360 4610 hns3_dbg_register_debugfs(hns3_driver_name);
4611
76ad4f0e
S		 4612 ret = hnae3_register_client(&client);
4613 if (ret)
b2292360 4614 goto err_reg_client;
76ad4f0e
S		 4615
4616 ret = pci_register_driver(&hns3_driver);
4617 if (ret)
b2292360 4618 goto err_reg_driver;
76ad4f0e
S		 4619
4620 return ret;
b2292360 4621
4622err_reg_driver:
4623 hnae3_unregister_client(&client);
4624err_reg_client:
4625 hns3_dbg_unregister_debugfs();
4626 return ret;
76ad4f0e
S		 4627}
4628module_init(hns3_init_module);
4629
4630/* hns3_exit_module - Driver exit cleanup routine
4631 * hns3_exit_module is called just before the driver is removed
4632 * from memory.
4633 */
4634static void __exit hns3_exit_module(void)
4635{
4636 pci_unregister_driver(&hns3_driver);
4637 hnae3_unregister_client(&client);
b2292360 4638 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4639}
4640module_exit(hns3_exit_module);
4641
4642MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4643MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4644MODULE_LICENSE("GPL");
4645MODULE_ALIAS("pci:hns-nic");
Linux 6.x block layer and io_uring tree(s)