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net: hns3: refine the flow director handle
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e
S		 10#include <linux/if_vlan.h>
11#include <linux/ip.h>
12#include <linux/ipv6.h>
13#include <linux/module.h>
14#include <linux/pci.h>
6ae4e733 15#include <linux/aer.h>
76ad4f0e
S		 16#include <linux/skbuff.h>
17#include <linux/sctp.h>
18#include <linux/vermagic.h>
19#include <net/gre.h>
30d240df 20#include <net/pkt_cls.h>
a6d53b97 21#include <net/tcp.h>
76ad4f0e
S		 22#include <net/vxlan.h>
23
24#include "hnae3.h"
25#include "hns3_enet.h"
26
cde4ffad 27#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 28#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 29
7b763f3f
FL		 30static void hns3_clear_all_ring(struct hnae3_handle *h);
31static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
f05e2109 32static void hns3_remove_hw_addr(struct net_device *netdev);
7b763f3f 33
1db9b1bf 34static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 35const char hns3_driver_version[] = VERMAGIC_STRING;
36static const char hns3_driver_string[] =
37 "Hisilicon Ethernet Network Driver for Hip08 Family";
38static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
39static struct hnae3_client client;
40
bb87be87
YL		 41static int debug = -1;
42module_param(debug, int, 0);
43MODULE_PARM_DESC(debug, " Network interface message level setting");
44
45#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
46 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
47
76ad4f0e
S		 48/* hns3_pci_tbl - PCI Device ID Table
49 *
50 * Last entry must be all 0s
51 *
52 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
53 * Class, Class Mask, private data (not used) }
54 */
55static const struct pci_device_id hns3_pci_tbl[] = {
56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
57 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 59 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 60 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 61 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 62 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 63 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 64 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 65 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 67 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 68 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
07acf909
JS		 69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
70 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 71 /* required last entry */
72 {0, }
73};
74MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
75
ef0c5009 76static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 77{
ef0c5009 78 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 79
fb00331b 80 napi_schedule_irqoff(&tqp_vector->napi);
76ad4f0e
S		 81
82 return IRQ_HANDLED;
83}
84
85static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
86{
87 struct hns3_enet_tqp_vector *tqp_vectors;
88 unsigned int i;
89
90 for (i = 0; i < priv->vector_num; i++) {
91 tqp_vectors = &priv->tqp_vector[i];
92
93 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
94 continue;
95
ffab9691 96 /* clear the affinity mask */
874bff0b
PL		 97 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
98
76ad4f0e
S		 99 /* release the irq resource */
100 free_irq(tqp_vectors->vector_irq, tqp_vectors);
101 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
102 }
103}
104
105static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
106{
107 struct hns3_enet_tqp_vector *tqp_vectors;
108 int txrx_int_idx = 0;
109 int rx_int_idx = 0;
110 int tx_int_idx = 0;
111 unsigned int i;
112 int ret;
113
114 for (i = 0; i < priv->vector_num; i++) {
115 tqp_vectors = &priv->tqp_vector[i];
116
117 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
118 continue;
119
120 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
121 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
122 "%s-%s-%d", priv->netdev->name, "TxRx",
123 txrx_int_idx++);
124 txrx_int_idx++;
125 } else if (tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "Rx",
128 rx_int_idx++);
129 } else if (tqp_vectors->tx_group.ring) {
130 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
131 "%s-%s-%d", priv->netdev->name, "Tx",
132 tx_int_idx++);
133 } else {
134 /* Skip this unused q_vector */
135 continue;
136 }
137
138 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
139
140 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
141 tqp_vectors->name,
142 tqp_vectors);
143 if (ret) {
144 netdev_err(priv->netdev, "request irq(%d) fail\n",
145 tqp_vectors->vector_irq);
146 return ret;
147 }
148
874bff0b
PL		 149 irq_set_affinity_hint(tqp_vectors->vector_irq,
150 &tqp_vectors->affinity_mask);
151
76ad4f0e
S		 152 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
153 }
154
155 return 0;
156}
157
158static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
159 u32 mask_en)
160{
161 writel(mask_en, tqp_vector->mask_addr);
162}
163
164static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
165{
166 napi_enable(&tqp_vector->napi);
167
168 /* enable vector */
169 hns3_mask_vector_irq(tqp_vector, 1);
170}
171
172static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
173{
174 /* disable vector */
175 hns3_mask_vector_irq(tqp_vector, 0);
176
177 disable_irq(tqp_vector->vector_irq);
178 napi_disable(&tqp_vector->napi);
179}
180
434776a5
FL		 181void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
182 u32 rl_value)
76ad4f0e 183{
434776a5
FL		 184 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
185
76ad4f0e
S		 186 /* this defines the configuration for RL (Interrupt Rate Limiter).
187 * Rl defines rate of interrupts i.e. number of interrupts-per-second
188 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
189 */
434776a5 190
9bc727a9
YL		 191 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
192 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 193 /* According to the hardware, the range of rl_reg is
194 * 0-59 and the unit is 4.
195 */
196 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
197
198 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
199}
200
201void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
202 u32 gl_value)
203{
204 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
205
206 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
207}
208
209void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
210 u32 gl_value)
211{
212 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
213
214 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 215}
216
5fd4789a
FL		 217static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
218 struct hns3_nic_priv *priv)
76ad4f0e
S		 219{
220 /* initialize the configuration for interrupt coalescing.
221 * 1. GL (Interrupt Gap Limiter)
222 * 2. RL (Interrupt Rate Limiter)
223 */
224
5fd4789a 225 /* Default: enable interrupt coalescing self-adaptive and GL */
9bc727a9
YL		 226 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
227 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 228
9bc727a9
YL		 229 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
230 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 231
9bc727a9
YL		 232 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
233 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 234}
235
dd38c726
YL		 236static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
237 struct hns3_nic_priv *priv)
238{
239 struct hnae3_handle *h = priv->ae_handle;
240
241 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 242 tqp_vector->tx_group.coal.int_gl);
dd38c726 243 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 244 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 245 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
246}
247
9df8f79a
YL		 248static int hns3_nic_set_real_num_queue(struct net_device *netdev)
249{
9780cb97 250 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 251 struct hnae3_knic_private_info *kinfo = &h->kinfo;
252 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
a75a8efa
YL		 253 int i, ret;
254
255 if (kinfo->num_tc <= 1) {
256 netdev_reset_tc(netdev);
257 } else {
258 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
259 if (ret) {
260 netdev_err(netdev,
261 "netdev_set_num_tc fail, ret=%d!\n", ret);
262 return ret;
263 }
264
265 for (i = 0; i < HNAE3_MAX_TC; i++) {
266 if (!kinfo->tc_info[i].enable)
267 continue;
268
269 netdev_set_tc_queue(netdev,
270 kinfo->tc_info[i].tc,
271 kinfo->tc_info[i].tqp_count,
272 kinfo->tc_info[i].tqp_offset);
273 }
274 }
9df8f79a
YL		 275
276 ret = netif_set_real_num_tx_queues(netdev, queue_size);
277 if (ret) {
278 netdev_err(netdev,
279 "netif_set_real_num_tx_queues fail, ret=%d!\n",
280 ret);
281 return ret;
282 }
283
284 ret = netif_set_real_num_rx_queues(netdev, queue_size);
285 if (ret) {
286 netdev_err(netdev,
287 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
288 return ret;
289 }
290
291 return 0;
292}
293
678335a1
PL		 294static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
295{
0d43bf45 296 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 297
0d43bf45
HT		 298 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
299 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 300
0d43bf45 301 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 302}
303
8df0fa91
HT		 304static void hns3_tqp_enable(struct hnae3_queue *tqp)
305{
306 u32 rcb_reg;
307
308 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
309 rcb_reg |= BIT(HNS3_RING_EN_B);
310 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
311}
312
313static void hns3_tqp_disable(struct hnae3_queue *tqp)
314{
315 u32 rcb_reg;
316
317 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
318 rcb_reg &= ~BIT(HNS3_RING_EN_B);
319 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
320}
321
ffab9691
JS		 322static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
323{
324#ifdef CONFIG_RFS_ACCEL
325 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
326 netdev->rx_cpu_rmap = NULL;
327#endif
328}
329
330static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
331{
332#ifdef CONFIG_RFS_ACCEL
333 struct hns3_nic_priv *priv = netdev_priv(netdev);
334 struct hns3_enet_tqp_vector *tqp_vector;
335 int i, ret;
336
337 if (!netdev->rx_cpu_rmap) {
338 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
339 if (!netdev->rx_cpu_rmap)
340 return -ENOMEM;
341 }
342
343 for (i = 0; i < priv->vector_num; i++) {
344 tqp_vector = &priv->tqp_vector[i];
345 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
346 tqp_vector->vector_irq);
347 if (ret) {
348 hns3_free_rx_cpu_rmap(netdev);
349 return ret;
350 }
351 }
352#endif
353 return 0;
354}
355
76ad4f0e
S		 356static int hns3_nic_net_up(struct net_device *netdev)
357{
358 struct hns3_nic_priv *priv = netdev_priv(netdev);
359 struct hnae3_handle *h = priv->ae_handle;
360 int i, j;
361 int ret;
362
7b763f3f
FL		 363 ret = hns3_nic_reset_all_ring(h);
364 if (ret)
365 return ret;
366
ffab9691
JS		 367 /* the device can work without cpu rmap, only aRFS needs it */
368 ret = hns3_set_rx_cpu_rmap(netdev);
369 if (ret)
370 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret);
371
76ad4f0e
S		 372 /* get irq resource for all vectors */
373 ret = hns3_nic_init_irq(priv);
374 if (ret) {
375 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
ffab9691 376 goto free_rmap;
76ad4f0e
S		 377 }
378
b7b585c2
JS		 379 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
380
76ad4f0e
S		 381 /* enable the vectors */
382 for (i = 0; i < priv->vector_num; i++)
383 hns3_vector_enable(&priv->tqp_vector[i]);
384
8df0fa91
HT		 385 /* enable rcb */
386 for (j = 0; j < h->kinfo.num_tqps; j++)
387 hns3_tqp_enable(h->kinfo.tqp[j]);
388
76ad4f0e
S		 389 /* start the ae_dev */
390 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
391 if (ret)
392 goto out_start_err;
393
394 return 0;
395
396out_start_err:
b7b585c2 397 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
8df0fa91
HT		 398 while (j--)
399 hns3_tqp_disable(h->kinfo.tqp[j]);
400
76ad4f0e
S		 401 for (j = i - 1; j >= 0; j--)
402 hns3_vector_disable(&priv->tqp_vector[j]);
403
404 hns3_nic_uninit_irq(priv);
ffab9691
JS		 405free_rmap:
406 hns3_free_rx_cpu_rmap(netdev);
76ad4f0e
S		 407 return ret;
408}
409
2a73ac3e
YL		 410static void hns3_config_xps(struct hns3_nic_priv *priv)
411{
412 int i;
413
414 for (i = 0; i < priv->vector_num; i++) {
415 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
416 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
417
418 while (ring) {
419 int ret;
420
421 ret = netif_set_xps_queue(priv->netdev,
422 &tqp_vector->affinity_mask,
423 ring->tqp->tqp_index);
424 if (ret)
425 netdev_warn(priv->netdev,
426 "set xps queue failed: %d", ret);
427
428 ring = ring->next;
429 }
430 }
431}
432
76ad4f0e
S		 433static int hns3_nic_net_open(struct net_device *netdev)
434{
8cdb992f 435 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 436 struct hnae3_handle *h = hns3_get_handle(netdev);
437 struct hnae3_knic_private_info *kinfo;
438 int i, ret;
76ad4f0e 439
257e4f29
HT		 440 if (hns3_nic_resetting(netdev))
441 return -EBUSY;
442
76ad4f0e
S		 443 netif_carrier_off(netdev);
444
9df8f79a
YL		 445 ret = hns3_nic_set_real_num_queue(netdev);
446 if (ret)
76ad4f0e 447 return ret;
76ad4f0e
S		 448
449 ret = hns3_nic_net_up(netdev);
450 if (ret) {
451 netdev_err(netdev,
452 "hns net up fail, ret=%d!\n", ret);
453 return ret;
454 }
455
a75a8efa
YL		 456 kinfo = &h->kinfo;
457 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
458 netdev_set_prio_tc_map(netdev, i,
459 kinfo->prio_tc[i]);
460 }
461
8cdb992f
JS		 462 if (h->ae_algo->ops->set_timer_task)
463 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
464
2a73ac3e 465 hns3_config_xps(priv);
76ad4f0e
S		 466 return 0;
467}
468
469static void hns3_nic_net_down(struct net_device *netdev)
470{
471 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 472 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 473 const struct hnae3_ae_ops *ops;
474 int i;
475
7b763f3f
FL		 476 /* disable vectors */
477 for (i = 0; i < priv->vector_num; i++)
478 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 479
480 /* disable rcb */
481 for (i = 0; i < h->kinfo.num_tqps; i++)
482 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 483
76ad4f0e
S		 484 /* stop ae_dev */
485 ops = priv->ae_handle->ae_algo->ops;
486 if (ops->stop)
487 ops->stop(priv->ae_handle);
488
ffab9691
JS		 489 hns3_free_rx_cpu_rmap(netdev);
490
76ad4f0e
S		 491 /* free irq resources */
492 hns3_nic_uninit_irq(priv);
7b763f3f
FL		 493
494 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 495}
496
497static int hns3_nic_net_stop(struct net_device *netdev)
498{
ff0699e0 499 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 500 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 501
502 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
503 return 0;
504
8cdb992f
JS		 505 if (h->ae_algo->ops->set_timer_task)
506 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
507
76ad4f0e
S		 508 netif_tx_stop_all_queues(netdev);
509 netif_carrier_off(netdev);
510
511 hns3_nic_net_down(netdev);
512
513 return 0;
514}
515
76ad4f0e
S		 516static int hns3_nic_uc_sync(struct net_device *netdev,
517 const unsigned char *addr)
518{
9780cb97 519 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 520
521 if (h->ae_algo->ops->add_uc_addr)
522 return h->ae_algo->ops->add_uc_addr(h, addr);
523
524 return 0;
525}
526
527static int hns3_nic_uc_unsync(struct net_device *netdev,
528 const unsigned char *addr)
529{
9780cb97 530 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 531
532 if (h->ae_algo->ops->rm_uc_addr)
533 return h->ae_algo->ops->rm_uc_addr(h, addr);
534
535 return 0;
536}
537
538static int hns3_nic_mc_sync(struct net_device *netdev,
539 const unsigned char *addr)
540{
9780cb97 541 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 542
720a8478 543 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 544 return h->ae_algo->ops->add_mc_addr(h, addr);
545
546 return 0;
547}
548
549static int hns3_nic_mc_unsync(struct net_device *netdev,
550 const unsigned char *addr)
551{
9780cb97 552 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 553
720a8478 554 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 555 return h->ae_algo->ops->rm_mc_addr(h, addr);
556
557 return 0;
558}
559
c60edc17
JS		 560static u8 hns3_get_netdev_flags(struct net_device *netdev)
561{
562 u8 flags = 0;
563
564 if (netdev->flags & IFF_PROMISC) {
28673b33 565 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS		 566 } else {
567 flags |= HNAE3_VLAN_FLTR;
568 if (netdev->flags & IFF_ALLMULTI)
569 flags |= HNAE3_USER_MPE;
570 }
571
572 return flags;
573}
574
1db9b1bf 575static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 576{
9780cb97 577 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17
JS		 578 u8 new_flags;
579 int ret;
76ad4f0e 580
c60edc17
JS		 581 new_flags = hns3_get_netdev_flags(netdev);
582
583 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
584 if (ret) {
76ad4f0e 585 netdev_err(netdev, "sync uc address fail\n");
c60edc17
JS		 586 if (ret == -ENOSPC)
587 new_flags |= HNAE3_OVERFLOW_UPE;
588 }
589
40cca1c5 590 if (netdev->flags & IFF_MULTICAST) {
c60edc17
JS		 591 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
592 hns3_nic_mc_unsync);
593 if (ret) {
76ad4f0e 594 netdev_err(netdev, "sync mc address fail\n");
c60edc17
JS		 595 if (ret == -ENOSPC)
596 new_flags |= HNAE3_OVERFLOW_MPE;
597 }
598 }
599
c60edc17
JS		 600 /* User mode Promisc mode enable and vlan filtering is disabled to
601 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
602 * vlan fitering is enabled
603 */
604 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
605 h->netdev_flags = new_flags;
28673b33 606 hns3_update_promisc_mode(netdev, new_flags);
c60edc17
JS		 607}
608
7fa6be4f 609int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
c60edc17
JS		 610{
611 struct hns3_nic_priv *priv = netdev_priv(netdev);
612 struct hnae3_handle *h = priv->ae_handle;
613
614 if (h->ae_algo->ops->set_promisc_mode) {
7fa6be4f
HT		 615 return h->ae_algo->ops->set_promisc_mode(h,
616 promisc_flags & HNAE3_UPE,
617 promisc_flags & HNAE3_MPE);
c60edc17 618 }
7fa6be4f
HT		 619
620 return 0;
c60edc17
JS		 621}
622
623void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
624{
625 struct hns3_nic_priv *priv = netdev_priv(netdev);
626 struct hnae3_handle *h = priv->ae_handle;
627 bool last_state;
628
629 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
630 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
631 if (enable != last_state) {
632 netdev_info(netdev,
633 "%s vlan filter\n",
634 enable ? "enable" : "disable");
635 h->ae_algo->ops->enable_vlan_filter(h, enable);
636 }
40cca1c5 637 }
76ad4f0e
S		 638}
639
640static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
641 u16 *mss, u32 *type_cs_vlan_tso)
642{
643 u32 l4_offset, hdr_len;
644 union l3_hdr_info l3;
645 union l4_hdr_info l4;
646 u32 l4_paylen;
647 int ret;
648
649 if (!skb_is_gso(skb))
650 return 0;
651
652 ret = skb_cow_head(skb, 0);
0cccebac 653 if (unlikely(ret))
76ad4f0e
S		 654 return ret;
655
656 l3.hdr = skb_network_header(skb);
657 l4.hdr = skb_transport_header(skb);
658
659 /* Software should clear the IPv4's checksum field when tso is
660 * needed.
661 */
662 if (l3.v4->version == 4)
663 l3.v4->check = 0;
664
665 /* tunnel packet.*/
666 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
667 SKB_GSO_GRE_CSUM |
668 SKB_GSO_UDP_TUNNEL |
669 SKB_GSO_UDP_TUNNEL_CSUM)) {
670 if ((!(skb_shinfo(skb)->gso_type &
671 SKB_GSO_PARTIAL)) &&
672 (skb_shinfo(skb)->gso_type &
673 SKB_GSO_UDP_TUNNEL_CSUM)) {
674 /* Software should clear the udp's checksum
675 * field when tso is needed.
676 */
677 l4.udp->check = 0;
678 }
679 /* reset l3&l4 pointers from outer to inner headers */
680 l3.hdr = skb_inner_network_header(skb);
681 l4.hdr = skb_inner_transport_header(skb);
682
683 /* Software should clear the IPv4's checksum field when
684 * tso is needed.
685 */
686 if (l3.v4->version == 4)
687 l3.v4->check = 0;
688 }
689
690 /* normal or tunnel packet*/
691 l4_offset = l4.hdr - skb->data;
3fe13ed9 692 hdr_len = (l4.tcp->doff << 2) + l4_offset;
76ad4f0e
S		 693
694 /* remove payload length from inner pseudo checksum when tso*/
695 l4_paylen = skb->len - l4_offset;
696 csum_replace_by_diff(&l4.tcp->check,
697 (__force __wsum)htonl(l4_paylen));
698
699 /* find the txbd field values */
700 *paylen = skb->len - hdr_len;
cde4ffad 701 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 702
703 /* get MSS for TSO */
704 *mss = skb_shinfo(skb)->gso_size;
705
706 return 0;
707}
708
1898d4e4
S		 709static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
710 u8 *il4_proto)
76ad4f0e 711{
1a6e552d 712 union l3_hdr_info l3;
76ad4f0e
S		 713 unsigned char *l4_hdr;
714 unsigned char *exthdr;
715 u8 l4_proto_tmp;
716 __be16 frag_off;
717
718 /* find outer header point */
719 l3.hdr = skb_network_header(skb);
35f58fd7 720 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 721
722 if (skb->protocol == htons(ETH_P_IPV6)) {
723 exthdr = l3.hdr + sizeof(*l3.v6);
724 l4_proto_tmp = l3.v6->nexthdr;
725 if (l4_hdr != exthdr)
726 ipv6_skip_exthdr(skb, exthdr - skb->data,
727 &l4_proto_tmp, &frag_off);
728 } else if (skb->protocol == htons(ETH_P_IP)) {
729 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 730 } else {
731 return -EINVAL;
76ad4f0e
S		 732 }
733
734 *ol4_proto = l4_proto_tmp;
735
736 /* tunnel packet */
737 if (!skb->encapsulation) {
738 *il4_proto = 0;
1898d4e4 739 return 0;
76ad4f0e
S		 740 }
741
742 /* find inner header point */
743 l3.hdr = skb_inner_network_header(skb);
744 l4_hdr = skb_inner_transport_header(skb);
745
746 if (l3.v6->version == 6) {
747 exthdr = l3.hdr + sizeof(*l3.v6);
748 l4_proto_tmp = l3.v6->nexthdr;
749 if (l4_hdr != exthdr)
750 ipv6_skip_exthdr(skb, exthdr - skb->data,
751 &l4_proto_tmp, &frag_off);
752 } else if (l3.v4->version == 4) {
753 l4_proto_tmp = l3.v4->protocol;
754 }
755
756 *il4_proto = l4_proto_tmp;
1898d4e4
S		 757
758 return 0;
76ad4f0e
S		 759}
760
3db084d2
YL		 761/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
762 * and it is udp packet, which has a dest port as the IANA assigned.
763 * the hardware is expected to do the checksum offload, but the
764 * hardware will not do the checksum offload when udp dest port is
765 * 4789.
766 */
767static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
768{
1a6e552d 769 union l4_hdr_info l4;
3db084d2
YL		 770
771 l4.hdr = skb_transport_header(skb);
772
bea96410
MS		 773 if (!(!skb->encapsulation &&
774 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
3db084d2
YL		 775 return false;
776
777 skb_checksum_help(skb);
778
779 return true;
780}
781
757cd1e4
YL		 782static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
783 u32 *ol_type_vlan_len_msec)
76ad4f0e 784{
757cd1e4
YL		 785 u32 l2_len, l3_len, l4_len;
786 unsigned char *il2_hdr;
1a6e552d 787 union l3_hdr_info l3;
757cd1e4 788 union l4_hdr_info l4;
76ad4f0e
S		 789
790 l3.hdr = skb_network_header(skb);
757cd1e4 791 l4.hdr = skb_transport_header(skb);
76ad4f0e 792
757cd1e4
YL		 793 /* compute OL2 header size, defined in 2 Bytes */
794 l2_len = l3.hdr - skb->data;
795 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
796
797 /* compute OL3 header size, defined in 4 Bytes */
798 l3_len = l4.hdr - l3.hdr;
799 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 800
757cd1e4
YL		 801 il2_hdr = skb_inner_mac_header(skb);
802 /* compute OL4 header size, defined in 4 Bytes. */
803 l4_len = il2_hdr - l4.hdr;
804 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
805
806 /* define outer network header type */
807 if (skb->protocol == htons(ETH_P_IP)) {
808 if (skb_is_gso(skb))
cde4ffad 809 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 810 HNS3_TXD_OL3T_S,
811 HNS3_OL3T_IPV4_CSUM);
812 else
cde4ffad 813 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 814 HNS3_TXD_OL3T_S,
815 HNS3_OL3T_IPV4_NO_CSUM);
816
817 } else if (skb->protocol == htons(ETH_P_IPV6)) {
818 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
819 HNS3_OL3T_IPV6);
820 }
821
822 if (ol4_proto == IPPROTO_UDP)
823 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
824 HNS3_TUN_MAC_IN_UDP);
825 else if (ol4_proto == IPPROTO_GRE)
826 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
827 HNS3_TUN_NVGRE);
828}
829
830static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
831 u8 il4_proto, u32 *type_cs_vlan_tso,
832 u32 *ol_type_vlan_len_msec)
833{
c264ed44 834 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 835 u32 l4_proto = ol4_proto;
836 union l4_hdr_info l4;
837 union l3_hdr_info l3;
838 u32 l2_len, l3_len;
839
840 l4.hdr = skb_transport_header(skb);
841 l3.hdr = skb_network_header(skb);
842
843 /* handle encapsulation skb */
844 if (skb->encapsulation) {
845 /* If this is a not UDP/GRE encapsulation skb */
846 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 847 /* drop the skb tunnel packet if hardware don't support,
848 * because hardware can't calculate csum when TSO.
849 */
850 if (skb_is_gso(skb))
851 return -EDOM;
852
853 /* the stack computes the IP header already,
854 * driver calculate l4 checksum when not TSO.
855 */
856 skb_checksum_help(skb);
857 return 0;
858 }
859
757cd1e4
YL		 860 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
861
862 /* switch to inner header */
863 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 864 l3.hdr = skb_inner_network_header(skb);
757cd1e4 865 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 866 l4_proto = il4_proto;
867 }
868
869 if (l3.v4->version == 4) {
cde4ffad
YL		 870 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
871 HNS3_L3T_IPV4);
76ad4f0e
S		 872
873 /* the stack computes the IP header already, the only time we
874 * need the hardware to recompute it is in the case of TSO.
875 */
876 if (skb_is_gso(skb))
cde4ffad 877 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 878 } else if (l3.v6->version == 6) {
cde4ffad
YL		 879 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
880 HNS3_L3T_IPV6);
76ad4f0e
S		 881 }
882
757cd1e4
YL		 883 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
884 l2_len = l3.hdr - l2_hdr;
885 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
886
887 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
888 l3_len = l4.hdr - l3.hdr;
889 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
890
891 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 892 switch (l4_proto) {
893 case IPPROTO_TCP:
cde4ffad
YL		 894 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
895 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
896 HNS3_L4T_TCP);
757cd1e4
YL		 897 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
898 l4.tcp->doff);
76ad4f0e
S		 899 break;
900 case IPPROTO_UDP:
3db084d2
YL		 901 if (hns3_tunnel_csum_bug(skb))
902 break;
903
cde4ffad
YL		 904 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
905 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
906 HNS3_L4T_UDP);
757cd1e4
YL		 907 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
908 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 909 break;
910 case IPPROTO_SCTP:
cde4ffad
YL		 911 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
913 HNS3_L4T_SCTP);
757cd1e4
YL		 914 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
915 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 916 break;
917 default:
918 /* drop the skb tunnel packet if hardware don't support,
919 * because hardware can't calculate csum when TSO.
920 */
921 if (skb_is_gso(skb))
922 return -EDOM;
923
924 /* the stack computes the IP header already,
925 * driver calculate l4 checksum when not TSO.
926 */
927 skb_checksum_help(skb);
928 return 0;
929 }
930
931 return 0;
932}
933
934static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
935{
936 /* Config bd buffer end */
cde4ffad
YL		 937 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
938 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
76ad4f0e
S		 939}
940
9699cffe
PL		 941static int hns3_fill_desc_vtags(struct sk_buff *skb,
942 struct hns3_enet_ring *tx_ring,
943 u32 *inner_vlan_flag,
944 u32 *out_vlan_flag,
945 u16 *inner_vtag,
946 u16 *out_vtag)
947{
948#define HNS3_TX_VLAN_PRIO_SHIFT 13
949
44e626f7
JS		 950 struct hnae3_handle *handle = tx_ring->tqp->handle;
951
952 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
953 * header is allowed in skb, otherwise it will cause RAS error.
954 */
955 if (unlikely(skb_vlan_tagged_multi(skb) &&
956 handle->port_base_vlan_state ==
957 HNAE3_PORT_BASE_VLAN_ENABLE))
958 return -EINVAL;
959
9699cffe
PL		 960 if (skb->protocol == htons(ETH_P_8021Q) &&
961 !(tx_ring->tqp->handle->kinfo.netdev->features &
962 NETIF_F_HW_VLAN_CTAG_TX)) {
963 /* When HW VLAN acceleration is turned off, and the stack
964 * sets the protocol to 802.1q, the driver just need to
965 * set the protocol to the encapsulated ethertype.
966 */
967 skb->protocol = vlan_get_protocol(skb);
968 return 0;
969 }
970
971 if (skb_vlan_tag_present(skb)) {
972 u16 vlan_tag;
973
974 vlan_tag = skb_vlan_tag_get(skb);
975 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
976
977 /* Based on hw strategy, use out_vtag in two layer tag case,
978 * and use inner_vtag in one tag case.
979 */
980 if (skb->protocol == htons(ETH_P_8021Q)) {
44e626f7
JS		 981 if (handle->port_base_vlan_state ==
982 HNAE3_PORT_BASE_VLAN_DISABLE){
983 hns3_set_field(*out_vlan_flag,
984 HNS3_TXD_OVLAN_B, 1);
985 *out_vtag = vlan_tag;
986 } else {
987 hns3_set_field(*inner_vlan_flag,
988 HNS3_TXD_VLAN_B, 1);
989 *inner_vtag = vlan_tag;
990 }
9699cffe 991 } else {
cde4ffad 992 hns3_set_field(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
9699cffe
PL		 993 *inner_vtag = vlan_tag;
994 }
995 } else if (skb->protocol == htons(ETH_P_8021Q)) {
996 struct vlan_ethhdr *vhdr;
997 int rc;
998
999 rc = skb_cow_head(skb, 0);
0cccebac 1000 if (unlikely(rc < 0))
9699cffe
PL		 1001 return rc;
1002 vhdr = (struct vlan_ethhdr *)skb->data;
1003 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1004 << HNS3_TX_VLAN_PRIO_SHIFT);
1005 }
1006
1007 skb->protocol = vlan_get_protocol(skb);
1008 return 0;
1009}
1010
76ad4f0e 1011static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
5188f218 1012 int size, int frag_end, enum hns_desc_type type)
76ad4f0e
S		 1013{
1014 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1015 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1016 struct device *dev = ring_to_dev(ring);
5188f218 1017 struct skb_frag_struct *frag;
1e8a7977 1018 unsigned int frag_buf_num;
47e7b13b 1019 int k, sizeoflast;
5188f218 1020 dma_addr_t dma;
76ad4f0e 1021
76ad4f0e 1022 if (type == DESC_TYPE_SKB) {
47e7b13b
YL		 1023 struct sk_buff *skb = (struct sk_buff *)priv;
1024 u32 ol_type_vlan_len_msec = 0;
1025 u32 type_cs_vlan_tso = 0;
1026 u32 paylen = skb->len;
1027 u16 inner_vtag = 0;
1028 u16 out_vtag = 0;
1029 u16 mss = 0;
1030 int ret;
76ad4f0e 1031
9699cffe
PL		 1032 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1033 &ol_type_vlan_len_msec,
1034 &inner_vtag, &out_vtag);
1035 if (unlikely(ret))
1036 return ret;
1037
76ad4f0e 1038 if (skb->ip_summed == CHECKSUM_PARTIAL) {
47e7b13b
YL		 1039 u8 ol4_proto, il4_proto;
1040
76ad4f0e 1041 skb_reset_mac_len(skb);
76ad4f0e 1042
1898d4e4 1043 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
0cccebac 1044 if (unlikely(ret))
1898d4e4 1045 return ret;
757cd1e4
YL		 1046
1047 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1048 &type_cs_vlan_tso,
1049 &ol_type_vlan_len_msec);
0cccebac 1050 if (unlikely(ret))
76ad4f0e
S		 1051 return ret;
1052
1053 ret = hns3_set_tso(skb, &paylen, &mss,
1054 &type_cs_vlan_tso);
0cccebac 1055 if (unlikely(ret))
76ad4f0e
S		 1056 return ret;
1057 }
1058
1059 /* Set txbd */
1060 desc->tx.ol_type_vlan_len_msec =
1061 cpu_to_le32(ol_type_vlan_len_msec);
1062 desc->tx.type_cs_vlan_tso_len =
1063 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 1064 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 1065 desc->tx.mss = cpu_to_le16(mss);
9699cffe
PL		 1066 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1067 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
5188f218
PL		 1068
1069 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1070 } else {
1071 frag = (struct skb_frag_struct *)priv;
1072 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1073 }
1074
845e0d1d 1075 if (unlikely(dma_mapping_error(dev, dma))) {
5188f218
PL		 1076 ring->stats.sw_err_cnt++;
1077 return -ENOMEM;
76ad4f0e
S		 1078 }
1079
bcdb12b7
FL		 1080 desc_cb->length = size;
1081
ceca4a5e
YL		 1082 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1083 u16 bdtp_fe_sc_vld_ra_ri = 0;
1084
1085 desc_cb->priv = priv;
1086 desc_cb->dma = dma;
1087 desc_cb->type = type;
1088 desc->addr = cpu_to_le64(dma);
1089 desc->tx.send_size = cpu_to_le16(size);
1090 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
1091 desc->tx.bdtp_fe_sc_vld_ra_ri =
1092 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1093
1094 ring_ptr_move_fw(ring, next_to_use);
1095 return 0;
1096 }
1097
5f543a54 1098 frag_buf_num = hns3_tx_bd_count(size);
3fe13ed9 1099 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1e8a7977
FL		 1100 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1101
1102 /* When frag size is bigger than hardware limit, split this frag */
1103 for (k = 0; k < frag_buf_num; k++) {
ceca4a5e
YL		 1104 u16 bdtp_fe_sc_vld_ra_ri = 0;
1105
1e8a7977
FL		 1106 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1107 desc_cb->priv = priv;
1e8a7977
FL		 1108 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1109 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1110 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1111
1112 /* now, fill the descriptor */
1113 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7
FL		 1114 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1115 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977
FL		 1116 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1117 frag_end && (k == frag_buf_num - 1) ?
1118 1 : 0);
1119 desc->tx.bdtp_fe_sc_vld_ra_ri =
1120 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1121
1122 /* move ring pointer to next.*/
1123 ring_ptr_move_fw(ring, next_to_use);
1124
1125 desc_cb = &ring->desc_cb[ring->next_to_use];
1126 desc = &ring->desc[ring->next_to_use];
1127 }
76ad4f0e
S		 1128
1129 return 0;
1130}
1131
3d5f3741 1132static int hns3_nic_bd_num(struct sk_buff *skb)
76ad4f0e 1133{
3d5f3741
YL		 1134 int size = skb_headlen(skb);
1135 int i, bd_num;
76ad4f0e 1136
3d5f3741
YL		 1137 /* if the total len is within the max bd limit */
1138 if (likely(skb->len <= HNS3_MAX_BD_SIZE))
1139 return skb_shinfo(skb)->nr_frags + 1;
76ad4f0e 1140
3d5f3741 1141 bd_num = hns3_tx_bd_count(size);
76ad4f0e 1142
3d5f3741
YL		 1143 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1144 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1145 int frag_bd_num;
76ad4f0e 1146
3d5f3741
YL		 1147 size = skb_frag_size(frag);
1148 frag_bd_num = hns3_tx_bd_count(size);
1149
1150 if (unlikely(frag_bd_num > HNS3_MAX_BD_PER_FRAG))
51e8439f 1151 return -ENOMEM;
51e8439f 1152
3d5f3741
YL		 1153 bd_num += frag_bd_num;
1154 }
76ad4f0e 1155
3d5f3741 1156 return bd_num;
76ad4f0e
S		 1157}
1158
db4970aa
YL		 1159static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1160{
1161 if (!skb->encapsulation)
1162 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1163
1164 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1165}
1166
1167/* HW need every continuous 8 buffer data to be larger than MSS,
1168 * we simplify it by ensuring skb_headlen + the first continuous
1169 * 7 frags to to be larger than gso header len + mss, and the remaining
1170 * continuous 7 frags to be larger than MSS except the last 7 frags.
1171 */
1172static bool hns3_skb_need_linearized(struct sk_buff *skb)
1173{
1174 int bd_limit = HNS3_MAX_BD_PER_FRAG - 1;
1175 unsigned int tot_len = 0;
1176 int i;
1177
1178 for (i = 0; i < bd_limit; i++)
1179 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i]);
1180
1181 /* ensure headlen + the first 7 frags is greater than mss + header
1182 * and the first 7 frags is greater than mss.
1183 */
1184 if (((tot_len + skb_headlen(skb)) < (skb_shinfo(skb)->gso_size +
1185 hns3_gso_hdr_len(skb))) || (tot_len < skb_shinfo(skb)->gso_size))
1186 return true;
1187
1188 /* ensure the remaining continuous 7 buffer is greater than mss */
1189 for (i = 0; i < (skb_shinfo(skb)->nr_frags - bd_limit - 1); i++) {
1190 tot_len -= skb_frag_size(&skb_shinfo(skb)->frags[i]);
1191 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i + bd_limit]);
1192
1193 if (tot_len < skb_shinfo(skb)->gso_size)
1194 return true;
1195 }
1196
1197 return false;
1198}
1199
3d5f3741
YL		 1200static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1201 struct sk_buff **out_skb)
76ad4f0e
S		 1202{
1203 struct sk_buff *skb = *out_skb;
3d5f3741 1204 int bd_num;
76ad4f0e 1205
3d5f3741
YL		 1206 bd_num = hns3_nic_bd_num(skb);
1207 if (bd_num < 0)
1208 return bd_num;
1209
1210 if (unlikely(bd_num > HNS3_MAX_BD_PER_FRAG)) {
1211 struct sk_buff *new_skb;
76ad4f0e 1212
db4970aa
YL		 1213 if (skb_is_gso(skb) && !hns3_skb_need_linearized(skb))
1214 goto out;
1215
3d5f3741
YL		 1216 bd_num = hns3_tx_bd_count(skb->len);
1217 if (unlikely(ring_space(ring) < bd_num))
51e8439f
PL		 1218 return -EBUSY;
1219 /* manual split the send packet */
1220 new_skb = skb_copy(skb, GFP_ATOMIC);
1221 if (!new_skb)
1222 return -ENOMEM;
1223 dev_kfree_skb_any(skb);
1224 *out_skb = new_skb;
3d5f3741
YL		 1225
1226 u64_stats_update_begin(&ring->syncp);
1227 ring->stats.tx_copy++;
1228 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1229 }
1230
db4970aa 1231out:
3d5f3741 1232 if (unlikely(ring_space(ring) < bd_num))
76ad4f0e
S		 1233 return -EBUSY;
1234
3d5f3741 1235 return bd_num;
76ad4f0e
S		 1236}
1237
ba3f808f 1238static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1239{
1240 struct device *dev = ring_to_dev(ring);
1241 unsigned int i;
1242
1243 for (i = 0; i < ring->desc_num; i++) {
1244 /* check if this is where we started */
1245 if (ring->next_to_use == next_to_use_orig)
1246 break;
1247
aa9d22dd
YL		 1248 /* rollback one */
1249 ring_ptr_move_bw(ring, next_to_use);
1250
76ad4f0e
S		 1251 /* unmap the descriptor dma address */
1252 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1253 dma_unmap_single(dev,
1254 ring->desc_cb[ring->next_to_use].dma,
1255 ring->desc_cb[ring->next_to_use].length,
1256 DMA_TO_DEVICE);
bcdb12b7 1257 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1258 dma_unmap_page(dev,
1259 ring->desc_cb[ring->next_to_use].dma,
1260 ring->desc_cb[ring->next_to_use].length,
1261 DMA_TO_DEVICE);
1262
bcdb12b7 1263 ring->desc_cb[ring->next_to_use].length = 0;
aa9d22dd 1264 ring->desc_cb[ring->next_to_use].dma = 0;
76ad4f0e
S		 1265 }
1266}
1267
d43e5aca 1268netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1269{
1270 struct hns3_nic_priv *priv = netdev_priv(netdev);
1271 struct hns3_nic_ring_data *ring_data =
1272 &tx_ring_data(priv, skb->queue_mapping);
1273 struct hns3_enet_ring *ring = ring_data->ring;
76ad4f0e
S		 1274 struct netdev_queue *dev_queue;
1275 struct skb_frag_struct *frag;
1276 int next_to_use_head;
76ad4f0e
S		 1277 int buf_num;
1278 int seg_num;
1279 int size;
1280 int ret;
1281 int i;
1282
1283 /* Prefetch the data used later */
1284 prefetch(skb->data);
1285
3d5f3741
YL		 1286 buf_num = hns3_nic_maybe_stop_tx(ring, &skb);
1287 if (unlikely(buf_num <= 0)) {
1288 if (buf_num == -EBUSY) {
1289 u64_stats_update_begin(&ring->syncp);
1290 ring->stats.tx_busy++;
1291 u64_stats_update_end(&ring->syncp);
1292 goto out_net_tx_busy;
1293 } else if (buf_num == -ENOMEM) {
1294 u64_stats_update_begin(&ring->syncp);
1295 ring->stats.sw_err_cnt++;
1296 u64_stats_update_end(&ring->syncp);
1297 }
76ad4f0e 1298
3d5f3741
YL		 1299 if (net_ratelimit())
1300 netdev_err(netdev, "xmit error: %d!\n", buf_num);
76ad4f0e
S		 1301
1302 goto out_err_tx_ok;
76ad4f0e
S		 1303 }
1304
1305 /* No. of segments (plus a header) */
1306 seg_num = skb_shinfo(skb)->nr_frags + 1;
1307 /* Fill the first part */
1308 size = skb_headlen(skb);
1309
1310 next_to_use_head = ring->next_to_use;
1311
d40fa7ee
YL		 1312 ret = hns3_fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1313 DESC_TYPE_SKB);
0cccebac 1314 if (unlikely(ret))
aa9d22dd 1315 goto fill_err;
76ad4f0e 1316
76ad4f0e
S		 1317 /* Fill the fragments */
1318 for (i = 1; i < seg_num; i++) {
1319 frag = &skb_shinfo(skb)->frags[i - 1];
1320 size = skb_frag_size(frag);
5188f218 1321
d40fa7ee
YL		 1322 ret = hns3_fill_desc(ring, frag, size,
1323 seg_num - 1 == i ? 1 : 0,
1324 DESC_TYPE_PAGE);
76ad4f0e 1325
0cccebac 1326 if (unlikely(ret))
aa9d22dd 1327 goto fill_err;
76ad4f0e
S		 1328 }
1329
1330 /* Complete translate all packets */
1331 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1332 netdev_tx_sent_queue(dev_queue, skb->len);
1333
1334 wmb(); /* Commit all data before submit */
1335
e4e87715 1336 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1337
1338 return NETDEV_TX_OK;
1339
aa9d22dd 1340fill_err:
ba3f808f 1341 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1342
1343out_err_tx_ok:
1344 dev_kfree_skb_any(skb);
1345 return NETDEV_TX_OK;
1346
1347out_net_tx_busy:
1348 netif_stop_subqueue(netdev, ring_data->queue_index);
1349 smp_mb(); /* Commit all data before submit */
1350
1351 return NETDEV_TX_BUSY;
1352}
1353
1354static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1355{
9780cb97 1356 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1357 struct sockaddr *mac_addr = p;
1358 int ret;
1359
1360 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1361 return -EADDRNOTAVAIL;
1362
5ec2a51e
JS		 1363 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1364 netdev_info(netdev, "already using mac address %pM\n",
1365 mac_addr->sa_data);
1366 return 0;
1367 }
1368
59098055 1369 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1370 if (ret) {
1371 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1372 return ret;
1373 }
1374
1375 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1376
1377 return 0;
1378}
1379
26483246
XW		 1380static int hns3_nic_do_ioctl(struct net_device *netdev,
1381 struct ifreq *ifr, int cmd)
1382{
1383 struct hnae3_handle *h = hns3_get_handle(netdev);
1384
1385 if (!netif_running(netdev))
1386 return -EINVAL;
1387
1388 if (!h->ae_algo->ops->do_ioctl)
1389 return -EOPNOTSUPP;
1390
1391 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1392}
1393
76ad4f0e
S		 1394static int hns3_nic_set_features(struct net_device *netdev,
1395 netdev_features_t features)
1396{
181d454b 1397 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1398 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1399 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1400 bool enable;
052ece6d 1401 int ret;
76ad4f0e 1402
5c9f6b39 1403 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 1404 enable = !!(features & NETIF_F_GRO_HW);
1405 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 1406 if (ret)
1407 return ret;
1408 }
1409
bd368416
JS		 1410 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1411 h->ae_algo->ops->enable_vlan_filter) {
1731be4c
YL		 1412 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1413 h->ae_algo->ops->enable_vlan_filter(h, enable);
181d454b 1414 }
391b5e93 1415
bd368416
JS		 1416 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1417 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 1418 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1419 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 1420 if (ret)
1421 return ret;
1422 }
1423
c17852a8 1424 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 1425 enable = !!(features & NETIF_F_NTUPLE);
1426 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 1427 }
1428
76ad4f0e
S		 1429 netdev->features = features;
1430 return 0;
1431}
1432
6c88d9d7
PL		 1433static void hns3_nic_get_stats64(struct net_device *netdev,
1434 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1435{
1436 struct hns3_nic_priv *priv = netdev_priv(netdev);
1437 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1438 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1439 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 1440 u64 rx_length_errors = 0;
1441 u64 rx_crc_errors = 0;
1442 u64 rx_multicast = 0;
76ad4f0e 1443 unsigned int start;
d3ec4ef6
JS		 1444 u64 tx_errors = 0;
1445 u64 rx_errors = 0;
76ad4f0e
S		 1446 unsigned int idx;
1447 u64 tx_bytes = 0;
1448 u64 rx_bytes = 0;
1449 u64 tx_pkts = 0;
1450 u64 rx_pkts = 0;
d2a5dca8
JS		 1451 u64 tx_drop = 0;
1452 u64 rx_drop = 0;
76ad4f0e 1453
b875cc37
JS		 1454 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1455 return;
1456
c5f65480
JS		 1457 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1458
76ad4f0e
S		 1459 for (idx = 0; idx < queue_num; idx++) {
1460 /* fetch the tx stats */
1461 ring = priv->ring_data[idx].ring;
1462 do {
d36d36ce 1463 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1464 tx_bytes += ring->stats.tx_bytes;
1465 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1466 tx_drop += ring->stats.sw_err_cnt;
d3ec4ef6 1467 tx_errors += ring->stats.sw_err_cnt;
76ad4f0e
S		 1468 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1469
1470 /* fetch the rx stats */
1471 ring = priv->ring_data[idx + queue_num].ring;
1472 do {
d36d36ce 1473 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1474 rx_bytes += ring->stats.rx_bytes;
1475 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1476 rx_drop += ring->stats.non_vld_descs;
d2a5dca8 1477 rx_drop += ring->stats.l2_err;
d3ec4ef6
JS		 1478 rx_errors += ring->stats.non_vld_descs;
1479 rx_errors += ring->stats.l2_err;
1480 rx_crc_errors += ring->stats.l2_err;
1481 rx_crc_errors += ring->stats.l3l4_csum_err;
1482 rx_multicast += ring->stats.rx_multicast;
1483 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 1484 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1485 }
1486
1487 stats->tx_bytes = tx_bytes;
1488 stats->tx_packets = tx_pkts;
1489 stats->rx_bytes = rx_bytes;
1490 stats->rx_packets = rx_pkts;
1491
d3ec4ef6
JS		 1492 stats->rx_errors = rx_errors;
1493 stats->multicast = rx_multicast;
1494 stats->rx_length_errors = rx_length_errors;
1495 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 1496 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1497
d3ec4ef6
JS		 1498 stats->tx_errors = tx_errors;
1499 stats->rx_dropped = rx_drop;
1500 stats->tx_dropped = tx_drop;
76ad4f0e
S		 1501 stats->collisions = netdev->stats.collisions;
1502 stats->rx_over_errors = netdev->stats.rx_over_errors;
1503 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1504 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1505 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1506 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1507 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1508 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1509 stats->tx_window_errors = netdev->stats.tx_window_errors;
1510 stats->rx_compressed = netdev->stats.rx_compressed;
1511 stats->tx_compressed = netdev->stats.tx_compressed;
1512}
1513
30d240df 1514static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1515{
30d240df 1516 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1517 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1518 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1519 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1520 u8 tc = mqprio_qopt->qopt.num_tc;
1521 u16 mode = mqprio_qopt->mode;
1522 u8 hw = mqprio_qopt->qopt.hw;
76ad4f0e 1523
30d240df
YL		 1524 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1525 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1526 return -EOPNOTSUPP;
1527
76ad4f0e
S		 1528 if (tc > HNAE3_MAX_TC)
1529 return -EINVAL;
1530
76ad4f0e
S		 1531 if (!netdev)
1532 return -EINVAL;
1533
1cce5eb6 1534 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
30d240df 1535 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e
S		 1536}
1537
2572ac53 1538static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1539 void *type_data)
76ad4f0e 1540{
575ed7d3 1541 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1542 return -EOPNOTSUPP;
76ad4f0e 1543
30d240df 1544 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1545}
1546
1547static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1548 __be16 proto, u16 vid)
1549{
9780cb97 1550 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1551 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1552 int ret = -EIO;
1553
1554 if (h->ae_algo->ops->set_vlan_filter)
1555 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1556
681ec399
YL		 1557 if (!ret)
1558 set_bit(vid, priv->active_vlans);
1559
76ad4f0e
S		 1560 return ret;
1561}
1562
1563static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1564 __be16 proto, u16 vid)
1565{
9780cb97 1566 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1567 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1568 int ret = -EIO;
1569
1570 if (h->ae_algo->ops->set_vlan_filter)
1571 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1572
681ec399
YL		 1573 if (!ret)
1574 clear_bit(vid, priv->active_vlans);
1575
76ad4f0e
S		 1576 return ret;
1577}
1578
7fa6be4f 1579static int hns3_restore_vlan(struct net_device *netdev)
681ec399
YL		 1580{
1581 struct hns3_nic_priv *priv = netdev_priv(netdev);
7fa6be4f 1582 int ret = 0;
681ec399 1583 u16 vid;
681ec399
YL		 1584
1585 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1586 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
7fa6be4f
HT		 1587 if (ret) {
1588 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1589 vid, ret);
1590 return ret;
1591 }
681ec399 1592 }
7fa6be4f
HT		 1593
1594 return ret;
681ec399
YL		 1595}
1596
76ad4f0e
S		 1597static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1598 u8 qos, __be16 vlan_proto)
1599{
9780cb97 1600 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1601 int ret = -EIO;
1602
1603 if (h->ae_algo->ops->set_vf_vlan_filter)
1604 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1605 qos, vlan_proto);
1606
1607 return ret;
1608}
1609
a8e8b7ff
S		 1610static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1611{
9780cb97 1612 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1613 int ret;
1614
6ff7ed80
HT		 1615 if (hns3_nic_resetting(netdev))
1616 return -EBUSY;
1617
a8e8b7ff
S		 1618 if (!h->ae_algo->ops->set_mtu)
1619 return -EOPNOTSUPP;
1620
a8e8b7ff 1621 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1622 if (ret)
a8e8b7ff
S		 1623 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1624 ret);
93d8daf4
YL		 1625 else
1626 netdev->mtu = new_mtu;
5bad95a1 1627
a8e8b7ff
S		 1628 return ret;
1629}
1630
f8fa222c
L		 1631static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1632{
1633 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1634 struct hnae3_handle *h = hns3_get_handle(ndev);
f8fa222c 1635 struct hns3_enet_ring *tx_ring = NULL;
e511c97d 1636 struct napi_struct *napi;
f8fa222c
L		 1637 int timeout_queue = 0;
1638 int hw_head, hw_tail;
e511c97d
JS		 1639 int fbd_num, fbd_oft;
1640 int ebd_num, ebd_oft;
1641 int bd_num, bd_err;
1642 int ring_en, tc;
f8fa222c
L		 1643 int i;
1644
1645 /* Find the stopped queue the same way the stack does */
fa6c4084 1646 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 1647 struct netdev_queue *q;
1648 unsigned long trans_start;
1649
1650 q = netdev_get_tx_queue(ndev, i);
1651 trans_start = q->trans_start;
1652 if (netif_xmit_stopped(q) &&
1653 time_after(jiffies,
1654 (trans_start + ndev->watchdog_timeo))) {
1655 timeout_queue = i;
1656 break;
1657 }
1658 }
1659
1660 if (i == ndev->num_tx_queues) {
1661 netdev_info(ndev,
1662 "no netdev TX timeout queue found, timeout count: %llu\n",
1663 priv->tx_timeout_count);
1664 return false;
1665 }
1666
beab694a
JS		 1667 priv->tx_timeout_count++;
1668
f8fa222c 1669 tx_ring = priv->ring_data[timeout_queue].ring;
e511c97d
JS		 1670 napi = &tx_ring->tqp_vector->napi;
1671
1672 netdev_info(ndev,
1673 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1674 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1675 tx_ring->next_to_clean, napi->state);
1676
1677 netdev_info(ndev,
1678 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1679 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1680 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1681
1682 netdev_info(ndev,
1683 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1684 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1685 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1686
1687 /* When mac received many pause frames continuous, it's unable to send
1688 * packets, which may cause tx timeout
1689 */
1690 if (h->ae_algo->ops->update_stats &&
1691 h->ae_algo->ops->get_mac_pause_stats) {
1692 u64 tx_pause_cnt, rx_pause_cnt;
1693
1694 h->ae_algo->ops->update_stats(h, &ndev->stats);
1695 h->ae_algo->ops->get_mac_pause_stats(h, &tx_pause_cnt,
1696 &rx_pause_cnt);
1697 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1698 tx_pause_cnt, rx_pause_cnt);
1699 }
f8fa222c
L		 1700
1701 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1702 HNS3_RING_TX_RING_HEAD_REG);
1703 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1704 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 1705 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1706 HNS3_RING_TX_RING_FBDNUM_REG);
1707 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1708 HNS3_RING_TX_RING_OFFSET_REG);
1709 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1710 HNS3_RING_TX_RING_EBDNUM_REG);
1711 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1712 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1713 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1714 HNS3_RING_TX_RING_BD_NUM_REG);
1715 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1716 HNS3_RING_TX_RING_BD_ERR_REG);
1717 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1718 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1719
f8fa222c 1720 netdev_info(ndev,
e511c97d
JS		 1721 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1722 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 1723 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 1724 netdev_info(ndev,
1725 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1726 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 1727
1728 return true;
1729}
1730
1731static void hns3_nic_net_timeout(struct net_device *ndev)
1732{
1733 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1734 struct hnae3_handle *h = priv->ae_handle;
1735
1736 if (!hns3_get_tx_timeo_queue_info(ndev))
1737 return;
1738
0742ed7c
HT		 1739 /* request the reset, and let the hclge to determine
1740 * which reset level should be done
1741 */
f8fa222c 1742 if (h->ae_algo->ops->reset_event)
6ae4e733 1743 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1744}
1745
76ad4f0e
S		 1746static const struct net_device_ops hns3_nic_netdev_ops = {
1747 .ndo_open = hns3_nic_net_open,
1748 .ndo_stop = hns3_nic_net_stop,
1749 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1750 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1751 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1752 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1753 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1754 .ndo_set_features = hns3_nic_set_features,
1755 .ndo_get_stats64 = hns3_nic_get_stats64,
1756 .ndo_setup_tc = hns3_nic_setup_tc,
1757 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1758 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1759 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1760 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1761};
1762
97afd47b 1763bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 1764{
1765 u32 dev_id = pdev->device;
1766
1767 switch (dev_id) {
1768 case HNAE3_DEV_ID_GE:
1769 case HNAE3_DEV_ID_25GE:
1770 case HNAE3_DEV_ID_25GE_RDMA:
1771 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1772 case HNAE3_DEV_ID_50GE_RDMA:
1773 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1774 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1775 return true;
1776 case HNAE3_DEV_ID_100G_VF:
1777 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1778 return false;
1779 default:
1780 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1781 dev_id);
1782 }
1783
1784 return false;
1785}
1786
2312e050
FL		 1787static void hns3_disable_sriov(struct pci_dev *pdev)
1788{
1789 /* If our VFs are assigned we cannot shut down SR-IOV
1790 * without causing issues, so just leave the hardware
1791 * available but disabled
1792 */
1793 if (pci_vfs_assigned(pdev)) {
1794 dev_warn(&pdev->dev,
1795 "disabling driver while VFs are assigned\n");
1796 return;
1797 }
1798
1799 pci_disable_sriov(pdev);
1800}
1801
d695964d
JS		 1802static void hns3_get_dev_capability(struct pci_dev *pdev,
1803 struct hnae3_ae_dev *ae_dev)
1804{
b26a6fea 1805 if (pdev->revision >= 0x21) {
d695964d 1806 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL		 1807 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1808 }
d695964d
JS		 1809}
1810
76ad4f0e
S		 1811/* hns3_probe - Device initialization routine
1812 * @pdev: PCI device information struct
1813 * @ent: entry in hns3_pci_tbl
1814 *
1815 * hns3_probe initializes a PF identified by a pci_dev structure.
1816 * The OS initialization, configuring of the PF private structure,
1817 * and a hardware reset occur.
1818 *
1819 * Returns 0 on success, negative on failure
1820 */
1821static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1822{
1823 struct hnae3_ae_dev *ae_dev;
1824 int ret;
1825
1826 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1827 GFP_KERNEL);
1828 if (!ae_dev) {
1829 ret = -ENOMEM;
1830 return ret;
1831 }
1832
1833 ae_dev->pdev = pdev;
e92a0843 1834 ae_dev->flag = ent->driver_data;
76ad4f0e 1835 ae_dev->dev_type = HNAE3_DEV_KNIC;
6871af29 1836 ae_dev->reset_type = HNAE3_NONE_RESET;
d695964d 1837 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 1838 pci_set_drvdata(pdev, ae_dev);
1839
74354140
HT		 1840 ret = hnae3_register_ae_dev(ae_dev);
1841 if (ret) {
1842 devm_kfree(&pdev->dev, ae_dev);
1843 pci_set_drvdata(pdev, NULL);
1844 }
2312e050 1845
74354140 1846 return ret;
76ad4f0e
S		 1847}
1848
1849/* hns3_remove - Device removal routine
1850 * @pdev: PCI device information struct
1851 */
1852static void hns3_remove(struct pci_dev *pdev)
1853{
1854 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1855
2312e050
FL		 1856 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1857 hns3_disable_sriov(pdev);
1858
76ad4f0e 1859 hnae3_unregister_ae_dev(ae_dev);
ac864c23 1860 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 1861}
1862
fa8d82e8
PL		 1863/**
1864 * hns3_pci_sriov_configure
1865 * @pdev: pointer to a pci_dev structure
1866 * @num_vfs: number of VFs to allocate
1867 *
1868 * Enable or change the number of VFs. Called when the user updates the number
1869 * of VFs in sysfs.
1870 **/
743e1a84 1871static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 1872{
1873 int ret;
1874
1875 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1876 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1877 return -EINVAL;
1878 }
1879
1880 if (num_vfs) {
1881 ret = pci_enable_sriov(pdev, num_vfs);
1882 if (ret)
1883 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 1884 else
1885 return num_vfs;
fa8d82e8
PL		 1886 } else if (!pci_vfs_assigned(pdev)) {
1887 pci_disable_sriov(pdev);
1888 } else {
1889 dev_warn(&pdev->dev,
1890 "Unable to free VFs because some are assigned to VMs.\n");
1891 }
1892
1893 return 0;
1894}
1895
ce2c1d2e
YL		 1896static void hns3_shutdown(struct pci_dev *pdev)
1897{
1898 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1899
1900 hnae3_unregister_ae_dev(ae_dev);
1901 devm_kfree(&pdev->dev, ae_dev);
1902 pci_set_drvdata(pdev, NULL);
1903
1904 if (system_state == SYSTEM_POWER_OFF)
1905 pci_set_power_state(pdev, PCI_D3hot);
1906}
1907
5a9f0eac
SJ		 1908static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1909 pci_channel_state_t state)
1910{
1911 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1912 pci_ers_result_t ret;
1913
1914 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1915
1916 if (state == pci_channel_io_perm_failure)
1917 return PCI_ERS_RESULT_DISCONNECT;
1918
1919 if (!ae_dev) {
1920 dev_err(&pdev->dev,
1921 "Can't recover - error happened during device init\n");
1922 return PCI_ERS_RESULT_NONE;
1923 }
1924
381c356e
SJ		 1925 if (ae_dev->ops->handle_hw_ras_error)
1926 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 1927 else
1928 return PCI_ERS_RESULT_NONE;
1929
1930 return ret;
1931}
1932
6ae4e733
SJ		 1933static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1934{
1935 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1936 struct device *dev = &pdev->dev;
1937
1938 dev_info(dev, "requesting reset due to PCI error\n");
1939
1940 /* request the reset */
1941 if (ae_dev->ops->reset_event) {
69b51bbb
SJ		 1942 if (!ae_dev->override_pci_need_reset)
1943 ae_dev->ops->reset_event(pdev, NULL);
1944
6ae4e733
SJ		 1945 return PCI_ERS_RESULT_RECOVERED;
1946 }
1947
1948 return PCI_ERS_RESULT_DISCONNECT;
1949}
1950
6b9a97ee
HT		 1951static void hns3_reset_prepare(struct pci_dev *pdev)
1952{
1953 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1954
1955 dev_info(&pdev->dev, "hns3 flr prepare\n");
1956 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1957 ae_dev->ops->flr_prepare(ae_dev);
1958}
1959
1960static void hns3_reset_done(struct pci_dev *pdev)
1961{
1962 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1963
1964 dev_info(&pdev->dev, "hns3 flr done\n");
1965 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1966 ae_dev->ops->flr_done(ae_dev);
1967}
1968
5a9f0eac
SJ		 1969static const struct pci_error_handlers hns3_err_handler = {
1970 .error_detected = hns3_error_detected,
6ae4e733 1971 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 1972 .reset_prepare = hns3_reset_prepare,
1973 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 1974};
1975
76ad4f0e
S		 1976static struct pci_driver hns3_driver = {
1977 .name = hns3_driver_name,
1978 .id_table = hns3_pci_tbl,
1979 .probe = hns3_probe,
1980 .remove = hns3_remove,
ce2c1d2e 1981 .shutdown = hns3_shutdown,
fa8d82e8 1982 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 1983 .err_handler = &hns3_err_handler,
76ad4f0e
S		 1984};
1985
1986/* set default feature to hns3 */
1987static void hns3_set_default_feature(struct net_device *netdev)
1988{
3e85af6a
PL		 1989 struct hnae3_handle *h = hns3_get_handle(netdev);
1990 struct pci_dev *pdev = h->pdev;
1991
76ad4f0e
S		 1992 netdev->priv_flags |= IFF_UNICAST_FLT;
1993
1994 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1995 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1996 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1997 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 1998 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1999
2000 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
2001
2002 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2003
2004 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2005 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2006 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2007 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2008 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2009 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2010 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 2011
2012 netdev->vlan_features |=
2013 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2014 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2015 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2016 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2017 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 2018
2019 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 2020 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2021 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2022 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2023 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2024 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
3e85af6a 2025
c17852a8 2026 if (pdev->revision >= 0x21) {
77af09c6 2027 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2028 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 2029
2030 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2031 netdev->hw_features |= NETIF_F_NTUPLE;
2032 netdev->features |= NETIF_F_NTUPLE;
2033 }
2034 }
76ad4f0e
S		 2035}
2036
2037static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2038 struct hns3_desc_cb *cb)
2039{
e4e87715 2040 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 2041 struct page *p;
2042
2043 p = dev_alloc_pages(order);
2044 if (!p)
2045 return -ENOMEM;
2046
2047 cb->priv = p;
2048 cb->page_offset = 0;
2049 cb->reuse_flag = 0;
2050 cb->buf = page_address(p);
e4e87715 2051 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 2052 cb->type = DESC_TYPE_PAGE;
2053
76ad4f0e
S		 2054 return 0;
2055}
2056
2057static void hns3_free_buffer(struct hns3_enet_ring *ring,
2058 struct hns3_desc_cb *cb)
2059{
2060 if (cb->type == DESC_TYPE_SKB)
2061 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2062 else if (!HNAE3_IS_TX_RING(ring))
2063 put_page((struct page *)cb->priv);
2064 memset(cb, 0, sizeof(*cb));
2065}
2066
2067static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2068{
2069 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2070 cb->length, ring_to_dma_dir(ring));
2071
2211f4e1 2072 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 2073 return -EIO;
2074
2075 return 0;
2076}
2077
2078static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2079 struct hns3_desc_cb *cb)
2080{
2081 if (cb->type == DESC_TYPE_SKB)
2082 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2083 ring_to_dma_dir(ring));
bcdb12b7 2084 else if (cb->length)
76ad4f0e
S		 2085 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2086 ring_to_dma_dir(ring));
2087}
2088
2089static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2090{
2091 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2092 ring->desc[i].addr = 0;
2093}
2094
2095static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2096{
2097 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2098
2099 if (!ring->desc_cb[i].dma)
2100 return;
2101
2102 hns3_buffer_detach(ring, i);
2103 hns3_free_buffer(ring, cb);
2104}
2105
2106static void hns3_free_buffers(struct hns3_enet_ring *ring)
2107{
2108 int i;
2109
2110 for (i = 0; i < ring->desc_num; i++)
2111 hns3_free_buffer_detach(ring, i);
2112}
2113
2114/* free desc along with its attached buffer */
2115static void hns3_free_desc(struct hns3_enet_ring *ring)
2116{
024cc792
HT		 2117 int size = ring->desc_num * sizeof(ring->desc[0]);
2118
76ad4f0e
S		 2119 hns3_free_buffers(ring);
2120
024cc792
HT		 2121 if (ring->desc) {
2122 dma_free_coherent(ring_to_dev(ring), size,
2123 ring->desc, ring->desc_dma_addr);
2124 ring->desc = NULL;
2125 }
76ad4f0e
S		 2126}
2127
2128static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2129{
2130 int size = ring->desc_num * sizeof(ring->desc[0]);
2131
750afb08
LC		 2132 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2133 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 2134 if (!ring->desc)
2135 return -ENOMEM;
2136
76ad4f0e
S		 2137 return 0;
2138}
2139
2140static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2141 struct hns3_desc_cb *cb)
2142{
2143 int ret;
2144
2145 ret = hns3_alloc_buffer(ring, cb);
2146 if (ret)
2147 goto out;
2148
2149 ret = hns3_map_buffer(ring, cb);
2150 if (ret)
2151 goto out_with_buf;
2152
2153 return 0;
2154
2155out_with_buf:
564883bb 2156 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2157out:
2158 return ret;
2159}
2160
2161static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2162{
2163 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2164
2165 if (ret)
2166 return ret;
2167
2168 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2169
2170 return 0;
2171}
2172
2173/* Allocate memory for raw pkg, and map with dma */
2174static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2175{
2176 int i, j, ret;
2177
2178 for (i = 0; i < ring->desc_num; i++) {
2179 ret = hns3_alloc_buffer_attach(ring, i);
2180 if (ret)
2181 goto out_buffer_fail;
2182 }
2183
2184 return 0;
2185
2186out_buffer_fail:
2187 for (j = i - 1; j >= 0; j--)
2188 hns3_free_buffer_detach(ring, j);
2189 return ret;
2190}
2191
2192/* detach a in-used buffer and replace with a reserved one */
2193static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2194 struct hns3_desc_cb *res_cb)
2195{
b9077428 2196 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2197 ring->desc_cb[i] = *res_cb;
2198 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2199 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2200}
2201
2202static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2203{
2204 ring->desc_cb[i].reuse_flag = 0;
2205 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2206 + ring->desc_cb[i].page_offset);
7d0b130c 2207 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2208}
2209
ce74370c
YL		 2210static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2211 int *bytes, int *pkts)
76ad4f0e 2212{
26cda2f1
YL		 2213 int ntc = ring->next_to_clean;
2214 struct hns3_desc_cb *desc_cb;
76ad4f0e 2215
ce74370c
YL		 2216 while (head != ntc) {
2217 desc_cb = &ring->desc_cb[ntc];
2218 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2219 (*bytes) += desc_cb->length;
2220 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2221 hns3_free_buffer_detach(ring, ntc);
76ad4f0e 2222
ce74370c
YL		 2223 if (++ntc == ring->desc_num)
2224 ntc = 0;
2225
2226 /* Issue prefetch for next Tx descriptor */
2227 prefetch(&ring->desc_cb[ntc]);
2228 }
26cda2f1
YL		 2229
2230 /* This smp_store_release() pairs with smp_load_acquire() in
2231 * ring_space called by hns3_nic_net_xmit.
2232 */
2233 smp_store_release(&ring->next_to_clean, ntc);
76ad4f0e
S		 2234}
2235
2236static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2237{
2238 int u = ring->next_to_use;
2239 int c = ring->next_to_clean;
2240
2241 if (unlikely(h > ring->desc_num))
2242 return 0;
2243
2244 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2245}
2246
799997a3 2247void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 2248{
2249 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
7a810110 2250 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2251 struct netdev_queue *dev_queue;
2252 int bytes, pkts;
2253 int head;
2254
2255 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2256 rmb(); /* Make sure head is ready before touch any data */
2257
2258 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2259 return; /* no data to poll */
76ad4f0e 2260
0e6084aa 2261 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 2262 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2263 ring->next_to_use, ring->next_to_clean);
2264
2265 u64_stats_update_begin(&ring->syncp);
2266 ring->stats.io_err_cnt++;
2267 u64_stats_update_end(&ring->syncp);
799997a3 2268 return;
76ad4f0e
S		 2269 }
2270
2271 bytes = 0;
2272 pkts = 0;
ce74370c 2273 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
76ad4f0e
S		 2274
2275 ring->tqp_vector->tx_group.total_bytes += bytes;
2276 ring->tqp_vector->tx_group.total_packets += pkts;
2277
2278 u64_stats_update_begin(&ring->syncp);
2279 ring->stats.tx_bytes += bytes;
2280 ring->stats.tx_pkts += pkts;
2281 u64_stats_update_end(&ring->syncp);
2282
2283 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2284 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2285
2286 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2287 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2288 /* Make sure that anybody stopping the queue after this
2289 * sees the new next_to_clean.
2290 */
2291 smp_mb();
7a810110
JS		 2292 if (netif_tx_queue_stopped(dev_queue) &&
2293 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2294 netif_tx_wake_queue(dev_queue);
2295 ring->stats.restart_queue++;
2296 }
2297 }
76ad4f0e
S		 2298}
2299
2300static int hns3_desc_unused(struct hns3_enet_ring *ring)
2301{
2302 int ntc = ring->next_to_clean;
2303 int ntu = ring->next_to_use;
2304
2305 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2306}
2307
2308static void
2309hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2310{
2311 struct hns3_desc_cb *desc_cb;
2312 struct hns3_desc_cb res_cbs;
2313 int i, ret;
2314
2315 for (i = 0; i < cleand_count; i++) {
2316 desc_cb = &ring->desc_cb[ring->next_to_use];
2317 if (desc_cb->reuse_flag) {
2318 u64_stats_update_begin(&ring->syncp);
2319 ring->stats.reuse_pg_cnt++;
2320 u64_stats_update_end(&ring->syncp);
2321
2322 hns3_reuse_buffer(ring, ring->next_to_use);
2323 } else {
2324 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2325 if (ret) {
2326 u64_stats_update_begin(&ring->syncp);
2327 ring->stats.sw_err_cnt++;
2328 u64_stats_update_end(&ring->syncp);
2329
2330 netdev_err(ring->tqp->handle->kinfo.netdev,
2331 "hnae reserve buffer map failed.\n");
2332 break;
2333 }
2334 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 2335
2336 u64_stats_update_begin(&ring->syncp);
2337 ring->stats.non_reuse_pg++;
2338 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 2339 }
2340
2341 ring_ptr_move_fw(ring, next_to_use);
2342 }
2343
2344 wmb(); /* Make all data has been write before submit */
2345 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2346}
2347
76ad4f0e
S		 2348static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2349 struct hns3_enet_ring *ring, int pull_len,
2350 struct hns3_desc_cb *desc_cb)
2351{
389ca146
YL		 2352 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2353 int size = le16_to_cpu(desc->rx.size);
2354 u32 truesize = hnae3_buf_size(ring);
76ad4f0e
S		 2355
2356 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2357 size - pull_len, truesize);
76ad4f0e 2358
389ca146
YL		 2359 /* Avoid re-using remote pages, or the stack is still using the page
2360 * when page_offset rollback to zero, flag default unreuse
2361 */
2362 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()) ||
2363 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
76ad4f0e 2364 return;
76ad4f0e
S		 2365
2366 /* Move offset up to the next cache line */
2367 desc_cb->page_offset += truesize;
2368
389ca146 2369 if (desc_cb->page_offset + truesize <= hnae3_page_size(ring)) {
76ad4f0e
S		 2370 desc_cb->reuse_flag = 1;
2371 /* Bump ref count on page before it is given*/
2372 get_page(desc_cb->priv);
389ca146
YL		 2373 } else if (page_count(desc_cb->priv) == 1) {
2374 desc_cb->reuse_flag = 1;
2375 desc_cb->page_offset = 0;
2376 get_page(desc_cb->priv);
76ad4f0e
S		 2377 }
2378}
2379
d474d88f
YL		 2380static int hns3_gro_complete(struct sk_buff *skb)
2381{
2382 __be16 type = skb->protocol;
2383 struct tcphdr *th;
2384 int depth = 0;
2385
2386 while (type == htons(ETH_P_8021Q)) {
2387 struct vlan_hdr *vh;
2388
2389 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2390 return -EFAULT;
2391
2392 vh = (struct vlan_hdr *)(skb->data + depth);
2393 type = vh->h_vlan_encapsulated_proto;
2394 depth += VLAN_HLEN;
2395 }
2396
2397 if (type == htons(ETH_P_IP)) {
2398 depth += sizeof(struct iphdr);
2399 } else if (type == htons(ETH_P_IPV6)) {
2400 depth += sizeof(struct ipv6hdr);
2401 } else {
2402 netdev_err(skb->dev,
2403 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2404 be16_to_cpu(type), depth);
2405 return -EFAULT;
2406 }
2407
2408 th = (struct tcphdr *)(skb->data + depth);
2409 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2410 if (th->cwr)
2411 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2412
2413 skb->ip_summed = CHECKSUM_UNNECESSARY;
2414
2415 return 0;
2416}
2417
76ad4f0e 2418static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
39c38824 2419 u32 l234info, u32 bd_base_info, u32 ol_info)
76ad4f0e
S		 2420{
2421 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2422 int l3_type, l4_type;
76ad4f0e 2423 int ol4_type;
76ad4f0e
S		 2424
2425 skb->ip_summed = CHECKSUM_NONE;
2426
2427 skb_checksum_none_assert(skb);
2428
2429 if (!(netdev->features & NETIF_F_RXCSUM))
2430 return;
2431
2432 /* check if hardware has done checksum */
e8149933 2433 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S		 2434 return;
2435
f4772dee
DC		 2436 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2437 BIT(HNS3_RXD_OL3E_B) |
e8149933 2438 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S		 2439 u64_stats_update_begin(&ring->syncp);
2440 ring->stats.l3l4_csum_err++;
2441 u64_stats_update_end(&ring->syncp);
2442
2443 return;
2444 }
2445
39c38824 2446 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 2447 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2448 switch (ol4_type) {
2449 case HNS3_OL4_TYPE_MAC_IN_UDP:
2450 case HNS3_OL4_TYPE_NVGRE:
2451 skb->csum_level = 1;
be44b3af 2452 /* fall through */
76ad4f0e 2453 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 2454 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2455 HNS3_RXD_L3ID_S);
2456 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2457 HNS3_RXD_L4ID_S);
2458
76ad4f0e 2459 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2460 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2461 l3_type == HNS3_L3_TYPE_IPV6) &&
2462 (l4_type == HNS3_L4_TYPE_UDP ||
2463 l4_type == HNS3_L4_TYPE_TCP ||
2464 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2465 skb->ip_summed = CHECKSUM_UNNECESSARY;
2466 break;
fa7a4bd5
JS		 2467 default:
2468 break;
76ad4f0e
S		 2469 }
2470}
2471
d43e5aca
YL		 2472static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2473{
81ae0e04
PL		 2474 if (skb_has_frag_list(skb))
2475 napi_gro_flush(&ring->tqp_vector->napi, false);
2476
d43e5aca
YL		 2477 napi_gro_receive(&ring->tqp_vector->napi, skb);
2478}
2479
701a6d6a
JS		 2480static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2481 struct hns3_desc *desc, u32 l234info,
2482 u16 *vlan_tag)
5b5455a9 2483{
44e626f7 2484 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 2485 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL		 2486
2487 if (pdev->revision == 0x20) {
701a6d6a
JS		 2488 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2489 if (!(*vlan_tag & VLAN_VID_MASK))
2490 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2491
701a6d6a 2492 return (*vlan_tag != 0);
5b5455a9
PL		 2493 }
2494
2495#define HNS3_STRP_OUTER_VLAN 0x1
2496#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 2497#define HNS3_STRP_BOTH 0x3
5b5455a9 2498
44e626f7
JS		 2499 /* Hardware always insert VLAN tag into RX descriptor when
2500 * remove the tag from packet, driver needs to determine
2501 * reporting which tag to stack.
2502 */
e4e87715
PL		 2503 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2504 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2505 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 2506 if (handle->port_base_vlan_state !=
2507 HNAE3_PORT_BASE_VLAN_DISABLE)
2508 return false;
2509
701a6d6a
JS		 2510 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2511 return true;
5b5455a9 2512 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 2513 if (handle->port_base_vlan_state !=
2514 HNAE3_PORT_BASE_VLAN_DISABLE)
2515 return false;
2516
701a6d6a 2517 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 2518 return true;
2519 case HNS3_STRP_BOTH:
2520 if (handle->port_base_vlan_state ==
2521 HNAE3_PORT_BASE_VLAN_DISABLE)
2522 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2523 else
2524 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2525
701a6d6a 2526 return true;
5b5455a9 2527 default:
701a6d6a 2528 return false;
5b5455a9 2529 }
5b5455a9
PL		 2530}
2531
e5597095
PL		 2532static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2533 unsigned char *va)
2534{
2535#define HNS3_NEED_ADD_FRAG 1
2536 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2537 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2538 struct sk_buff *skb;
2539
2540 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2541 skb = ring->skb;
2542 if (unlikely(!skb)) {
2543 netdev_err(netdev, "alloc rx skb fail\n");
2544
2545 u64_stats_update_begin(&ring->syncp);
2546 ring->stats.sw_err_cnt++;
2547 u64_stats_update_end(&ring->syncp);
2548
2549 return -ENOMEM;
2550 }
2551
2552 prefetchw(skb->data);
2553
2554 ring->pending_buf = 1;
81ae0e04
PL		 2555 ring->frag_num = 0;
2556 ring->tail_skb = NULL;
e5597095
PL		 2557 if (length <= HNS3_RX_HEAD_SIZE) {
2558 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2559
2560 /* We can reuse buffer as-is, just make sure it is local */
2561 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2562 desc_cb->reuse_flag = 1;
2563 else /* This page cannot be reused so discard it */
2564 put_page(desc_cb->priv);
2565
2566 ring_ptr_move_fw(ring, next_to_clean);
2567 return 0;
2568 }
2569 u64_stats_update_begin(&ring->syncp);
2570 ring->stats.seg_pkt_cnt++;
2571 u64_stats_update_end(&ring->syncp);
2572
c43f1255 2573 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 2574 __skb_put(skb, ring->pull_len);
81ae0e04 2575 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL		 2576 desc_cb);
2577 ring_ptr_move_fw(ring, next_to_clean);
2578
2579 return HNS3_NEED_ADD_FRAG;
2580}
2581
2582static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2583 struct sk_buff **out_skb, bool pending)
2584{
2585 struct sk_buff *skb = *out_skb;
81ae0e04
PL		 2586 struct sk_buff *head_skb = *out_skb;
2587 struct sk_buff *new_skb;
e5597095
PL		 2588 struct hns3_desc_cb *desc_cb;
2589 struct hns3_desc *pre_desc;
2590 u32 bd_base_info;
2591 int pre_bd;
2592
2593 /* if there is pending bd, the SW param next_to_clean has moved
2594 * to next and the next is NULL
2595 */
2596 if (pending) {
2597 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2598 ring->desc_num;
2599 pre_desc = &ring->desc[pre_bd];
2600 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2601 } else {
2602 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2603 }
2604
e8149933 2605 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
e5597095
PL		 2606 desc = &ring->desc[ring->next_to_clean];
2607 desc_cb = &ring->desc_cb[ring->next_to_clean];
2608 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 2609 /* make sure HW write desc complete */
2610 dma_rmb();
e8149933 2611 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 2612 return -ENXIO;
2613
81ae0e04
PL		 2614 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2615 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2616 HNS3_RX_HEAD_SIZE);
2617 if (unlikely(!new_skb)) {
2618 netdev_err(ring->tqp->handle->kinfo.netdev,
2619 "alloc rx skb frag fail\n");
2620 return -ENXIO;
2621 }
2622 ring->frag_num = 0;
2623
2624 if (ring->tail_skb) {
2625 ring->tail_skb->next = new_skb;
2626 ring->tail_skb = new_skb;
2627 } else {
2628 skb_shinfo(skb)->frag_list = new_skb;
2629 ring->tail_skb = new_skb;
2630 }
2631 }
2632
2633 if (ring->tail_skb) {
2634 head_skb->truesize += hnae3_buf_size(ring);
2635 head_skb->data_len += le16_to_cpu(desc->rx.size);
2636 head_skb->len += le16_to_cpu(desc->rx.size);
2637 skb = ring->tail_skb;
2638 }
2639
2640 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
e5597095
PL		 2641 ring_ptr_move_fw(ring, next_to_clean);
2642 ring->pending_buf++;
2643 }
2644
2645 return 0;
2646}
2647
d474d88f
YL		 2648static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2649 struct sk_buff *skb, u32 l234info,
39c38824 2650 u32 bd_base_info, u32 ol_info)
a6d53b97
PL		 2651{
2652 u16 gro_count;
2653 u32 l3_type;
2654
2655 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2656 HNS3_RXD_GRO_COUNT_S);
2657 /* if there is no HW GRO, do not set gro params */
d474d88f 2658 if (!gro_count) {
39c38824 2659 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
d474d88f
YL		 2660 return 0;
2661 }
a6d53b97 2662
a6d53b97
PL		 2663 NAPI_GRO_CB(skb)->count = gro_count;
2664
2665 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2666 HNS3_RXD_L3ID_S);
2667 if (l3_type == HNS3_L3_TYPE_IPV4)
2668 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2669 else if (l3_type == HNS3_L3_TYPE_IPV6)
2670 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2671 else
d474d88f 2672 return -EFAULT;
a6d53b97
PL		 2673
2674 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2675 HNS3_RXD_GRO_SIZE_M,
2676 HNS3_RXD_GRO_SIZE_S);
d474d88f
YL		 2677
2678 return hns3_gro_complete(skb);
a6d53b97
PL		 2679}
2680
232fc64b 2681static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 2682 struct sk_buff *skb, u32 rss_hash)
232fc64b 2683{
232fc64b
PL		 2684 struct hnae3_handle *handle = ring->tqp->handle;
2685 enum pkt_hash_types rss_type;
2686
ea485867 2687 if (rss_hash)
232fc64b
PL		 2688 rss_type = handle->kinfo.rss_type;
2689 else
2690 rss_type = PKT_HASH_TYPE_NONE;
2691
ea485867 2692 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 2693}
2694
ea485867 2695static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e
S		 2696{
2697 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
c376fa1a 2698 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 2699 u32 bd_base_info, l234info, ol_info;
ea485867 2700 struct hns3_desc *desc;
d474d88f 2701 unsigned int len;
ea485867
YL		 2702 int pre_ntc, ret;
2703
2704 /* bdinfo handled below is only valid on the last BD of the
2705 * current packet, and ring->next_to_clean indicates the first
2706 * descriptor of next packet, so need - 1 below.
2707 */
2708 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2709 (ring->desc_num - 1);
2710 desc = &ring->desc[pre_ntc];
2711 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2712 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 2713 ol_info = le32_to_cpu(desc->rx.ol_info);
d474d88f
YL		 2714
2715 /* Based on hw strategy, the tag offloaded will be stored at
2716 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2717 * in one layer tag case.
2718 */
2719 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2720 u16 vlan_tag;
2721
2722 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2723 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2724 vlan_tag);
2725 }
2726
2727 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) {
2728 u64_stats_update_begin(&ring->syncp);
2729 ring->stats.non_vld_descs++;
2730 u64_stats_update_end(&ring->syncp);
2731
2732 return -EINVAL;
2733 }
2734
2735 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
2736 BIT(HNS3_RXD_L2E_B))))) {
2737 u64_stats_update_begin(&ring->syncp);
2738 if (l234info & BIT(HNS3_RXD_L2E_B))
2739 ring->stats.l2_err++;
2740 else
2741 ring->stats.err_pkt_len++;
2742 u64_stats_update_end(&ring->syncp);
2743
2744 return -EFAULT;
2745 }
2746
2747 len = skb->len;
2748
2749 /* Do update ip stack process */
2750 skb->protocol = eth_type_trans(skb, netdev);
2751
2752 /* This is needed in order to enable forwarding support */
39c38824
YL		 2753 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
2754 bd_base_info, ol_info);
d474d88f
YL		 2755 if (unlikely(ret)) {
2756 u64_stats_update_begin(&ring->syncp);
2757 ring->stats.rx_err_cnt++;
2758 u64_stats_update_end(&ring->syncp);
2759 return ret;
2760 }
2761
2762 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
2763 HNS3_RXD_DMAC_S);
2764
2765 u64_stats_update_begin(&ring->syncp);
2766 ring->stats.rx_pkts++;
2767 ring->stats.rx_bytes += len;
2768
2769 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
2770 ring->stats.rx_multicast++;
2771
2772 u64_stats_update_end(&ring->syncp);
2773
2774 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 2775
2776 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 2777 return 0;
2778}
2779
2780static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2781 struct sk_buff **out_skb)
2782{
e5597095 2783 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 2784 struct hns3_desc_cb *desc_cb;
2785 struct hns3_desc *desc;
76ad4f0e 2786 u32 bd_base_info;
76ad4f0e 2787 int length;
e5597095 2788 int ret;
76ad4f0e
S		 2789
2790 desc = &ring->desc[ring->next_to_clean];
2791 desc_cb = &ring->desc_cb[ring->next_to_clean];
2792
2793 prefetch(desc);
2794
846fcc83 2795 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2796 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2797
2798 /* Check valid BD */
e8149933 2799 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
e5597095 2800 return -ENXIO;
76ad4f0e 2801
e5597095
PL		 2802 if (!skb)
2803 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S		 2804
2805 /* Prefetch first cache line of first page
2806 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2807 * line size is 64B so need to prefetch twice to make it 128B. But in
2808 * actual we can have greater size of caches with 128B Level 1 cache
2809 * lines. In such a case, single fetch would suffice to cache in the
2810 * relevant part of the header.
2811 */
e5597095 2812 prefetch(ring->va);
76ad4f0e 2813#if L1_CACHE_BYTES < 128
e5597095 2814 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S		 2815#endif
2816
e5597095
PL		 2817 if (!skb) {
2818 ret = hns3_alloc_skb(ring, length, ring->va);
2819 *out_skb = skb = ring->skb;
76ad4f0e 2820
e5597095
PL		 2821 if (ret < 0) /* alloc buffer fail */
2822 return ret;
2823 if (ret > 0) { /* need add frag */
2824 ret = hns3_add_frag(ring, desc, &skb, false);
2825 if (ret)
2826 return ret;
76ad4f0e 2827
e5597095
PL		 2828 /* As the head data may be changed when GRO enable, copy
2829 * the head data in after other data rx completed
2830 */
2831 memcpy(skb->data, ring->va,
2832 ALIGN(ring->pull_len, sizeof(long)));
2833 }
76ad4f0e 2834 } else {
e5597095
PL		 2835 ret = hns3_add_frag(ring, desc, &skb, true);
2836 if (ret)
2837 return ret;
76ad4f0e 2838
e5597095
PL		 2839 /* As the head data may be changed when GRO enable, copy
2840 * the head data in after other data rx completed
2841 */
2842 memcpy(skb->data, ring->va,
2843 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S		 2844 }
2845
ea485867 2846 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 2847 if (unlikely(ret)) {
76ad4f0e 2848 dev_kfree_skb_any(skb);
d474d88f 2849 return ret;
76ad4f0e
S		 2850 }
2851
e5597095 2852 *out_skb = skb;
232fc64b 2853
76ad4f0e
S		 2854 return 0;
2855}
2856
d43e5aca
YL		 2857int hns3_clean_rx_ring(
2858 struct hns3_enet_ring *ring, int budget,
2859 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2860{
2861#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
76ad4f0e 2862 int recv_pkts, recv_bds, clean_count, err;
63380a1a 2863 int unused_count = hns3_desc_unused(ring);
e5597095
PL		 2864 struct sk_buff *skb = ring->skb;
2865 int num;
76ad4f0e
S		 2866
2867 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2868 rmb(); /* Make sure num taken effect before the other data is touched */
2869
2870 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2871 num -= unused_count;
63380a1a 2872 unused_count -= ring->pending_buf;
76ad4f0e
S		 2873
2874 while (recv_pkts < budget && recv_bds < num) {
2875 /* Reuse or realloc buffers */
2876 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2877 hns3_nic_alloc_rx_buffers(ring,
2878 clean_count + unused_count);
2879 clean_count = 0;
e5597095
PL		 2880 unused_count = hns3_desc_unused(ring) -
2881 ring->pending_buf;
76ad4f0e
S		 2882 }
2883
2884 /* Poll one pkt */
e5597095 2885 err = hns3_handle_rx_bd(ring, &skb);
76ad4f0e
S		 2886 if (unlikely(!skb)) /* This fault cannot be repaired */
2887 goto out;
2888
e5597095
PL		 2889 if (err == -ENXIO) { /* Do not get FE for the packet */
2890 goto out;
2891 } else if (unlikely(err)) { /* Do jump the err */
2892 recv_bds += ring->pending_buf;
2893 clean_count += ring->pending_buf;
2894 ring->skb = NULL;
2895 ring->pending_buf = 0;
76ad4f0e
S		 2896 continue;
2897 }
2898
d43e5aca 2899 rx_fn(ring, skb);
e5597095
PL		 2900 recv_bds += ring->pending_buf;
2901 clean_count += ring->pending_buf;
2902 ring->skb = NULL;
2903 ring->pending_buf = 0;
76ad4f0e
S		 2904
2905 recv_pkts++;
2906 }
2907
2908out:
2909 /* Make all data has been write before submit */
2910 if (clean_count + unused_count > 0)
2911 hns3_nic_alloc_rx_buffers(ring,
2912 clean_count + unused_count);
2913
2914 return recv_pkts;
2915}
2916
2917static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2918{
a95e1f86
FL		 2919 struct hns3_enet_tqp_vector *tqp_vector =
2920 ring_group->ring->tqp_vector;
76ad4f0e 2921 enum hns3_flow_level_range new_flow_level;
a95e1f86
FL		 2922 int packets_per_msecs;
2923 int bytes_per_msecs;
2924 u32 time_passed_ms;
76ad4f0e 2925 u16 new_int_gl;
76ad4f0e 2926
6241e71e 2927 if (!tqp_vector->last_jiffies)
76ad4f0e
S		 2928 return false;
2929
2930 if (ring_group->total_packets == 0) {
9bc727a9
YL		 2931 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2932 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2933 return true;
2934 }
2935
2936 /* Simple throttlerate management
2937 * 0-10MB/s lower (50000 ints/s)
2938 * 10-20MB/s middle (20000 ints/s)
2939 * 20-1249MB/s high (18000 ints/s)
2940 * > 40000pps ultra (8000 ints/s)
2941 */
9bc727a9
YL		 2942 new_flow_level = ring_group->coal.flow_level;
2943 new_int_gl = ring_group->coal.int_gl;
a95e1f86
FL		 2944 time_passed_ms =
2945 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2946
2947 if (!time_passed_ms)
2948 return false;
2949
2950 do_div(ring_group->total_packets, time_passed_ms);
2951 packets_per_msecs = ring_group->total_packets;
2952
2953 do_div(ring_group->total_bytes, time_passed_ms);
2954 bytes_per_msecs = ring_group->total_bytes;
2955
2956#define HNS3_RX_LOW_BYTE_RATE 10000
2957#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2958
2959 switch (new_flow_level) {
2960 case HNS3_FLOW_LOW:
a95e1f86 2961 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2962 new_flow_level = HNS3_FLOW_MID;
2963 break;
2964 case HNS3_FLOW_MID:
a95e1f86 2965 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2966 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 2967 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2968 new_flow_level = HNS3_FLOW_LOW;
2969 break;
2970 case HNS3_FLOW_HIGH:
2971 case HNS3_FLOW_ULTRA:
2972 default:
a95e1f86 2973 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2974 new_flow_level = HNS3_FLOW_MID;
2975 break;
2976 }
2977
a95e1f86
FL		 2978#define HNS3_RX_ULTRA_PACKET_RATE 40
2979
2980 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2981 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2982 new_flow_level = HNS3_FLOW_ULTRA;
2983
2984 switch (new_flow_level) {
2985 case HNS3_FLOW_LOW:
2986 new_int_gl = HNS3_INT_GL_50K;
2987 break;
2988 case HNS3_FLOW_MID:
2989 new_int_gl = HNS3_INT_GL_20K;
2990 break;
2991 case HNS3_FLOW_HIGH:
2992 new_int_gl = HNS3_INT_GL_18K;
2993 break;
2994 case HNS3_FLOW_ULTRA:
2995 new_int_gl = HNS3_INT_GL_8K;
2996 break;
2997 default:
2998 break;
2999 }
3000
3001 ring_group->total_bytes = 0;
3002 ring_group->total_packets = 0;
9bc727a9
YL		 3003 ring_group->coal.flow_level = new_flow_level;
3004 if (new_int_gl != ring_group->coal.int_gl) {
3005 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 3006 return true;
3007 }
3008 return false;
3009}
3010
3011static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3012{
8b1ff1ea
FL		 3013 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3014 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3015 bool rx_update, tx_update;
3016
7445565c
PL		 3017 /* update param every 1000ms */
3018 if (time_before(jiffies,
3019 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3020 return;
cd9d187b 3021
9bc727a9 3022 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 3023 rx_update = hns3_get_new_int_gl(rx_group);
3024 if (rx_update)
3025 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3026 rx_group->coal.int_gl);
8b1ff1ea
FL		 3027 }
3028
9bc727a9 3029 if (tx_group->coal.gl_adapt_enable) {
9e50dc11 3030 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL		 3031 if (tx_update)
3032 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3033 tx_group->coal.int_gl);
76ad4f0e 3034 }
cd9d187b 3035
a95e1f86 3036 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 3037}
3038
3039static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3040{
ff0699e0 3041 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 3042 struct hns3_enet_ring *ring;
3043 int rx_pkt_total = 0;
3044
3045 struct hns3_enet_tqp_vector *tqp_vector =
3046 container_of(napi, struct hns3_enet_tqp_vector, napi);
3047 bool clean_complete = true;
ceca4a5e 3048 int rx_budget = budget;
76ad4f0e 3049
ff0699e0
HT		 3050 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3051 napi_complete(napi);
3052 return 0;
3053 }
3054
76ad4f0e
S		 3055 /* Since the actual Tx work is minimal, we can give the Tx a larger
3056 * budget and be more aggressive about cleaning up the Tx descriptors.
3057 */
799997a3
PL		 3058 hns3_for_each_ring(ring, tqp_vector->tx_group)
3059 hns3_clean_tx_ring(ring);
76ad4f0e
S		 3060
3061 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 3062 if (tqp_vector->num_tqps > 1)
3063 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 3064
3065 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 3066 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3067 hns3_rx_skb);
76ad4f0e
S		 3068
3069 if (rx_cleaned >= rx_budget)
3070 clean_complete = false;
3071
3072 rx_pkt_total += rx_cleaned;
3073 }
3074
3075 tqp_vector->rx_group.total_packets += rx_pkt_total;
3076
3077 if (!clean_complete)
3078 return budget;
3079
531eba0f
HT		 3080 if (napi_complete(napi) &&
3081 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 3082 hns3_update_new_int_gl(tqp_vector);
3083 hns3_mask_vector_irq(tqp_vector, 1);
3084 }
76ad4f0e
S		 3085
3086 return rx_pkt_total;
3087}
3088
3089static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3090 struct hnae3_ring_chain_node *head)
3091{
3092 struct pci_dev *pdev = tqp_vector->handle->pdev;
3093 struct hnae3_ring_chain_node *cur_chain = head;
3094 struct hnae3_ring_chain_node *chain;
3095 struct hns3_enet_ring *tx_ring;
3096 struct hns3_enet_ring *rx_ring;
3097
3098 tx_ring = tqp_vector->tx_group.ring;
3099 if (tx_ring) {
3100 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3101 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3102 HNAE3_RING_TYPE_TX);
3103 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3104 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 3105
3106 cur_chain->next = NULL;
3107
3108 while (tx_ring->next) {
3109 tx_ring = tx_ring->next;
3110
3111 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3112 GFP_KERNEL);
3113 if (!chain)
73b907a0 3114 goto err_free_chain;
76ad4f0e
S		 3115
3116 cur_chain->next = chain;
3117 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3118 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3119 HNAE3_RING_TYPE_TX);
3120 hnae3_set_field(chain->int_gl_idx,
3121 HNAE3_RING_GL_IDX_M,
3122 HNAE3_RING_GL_IDX_S,
3123 HNAE3_RING_GL_TX);
76ad4f0e
S		 3124
3125 cur_chain = chain;
3126 }
3127 }
3128
3129 rx_ring = tqp_vector->rx_group.ring;
3130 if (!tx_ring && rx_ring) {
3131 cur_chain->next = NULL;
3132 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3133 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3134 HNAE3_RING_TYPE_RX);
3135 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3136 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 3137
3138 rx_ring = rx_ring->next;
3139 }
3140
3141 while (rx_ring) {
3142 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3143 if (!chain)
73b907a0 3144 goto err_free_chain;
76ad4f0e
S		 3145
3146 cur_chain->next = chain;
3147 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3148 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3149 HNAE3_RING_TYPE_RX);
3150 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3151 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3152
76ad4f0e
S		 3153 cur_chain = chain;
3154
3155 rx_ring = rx_ring->next;
3156 }
3157
3158 return 0;
73b907a0
HT		 3159
3160err_free_chain:
3161 cur_chain = head->next;
3162 while (cur_chain) {
3163 chain = cur_chain->next;
cda69d24 3164 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 3165 cur_chain = chain;
3166 }
cda69d24 3167 head->next = NULL;
73b907a0
HT		 3168
3169 return -ENOMEM;
76ad4f0e
S		 3170}
3171
3172static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3173 struct hnae3_ring_chain_node *head)
3174{
3175 struct pci_dev *pdev = tqp_vector->handle->pdev;
3176 struct hnae3_ring_chain_node *chain_tmp, *chain;
3177
3178 chain = head->next;
3179
3180 while (chain) {
3181 chain_tmp = chain->next;
3182 devm_kfree(&pdev->dev, chain);
3183 chain = chain_tmp;
3184 }
3185}
3186
3187static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3188 struct hns3_enet_ring *ring)
3189{
3190 ring->next = group->ring;
3191 group->ring = ring;
3192
3193 group->count++;
3194}
3195
874bff0b
PL		 3196static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3197{
3198 struct pci_dev *pdev = priv->ae_handle->pdev;
3199 struct hns3_enet_tqp_vector *tqp_vector;
3200 int num_vectors = priv->vector_num;
3201 int numa_node;
3202 int vector_i;
3203
3204 numa_node = dev_to_node(&pdev->dev);
3205
3206 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3207 tqp_vector = &priv->tqp_vector[vector_i];
3208 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3209 &tqp_vector->affinity_mask);
3210 }
3211}
3212
76ad4f0e
S		 3213static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3214{
3215 struct hnae3_ring_chain_node vector_ring_chain;
3216 struct hnae3_handle *h = priv->ae_handle;
3217 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3218 int ret = 0;
ece4bf46 3219 int i;
76ad4f0e 3220
874bff0b
PL		 3221 hns3_nic_set_cpumask(priv);
3222
dd38c726
YL		 3223 for (i = 0; i < priv->vector_num; i++) {
3224 tqp_vector = &priv->tqp_vector[i];
3225 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3226 tqp_vector->num_tqps = 0;
3227 }
76ad4f0e 3228
dd38c726
YL		 3229 for (i = 0; i < h->kinfo.num_tqps; i++) {
3230 u16 vector_i = i % priv->vector_num;
3231 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3232
3233 tqp_vector = &priv->tqp_vector[vector_i];
3234
3235 hns3_add_ring_to_group(&tqp_vector->tx_group,
3236 priv->ring_data[i].ring);
3237
3238 hns3_add_ring_to_group(&tqp_vector->rx_group,
3239 priv->ring_data[i + tqp_num].ring);
3240
76ad4f0e
S		 3241 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3242 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
dd38c726 3243 tqp_vector->num_tqps++;
76ad4f0e
S		 3244 }
3245
dd38c726 3246 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3247 tqp_vector = &priv->tqp_vector[i];
3248
3249 tqp_vector->rx_group.total_bytes = 0;
3250 tqp_vector->rx_group.total_packets = 0;
3251 tqp_vector->tx_group.total_bytes = 0;
3252 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3253 tqp_vector->handle = h;
3254
3255 ret = hns3_get_vector_ring_chain(tqp_vector,
3256 &vector_ring_chain);
3257 if (ret)
cda69d24 3258 goto map_ring_fail;
76ad4f0e
S		 3259
3260 ret = h->ae_algo->ops->map_ring_to_vector(h,
3261 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3262
3263 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3264
dd38c726 3265 if (ret)
ece4bf46 3266 goto map_ring_fail;
dd38c726 3267
76ad4f0e
S		 3268 netif_napi_add(priv->netdev, &tqp_vector->napi,
3269 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3270 }
3271
dd38c726 3272 return 0;
ece4bf46
HT		 3273
3274map_ring_fail:
3275 while (i--)
3276 netif_napi_del(&priv->tqp_vector[i].napi);
3277
3278 return ret;
dd38c726
YL		 3279}
3280
3281static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3282{
75edb610
JS		 3283#define HNS3_VECTOR_PF_MAX_NUM 64
3284
dd38c726
YL		 3285 struct hnae3_handle *h = priv->ae_handle;
3286 struct hns3_enet_tqp_vector *tqp_vector;
3287 struct hnae3_vector_info *vector;
3288 struct pci_dev *pdev = h->pdev;
3289 u16 tqp_num = h->kinfo.num_tqps;
3290 u16 vector_num;
3291 int ret = 0;
3292 u16 i;
3293
3294 /* RSS size, cpu online and vector_num should be the same */
3295 /* Should consider 2p/4p later */
3296 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS		 3297 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3298
dd38c726
YL		 3299 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3300 GFP_KERNEL);
3301 if (!vector)
3302 return -ENOMEM;
3303
3304 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3305
3306 priv->vector_num = vector_num;
3307 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3308 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3309 GFP_KERNEL);
3310 if (!priv->tqp_vector) {
3311 ret = -ENOMEM;
3312 goto out;
3313 }
3314
3315 for (i = 0; i < priv->vector_num; i++) {
3316 tqp_vector = &priv->tqp_vector[i];
3317 tqp_vector->idx = i;
3318 tqp_vector->mask_addr = vector[i].io_addr;
3319 tqp_vector->vector_irq = vector[i].vector;
3320 hns3_vector_gl_rl_init(tqp_vector, priv);
3321 }
3322
76ad4f0e
S		 3323out:
3324 devm_kfree(&pdev->dev, vector);
3325 return ret;
3326}
3327
dd38c726
YL		 3328static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3329{
3330 group->ring = NULL;
3331 group->count = 0;
3332}
3333
e2152785 3334static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 3335{
3336 struct hnae3_ring_chain_node vector_ring_chain;
3337 struct hnae3_handle *h = priv->ae_handle;
3338 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3339 int i;
76ad4f0e
S		 3340
3341 for (i = 0; i < priv->vector_num; i++) {
3342 tqp_vector = &priv->tqp_vector[i];
3343
2c9dd668
HT		 3344 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3345 continue;
3346
e2152785 3347 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain);
76ad4f0e 3348
e2152785 3349 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3350 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3351
3352 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3353
ae6017a7 3354 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
ae6017a7
HT		 3355 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3356 free_irq(tqp_vector->vector_irq, tqp_vector);
3357 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S		 3358 }
3359
dd38c726
YL		 3360 hns3_clear_ring_group(&tqp_vector->rx_group);
3361 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3362 netif_napi_del(&priv->tqp_vector[i].napi);
3363 }
dd38c726
YL		 3364}
3365
3366static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3367{
3368 struct hnae3_handle *h = priv->ae_handle;
3369 struct pci_dev *pdev = h->pdev;
3370 int i, ret;
3371
3372 for (i = 0; i < priv->vector_num; i++) {
3373 struct hns3_enet_tqp_vector *tqp_vector;
3374
3375 tqp_vector = &priv->tqp_vector[i];
3376 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3377 if (ret)
3378 return ret;
3379 }
76ad4f0e 3380
dd38c726 3381 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3382 return 0;
3383}
3384
3385static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3386 int ring_type)
3387{
3388 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3389 int queue_num = priv->ae_handle->kinfo.num_tqps;
3390 struct pci_dev *pdev = priv->ae_handle->pdev;
3391 struct hns3_enet_ring *ring;
c0425944 3392 int desc_num;
76ad4f0e
S		 3393
3394 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3395 if (!ring)
3396 return -ENOMEM;
3397
3398 if (ring_type == HNAE3_RING_TYPE_TX) {
c0425944 3399 desc_num = priv->ae_handle->kinfo.num_tx_desc;
76ad4f0e 3400 ring_data[q->tqp_index].ring = ring;
66b44730 3401 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 3402 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3403 } else {
c0425944 3404 desc_num = priv->ae_handle->kinfo.num_rx_desc;
76ad4f0e 3405 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 3406 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 3407 ring->io_base = q->io_base;
3408 }
3409
e4e87715 3410 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3411
76ad4f0e
S		 3412 ring->tqp = q;
3413 ring->desc = NULL;
3414 ring->desc_cb = NULL;
3415 ring->dev = priv->dev;
3416 ring->desc_dma_addr = 0;
3417 ring->buf_size = q->buf_size;
2c9dd668 3418 ring->desc_num = desc_num;
76ad4f0e
S		 3419 ring->next_to_use = 0;
3420 ring->next_to_clean = 0;
3421
3422 return 0;
3423}
3424
3425static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3426 struct hns3_nic_priv *priv)
3427{
3428 int ret;
3429
3430 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3431 if (ret)
3432 return ret;
3433
3434 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
73b907a0
HT		 3435 if (ret) {
3436 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
76ad4f0e 3437 return ret;
73b907a0 3438 }
76ad4f0e
S		 3439
3440 return 0;
3441}
3442
3443static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3444{
3445 struct hnae3_handle *h = priv->ae_handle;
3446 struct pci_dev *pdev = h->pdev;
3447 int i, ret;
3448
a86854d0
KC		 3449 priv->ring_data = devm_kzalloc(&pdev->dev,
3450 array3_size(h->kinfo.num_tqps,
3451 sizeof(*priv->ring_data),
3452 2),
76ad4f0e
S		 3453 GFP_KERNEL);
3454 if (!priv->ring_data)
3455 return -ENOMEM;
3456
3457 for (i = 0; i < h->kinfo.num_tqps; i++) {
3458 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3459 if (ret)
3460 goto err;
3461 }
3462
3463 return 0;
3464err:
73b907a0
HT		 3465 while (i--) {
3466 devm_kfree(priv->dev, priv->ring_data[i].ring);
3467 devm_kfree(priv->dev,
3468 priv->ring_data[i + h->kinfo.num_tqps].ring);
3469 }
3470
76ad4f0e 3471 devm_kfree(&pdev->dev, priv->ring_data);
7b8f622e 3472 priv->ring_data = NULL;
76ad4f0e
S		 3473 return ret;
3474}
3475
09f2af64
PL		 3476static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3477{
3478 struct hnae3_handle *h = priv->ae_handle;
3479 int i;
3480
7b8f622e
HT		 3481 if (!priv->ring_data)
3482 return;
3483
09f2af64
PL		 3484 for (i = 0; i < h->kinfo.num_tqps; i++) {
3485 devm_kfree(priv->dev, priv->ring_data[i].ring);
3486 devm_kfree(priv->dev,
3487 priv->ring_data[i + h->kinfo.num_tqps].ring);
3488 }
3489 devm_kfree(priv->dev, priv->ring_data);
7b8f622e 3490 priv->ring_data = NULL;
09f2af64
PL		 3491}
3492
76ad4f0e
S		 3493static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3494{
3495 int ret;
3496
3497 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3498 return -EINVAL;
3499
77296bf6
YL		 3500 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3501 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 3502 if (!ring->desc_cb) {
3503 ret = -ENOMEM;
3504 goto out;
3505 }
3506
3507 ret = hns3_alloc_desc(ring);
3508 if (ret)
3509 goto out_with_desc_cb;
3510
3511 if (!HNAE3_IS_TX_RING(ring)) {
3512 ret = hns3_alloc_ring_buffers(ring);
3513 if (ret)
3514 goto out_with_desc;
3515 }
3516
3517 return 0;
3518
3519out_with_desc:
3520 hns3_free_desc(ring);
3521out_with_desc_cb:
77296bf6 3522 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3523 ring->desc_cb = NULL;
3524out:
3525 return ret;
3526}
3527
3528static void hns3_fini_ring(struct hns3_enet_ring *ring)
3529{
3530 hns3_free_desc(ring);
77296bf6 3531 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3532 ring->desc_cb = NULL;
3533 ring->next_to_clean = 0;
3534 ring->next_to_use = 0;
ac574b80
PL		 3535 ring->pending_buf = 0;
3536 if (ring->skb) {
3537 dev_kfree_skb_any(ring->skb);
3538 ring->skb = NULL;
3539 }
76ad4f0e
S		 3540}
3541
1db9b1bf 3542static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3543{
3544 int bd_size_type;
3545
3546 switch (buf_size) {
3547 case 512:
3548 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3549 break;
3550 case 1024:
3551 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3552 break;
3553 case 2048:
3554 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3555 break;
3556 case 4096:
3557 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3558 break;
3559 default:
3560 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3561 }
3562
3563 return bd_size_type;
3564}
3565
3566static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3567{
3568 dma_addr_t dma = ring->desc_dma_addr;
3569 struct hnae3_queue *q = ring->tqp;
3570
3571 if (!HNAE3_IS_TX_RING(ring)) {
3572 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3573 (u32)dma);
3574 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3575 (u32)((dma >> 31) >> 1));
3576
3577 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3578 hns3_buf_size2type(ring->buf_size));
3579 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3580 ring->desc_num / 8 - 1);
3581
3582 } else {
3583 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3584 (u32)dma);
3585 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3586 (u32)((dma >> 31) >> 1));
3587
76ad4f0e
S		 3588 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3589 ring->desc_num / 8 - 1);
3590 }
3591}
3592
1c772154
YL		 3593static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3594{
3595 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3596 int i;
3597
3598 for (i = 0; i < HNAE3_MAX_TC; i++) {
3599 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3600 int j;
3601
3602 if (!tc_info->enable)
3603 continue;
3604
3605 for (j = 0; j < tc_info->tqp_count; j++) {
3606 struct hnae3_queue *q;
3607
3608 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3609 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3610 tc_info->tc);
3611 }
3612 }
3613}
3614
5668abda 3615int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3616{
3617 struct hnae3_handle *h = priv->ae_handle;
3618 int ring_num = h->kinfo.num_tqps * 2;
3619 int i, j;
3620 int ret;
3621
3622 for (i = 0; i < ring_num; i++) {
3623 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3624 if (ret) {
3625 dev_err(priv->dev,
3626 "Alloc ring memory fail! ret=%d\n", ret);
3627 goto out_when_alloc_ring_memory;
3628 }
3629
76ad4f0e
S		 3630 u64_stats_init(&priv->ring_data[i].ring->syncp);
3631 }
3632
3633 return 0;
3634
3635out_when_alloc_ring_memory:
3636 for (j = i - 1; j >= 0; j--)
ee83f776 3637 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3638
3639 return -ENOMEM;
3640}
3641
5668abda 3642int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3643{
3644 struct hnae3_handle *h = priv->ae_handle;
3645 int i;
3646
3647 for (i = 0; i < h->kinfo.num_tqps; i++) {
76ad4f0e
S		 3648 hns3_fini_ring(priv->ring_data[i].ring);
3649 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3650 }
76ad4f0e
S		 3651 return 0;
3652}
3653
3654/* Set mac addr if it is configured. or leave it to the AE driver */
7fa6be4f 3655static int hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3656{
3657 struct hns3_nic_priv *priv = netdev_priv(netdev);
3658 struct hnae3_handle *h = priv->ae_handle;
3659 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3660 int ret = 0;
76ad4f0e 3661
f09555ff 3662 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3663 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3664 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3665 }
3666
3667 /* Check if the MAC address is valid, if not get a random one */
3668 if (!is_valid_ether_addr(netdev->dev_addr)) {
3669 eth_hw_addr_random(netdev);
3670 dev_warn(priv->dev, "using random MAC address %pM\n",
3671 netdev->dev_addr);
76ad4f0e 3672 }
139e8792
L		 3673
3674 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3675 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3676
7fa6be4f 3677 return ret;
76ad4f0e
S		 3678}
3679
c8a8045b
HT		 3680static int hns3_init_phy(struct net_device *netdev)
3681{
3682 struct hnae3_handle *h = hns3_get_handle(netdev);
3683 int ret = 0;
3684
3685 if (h->ae_algo->ops->mac_connect_phy)
3686 ret = h->ae_algo->ops->mac_connect_phy(h);
3687
3688 return ret;
3689}
3690
3691static void hns3_uninit_phy(struct net_device *netdev)
3692{
3693 struct hnae3_handle *h = hns3_get_handle(netdev);
3694
3695 if (h->ae_algo->ops->mac_disconnect_phy)
3696 h->ae_algo->ops->mac_disconnect_phy(h);
3697}
3698
6871af29
JS		 3699static int hns3_restore_fd_rules(struct net_device *netdev)
3700{
3701 struct hnae3_handle *h = hns3_get_handle(netdev);
3702 int ret = 0;
3703
3704 if (h->ae_algo->ops->restore_fd_rules)
3705 ret = h->ae_algo->ops->restore_fd_rules(h);
3706
3707 return ret;
3708}
3709
3710static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3711{
3712 struct hnae3_handle *h = hns3_get_handle(netdev);
3713
3714 if (h->ae_algo->ops->del_all_fd_entries)
3715 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3716}
3717
a6d818e3
YL		 3718static int hns3_client_start(struct hnae3_handle *handle)
3719{
3720 if (!handle->ae_algo->ops->client_start)
3721 return 0;
3722
3723 return handle->ae_algo->ops->client_start(handle);
3724}
3725
3726static void hns3_client_stop(struct hnae3_handle *handle)
3727{
3728 if (!handle->ae_algo->ops->client_stop)
3729 return;
3730
3731 handle->ae_algo->ops->client_stop(handle);
3732}
3733
bb87be87
YL		 3734static void hns3_info_show(struct hns3_nic_priv *priv)
3735{
3736 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3737
3738 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3739 dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps);
3740 dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size);
3741 dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size);
3742 dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len);
3743 dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc);
3744 dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc);
3745 dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc);
3746 dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu);
3747}
3748
76ad4f0e
S		 3749static int hns3_client_init(struct hnae3_handle *handle)
3750{
3751 struct pci_dev *pdev = handle->pdev;
0d43bf45 3752 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3753 struct hns3_nic_priv *priv;
3754 struct net_device *netdev;
3755 int ret;
3756
0d43bf45
HT		 3757 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3758 &max_rss_size);
3759 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3760 if (!netdev)
3761 return -ENOMEM;
3762
3763 priv = netdev_priv(netdev);
3764 priv->dev = &pdev->dev;
3765 priv->netdev = netdev;
3766 priv->ae_handle = handle;
f8fa222c 3767 priv->tx_timeout_count = 0;
b7b585c2 3768 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 3769
bb87be87
YL		 3770 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3771
76ad4f0e
S		 3772 handle->kinfo.netdev = netdev;
3773 handle->priv = (void *)priv;
3774
f09555ff 3775 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3776
3777 hns3_set_default_feature(netdev);
3778
3779 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3780 netdev->priv_flags |= IFF_UNICAST_FLT;
3781 netdev->netdev_ops = &hns3_nic_netdev_ops;
3782 SET_NETDEV_DEV(netdev, &pdev->dev);
3783 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 3784
3785 /* Carrier off reporting is important to ethtool even BEFORE open */
3786 netif_carrier_off(netdev);
3787
3788 ret = hns3_get_ring_config(priv);
3789 if (ret) {
3790 ret = -ENOMEM;
3791 goto out_get_ring_cfg;
3792 }
3793
dd38c726
YL		 3794 ret = hns3_nic_alloc_vector_data(priv);
3795 if (ret) {
3796 ret = -ENOMEM;
3797 goto out_alloc_vector_data;
3798 }
3799
76ad4f0e
S		 3800 ret = hns3_nic_init_vector_data(priv);
3801 if (ret) {
3802 ret = -ENOMEM;
3803 goto out_init_vector_data;
3804 }
3805
3806 ret = hns3_init_all_ring(priv);
3807 if (ret) {
3808 ret = -ENOMEM;
3809 goto out_init_ring_data;
3810 }
3811
c8a8045b
HT		 3812 ret = hns3_init_phy(netdev);
3813 if (ret)
3814 goto out_init_phy;
3815
76ad4f0e
S		 3816 ret = register_netdev(netdev);
3817 if (ret) {
3818 dev_err(priv->dev, "probe register netdev fail!\n");
3819 goto out_reg_netdev_fail;
3820 }
3821
a6d818e3
YL		 3822 ret = hns3_client_start(handle);
3823 if (ret) {
3824 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
18655128 3825 goto out_client_start;
a6d818e3
YL		 3826 }
3827
986743db
YL		 3828 hns3_dcbnl_setup(handle);
3829
b2292360 3830 hns3_dbg_init(handle);
3831
a0b43717 3832 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 3833 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 3834
814da63c
HT		 3835 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3836
bb87be87
YL		 3837 if (netif_msg_drv(handle))
3838 hns3_info_show(priv);
3839
76ad4f0e
S		 3840 return ret;
3841
18655128
HT		 3842out_client_start:
3843 unregister_netdev(netdev);
76ad4f0e 3844out_reg_netdev_fail:
c8a8045b
HT		 3845 hns3_uninit_phy(netdev);
3846out_init_phy:
3847 hns3_uninit_all_ring(priv);
76ad4f0e 3848out_init_ring_data:
e2152785 3849 hns3_nic_uninit_vector_data(priv);
76ad4f0e 3850out_init_vector_data:
dd38c726
YL		 3851 hns3_nic_dealloc_vector_data(priv);
3852out_alloc_vector_data:
3853 priv->ring_data = NULL;
76ad4f0e
S		 3854out_get_ring_cfg:
3855 priv->ae_handle = NULL;
3856 free_netdev(netdev);
3857 return ret;
3858}
3859
3860static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3861{
3862 struct net_device *netdev = handle->kinfo.netdev;
3863 struct hns3_nic_priv *priv = netdev_priv(netdev);
3864 int ret;
3865
f05e2109
JS		 3866 hns3_remove_hw_addr(netdev);
3867
76ad4f0e
S		 3868 if (netdev->reg_state != NETREG_UNINITIALIZED)
3869 unregister_netdev(netdev);
3870
eb32c896
HT		 3871 hns3_client_stop(handle);
3872
814da63c
HT		 3873 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3874 netdev_warn(netdev, "already uninitialized\n");
3875 goto out_netdev_free;
3876 }
3877
dc5e6064
JS		 3878 hns3_del_all_fd_rules(netdev, true);
3879
7b763f3f
FL		 3880 hns3_force_clear_all_rx_ring(handle);
3881
c8a8045b
HT		 3882 hns3_uninit_phy(netdev);
3883
e2152785 3884 hns3_nic_uninit_vector_data(priv);
76ad4f0e 3885
dd38c726
YL		 3886 ret = hns3_nic_dealloc_vector_data(priv);
3887 if (ret)
3888 netdev_err(netdev, "dealloc vector error\n");
3889
76ad4f0e
S		 3890 ret = hns3_uninit_all_ring(priv);
3891 if (ret)
3892 netdev_err(netdev, "uninit ring error\n");
3893
ec777890
YL		 3894 hns3_put_ring_config(priv);
3895
b2292360 3896 hns3_dbg_uninit(handle);
3897
814da63c 3898out_netdev_free:
76ad4f0e
S		 3899 free_netdev(netdev);
3900}
3901
3902static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3903{
3904 struct net_device *netdev = handle->kinfo.netdev;
3905
3906 if (!netdev)
3907 return;
3908
3909 if (linkup) {
3910 netif_carrier_on(netdev);
3911 netif_tx_wake_all_queues(netdev);
bb87be87
YL		 3912 if (netif_msg_link(handle))
3913 netdev_info(netdev, "link up\n");
76ad4f0e
S		 3914 } else {
3915 netif_carrier_off(netdev);
3916 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 3917 if (netif_msg_link(handle))
3918 netdev_info(netdev, "link down\n");
76ad4f0e
S		 3919 }
3920}
3921
9df8f79a
YL		 3922static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3923{
3924 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3925 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL		 3926
3927 if (tc > HNAE3_MAX_TC)
3928 return -EINVAL;
3929
3930 if (!ndev)
3931 return -ENODEV;
3932
a1ef124e 3933 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL		 3934}
3935
7fa6be4f 3936static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L		 3937{
3938 struct netdev_hw_addr_list *list;
3939 struct netdev_hw_addr *ha, *tmp;
7fa6be4f 3940 int ret = 0;
bb6b94a8 3941
389775a6 3942 netif_addr_lock_bh(ndev);
bb6b94a8
L		 3943 /* go through and sync uc_addr entries to the device */
3944 list = &ndev->uc;
7fa6be4f
HT		 3945 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3946 ret = hns3_nic_uc_sync(ndev, ha->addr);
3947 if (ret)
389775a6 3948 goto out;
7fa6be4f 3949 }
bb6b94a8
L		 3950
3951 /* go through and sync mc_addr entries to the device */
3952 list = &ndev->mc;
7fa6be4f
HT		 3953 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3954 ret = hns3_nic_mc_sync(ndev, ha->addr);
3955 if (ret)
389775a6 3956 goto out;
7fa6be4f
HT		 3957 }
3958
389775a6
JS		 3959out:
3960 netif_addr_unlock_bh(ndev);
7fa6be4f 3961 return ret;
bb6b94a8
L		 3962}
3963
f05e2109
JS		 3964static void hns3_remove_hw_addr(struct net_device *netdev)
3965{
3966 struct netdev_hw_addr_list *list;
3967 struct netdev_hw_addr *ha, *tmp;
3968
3969 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3970
389775a6 3971 netif_addr_lock_bh(netdev);
f05e2109
JS		 3972 /* go through and unsync uc_addr entries to the device */
3973 list = &netdev->uc;
3974 list_for_each_entry_safe(ha, tmp, &list->list, list)
3975 hns3_nic_uc_unsync(netdev, ha->addr);
3976
3977 /* go through and unsync mc_addr entries to the device */
3978 list = &netdev->mc;
3979 list_for_each_entry_safe(ha, tmp, &list->list, list)
3980 if (ha->refcount > 1)
3981 hns3_nic_mc_unsync(netdev, ha->addr);
389775a6
JS		 3982
3983 netif_addr_unlock_bh(netdev);
f05e2109
JS		 3984}
3985
beebca3a 3986static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 3987{
beebca3a 3988 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 3989 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL		 3990 hns3_free_buffer_detach(ring, ring->next_to_clean);
3991 ring_ptr_move_fw(ring, next_to_clean);
3992 }
3993}
3994
7b763f3f
FL		 3995static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3996{
3997 struct hns3_desc_cb res_cbs;
3998 int ret;
3999
4000 while (ring->next_to_use != ring->next_to_clean) {
4001 /* When a buffer is not reused, it's memory has been
4002 * freed in hns3_handle_rx_bd or will be freed by
4003 * stack, so we need to replace the buffer here.
4004 */
4005 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4006 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4007 if (ret) {
4008 u64_stats_update_begin(&ring->syncp);
4009 ring->stats.sw_err_cnt++;
4010 u64_stats_update_end(&ring->syncp);
4011 /* if alloc new buffer fail, exit directly
4012 * and reclear in up flow.
4013 */
4014 netdev_warn(ring->tqp->handle->kinfo.netdev,
4015 "reserve buffer map failed, ret = %d\n",
4016 ret);
4017 return ret;
4018 }
4019 hns3_replace_buffer(ring, ring->next_to_use,
4020 &res_cbs);
4021 }
4022 ring_ptr_move_fw(ring, next_to_use);
4023 }
4024
cc5ff6e9
PL		 4025 /* Free the pending skb in rx ring */
4026 if (ring->skb) {
4027 dev_kfree_skb_any(ring->skb);
4028 ring->skb = NULL;
4029 ring->pending_buf = 0;
4030 }
4031
7b763f3f
FL		 4032 return 0;
4033}
4034
4035static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4036{
beebca3a
YL		 4037 while (ring->next_to_use != ring->next_to_clean) {
4038 /* When a buffer is not reused, it's memory has been
4039 * freed in hns3_handle_rx_bd or will be freed by
4040 * stack, so only need to unmap the buffer here.
4041 */
4042 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4043 hns3_unmap_buffer(ring,
4044 &ring->desc_cb[ring->next_to_use]);
4045 ring->desc_cb[ring->next_to_use].dma = 0;
4046 }
4047
4048 ring_ptr_move_fw(ring, next_to_use);
4049 }
bb6b94a8
L		 4050}
4051
7b763f3f
FL		 4052static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
4053{
4054 struct net_device *ndev = h->kinfo.netdev;
4055 struct hns3_nic_priv *priv = netdev_priv(ndev);
4056 struct hns3_enet_ring *ring;
4057 u32 i;
4058
4059 for (i = 0; i < h->kinfo.num_tqps; i++) {
4060 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
4061 hns3_force_clear_rx_ring(ring);
4062 }
4063}
4064
bb6b94a8
L		 4065static void hns3_clear_all_ring(struct hnae3_handle *h)
4066{
4067 struct net_device *ndev = h->kinfo.netdev;
4068 struct hns3_nic_priv *priv = netdev_priv(ndev);
4069 u32 i;
4070
4071 for (i = 0; i < h->kinfo.num_tqps; i++) {
4072 struct netdev_queue *dev_queue;
4073 struct hns3_enet_ring *ring;
4074
4075 ring = priv->ring_data[i].ring;
beebca3a 4076 hns3_clear_tx_ring(ring);
bb6b94a8
L		 4077 dev_queue = netdev_get_tx_queue(ndev,
4078 priv->ring_data[i].queue_index);
4079 netdev_tx_reset_queue(dev_queue);
4080
4081 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
7b763f3f
FL		 4082 /* Continue to clear other rings even if clearing some
4083 * rings failed.
4084 */
beebca3a 4085 hns3_clear_rx_ring(ring);
bb6b94a8
L		 4086 }
4087}
4088
7b763f3f
FL		 4089int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4090{
4091 struct net_device *ndev = h->kinfo.netdev;
4092 struct hns3_nic_priv *priv = netdev_priv(ndev);
4093 struct hns3_enet_ring *rx_ring;
4094 int i, j;
4095 int ret;
4096
4097 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 4098 ret = h->ae_algo->ops->reset_queue(h, i);
4099 if (ret)
4100 return ret;
4101
7b763f3f
FL		 4102 hns3_init_ring_hw(priv->ring_data[i].ring);
4103
4104 /* We need to clear tx ring here because self test will
4105 * use the ring and will not run down before up
4106 */
4107 hns3_clear_tx_ring(priv->ring_data[i].ring);
4108 priv->ring_data[i].ring->next_to_clean = 0;
4109 priv->ring_data[i].ring->next_to_use = 0;
4110
4111 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
4112 hns3_init_ring_hw(rx_ring);
4113 ret = hns3_clear_rx_ring(rx_ring);
4114 if (ret)
4115 return ret;
4116
4117 /* We can not know the hardware head and tail when this
4118 * function is called in reset flow, so we reuse all desc.
4119 */
4120 for (j = 0; j < rx_ring->desc_num; j++)
4121 hns3_reuse_buffer(rx_ring, j);
4122
4123 rx_ring->next_to_clean = 0;
4124 rx_ring->next_to_use = 0;
4125 }
4126
1c772154
YL		 4127 hns3_init_tx_ring_tc(priv);
4128
7b763f3f
FL		 4129 return 0;
4130}
4131
e4fd7502
HT		 4132static void hns3_store_coal(struct hns3_nic_priv *priv)
4133{
4134 /* ethtool only support setting and querying one coal
4135 * configuation for now, so save the vector 0' coal
4136 * configuation here in order to restore it.
4137 */
4138 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4139 sizeof(struct hns3_enet_coalesce));
4140 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4141 sizeof(struct hns3_enet_coalesce));
4142}
4143
4144static void hns3_restore_coal(struct hns3_nic_priv *priv)
4145{
4146 u16 vector_num = priv->vector_num;
4147 int i;
4148
4149 for (i = 0; i < vector_num; i++) {
4150 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4151 sizeof(struct hns3_enet_coalesce));
4152 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4153 sizeof(struct hns3_enet_coalesce));
4154 }
4155}
4156
bb6b94a8
L		 4157static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4158{
7edff533 4159 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L		 4160 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4161 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 4162 struct hns3_nic_priv *priv = netdev_priv(ndev);
4163
4164 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4165 return 0;
bb6b94a8 4166
7edff533
HT		 4167 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4168 * from table space. Hence, for function reset software intervention is
4169 * required to delete the entries
4170 */
4171 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4172 hns3_remove_hw_addr(ndev);
4173 hns3_del_all_fd_rules(ndev, false);
4174 }
4175
bb6b94a8 4176 if (!netif_running(ndev))
6b1385cc 4177 return 0;
bb6b94a8
L		 4178
4179 return hns3_nic_net_stop(ndev);
4180}
4181
4182static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4183{
4184 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4185 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4186 int ret = 0;
4187
e8884027
HT		 4188 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4189
bb6b94a8 4190 if (netif_running(kinfo->netdev)) {
e8884027 4191 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4192 if (ret) {
e8884027 4193 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8
L		 4194 netdev_err(kinfo->netdev,
4195 "hns net up fail, ret=%d!\n", ret);
4196 return ret;
4197 }
bb6b94a8
L		 4198 }
4199
4200 return ret;
4201}
4202
4203static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4204{
4205 struct net_device *netdev = handle->kinfo.netdev;
4206 struct hns3_nic_priv *priv = netdev_priv(netdev);
4207 int ret;
4208
bb6b94a8
L		 4209 /* Carrier off reporting is important to ethtool even BEFORE open */
4210 netif_carrier_off(netdev);
4211
2c9dd668 4212 ret = hns3_get_ring_config(priv);
862d969a
HT		 4213 if (ret)
4214 return ret;
4215
2c9dd668
HT		 4216 ret = hns3_nic_alloc_vector_data(priv);
4217 if (ret)
4218 goto err_put_ring;
4219
e4fd7502
HT		 4220 hns3_restore_coal(priv);
4221
bb6b94a8
L		 4222 ret = hns3_nic_init_vector_data(priv);
4223 if (ret)
862d969a 4224 goto err_dealloc_vector;
bb6b94a8
L		 4225
4226 ret = hns3_init_all_ring(priv);
862d969a
HT		 4227 if (ret)
4228 goto err_uninit_vector;
bb6b94a8 4229
cd513a69
HT		 4230 ret = hns3_client_start(handle);
4231 if (ret) {
4232 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4233 goto err_uninit_ring;
4234 }
4235
814da63c
HT		 4236 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4237
862d969a
HT		 4238 return ret;
4239
cd513a69
HT		 4240err_uninit_ring:
4241 hns3_uninit_all_ring(priv);
862d969a
HT		 4242err_uninit_vector:
4243 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 4244err_dealloc_vector:
4245 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 4246err_put_ring:
4247 hns3_put_ring_config(priv);
862d969a 4248
bb6b94a8
L		 4249 return ret;
4250}
4251
1f609492
YL		 4252static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4253{
4254 struct net_device *netdev = handle->kinfo.netdev;
4255 bool vlan_filter_enable;
4256 int ret;
4257
4258 ret = hns3_init_mac_addr(netdev, false);
4259 if (ret)
4260 return ret;
4261
4262 ret = hns3_recover_hw_addr(netdev);
4263 if (ret)
4264 return ret;
4265
4266 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4267 if (ret)
4268 return ret;
4269
4270 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4271 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4272
4273 /* Hardware table is only clear when pf resets */
4274 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4275 ret = hns3_restore_vlan(netdev);
4276 if (ret)
4277 return ret;
4278 }
4279
4280 return hns3_restore_fd_rules(netdev);
4281}
4282
bb6b94a8
L		 4283static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4284{
4285 struct net_device *netdev = handle->kinfo.netdev;
4286 struct hns3_nic_priv *priv = netdev_priv(netdev);
4287 int ret;
4288
1eeb3367 4289 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 4290 netdev_warn(netdev, "already uninitialized\n");
4291 return 0;
4292 }
4293
7b763f3f 4294 hns3_force_clear_all_rx_ring(handle);
bb6b94a8 4295
e2152785 4296 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4297
e4fd7502
HT		 4298 hns3_store_coal(priv);
4299
862d969a
HT		 4300 ret = hns3_nic_dealloc_vector_data(priv);
4301 if (ret)
4302 netdev_err(netdev, "dealloc vector error\n");
4303
bb6b94a8
L		 4304 ret = hns3_uninit_all_ring(priv);
4305 if (ret)
4306 netdev_err(netdev, "uninit ring error\n");
4307
2c9dd668 4308 hns3_put_ring_config(priv);
2c9dd668 4309
bb6b94a8
L		 4310 return ret;
4311}
4312
4313static int hns3_reset_notify(struct hnae3_handle *handle,
4314 enum hnae3_reset_notify_type type)
4315{
4316 int ret = 0;
4317
4318 switch (type) {
4319 case HNAE3_UP_CLIENT:
e1586241
SM		 4320 ret = hns3_reset_notify_up_enet(handle);
4321 break;
bb6b94a8
L		 4322 case HNAE3_DOWN_CLIENT:
4323 ret = hns3_reset_notify_down_enet(handle);
4324 break;
4325 case HNAE3_INIT_CLIENT:
4326 ret = hns3_reset_notify_init_enet(handle);
4327 break;
4328 case HNAE3_UNINIT_CLIENT:
4329 ret = hns3_reset_notify_uninit_enet(handle);
4330 break;
1f609492
YL		 4331 case HNAE3_RESTORE_CLIENT:
4332 ret = hns3_reset_notify_restore_enet(handle);
4333 break;
bb6b94a8
L		 4334 default:
4335 break;
4336 }
4337
4338 return ret;
4339}
4340
09f2af64
PL		 4341int hns3_set_channels(struct net_device *netdev,
4342 struct ethtool_channels *ch)
4343{
09f2af64
PL		 4344 struct hnae3_handle *h = hns3_get_handle(netdev);
4345 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4346 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 4347 u32 new_tqp_num = ch->combined_count;
4348 u16 org_tqp_num;
4349 int ret;
4350
4351 if (ch->rx_count || ch->tx_count)
4352 return -EINVAL;
4353
678335a1 4354 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4355 new_tqp_num < 1) {
09f2af64 4356 dev_err(&netdev->dev,
c78b5b6c 4357 "Change tqps fail, the tqp range is from 1 to %d",
678335a1 4358 hns3_get_max_available_channels(h));
09f2af64
PL		 4359 return -EINVAL;
4360 }
4361
c78b5b6c 4362 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 4363 return 0;
4364
65749f73
HT		 4365 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4366 if (ret)
4367 return ret;
dd38c726 4368
65749f73
HT		 4369 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4370 if (ret)
4371 return ret;
09f2af64
PL		 4372
4373 org_tqp_num = h->kinfo.num_tqps;
90c68a41 4374 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4375 if (ret) {
90c68a41
YL		 4376 ret = h->ae_algo->ops->set_channels(h, org_tqp_num,
4377 rxfh_configured);
09f2af64
PL		 4378 if (ret) {
4379 /* If revert to old tqp failed, fatal error occurred */
4380 dev_err(&netdev->dev,
4381 "Revert to old tqp num fail, ret=%d", ret);
4382 return ret;
4383 }
4384 dev_info(&netdev->dev,
4385 "Change tqp num fail, Revert to old tqp num");
4386 }
65749f73
HT		 4387 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT);
4388 if (ret)
4389 return ret;
09f2af64 4390
65749f73 4391 return hns3_reset_notify(h, HNAE3_UP_CLIENT);
09f2af64
PL		 4392}
4393
1db9b1bf 4394static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4395 .init_instance = hns3_client_init,
4396 .uninit_instance = hns3_client_uninit,
4397 .link_status_change = hns3_link_status_change,
9df8f79a 4398 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4399 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 4400};
4401
4402/* hns3_init_module - Driver registration routine
4403 * hns3_init_module is the first routine called when the driver is
4404 * loaded. All it does is register with the PCI subsystem.
4405 */
4406static int __init hns3_init_module(void)
4407{
4408 int ret;
4409
4410 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4411 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4412
4413 client.type = HNAE3_CLIENT_KNIC;
4414 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4415 hns3_driver_name);
4416
4417 client.ops = &client_ops;
4418
13562d1f
XW		 4419 INIT_LIST_HEAD(&client.node);
4420
b2292360 4421 hns3_dbg_register_debugfs(hns3_driver_name);
4422
76ad4f0e
S		 4423 ret = hnae3_register_client(&client);
4424 if (ret)
b2292360 4425 goto err_reg_client;
76ad4f0e
S		 4426
4427 ret = pci_register_driver(&hns3_driver);
4428 if (ret)
b2292360 4429 goto err_reg_driver;
76ad4f0e
S		 4430
4431 return ret;
b2292360 4432
4433err_reg_driver:
4434 hnae3_unregister_client(&client);
4435err_reg_client:
4436 hns3_dbg_unregister_debugfs();
4437 return ret;
76ad4f0e
S		 4438}
4439module_init(hns3_init_module);
4440
4441/* hns3_exit_module - Driver exit cleanup routine
4442 * hns3_exit_module is called just before the driver is removed
4443 * from memory.
4444 */
4445static void __exit hns3_exit_module(void)
4446{
4447 pci_unregister_driver(&hns3_driver);
4448 hnae3_unregister_client(&client);
b2292360 4449 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4450}
4451module_exit(hns3_exit_module);
4452
4453MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4454MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4455MODULE_LICENSE("GPL");
4456MODULE_ALIAS("pci:hns-nic");
3c7624d8 4457MODULE_VERSION(HNS3_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)