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9f35a734 TT |
1 | /* |
2 | * QorIQ 10G MDIO Controller | |
3 | * | |
4 | * Copyright 2012 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Authors: Andy Fleming <afleming@freescale.com> | |
7 | * Timur Tabi <timur@freescale.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public License | |
10 | * version 2. This program is licensed "as is" without any warranty of any | |
11 | * kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/phy.h> | |
19 | #include <linux/mdio.h> | |
5af50730 | 20 | #include <linux/of_address.h> |
9f35a734 TT |
21 | #include <linux/of_platform.h> |
22 | #include <linux/of_mdio.h> | |
23 | ||
24 | /* Number of microseconds to wait for a register to respond */ | |
25 | #define TIMEOUT 1000 | |
26 | ||
27 | struct tgec_mdio_controller { | |
28 | __be32 reserved[12]; | |
29 | __be32 mdio_stat; /* MDIO configuration and status */ | |
30 | __be32 mdio_ctl; /* MDIO control */ | |
31 | __be32 mdio_data; /* MDIO data */ | |
32 | __be32 mdio_addr; /* MDIO address */ | |
33 | } __packed; | |
34 | ||
1fcf77c8 | 35 | #define MDIO_STAT_ENC BIT(6) |
9f35a734 | 36 | #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) |
49ff2d3f SX |
37 | #define MDIO_STAT_BSY BIT(0) |
38 | #define MDIO_STAT_RD_ER BIT(1) | |
9f35a734 TT |
39 | #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) |
40 | #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) | |
49ff2d3f SX |
41 | #define MDIO_CTL_PRE_DIS BIT(10) |
42 | #define MDIO_CTL_SCAN_EN BIT(11) | |
43 | #define MDIO_CTL_POST_INC BIT(14) | |
44 | #define MDIO_CTL_READ BIT(15) | |
9f35a734 TT |
45 | |
46 | #define MDIO_DATA(x) (x & 0xffff) | |
49ff2d3f | 47 | #define MDIO_DATA_BSY BIT(31) |
9f35a734 TT |
48 | |
49 | /* | |
c1543d37 | 50 | * Wait until the MDIO bus is free |
9f35a734 TT |
51 | */ |
52 | static int xgmac_wait_until_free(struct device *dev, | |
53 | struct tgec_mdio_controller __iomem *regs) | |
54 | { | |
22f6bba7 | 55 | unsigned int timeout; |
9f35a734 TT |
56 | |
57 | /* Wait till the bus is free */ | |
22f6bba7 SX |
58 | timeout = TIMEOUT; |
59 | while ((ioread32be(®s->mdio_stat) & MDIO_STAT_BSY) && timeout) { | |
60 | cpu_relax(); | |
61 | timeout--; | |
62 | } | |
63 | ||
64 | if (!timeout) { | |
9f35a734 TT |
65 | dev_err(dev, "timeout waiting for bus to be free\n"); |
66 | return -ETIMEDOUT; | |
67 | } | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
72 | /* | |
73 | * Wait till the MDIO read or write operation is complete | |
74 | */ | |
75 | static int xgmac_wait_until_done(struct device *dev, | |
76 | struct tgec_mdio_controller __iomem *regs) | |
77 | { | |
22f6bba7 | 78 | unsigned int timeout; |
9f35a734 TT |
79 | |
80 | /* Wait till the MDIO write is complete */ | |
22f6bba7 SX |
81 | timeout = TIMEOUT; |
82 | while ((ioread32be(®s->mdio_data) & MDIO_DATA_BSY) && timeout) { | |
83 | cpu_relax(); | |
84 | timeout--; | |
85 | } | |
86 | ||
87 | if (!timeout) { | |
9f35a734 TT |
88 | dev_err(dev, "timeout waiting for operation to complete\n"); |
89 | return -ETIMEDOUT; | |
90 | } | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
95 | /* | |
96 | * Write value to the PHY for this device to the register at regnum,waiting | |
97 | * until the write is done before it returns. All PHY configuration has to be | |
98 | * done through the TSEC1 MIIM regs. | |
99 | */ | |
100 | static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value) | |
101 | { | |
102 | struct tgec_mdio_controller __iomem *regs = bus->priv; | |
1fcf77c8 AF |
103 | uint16_t dev_addr; |
104 | u32 mdio_ctl, mdio_stat; | |
9f35a734 TT |
105 | int ret; |
106 | ||
ca43e58c | 107 | mdio_stat = ioread32be(®s->mdio_stat); |
1fcf77c8 AF |
108 | if (regnum & MII_ADDR_C45) { |
109 | /* Clause 45 (ie 10G) */ | |
110 | dev_addr = (regnum >> 16) & 0x1f; | |
111 | mdio_stat |= MDIO_STAT_ENC; | |
112 | } else { | |
113 | /* Clause 22 (ie 1G) */ | |
114 | dev_addr = regnum & 0x1f; | |
115 | mdio_stat &= ~MDIO_STAT_ENC; | |
116 | } | |
9f35a734 | 117 | |
ca43e58c | 118 | iowrite32be(mdio_stat, ®s->mdio_stat); |
9f35a734 TT |
119 | |
120 | ret = xgmac_wait_until_free(&bus->dev, regs); | |
121 | if (ret) | |
122 | return ret; | |
123 | ||
1fcf77c8 AF |
124 | /* Set the port and dev addr */ |
125 | mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); | |
ca43e58c | 126 | iowrite32be(mdio_ctl, ®s->mdio_ctl); |
1fcf77c8 AF |
127 | |
128 | /* Set the register address */ | |
129 | if (regnum & MII_ADDR_C45) { | |
ca43e58c | 130 | iowrite32be(regnum & 0xffff, ®s->mdio_addr); |
1fcf77c8 AF |
131 | |
132 | ret = xgmac_wait_until_free(&bus->dev, regs); | |
133 | if (ret) | |
134 | return ret; | |
135 | } | |
136 | ||
9f35a734 | 137 | /* Write the value to the register */ |
ca43e58c | 138 | iowrite32be(MDIO_DATA(value), ®s->mdio_data); |
9f35a734 TT |
139 | |
140 | ret = xgmac_wait_until_done(&bus->dev, regs); | |
141 | if (ret) | |
142 | return ret; | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | /* | |
148 | * Reads from register regnum in the PHY for device dev, returning the value. | |
149 | * Clears miimcom first. All PHY configuration has to be done through the | |
150 | * TSEC1 MIIM regs. | |
151 | */ | |
152 | static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum) | |
153 | { | |
154 | struct tgec_mdio_controller __iomem *regs = bus->priv; | |
1fcf77c8 AF |
155 | uint16_t dev_addr; |
156 | uint32_t mdio_stat; | |
9f35a734 TT |
157 | uint32_t mdio_ctl; |
158 | uint16_t value; | |
159 | int ret; | |
160 | ||
ca43e58c | 161 | mdio_stat = ioread32be(®s->mdio_stat); |
1fcf77c8 AF |
162 | if (regnum & MII_ADDR_C45) { |
163 | dev_addr = (regnum >> 16) & 0x1f; | |
164 | mdio_stat |= MDIO_STAT_ENC; | |
165 | } else { | |
166 | dev_addr = regnum & 0x1f; | |
e54bfe9d | 167 | mdio_stat &= ~MDIO_STAT_ENC; |
1fcf77c8 AF |
168 | } |
169 | ||
ca43e58c | 170 | iowrite32be(mdio_stat, ®s->mdio_stat); |
1fcf77c8 AF |
171 | |
172 | ret = xgmac_wait_until_free(&bus->dev, regs); | |
173 | if (ret) | |
174 | return ret; | |
175 | ||
9f35a734 TT |
176 | /* Set the Port and Device Addrs */ |
177 | mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); | |
ca43e58c | 178 | iowrite32be(mdio_ctl, ®s->mdio_ctl); |
9f35a734 TT |
179 | |
180 | /* Set the register address */ | |
1fcf77c8 | 181 | if (regnum & MII_ADDR_C45) { |
ca43e58c | 182 | iowrite32be(regnum & 0xffff, ®s->mdio_addr); |
9f35a734 | 183 | |
1fcf77c8 AF |
184 | ret = xgmac_wait_until_free(&bus->dev, regs); |
185 | if (ret) | |
186 | return ret; | |
187 | } | |
9f35a734 TT |
188 | |
189 | /* Initiate the read */ | |
ca43e58c | 190 | iowrite32be(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl); |
9f35a734 TT |
191 | |
192 | ret = xgmac_wait_until_done(&bus->dev, regs); | |
193 | if (ret) | |
194 | return ret; | |
195 | ||
196 | /* Return all Fs if nothing was there */ | |
ca43e58c | 197 | if (ioread32be(®s->mdio_stat) & MDIO_STAT_RD_ER) { |
55fd3641 | 198 | dev_err(&bus->dev, |
9e6492ec | 199 | "Error while reading PHY%d reg at %d.%hhu\n", |
55fd3641 | 200 | phy_id, dev_addr, regnum); |
9f35a734 TT |
201 | return 0xffff; |
202 | } | |
203 | ||
ca43e58c | 204 | value = ioread32be(®s->mdio_data) & 0xffff; |
9f35a734 TT |
205 | dev_dbg(&bus->dev, "read %04x\n", value); |
206 | ||
207 | return value; | |
208 | } | |
209 | ||
33897cc8 | 210 | static int xgmac_mdio_probe(struct platform_device *pdev) |
9f35a734 TT |
211 | { |
212 | struct device_node *np = pdev->dev.of_node; | |
213 | struct mii_bus *bus; | |
214 | struct resource res; | |
215 | int ret; | |
216 | ||
217 | ret = of_address_to_resource(np, 0, &res); | |
218 | if (ret) { | |
219 | dev_err(&pdev->dev, "could not obtain address\n"); | |
220 | return ret; | |
221 | } | |
222 | ||
aa842478 | 223 | bus = mdiobus_alloc(); |
9f35a734 TT |
224 | if (!bus) |
225 | return -ENOMEM; | |
226 | ||
227 | bus->name = "Freescale XGMAC MDIO Bus"; | |
228 | bus->read = xgmac_mdio_read; | |
229 | bus->write = xgmac_mdio_write; | |
9f35a734 TT |
230 | bus->parent = &pdev->dev; |
231 | snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start); | |
232 | ||
233 | /* Set the PHY base address */ | |
234 | bus->priv = of_iomap(np, 0); | |
235 | if (!bus->priv) { | |
236 | ret = -ENOMEM; | |
237 | goto err_ioremap; | |
238 | } | |
239 | ||
240 | ret = of_mdiobus_register(bus, np); | |
241 | if (ret) { | |
242 | dev_err(&pdev->dev, "cannot register MDIO bus\n"); | |
243 | goto err_registration; | |
244 | } | |
245 | ||
8513fbd8 | 246 | platform_set_drvdata(pdev, bus); |
9f35a734 TT |
247 | |
248 | return 0; | |
249 | ||
250 | err_registration: | |
251 | iounmap(bus->priv); | |
252 | ||
253 | err_ioremap: | |
254 | mdiobus_free(bus); | |
255 | ||
256 | return ret; | |
257 | } | |
258 | ||
33897cc8 | 259 | static int xgmac_mdio_remove(struct platform_device *pdev) |
9f35a734 | 260 | { |
8513fbd8 | 261 | struct mii_bus *bus = platform_get_drvdata(pdev); |
9f35a734 TT |
262 | |
263 | mdiobus_unregister(bus); | |
264 | iounmap(bus->priv); | |
265 | mdiobus_free(bus); | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | static struct of_device_id xgmac_mdio_match[] = { | |
271 | { | |
272 | .compatible = "fsl,fman-xmdio", | |
273 | }, | |
1fcf77c8 AF |
274 | { |
275 | .compatible = "fsl,fman-memac-mdio", | |
276 | }, | |
9f35a734 TT |
277 | {}, |
278 | }; | |
279 | MODULE_DEVICE_TABLE(of, xgmac_mdio_match); | |
280 | ||
281 | static struct platform_driver xgmac_mdio_driver = { | |
282 | .driver = { | |
283 | .name = "fsl-fman_xmdio", | |
284 | .of_match_table = xgmac_mdio_match, | |
285 | }, | |
286 | .probe = xgmac_mdio_probe, | |
287 | .remove = xgmac_mdio_remove, | |
288 | }; | |
289 | ||
290 | module_platform_driver(xgmac_mdio_driver); | |
291 | ||
292 | MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller"); | |
293 | MODULE_LICENSE("GPL v2"); |