projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Altera TSE: constify of_device_id array
[linux-2.6-block.git] / drivers / net / ethernet / freescale / ucc_geth.c
CommitLineData
ce973b14 1/*
047584ce 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
ce973b14
LY		 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 5 * Li Yang <leoli@freescale.com>
ce973b14
LY		 6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
ce973b14
LY		 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
c84d8055
JP		 15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
ce973b14
LY		 18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/slab.h>
22#include <linux/stddef.h>
9d9779e7 23#include <linux/module.h>
ce973b14
LY		 24#include <linux/interrupt.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
ce973b14 30#include <linux/dma-mapping.h>
ce973b14 31#include <linux/mii.h>
728de4c9 32#include <linux/phy.h>
df19b6b0 33#include <linux/workqueue.h>
5af50730
RH		 34#include <linux/of_address.h>
35#include <linux/of_irq.h>
0b9da337 36#include <linux/of_mdio.h>
4b6ba8aa 37#include <linux/of_net.h>
55b6c8e9 38#include <linux/of_platform.h>
ce973b14
LY		 39
40#include <asm/uaccess.h>
41#include <asm/irq.h>
42#include <asm/io.h>
43#include <asm/immap_qe.h>
44#include <asm/qe.h>
45#include <asm/ucc.h>
46#include <asm/ucc_fast.h>
81abb43a 47#include <asm/machdep.h>
ce973b14
LY		 48
49#include "ucc_geth.h"
ce973b14
LY		 50
51#undef DEBUG
52
ce973b14
LY		 53#define ugeth_printk(level, format, arg...) \
54 printk(level format "\n", ## arg)
55
56#define ugeth_dbg(format, arg...) \
57 ugeth_printk(KERN_DEBUG , format , ## arg)
ce973b14
LY		 58
59#ifdef UGETH_VERBOSE_DEBUG
60#define ugeth_vdbg ugeth_dbg
61#else
62#define ugeth_vdbg(fmt, args...) do { } while (0)
63#endif /* UGETH_VERBOSE_DEBUG */
890de95e 64#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
ce973b14 65
88a15f2e 66
ce973b14
LY		 67static DEFINE_SPINLOCK(ugeth_lock);
68
890de95e
LY		 69static struct {
70 u32 msg_enable;
71} debug = { -1 };
72
73module_param_named(debug, debug.msg_enable, int, 0);
74MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
75
18a8e864 76static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 77 .uf_info = {
78 .bd_mem_part = MEM_PART_SYSTEM,
79 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
80 .max_rx_buf_length = 1536,
728de4c9 81 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 82 .urfs = UCC_GETH_URFS_INIT,
83 .urfet = UCC_GETH_URFET_INIT,
84 .urfset = UCC_GETH_URFSET_INIT,
85 .utfs = UCC_GETH_UTFS_INIT,
86 .utfet = UCC_GETH_UTFET_INIT,
87 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 88 .ufpt = 256,
89 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
90 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
91 .tenc = UCC_FAST_TX_ENCODING_NRZ,
92 .renc = UCC_FAST_RX_ENCODING_NRZ,
93 .tcrc = UCC_FAST_16_BIT_CRC,
94 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
95 },
96 .numQueuesTx = 1,
97 .numQueuesRx = 1,
98 .extendedFilteringChainPointer = ((uint32_t) NULL),
99 .typeorlen = 3072 /*1536 */ ,
100 .nonBackToBackIfgPart1 = 0x40,
101 .nonBackToBackIfgPart2 = 0x60,
102 .miminumInterFrameGapEnforcement = 0x50,
103 .backToBackInterFrameGap = 0x60,
104 .mblinterval = 128,
105 .nortsrbytetime = 5,
106 .fracsiz = 1,
107 .strictpriorityq = 0xff,
108 .altBebTruncation = 0xa,
109 .excessDefer = 1,
110 .maxRetransmission = 0xf,
111 .collisionWindow = 0x37,
112 .receiveFlowControl = 1,
ac421852 113 .transmitFlowControl = 1,
ce973b14
LY		 114 .maxGroupAddrInHash = 4,
115 .maxIndAddrInHash = 4,
116 .prel = 7,
70f8002d 117 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
ce973b14 118 .minFrameLength = 64,
70f8002d
JT		 119 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
120 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
ce973b14
LY		 121 .vlantype = 0x8100,
122 .ecamptr = ((uint32_t) NULL),
123 .eventRegMask = UCCE_OTHER,
124 .pausePeriod = 0xf000,
125 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
126 .bdRingLenTx = {
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN,
134 TX_BD_RING_LEN},
135
136 .bdRingLenRx = {
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN,
144 RX_BD_RING_LEN},
145
146 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
147 .largestexternallookupkeysize =
148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
ac421852
LY		 149 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
ce973b14
LY		 152 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
153 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
154 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
155 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
156 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
ffea31ed
JT		 157 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
158 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
ce973b14
LY		 159 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161};
162
18a8e864 163static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 164
165#ifdef DEBUG
166static void mem_disp(u8 *addr, int size)
167{
168 u8 *i;
169 int size16Aling = (size >> 4) << 4;
170 int size4Aling = (size >> 2) << 2;
171 int notAlign = 0;
172 if (size % 16)
173 notAlign = 1;
174
175 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
176 printk("0x%08x: %08x %08x %08x %08x\r\n",
177 (u32) i,
178 *((u32 *) (i)),
179 *((u32 *) (i + 4)),
180 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
181 if (notAlign == 1)
182 printk("0x%08x: ", (u32) i);
183 for (; (u32) i < (u32) addr + size4Aling; i += 4)
184 printk("%08x ", *((u32 *) (i)));
185 for (; (u32) i < (u32) addr + size; i++)
64699336 186 printk("%02x", *((i)));
ce973b14
LY		 187 if (notAlign == 1)
188 printk("\r\n");
189}
190#endif /* DEBUG */
191
ce973b14
LY		 192static struct list_head *dequeue(struct list_head *lh)
193{
194 unsigned long flags;
195
1083cfe1 196 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 197 if (!list_empty(lh)) {
198 struct list_head *node = lh->next;
199 list_del(node);
1083cfe1 200 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 201 return node;
202 } else {
1083cfe1 203 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 204 return NULL;
205 }
206}
207
6fee40e9
AF		 208static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
209 u8 __iomem *bd)
ce973b14 210{
acb600de 211 struct sk_buff *skb;
ce973b14 212
acb600de
ED		 213 skb = netdev_alloc_skb(ugeth->ndev,
214 ugeth->ug_info->uf_info.max_rx_buf_length +
215 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
50f238fd 216 if (!skb)
ce973b14
LY		 217 return NULL;
218
219 /* We need the data buffer to be aligned properly. We will reserve
220 * as many bytes as needed to align the data properly
221 */
222 skb_reserve(skb,
223 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
225 1)));
226
6fee40e9 227 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 228 dma_map_single(ugeth->dev,
ce973b14
LY		 229 skb->data,
230 ugeth->ug_info->uf_info.max_rx_buf_length +
231 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
232 DMA_FROM_DEVICE));
233
6fee40e9
AF		 234 out_be32((u32 __iomem *)bd,
235 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
ce973b14
LY		 236
237 return skb;
238}
239
18a8e864 240static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14 241{
6fee40e9 242 u8 __iomem *bd;
ce973b14
LY		 243 u32 bd_status;
244 struct sk_buff *skb;
245 int i;
246
247 bd = ugeth->p_rx_bd_ring[rxQ];
248 i = 0;
249
250 do {
6fee40e9 251 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 252 skb = get_new_skb(ugeth, bd);
253
254 if (!skb) /* If can not allocate data buffer,
255 abort. Cleanup will be elsewhere */
256 return -ENOMEM;
257
258 ugeth->rx_skbuff[rxQ][i] = skb;
259
260 /* advance the BD pointer */
18a8e864 261 bd += sizeof(struct qe_bd);
ce973b14
LY		 262 i++;
263 } while (!(bd_status & R_W));
264
265 return 0;
266}
267
18a8e864 268static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 269 u32 *p_start,
ce973b14
LY		 270 u8 num_entries,
271 u32 thread_size,
272 u32 thread_alignment,
345f8422 273 unsigned int risc,
ce973b14
LY		 274 int skip_page_for_first_entry)
275{
276 u32 init_enet_offset;
277 u8 i;
278 int snum;
279
280 for (i = 0; i < num_entries; i++) {
281 if ((snum = qe_get_snum()) < 0) {
890de95e 282 if (netif_msg_ifup(ugeth))
c84d8055 283 pr_err("Can not get SNUM\n");
ce973b14
LY		 284 return snum;
285 }
286 if ((i == 0) && skip_page_for_first_entry)
287 /* First entry of Rx does not have page */
288 init_enet_offset = 0;
289 else {
290 init_enet_offset =
291 qe_muram_alloc(thread_size, thread_alignment);
4c35630c 292 if (IS_ERR_VALUE(init_enet_offset)) {
890de95e 293 if (netif_msg_ifup(ugeth))
c84d8055 294 pr_err("Can not allocate DPRAM memory\n");
ce973b14
LY		 295 qe_put_snum((u8) snum);
296 return -ENOMEM;
297 }
298 }
299 *(p_start++) =
300 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
301 | risc;
302 }
303
304 return 0;
305}
306
18a8e864 307static int return_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 308 u32 *p_start,
ce973b14 309 u8 num_entries,
345f8422 310 unsigned int risc,
ce973b14
LY		 311 int skip_page_for_first_entry)
312{
313 u32 init_enet_offset;
314 u8 i;
315 int snum;
316
317 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 318 u32 val = *p_start;
319
ce973b14
LY		 320 /* Check that this entry was actually valid --
321 needed in case failed in allocations */
6fee40e9 322 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 323 snum =
6fee40e9 324 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 325 ENET_INIT_PARAM_SNUM_SHIFT;
326 qe_put_snum((u8) snum);
327 if (!((i == 0) && skip_page_for_first_entry)) {
328 /* First entry of Rx does not have page */
329 init_enet_offset =
6fee40e9 330 (val & ENET_INIT_PARAM_PTR_MASK);
ce973b14
LY		 331 qe_muram_free(init_enet_offset);
332 }
6fee40e9 333 *p_start++ = 0;
ce973b14
LY		 334 }
335 }
336
337 return 0;
338}
339
340#ifdef DEBUG
18a8e864 341static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 342 u32 __iomem *p_start,
ce973b14
LY		 343 u8 num_entries,
344 u32 thread_size,
345f8422 345 unsigned int risc,
ce973b14
LY		 346 int skip_page_for_first_entry)
347{
348 u32 init_enet_offset;
349 u8 i;
350 int snum;
351
352 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 353 u32 val = in_be32(p_start);
354
ce973b14
LY		 355 /* Check that this entry was actually valid --
356 needed in case failed in allocations */
6fee40e9 357 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 358 snum =
6fee40e9 359 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 360 ENET_INIT_PARAM_SNUM_SHIFT;
361 qe_put_snum((u8) snum);
362 if (!((i == 0) && skip_page_for_first_entry)) {
363 /* First entry of Rx does not have page */
364 init_enet_offset =
365 (in_be32(p_start) &
366 ENET_INIT_PARAM_PTR_MASK);
c84d8055
JP		 367 pr_info("Init enet entry %d:\n", i);
368 pr_info("Base address: 0x%08x\n",
369 (u32)qe_muram_addr(init_enet_offset));
ce973b14
LY		 370 mem_disp(qe_muram_addr(init_enet_offset),
371 thread_size);
372 }
373 p_start++;
374 }
375 }
376
377 return 0;
378}
379#endif
380
18a8e864 381static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 382{
383 kfree(enet_addr_cont);
384}
385
df19b6b0 386static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 387{
388 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
389 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
390 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
391}
392
18a8e864 393static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 394{
6fee40e9 395 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14 396
c84d8055
JP		 397 if (paddr_num >= NUM_OF_PADDRS) {
398 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num);
ce973b14
LY		 399 return -EINVAL;
400 }
401
402 p_82xx_addr_filt =
6fee40e9 403 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 404 addressfiltering;
405
406 /* Writing address ff.ff.ff.ff.ff.ff disables address
407 recognition for this register */
408 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
409 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
411
412 return 0;
413}
414
18a8e864
LY		 415static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
416 u8 *p_enet_addr)
ce973b14 417{
6fee40e9 418 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 419 u32 cecr_subblock;
420
421 p_82xx_addr_filt =
6fee40e9 422 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 423 addressfiltering;
424
425 cecr_subblock =
426 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
427
428 /* Ethernet frames are defined in Little Endian mode,
3ad2f3fb 429 therefore to insert */
ce973b14 430 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 431
432 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 433
434 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 435 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 436}
437
ce973b14 438#ifdef DEBUG
18a8e864
LY		 439static void get_statistics(struct ucc_geth_private *ugeth,
440 struct ucc_geth_tx_firmware_statistics *
ce973b14 441 tx_firmware_statistics,
18a8e864 442 struct ucc_geth_rx_firmware_statistics *
ce973b14 443 rx_firmware_statistics,
18a8e864 444 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 445{
6fee40e9
AF		 446 struct ucc_fast __iomem *uf_regs;
447 struct ucc_geth __iomem *ug_regs;
18a8e864
LY		 448 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
449 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 450
451 ug_regs = ugeth->ug_regs;
6fee40e9 452 uf_regs = (struct ucc_fast __iomem *) ug_regs;
ce973b14
LY		 453 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
454 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
455
456 /* Tx firmware only if user handed pointer and driver actually
457 gathers Tx firmware statistics */
458 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
459 tx_firmware_statistics->sicoltx =
460 in_be32(&p_tx_fw_statistics_pram->sicoltx);
461 tx_firmware_statistics->mulcoltx =
462 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
463 tx_firmware_statistics->latecoltxfr =
464 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
465 tx_firmware_statistics->frabortduecol =
466 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
467 tx_firmware_statistics->frlostinmactxer =
468 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
469 tx_firmware_statistics->carriersenseertx =
470 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
471 tx_firmware_statistics->frtxok =
472 in_be32(&p_tx_fw_statistics_pram->frtxok);
473 tx_firmware_statistics->txfrexcessivedefer =
474 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
475 tx_firmware_statistics->txpkts256 =
476 in_be32(&p_tx_fw_statistics_pram->txpkts256);
477 tx_firmware_statistics->txpkts512 =
478 in_be32(&p_tx_fw_statistics_pram->txpkts512);
479 tx_firmware_statistics->txpkts1024 =
480 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
481 tx_firmware_statistics->txpktsjumbo =
482 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
483 }
484
485 /* Rx firmware only if user handed pointer and driver actually
486 * gathers Rx firmware statistics */
487 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
488 int i;
489 rx_firmware_statistics->frrxfcser =
490 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
491 rx_firmware_statistics->fraligner =
492 in_be32(&p_rx_fw_statistics_pram->fraligner);
493 rx_firmware_statistics->inrangelenrxer =
494 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
495 rx_firmware_statistics->outrangelenrxer =
496 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
497 rx_firmware_statistics->frtoolong =
498 in_be32(&p_rx_fw_statistics_pram->frtoolong);
499 rx_firmware_statistics->runt =
500 in_be32(&p_rx_fw_statistics_pram->runt);
501 rx_firmware_statistics->verylongevent =
502 in_be32(&p_rx_fw_statistics_pram->verylongevent);
503 rx_firmware_statistics->symbolerror =
504 in_be32(&p_rx_fw_statistics_pram->symbolerror);
505 rx_firmware_statistics->dropbsy =
506 in_be32(&p_rx_fw_statistics_pram->dropbsy);
507 for (i = 0; i < 0x8; i++)
508 rx_firmware_statistics->res0[i] =
509 p_rx_fw_statistics_pram->res0[i];
510 rx_firmware_statistics->mismatchdrop =
511 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
512 rx_firmware_statistics->underpkts =
513 in_be32(&p_rx_fw_statistics_pram->underpkts);
514 rx_firmware_statistics->pkts256 =
515 in_be32(&p_rx_fw_statistics_pram->pkts256);
516 rx_firmware_statistics->pkts512 =
517 in_be32(&p_rx_fw_statistics_pram->pkts512);
518 rx_firmware_statistics->pkts1024 =
519 in_be32(&p_rx_fw_statistics_pram->pkts1024);
520 rx_firmware_statistics->pktsjumbo =
521 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
522 rx_firmware_statistics->frlossinmacer =
523 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
524 rx_firmware_statistics->pausefr =
525 in_be32(&p_rx_fw_statistics_pram->pausefr);
526 for (i = 0; i < 0x4; i++)
527 rx_firmware_statistics->res1[i] =
528 p_rx_fw_statistics_pram->res1[i];
529 rx_firmware_statistics->removevlan =
530 in_be32(&p_rx_fw_statistics_pram->removevlan);
531 rx_firmware_statistics->replacevlan =
532 in_be32(&p_rx_fw_statistics_pram->replacevlan);
533 rx_firmware_statistics->insertvlan =
534 in_be32(&p_rx_fw_statistics_pram->insertvlan);
535 }
536
537 /* Hardware only if user handed pointer and driver actually
538 gathers hardware statistics */
3bc53427
TT		 539 if (hardware_statistics &&
540 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
ce973b14
LY		 541 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
542 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
543 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
544 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
545 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
546 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
547 hardware_statistics->txok = in_be32(&ug_regs->txok);
548 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
549 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
550 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
551 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
552 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
553 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
554 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
555 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
556 }
557}
558
18a8e864 559static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 560{
561 int i;
562 int length;
563
564 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
565 if (ugeth->p_tx_bd_ring[i]) {
566 length =
567 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 568 sizeof(struct qe_bd));
c84d8055 569 pr_info("TX BDs[%d]\n", i);
ce973b14
LY		 570 mem_disp(ugeth->p_tx_bd_ring[i], length);
571 }
572 }
573 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
574 if (ugeth->p_rx_bd_ring[i]) {
575 length =
576 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 577 sizeof(struct qe_bd));
c84d8055 578 pr_info("RX BDs[%d]\n", i);
ce973b14
LY		 579 mem_disp(ugeth->p_rx_bd_ring[i], length);
580 }
581 }
582}
583
18a8e864 584static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 585{
586 int i;
587
c84d8055
JP		 588 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
589 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
590
591 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n",
592 (u32)&ugeth->ug_regs->maccfg1,
593 in_be32(&ugeth->ug_regs->maccfg1));
594 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n",
595 (u32)&ugeth->ug_regs->maccfg2,
596 in_be32(&ugeth->ug_regs->maccfg2));
597 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n",
598 (u32)&ugeth->ug_regs->ipgifg,
599 in_be32(&ugeth->ug_regs->ipgifg));
600 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n",
601 (u32)&ugeth->ug_regs->hafdup,
602 in_be32(&ugeth->ug_regs->hafdup));
603 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n",
604 (u32)&ugeth->ug_regs->ifctl,
605 in_be32(&ugeth->ug_regs->ifctl));
606 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n",
607 (u32)&ugeth->ug_regs->ifstat,
608 in_be32(&ugeth->ug_regs->ifstat));
609 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
610 (u32)&ugeth->ug_regs->macstnaddr1,
611 in_be32(&ugeth->ug_regs->macstnaddr1));
612 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
613 (u32)&ugeth->ug_regs->macstnaddr2,
614 in_be32(&ugeth->ug_regs->macstnaddr2));
615 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n",
616 (u32)&ugeth->ug_regs->uempr,
617 in_be32(&ugeth->ug_regs->uempr));
618 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n",
619 (u32)&ugeth->ug_regs->utbipar,
620 in_be32(&ugeth->ug_regs->utbipar));
621 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n",
622 (u32)&ugeth->ug_regs->uescr,
623 in_be16(&ugeth->ug_regs->uescr));
624 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n",
625 (u32)&ugeth->ug_regs->tx64,
626 in_be32(&ugeth->ug_regs->tx64));
627 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n",
628 (u32)&ugeth->ug_regs->tx127,
629 in_be32(&ugeth->ug_regs->tx127));
630 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n",
631 (u32)&ugeth->ug_regs->tx255,
632 in_be32(&ugeth->ug_regs->tx255));
633 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n",
634 (u32)&ugeth->ug_regs->rx64,
635 in_be32(&ugeth->ug_regs->rx64));
636 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n",
637 (u32)&ugeth->ug_regs->rx127,
638 in_be32(&ugeth->ug_regs->rx127));
639 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n",
640 (u32)&ugeth->ug_regs->rx255,
641 in_be32(&ugeth->ug_regs->rx255));
642 pr_info("txok : addr - 0x%08x, val - 0x%08x\n",
643 (u32)&ugeth->ug_regs->txok,
644 in_be32(&ugeth->ug_regs->txok));
645 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n",
646 (u32)&ugeth->ug_regs->txcf,
647 in_be16(&ugeth->ug_regs->txcf));
648 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n",
649 (u32)&ugeth->ug_regs->tmca,
650 in_be32(&ugeth->ug_regs->tmca));
651 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n",
652 (u32)&ugeth->ug_regs->tbca,
653 in_be32(&ugeth->ug_regs->tbca));
654 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n",
655 (u32)&ugeth->ug_regs->rxfok,
656 in_be32(&ugeth->ug_regs->rxfok));
657 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n",
658 (u32)&ugeth->ug_regs->rxbok,
659 in_be32(&ugeth->ug_regs->rxbok));
660 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n",
661 (u32)&ugeth->ug_regs->rbyt,
662 in_be32(&ugeth->ug_regs->rbyt));
663 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n",
664 (u32)&ugeth->ug_regs->rmca,
665 in_be32(&ugeth->ug_regs->rmca));
666 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n",
667 (u32)&ugeth->ug_regs->rbca,
668 in_be32(&ugeth->ug_regs->rbca));
669 pr_info("scar : addr - 0x%08x, val - 0x%08x\n",
670 (u32)&ugeth->ug_regs->scar,
671 in_be32(&ugeth->ug_regs->scar));
672 pr_info("scam : addr - 0x%08x, val - 0x%08x\n",
673 (u32)&ugeth->ug_regs->scam,
674 in_be32(&ugeth->ug_regs->scam));
ce973b14
LY		 675
676 if (ugeth->p_thread_data_tx) {
677 int numThreadsTxNumerical;
678 switch (ugeth->ug_info->numThreadsTx) {
679 case UCC_GETH_NUM_OF_THREADS_1:
680 numThreadsTxNumerical = 1;
681 break;
682 case UCC_GETH_NUM_OF_THREADS_2:
683 numThreadsTxNumerical = 2;
684 break;
685 case UCC_GETH_NUM_OF_THREADS_4:
686 numThreadsTxNumerical = 4;
687 break;
688 case UCC_GETH_NUM_OF_THREADS_6:
689 numThreadsTxNumerical = 6;
690 break;
691 case UCC_GETH_NUM_OF_THREADS_8:
692 numThreadsTxNumerical = 8;
693 break;
694 default:
695 numThreadsTxNumerical = 0;
696 break;
697 }
698
c84d8055
JP		 699 pr_info("Thread data TXs:\n");
700 pr_info("Base address: 0x%08x\n",
701 (u32)ugeth->p_thread_data_tx);
ce973b14 702 for (i = 0; i < numThreadsTxNumerical; i++) {
c84d8055
JP		 703 pr_info("Thread data TX[%d]:\n", i);
704 pr_info("Base address: 0x%08x\n",
705 (u32)&ugeth->p_thread_data_tx[i]);
ce973b14 706 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 707 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 708 }
709 }
710 if (ugeth->p_thread_data_rx) {
711 int numThreadsRxNumerical;
712 switch (ugeth->ug_info->numThreadsRx) {
713 case UCC_GETH_NUM_OF_THREADS_1:
714 numThreadsRxNumerical = 1;
715 break;
716 case UCC_GETH_NUM_OF_THREADS_2:
717 numThreadsRxNumerical = 2;
718 break;
719 case UCC_GETH_NUM_OF_THREADS_4:
720 numThreadsRxNumerical = 4;
721 break;
722 case UCC_GETH_NUM_OF_THREADS_6:
723 numThreadsRxNumerical = 6;
724 break;
725 case UCC_GETH_NUM_OF_THREADS_8:
726 numThreadsRxNumerical = 8;
727 break;
728 default:
729 numThreadsRxNumerical = 0;
730 break;
731 }
732
c84d8055
JP		 733 pr_info("Thread data RX:\n");
734 pr_info("Base address: 0x%08x\n",
735 (u32)ugeth->p_thread_data_rx);
ce973b14 736 for (i = 0; i < numThreadsRxNumerical; i++) {
c84d8055
JP		 737 pr_info("Thread data RX[%d]:\n", i);
738 pr_info("Base address: 0x%08x\n",
739 (u32)&ugeth->p_thread_data_rx[i]);
ce973b14 740 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 741 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 742 }
743 }
744 if (ugeth->p_exf_glbl_param) {
c84d8055
JP		 745 pr_info("EXF global param:\n");
746 pr_info("Base address: 0x%08x\n",
747 (u32)ugeth->p_exf_glbl_param);
ce973b14
LY		 748 mem_disp((u8 *) ugeth->p_exf_glbl_param,
749 sizeof(*ugeth->p_exf_glbl_param));
750 }
751 if (ugeth->p_tx_glbl_pram) {
c84d8055
JP		 752 pr_info("TX global param:\n");
753 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
754 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n",
755 (u32)&ugeth->p_tx_glbl_pram->temoder,
756 in_be16(&ugeth->p_tx_glbl_pram->temoder));
757 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n",
758 (u32)&ugeth->p_tx_glbl_pram->sqptr,
759 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
760 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
761 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
762 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
763 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
764 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
765 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
766 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n",
767 (u32)&ugeth->p_tx_glbl_pram->tstate,
768 in_be32(&ugeth->p_tx_glbl_pram->tstate));
769 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
770 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
771 ugeth->p_tx_glbl_pram->iphoffset[0]);
772 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
773 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
774 ugeth->p_tx_glbl_pram->iphoffset[1]);
775 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
776 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
777 ugeth->p_tx_glbl_pram->iphoffset[2]);
778 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
779 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
780 ugeth->p_tx_glbl_pram->iphoffset[3]);
781 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
782 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
783 ugeth->p_tx_glbl_pram->iphoffset[4]);
784 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
785 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
786 ugeth->p_tx_glbl_pram->iphoffset[5]);
787 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
788 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
789 ugeth->p_tx_glbl_pram->iphoffset[6]);
790 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
791 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
792 ugeth->p_tx_glbl_pram->iphoffset[7]);
793 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
794 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
795 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
796 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
797 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
798 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
799 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
800 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
801 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
802 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
803 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
804 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
805 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
806 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
807 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
808 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
809 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
810 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
811 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
812 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
813 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
814 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
815 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
816 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
817 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n",
818 (u32)&ugeth->p_tx_glbl_pram->tqptr,
819 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
ce973b14
LY		 820 }
821 if (ugeth->p_rx_glbl_pram) {
c84d8055
JP		 822 pr_info("RX global param:\n");
823 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
824 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n",
825 (u32)&ugeth->p_rx_glbl_pram->remoder,
826 in_be32(&ugeth->p_rx_glbl_pram->remoder));
827 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n",
828 (u32)&ugeth->p_rx_glbl_pram->rqptr,
829 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
830 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n",
831 (u32)&ugeth->p_rx_glbl_pram->typeorlen,
832 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
833 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n",
834 (u32)&ugeth->p_rx_glbl_pram->rxgstpack,
835 ugeth->p_rx_glbl_pram->rxgstpack);
836 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n",
837 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
838 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
839 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
840 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
841 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
842 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n",
843 (u32)&ugeth->p_rx_glbl_pram->rstate,
844 ugeth->p_rx_glbl_pram->rstate);
845 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n",
846 (u32)&ugeth->p_rx_glbl_pram->mrblr,
847 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
848 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n",
849 (u32)&ugeth->p_rx_glbl_pram->rbdqptr,
850 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
851 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n",
852 (u32)&ugeth->p_rx_glbl_pram->mflr,
853 in_be16(&ugeth->p_rx_glbl_pram->mflr));
854 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n",
855 (u32)&ugeth->p_rx_glbl_pram->minflr,
856 in_be16(&ugeth->p_rx_glbl_pram->minflr));
857 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n",
858 (u32)&ugeth->p_rx_glbl_pram->maxd1,
859 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
860 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n",
861 (u32)&ugeth->p_rx_glbl_pram->maxd2,
862 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
863 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n",
864 (u32)&ugeth->p_rx_glbl_pram->ecamptr,
865 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
866 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n",
867 (u32)&ugeth->p_rx_glbl_pram->l2qt,
868 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
869 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n",
870 (u32)&ugeth->p_rx_glbl_pram->l3qt[0],
871 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
872 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n",
873 (u32)&ugeth->p_rx_glbl_pram->l3qt[1],
874 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
875 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n",
876 (u32)&ugeth->p_rx_glbl_pram->l3qt[2],
877 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
878 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n",
879 (u32)&ugeth->p_rx_glbl_pram->l3qt[3],
880 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
881 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n",
882 (u32)&ugeth->p_rx_glbl_pram->l3qt[4],
883 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
884 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n",
885 (u32)&ugeth->p_rx_glbl_pram->l3qt[5],
886 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
887 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n",
888 (u32)&ugeth->p_rx_glbl_pram->l3qt[6],
889 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
890 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n",
891 (u32)&ugeth->p_rx_glbl_pram->l3qt[7],
892 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
893 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n",
894 (u32)&ugeth->p_rx_glbl_pram->vlantype,
895 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
896 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n",
897 (u32)&ugeth->p_rx_glbl_pram->vlantci,
898 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
ce973b14 899 for (i = 0; i < 64; i++)
c84d8055
JP		 900 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
901 i,
902 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
903 ugeth->p_rx_glbl_pram->addressfiltering[i]);
904 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n",
905 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
906 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
ce973b14
LY		 907 }
908 if (ugeth->p_send_q_mem_reg) {
c84d8055
JP		 909 pr_info("Send Q memory registers:\n");
910 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
ce973b14 911 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
c84d8055
JP		 912 pr_info("SQQD[%d]:\n", i);
913 pr_info("Base address: 0x%08x\n",
914 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
ce973b14 915 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 916 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 917 }
918 }
919 if (ugeth->p_scheduler) {
c84d8055
JP		 920 pr_info("Scheduler:\n");
921 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
ce973b14
LY		 922 mem_disp((u8 *) ugeth->p_scheduler,
923 sizeof(*ugeth->p_scheduler));
924 }
925 if (ugeth->p_tx_fw_statistics_pram) {
c84d8055
JP		 926 pr_info("TX FW statistics pram:\n");
927 pr_info("Base address: 0x%08x\n",
928 (u32)ugeth->p_tx_fw_statistics_pram);
ce973b14
LY		 929 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
930 sizeof(*ugeth->p_tx_fw_statistics_pram));
931 }
932 if (ugeth->p_rx_fw_statistics_pram) {
c84d8055
JP		 933 pr_info("RX FW statistics pram:\n");
934 pr_info("Base address: 0x%08x\n",
935 (u32)ugeth->p_rx_fw_statistics_pram);
ce973b14
LY		 936 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
937 sizeof(*ugeth->p_rx_fw_statistics_pram));
938 }
939 if (ugeth->p_rx_irq_coalescing_tbl) {
c84d8055
JP		 940 pr_info("RX IRQ coalescing tables:\n");
941 pr_info("Base address: 0x%08x\n",
942 (u32)ugeth->p_rx_irq_coalescing_tbl);
ce973b14 943 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
c84d8055
JP		 944 pr_info("RX IRQ coalescing table entry[%d]:\n", i);
945 pr_info("Base address: 0x%08x\n",
946 (u32)&ugeth->p_rx_irq_coalescing_tbl->
947 coalescingentry[i]);
948 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
949 (u32)&ugeth->p_rx_irq_coalescing_tbl->
950 coalescingentry[i].interruptcoalescingmaxvalue,
951 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
952 coalescingentry[i].
953 interruptcoalescingmaxvalue));
954 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
955 (u32)&ugeth->p_rx_irq_coalescing_tbl->
956 coalescingentry[i].interruptcoalescingcounter,
957 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
958 coalescingentry[i].
959 interruptcoalescingcounter));
ce973b14
LY		 960 }
961 }
962 if (ugeth->p_rx_bd_qs_tbl) {
c84d8055
JP		 963 pr_info("RX BD QS tables:\n");
964 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
ce973b14 965 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
c84d8055
JP		 966 pr_info("RX BD QS table[%d]:\n", i);
967 pr_info("Base address: 0x%08x\n",
968 (u32)&ugeth->p_rx_bd_qs_tbl[i]);
969 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n",
970 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
971 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
972 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n",
973 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
974 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
975 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
976 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
977 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
978 externalbdbaseptr));
979 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n",
980 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
981 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
982 pr_info("ucode RX Prefetched BDs:\n");
983 pr_info("Base address: 0x%08x\n",
984 (u32)qe_muram_addr(in_be32
985 (&ugeth->p_rx_bd_qs_tbl[i].
986 bdbaseptr)));
ce973b14
LY		 987 mem_disp((u8 *)
988 qe_muram_addr(in_be32
989 (&ugeth->p_rx_bd_qs_tbl[i].
990 bdbaseptr)),
18a8e864 991 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 992 }
993 }
994 if (ugeth->p_init_enet_param_shadow) {
995 int size;
c84d8055
JP		 996 pr_info("Init enet param shadow:\n");
997 pr_info("Base address: 0x%08x\n",
998 (u32) ugeth->p_init_enet_param_shadow);
ce973b14
LY		 999 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1000 sizeof(*ugeth->p_init_enet_param_shadow));
1001
18a8e864 1002 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1003 if (ugeth->ug_info->rxExtendedFiltering) {
1004 size +=
1005 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1006 if (ugeth->ug_info->largestexternallookupkeysize ==
1007 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1008 size +=
1009 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1010 if (ugeth->ug_info->largestexternallookupkeysize ==
1011 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1012 size +=
1013 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1014 }
1015
1016 dump_init_enet_entries(ugeth,
1017 &(ugeth->p_init_enet_param_shadow->
1018 txthread[0]),
1019 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1020 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1021 ugeth->ug_info->riscTx, 0);
1022 dump_init_enet_entries(ugeth,
1023 &(ugeth->p_init_enet_param_shadow->
1024 rxthread[0]),
1025 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1026 ugeth->ug_info->riscRx, 1);
1027 }
1028}
1029#endif /* DEBUG */
1030
6fee40e9
AF		 1031static void init_default_reg_vals(u32 __iomem *upsmr_register,
1032 u32 __iomem *maccfg1_register,
1033 u32 __iomem *maccfg2_register)
ce973b14
LY		 1034{
1035 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1036 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1037 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1038}
1039
1040static int init_half_duplex_params(int alt_beb,
1041 int back_pressure_no_backoff,
1042 int no_backoff,
1043 int excess_defer,
1044 u8 alt_beb_truncation,
1045 u8 max_retransmissions,
1046 u8 collision_window,
6fee40e9 1047 u32 __iomem *hafdup_register)
ce973b14
LY		 1048{
1049 u32 value = 0;
1050
1051 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1052 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1053 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1054 return -EINVAL;
1055
1056 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1057
1058 if (alt_beb)
1059 value |= HALFDUP_ALT_BEB;
1060 if (back_pressure_no_backoff)
1061 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1062 if (no_backoff)
1063 value |= HALFDUP_NO_BACKOFF;
1064 if (excess_defer)
1065 value |= HALFDUP_EXCESSIVE_DEFER;
1066
1067 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1068
1069 value |= collision_window;
1070
1071 out_be32(hafdup_register, value);
1072 return 0;
1073}
1074
1075static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1076 u8 non_btb_ipg,
1077 u8 min_ifg,
1078 u8 btb_ipg,
6fee40e9 1079 u32 __iomem *ipgifg_register)
ce973b14
LY		 1080{
1081 u32 value = 0;
1082
1083 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1084 IPG part 2 */
1085 if (non_btb_cs_ipg > non_btb_ipg)
1086 return -EINVAL;
1087
1088 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1089 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1090 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1091 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1092 return -EINVAL;
1093
1094 value |=
1095 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1096 IPGIFG_NBTB_CS_IPG_MASK);
1097 value |=
1098 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1099 IPGIFG_NBTB_IPG_MASK);
1100 value |=
1101 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1102 IPGIFG_MIN_IFG_MASK);
1103 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1104
1105 out_be32(ipgifg_register, value);
1106 return 0;
1107}
1108
ac421852 1109int init_flow_control_params(u32 automatic_flow_control_mode,
ce973b14
LY		 1110 int rx_flow_control_enable,
1111 int tx_flow_control_enable,
1112 u16 pause_period,
1113 u16 extension_field,
6fee40e9
AF		 1114 u32 __iomem *upsmr_register,
1115 u32 __iomem *uempr_register,
1116 u32 __iomem *maccfg1_register)
ce973b14
LY		 1117{
1118 u32 value = 0;
1119
1120 /* Set UEMPR register */
1121 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1122 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1123 out_be32(uempr_register, value);
1124
1125 /* Set UPSMR register */
3bc53427 1126 setbits32(upsmr_register, automatic_flow_control_mode);
ce973b14
LY		 1127
1128 value = in_be32(maccfg1_register);
1129 if (rx_flow_control_enable)
1130 value |= MACCFG1_FLOW_RX;
1131 if (tx_flow_control_enable)
1132 value |= MACCFG1_FLOW_TX;
1133 out_be32(maccfg1_register, value);
1134
1135 return 0;
1136}
1137
1138static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1139 int auto_zero_hardware_statistics,
6fee40e9
AF		 1140 u32 __iomem *upsmr_register,
1141 u16 __iomem *uescr_register)
ce973b14 1142{
ce973b14 1143 u16 uescr_value = 0;
3bc53427 1144
ce973b14 1145 /* Enable hardware statistics gathering if requested */
3bc53427
TT		 1146 if (enable_hardware_statistics)
1147 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
ce973b14
LY		 1148
1149 /* Clear hardware statistics counters */
1150 uescr_value = in_be16(uescr_register);
1151 uescr_value |= UESCR_CLRCNT;
1152 /* Automatically zero hardware statistics counters on read,
1153 if requested */
1154 if (auto_zero_hardware_statistics)
1155 uescr_value |= UESCR_AUTOZ;
1156 out_be16(uescr_register, uescr_value);
1157
1158 return 0;
1159}
1160
1161static int init_firmware_statistics_gathering_mode(int
1162 enable_tx_firmware_statistics,
1163 int enable_rx_firmware_statistics,
6fee40e9 1164 u32 __iomem *tx_rmon_base_ptr,
ce973b14 1165 u32 tx_firmware_statistics_structure_address,
6fee40e9 1166 u32 __iomem *rx_rmon_base_ptr,
ce973b14 1167 u32 rx_firmware_statistics_structure_address,
6fee40e9
AF		 1168 u16 __iomem *temoder_register,
1169 u32 __iomem *remoder_register)
ce973b14
LY		 1170{
1171 /* Note: this function does not check if */
1172 /* the parameters it receives are NULL */
ce973b14
LY		 1173
1174 if (enable_tx_firmware_statistics) {
1175 out_be32(tx_rmon_base_ptr,
1176 tx_firmware_statistics_structure_address);
3bc53427 1177 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1178 }
1179
1180 if (enable_rx_firmware_statistics) {
1181 out_be32(rx_rmon_base_ptr,
1182 rx_firmware_statistics_structure_address);
3bc53427 1183 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1184 }
1185
1186 return 0;
1187}
1188
1189static int init_mac_station_addr_regs(u8 address_byte_0,
1190 u8 address_byte_1,
1191 u8 address_byte_2,
1192 u8 address_byte_3,
1193 u8 address_byte_4,
1194 u8 address_byte_5,
6fee40e9
AF		 1195 u32 __iomem *macstnaddr1_register,
1196 u32 __iomem *macstnaddr2_register)
ce973b14
LY		 1197{
1198 u32 value = 0;
1199
1200 /* Example: for a station address of 0x12345678ABCD, */
1201 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1202
1203 /* MACSTNADDR1 Register: */
1204
1205 /* 0 7 8 15 */
1206 /* station address byte 5 station address byte 4 */
1207 /* 16 23 24 31 */
1208 /* station address byte 3 station address byte 2 */
1209 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1210 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1211 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1212 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1213
1214 out_be32(macstnaddr1_register, value);
1215
1216 /* MACSTNADDR2 Register: */
1217
1218 /* 0 7 8 15 */
1219 /* station address byte 1 station address byte 0 */
1220 /* 16 23 24 31 */
1221 /* reserved reserved */
1222 value = 0;
1223 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1224 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1225
1226 out_be32(macstnaddr2_register, value);
1227
1228 return 0;
1229}
1230
ce973b14 1231static int init_check_frame_length_mode(int length_check,
6fee40e9 1232 u32 __iomem *maccfg2_register)
ce973b14
LY		 1233{
1234 u32 value = 0;
1235
1236 value = in_be32(maccfg2_register);
1237
1238 if (length_check)
1239 value |= MACCFG2_LC;
1240 else
1241 value &= ~MACCFG2_LC;
1242
1243 out_be32(maccfg2_register, value);
1244 return 0;
1245}
1246
1247static int init_preamble_length(u8 preamble_length,
6fee40e9 1248 u32 __iomem *maccfg2_register)
ce973b14 1249{
ce973b14
LY		 1250 if ((preamble_length < 3) || (preamble_length > 7))
1251 return -EINVAL;
1252
3bc53427
TT		 1253 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1254 preamble_length << MACCFG2_PREL_SHIFT);
1255
ce973b14
LY		 1256 return 0;
1257}
1258
ce973b14
LY		 1259static int init_rx_parameters(int reject_broadcast,
1260 int receive_short_frames,
6fee40e9 1261 int promiscuous, u32 __iomem *upsmr_register)
ce973b14
LY		 1262{
1263 u32 value = 0;
1264
1265 value = in_be32(upsmr_register);
1266
1267 if (reject_broadcast)
3bc53427 1268 value |= UCC_GETH_UPSMR_BRO;
ce973b14 1269 else
3bc53427 1270 value &= ~UCC_GETH_UPSMR_BRO;
ce973b14
LY		 1271
1272 if (receive_short_frames)
3bc53427 1273 value |= UCC_GETH_UPSMR_RSH;
ce973b14 1274 else
3bc53427 1275 value &= ~UCC_GETH_UPSMR_RSH;
ce973b14
LY		 1276
1277 if (promiscuous)
3bc53427 1278 value |= UCC_GETH_UPSMR_PRO;
ce973b14 1279 else
3bc53427 1280 value &= ~UCC_GETH_UPSMR_PRO;
ce973b14
LY		 1281
1282 out_be32(upsmr_register, value);
1283
1284 return 0;
1285}
1286
1287static int init_max_rx_buff_len(u16 max_rx_buf_len,
6fee40e9 1288 u16 __iomem *mrblr_register)
ce973b14
LY		 1289{
1290 /* max_rx_buf_len value must be a multiple of 128 */
8e95a202
JP		 1291 if ((max_rx_buf_len == 0) ||
1292 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
ce973b14
LY		 1293 return -EINVAL;
1294
1295 out_be16(mrblr_register, max_rx_buf_len);
1296 return 0;
1297}
1298
1299static int init_min_frame_len(u16 min_frame_length,
6fee40e9
AF		 1300 u16 __iomem *minflr_register,
1301 u16 __iomem *mrblr_register)
ce973b14
LY		 1302{
1303 u16 mrblr_value = 0;
1304
1305 mrblr_value = in_be16(mrblr_register);
1306 if (min_frame_length >= (mrblr_value - 4))
1307 return -EINVAL;
1308
1309 out_be16(minflr_register, min_frame_length);
1310 return 0;
1311}
1312
18a8e864 1313static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1314{
18a8e864 1315 struct ucc_geth_info *ug_info;
6fee40e9
AF		 1316 struct ucc_geth __iomem *ug_regs;
1317 struct ucc_fast __iomem *uf_regs;
728de4c9 1318 int ret_val;
81abb43a 1319 u32 upsmr, maccfg2;
ce973b14
LY		 1320 u16 value;
1321
b39d66a8 1322 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1323
1324 ug_info = ugeth->ug_info;
1325 ug_regs = ugeth->ug_regs;
1326 uf_regs = ugeth->uccf->uf_regs;
1327
ce973b14
LY		 1328 /* Set MACCFG2 */
1329 maccfg2 = in_be32(&ug_regs->maccfg2);
1330 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1331 if ((ugeth->max_speed == SPEED_10) ||
1332 (ugeth->max_speed == SPEED_100))
ce973b14 1333 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1334 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1335 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1336 maccfg2 |= ug_info->padAndCrc;
1337 out_be32(&ug_regs->maccfg2, maccfg2);
1338
1339 /* Set UPSMR */
1340 upsmr = in_be32(&uf_regs->upsmr);
3bc53427
TT		 1341 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1342 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
728de4c9
KP		 1343 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1344 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1345 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1346 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1347 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9 1348 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
cef309cf
HS		 1349 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1350 upsmr |= UCC_GETH_UPSMR_RPM;
728de4c9
KP		 1351 switch (ugeth->max_speed) {
1352 case SPEED_10:
3bc53427 1353 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9
KP		 1354 /* FALLTHROUGH */
1355 case SPEED_100:
1356 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
3bc53427 1357 upsmr |= UCC_GETH_UPSMR_RMM;
728de4c9
KP		 1358 }
1359 }
1360 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1361 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
3bc53427 1362 upsmr |= UCC_GETH_UPSMR_TBIM;
728de4c9 1363 }
047584ce
HW		 1364 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1365 upsmr |= UCC_GETH_UPSMR_SGMM;
1366
ce973b14
LY		 1367 out_be32(&uf_regs->upsmr, upsmr);
1368
ce973b14
LY		 1369 /* Disable autonegotiation in tbi mode, because by default it
1370 comes up in autonegotiation mode. */
1371 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1372 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1373 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
81abb43a
LYB		 1374 struct ucc_geth_info *ug_info = ugeth->ug_info;
1375 struct phy_device *tbiphy;
1376
1377 if (!ug_info->tbi_node)
c84d8055 1378 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
81abb43a
LYB		 1379
1380 tbiphy = of_phy_find_device(ug_info->tbi_node);
1381 if (!tbiphy)
c84d8055 1382 pr_warn("Could not get TBI device\n");
81abb43a
LYB		 1383
1384 value = phy_read(tbiphy, ENET_TBI_MII_CR);
ce973b14 1385 value &= ~0x1000; /* Turn off autonegotiation */
81abb43a 1386 phy_write(tbiphy, ENET_TBI_MII_CR, value);
ce973b14
LY		 1387 }
1388
1389 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1390
1391 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1392 if (ret_val != 0) {
890de95e 1393 if (netif_msg_probe(ugeth))
c84d8055 1394 pr_err("Preamble length must be between 3 and 7 inclusive\n");
ce973b14
LY		 1395 return ret_val;
1396 }
1397
1398 return 0;
1399}
1400
7de8ee78
AV		 1401static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1402{
1403 struct ucc_fast_private *uccf;
1404 u32 cecr_subblock;
1405 u32 temp;
1406 int i = 10;
1407
1408 uccf = ugeth->uccf;
1409
1410 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1411 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1412 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1413
1414 /* Issue host command */
1415 cecr_subblock =
1416 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1417 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1418 QE_CR_PROTOCOL_ETHERNET, 0);
1419
1420 /* Wait for command to complete */
1421 do {
1422 msleep(10);
1423 temp = in_be32(uccf->p_ucce);
1424 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1425
1426 uccf->stopped_tx = 1;
1427
1428 return 0;
1429}
1430
1431static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1432{
1433 struct ucc_fast_private *uccf;
1434 u32 cecr_subblock;
1435 u8 temp;
1436 int i = 10;
1437
1438 uccf = ugeth->uccf;
1439
1440 /* Clear acknowledge bit */
1441 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1442 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1443 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1444
1445 /* Keep issuing command and checking acknowledge bit until
1446 it is asserted, according to spec */
1447 do {
1448 /* Issue host command */
1449 cecr_subblock =
1450 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1451 ucc_num);
1452 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1453 QE_CR_PROTOCOL_ETHERNET, 0);
1454 msleep(10);
1455 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1456 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1457
1458 uccf->stopped_rx = 1;
1459
1460 return 0;
1461}
1462
1463static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1464{
1465 struct ucc_fast_private *uccf;
1466 u32 cecr_subblock;
1467
1468 uccf = ugeth->uccf;
1469
1470 cecr_subblock =
1471 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1472 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1473 uccf->stopped_tx = 0;
1474
1475 return 0;
1476}
1477
1478static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1479{
1480 struct ucc_fast_private *uccf;
1481 u32 cecr_subblock;
1482
1483 uccf = ugeth->uccf;
1484
1485 cecr_subblock =
1486 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1487 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1488 0);
1489 uccf->stopped_rx = 0;
1490
1491 return 0;
1492}
1493
1494static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1495{
1496 struct ucc_fast_private *uccf;
1497 int enabled_tx, enabled_rx;
1498
1499 uccf = ugeth->uccf;
1500
1501 /* check if the UCC number is in range. */
1502 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1503 if (netif_msg_probe(ugeth))
c84d8055 1504 pr_err("ucc_num out of range\n");
7de8ee78
AV		 1505 return -EINVAL;
1506 }
1507
1508 enabled_tx = uccf->enabled_tx;
1509 enabled_rx = uccf->enabled_rx;
1510
1511 /* Get Tx and Rx going again, in case this channel was actively
1512 disabled. */
1513 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1514 ugeth_restart_tx(ugeth);
1515 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1516 ugeth_restart_rx(ugeth);
1517
1518 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1519
1520 return 0;
1521
1522}
1523
1524static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1525{
1526 struct ucc_fast_private *uccf;
1527
1528 uccf = ugeth->uccf;
1529
1530 /* check if the UCC number is in range. */
1531 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1532 if (netif_msg_probe(ugeth))
c84d8055 1533 pr_err("ucc_num out of range\n");
7de8ee78
AV		 1534 return -EINVAL;
1535 }
1536
1537 /* Stop any transmissions */
1538 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1539 ugeth_graceful_stop_tx(ugeth);
1540
1541 /* Stop any receptions */
1542 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1543 ugeth_graceful_stop_rx(ugeth);
1544
1545 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1546
1547 return 0;
1548}
1549
864fdf88
AV		 1550static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1551{
08b5e1c9
AV		 1552 /* Prevent any further xmits, plus detach the device. */
1553 netif_device_detach(ugeth->ndev);
1554
1555 /* Wait for any current xmits to finish. */
864fdf88
AV		 1556 netif_tx_disable(ugeth->ndev);
1557
1558 /* Disable the interrupt to avoid NAPI rescheduling. */
1559 disable_irq(ugeth->ug_info->uf_info.irq);
1560
1561 /* Stop NAPI, and possibly wait for its completion. */
1562 napi_disable(&ugeth->napi);
1563}
1564
1565static void ugeth_activate(struct ucc_geth_private *ugeth)
1566{
1567 napi_enable(&ugeth->napi);
1568 enable_irq(ugeth->ug_info->uf_info.irq);
08b5e1c9 1569 netif_device_attach(ugeth->ndev);
864fdf88
AV		 1570}
1571
ce973b14
LY		 1572/* Called every time the controller might need to be made
1573 * aware of new link state. The PHY code conveys this
1574 * information through variables in the ugeth structure, and this
1575 * function converts those variables into the appropriate
1576 * register values, and can bring down the device if needed.
1577 */
728de4c9 1578
ce973b14
LY		 1579static void adjust_link(struct net_device *dev)
1580{
18a8e864 1581 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9
AF		 1582 struct ucc_geth __iomem *ug_regs;
1583 struct ucc_fast __iomem *uf_regs;
728de4c9 1584 struct phy_device *phydev = ugeth->phydev;
728de4c9 1585 int new_state = 0;
ce973b14
LY		 1586
1587 ug_regs = ugeth->ug_regs;
728de4c9 1588 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1589
728de4c9
KP		 1590 if (phydev->link) {
1591 u32 tempval = in_be32(&ug_regs->maccfg2);
1592 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1593 /* Now we make sure that we can be in full duplex mode.
1594 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1595 if (phydev->duplex != ugeth->oldduplex) {
1596 new_state = 1;
1597 if (!(phydev->duplex))
ce973b14 1598 tempval &= ~(MACCFG2_FDX);
728de4c9 1599 else
ce973b14 1600 tempval |= MACCFG2_FDX;
728de4c9 1601 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1602 }
1603
728de4c9
KP		 1604 if (phydev->speed != ugeth->oldspeed) {
1605 new_state = 1;
1606 switch (phydev->speed) {
1607 case SPEED_1000:
1608 tempval = ((tempval &
1609 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1610 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1611 break;
728de4c9
KP		 1612 case SPEED_100:
1613 case SPEED_10:
1614 tempval = ((tempval &
1615 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1616 MACCFG2_INTERFACE_MODE_NIBBLE);
1617 /* if reduced mode, re-set UPSMR.R10M */
1618 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1619 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1620 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1621 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1622 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9
KP		 1623 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1624 if (phydev->speed == SPEED_10)
3bc53427 1625 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9 1626 else
3bc53427 1627 upsmr &= ~UCC_GETH_UPSMR_R10M;
728de4c9 1628 }
ce973b14
LY		 1629 break;
1630 default:
728de4c9 1631 if (netif_msg_link(ugeth))
c84d8055 1632 pr_warn(
728de4c9
KP		 1633 "%s: Ack! Speed (%d) is not 10/100/1000!",
1634 dev->name, phydev->speed);
ce973b14
LY		 1635 break;
1636 }
728de4c9 1637 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1638 }
1639
1640 if (!ugeth->oldlink) {
728de4c9 1641 new_state = 1;
ce973b14 1642 ugeth->oldlink = 1;
ce973b14 1643 }
08fafd84
AV		 1644
1645 if (new_state) {
1646 /*
1647 * To change the MAC configuration we need to disable
1648 * the controller. To do so, we have to either grab
1649 * ugeth->lock, which is a bad idea since 'graceful
1650 * stop' commands might take quite a while, or we can
1651 * quiesce driver's activity.
1652 */
1653 ugeth_quiesce(ugeth);
1654 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1655
1656 out_be32(&ug_regs->maccfg2, tempval);
1657 out_be32(&uf_regs->upsmr, upsmr);
1658
1659 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1660 ugeth_activate(ugeth);
1661 }
728de4c9
KP		 1662 } else if (ugeth->oldlink) {
1663 new_state = 1;
ce973b14
LY		 1664 ugeth->oldlink = 0;
1665 ugeth->oldspeed = 0;
1666 ugeth->oldduplex = -1;
ce973b14 1667 }
728de4c9
KP		 1668
1669 if (new_state && netif_msg_link(ugeth))
1670 phy_print_status(phydev);
ce973b14
LY		 1671}
1672
fb1001f3
HW		 1673/* Initialize TBI PHY interface for communicating with the
1674 * SERDES lynx PHY on the chip. We communicate with this PHY
1675 * through the MDIO bus on each controller, treating it as a
1676 * "normal" PHY at the address found in the UTBIPA register. We assume
1677 * that the UTBIPA register is valid. Either the MDIO bus code will set
1678 * it to a value that doesn't conflict with other PHYs on the bus, or the
1679 * value doesn't matter, as there are no other PHYs on the bus.
1680 */
1681static void uec_configure_serdes(struct net_device *dev)
1682{
1683 struct ucc_geth_private *ugeth = netdev_priv(dev);
1684 struct ucc_geth_info *ug_info = ugeth->ug_info;
1685 struct phy_device *tbiphy;
1686
1687 if (!ug_info->tbi_node) {
1688 dev_warn(&dev->dev, "SGMII mode requires that the device "
1689 "tree specify a tbi-handle\n");
1690 return;
1691 }
1692
1693 tbiphy = of_phy_find_device(ug_info->tbi_node);
1694 if (!tbiphy) {
1695 dev_err(&dev->dev, "error: Could not get TBI device\n");
1696 return;
1697 }
1698
1699 /*
1700 * If the link is already up, we must already be ok, and don't need to
1701 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1702 * everything for us? Resetting it takes the link down and requires
1703 * several seconds for it to come back.
1704 */
1705 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1706 return;
1707
1708 /* Single clk mode, mii mode off(for serdes communication) */
1709 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1710
1711 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1712
1713 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1714}
1715
ce973b14
LY		 1716/* Configure the PHY for dev.
1717 * returns 0 if success. -1 if failure
1718 */
1719static int init_phy(struct net_device *dev)
1720{
728de4c9 1721 struct ucc_geth_private *priv = netdev_priv(dev);
61fa9dcf 1722 struct ucc_geth_info *ug_info = priv->ug_info;
728de4c9 1723 struct phy_device *phydev;
ce973b14 1724
728de4c9
KP		 1725 priv->oldlink = 0;
1726 priv->oldspeed = 0;
1727 priv->oldduplex = -1;
ce973b14 1728
0b9da337
GL		 1729 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1730 priv->phy_interface);
1731 if (!phydev) {
3104a6ff 1732 dev_err(&dev->dev, "Could not attach to PHY\n");
0b9da337 1733 return -ENODEV;
ce973b14
LY		 1734 }
1735
047584ce
HW		 1736 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1737 uec_configure_serdes(dev);
1738
bb24fd6a
JT		 1739 phydev->supported &= (SUPPORTED_MII |
1740 SUPPORTED_Autoneg |
1741 ADVERTISED_10baseT_Half |
1742 ADVERTISED_10baseT_Full |
1743 ADVERTISED_100baseT_Half |
1744 ADVERTISED_100baseT_Full);
ce973b14 1745
728de4c9
KP		 1746 if (priv->max_speed == SPEED_1000)
1747 phydev->supported |= ADVERTISED_1000baseT_Full;
ce973b14 1748
728de4c9 1749 phydev->advertising = phydev->supported;
68dc44af 1750
728de4c9 1751 priv->phydev = phydev;
ce973b14
LY		 1752
1753 return 0;
ce973b14
LY		 1754}
1755
18a8e864 1756static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1757{
1758#ifdef DEBUG
1759 ucc_fast_dump_regs(ugeth->uccf);
1760 dump_regs(ugeth);
1761 dump_bds(ugeth);
1762#endif
1763}
1764
18a8e864 1765static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1766 ugeth,
18a8e864 1767 enum enet_addr_type
ce973b14
LY		 1768 enet_addr_type)
1769{
6fee40e9 1770 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
18a8e864
LY		 1771 struct ucc_fast_private *uccf;
1772 enum comm_dir comm_dir;
ce973b14
LY		 1773 struct list_head *p_lh;
1774 u16 i, num;
6fee40e9
AF		 1775 u32 __iomem *addr_h;
1776 u32 __iomem *addr_l;
ce973b14
LY		 1777 u8 *p_counter;
1778
1779 uccf = ugeth->uccf;
1780
1781 p_82xx_addr_filt =
6fee40e9
AF		 1782 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1783 ugeth->p_rx_glbl_pram->addressfiltering;
ce973b14
LY		 1784
1785 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1786 addr_h = &(p_82xx_addr_filt->gaddr_h);
1787 addr_l = &(p_82xx_addr_filt->gaddr_l);
1788 p_lh = &ugeth->group_hash_q;
1789 p_counter = &(ugeth->numGroupAddrInHash);
1790 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1791 addr_h = &(p_82xx_addr_filt->iaddr_h);
1792 addr_l = &(p_82xx_addr_filt->iaddr_l);
1793 p_lh = &ugeth->ind_hash_q;
1794 p_counter = &(ugeth->numIndAddrInHash);
1795 } else
1796 return -EINVAL;
1797
1798 comm_dir = 0;
1799 if (uccf->enabled_tx)
1800 comm_dir |= COMM_DIR_TX;
1801 if (uccf->enabled_rx)
1802 comm_dir |= COMM_DIR_RX;
1803 if (comm_dir)
1804 ugeth_disable(ugeth, comm_dir);
1805
1806 /* Clear the hash table. */
1807 out_be32(addr_h, 0x00000000);
1808 out_be32(addr_l, 0x00000000);
1809
1810 if (!p_lh)
1811 return 0;
1812
1813 num = *p_counter;
1814
1815 /* Delete all remaining CQ elements */
1816 for (i = 0; i < num; i++)
1817 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1818
1819 *p_counter = 0;
1820
1821 if (comm_dir)
1822 ugeth_enable(ugeth, comm_dir);
1823
1824 return 0;
1825}
1826
18a8e864 1827static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 1828 u8 paddr_num)
1829{
1830 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1831 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1832}
1833
e19a82c1
PG		 1834static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1835{
1836 struct ucc_geth_info *ug_info;
1837 struct ucc_fast_info *uf_info;
1838 u16 i, j;
1839 u8 __iomem *bd;
1840
1841
1842 ug_info = ugeth->ug_info;
1843 uf_info = &ug_info->uf_info;
1844
1845 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1846 if (ugeth->p_rx_bd_ring[i]) {
1847 /* Return existing data buffers in ring */
1848 bd = ugeth->p_rx_bd_ring[i];
1849 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1850 if (ugeth->rx_skbuff[i][j]) {
1851 dma_unmap_single(ugeth->dev,
1852 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1853 ugeth->ug_info->
1854 uf_info.max_rx_buf_length +
1855 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1856 DMA_FROM_DEVICE);
1857 dev_kfree_skb_any(
1858 ugeth->rx_skbuff[i][j]);
1859 ugeth->rx_skbuff[i][j] = NULL;
1860 }
1861 bd += sizeof(struct qe_bd);
1862 }
1863
1864 kfree(ugeth->rx_skbuff[i]);
1865
1866 if (ugeth->ug_info->uf_info.bd_mem_part ==
1867 MEM_PART_SYSTEM)
1868 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1869 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1870 MEM_PART_MURAM)
1871 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1872 ugeth->p_rx_bd_ring[i] = NULL;
1873 }
1874 }
1875
1876}
1877
1878static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
ce973b14 1879{
e19a82c1
PG		 1880 struct ucc_geth_info *ug_info;
1881 struct ucc_fast_info *uf_info;
ce973b14 1882 u16 i, j;
6fee40e9 1883 u8 __iomem *bd;
ce973b14 1884
e19a82c1
PG		 1885 ug_info = ugeth->ug_info;
1886 uf_info = &ug_info->uf_info;
1887
1888 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1889 bd = ugeth->p_tx_bd_ring[i];
1890 if (!bd)
1891 continue;
1892 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1893 if (ugeth->tx_skbuff[i][j]) {
1894 dma_unmap_single(ugeth->dev,
1895 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1896 (in_be32((u32 __iomem *)bd) &
1897 BD_LENGTH_MASK),
1898 DMA_TO_DEVICE);
1899 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1900 ugeth->tx_skbuff[i][j] = NULL;
1901 }
1902 }
1903
1904 kfree(ugeth->tx_skbuff[i]);
1905
1906 if (ugeth->p_tx_bd_ring[i]) {
1907 if (ugeth->ug_info->uf_info.bd_mem_part ==
1908 MEM_PART_SYSTEM)
1909 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1910 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1911 MEM_PART_MURAM)
1912 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1913 ugeth->p_tx_bd_ring[i] = NULL;
1914 }
1915 }
1916
1917}
1918
1919static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1920{
ce973b14
LY		 1921 if (!ugeth)
1922 return;
1923
80a9fad8 1924 if (ugeth->uccf) {
ce973b14 1925 ucc_fast_free(ugeth->uccf);
80a9fad8
AV		 1926 ugeth->uccf = NULL;
1927 }
ce973b14
LY		 1928
1929 if (ugeth->p_thread_data_tx) {
1930 qe_muram_free(ugeth->thread_dat_tx_offset);
1931 ugeth->p_thread_data_tx = NULL;
1932 }
1933 if (ugeth->p_thread_data_rx) {
1934 qe_muram_free(ugeth->thread_dat_rx_offset);
1935 ugeth->p_thread_data_rx = NULL;
1936 }
1937 if (ugeth->p_exf_glbl_param) {
1938 qe_muram_free(ugeth->exf_glbl_param_offset);
1939 ugeth->p_exf_glbl_param = NULL;
1940 }
1941 if (ugeth->p_rx_glbl_pram) {
1942 qe_muram_free(ugeth->rx_glbl_pram_offset);
1943 ugeth->p_rx_glbl_pram = NULL;
1944 }
1945 if (ugeth->p_tx_glbl_pram) {
1946 qe_muram_free(ugeth->tx_glbl_pram_offset);
1947 ugeth->p_tx_glbl_pram = NULL;
1948 }
1949 if (ugeth->p_send_q_mem_reg) {
1950 qe_muram_free(ugeth->send_q_mem_reg_offset);
1951 ugeth->p_send_q_mem_reg = NULL;
1952 }
1953 if (ugeth->p_scheduler) {
1954 qe_muram_free(ugeth->scheduler_offset);
1955 ugeth->p_scheduler = NULL;
1956 }
1957 if (ugeth->p_tx_fw_statistics_pram) {
1958 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1959 ugeth->p_tx_fw_statistics_pram = NULL;
1960 }
1961 if (ugeth->p_rx_fw_statistics_pram) {
1962 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1963 ugeth->p_rx_fw_statistics_pram = NULL;
1964 }
1965 if (ugeth->p_rx_irq_coalescing_tbl) {
1966 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1967 ugeth->p_rx_irq_coalescing_tbl = NULL;
1968 }
1969 if (ugeth->p_rx_bd_qs_tbl) {
1970 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1971 ugeth->p_rx_bd_qs_tbl = NULL;
1972 }
1973 if (ugeth->p_init_enet_param_shadow) {
1974 return_init_enet_entries(ugeth,
1975 &(ugeth->p_init_enet_param_shadow->
1976 rxthread[0]),
1977 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1978 ugeth->ug_info->riscRx, 1);
1979 return_init_enet_entries(ugeth,
1980 &(ugeth->p_init_enet_param_shadow->
1981 txthread[0]),
1982 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1983 ugeth->ug_info->riscTx, 0);
1984 kfree(ugeth->p_init_enet_param_shadow);
1985 ugeth->p_init_enet_param_shadow = NULL;
1986 }
e19a82c1
PG		 1987 ucc_geth_free_tx(ugeth);
1988 ucc_geth_free_rx(ugeth);
ce973b14
LY		 1989 while (!list_empty(&ugeth->group_hash_q))
1990 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1991 (dequeue(&ugeth->group_hash_q)));
1992 while (!list_empty(&ugeth->ind_hash_q))
1993 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1994 (dequeue(&ugeth->ind_hash_q)));
3e73fc9a
AV		 1995 if (ugeth->ug_regs) {
1996 iounmap(ugeth->ug_regs);
1997 ugeth->ug_regs = NULL;
1998 }
ce973b14
LY		 1999}
2000
2001static void ucc_geth_set_multi(struct net_device *dev)
2002{
18a8e864 2003 struct ucc_geth_private *ugeth;
22bedad3 2004 struct netdev_hw_addr *ha;
6fee40e9
AF		 2005 struct ucc_fast __iomem *uf_regs;
2006 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 2007
2008 ugeth = netdev_priv(dev);
2009
2010 uf_regs = ugeth->uccf->uf_regs;
2011
2012 if (dev->flags & IFF_PROMISC) {
3bc53427 2013 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14 2014 } else {
3bc53427 2015 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14
LY		 2016
2017 p_82xx_addr_filt =
6fee40e9 2018 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2019 p_rx_glbl_pram->addressfiltering;
2020
2021 if (dev->flags & IFF_ALLMULTI) {
2022 /* Catch all multicast addresses, so set the
2023 * filter to all 1's.
2024 */
2025 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2026 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2027 } else {
2028 /* Clear filter and add the addresses in the list.
2029 */
2030 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2031 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2032
22bedad3 2033 netdev_for_each_mc_addr(ha, dev) {
ce973b14
LY		 2034 /* Ask CPM to run CRC and set bit in
2035 * filter mask.
2036 */
22bedad3 2037 hw_add_addr_in_hash(ugeth, ha->addr);
ce973b14
LY		 2038 }
2039 }
2040 }
2041}
2042
18a8e864 2043static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 2044{
6fee40e9 2045 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
728de4c9 2046 struct phy_device *phydev = ugeth->phydev;
ce973b14 2047
b39d66a8 2048 ugeth_vdbg("%s: IN", __func__);
ce973b14 2049
75e60474
JT		 2050 /*
2051 * Tell the kernel the link is down.
2052 * Must be done before disabling the controller
2053 * or deadlock may happen.
2054 */
2055 phy_stop(phydev);
2056
ce973b14
LY		 2057 /* Disable the controller */
2058 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2059
ce973b14 2060 /* Mask all interrupts */
c6f5047b 2061 out_be32(ugeth->uccf->p_uccm, 0x00000000);
ce973b14
LY		 2062
2063 /* Clear all interrupts */
2064 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2065
2066 /* Disable Rx and Tx */
3bc53427 2067 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14 2068
ce973b14
LY		 2069 ucc_geth_memclean(ugeth);
2070}
2071
728de4c9 2072static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2073{
18a8e864
LY		 2074 struct ucc_geth_info *ug_info;
2075 struct ucc_fast_info *uf_info;
728de4c9 2076 int i;
ce973b14
LY		 2077
2078 ug_info = ugeth->ug_info;
2079 uf_info = &ug_info->uf_info;
2080
2081 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2082 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
890de95e 2083 if (netif_msg_probe(ugeth))
c84d8055 2084 pr_err("Bad memory partition value\n");
ce973b14
LY		 2085 return -EINVAL;
2086 }
2087
2088 /* Rx BD lengths */
2089 for (i = 0; i < ug_info->numQueuesRx; i++) {
2090 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2091 (ug_info->bdRingLenRx[i] %
2092 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
890de95e 2093 if (netif_msg_probe(ugeth))
c84d8055 2094 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
ce973b14
LY		 2095 return -EINVAL;
2096 }
2097 }
2098
2099 /* Tx BD lengths */
2100 for (i = 0; i < ug_info->numQueuesTx; i++) {
2101 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
890de95e 2102 if (netif_msg_probe(ugeth))
c84d8055 2103 pr_err("Tx BD ring length must be no smaller than 2\n");
ce973b14
LY		 2104 return -EINVAL;
2105 }
2106 }
2107
2108 /* mrblr */
2109 if ((uf_info->max_rx_buf_length == 0) ||
2110 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
890de95e 2111 if (netif_msg_probe(ugeth))
c84d8055 2112 pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
ce973b14
LY		 2113 return -EINVAL;
2114 }
2115
2116 /* num Tx queues */
2117 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
890de95e 2118 if (netif_msg_probe(ugeth))
c84d8055 2119 pr_err("number of tx queues too large\n");
ce973b14
LY		 2120 return -EINVAL;
2121 }
2122
2123 /* num Rx queues */
2124 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
890de95e 2125 if (netif_msg_probe(ugeth))
c84d8055 2126 pr_err("number of rx queues too large\n");
ce973b14
LY		 2127 return -EINVAL;
2128 }
2129
2130 /* l2qt */
2131 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2132 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
890de95e 2133 if (netif_msg_probe(ugeth))
c84d8055 2134 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
ce973b14
LY		 2135 return -EINVAL;
2136 }
2137 }
2138
2139 /* l3qt */
2140 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2141 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
890de95e 2142 if (netif_msg_probe(ugeth))
c84d8055 2143 pr_err("IP priority table entry must not be larger than number of Rx queues\n");
ce973b14
LY		 2144 return -EINVAL;
2145 }
2146 }
2147
2148 if (ug_info->cam && !ug_info->ecamptr) {
890de95e 2149 if (netif_msg_probe(ugeth))
c84d8055 2150 pr_err("If cam mode is chosen, must supply cam ptr\n");
ce973b14
LY		 2151 return -EINVAL;
2152 }
2153
2154 if ((ug_info->numStationAddresses !=
8e95a202
JP		 2155 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2156 ug_info->rxExtendedFiltering) {
890de95e 2157 if (netif_msg_probe(ugeth))
c84d8055 2158 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
ce973b14
LY		 2159 return -EINVAL;
2160 }
2161
2162 /* Generate uccm_mask for receive */
2163 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2164 for (i = 0; i < ug_info->numQueuesRx; i++)
3bc53427 2165 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
ce973b14
LY		 2166
2167 for (i = 0; i < ug_info->numQueuesTx; i++)
3bc53427 2168 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
ce973b14 2169 /* Initialize the general fast UCC block. */
728de4c9 2170 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
890de95e 2171 if (netif_msg_probe(ugeth))
c84d8055 2172 pr_err("Failed to init uccf\n");
ce973b14
LY		 2173 return -ENOMEM;
2174 }
728de4c9 2175
345f8422
HW		 2176 /* read the number of risc engines, update the riscTx and riscRx
2177 * if there are 4 riscs in QE
2178 */
2179 if (qe_get_num_of_risc() == 4) {
2180 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2181 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2182 }
2183
3e73fc9a
AV		 2184 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2185 if (!ugeth->ug_regs) {
2186 if (netif_msg_probe(ugeth))
c84d8055 2187 pr_err("Failed to ioremap regs\n");
3e73fc9a
AV		 2188 return -ENOMEM;
2189 }
728de4c9
KP		 2190
2191 return 0;
2192}
2193
e19a82c1
PG		 2194static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2195{
2196 struct ucc_geth_info *ug_info;
2197 struct ucc_fast_info *uf_info;
2198 int length;
2199 u16 i, j;
2200 u8 __iomem *bd;
2201
2202 ug_info = ugeth->ug_info;
2203 uf_info = &ug_info->uf_info;
2204
2205 /* Allocate Tx bds */
2206 for (j = 0; j < ug_info->numQueuesTx; j++) {
2207 /* Allocate in multiple of
2208 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2209 according to spec */
2210 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2211 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2212 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2213 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2214 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2215 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2216 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2217 u32 align = 4;
2218 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2219 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2220 ugeth->tx_bd_ring_offset[j] =
2221 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2222
2223 if (ugeth->tx_bd_ring_offset[j] != 0)
2224 ugeth->p_tx_bd_ring[j] =
2225 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2226 align) & ~(align - 1));
2227 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2228 ugeth->tx_bd_ring_offset[j] =
2229 qe_muram_alloc(length,
2230 UCC_GETH_TX_BD_RING_ALIGNMENT);
2231 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2232 ugeth->p_tx_bd_ring[j] =
2233 (u8 __iomem *) qe_muram_addr(ugeth->
2234 tx_bd_ring_offset[j]);
2235 }
2236 if (!ugeth->p_tx_bd_ring[j]) {
2237 if (netif_msg_ifup(ugeth))
c84d8055 2238 pr_err("Can not allocate memory for Tx bd rings\n");
e19a82c1
PG		 2239 return -ENOMEM;
2240 }
2241 /* Zero unused end of bd ring, according to spec */
2242 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2243 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2244 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2245 }
2246
2247 /* Init Tx bds */
2248 for (j = 0; j < ug_info->numQueuesTx; j++) {
2249 /* Setup the skbuff rings */
2250 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2251 ugeth->ug_info->bdRingLenTx[j],
2252 GFP_KERNEL);
2253
2254 if (ugeth->tx_skbuff[j] == NULL) {
2255 if (netif_msg_ifup(ugeth))
c84d8055 2256 pr_err("Could not allocate tx_skbuff\n");
e19a82c1
PG		 2257 return -ENOMEM;
2258 }
2259
2260 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2261 ugeth->tx_skbuff[j][i] = NULL;
2262
2263 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2264 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2265 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2266 /* clear bd buffer */
2267 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2268 /* set bd status and length */
2269 out_be32((u32 __iomem *)bd, 0);
2270 bd += sizeof(struct qe_bd);
2271 }
2272 bd -= sizeof(struct qe_bd);
2273 /* set bd status and length */
2274 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2275 }
2276
2277 return 0;
2278}
2279
2280static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2281{
2282 struct ucc_geth_info *ug_info;
2283 struct ucc_fast_info *uf_info;
2284 int length;
2285 u16 i, j;
2286 u8 __iomem *bd;
2287
2288 ug_info = ugeth->ug_info;
2289 uf_info = &ug_info->uf_info;
2290
2291 /* Allocate Rx bds */
2292 for (j = 0; j < ug_info->numQueuesRx; j++) {
2293 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2294 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2295 u32 align = 4;
2296 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2297 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2298 ugeth->rx_bd_ring_offset[j] =
2299 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2300 if (ugeth->rx_bd_ring_offset[j] != 0)
2301 ugeth->p_rx_bd_ring[j] =
2302 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2303 align) & ~(align - 1));
2304 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2305 ugeth->rx_bd_ring_offset[j] =
2306 qe_muram_alloc(length,
2307 UCC_GETH_RX_BD_RING_ALIGNMENT);
2308 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2309 ugeth->p_rx_bd_ring[j] =
2310 (u8 __iomem *) qe_muram_addr(ugeth->
2311 rx_bd_ring_offset[j]);
2312 }
2313 if (!ugeth->p_rx_bd_ring[j]) {
2314 if (netif_msg_ifup(ugeth))
c84d8055 2315 pr_err("Can not allocate memory for Rx bd rings\n");
e19a82c1
PG		 2316 return -ENOMEM;
2317 }
2318 }
2319
2320 /* Init Rx bds */
2321 for (j = 0; j < ug_info->numQueuesRx; j++) {
2322 /* Setup the skbuff rings */
2323 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2324 ugeth->ug_info->bdRingLenRx[j],
2325 GFP_KERNEL);
2326
2327 if (ugeth->rx_skbuff[j] == NULL) {
2328 if (netif_msg_ifup(ugeth))
c84d8055 2329 pr_err("Could not allocate rx_skbuff\n");
e19a82c1
PG		 2330 return -ENOMEM;
2331 }
2332
2333 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2334 ugeth->rx_skbuff[j][i] = NULL;
2335
2336 ugeth->skb_currx[j] = 0;
2337 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2338 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2339 /* set bd status and length */
2340 out_be32((u32 __iomem *)bd, R_I);
2341 /* clear bd buffer */
2342 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2343 bd += sizeof(struct qe_bd);
2344 }
2345 bd -= sizeof(struct qe_bd);
2346 /* set bd status and length */
2347 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2348 }
2349
2350 return 0;
2351}
2352
728de4c9
KP		 2353static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2354{
6fee40e9
AF		 2355 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2356 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
728de4c9
KP		 2357 struct ucc_fast_private *uccf;
2358 struct ucc_geth_info *ug_info;
2359 struct ucc_fast_info *uf_info;
6fee40e9
AF		 2360 struct ucc_fast __iomem *uf_regs;
2361 struct ucc_geth __iomem *ug_regs;
728de4c9
KP		 2362 int ret_val = -EINVAL;
2363 u32 remoder = UCC_GETH_REMODER_INIT;
3bc53427 2364 u32 init_enet_pram_offset, cecr_subblock, command;
e19a82c1 2365 u32 ifstat, i, j, size, l2qt, l3qt;
728de4c9
KP		 2366 u16 temoder = UCC_GETH_TEMODER_INIT;
2367 u16 test;
2368 u8 function_code = 0;
6fee40e9 2369 u8 __iomem *endOfRing;
728de4c9
KP		 2370 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2371
b39d66a8 2372 ugeth_vdbg("%s: IN", __func__);
728de4c9
KP		 2373 uccf = ugeth->uccf;
2374 ug_info = ugeth->ug_info;
2375 uf_info = &ug_info->uf_info;
2376 uf_regs = uccf->uf_regs;
2377 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2378
2379 switch (ug_info->numThreadsRx) {
2380 case UCC_GETH_NUM_OF_THREADS_1:
2381 numThreadsRxNumerical = 1;
2382 break;
2383 case UCC_GETH_NUM_OF_THREADS_2:
2384 numThreadsRxNumerical = 2;
2385 break;
2386 case UCC_GETH_NUM_OF_THREADS_4:
2387 numThreadsRxNumerical = 4;
2388 break;
2389 case UCC_GETH_NUM_OF_THREADS_6:
2390 numThreadsRxNumerical = 6;
2391 break;
2392 case UCC_GETH_NUM_OF_THREADS_8:
2393 numThreadsRxNumerical = 8;
2394 break;
2395 default:
890de95e 2396 if (netif_msg_ifup(ugeth))
c84d8055 2397 pr_err("Bad number of Rx threads value\n");
ce973b14 2398 return -EINVAL;
ce973b14
LY		 2399 }
2400
2401 switch (ug_info->numThreadsTx) {
2402 case UCC_GETH_NUM_OF_THREADS_1:
2403 numThreadsTxNumerical = 1;
2404 break;
2405 case UCC_GETH_NUM_OF_THREADS_2:
2406 numThreadsTxNumerical = 2;
2407 break;
2408 case UCC_GETH_NUM_OF_THREADS_4:
2409 numThreadsTxNumerical = 4;
2410 break;
2411 case UCC_GETH_NUM_OF_THREADS_6:
2412 numThreadsTxNumerical = 6;
2413 break;
2414 case UCC_GETH_NUM_OF_THREADS_8:
2415 numThreadsTxNumerical = 8;
2416 break;
2417 default:
890de95e 2418 if (netif_msg_ifup(ugeth))
c84d8055 2419 pr_err("Bad number of Tx threads value\n");
ce973b14 2420 return -EINVAL;
ce973b14
LY		 2421 }
2422
2423 /* Calculate rx_extended_features */
2424 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2425 ug_info->ipAddressAlignment ||
2426 (ug_info->numStationAddresses !=
2427 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2428
2429 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
8e95a202
JP		 2430 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2431 (ug_info->vlanOperationNonTagged !=
2432 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
ce973b14 2433
ce973b14
LY		 2434 init_default_reg_vals(&uf_regs->upsmr,
2435 &ug_regs->maccfg1, &ug_regs->maccfg2);
2436
2437 /* Set UPSMR */
2438 /* For more details see the hardware spec. */
2439 init_rx_parameters(ug_info->bro,
2440 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2441
2442 /* We're going to ignore other registers for now, */
2443 /* except as needed to get up and running */
2444
2445 /* Set MACCFG1 */
2446 /* For more details see the hardware spec. */
2447 init_flow_control_params(ug_info->aufc,
2448 ug_info->receiveFlowControl,
ac421852 2449 ug_info->transmitFlowControl,
ce973b14
LY		 2450 ug_info->pausePeriod,
2451 ug_info->extensionField,
2452 &uf_regs->upsmr,
2453 &ug_regs->uempr, &ug_regs->maccfg1);
2454
3bc53427 2455 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14
LY		 2456
2457 /* Set IPGIFG */
2458 /* For more details see the hardware spec. */
2459 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2460 ug_info->nonBackToBackIfgPart2,
2461 ug_info->
2462 miminumInterFrameGapEnforcement,
2463 ug_info->backToBackInterFrameGap,
2464 &ug_regs->ipgifg);
2465 if (ret_val != 0) {
890de95e 2466 if (netif_msg_ifup(ugeth))
c84d8055 2467 pr_err("IPGIFG initialization parameter too large\n");
ce973b14
LY		 2468 return ret_val;
2469 }
2470
2471 /* Set HAFDUP */
2472 /* For more details see the hardware spec. */
2473 ret_val = init_half_duplex_params(ug_info->altBeb,
2474 ug_info->backPressureNoBackoff,
2475 ug_info->noBackoff,
2476 ug_info->excessDefer,
2477 ug_info->altBebTruncation,
2478 ug_info->maxRetransmission,
2479 ug_info->collisionWindow,
2480 &ug_regs->hafdup);
2481 if (ret_val != 0) {
890de95e 2482 if (netif_msg_ifup(ugeth))
c84d8055 2483 pr_err("Half Duplex initialization parameter too large\n");
ce973b14
LY		 2484 return ret_val;
2485 }
2486
2487 /* Set IFSTAT */
2488 /* For more details see the hardware spec. */
2489 /* Read only - resets upon read */
2490 ifstat = in_be32(&ug_regs->ifstat);
2491
2492 /* Clear UEMPR */
2493 /* For more details see the hardware spec. */
2494 out_be32(&ug_regs->uempr, 0);
2495
2496 /* Set UESCR */
2497 /* For more details see the hardware spec. */
2498 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2499 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2500 0, &uf_regs->upsmr, &ug_regs->uescr);
2501
e19a82c1
PG		 2502 ret_val = ucc_geth_alloc_tx(ugeth);
2503 if (ret_val != 0)
2504 return ret_val;
ce973b14 2505
e19a82c1
PG		 2506 ret_val = ucc_geth_alloc_rx(ugeth);
2507 if (ret_val != 0)
2508 return ret_val;
ce973b14
LY		 2509
2510 /*
2511 * Global PRAM
2512 */
2513 /* Tx global PRAM */
2514 /* Allocate global tx parameter RAM page */
2515 ugeth->tx_glbl_pram_offset =
18a8e864 2516 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14 2517 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2518 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
890de95e 2519 if (netif_msg_ifup(ugeth))
c84d8055 2520 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
ce973b14
LY		 2521 return -ENOMEM;
2522 }
2523 ugeth->p_tx_glbl_pram =
6fee40e9 2524 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2525 tx_glbl_pram_offset);
2526 /* Zero out p_tx_glbl_pram */
6fee40e9 2527 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2528
2529 /* Fill global PRAM */
2530
2531 /* TQPTR */
2532 /* Size varies with number of Tx threads */
2533 ugeth->thread_dat_tx_offset =
2534 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2535 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2536 32 * (numThreadsTxNumerical == 1),
2537 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2538 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
890de95e 2539 if (netif_msg_ifup(ugeth))
c84d8055 2540 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
ce973b14
LY		 2541 return -ENOMEM;
2542 }
2543
2544 ugeth->p_thread_data_tx =
6fee40e9 2545 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2546 thread_dat_tx_offset);
2547 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2548
2549 /* vtagtable */
2550 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2551 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2552 ug_info->vtagtable[i]);
2553
2554 /* iphoffset */
2555 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
6fee40e9
AF		 2556 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2557 ug_info->iphoffset[i]);
ce973b14
LY		 2558
2559 /* SQPTR */
2560 /* Size varies with number of Tx queues */
2561 ugeth->send_q_mem_reg_offset =
2562 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2563 sizeof(struct ucc_geth_send_queue_qd),
ce973b14 2564 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
4c35630c 2565 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
890de95e 2566 if (netif_msg_ifup(ugeth))
c84d8055 2567 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
ce973b14
LY		 2568 return -ENOMEM;
2569 }
2570
2571 ugeth->p_send_q_mem_reg =
6fee40e9 2572 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2573 send_q_mem_reg_offset);
2574 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2575
2576 /* Setup the table */
2577 /* Assume BD rings are already established */
2578 for (i = 0; i < ug_info->numQueuesTx; i++) {
2579 endOfRing =
2580 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2581 1) * sizeof(struct qe_bd);
ce973b14
LY		 2582 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2583 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2584 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2585 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2586 last_bd_completed_address,
2587 (u32) virt_to_phys(endOfRing));
2588 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2589 MEM_PART_MURAM) {
2590 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2591 (u32) immrbar_virt_to_phys(ugeth->
2592 p_tx_bd_ring[i]));
2593 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2594 last_bd_completed_address,
2595 (u32) immrbar_virt_to_phys(endOfRing));
2596 }
2597 }
2598
2599 /* schedulerbasepointer */
2600
2601 if (ug_info->numQueuesTx > 1) {
2602 /* scheduler exists only if more than 1 tx queue */
2603 ugeth->scheduler_offset =
18a8e864 2604 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14 2605 UCC_GETH_SCHEDULER_ALIGNMENT);
4c35630c 2606 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
890de95e 2607 if (netif_msg_ifup(ugeth))
c84d8055 2608 pr_err("Can not allocate DPRAM memory for p_scheduler\n");
ce973b14
LY		 2609 return -ENOMEM;
2610 }
2611
2612 ugeth->p_scheduler =
6fee40e9 2613 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2614 scheduler_offset);
2615 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2616 ugeth->scheduler_offset);
2617 /* Zero out p_scheduler */
6fee40e9 2618 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2619
2620 /* Set values in scheduler */
2621 out_be32(&ugeth->p_scheduler->mblinterval,
2622 ug_info->mblinterval);
2623 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2624 ug_info->nortsrbytetime);
6fee40e9
AF		 2625 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2626 out_8(&ugeth->p_scheduler->strictpriorityq,
2627 ug_info->strictpriorityq);
2628 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2629 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
ce973b14 2630 for (i = 0; i < NUM_TX_QUEUES; i++)
6fee40e9
AF		 2631 out_8(&ugeth->p_scheduler->weightfactor[i],
2632 ug_info->weightfactor[i]);
ce973b14
LY		 2633
2634 /* Set pointers to cpucount registers in scheduler */
2635 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2636 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2637 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2638 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2639 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2640 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2641 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2642 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2643 }
2644
2645 /* schedulerbasepointer */
2646 /* TxRMON_PTR (statistics) */
2647 if (ug_info->
2648 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2649 ugeth->tx_fw_statistics_pram_offset =
2650 qe_muram_alloc(sizeof
18a8e864 2651 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14 2652 UCC_GETH_TX_STATISTICS_ALIGNMENT);
4c35630c 2653 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
890de95e 2654 if (netif_msg_ifup(ugeth))
c84d8055 2655 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
ce973b14
LY		 2656 return -ENOMEM;
2657 }
2658 ugeth->p_tx_fw_statistics_pram =
6fee40e9 2659 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2660 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2661 /* Zero out p_tx_fw_statistics_pram */
6fee40e9 2662 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
18a8e864 2663 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2664 }
2665
2666 /* temoder */
2667 /* Already has speed set */
2668
2669 if (ug_info->numQueuesTx > 1)
2670 temoder |= TEMODER_SCHEDULER_ENABLE;
2671 if (ug_info->ipCheckSumGenerate)
2672 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2673 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2674 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2675
2676 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2677
2678 /* Function code register value to be used later */
6b0b594b 2679 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
ce973b14
LY		 2680 /* Required for QE */
2681
2682 /* function code register */
2683 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2684
2685 /* Rx global PRAM */
2686 /* Allocate global rx parameter RAM page */
2687 ugeth->rx_glbl_pram_offset =
18a8e864 2688 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14 2689 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2690 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
890de95e 2691 if (netif_msg_ifup(ugeth))
c84d8055 2692 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
ce973b14
LY		 2693 return -ENOMEM;
2694 }
2695 ugeth->p_rx_glbl_pram =
6fee40e9 2696 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2697 rx_glbl_pram_offset);
2698 /* Zero out p_rx_glbl_pram */
6fee40e9 2699 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2700
2701 /* Fill global PRAM */
2702
2703 /* RQPTR */
2704 /* Size varies with number of Rx threads */
2705 ugeth->thread_dat_rx_offset =
2706 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2707 sizeof(struct ucc_geth_thread_data_rx),
ce973b14 2708 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2709 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
890de95e 2710 if (netif_msg_ifup(ugeth))
c84d8055 2711 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
ce973b14
LY		 2712 return -ENOMEM;
2713 }
2714
2715 ugeth->p_thread_data_rx =
6fee40e9 2716 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2717 thread_dat_rx_offset);
2718 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2719
2720 /* typeorlen */
2721 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2722
2723 /* rxrmonbaseptr (statistics) */
2724 if (ug_info->
2725 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2726 ugeth->rx_fw_statistics_pram_offset =
2727 qe_muram_alloc(sizeof
18a8e864 2728 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14 2729 UCC_GETH_RX_STATISTICS_ALIGNMENT);
4c35630c 2730 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
890de95e 2731 if (netif_msg_ifup(ugeth))
c84d8055 2732 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
ce973b14
LY		 2733 return -ENOMEM;
2734 }
2735 ugeth->p_rx_fw_statistics_pram =
6fee40e9 2736 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2737 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2738 /* Zero out p_rx_fw_statistics_pram */
6fee40e9 2739 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2740 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2741 }
2742
2743 /* intCoalescingPtr */
2744
2745 /* Size varies with number of Rx queues */
2746 ugeth->rx_irq_coalescing_tbl_offset =
2747 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 2748 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2749 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
4c35630c 2750 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
890de95e 2751 if (netif_msg_ifup(ugeth))
c84d8055 2752 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
ce973b14
LY		 2753 return -ENOMEM;
2754 }
2755
2756 ugeth->p_rx_irq_coalescing_tbl =
6fee40e9 2757 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
ce973b14
LY		 2758 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2759 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2760 ugeth->rx_irq_coalescing_tbl_offset);
2761
2762 /* Fill interrupt coalescing table */
2763 for (i = 0; i < ug_info->numQueuesRx; i++) {
2764 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2765 interruptcoalescingmaxvalue,
2766 ug_info->interruptcoalescingmaxvalue[i]);
2767 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2768 interruptcoalescingcounter,
2769 ug_info->interruptcoalescingmaxvalue[i]);
2770 }
2771
2772 /* MRBLR */
2773 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2774 &ugeth->p_rx_glbl_pram->mrblr);
2775 /* MFLR */
2776 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2777 /* MINFLR */
2778 init_min_frame_len(ug_info->minFrameLength,
2779 &ugeth->p_rx_glbl_pram->minflr,
2780 &ugeth->p_rx_glbl_pram->mrblr);
2781 /* MAXD1 */
2782 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2783 /* MAXD2 */
2784 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2785
2786 /* l2qt */
2787 l2qt = 0;
2788 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2789 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2790 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2791
2792 /* l3qt */
2793 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2794 l3qt = 0;
2795 for (i = 0; i < 8; i++)
2796 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 2797 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 2798 }
2799
2800 /* vlantype */
2801 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2802
2803 /* vlantci */
2804 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2805
2806 /* ecamptr */
2807 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2808
2809 /* RBDQPTR */
2810 /* Size varies with number of Rx queues */
2811 ugeth->rx_bd_qs_tbl_offset =
2812 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 2813 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2814 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14 2815 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
4c35630c 2816 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
890de95e 2817 if (netif_msg_ifup(ugeth))
c84d8055 2818 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
ce973b14
LY		 2819 return -ENOMEM;
2820 }
2821
2822 ugeth->p_rx_bd_qs_tbl =
6fee40e9 2823 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2824 rx_bd_qs_tbl_offset);
2825 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2826 /* Zero out p_rx_bd_qs_tbl */
6fee40e9 2827 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
ce973b14 2828 0,
18a8e864
LY		 2829 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2830 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 2831
2832 /* Setup the table */
2833 /* Assume BD rings are already established */
2834 for (i = 0; i < ug_info->numQueuesRx; i++) {
2835 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2836 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2837 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2838 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2839 MEM_PART_MURAM) {
2840 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2841 (u32) immrbar_virt_to_phys(ugeth->
2842 p_rx_bd_ring[i]));
2843 }
2844 /* rest of fields handled by QE */
2845 }
2846
2847 /* remoder */
2848 /* Already has speed set */
2849
2850 if (ugeth->rx_extended_features)
2851 remoder |= REMODER_RX_EXTENDED_FEATURES;
2852 if (ug_info->rxExtendedFiltering)
2853 remoder |= REMODER_RX_EXTENDED_FILTERING;
2854 if (ug_info->dynamicMaxFrameLength)
2855 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2856 if (ug_info->dynamicMinFrameLength)
2857 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2858 remoder |=
2859 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2860 remoder |=
2861 ug_info->
2862 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2863 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2864 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2865 if (ug_info->ipCheckSumCheck)
2866 remoder |= REMODER_IP_CHECKSUM_CHECK;
2867 if (ug_info->ipAddressAlignment)
2868 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2869 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2870
2871 /* Note that this function must be called */
2872 /* ONLY AFTER p_tx_fw_statistics_pram */
2873 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2874 init_firmware_statistics_gathering_mode((ug_info->
2875 statisticsMode &
2876 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2877 (ug_info->statisticsMode &
2878 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2879 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2880 ugeth->tx_fw_statistics_pram_offset,
2881 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2882 ugeth->rx_fw_statistics_pram_offset,
2883 &ugeth->p_tx_glbl_pram->temoder,
2884 &ugeth->p_rx_glbl_pram->remoder);
2885
2886 /* function code register */
6fee40e9 2887 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
ce973b14
LY		 2888
2889 /* initialize extended filtering */
2890 if (ug_info->rxExtendedFiltering) {
2891 if (!ug_info->extendedFilteringChainPointer) {
890de95e 2892 if (netif_msg_ifup(ugeth))
c84d8055 2893 pr_err("Null Extended Filtering Chain Pointer\n");
ce973b14
LY		 2894 return -EINVAL;
2895 }
2896
2897 /* Allocate memory for extended filtering Mode Global
2898 Parameters */
2899 ugeth->exf_glbl_param_offset =
18a8e864 2900 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14 2901 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
4c35630c 2902 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
890de95e 2903 if (netif_msg_ifup(ugeth))
c84d8055 2904 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
ce973b14
LY		 2905 return -ENOMEM;
2906 }
2907
2908 ugeth->p_exf_glbl_param =
6fee40e9 2909 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2910 exf_glbl_param_offset);
2911 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2912 ugeth->exf_glbl_param_offset);
2913 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2914 (u32) ug_info->extendedFilteringChainPointer);
2915
2916 } else { /* initialize 82xx style address filtering */
2917
2918 /* Init individual address recognition registers to disabled */
2919
2920 for (j = 0; j < NUM_OF_PADDRS; j++)
2921 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2922
ce973b14 2923 p_82xx_addr_filt =
6fee40e9 2924 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2925 p_rx_glbl_pram->addressfiltering;
2926
2927 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2928 ENET_ADDR_TYPE_GROUP);
2929 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2930 ENET_ADDR_TYPE_INDIVIDUAL);
2931 }
2932
2933 /*
2934 * Initialize UCC at QE level
2935 */
2936
2937 command = QE_INIT_TX_RX;
2938
2939 /* Allocate shadow InitEnet command parameter structure.
2940 * This is needed because after the InitEnet command is executed,
2941 * the structure in DPRAM is released, because DPRAM is a premium
2942 * resource.
2943 * This shadow structure keeps a copy of what was done so that the
2944 * allocated resources can be released when the channel is freed.
2945 */
2946 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 2947 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
890de95e 2948 if (netif_msg_ifup(ugeth))
c84d8055 2949 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
ce973b14
LY		 2950 return -ENOMEM;
2951 }
2952 /* Zero out *p_init_enet_param_shadow */
2953 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 2954 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 2955
2956 /* Fill shadow InitEnet command parameter structure */
2957
2958 ugeth->p_init_enet_param_shadow->resinit1 =
2959 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2960 ugeth->p_init_enet_param_shadow->resinit2 =
2961 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2962 ugeth->p_init_enet_param_shadow->resinit3 =
2963 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2964 ugeth->p_init_enet_param_shadow->resinit4 =
2965 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2966 ugeth->p_init_enet_param_shadow->resinit5 =
2967 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2968 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2969 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2970 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2971 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2972
2973 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2974 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2975 if ((ug_info->largestexternallookupkeysize !=
8e95a202
JP		 2976 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2977 (ug_info->largestexternallookupkeysize !=
2978 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2979 (ug_info->largestexternallookupkeysize !=
2980 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
890de95e 2981 if (netif_msg_ifup(ugeth))
c84d8055 2982 pr_err("Invalid largest External Lookup Key Size\n");
ce973b14
LY		 2983 return -EINVAL;
2984 }
2985 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2986 ug_info->largestexternallookupkeysize;
18a8e864 2987 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 2988 if (ug_info->rxExtendedFiltering) {
2989 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2990 if (ug_info->largestexternallookupkeysize ==
8844a006 2991 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
ce973b14
LY		 2992 size +=
2993 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2994 if (ug_info->largestexternallookupkeysize ==
8844a006 2995 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
ce973b14
LY		 2996 size +=
2997 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2998 }
2999
3000 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3001 p_init_enet_param_shadow->rxthread[0]),
3002 (u8) (numThreadsRxNumerical + 1)
3003 /* Rx needs one extra for terminator */
3004 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3005 ug_info->riscRx, 1)) != 0) {
890de95e 3006 if (netif_msg_ifup(ugeth))
c84d8055 3007 pr_err("Can not fill p_init_enet_param_shadow\n");
ce973b14
LY		 3008 return ret_val;
3009 }
3010
3011 ugeth->p_init_enet_param_shadow->txglobal =
3012 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3013 if ((ret_val =
3014 fill_init_enet_entries(ugeth,
3015 &(ugeth->p_init_enet_param_shadow->
3016 txthread[0]), numThreadsTxNumerical,
18a8e864 3017 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 3018 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3019 ug_info->riscTx, 0)) != 0) {
890de95e 3020 if (netif_msg_ifup(ugeth))
c84d8055 3021 pr_err("Can not fill p_init_enet_param_shadow\n");
ce973b14
LY		 3022 return ret_val;
3023 }
3024
3025 /* Load Rx bds with buffers */
3026 for (i = 0; i < ug_info->numQueuesRx; i++) {
3027 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
890de95e 3028 if (netif_msg_ifup(ugeth))
c84d8055 3029 pr_err("Can not fill Rx bds with buffers\n");
ce973b14
LY		 3030 return ret_val;
3031 }
3032 }
3033
3034 /* Allocate InitEnet command parameter structure */
18a8e864 3035 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
4c35630c 3036 if (IS_ERR_VALUE(init_enet_pram_offset)) {
890de95e 3037 if (netif_msg_ifup(ugeth))
c84d8055 3038 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
ce973b14
LY		 3039 return -ENOMEM;
3040 }
3041 p_init_enet_pram =
6fee40e9 3042 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3043
3044 /* Copy shadow InitEnet command parameter structure into PRAM */
6fee40e9
AF		 3045 out_8(&p_init_enet_pram->resinit1,
3046 ugeth->p_init_enet_param_shadow->resinit1);
3047 out_8(&p_init_enet_pram->resinit2,
3048 ugeth->p_init_enet_param_shadow->resinit2);
3049 out_8(&p_init_enet_pram->resinit3,
3050 ugeth->p_init_enet_param_shadow->resinit3);
3051 out_8(&p_init_enet_pram->resinit4,
3052 ugeth->p_init_enet_param_shadow->resinit4);
ce973b14
LY		 3053 out_be16(&p_init_enet_pram->resinit5,
3054 ugeth->p_init_enet_param_shadow->resinit5);
6fee40e9
AF		 3055 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3056 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
ce973b14
LY		 3057 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3058 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3059 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3060 out_be32(&p_init_enet_pram->rxthread[i],
3061 ugeth->p_init_enet_param_shadow->rxthread[i]);
3062 out_be32(&p_init_enet_pram->txglobal,
3063 ugeth->p_init_enet_param_shadow->txglobal);
3064 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3065 out_be32(&p_init_enet_pram->txthread[i],
3066 ugeth->p_init_enet_param_shadow->txthread[i]);
3067
3068 /* Issue QE command */
3069 cecr_subblock =
3070 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3071 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3072 init_enet_pram_offset);
3073
3074 /* Free InitEnet command parameter */
3075 qe_muram_free(init_enet_pram_offset);
3076
3077 return 0;
3078}
3079
ce973b14
LY		 3080/* This is called by the kernel when a frame is ready for transmission. */
3081/* It is pointed to by the dev->hard_start_xmit function pointer */
3082static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3083{
18a8e864 3084 struct ucc_geth_private *ugeth = netdev_priv(dev);
d5b9049d
MR		 3085#ifdef CONFIG_UGETH_TX_ON_DEMAND
3086 struct ucc_fast_private *uccf;
3087#endif
6fee40e9 3088 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3089 u32 bd_status;
3090 u8 txQ = 0;
22580f89 3091 unsigned long flags;
ce973b14 3092
b39d66a8 3093 ugeth_vdbg("%s: IN", __func__);
ce973b14 3094
22580f89 3095 spin_lock_irqsave(&ugeth->lock, flags);
ce973b14 3096
09f75cd7 3097 dev->stats.tx_bytes += skb->len;
ce973b14
LY		 3098
3099 /* Start from the next BD that should be filled */
3100 bd = ugeth->txBd[txQ];
6fee40e9 3101 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3102 /* Save the skb pointer so we can free it later */
3103 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3104
3105 /* Update the current skb pointer (wrapping if this was the last) */
3106 ugeth->skb_curtx[txQ] =
3107 (ugeth->skb_curtx[txQ] +
3108 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3109
3110 /* set up the buffer descriptor */
6fee40e9 3111 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 3112 dma_map_single(ugeth->dev, skb->data,
7f80202b 3113 skb->len, DMA_TO_DEVICE));
ce973b14 3114
18a8e864 3115 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3116
3117 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3118
18a8e864 3119 /* set bd status and length */
6fee40e9 3120 out_be32((u32 __iomem *)bd, bd_status);
ce973b14 3121
ce973b14
LY		 3122 /* Move to next BD in the ring */
3123 if (!(bd_status & T_W))
a394f013 3124 bd += sizeof(struct qe_bd);
ce973b14 3125 else
a394f013 3126 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3127
3128 /* If the next BD still needs to be cleaned up, then the bds
3129 are full. We need to tell the kernel to stop sending us stuff. */
3130 if (bd == ugeth->confBd[txQ]) {
3131 if (!netif_queue_stopped(dev))
3132 netif_stop_queue(dev);
3133 }
3134
a394f013
LY		 3135 ugeth->txBd[txQ] = bd;
3136
d13d6bff
RC		 3137 skb_tx_timestamp(skb);
3138
ce973b14
LY		 3139 if (ugeth->p_scheduler) {
3140 ugeth->cpucount[txQ]++;
3141 /* Indicate to QE that there are more Tx bds ready for
3142 transmission */
3143 /* This is done by writing a running counter of the bd
3144 count to the scheduler PRAM. */
3145 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3146 }
3147
d5b9049d
MR		 3148#ifdef CONFIG_UGETH_TX_ON_DEMAND
3149 uccf = ugeth->uccf;
3150 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3151#endif
22580f89 3152 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14 3153
6ed10654 3154 return NETDEV_TX_OK;
ce973b14
LY		 3155}
3156
18a8e864 3157static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3158{
3159 struct sk_buff *skb;
6fee40e9 3160 u8 __iomem *bd;
ce973b14
LY		 3161 u16 length, howmany = 0;
3162 u32 bd_status;
3163 u8 *bdBuffer;
4b8fdefa 3164 struct net_device *dev;
ce973b14 3165
b39d66a8 3166 ugeth_vdbg("%s: IN", __func__);
ce973b14 3167
da1aa63e 3168 dev = ugeth->ndev;
88a15f2e 3169
ce973b14
LY		 3170 /* collect received buffers */
3171 bd = ugeth->rxBd[rxQ];
3172
6fee40e9 3173 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3174
3175 /* while there are received buffers and BD is full (~R_E) */
3176 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
6fee40e9 3177 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
ce973b14
LY		 3178 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3179 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3180
3181 /* determine whether buffer is first, last, first and last
3182 (single buffer frame) or middle (not first and not last) */
3183 if (!skb ||
3184 (!(bd_status & (R_F | R_L))) ||
3185 (bd_status & R_ERRORS_FATAL)) {
890de95e 3186 if (netif_msg_rx_err(ugeth))
c84d8055
JP		 3187 pr_err("%d: ERROR!!! skb - 0x%08x\n",
3188 __LINE__, (u32)skb);
66eef59f 3189 dev_kfree_skb(skb);
ce973b14
LY		 3190
3191 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
09f75cd7 3192 dev->stats.rx_dropped++;
ce973b14 3193 } else {
09f75cd7 3194 dev->stats.rx_packets++;
ce973b14
LY		 3195 howmany++;
3196
3197 /* Prep the skb for the packet */
3198 skb_put(skb, length);
3199
3200 /* Tell the skb what kind of packet this is */
da1aa63e 3201 skb->protocol = eth_type_trans(skb, ugeth->ndev);
ce973b14 3202
09f75cd7 3203 dev->stats.rx_bytes += length;
ce973b14 3204 /* Send the packet up the stack */
ce973b14 3205 netif_receive_skb(skb);
ce973b14
LY		 3206 }
3207
ce973b14
LY		 3208 skb = get_new_skb(ugeth, bd);
3209 if (!skb) {
890de95e 3210 if (netif_msg_rx_err(ugeth))
c84d8055 3211 pr_warn("No Rx Data Buffer\n");
09f75cd7 3212 dev->stats.rx_dropped++;
ce973b14
LY		 3213 break;
3214 }
3215
3216 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3217
3218 /* update to point at the next skb */
3219 ugeth->skb_currx[rxQ] =
3220 (ugeth->skb_currx[rxQ] +
3221 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3222
3223 if (bd_status & R_W)
3224 bd = ugeth->p_rx_bd_ring[rxQ];
3225 else
18a8e864 3226 bd += sizeof(struct qe_bd);
ce973b14 3227
6fee40e9 3228 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3229 }
3230
3231 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3232 return howmany;
3233}
3234
3235static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3236{
3237 /* Start from the next BD that should be filled */
18a8e864 3238 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9 3239 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3240 u32 bd_status;
3241
3242 bd = ugeth->confBd[txQ];
6fee40e9 3243 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3244
3245 /* Normal processing. */
3246 while ((bd_status & T_R) == 0) {
50f238fd
AV		 3247 struct sk_buff *skb;
3248
ce973b14
LY		 3249 /* BD contains already transmitted buffer. */
3250 /* Handle the transmitted buffer and release */
3251 /* the BD to be used with the current frame */
3252
34692421
JW		 3253 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3254 if (!skb)
ce973b14
LY		 3255 break;
3256
09f75cd7 3257 dev->stats.tx_packets++;
ce973b14 3258
36145741 3259 dev_consume_skb_any(skb);
50f238fd 3260
ce973b14
LY		 3261 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3262 ugeth->skb_dirtytx[txQ] =
3263 (ugeth->skb_dirtytx[txQ] +
3264 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3265
3266 /* We freed a buffer, so now we can restart transmission */
3267 if (netif_queue_stopped(dev))
3268 netif_wake_queue(dev);
3269
3270 /* Advance the confirmation BD pointer */
3271 if (!(bd_status & T_W))
a394f013 3272 bd += sizeof(struct qe_bd);
ce973b14 3273 else
a394f013 3274 bd = ugeth->p_tx_bd_ring[txQ];
6fee40e9 3275 bd_status = in_be32((u32 __iomem *)bd);
ce973b14 3276 }
a394f013 3277 ugeth->confBd[txQ] = bd;
ce973b14
LY		 3278 return 0;
3279}
3280
bea3348e 3281static int ucc_geth_poll(struct napi_struct *napi, int budget)
ce973b14 3282{
bea3348e 3283 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
702ff12c 3284 struct ucc_geth_info *ug_info;
bea3348e 3285 int howmany, i;
ce973b14 3286
702ff12c
MR		 3287 ug_info = ugeth->ug_info;
3288
0cededf3
JT		 3289 /* Tx event processing */
3290 spin_lock(&ugeth->lock);
3291 for (i = 0; i < ug_info->numQueuesTx; i++)
3292 ucc_geth_tx(ugeth->ndev, i);
3293 spin_unlock(&ugeth->lock);
3294
50f238fd
AV		 3295 howmany = 0;
3296 for (i = 0; i < ug_info->numQueuesRx; i++)
3297 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3298
bea3348e 3299 if (howmany < budget) {
288379f0 3300 napi_complete(napi);
0cededf3 3301 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3302 }
ce973b14 3303
bea3348e 3304 return howmany;
ce973b14 3305}
ce973b14 3306
7d12e780 3307static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14 3308{
06efcad0 3309 struct net_device *dev = info;
18a8e864
LY		 3310 struct ucc_geth_private *ugeth = netdev_priv(dev);
3311 struct ucc_fast_private *uccf;
3312 struct ucc_geth_info *ug_info;
702ff12c
MR		 3313 register u32 ucce;
3314 register u32 uccm;
ce973b14 3315
b39d66a8 3316 ugeth_vdbg("%s: IN", __func__);
ce973b14 3317
ce973b14
LY		 3318 uccf = ugeth->uccf;
3319 ug_info = ugeth->ug_info;
3320
702ff12c
MR		 3321 /* read and clear events */
3322 ucce = (u32) in_be32(uccf->p_ucce);
3323 uccm = (u32) in_be32(uccf->p_uccm);
3324 ucce &= uccm;
3325 out_be32(uccf->p_ucce, ucce);
ce973b14 3326
702ff12c 3327 /* check for receive events that require processing */
0cededf3 3328 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
288379f0 3329 if (napi_schedule_prep(&ugeth->napi)) {
0cededf3 3330 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3331 out_be32(uccf->p_uccm, uccm);
288379f0 3332 __napi_schedule(&ugeth->napi);
702ff12c 3333 }
702ff12c 3334 }
ce973b14 3335
702ff12c
MR		 3336 /* Errors and other events */
3337 if (ucce & UCCE_OTHER) {
3bc53427 3338 if (ucce & UCC_GETH_UCCE_BSY)
09f75cd7 3339 dev->stats.rx_errors++;
3bc53427 3340 if (ucce & UCC_GETH_UCCE_TXE)
09f75cd7 3341 dev->stats.tx_errors++;
ce973b14 3342 }
ce973b14
LY		 3343
3344 return IRQ_HANDLED;
3345}
3346
26d29ea7
AV		 3347#ifdef CONFIG_NET_POLL_CONTROLLER
3348/*
3349 * Polling 'interrupt' - used by things like netconsole to send skbs
3350 * without having to re-enable interrupts. It's not called while
3351 * the interrupt routine is executing.
3352 */
3353static void ucc_netpoll(struct net_device *dev)
3354{
3355 struct ucc_geth_private *ugeth = netdev_priv(dev);
3356 int irq = ugeth->ug_info->uf_info.irq;
3357
3358 disable_irq(irq);
3359 ucc_geth_irq_handler(irq, dev);
3360 enable_irq(irq);
3361}
3362#endif /* CONFIG_NET_POLL_CONTROLLER */
3363
3d6593e9
KH		 3364static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3365{
3366 struct ucc_geth_private *ugeth = netdev_priv(dev);
3367 struct sockaddr *addr = p;
3368
3369 if (!is_valid_ether_addr(addr->sa_data))
3370 return -EADDRNOTAVAIL;
3371
3372 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3373
3374 /*
3375 * If device is not running, we will set mac addr register
3376 * when opening the device.
3377 */
3378 if (!netif_running(dev))
3379 return 0;
3380
3381 spin_lock_irq(&ugeth->lock);
3382 init_mac_station_addr_regs(dev->dev_addr[0],
3383 dev->dev_addr[1],
3384 dev->dev_addr[2],
3385 dev->dev_addr[3],
3386 dev->dev_addr[4],
3387 dev->dev_addr[5],
3388 &ugeth->ug_regs->macstnaddr1,
3389 &ugeth->ug_regs->macstnaddr2);
3390 spin_unlock_irq(&ugeth->lock);
3391
3392 return 0;
3393}
3394
54b15983 3395static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
ce973b14 3396{
54b15983 3397 struct net_device *dev = ugeth->ndev;
ce973b14
LY		 3398 int err;
3399
728de4c9
KP		 3400 err = ucc_struct_init(ugeth);
3401 if (err) {
c84d8055 3402 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
54b15983 3403 goto err;
728de4c9
KP		 3404 }
3405
ce973b14
LY		 3406 err = ucc_geth_startup(ugeth);
3407 if (err) {
c84d8055 3408 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
54b15983 3409 goto err;
ce973b14
LY		 3410 }
3411
3412 err = adjust_enet_interface(ugeth);
3413 if (err) {
c84d8055 3414 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
54b15983 3415 goto err;
ce973b14
LY		 3416 }
3417
3418 /* Set MACSTNADDR1, MACSTNADDR2 */
3419 /* For more details see the hardware spec. */
3420 init_mac_station_addr_regs(dev->dev_addr[0],
3421 dev->dev_addr[1],
3422 dev->dev_addr[2],
3423 dev->dev_addr[3],
3424 dev->dev_addr[4],
3425 dev->dev_addr[5],
3426 &ugeth->ug_regs->macstnaddr1,
3427 &ugeth->ug_regs->macstnaddr2);
3428
67c2fb8f 3429 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
ce973b14 3430 if (err) {
c84d8055 3431 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n");
54b15983
AV		 3432 goto err;
3433 }
3434
3435 return 0;
3436err:
3437 ucc_geth_stop(ugeth);
3438 return err;
3439}
3440
3441/* Called when something needs to use the ethernet device */
3442/* Returns 0 for success. */
3443static int ucc_geth_open(struct net_device *dev)
3444{
3445 struct ucc_geth_private *ugeth = netdev_priv(dev);
3446 int err;
3447
3448 ugeth_vdbg("%s: IN", __func__);
3449
3450 /* Test station address */
3451 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
c84d8055
JP		 3452 netif_err(ugeth, ifup, dev,
3453 "Multicast address used for station address - is this what you wanted?\n");
54b15983
AV		 3454 return -EINVAL;
3455 }
3456
3457 err = init_phy(dev);
3458 if (err) {
c84d8055 3459 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n");
54b15983
AV		 3460 return err;
3461 }
3462
3463 err = ucc_geth_init_mac(ugeth);
3464 if (err) {
c84d8055 3465 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
54b15983 3466 goto err;
ce973b14 3467 }
ce973b14 3468
67c2fb8f
AV		 3469 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3470 0, "UCC Geth", dev);
ce973b14 3471 if (err) {
c84d8055 3472 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
54b15983 3473 goto err;
ce973b14
LY		 3474 }
3475
54b15983
AV		 3476 phy_start(ugeth->phydev);
3477 napi_enable(&ugeth->napi);
ce973b14
LY		 3478 netif_start_queue(dev);
3479
2394905f
AV		 3480 device_set_wakeup_capable(&dev->dev,
3481 qe_alive_during_sleep() || ugeth->phydev->irq);
3482 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3483
ce973b14 3484 return err;
bea3348e 3485
54b15983 3486err:
ba574696 3487 ucc_geth_stop(ugeth);
bea3348e 3488 return err;
ce973b14
LY		 3489}
3490
3491/* Stops the kernel queue, and halts the controller */
3492static int ucc_geth_close(struct net_device *dev)
3493{
18a8e864 3494 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14 3495
b39d66a8 3496 ugeth_vdbg("%s: IN", __func__);
ce973b14 3497
bea3348e 3498 napi_disable(&ugeth->napi);
bea3348e 3499
2040bd57 3500 cancel_work_sync(&ugeth->timeout_work);
ce973b14 3501 ucc_geth_stop(ugeth);
2040bd57
JT		 3502 phy_disconnect(ugeth->phydev);
3503 ugeth->phydev = NULL;
ce973b14 3504
da1aa63e 3505 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
67c2fb8f 3506
ce973b14
LY		 3507 netif_stop_queue(dev);
3508
3509 return 0;
3510}
3511
fdb614c2
AV		 3512/* Reopen device. This will reset the MAC and PHY. */
3513static void ucc_geth_timeout_work(struct work_struct *work)
3514{
3515 struct ucc_geth_private *ugeth;
3516 struct net_device *dev;
3517
3518 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
da1aa63e 3519 dev = ugeth->ndev;
fdb614c2
AV		 3520
3521 ugeth_vdbg("%s: IN", __func__);
3522
3523 dev->stats.tx_errors++;
3524
3525 ugeth_dump_regs(ugeth);
3526
3527 if (dev->flags & IFF_UP) {
3528 /*
3529 * Must reset MAC *and* PHY. This is done by reopening
3530 * the device.
3531 */
2040bd57
JT		 3532 netif_tx_stop_all_queues(dev);
3533 ucc_geth_stop(ugeth);
3534 ucc_geth_init_mac(ugeth);
3535 /* Must start PHY here */
3536 phy_start(ugeth->phydev);
3537 netif_tx_start_all_queues(dev);
fdb614c2
AV		 3538 }
3539
3540 netif_tx_schedule_all(dev);
3541}
3542
3543/*
3544 * ucc_geth_timeout gets called when a packet has not been
3545 * transmitted after a set amount of time.
3546 */
3547static void ucc_geth_timeout(struct net_device *dev)
3548{
3549 struct ucc_geth_private *ugeth = netdev_priv(dev);
3550
fdb614c2
AV		 3551 schedule_work(&ugeth->timeout_work);
3552}
3553
2394905f
AV		 3554
3555#ifdef CONFIG_PM
3556
2dc11581 3557static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
2394905f 3558{
8513fbd8 3559 struct net_device *ndev = platform_get_drvdata(ofdev);
2394905f
AV		 3560 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3561
3562 if (!netif_running(ndev))
3563 return 0;
3564
29fb00e0 3565 netif_device_detach(ndev);
2394905f
AV		 3566 napi_disable(&ugeth->napi);
3567
3568 /*
3569 * Disable the controller, otherwise we'll wakeup on any network
3570 * activity.
3571 */
3572 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3573
3574 if (ugeth->wol_en & WAKE_MAGIC) {
3575 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3576 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3577 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3578 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3579 phy_stop(ugeth->phydev);
3580 }
3581
3582 return 0;
3583}
3584
2dc11581 3585static int ucc_geth_resume(struct platform_device *ofdev)
2394905f 3586{
8513fbd8 3587 struct net_device *ndev = platform_get_drvdata(ofdev);
2394905f
AV		 3588 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3589 int err;
3590
3591 if (!netif_running(ndev))
3592 return 0;
3593
3594 if (qe_alive_during_sleep()) {
3595 if (ugeth->wol_en & WAKE_MAGIC) {
3596 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3597 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3598 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3599 }
3600 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3601 } else {
3602 /*
3603 * Full reinitialization is required if QE shuts down
3604 * during sleep.
3605 */
3606 ucc_geth_memclean(ugeth);
3607
3608 err = ucc_geth_init_mac(ugeth);
3609 if (err) {
c84d8055 3610 netdev_err(ndev, "Cannot initialize MAC, aborting\n");
2394905f
AV		 3611 return err;
3612 }
3613 }
3614
3615 ugeth->oldlink = 0;
3616 ugeth->oldspeed = 0;
3617 ugeth->oldduplex = -1;
3618
3619 phy_stop(ugeth->phydev);
3620 phy_start(ugeth->phydev);
3621
3622 napi_enable(&ugeth->napi);
29fb00e0 3623 netif_device_attach(ndev);
2394905f
AV		 3624
3625 return 0;
3626}
3627
3628#else
3629#define ucc_geth_suspend NULL
3630#define ucc_geth_resume NULL
3631#endif
3632
4e19b5c1 3633static phy_interface_t to_phy_interface(const char *phy_connection_type)
728de4c9 3634{
4e19b5c1 3635 if (strcasecmp(phy_connection_type, "mii") == 0)
728de4c9 3636 return PHY_INTERFACE_MODE_MII;
4e19b5c1 3637 if (strcasecmp(phy_connection_type, "gmii") == 0)
728de4c9 3638 return PHY_INTERFACE_MODE_GMII;
4e19b5c1 3639 if (strcasecmp(phy_connection_type, "tbi") == 0)
728de4c9 3640 return PHY_INTERFACE_MODE_TBI;
4e19b5c1 3641 if (strcasecmp(phy_connection_type, "rmii") == 0)
728de4c9 3642 return PHY_INTERFACE_MODE_RMII;
4e19b5c1 3643 if (strcasecmp(phy_connection_type, "rgmii") == 0)
728de4c9 3644 return PHY_INTERFACE_MODE_RGMII;
4e19b5c1 3645 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
728de4c9 3646 return PHY_INTERFACE_MODE_RGMII_ID;
bd0ceaab
KP		 3647 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3648 return PHY_INTERFACE_MODE_RGMII_TXID;
3649 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3650 return PHY_INTERFACE_MODE_RGMII_RXID;
4e19b5c1 3651 if (strcasecmp(phy_connection_type, "rtbi") == 0)
728de4c9 3652 return PHY_INTERFACE_MODE_RTBI;
047584ce
HW		 3653 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3654 return PHY_INTERFACE_MODE_SGMII;
728de4c9
KP		 3655
3656 return PHY_INTERFACE_MODE_MII;
3657}
3658
d19b5149
SM		 3659static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3660{
3661 struct ucc_geth_private *ugeth = netdev_priv(dev);
3662
3663 if (!netif_running(dev))
3664 return -EINVAL;
3665
3666 if (!ugeth->phydev)
3667 return -ENODEV;
3668
28b04113 3669 return phy_mii_ioctl(ugeth->phydev, rq, cmd);
d19b5149
SM		 3670}
3671
a9dbae78
JT		 3672static const struct net_device_ops ucc_geth_netdev_ops = {
3673 .ndo_open = ucc_geth_open,
3674 .ndo_stop = ucc_geth_close,
3675 .ndo_start_xmit = ucc_geth_start_xmit,
3676 .ndo_validate_addr = eth_validate_addr,
3d6593e9 3677 .ndo_set_mac_address = ucc_geth_set_mac_addr,
a9dbae78 3678 .ndo_change_mtu = eth_change_mtu,
afc4b13d 3679 .ndo_set_rx_mode = ucc_geth_set_multi,
a9dbae78 3680 .ndo_tx_timeout = ucc_geth_timeout,
d19b5149 3681 .ndo_do_ioctl = ucc_geth_ioctl,
a9dbae78
JT		 3682#ifdef CONFIG_NET_POLL_CONTROLLER
3683 .ndo_poll_controller = ucc_netpoll,
3684#endif
3685};
3686
74888760 3687static int ucc_geth_probe(struct platform_device* ofdev)
ce973b14 3688{
18a8e864 3689 struct device *device = &ofdev->dev;
61c7a080 3690 struct device_node *np = ofdev->dev.of_node;
ce973b14
LY		 3691 struct net_device *dev = NULL;
3692 struct ucc_geth_private *ugeth = NULL;
3693 struct ucc_geth_info *ug_info;
18a8e864 3694 struct resource res;
728de4c9 3695 int err, ucc_num, max_speed = 0;
18a8e864 3696 const unsigned int *prop;
9fb1e350 3697 const char *sprop;
9b4c7a4e 3698 const void *mac_addr;
728de4c9
KP		 3699 phy_interface_t phy_interface;
3700 static const int enet_to_speed[] = {
3701 SPEED_10, SPEED_10, SPEED_10,
3702 SPEED_100, SPEED_100, SPEED_100,
3703 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3704 };
3705 static const phy_interface_t enet_to_phy_interface[] = {
3706 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3707 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3708 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3709 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3710 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
047584ce 3711 PHY_INTERFACE_MODE_SGMII,
728de4c9 3712 };
ce973b14 3713
b39d66a8 3714 ugeth_vdbg("%s: IN", __func__);
ce973b14 3715
56626f33
AV		 3716 prop = of_get_property(np, "cell-index", NULL);
3717 if (!prop) {
3718 prop = of_get_property(np, "device-id", NULL);
3719 if (!prop)
3720 return -ENODEV;
3721 }
3722
18a8e864
LY		 3723 ucc_num = *prop - 1;
3724 if ((ucc_num < 0) || (ucc_num > 7))
3725 return -ENODEV;
3726
3727 ug_info = &ugeth_info[ucc_num];
890de95e
LY		 3728 if (ug_info == NULL) {
3729 if (netif_msg_probe(&debug))
c84d8055 3730 pr_err("[%d] Missing additional data!\n", ucc_num);
890de95e
LY		 3731 return -ENODEV;
3732 }
3733
18a8e864 3734 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3735
9fb1e350
TT		 3736 sprop = of_get_property(np, "rx-clock-name", NULL);
3737 if (sprop) {
3738 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3739 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3740 (ug_info->uf_info.rx_clock > QE_CLK24)) {
c84d8055 3741 pr_err("invalid rx-clock-name property\n");
9fb1e350
TT		 3742 return -EINVAL;
3743 }
3744 } else {
3745 prop = of_get_property(np, "rx-clock", NULL);
3746 if (!prop) {
3747 /* If both rx-clock-name and rx-clock are missing,
3748 we want to tell people to use rx-clock-name. */
c84d8055 3749 pr_err("missing rx-clock-name property\n");
9fb1e350
TT		 3750 return -EINVAL;
3751 }
3752 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
c84d8055 3753 pr_err("invalid rx-clock propperty\n");
9fb1e350
TT		 3754 return -EINVAL;
3755 }
3756 ug_info->uf_info.rx_clock = *prop;
3757 }
3758
3759 sprop = of_get_property(np, "tx-clock-name", NULL);
3760 if (sprop) {
3761 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3762 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3763 (ug_info->uf_info.tx_clock > QE_CLK24)) {
c84d8055 3764 pr_err("invalid tx-clock-name property\n");
9fb1e350
TT		 3765 return -EINVAL;
3766 }
3767 } else {
e410553f 3768 prop = of_get_property(np, "tx-clock", NULL);
9fb1e350 3769 if (!prop) {
c84d8055 3770 pr_err("missing tx-clock-name property\n");
9fb1e350
TT		 3771 return -EINVAL;
3772 }
3773 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
c84d8055 3774 pr_err("invalid tx-clock property\n");
9fb1e350
TT		 3775 return -EINVAL;
3776 }
3777 ug_info->uf_info.tx_clock = *prop;
3778 }
3779
18a8e864
LY		 3780 err = of_address_to_resource(np, 0, &res);
3781 if (err)
3782 return -EINVAL;
3783
3784 ug_info->uf_info.regs = res.start;
3785 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3104a6ff
AV		 3786
3787 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
a1f7d81b
UKK		 3788 if (!ug_info->phy_node && of_phy_is_fixed_link(np)) {
3789 /*
3790 * In the case of a fixed PHY, the DT node associated
87009814
FF		 3791 * to the PHY is the Ethernet MAC DT node.
3792 */
a1f7d81b
UKK		 3793 err = of_phy_register_fixed_link(np);
3794 if (err)
3795 return err;
f1f02fa4 3796 ug_info->phy_node = of_node_get(np);
87009814 3797 }
728de4c9 3798
fb1001f3
HW		 3799 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3800 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3801
728de4c9 3802 /* get the phy interface type, or default to MII */
4e19b5c1 3803 prop = of_get_property(np, "phy-connection-type", NULL);
728de4c9
KP		 3804 if (!prop) {
3805 /* handle interface property present in old trees */
3104a6ff 3806 prop = of_get_property(ug_info->phy_node, "interface", NULL);
4e19b5c1 3807 if (prop != NULL) {
728de4c9 3808 phy_interface = enet_to_phy_interface[*prop];
4e19b5c1
KP		 3809 max_speed = enet_to_speed[*prop];
3810 } else
728de4c9
KP		 3811 phy_interface = PHY_INTERFACE_MODE_MII;
3812 } else {
3813 phy_interface = to_phy_interface((const char *)prop);
3814 }
3815
4e19b5c1
KP		 3816 /* get speed, or derive from PHY interface */
3817 if (max_speed == 0)
728de4c9
KP		 3818 switch (phy_interface) {
3819 case PHY_INTERFACE_MODE_GMII:
3820 case PHY_INTERFACE_MODE_RGMII:
3821 case PHY_INTERFACE_MODE_RGMII_ID:
bd0ceaab
KP		 3822 case PHY_INTERFACE_MODE_RGMII_RXID:
3823 case PHY_INTERFACE_MODE_RGMII_TXID:
728de4c9
KP		 3824 case PHY_INTERFACE_MODE_TBI:
3825 case PHY_INTERFACE_MODE_RTBI:
047584ce 3826 case PHY_INTERFACE_MODE_SGMII:
728de4c9
KP		 3827 max_speed = SPEED_1000;
3828 break;
3829 default:
3830 max_speed = SPEED_100;
3831 break;
3832 }
728de4c9
KP		 3833
3834 if (max_speed == SPEED_1000) {
fa1b42b4
DL		 3835 unsigned int snums = qe_get_num_of_snums();
3836
4e19b5c1 3837 /* configure muram FIFOs for gigabit operation */
728de4c9
KP		 3838 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3839 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3840 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3841 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3842 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3843 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ffea31ed 3844 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
674e4f93 3845
fa1b42b4 3846 /* If QE's snum number is 46/76 which means we need to support
674e4f93
HW		 3847 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3848 * more Threads to Rx.
3849 */
fa1b42b4 3850 if ((snums == 76) || (snums == 46))
674e4f93
HW		 3851 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3852 else
3853 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
728de4c9
KP		 3854 }
3855
890de95e 3856 if (netif_msg_probe(&debug))
c84d8055 3857 pr_info("UCC%1d at 0x%8x (irq = %d)\n",
890de95e
LY		 3858 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3859 ug_info->uf_info.irq);
ce973b14 3860
ce973b14
LY		 3861 /* Create an ethernet device instance */
3862 dev = alloc_etherdev(sizeof(*ugeth));
3863
fa310789
UKK		 3864 if (dev == NULL) {
3865 of_node_put(ug_info->tbi_node);
3866 of_node_put(ug_info->phy_node);
ce973b14 3867 return -ENOMEM;
fa310789 3868 }
ce973b14
LY		 3869
3870 ugeth = netdev_priv(dev);
3871 spin_lock_init(&ugeth->lock);
3872
80a9fad8
AV		 3873 /* Create CQs for hash tables */
3874 INIT_LIST_HEAD(&ugeth->group_hash_q);
3875 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3876
ce973b14
LY		 3877 dev_set_drvdata(device, dev);
3878
3879 /* Set the dev->base_addr to the gfar reg region */
3880 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3881
ce973b14
LY		 3882 SET_NETDEV_DEV(dev, device);
3883
3884 /* Fill in the dev structure */
ac421852 3885 uec_set_ethtool_ops(dev);
a9dbae78 3886 dev->netdev_ops = &ucc_geth_netdev_ops;
ce973b14 3887 dev->watchdog_timeo = TX_TIMEOUT;
1762a29a 3888 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
0cededf3 3889 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
ce973b14 3890 dev->mtu = 1500;
ce973b14 3891
890de95e 3892 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
728de4c9
KP		 3893 ugeth->phy_interface = phy_interface;
3894 ugeth->max_speed = max_speed;
3895
ce973b14
LY		 3896 err = register_netdev(dev);
3897 if (err) {
890de95e 3898 if (netif_msg_probe(ugeth))
c84d8055
JP		 3899 pr_err("%s: Cannot register net device, aborting\n",
3900 dev->name);
ce973b14 3901 free_netdev(dev);
fa310789
UKK		 3902 of_node_put(ug_info->tbi_node);
3903 of_node_put(ug_info->phy_node);
ce973b14
LY		 3904 return err;
3905 }
3906
e9eb70c9 3907 mac_addr = of_get_mac_address(np);
9b4c7a4e 3908 if (mac_addr)
d458cdf7 3909 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
ce973b14 3910
728de4c9 3911 ugeth->ug_info = ug_info;
da1aa63e
AV		 3912 ugeth->dev = device;
3913 ugeth->ndev = dev;
b1c4a9dd 3914 ugeth->node = np;
728de4c9 3915
ce973b14
LY		 3916 return 0;
3917}
3918
2dc11581 3919static int ucc_geth_remove(struct platform_device* ofdev)
ce973b14 3920{
65d7e7ad 3921 struct net_device *dev = platform_get_drvdata(ofdev);
ce973b14
LY		 3922 struct ucc_geth_private *ugeth = netdev_priv(dev);
3923
80a9fad8 3924 unregister_netdev(dev);
ce973b14 3925 free_netdev(dev);
80a9fad8 3926 ucc_geth_memclean(ugeth);
4da5e6a0
UKK		 3927 of_node_put(ugeth->ug_info->tbi_node);
3928 of_node_put(ugeth->ug_info->phy_node);
ce973b14
LY		 3929
3930 return 0;
3931}
3932
18a8e864
LY		 3933static struct of_device_id ucc_geth_match[] = {
3934 {
3935 .type = "network",
3936 .compatible = "ucc_geth",
3937 },
3938 {},
3939};
3940
3941MODULE_DEVICE_TABLE(of, ucc_geth_match);
3942
74888760 3943static struct platform_driver ucc_geth_driver = {
4018294b
GL		 3944 .driver = {
3945 .name = DRV_NAME,
4018294b
GL		 3946 .of_match_table = ucc_geth_match,
3947 },
18a8e864
LY		 3948 .probe = ucc_geth_probe,
3949 .remove = ucc_geth_remove,
2394905f
AV		 3950 .suspend = ucc_geth_suspend,
3951 .resume = ucc_geth_resume,
ce973b14
LY		 3952};
3953
3954static int __init ucc_geth_init(void)
3955{
728de4c9
KP		 3956 int i, ret;
3957
890de95e 3958 if (netif_msg_drv(&debug))
c84d8055 3959 pr_info(DRV_DESC "\n");
ce973b14
LY		 3960 for (i = 0; i < 8; i++)
3961 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3962 sizeof(ugeth_primary_info));
3963
74888760 3964 ret = platform_driver_register(&ucc_geth_driver);
728de4c9 3965
728de4c9 3966 return ret;
ce973b14
LY		 3967}
3968
3969static void __exit ucc_geth_exit(void)
3970{
74888760 3971 platform_driver_unregister(&ucc_geth_driver);
ce973b14
LY		 3972}
3973
3974module_init(ucc_geth_init);
3975module_exit(ucc_geth_exit);
3976
3977MODULE_AUTHOR("Freescale Semiconductor, Inc");
3978MODULE_DESCRIPTION(DRV_DESC);
c2bcf00b 3979MODULE_VERSION(DRV_VERSION);
ce973b14 3980MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)