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bgmac: fix "cmdcfg" calls for promisc and loopback modes
[linux-block.git] / drivers / net / ethernet / freescale / gianfar.c
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0977f817 1/* drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 2 *
3 * Gianfar Ethernet Driver
7f7f5316
AF		 4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
6c43e046 12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
a12f801d 13 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
0bbaf069 27 *
b31a1d8b
AF		 28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
0bbaf069 38 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
bb40dcbb 42 * of frames or amount of time have passed). In NAPI, the
1da177e4 43 * interrupt handler will signal there is work to be done, and
0aa1538f 44 * exit. This method will start at the last known empty
0bbaf069 45 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
59deab26
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
1da177e4 67#include <linux/kernel.h>
1da177e4
LT		 68#include <linux/string.h>
69#include <linux/errno.h>
bb40dcbb 70#include <linux/unistd.h>
1da177e4
LT		 71#include <linux/slab.h>
72#include <linux/interrupt.h>
73#include <linux/init.h>
74#include <linux/delay.h>
75#include <linux/netdevice.h>
76#include <linux/etherdevice.h>
77#include <linux/skbuff.h>
0bbaf069 78#include <linux/if_vlan.h>
1da177e4
LT		 79#include <linux/spinlock.h>
80#include <linux/mm.h>
fe192a49 81#include <linux/of_mdio.h>
b31a1d8b 82#include <linux/of_platform.h>
0bbaf069
KG		 83#include <linux/ip.h>
84#include <linux/tcp.h>
85#include <linux/udp.h>
9c07b884 86#include <linux/in.h>
cc772ab7 87#include <linux/net_tstamp.h>
1da177e4
LT		 88
89#include <asm/io.h>
7d350977 90#include <asm/reg.h>
1da177e4
LT		 91#include <asm/irq.h>
92#include <asm/uaccess.h>
93#include <linux/module.h>
1da177e4
LT		 94#include <linux/dma-mapping.h>
95#include <linux/crc32.h>
bb40dcbb
AF		 96#include <linux/mii.h>
97#include <linux/phy.h>
b31a1d8b
AF		 98#include <linux/phy_fixed.h>
99#include <linux/of.h>
4b6ba8aa 100#include <linux/of_net.h>
1da177e4
LT		 101
102#include "gianfar.h"
1da177e4
LT		 103
104#define TX_TIMEOUT (1*HZ)
1da177e4 105
7f7f5316 106const char gfar_driver_version[] = "1.3";
1da177e4 107
1da177e4
LT		 108static int gfar_enet_open(struct net_device *dev);
109static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 110static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 111static void gfar_timeout(struct net_device *dev);
112static int gfar_close(struct net_device *dev);
815b97c6 113struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 114static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
bc4598bc 115 struct sk_buff *skb);
1da177e4
LT		 116static int gfar_set_mac_address(struct net_device *dev);
117static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 118static irqreturn_t gfar_error(int irq, void *dev_id);
119static irqreturn_t gfar_transmit(int irq, void *dev_id);
120static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 121static void adjust_link(struct net_device *dev);
122static void init_registers(struct net_device *dev);
123static int init_phy(struct net_device *dev);
74888760 124static int gfar_probe(struct platform_device *ofdev);
2dc11581 125static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 126static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 127static void gfar_set_multi(struct net_device *dev);
128static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 129static void gfar_configure_serdes(struct net_device *dev);
bea3348e 130static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 131#ifdef CONFIG_NET_POLL_CONTROLLER
132static void gfar_netpoll(struct net_device *dev);
133#endif
a12f801d
SG		 134int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a 136static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
cd754a57 137 int amount_pull, struct napi_struct *napi);
7f7f5316 138void gfar_halt(struct net_device *dev);
d87eb127 139static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 140void gfar_start(struct net_device *dev);
141static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 142static void gfar_set_mac_for_addr(struct net_device *dev, int num,
143 const u8 *addr);
26ccfc37 144static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 145
1da177e4
LT		 146MODULE_AUTHOR("Freescale Semiconductor, Inc");
147MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148MODULE_LICENSE("GPL");
149
a12f801d 150static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 151 dma_addr_t buf)
152{
8a102fe0
AV		 153 u32 lstatus;
154
155 bdp->bufPtr = buf;
156
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 159 lstatus |= BD_LFLAG(RXBD_WRAP);
160
161 eieio();
162
163 bdp->lstatus = lstatus;
164}
165
8728327e 166static int gfar_init_bds(struct net_device *ndev)
826aa4a0 167{
8728327e 168 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 171 struct txbd8 *txbdp;
172 struct rxbd8 *rxbdp;
fba4ed03 173 int i, j;
a12f801d 174
fba4ed03
SG		 175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
183
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
187 txbdp->lstatus = 0;
188 txbdp->bufPtr = 0;
189 txbdp++;
190 }
8728327e 191
fba4ed03
SG		 192 /* Set the last descriptor in the ring to indicate wrap */
193 txbdp--;
194 txbdp->status |= TXBD_WRAP;
8728327e
AV		 195 }
196
fba4ed03
SG		 197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
8728327e 202
fba4ed03
SG		 203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 205
fba4ed03
SG		 206 if (skb) {
207 gfar_init_rxbdp(rx_queue, rxbdp,
208 rxbdp->bufPtr);
209 } else {
210 skb = gfar_new_skb(ndev);
211 if (!skb) {
59deab26 212 netdev_err(ndev, "Can't allocate RX buffers\n");
1eb8f7a7 213 return -ENOMEM;
fba4ed03
SG		 214 }
215 rx_queue->rx_skbuff[j] = skb;
216
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 218 }
8728327e 219
fba4ed03 220 rxbdp++;
8728327e
AV		 221 }
222
8728327e
AV		 223 }
224
225 return 0;
226}
227
228static int gfar_alloc_skb_resources(struct net_device *ndev)
229{
826aa4a0 230 void *vaddr;
fba4ed03
SG		 231 dma_addr_t addr;
232 int i, j, k;
826aa4a0
AV		 233 struct gfar_private *priv = netdev_priv(ndev);
234 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
237
fba4ed03
SG		 238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
241
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 245
246 /* Allocate memory for the buffer descriptors */
8728327e 247 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 248 sizeof(struct txbd8) * priv->total_tx_ring_size +
249 sizeof(struct rxbd8) * priv->total_rx_ring_size,
250 &addr, GFP_KERNEL);
826aa4a0 251 if (!vaddr) {
59deab26
JP		 252 netif_err(priv, ifup, ndev,
253 "Could not allocate buffer descriptors!\n");
826aa4a0
AV		 254 return -ENOMEM;
255 }
256
fba4ed03
SG		 257 for (i = 0; i < priv->num_tx_queues; i++) {
258 tx_queue = priv->tx_queue[i];
43d620c8 259 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 260 tx_queue->tx_bd_dma_base = addr;
261 tx_queue->dev = ndev;
262 /* enet DMA only understands physical addresses */
bc4598bc
JC		 263 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
264 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
fba4ed03 265 }
826aa4a0 266
826aa4a0 267 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 268 for (i = 0; i < priv->num_rx_queues; i++) {
269 rx_queue = priv->rx_queue[i];
43d620c8 270 rx_queue->rx_bd_base = vaddr;
fba4ed03
SG		 271 rx_queue->rx_bd_dma_base = addr;
272 rx_queue->dev = ndev;
bc4598bc
JC		 273 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
274 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
fba4ed03 275 }
826aa4a0
AV		 276
277 /* Setup the skbuff rings */
fba4ed03
SG		 278 for (i = 0; i < priv->num_tx_queues; i++) {
279 tx_queue = priv->tx_queue[i];
280 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
bc4598bc
JC		 281 tx_queue->tx_ring_size,
282 GFP_KERNEL);
fba4ed03 283 if (!tx_queue->tx_skbuff) {
59deab26
JP		 284 netif_err(priv, ifup, ndev,
285 "Could not allocate tx_skbuff\n");
fba4ed03
SG		 286 goto cleanup;
287 }
826aa4a0 288
fba4ed03
SG		 289 for (k = 0; k < tx_queue->tx_ring_size; k++)
290 tx_queue->tx_skbuff[k] = NULL;
291 }
826aa4a0 292
fba4ed03
SG		 293 for (i = 0; i < priv->num_rx_queues; i++) {
294 rx_queue = priv->rx_queue[i];
295 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
bc4598bc
JC		 296 rx_queue->rx_ring_size,
297 GFP_KERNEL);
826aa4a0 298
fba4ed03 299 if (!rx_queue->rx_skbuff) {
59deab26
JP		 300 netif_err(priv, ifup, ndev,
301 "Could not allocate rx_skbuff\n");
fba4ed03
SG		 302 goto cleanup;
303 }
304
305 for (j = 0; j < rx_queue->rx_ring_size; j++)
306 rx_queue->rx_skbuff[j] = NULL;
307 }
826aa4a0 308
8728327e
AV		 309 if (gfar_init_bds(ndev))
310 goto cleanup;
826aa4a0
AV		 311
312 return 0;
313
314cleanup:
315 free_skb_resources(priv);
316 return -ENOMEM;
317}
318
fba4ed03
SG		 319static void gfar_init_tx_rx_base(struct gfar_private *priv)
320{
46ceb60c 321 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 322 u32 __iomem *baddr;
fba4ed03
SG		 323 int i;
324
325 baddr = &regs->tbase0;
bc4598bc 326 for (i = 0; i < priv->num_tx_queues; i++) {
fba4ed03 327 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
bc4598bc 328 baddr += 2;
fba4ed03
SG		 329 }
330
331 baddr = &regs->rbase0;
bc4598bc 332 for (i = 0; i < priv->num_rx_queues; i++) {
fba4ed03 333 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
bc4598bc 334 baddr += 2;
fba4ed03
SG		 335 }
336}
337
826aa4a0
AV		 338static void gfar_init_mac(struct net_device *ndev)
339{
340 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 341 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 342 u32 rctrl = 0;
343 u32 tctrl = 0;
344 u32 attrs = 0;
345
fba4ed03
SG		 346 /* write the tx/rx base registers */
347 gfar_init_tx_rx_base(priv);
32c513bc 348
826aa4a0 349 /* Configure the coalescing support */
46ceb60c 350 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 351
1ccb8389 352 if (priv->rx_filer_enable) {
fba4ed03 353 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 354 /* Program the RIR0 reg with the required distribution */
355 gfar_write(&regs->rir0, DEFAULT_RIR0);
356 }
826aa4a0 357
f5ae6279
CM		 358 /* Restore PROMISC mode */
359 if (ndev->flags & IFF_PROMISC)
360 rctrl |= RCTRL_PROM;
361
8b3afe95 362 if (ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 363 rctrl |= RCTRL_CHECKSUMMING;
364
365 if (priv->extended_hash) {
366 rctrl |= RCTRL_EXTHASH;
367
368 gfar_clear_exact_match(ndev);
369 rctrl |= RCTRL_EMEN;
370 }
371
372 if (priv->padding) {
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
375 }
376
cc772ab7
MR		 377 /* Insert receive time stamps into padding alignment bytes */
378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
379 rctrl &= ~RCTRL_PAL_MASK;
97553f7f 380 rctrl |= RCTRL_PADDING(8);
cc772ab7
MR		 381 priv->padding = 8;
382 }
383
97553f7f
MR		 384 /* Enable HW time stamping if requested from user space */
385 if (priv->hwts_rx_en)
386 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
387
87c288c6 388 if (ndev->features & NETIF_F_HW_VLAN_RX)
b852b720 389 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
826aa4a0
AV		 390
391 /* Init rctrl based on our settings */
392 gfar_write(&regs->rctrl, rctrl);
393
394 if (ndev->features & NETIF_F_IP_CSUM)
395 tctrl |= TCTRL_INIT_CSUM;
396
b98b8bab
CM		 397 if (priv->prio_sched_en)
398 tctrl |= TCTRL_TXSCHED_PRIO;
399 else {
400 tctrl |= TCTRL_TXSCHED_WRRS;
401 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
402 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
403 }
fba4ed03 404
826aa4a0
AV		 405 gfar_write(&regs->tctrl, tctrl);
406
407 /* Set the extraction length and index */
408 attrs = ATTRELI_EL(priv->rx_stash_size) |
409 ATTRELI_EI(priv->rx_stash_index);
410
411 gfar_write(&regs->attreli, attrs);
412
413 /* Start with defaults, and add stashing or locking
0977f817
JC		 414 * depending on the approprate variables
415 */
826aa4a0
AV		 416 attrs = ATTR_INIT_SETTINGS;
417
418 if (priv->bd_stash_en)
419 attrs |= ATTR_BDSTASH;
420
421 if (priv->rx_stash_size != 0)
422 attrs |= ATTR_BUFSTASH;
423
424 gfar_write(&regs->attr, attrs);
425
426 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
427 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
428 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
429}
430
a7f38041
SG		 431static struct net_device_stats *gfar_get_stats(struct net_device *dev)
432{
433 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 434 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
435 unsigned long tx_packets = 0, tx_bytes = 0;
3a2e16c8 436 int i;
a7f38041
SG		 437
438 for (i = 0; i < priv->num_rx_queues; i++) {
439 rx_packets += priv->rx_queue[i]->stats.rx_packets;
bc4598bc 440 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
a7f38041
SG		 441 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
442 }
443
444 dev->stats.rx_packets = rx_packets;
bc4598bc 445 dev->stats.rx_bytes = rx_bytes;
a7f38041
SG		 446 dev->stats.rx_dropped = rx_dropped;
447
448 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 449 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
450 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 451 }
452
bc4598bc 453 dev->stats.tx_bytes = tx_bytes;
a7f38041
SG		 454 dev->stats.tx_packets = tx_packets;
455
456 return &dev->stats;
457}
458
26ccfc37
AF		 459static const struct net_device_ops gfar_netdev_ops = {
460 .ndo_open = gfar_enet_open,
461 .ndo_start_xmit = gfar_start_xmit,
462 .ndo_stop = gfar_close,
463 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 464 .ndo_set_features = gfar_set_features,
afc4b13d 465 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 466 .ndo_tx_timeout = gfar_timeout,
467 .ndo_do_ioctl = gfar_ioctl,
a7f38041 468 .ndo_get_stats = gfar_get_stats,
240c102d
BH		 469 .ndo_set_mac_address = eth_mac_addr,
470 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 471#ifdef CONFIG_NET_POLL_CONTROLLER
472 .ndo_poll_controller = gfar_netpoll,
473#endif
474};
475
fba4ed03
SG		 476void lock_rx_qs(struct gfar_private *priv)
477{
3a2e16c8 478 int i;
fba4ed03
SG		 479
480 for (i = 0; i < priv->num_rx_queues; i++)
481 spin_lock(&priv->rx_queue[i]->rxlock);
482}
483
484void lock_tx_qs(struct gfar_private *priv)
485{
3a2e16c8 486 int i;
fba4ed03
SG		 487
488 for (i = 0; i < priv->num_tx_queues; i++)
489 spin_lock(&priv->tx_queue[i]->txlock);
490}
491
492void unlock_rx_qs(struct gfar_private *priv)
493{
3a2e16c8 494 int i;
fba4ed03
SG		 495
496 for (i = 0; i < priv->num_rx_queues; i++)
497 spin_unlock(&priv->rx_queue[i]->rxlock);
498}
499
500void unlock_tx_qs(struct gfar_private *priv)
501{
3a2e16c8 502 int i;
fba4ed03
SG		 503
504 for (i = 0; i < priv->num_tx_queues; i++)
505 spin_unlock(&priv->tx_queue[i]->txlock);
506}
507
87c288c6
JP		 508static bool gfar_is_vlan_on(struct gfar_private *priv)
509{
510 return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
511 (priv->ndev->features & NETIF_F_HW_VLAN_TX);
512}
513
7f7f5316
AF		 514/* Returns 1 if incoming frames use an FCB */
515static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 516{
87c288c6 517 return gfar_is_vlan_on(priv) ||
bc4598bc
JC		 518 (priv->ndev->features & NETIF_F_RXCSUM) ||
519 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
0bbaf069 520}
bb40dcbb 521
fba4ed03
SG		 522static void free_tx_pointers(struct gfar_private *priv)
523{
3a2e16c8 524 int i;
fba4ed03
SG		 525
526 for (i = 0; i < priv->num_tx_queues; i++)
527 kfree(priv->tx_queue[i]);
528}
529
530static void free_rx_pointers(struct gfar_private *priv)
531{
3a2e16c8 532 int i;
fba4ed03
SG		 533
534 for (i = 0; i < priv->num_rx_queues; i++)
535 kfree(priv->rx_queue[i]);
536}
537
46ceb60c
SG		 538static void unmap_group_regs(struct gfar_private *priv)
539{
3a2e16c8 540 int i;
46ceb60c
SG		 541
542 for (i = 0; i < MAXGROUPS; i++)
543 if (priv->gfargrp[i].regs)
544 iounmap(priv->gfargrp[i].regs);
545}
546
ee873fda
CM		 547static void free_gfar_dev(struct gfar_private *priv)
548{
549 int i, j;
550
551 for (i = 0; i < priv->num_grps; i++)
552 for (j = 0; j < GFAR_NUM_IRQS; j++) {
553 kfree(priv->gfargrp[i].irqinfo[j]);
554 priv->gfargrp[i].irqinfo[j] = NULL;
555 }
556
557 free_netdev(priv->ndev);
558}
559
46ceb60c
SG		 560static void disable_napi(struct gfar_private *priv)
561{
3a2e16c8 562 int i;
46ceb60c
SG		 563
564 for (i = 0; i < priv->num_grps; i++)
565 napi_disable(&priv->gfargrp[i].napi);
566}
567
568static void enable_napi(struct gfar_private *priv)
569{
3a2e16c8 570 int i;
46ceb60c
SG		 571
572 for (i = 0; i < priv->num_grps; i++)
573 napi_enable(&priv->gfargrp[i].napi);
574}
575
576static int gfar_parse_group(struct device_node *np,
bc4598bc 577 struct gfar_private *priv, const char *model)
46ceb60c 578{
5fedcc14 579 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
46ceb60c 580 u32 *queue_mask;
ee873fda
CM		 581 int i;
582
7c1e7e99
PG		 583 for (i = 0; i < GFAR_NUM_IRQS; i++) {
584 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
585 GFP_KERNEL);
586 if (!grp->irqinfo[i])
ee873fda 587 return -ENOMEM;
ee873fda 588 }
46ceb60c 589
5fedcc14
CM		 590 grp->regs = of_iomap(np, 0);
591 if (!grp->regs)
46ceb60c
SG		 592 return -ENOMEM;
593
ee873fda 594 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
46ceb60c
SG		 595
596 /* If we aren't the FEC we have multiple interrupts */
597 if (model && strcasecmp(model, "FEC")) {
ee873fda
CM		 598 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
599 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
600 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
601 gfar_irq(grp, RX)->irq == NO_IRQ ||
602 gfar_irq(grp, ER)->irq == NO_IRQ)
46ceb60c 603 return -EINVAL;
46ceb60c
SG		 604 }
605
5fedcc14
CM		 606 grp->grp_id = priv->num_grps;
607 grp->priv = priv;
608 spin_lock_init(&grp->grplock);
bc4598bc
JC		 609 if (priv->mode == MQ_MG_MODE) {
610 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
5fedcc14 611 grp->rx_bit_map = queue_mask ?
bc4598bc
JC		 612 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
613 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
5fedcc14 614 grp->tx_bit_map = queue_mask ?
bc4598bc 615 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
46ceb60c 616 } else {
5fedcc14
CM		 617 grp->rx_bit_map = 0xFF;
618 grp->tx_bit_map = 0xFF;
46ceb60c
SG		 619 }
620 priv->num_grps++;
621
622 return 0;
623}
624
2dc11581 625static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 626{
b31a1d8b
AF		 627 const char *model;
628 const char *ctype;
629 const void *mac_addr;
fba4ed03
SG		 630 int err = 0, i;
631 struct net_device *dev = NULL;
632 struct gfar_private *priv = NULL;
61c7a080 633 struct device_node *np = ofdev->dev.of_node;
46ceb60c 634 struct device_node *child = NULL;
4d7902f2
AF		 635 const u32 *stash;
636 const u32 *stash_len;
637 const u32 *stash_idx;
fba4ed03
SG		 638 unsigned int num_tx_qs, num_rx_qs;
639 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 640
641 if (!np || !of_device_is_available(np))
642 return -ENODEV;
643
fba4ed03
SG		 644 /* parse the num of tx and rx queues */
645 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
646 num_tx_qs = tx_queues ? *tx_queues : 1;
647
648 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 649 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
650 num_tx_qs, MAX_TX_QS);
651 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 652 return -EINVAL;
653 }
654
655 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
656 num_rx_qs = rx_queues ? *rx_queues : 1;
657
658 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 659 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
660 num_rx_qs, MAX_RX_QS);
661 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 662 return -EINVAL;
663 }
664
665 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
666 dev = *pdev;
667 if (NULL == dev)
668 return -ENOMEM;
669
670 priv = netdev_priv(dev);
61c7a080 671 priv->node = ofdev->dev.of_node;
fba4ed03
SG		 672 priv->ndev = dev;
673
fba4ed03 674 priv->num_tx_queues = num_tx_qs;
fe069123 675 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 676 priv->num_rx_queues = num_rx_qs;
46ceb60c 677 priv->num_grps = 0x0;
b31a1d8b 678
0977f817 679 /* Init Rx queue filer rule set linked list */
4aa3a715
SP		 680 INIT_LIST_HEAD(&priv->rx_list.list);
681 priv->rx_list.count = 0;
682 mutex_init(&priv->rx_queue_access);
683
b31a1d8b
AF		 684 model = of_get_property(np, "model", NULL);
685
46ceb60c
SG		 686 for (i = 0; i < MAXGROUPS; i++)
687 priv->gfargrp[i].regs = NULL;
b31a1d8b 688
46ceb60c
SG		 689 /* Parse and initialize group specific information */
690 if (of_device_is_compatible(np, "fsl,etsec2")) {
691 priv->mode = MQ_MG_MODE;
692 for_each_child_of_node(np, child) {
693 err = gfar_parse_group(child, priv, model);
694 if (err)
695 goto err_grp_init;
b31a1d8b 696 }
46ceb60c
SG		 697 } else {
698 priv->mode = SQ_SG_MODE;
699 err = gfar_parse_group(np, priv, model);
bc4598bc 700 if (err)
46ceb60c 701 goto err_grp_init;
b31a1d8b
AF		 702 }
703
fba4ed03
SG		 704 for (i = 0; i < priv->num_tx_queues; i++)
705 priv->tx_queue[i] = NULL;
706 for (i = 0; i < priv->num_rx_queues; i++)
707 priv->rx_queue[i] = NULL;
708
709 for (i = 0; i < priv->num_tx_queues; i++) {
de47f072
JP		 710 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
711 GFP_KERNEL);
fba4ed03
SG		 712 if (!priv->tx_queue[i]) {
713 err = -ENOMEM;
714 goto tx_alloc_failed;
715 }
716 priv->tx_queue[i]->tx_skbuff = NULL;
717 priv->tx_queue[i]->qindex = i;
718 priv->tx_queue[i]->dev = dev;
719 spin_lock_init(&(priv->tx_queue[i]->txlock));
720 }
721
722 for (i = 0; i < priv->num_rx_queues; i++) {
de47f072
JP		 723 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
724 GFP_KERNEL);
fba4ed03
SG		 725 if (!priv->rx_queue[i]) {
726 err = -ENOMEM;
727 goto rx_alloc_failed;
728 }
729 priv->rx_queue[i]->rx_skbuff = NULL;
730 priv->rx_queue[i]->qindex = i;
731 priv->rx_queue[i]->dev = dev;
732 spin_lock_init(&(priv->rx_queue[i]->rxlock));
733 }
734
735
4d7902f2
AF		 736 stash = of_get_property(np, "bd-stash", NULL);
737
a12f801d 738 if (stash) {
4d7902f2
AF		 739 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
740 priv->bd_stash_en = 1;
741 }
742
743 stash_len = of_get_property(np, "rx-stash-len", NULL);
744
745 if (stash_len)
746 priv->rx_stash_size = *stash_len;
747
748 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
749
750 if (stash_idx)
751 priv->rx_stash_index = *stash_idx;
752
753 if (stash_len || stash_idx)
754 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
755
b31a1d8b 756 mac_addr = of_get_mac_address(np);
bc4598bc 757
b31a1d8b 758 if (mac_addr)
6a3c910c 759 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 760
761 if (model && !strcasecmp(model, "TSEC"))
bc4598bc
JC		 762 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
763 FSL_GIANFAR_DEV_HAS_COALESCE |
764 FSL_GIANFAR_DEV_HAS_RMON |
765 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
766
b31a1d8b 767 if (model && !strcasecmp(model, "eTSEC"))
bc4598bc
JC		 768 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
769 FSL_GIANFAR_DEV_HAS_COALESCE |
770 FSL_GIANFAR_DEV_HAS_RMON |
771 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
772 FSL_GIANFAR_DEV_HAS_PADDING |
773 FSL_GIANFAR_DEV_HAS_CSUM |
774 FSL_GIANFAR_DEV_HAS_VLAN |
775 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
776 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
777 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 778
779 ctype = of_get_property(np, "phy-connection-type", NULL);
780
781 /* We only care about rgmii-id. The rest are autodetected */
782 if (ctype && !strcmp(ctype, "rgmii-id"))
783 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
784 else
785 priv->interface = PHY_INTERFACE_MODE_MII;
786
787 if (of_get_property(np, "fsl,magic-packet", NULL))
788 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
789
fe192a49 790 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 791
792 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 793 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 794
795 return 0;
796
fba4ed03
SG		 797rx_alloc_failed:
798 free_rx_pointers(priv);
799tx_alloc_failed:
800 free_tx_pointers(priv);
46ceb60c
SG		 801err_grp_init:
802 unmap_group_regs(priv);
ee873fda 803 free_gfar_dev(priv);
b31a1d8b
AF		 804 return err;
805}
806
cc772ab7 807static int gfar_hwtstamp_ioctl(struct net_device *netdev,
bc4598bc 808 struct ifreq *ifr, int cmd)
cc772ab7
MR		 809{
810 struct hwtstamp_config config;
811 struct gfar_private *priv = netdev_priv(netdev);
812
813 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
814 return -EFAULT;
815
816 /* reserved for future extensions */
817 if (config.flags)
818 return -EINVAL;
819
f0ee7acf
MR		 820 switch (config.tx_type) {
821 case HWTSTAMP_TX_OFF:
822 priv->hwts_tx_en = 0;
823 break;
824 case HWTSTAMP_TX_ON:
825 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
826 return -ERANGE;
827 priv->hwts_tx_en = 1;
828 break;
829 default:
cc772ab7 830 return -ERANGE;
f0ee7acf 831 }
cc772ab7
MR		 832
833 switch (config.rx_filter) {
834 case HWTSTAMP_FILTER_NONE:
97553f7f
MR		 835 if (priv->hwts_rx_en) {
836 stop_gfar(netdev);
837 priv->hwts_rx_en = 0;
838 startup_gfar(netdev);
839 }
cc772ab7
MR		 840 break;
841 default:
842 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
843 return -ERANGE;
97553f7f
MR		 844 if (!priv->hwts_rx_en) {
845 stop_gfar(netdev);
846 priv->hwts_rx_en = 1;
847 startup_gfar(netdev);
848 }
cc772ab7
MR		 849 config.rx_filter = HWTSTAMP_FILTER_ALL;
850 break;
851 }
852
853 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
854 -EFAULT : 0;
855}
856
0faac9f7
CW		 857/* Ioctl MII Interface */
858static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
859{
860 struct gfar_private *priv = netdev_priv(dev);
861
862 if (!netif_running(dev))
863 return -EINVAL;
864
cc772ab7
MR		 865 if (cmd == SIOCSHWTSTAMP)
866 return gfar_hwtstamp_ioctl(dev, rq, cmd);
867
0faac9f7
CW		 868 if (!priv->phydev)
869 return -ENODEV;
870
28b04113 871 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 872}
873
fba4ed03
SG		 874static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
875{
876 unsigned int new_bit_map = 0x0;
877 int mask = 0x1 << (max_qs - 1), i;
bc4598bc 878
fba4ed03
SG		 879 for (i = 0; i < max_qs; i++) {
880 if (bit_map & mask)
881 new_bit_map = new_bit_map + (1 << i);
882 mask = mask >> 0x1;
883 }
884 return new_bit_map;
885}
7a8b3372 886
18294ad1
AV		 887static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
888 u32 class)
7a8b3372
SG		 889{
890 u32 rqfpr = FPR_FILER_MASK;
891 u32 rqfcr = 0x0;
892
893 rqfar--;
894 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 895 priv->ftp_rqfpr[rqfar] = rqfpr;
896 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 897 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
898
899 rqfar--;
900 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 901 priv->ftp_rqfpr[rqfar] = rqfpr;
902 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 903 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
904
905 rqfar--;
906 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
907 rqfpr = class;
6c43e046
WJB		 908 priv->ftp_rqfcr[rqfar] = rqfcr;
909 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 910 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
911
912 rqfar--;
913 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
914 rqfpr = class;
6c43e046
WJB		 915 priv->ftp_rqfcr[rqfar] = rqfcr;
916 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 917 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
918
919 return rqfar;
920}
921
922static void gfar_init_filer_table(struct gfar_private *priv)
923{
924 int i = 0x0;
925 u32 rqfar = MAX_FILER_IDX;
926 u32 rqfcr = 0x0;
927 u32 rqfpr = FPR_FILER_MASK;
928
929 /* Default rule */
930 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 931 priv->ftp_rqfcr[rqfar] = rqfcr;
932 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 933 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
934
935 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
936 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
937 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
938 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
939 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
940 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
941
85dd08eb 942 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 943 priv->cur_filer_idx = rqfar;
944
945 /* Rest are masked rules */
946 rqfcr = RQFCR_CMP_NOMATCH;
947 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 948 priv->ftp_rqfcr[i] = rqfcr;
949 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 950 gfar_write_filer(priv, i, rqfcr, rqfpr);
951 }
952}
953
7d350977
AV		 954static void gfar_detect_errata(struct gfar_private *priv)
955{
956 struct device *dev = &priv->ofdev->dev;
957 unsigned int pvr = mfspr(SPRN_PVR);
958 unsigned int svr = mfspr(SPRN_SVR);
959 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
960 unsigned int rev = svr & 0xffff;
961
962 /* MPC8313 Rev 2.0 and higher; All MPC837x */
963 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
bc4598bc 964 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
7d350977
AV		 965 priv->errata |= GFAR_ERRATA_74;
966
deb90eac
AV		 967 /* MPC8313 and MPC837x all rev */
968 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 969 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
deb90eac
AV		 970 priv->errata |= GFAR_ERRATA_76;
971
511d934f
AV		 972 /* MPC8313 and MPC837x all rev */
973 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 974 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
511d934f
AV		 975 priv->errata |= GFAR_ERRATA_A002;
976
4363c2fd
AD		 977 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
978 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
bc4598bc 979 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
4363c2fd
AD		 980 priv->errata |= GFAR_ERRATA_12;
981
7d350977
AV		 982 if (priv->errata)
983 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
984 priv->errata);
985}
986
bb40dcbb 987/* Set up the ethernet device structure, private data,
0977f817
JC		 988 * and anything else we need before we start
989 */
74888760 990static int gfar_probe(struct platform_device *ofdev)
1da177e4
LT		 991{
992 u32 tempval;
993 struct net_device *dev = NULL;
994 struct gfar_private *priv = NULL;
f4983704 995 struct gfar __iomem *regs = NULL;
46ceb60c 996 int err = 0, i, grp_idx = 0;
fba4ed03 997 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 998 u32 isrg = 0;
18294ad1 999 u32 __iomem *baddr;
1da177e4 1000
fba4ed03 1001 err = gfar_of_init(ofdev, &dev);
1da177e4 1002
fba4ed03
SG		 1003 if (err)
1004 return err;
1da177e4
LT		 1005
1006 priv = netdev_priv(dev);
4826857f
KG		 1007 priv->ndev = dev;
1008 priv->ofdev = ofdev;
61c7a080 1009 priv->node = ofdev->dev.of_node;
4826857f 1010 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 1011
d87eb127 1012 spin_lock_init(&priv->bflock);
ab939905 1013 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 1014
b31a1d8b 1015 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 1016 regs = priv->gfargrp[0].regs;
1da177e4 1017
7d350977
AV		 1018 gfar_detect_errata(priv);
1019
0977f817
JC		 1020 /* Stop the DMA engine now, in case it was running before
1021 * (The firmware could have used it, and left it running).
1022 */
257d938a 1023 gfar_halt(dev);
1da177e4
LT		 1024
1025 /* Reset MAC layer */
f4983704 1026 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 1027
b98ac702
AF		 1028 /* We need to delay at least 3 TX clocks */
1029 udelay(2);
1030
1da177e4 1031 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 1032 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 1033
1034 /* Initialize MACCFG2. */
7d350977
AV		 1035 tempval = MACCFG2_INIT_SETTINGS;
1036 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1037 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1038 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 1039
1040 /* Initialize ECNTRL */
f4983704 1041 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 1042
1da177e4 1043 /* Set the dev->base_addr to the gfar reg region */
f4983704 1044 dev->base_addr = (unsigned long) regs;
1da177e4 1045
b31a1d8b 1046 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 1047
1048 /* Fill in the dev structure */
1da177e4 1049 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1050 dev->mtu = 1500;
26ccfc37 1051 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1052 dev->ethtool_ops = &gfar_ethtool_ops;
1053
fba4ed03 1054 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c 1055 for (i = 0; i < priv->num_grps; i++)
bc4598bc
JC		 1056 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1057 GFAR_DEV_WEIGHT);
a12f801d 1058
b31a1d8b 1059 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95 1060 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1061 NETIF_F_RXCSUM;
8b3afe95 1062 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1063 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
8b3afe95 1064 }
0bbaf069 1065
87c288c6
JP		 1066 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1067 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
e2c53be2 1068 dev->features |= NETIF_F_HW_VLAN_RX;
87c288c6 1069 }
0bbaf069 1070
b31a1d8b 1071 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 1072 priv->extended_hash = 1;
1073 priv->hash_width = 9;
1074
f4983704
SG		 1075 priv->hash_regs[0] = &regs->igaddr0;
1076 priv->hash_regs[1] = &regs->igaddr1;
1077 priv->hash_regs[2] = &regs->igaddr2;
1078 priv->hash_regs[3] = &regs->igaddr3;
1079 priv->hash_regs[4] = &regs->igaddr4;
1080 priv->hash_regs[5] = &regs->igaddr5;
1081 priv->hash_regs[6] = &regs->igaddr6;
1082 priv->hash_regs[7] = &regs->igaddr7;
1083 priv->hash_regs[8] = &regs->gaddr0;
1084 priv->hash_regs[9] = &regs->gaddr1;
1085 priv->hash_regs[10] = &regs->gaddr2;
1086 priv->hash_regs[11] = &regs->gaddr3;
1087 priv->hash_regs[12] = &regs->gaddr4;
1088 priv->hash_regs[13] = &regs->gaddr5;
1089 priv->hash_regs[14] = &regs->gaddr6;
1090 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1091
1092 } else {
1093 priv->extended_hash = 0;
1094 priv->hash_width = 8;
1095
f4983704
SG		 1096 priv->hash_regs[0] = &regs->gaddr0;
1097 priv->hash_regs[1] = &regs->gaddr1;
1098 priv->hash_regs[2] = &regs->gaddr2;
1099 priv->hash_regs[3] = &regs->gaddr3;
1100 priv->hash_regs[4] = &regs->gaddr4;
1101 priv->hash_regs[5] = &regs->gaddr5;
1102 priv->hash_regs[6] = &regs->gaddr6;
1103 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1104 }
1105
b31a1d8b 1106 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1107 priv->padding = DEFAULT_PADDING;
1108 else
1109 priv->padding = 0;
1110
cc772ab7 1111 if (dev->features & NETIF_F_IP_CSUM ||
bc4598bc 1112 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1113 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4 1114
46ceb60c
SG		 1115 /* Program the isrg regs only if number of grps > 1 */
1116 if (priv->num_grps > 1) {
1117 baddr = &regs->isrg0;
1118 for (i = 0; i < priv->num_grps; i++) {
1119 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1120 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1121 gfar_write(baddr, isrg);
1122 baddr++;
1123 isrg = 0x0;
1124 }
1125 }
1126
fba4ed03 1127 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1128 * but, for_each_set_bit parses from right to left, which
0977f817
JC		 1129 * basically reverses the queue numbers
1130 */
46ceb60c 1131 for (i = 0; i< priv->num_grps; i++) {
bc4598bc
JC		 1132 priv->gfargrp[i].tx_bit_map =
1133 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1134 priv->gfargrp[i].rx_bit_map =
1135 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
46ceb60c
SG		 1136 }
1137
1138 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
0977f817
JC		 1139 * also assign queues to groups
1140 */
46ceb60c
SG		 1141 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1142 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
bc4598bc 1143
984b3f57 1144 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
bc4598bc 1145 priv->num_rx_queues) {
46ceb60c
SG		 1146 priv->gfargrp[grp_idx].num_rx_queues++;
1147 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1148 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1149 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1150 }
1151 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
bc4598bc 1152
984b3f57 1153 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
bc4598bc 1154 priv->num_tx_queues) {
46ceb60c
SG		 1155 priv->gfargrp[grp_idx].num_tx_queues++;
1156 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1157 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1158 tqueue = tqueue | (TQUEUE_EN0 >> i);
1159 }
1160 priv->gfargrp[grp_idx].rstat = rstat;
1161 priv->gfargrp[grp_idx].tstat = tstat;
1162 rstat = tstat =0;
fba4ed03 1163 }
fba4ed03
SG		 1164
1165 gfar_write(&regs->rqueue, rqueue);
1166 gfar_write(&regs->tqueue, tqueue);
1167
1da177e4 1168 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1169
a12f801d 1170 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1171 for (i = 0; i < priv->num_tx_queues; i++) {
1172 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1173 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1174 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1175 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1176 }
a12f801d 1177
fba4ed03
SG		 1178 for (i = 0; i < priv->num_rx_queues; i++) {
1179 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1180 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1181 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1182 }
1da177e4 1183
0977f817 1184 /* always enable rx filer */
4aa3a715 1185 priv->rx_filer_enable = 1;
0bbaf069
KG		 1186 /* Enable most messages by default */
1187 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
b98b8bab
CM		 1188 /* use pritority h/w tx queue scheduling for single queue devices */
1189 if (priv->num_tx_queues == 1)
1190 priv->prio_sched_en = 1;
0bbaf069 1191
d3eab82b
TP		 1192 /* Carrier starts down, phylib will bring it up */
1193 netif_carrier_off(dev);
1194
1da177e4
LT		 1195 err = register_netdev(dev);
1196
1197 if (err) {
59deab26 1198 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1199 goto register_fail;
1200 }
1201
2884e5cc 1202 device_init_wakeup(&dev->dev,
bc4598bc
JC		 1203 priv->device_flags &
1204 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
2884e5cc 1205
c50a5d9a 1206 /* fill out IRQ number and name fields */
46ceb60c 1207 for (i = 0; i < priv->num_grps; i++) {
ee873fda 1208 struct gfar_priv_grp *grp = &priv->gfargrp[i];
46ceb60c 1209 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
ee873fda 1210 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
0015e551 1211 dev->name, "_g", '0' + i, "_tx");
ee873fda 1212 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
0015e551 1213 dev->name, "_g", '0' + i, "_rx");
ee873fda 1214 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
0015e551 1215 dev->name, "_g", '0' + i, "_er");
46ceb60c 1216 } else
ee873fda 1217 strcpy(gfar_irq(grp, TX)->name, dev->name);
46ceb60c 1218 }
c50a5d9a 1219
7a8b3372
SG		 1220 /* Initialize the filer table */
1221 gfar_init_filer_table(priv);
1222
7f7f5316
AF		 1223 /* Create all the sysfs files */
1224 gfar_init_sysfs(dev);
1225
1da177e4 1226 /* Print out the device info */
59deab26 1227 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4 1228
0977f817
JC		 1229 /* Even more device info helps when determining which kernel
1230 * provided which set of benchmarks.
1231 */
59deab26 1232 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1233 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1234 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1235 i, priv->rx_queue[i]->rx_ring_size);
bc4598bc 1236 for (i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1237 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1238 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1239
1240 return 0;
1241
1242register_fail:
46ceb60c 1243 unmap_group_regs(priv);
fba4ed03
SG		 1244 free_tx_pointers(priv);
1245 free_rx_pointers(priv);
fe192a49
GL		 1246 if (priv->phy_node)
1247 of_node_put(priv->phy_node);
1248 if (priv->tbi_node)
1249 of_node_put(priv->tbi_node);
ee873fda 1250 free_gfar_dev(priv);
bb40dcbb 1251 return err;
1da177e4
LT		 1252}
1253
2dc11581 1254static int gfar_remove(struct platform_device *ofdev)
1da177e4 1255{
b31a1d8b 1256 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1257
fe192a49
GL		 1258 if (priv->phy_node)
1259 of_node_put(priv->phy_node);
1260 if (priv->tbi_node)
1261 of_node_put(priv->tbi_node);
1262
b31a1d8b 1263 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1264
d9d8e041 1265 unregister_netdev(priv->ndev);
46ceb60c 1266 unmap_group_regs(priv);
ee873fda 1267 free_gfar_dev(priv);
1da177e4
LT		 1268
1269 return 0;
1270}
1271
d87eb127 1272#ifdef CONFIG_PM
be926fc4
AV		 1273
1274static int gfar_suspend(struct device *dev)
d87eb127 1275{
be926fc4
AV		 1276 struct gfar_private *priv = dev_get_drvdata(dev);
1277 struct net_device *ndev = priv->ndev;
46ceb60c 1278 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1279 unsigned long flags;
1280 u32 tempval;
1281
1282 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1283 (priv->device_flags &
1284 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1285
be926fc4 1286 netif_device_detach(ndev);
d87eb127 1287
be926fc4 1288 if (netif_running(ndev)) {
fba4ed03
SG		 1289
1290 local_irq_save(flags);
1291 lock_tx_qs(priv);
1292 lock_rx_qs(priv);
d87eb127 1293
be926fc4 1294 gfar_halt_nodisable(ndev);
d87eb127
SW		 1295
1296 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1297 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1298
1299 tempval &= ~MACCFG1_TX_EN;
1300
1301 if (!magic_packet)
1302 tempval &= ~MACCFG1_RX_EN;
1303
f4983704 1304 gfar_write(&regs->maccfg1, tempval);
d87eb127 1305
fba4ed03
SG		 1306 unlock_rx_qs(priv);
1307 unlock_tx_qs(priv);
1308 local_irq_restore(flags);
d87eb127 1309
46ceb60c 1310 disable_napi(priv);
d87eb127
SW		 1311
1312 if (magic_packet) {
1313 /* Enable interrupt on Magic Packet */
f4983704 1314 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1315
1316 /* Enable Magic Packet mode */
f4983704 1317 tempval = gfar_read(&regs->maccfg2);
d87eb127 1318 tempval |= MACCFG2_MPEN;
f4983704 1319 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1320 } else {
1321 phy_stop(priv->phydev);
1322 }
1323 }
1324
1325 return 0;
1326}
1327
be926fc4 1328static int gfar_resume(struct device *dev)
d87eb127 1329{
be926fc4
AV		 1330 struct gfar_private *priv = dev_get_drvdata(dev);
1331 struct net_device *ndev = priv->ndev;
46ceb60c 1332 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1333 unsigned long flags;
1334 u32 tempval;
1335 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1336 (priv->device_flags &
1337 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1338
be926fc4
AV		 1339 if (!netif_running(ndev)) {
1340 netif_device_attach(ndev);
d87eb127
SW		 1341 return 0;
1342 }
1343
1344 if (!magic_packet && priv->phydev)
1345 phy_start(priv->phydev);
1346
1347 /* Disable Magic Packet mode, in case something
1348 * else woke us up.
1349 */
fba4ed03
SG		 1350 local_irq_save(flags);
1351 lock_tx_qs(priv);
1352 lock_rx_qs(priv);
d87eb127 1353
f4983704 1354 tempval = gfar_read(&regs->maccfg2);
d87eb127 1355 tempval &= ~MACCFG2_MPEN;
f4983704 1356 gfar_write(&regs->maccfg2, tempval);
d87eb127 1357
be926fc4 1358 gfar_start(ndev);
d87eb127 1359
fba4ed03
SG		 1360 unlock_rx_qs(priv);
1361 unlock_tx_qs(priv);
1362 local_irq_restore(flags);
d87eb127 1363
be926fc4
AV		 1364 netif_device_attach(ndev);
1365
46ceb60c 1366 enable_napi(priv);
be926fc4
AV		 1367
1368 return 0;
1369}
1370
1371static int gfar_restore(struct device *dev)
1372{
1373 struct gfar_private *priv = dev_get_drvdata(dev);
1374 struct net_device *ndev = priv->ndev;
1375
103cdd1d
WD		 1376 if (!netif_running(ndev)) {
1377 netif_device_attach(ndev);
1378
be926fc4 1379 return 0;
103cdd1d 1380 }
be926fc4 1381
1eb8f7a7
CM		 1382 if (gfar_init_bds(ndev)) {
1383 free_skb_resources(priv);
1384 return -ENOMEM;
1385 }
1386
be926fc4
AV		 1387 init_registers(ndev);
1388 gfar_set_mac_address(ndev);
1389 gfar_init_mac(ndev);
1390 gfar_start(ndev);
1391
1392 priv->oldlink = 0;
1393 priv->oldspeed = 0;
1394 priv->oldduplex = -1;
1395
1396 if (priv->phydev)
1397 phy_start(priv->phydev);
d87eb127 1398
be926fc4 1399 netif_device_attach(ndev);
5ea681d4 1400 enable_napi(priv);
d87eb127
SW		 1401
1402 return 0;
1403}
be926fc4
AV		 1404
1405static struct dev_pm_ops gfar_pm_ops = {
1406 .suspend = gfar_suspend,
1407 .resume = gfar_resume,
1408 .freeze = gfar_suspend,
1409 .thaw = gfar_resume,
1410 .restore = gfar_restore,
1411};
1412
1413#define GFAR_PM_OPS (&gfar_pm_ops)
1414
d87eb127 1415#else
be926fc4
AV		 1416
1417#define GFAR_PM_OPS NULL
be926fc4 1418
d87eb127 1419#endif
1da177e4 1420
e8a2b6a4
AF		 1421/* Reads the controller's registers to determine what interface
1422 * connects it to the PHY.
1423 */
1424static phy_interface_t gfar_get_interface(struct net_device *dev)
1425{
1426 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1427 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1428 u32 ecntrl;
1429
f4983704 1430 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1431
1432 if (ecntrl & ECNTRL_SGMII_MODE)
1433 return PHY_INTERFACE_MODE_SGMII;
1434
1435 if (ecntrl & ECNTRL_TBI_MODE) {
1436 if (ecntrl & ECNTRL_REDUCED_MODE)
1437 return PHY_INTERFACE_MODE_RTBI;
1438 else
1439 return PHY_INTERFACE_MODE_TBI;
1440 }
1441
1442 if (ecntrl & ECNTRL_REDUCED_MODE) {
bc4598bc 1443 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
e8a2b6a4 1444 return PHY_INTERFACE_MODE_RMII;
bc4598bc 1445 }
7132ab7f 1446 else {
b31a1d8b 1447 phy_interface_t interface = priv->interface;
7132ab7f 1448
0977f817 1449 /* This isn't autodetected right now, so it must
7132ab7f
AF		 1450 * be set by the device tree or platform code.
1451 */
1452 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1453 return PHY_INTERFACE_MODE_RGMII_ID;
1454
e8a2b6a4 1455 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1456 }
e8a2b6a4
AF		 1457 }
1458
b31a1d8b 1459 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1460 return PHY_INTERFACE_MODE_GMII;
1461
1462 return PHY_INTERFACE_MODE_MII;
1463}
1464
1465
bb40dcbb
AF		 1466/* Initializes driver's PHY state, and attaches to the PHY.
1467 * Returns 0 on success.
1da177e4
LT		 1468 */
1469static int init_phy(struct net_device *dev)
1470{
1471 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1472 uint gigabit_support =
b31a1d8b 1473 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1474 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1475 phy_interface_t interface;
1da177e4
LT		 1476
1477 priv->oldlink = 0;
1478 priv->oldspeed = 0;
1479 priv->oldduplex = -1;
1480
e8a2b6a4
AF		 1481 interface = gfar_get_interface(dev);
1482
1db780f8
AV		 1483 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1484 interface);
1485 if (!priv->phydev)
1486 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1487 interface);
1488 if (!priv->phydev) {
1489 dev_err(&dev->dev, "could not attach to PHY\n");
1490 return -ENODEV;
fe192a49 1491 }
1da177e4 1492
d3c12873
KJ		 1493 if (interface == PHY_INTERFACE_MODE_SGMII)
1494 gfar_configure_serdes(dev);
1495
bb40dcbb 1496 /* Remove any features not supported by the controller */
fe192a49
GL		 1497 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1498 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1499
1500 return 0;
1da177e4
LT		 1501}
1502
0977f817 1503/* Initialize TBI PHY interface for communicating with the
d0313587
PG		 1504 * SERDES lynx PHY on the chip. We communicate with this PHY
1505 * through the MDIO bus on each controller, treating it as a
1506 * "normal" PHY at the address found in the TBIPA register. We assume
1507 * that the TBIPA register is valid. Either the MDIO bus code will set
1508 * it to a value that doesn't conflict with other PHYs on the bus, or the
1509 * value doesn't matter, as there are no other PHYs on the bus.
1510 */
d3c12873
KJ		 1511static void gfar_configure_serdes(struct net_device *dev)
1512{
1513 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1514 struct phy_device *tbiphy;
1515
1516 if (!priv->tbi_node) {
1517 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1518 "device tree specify a tbi-handle\n");
1519 return;
1520 }
c132419e 1521
fe192a49
GL		 1522 tbiphy = of_phy_find_device(priv->tbi_node);
1523 if (!tbiphy) {
1524 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1525 return;
1526 }
d3c12873 1527
0977f817 1528 /* If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1529 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1530 * everything for us? Resetting it takes the link down and requires
1531 * several seconds for it to come back.
1532 */
fe192a49 1533 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1534 return;
d3c12873 1535
d0313587 1536 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1537 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1538
fe192a49 1539 phy_write(tbiphy, MII_ADVERTISE,
bc4598bc
JC		 1540 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1541 ADVERTISE_1000XPSE_ASYM);
d3c12873 1542
bc4598bc
JC		 1543 phy_write(tbiphy, MII_BMCR,
1544 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1545 BMCR_SPEED1000);
d3c12873
KJ		 1546}
1547
1da177e4
LT		 1548static void init_registers(struct net_device *dev)
1549{
1550 struct gfar_private *priv = netdev_priv(dev);
f4983704 1551 struct gfar __iomem *regs = NULL;
3a2e16c8 1552 int i;
1da177e4 1553
46ceb60c
SG		 1554 for (i = 0; i < priv->num_grps; i++) {
1555 regs = priv->gfargrp[i].regs;
1556 /* Clear IEVENT */
1557 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1558
46ceb60c
SG		 1559 /* Initialize IMASK */
1560 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1561 }
1da177e4 1562
46ceb60c 1563 regs = priv->gfargrp[0].regs;
1da177e4 1564 /* Init hash registers to zero */
f4983704
SG		 1565 gfar_write(&regs->igaddr0, 0);
1566 gfar_write(&regs->igaddr1, 0);
1567 gfar_write(&regs->igaddr2, 0);
1568 gfar_write(&regs->igaddr3, 0);
1569 gfar_write(&regs->igaddr4, 0);
1570 gfar_write(&regs->igaddr5, 0);
1571 gfar_write(&regs->igaddr6, 0);
1572 gfar_write(&regs->igaddr7, 0);
1573
1574 gfar_write(&regs->gaddr0, 0);
1575 gfar_write(&regs->gaddr1, 0);
1576 gfar_write(&regs->gaddr2, 0);
1577 gfar_write(&regs->gaddr3, 0);
1578 gfar_write(&regs->gaddr4, 0);
1579 gfar_write(&regs->gaddr5, 0);
1580 gfar_write(&regs->gaddr6, 0);
1581 gfar_write(&regs->gaddr7, 0);
1da177e4 1582
1da177e4 1583 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1584 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1585 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1586
1587 /* Mask off the CAM interrupts */
f4983704
SG		 1588 gfar_write(&regs->rmon.cam1, 0xffffffff);
1589 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1590 }
1591
1592 /* Initialize the max receive buffer length */
f4983704 1593 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1594
1da177e4 1595 /* Initialize the Minimum Frame Length Register */
f4983704 1596 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1597}
1598
511d934f
AV		 1599static int __gfar_is_rx_idle(struct gfar_private *priv)
1600{
1601 u32 res;
1602
0977f817 1603 /* Normaly TSEC should not hang on GRS commands, so we should
511d934f
AV		 1604 * actually wait for IEVENT_GRSC flag.
1605 */
1606 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1607 return 0;
1608
0977f817 1609 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
511d934f
AV		 1610 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1611 * and the Rx can be safely reset.
1612 */
1613 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1614 res &= 0x7f807f80;
1615 if ((res & 0xffff) == (res >> 16))
1616 return 1;
1617
1618 return 0;
1619}
0bbaf069
KG		 1620
1621/* Halt the receive and transmit queues */
d87eb127 1622static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1623{
1624 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1625 struct gfar __iomem *regs = NULL;
1da177e4 1626 u32 tempval;
3a2e16c8 1627 int i;
1da177e4 1628
46ceb60c
SG		 1629 for (i = 0; i < priv->num_grps; i++) {
1630 regs = priv->gfargrp[i].regs;
1631 /* Mask all interrupts */
1632 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1633
46ceb60c
SG		 1634 /* Clear all interrupts */
1635 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1636 }
1da177e4 1637
46ceb60c 1638 regs = priv->gfargrp[0].regs;
1da177e4 1639 /* Stop the DMA, and wait for it to stop */
f4983704 1640 tempval = gfar_read(&regs->dmactrl);
bc4598bc
JC		 1641 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1642 (DMACTRL_GRS | DMACTRL_GTS)) {
511d934f
AV		 1643 int ret;
1644
1da177e4 1645 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1646 gfar_write(&regs->dmactrl, tempval);
1da177e4 1647
511d934f
AV		 1648 do {
1649 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1650 (IEVENT_GRSC | IEVENT_GTSC)) ==
1651 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1652 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1653 ret = __gfar_is_rx_idle(priv);
1654 } while (!ret);
1da177e4 1655 }
d87eb127 1656}
d87eb127
SW		 1657
1658/* Halt the receive and transmit queues */
1659void gfar_halt(struct net_device *dev)
1660{
1661 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1662 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1663 u32 tempval;
1da177e4 1664
2a54adc3
SW		 1665 gfar_halt_nodisable(dev);
1666
1da177e4
LT		 1667 /* Disable Rx and Tx */
1668 tempval = gfar_read(&regs->maccfg1);
1669 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1670 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1671}
1672
46ceb60c
SG		 1673static void free_grp_irqs(struct gfar_priv_grp *grp)
1674{
ee873fda
CM		 1675 free_irq(gfar_irq(grp, TX)->irq, grp);
1676 free_irq(gfar_irq(grp, RX)->irq, grp);
1677 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 1678}
1679
0bbaf069
KG		 1680void stop_gfar(struct net_device *dev)
1681{
1682 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1683 unsigned long flags;
46ceb60c 1684 int i;
0bbaf069 1685
bb40dcbb
AF		 1686 phy_stop(priv->phydev);
1687
a12f801d 1688
0bbaf069 1689 /* Lock it down */
fba4ed03
SG		 1690 local_irq_save(flags);
1691 lock_tx_qs(priv);
1692 lock_rx_qs(priv);
0bbaf069 1693
0bbaf069 1694 gfar_halt(dev);
1da177e4 1695
fba4ed03
SG		 1696 unlock_rx_qs(priv);
1697 unlock_tx_qs(priv);
1698 local_irq_restore(flags);
1da177e4
LT		 1699
1700 /* Free the IRQs */
b31a1d8b 1701 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1702 for (i = 0; i < priv->num_grps; i++)
1703 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1704 } else {
46ceb60c 1705 for (i = 0; i < priv->num_grps; i++)
ee873fda 1706 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
bc4598bc 1707 &priv->gfargrp[i]);
1da177e4
LT		 1708 }
1709
1710 free_skb_resources(priv);
1da177e4
LT		 1711}
1712
fba4ed03 1713static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1714{
1da177e4 1715 struct txbd8 *txbdp;
fba4ed03 1716 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1717 int i, j;
1da177e4 1718
a12f801d 1719 txbdp = tx_queue->tx_bd_base;
1da177e4 1720
a12f801d
SG		 1721 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1722 if (!tx_queue->tx_skbuff[i])
4669bc90 1723 continue;
1da177e4 1724
4826857f 1725 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
bc4598bc 1726 txbdp->length, DMA_TO_DEVICE);
4669bc90 1727 txbdp->lstatus = 0;
fba4ed03 1728 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
bc4598bc 1729 j++) {
4669bc90 1730 txbdp++;
4826857f 1731 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
bc4598bc 1732 txbdp->length, DMA_TO_DEVICE);
1da177e4 1733 }
ad5da7ab 1734 txbdp++;
a12f801d
SG		 1735 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1736 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1737 }
a12f801d 1738 kfree(tx_queue->tx_skbuff);
1eb8f7a7 1739 tx_queue->tx_skbuff = NULL;
fba4ed03 1740}
1da177e4 1741
fba4ed03
SG		 1742static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1743{
1744 struct rxbd8 *rxbdp;
1745 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1746 int i;
1da177e4 1747
fba4ed03 1748 rxbdp = rx_queue->rx_bd_base;
1da177e4 1749
a12f801d
SG		 1750 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1751 if (rx_queue->rx_skbuff[i]) {
fba4ed03 1752 dma_unmap_single(&priv->ofdev->dev,
bc4598bc
JC		 1753 rxbdp->bufPtr, priv->rx_buffer_size,
1754 DMA_FROM_DEVICE);
a12f801d
SG		 1755 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1756 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1757 }
e69edd21
AV		 1758 rxbdp->lstatus = 0;
1759 rxbdp->bufPtr = 0;
1760 rxbdp++;
1da177e4 1761 }
a12f801d 1762 kfree(rx_queue->rx_skbuff);
1eb8f7a7 1763 rx_queue->rx_skbuff = NULL;
fba4ed03 1764}
e69edd21 1765
fba4ed03 1766/* If there are any tx skbs or rx skbs still around, free them.
0977f817
JC		 1767 * Then free tx_skbuff and rx_skbuff
1768 */
fba4ed03
SG		 1769static void free_skb_resources(struct gfar_private *priv)
1770{
1771 struct gfar_priv_tx_q *tx_queue = NULL;
1772 struct gfar_priv_rx_q *rx_queue = NULL;
1773 int i;
1774
1775 /* Go through all the buffer descriptors and free their data buffers */
1776 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 1777 struct netdev_queue *txq;
bc4598bc 1778
fba4ed03 1779 tx_queue = priv->tx_queue[i];
d8a0f1b0 1780 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
bc4598bc 1781 if (tx_queue->tx_skbuff)
fba4ed03 1782 free_skb_tx_queue(tx_queue);
d8a0f1b0 1783 netdev_tx_reset_queue(txq);
fba4ed03
SG		 1784 }
1785
1786 for (i = 0; i < priv->num_rx_queues; i++) {
1787 rx_queue = priv->rx_queue[i];
bc4598bc 1788 if (rx_queue->rx_skbuff)
fba4ed03
SG		 1789 free_skb_rx_queue(rx_queue);
1790 }
1791
1792 dma_free_coherent(&priv->ofdev->dev,
bc4598bc
JC		 1793 sizeof(struct txbd8) * priv->total_tx_ring_size +
1794 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1795 priv->tx_queue[0]->tx_bd_base,
1796 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1797}
1798
0bbaf069
KG		 1799void gfar_start(struct net_device *dev)
1800{
1801 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1802 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1803 u32 tempval;
46ceb60c 1804 int i = 0;
0bbaf069
KG		 1805
1806 /* Enable Rx and Tx in MACCFG1 */
1807 tempval = gfar_read(&regs->maccfg1);
1808 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1809 gfar_write(&regs->maccfg1, tempval);
1810
1811 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1812 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1813 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1814 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1815
0bbaf069 1816 /* Make sure we aren't stopped */
f4983704 1817 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1818 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1819 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1820
46ceb60c
SG		 1821 for (i = 0; i < priv->num_grps; i++) {
1822 regs = priv->gfargrp[i].regs;
1823 /* Clear THLT/RHLT, so that the DMA starts polling now */
1824 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1825 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1826 /* Unmask the interrupts we look for */
1827 gfar_write(&regs->imask, IMASK_DEFAULT);
1828 }
12dea57b 1829
1ae5dc34 1830 dev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1831}
1832
46ceb60c 1833void gfar_configure_coalescing(struct gfar_private *priv,
bc4598bc 1834 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1835{
46ceb60c 1836 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1837 u32 __iomem *baddr;
46ceb60c 1838 int i = 0;
1da177e4 1839
46ceb60c
SG		 1840 /* Backward compatible case ---- even if we enable
1841 * multiple queues, there's only single reg to program
1842 */
1843 gfar_write(&regs->txic, 0);
bc4598bc 1844 if (likely(priv->tx_queue[0]->txcoalescing))
46ceb60c 1845 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1846
46ceb60c 1847 gfar_write(&regs->rxic, 0);
bc4598bc 1848 if (unlikely(priv->rx_queue[0]->rxcoalescing))
46ceb60c 1849 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1850
46ceb60c
SG		 1851 if (priv->mode == MQ_MG_MODE) {
1852 baddr = &regs->txic0;
984b3f57 1853 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
9740e001
CM		 1854 gfar_write(baddr + i, 0);
1855 if (likely(priv->tx_queue[i]->txcoalescing))
46ceb60c 1856 gfar_write(baddr + i, priv->tx_queue[i]->txic);
46ceb60c
SG		 1857 }
1858
1859 baddr = &regs->rxic0;
984b3f57 1860 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
9740e001
CM		 1861 gfar_write(baddr + i, 0);
1862 if (likely(priv->rx_queue[i]->rxcoalescing))
46ceb60c 1863 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
46ceb60c
SG		 1864 }
1865 }
1866}
1867
1868static int register_grp_irqs(struct gfar_priv_grp *grp)
1869{
1870 struct gfar_private *priv = grp->priv;
1871 struct net_device *dev = priv->ndev;
1872 int err;
1da177e4 1873
1da177e4 1874 /* If the device has multiple interrupts, register for
0977f817
JC		 1875 * them. Otherwise, only register for the one
1876 */
b31a1d8b 1877 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1878 /* Install our interrupt handlers for Error,
0977f817
JC		 1879 * Transmit, and Receive
1880 */
ee873fda
CM		 1881 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1882 gfar_irq(grp, ER)->name, grp);
1883 if (err < 0) {
59deab26 1884 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1885 gfar_irq(grp, ER)->irq);
46ceb60c 1886
2145f1af 1887 goto err_irq_fail;
1da177e4 1888 }
ee873fda
CM		 1889 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1890 gfar_irq(grp, TX)->name, grp);
1891 if (err < 0) {
59deab26 1892 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1893 gfar_irq(grp, TX)->irq);
1da177e4
LT		 1894 goto tx_irq_fail;
1895 }
ee873fda
CM		 1896 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1897 gfar_irq(grp, RX)->name, grp);
1898 if (err < 0) {
59deab26 1899 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1900 gfar_irq(grp, RX)->irq);
1da177e4
LT		 1901 goto rx_irq_fail;
1902 }
1903 } else {
ee873fda
CM		 1904 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1905 gfar_irq(grp, TX)->name, grp);
1906 if (err < 0) {
59deab26 1907 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1908 gfar_irq(grp, TX)->irq);
1da177e4
LT		 1909 goto err_irq_fail;
1910 }
1911 }
1912
46ceb60c
SG		 1913 return 0;
1914
1915rx_irq_fail:
ee873fda 1916 free_irq(gfar_irq(grp, TX)->irq, grp);
46ceb60c 1917tx_irq_fail:
ee873fda 1918 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 1919err_irq_fail:
1920 return err;
1921
1922}
1923
1924/* Bring the controller up and running */
1925int startup_gfar(struct net_device *ndev)
1926{
1927 struct gfar_private *priv = netdev_priv(ndev);
1928 struct gfar __iomem *regs = NULL;
1929 int err, i, j;
1930
1931 for (i = 0; i < priv->num_grps; i++) {
1932 regs= priv->gfargrp[i].regs;
1933 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1934 }
1935
1936 regs= priv->gfargrp[0].regs;
1937 err = gfar_alloc_skb_resources(ndev);
1938 if (err)
1939 return err;
1940
1941 gfar_init_mac(ndev);
1942
1943 for (i = 0; i < priv->num_grps; i++) {
1944 err = register_grp_irqs(&priv->gfargrp[i]);
1945 if (err) {
1946 for (j = 0; j < i; j++)
1947 free_grp_irqs(&priv->gfargrp[j]);
ff76015f 1948 goto irq_fail;
46ceb60c
SG		 1949 }
1950 }
1951
7f7f5316 1952 /* Start the controller */
ccc05c6e 1953 gfar_start(ndev);
1da177e4 1954
826aa4a0
AV		 1955 phy_start(priv->phydev);
1956
46ceb60c
SG		 1957 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1958
1da177e4
LT		 1959 return 0;
1960
46ceb60c 1961irq_fail:
e69edd21 1962 free_skb_resources(priv);
1da177e4
LT		 1963 return err;
1964}
1965
0977f817
JC		 1966/* Called when something needs to use the ethernet device
1967 * Returns 0 for success.
1968 */
1da177e4
LT		 1969static int gfar_enet_open(struct net_device *dev)
1970{
94e8cc35 1971 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1972 int err;
1973
46ceb60c 1974 enable_napi(priv);
bea3348e 1975
1da177e4
LT		 1976 /* Initialize a bunch of registers */
1977 init_registers(dev);
1978
1979 gfar_set_mac_address(dev);
1980
1981 err = init_phy(dev);
1982
a12f801d 1983 if (err) {
46ceb60c 1984 disable_napi(priv);
1da177e4 1985 return err;
bea3348e 1986 }
1da177e4
LT		 1987
1988 err = startup_gfar(dev);
db0e8e3f 1989 if (err) {
46ceb60c 1990 disable_napi(priv);
db0e8e3f
AV		 1991 return err;
1992 }
1da177e4 1993
fba4ed03 1994 netif_tx_start_all_queues(dev);
1da177e4 1995
2884e5cc
AV		 1996 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1997
1da177e4
LT		 1998 return err;
1999}
2000
54dc79fe 2001static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 2002{
54dc79fe 2003 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 2004
2005 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 2006
0bbaf069
KG		 2007 return fcb;
2008}
2009
9c4886e5 2010static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
bc4598bc 2011 int fcb_length)
0bbaf069 2012{
0bbaf069
KG		 2013 /* If we're here, it's a IP packet with a TCP or UDP
2014 * payload. We set it to checksum, using a pseudo-header
2015 * we provide
2016 */
3a2e16c8 2017 u8 flags = TXFCB_DEFAULT;
0bbaf069 2018
0977f817
JC		 2019 /* Tell the controller what the protocol is
2020 * And provide the already calculated phcs
2021 */
eddc9ec5 2022 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2023 flags |= TXFCB_UDP;
4bedb452 2024 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 2025 } else
8da32de5 2026 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 2027
2028 /* l3os is the distance between the start of the
2029 * frame (skb->data) and the start of the IP hdr.
2030 * l4os is the distance between the start of the
0977f817
JC		 2031 * l3 hdr and the l4 hdr
2032 */
9c4886e5 2033 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
cfe1fc77 2034 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2035
7f7f5316 2036 fcb->flags = flags;
0bbaf069
KG		 2037}
2038
7f7f5316 2039void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2040{
7f7f5316 2041 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 2042 fcb->vlctl = vlan_tx_tag_get(skb);
2043}
2044
4669bc90 2045static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
bc4598bc 2046 struct txbd8 *base, int ring_size)
4669bc90
DH		 2047{
2048 struct txbd8 *new_bd = bdp + stride;
2049
2050 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2051}
2052
2053static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
bc4598bc 2054 int ring_size)
4669bc90
DH		 2055{
2056 return skip_txbd(bdp, 1, base, ring_size);
2057}
2058
0977f817
JC		 2059/* This is called by the kernel when a frame is ready for transmission.
2060 * It is pointed to by the dev->hard_start_xmit function pointer
2061 */
1da177e4
LT		 2062static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2063{
2064 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2065 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2066 struct netdev_queue *txq;
f4983704 2067 struct gfar __iomem *regs = NULL;
0bbaf069 2068 struct txfcb *fcb = NULL;
f0ee7acf 2069 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2070 u32 lstatus;
f0ee7acf 2071 int i, rq = 0, do_tstamp = 0;
4669bc90 2072 u32 bufaddr;
fef6108d 2073 unsigned long flags;
9c4886e5 2074 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
fba4ed03 2075
0977f817 2076 /* TOE=1 frames larger than 2500 bytes may see excess delays
deb90eac
AV		 2077 * before start of transmission.
2078 */
2079 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
bc4598bc
JC		 2080 skb->ip_summed == CHECKSUM_PARTIAL &&
2081 skb->len > 2500)) {
deb90eac
AV		 2082 int ret;
2083
2084 ret = skb_checksum_help(skb);
2085 if (ret)
2086 return ret;
2087 }
2088
fba4ed03
SG		 2089 rq = skb->queue_mapping;
2090 tx_queue = priv->tx_queue[rq];
2091 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2092 base = tx_queue->tx_bd_base;
46ceb60c 2093 regs = tx_queue->grp->regs;
f0ee7acf
MR		 2094
2095 /* check if time stamp should be generated */
2244d07b 2096 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
bc4598bc 2097 priv->hwts_tx_en)) {
f0ee7acf 2098 do_tstamp = 1;
9c4886e5
MR		 2099 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2100 }
4669bc90 2101
5b28beaf
LY		 2102 /* make space for additional header when fcb is needed */
2103 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
bc4598bc
JC		 2104 vlan_tx_tag_present(skb) ||
2105 unlikely(do_tstamp)) &&
2106 (skb_headroom(skb) < fcb_length)) {
54dc79fe
SH		 2107 struct sk_buff *skb_new;
2108
9c4886e5 2109 skb_new = skb_realloc_headroom(skb, fcb_length);
54dc79fe
SH		 2110 if (!skb_new) {
2111 dev->stats.tx_errors++;
bd14ba84 2112 kfree_skb(skb);
54dc79fe
SH		 2113 return NETDEV_TX_OK;
2114 }
db83d136 2115
313b037c
ED		 2116 if (skb->sk)
2117 skb_set_owner_w(skb_new, skb->sk);
2118 consume_skb(skb);
54dc79fe
SH		 2119 skb = skb_new;
2120 }
2121
4669bc90
DH		 2122 /* total number of fragments in the SKB */
2123 nr_frags = skb_shinfo(skb)->nr_frags;
2124
f0ee7acf
MR		 2125 /* calculate the required number of TxBDs for this skb */
2126 if (unlikely(do_tstamp))
2127 nr_txbds = nr_frags + 2;
2128 else
2129 nr_txbds = nr_frags + 1;
2130
4669bc90 2131 /* check if there is space to queue this packet */
f0ee7acf 2132 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2133 /* no space, stop the queue */
fba4ed03 2134 netif_tx_stop_queue(txq);
4669bc90 2135 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2136 return NETDEV_TX_BUSY;
2137 }
1da177e4
LT		 2138
2139 /* Update transmit stats */
1ac9ad13
ED		 2140 tx_queue->stats.tx_bytes += skb->len;
2141 tx_queue->stats.tx_packets++;
1da177e4 2142
a12f801d 2143 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2144 lstatus = txbdp->lstatus;
2145
2146 /* Time stamp insertion requires one additional TxBD */
2147 if (unlikely(do_tstamp))
2148 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
bc4598bc 2149 tx_queue->tx_ring_size);
1da177e4 2150
4669bc90 2151 if (nr_frags == 0) {
f0ee7acf
MR		 2152 if (unlikely(do_tstamp))
2153 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
bc4598bc 2154 TXBD_INTERRUPT);
f0ee7acf
MR		 2155 else
2156 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2157 } else {
2158 /* Place the fragment addresses and lengths into the TxBDs */
2159 for (i = 0; i < nr_frags; i++) {
2160 /* Point at the next BD, wrapping as needed */
a12f801d 2161 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2162
2163 length = skb_shinfo(skb)->frags[i].size;
2164
2165 lstatus = txbdp->lstatus | length |
bc4598bc 2166 BD_LFLAG(TXBD_READY);
4669bc90
DH		 2167
2168 /* Handle the last BD specially */
2169 if (i == nr_frags - 1)
2170 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2171
2234a722
IC		 2172 bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2173 &skb_shinfo(skb)->frags[i],
2174 0,
2175 length,
2176 DMA_TO_DEVICE);
4669bc90
DH		 2177
2178 /* set the TxBD length and buffer pointer */
2179 txbdp->bufPtr = bufaddr;
2180 txbdp->lstatus = lstatus;
2181 }
2182
2183 lstatus = txbdp_start->lstatus;
2184 }
1da177e4 2185
9c4886e5
MR		 2186 /* Add TxPAL between FCB and frame if required */
2187 if (unlikely(do_tstamp)) {
2188 skb_push(skb, GMAC_TXPAL_LEN);
2189 memset(skb->data, 0, GMAC_TXPAL_LEN);
2190 }
2191
0bbaf069 2192 /* Set up checksumming */
12dea57b 2193 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe 2194 fcb = gfar_add_fcb(skb);
4363c2fd 2195 /* as specified by errata */
bc4598bc
JC		 2196 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2197 ((unsigned long)fcb % 0x20) > 0x18)) {
4363c2fd
AD		 2198 __skb_pull(skb, GMAC_FCB_LEN);
2199 skb_checksum_help(skb);
2200 } else {
2201 lstatus |= BD_LFLAG(TXBD_TOE);
9c4886e5 2202 gfar_tx_checksum(skb, fcb, fcb_length);
4363c2fd 2203 }
0bbaf069
KG		 2204 }
2205
eab6d18d 2206 if (vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2207 if (unlikely(NULL == fcb)) {
2208 fcb = gfar_add_fcb(skb);
5a5efed4 2209 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2210 }
54dc79fe
SH		 2211
2212 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2213 }
2214
f0ee7acf
MR		 2215 /* Setup tx hardware time stamping if requested */
2216 if (unlikely(do_tstamp)) {
2244d07b 2217 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf
MR		 2218 if (fcb == NULL)
2219 fcb = gfar_add_fcb(skb);
2220 fcb->ptp = 1;
2221 lstatus |= BD_LFLAG(TXBD_TOE);
2222 }
2223
4826857f 2224 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
bc4598bc 2225 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2226
0977f817 2227 /* If time stamping is requested one additional TxBD must be set up. The
f0ee7acf
MR		 2228 * first TxBD points to the FCB and must have a data length of
2229 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2230 * the full frame length.
2231 */
2232 if (unlikely(do_tstamp)) {
9c4886e5 2233 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
f0ee7acf 2234 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
bc4598bc 2235 (skb_headlen(skb) - fcb_length);
f0ee7acf
MR		 2236 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2237 } else {
2238 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2239 }
1da177e4 2240
d8a0f1b0
PG		 2241 netdev_tx_sent_queue(txq, skb->len);
2242
0977f817 2243 /* We can work in parallel with gfar_clean_tx_ring(), except
a3bc1f11
AV		 2244 * when modifying num_txbdfree. Note that we didn't grab the lock
2245 * when we were reading the num_txbdfree and checking for available
2246 * space, that's because outside of this function it can only grow,
2247 * and once we've got needed space, it cannot suddenly disappear.
2248 *
2249 * The lock also protects us from gfar_error(), which can modify
2250 * regs->tstat and thus retrigger the transfers, which is why we
2251 * also must grab the lock before setting ready bit for the first
2252 * to be transmitted BD.
2253 */
2254 spin_lock_irqsave(&tx_queue->txlock, flags);
2255
0977f817 2256 /* The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2257 * semantics (it requires synchronization between cacheable and
2258 * uncacheable mappings, which eieio doesn't provide and which we
2259 * don't need), thus requiring a more expensive sync instruction. At
2260 * some point, the set of architecture-independent barrier functions
2261 * should be expanded to include weaker barriers.
2262 */
3b6330ce 2263 eieio();
7f7f5316 2264
4669bc90
DH		 2265 txbdp_start->lstatus = lstatus;
2266
0eddba52
AV		 2267 eieio(); /* force lstatus write before tx_skbuff */
2268
2269 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2270
4669bc90 2271 /* Update the current skb pointer to the next entry we will use
0977f817
JC		 2272 * (wrapping if necessary)
2273 */
a12f801d 2274 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
bc4598bc 2275 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2276
a12f801d 2277 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2278
2279 /* reduce TxBD free count */
f0ee7acf 2280 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2281
2282 /* If the next BD still needs to be cleaned up, then the bds
0977f817
JC		 2283 * are full. We need to tell the kernel to stop sending us stuff.
2284 */
a12f801d 2285 if (!tx_queue->num_txbdfree) {
fba4ed03 2286 netif_tx_stop_queue(txq);
1da177e4 2287
09f75cd7 2288 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2289 }
2290
1da177e4 2291 /* Tell the DMA to go go go */
fba4ed03 2292 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2293
2294 /* Unlock priv */
a12f801d 2295 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2296
54dc79fe 2297 return NETDEV_TX_OK;
1da177e4
LT		 2298}
2299
2300/* Stops the kernel queue, and halts the controller */
2301static int gfar_close(struct net_device *dev)
2302{
2303 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2304
46ceb60c 2305 disable_napi(priv);
bea3348e 2306
ab939905 2307 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2308 stop_gfar(dev);
2309
bb40dcbb
AF		 2310 /* Disconnect from the PHY */
2311 phy_disconnect(priv->phydev);
2312 priv->phydev = NULL;
1da177e4 2313
fba4ed03 2314 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2315
2316 return 0;
2317}
2318
1da177e4 2319/* Changes the mac address if the controller is not running. */
f162b9d5 2320static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2321{
7f7f5316 2322 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2323
2324 return 0;
2325}
2326
f3dc1586
SP		 2327/* Check if rx parser should be activated */
2328void gfar_check_rx_parser_mode(struct gfar_private *priv)
2329{
2330 struct gfar __iomem *regs;
2331 u32 tempval;
2332
2333 regs = priv->gfargrp[0].regs;
2334
2335 tempval = gfar_read(&regs->rctrl);
2336 /* If parse is no longer required, then disable parser */
2337 if (tempval & RCTRL_REQ_PARSER)
2338 tempval |= RCTRL_PRSDEP_INIT;
2339 else
2340 tempval &= ~RCTRL_PRSDEP_INIT;
2341 gfar_write(&regs->rctrl, tempval);
2342}
2343
0bbaf069 2344/* Enables and disables VLAN insertion/extraction */
c8f44aff 2345void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
0bbaf069
KG		 2346{
2347 struct gfar_private *priv = netdev_priv(dev);
f4983704 2348 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2349 unsigned long flags;
2350 u32 tempval;
2351
46ceb60c 2352 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2353 local_irq_save(flags);
2354 lock_rx_qs(priv);
0bbaf069 2355
87c288c6 2356 if (features & NETIF_F_HW_VLAN_TX) {
0bbaf069 2357 /* Enable VLAN tag insertion */
f4983704 2358 tempval = gfar_read(&regs->tctrl);
0bbaf069 2359 tempval |= TCTRL_VLINS;
f4983704 2360 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2361 } else {
2362 /* Disable VLAN tag insertion */
f4983704 2363 tempval = gfar_read(&regs->tctrl);
0bbaf069 2364 tempval &= ~TCTRL_VLINS;
f4983704 2365 gfar_write(&regs->tctrl, tempval);
87c288c6 2366 }
0bbaf069 2367
87c288c6
JP		 2368 if (features & NETIF_F_HW_VLAN_RX) {
2369 /* Enable VLAN tag extraction */
2370 tempval = gfar_read(&regs->rctrl);
2371 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2372 gfar_write(&regs->rctrl, tempval);
2373 } else {
0bbaf069 2374 /* Disable VLAN tag extraction */
f4983704 2375 tempval = gfar_read(&regs->rctrl);
0bbaf069 2376 tempval &= ~RCTRL_VLEX;
f4983704 2377 gfar_write(&regs->rctrl, tempval);
f3dc1586
SP		 2378
2379 gfar_check_rx_parser_mode(priv);
0bbaf069
KG		 2380 }
2381
77ecaf2d
DH		 2382 gfar_change_mtu(dev, dev->mtu);
2383
fba4ed03
SG		 2384 unlock_rx_qs(priv);
2385 local_irq_restore(flags);
0bbaf069
KG		 2386}
2387
1da177e4
LT		 2388static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2389{
2390 int tempsize, tempval;
2391 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2392 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2393 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2394 int frame_size = new_mtu + ETH_HLEN;
2395
87c288c6 2396 if (gfar_is_vlan_on(priv))
faa89577 2397 frame_size += VLAN_HLEN;
0bbaf069 2398
1da177e4 2399 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2400 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2401 return -EINVAL;
2402 }
2403
77ecaf2d
DH		 2404 if (gfar_uses_fcb(priv))
2405 frame_size += GMAC_FCB_LEN;
2406
2407 frame_size += priv->padding;
2408
bc4598bc
JC		 2409 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2410 INCREMENTAL_BUFFER_SIZE;
1da177e4
LT		 2411
2412 /* Only stop and start the controller if it isn't already
0977f817
JC		 2413 * stopped, and we changed something
2414 */
1da177e4
LT		 2415 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2416 stop_gfar(dev);
2417
2418 priv->rx_buffer_size = tempsize;
2419
2420 dev->mtu = new_mtu;
2421
f4983704
SG		 2422 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2423 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2424
2425 /* If the mtu is larger than the max size for standard
2426 * ethernet frames (ie, a jumbo frame), then set maccfg2
0977f817
JC		 2427 * to allow huge frames, and to check the length
2428 */
f4983704 2429 tempval = gfar_read(&regs->maccfg2);
1da177e4 2430
7d350977 2431 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
bc4598bc 2432 gfar_has_errata(priv, GFAR_ERRATA_74))
1da177e4
LT		 2433 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2434 else
2435 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2436
f4983704 2437 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2438
2439 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2440 startup_gfar(dev);
2441
2442 return 0;
2443}
2444
ab939905 2445/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2446 * transmitted after a set amount of time.
2447 * For now, assume that clearing out all the structures, and
ab939905
SS		 2448 * starting over will fix the problem.
2449 */
2450static void gfar_reset_task(struct work_struct *work)
1da177e4 2451{
ab939905 2452 struct gfar_private *priv = container_of(work, struct gfar_private,
bc4598bc 2453 reset_task);
4826857f 2454 struct net_device *dev = priv->ndev;
1da177e4
LT		 2455
2456 if (dev->flags & IFF_UP) {
fba4ed03 2457 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2458 stop_gfar(dev);
2459 startup_gfar(dev);
fba4ed03 2460 netif_tx_start_all_queues(dev);
1da177e4
LT		 2461 }
2462
263ba320 2463 netif_tx_schedule_all(dev);
1da177e4
LT		 2464}
2465
ab939905
SS		 2466static void gfar_timeout(struct net_device *dev)
2467{
2468 struct gfar_private *priv = netdev_priv(dev);
2469
2470 dev->stats.tx_errors++;
2471 schedule_work(&priv->reset_task);
2472}
2473
acbc0f03
EL		 2474static void gfar_align_skb(struct sk_buff *skb)
2475{
2476 /* We need the data buffer to be aligned properly. We will reserve
2477 * as many bytes as needed to align the data properly
2478 */
2479 skb_reserve(skb, RXBUF_ALIGNMENT -
bc4598bc 2480 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
acbc0f03
EL		 2481}
2482
1da177e4 2483/* Interrupt Handler for Transmit complete */
a12f801d 2484static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2485{
a12f801d 2486 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2487 struct netdev_queue *txq;
d080cd63 2488 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2489 struct gfar_priv_rx_q *rx_queue = NULL;
f0ee7acf 2490 struct txbd8 *bdp, *next = NULL;
4669bc90 2491 struct txbd8 *lbdp = NULL;
a12f801d 2492 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2493 struct sk_buff *skb;
2494 int skb_dirtytx;
a12f801d 2495 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2496 int frags = 0, nr_txbds = 0;
4669bc90 2497 int i;
d080cd63 2498 int howmany = 0;
d8a0f1b0
PG		 2499 int tqi = tx_queue->qindex;
2500 unsigned int bytes_sent = 0;
4669bc90 2501 u32 lstatus;
f0ee7acf 2502 size_t buflen;
1da177e4 2503
d8a0f1b0
PG		 2504 rx_queue = priv->rx_queue[tqi];
2505 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2506 bdp = tx_queue->dirty_tx;
2507 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2508
a12f801d 2509 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2510 unsigned long flags;
2511
4669bc90 2512 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf 2513
0977f817 2514 /* When time stamping, one additional TxBD must be freed.
f0ee7acf
MR		 2515 * Also, we need to dma_unmap_single() the TxPAL.
2516 */
2244d07b 2517 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2518 nr_txbds = frags + 2;
2519 else
2520 nr_txbds = frags + 1;
2521
2522 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2523
4669bc90 2524 lstatus = lbdp->lstatus;
1da177e4 2525
4669bc90
DH		 2526 /* Only clean completed frames */
2527 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
bc4598bc 2528 (lstatus & BD_LENGTH_MASK))
4669bc90
DH		 2529 break;
2530
2244d07b 2531 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2532 next = next_txbd(bdp, base, tx_ring_size);
9c4886e5 2533 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf
MR		 2534 } else
2535 buflen = bdp->length;
2536
2537 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
bc4598bc 2538 buflen, DMA_TO_DEVICE);
f0ee7acf 2539
2244d07b 2540 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2541 struct skb_shared_hwtstamps shhwtstamps;
2542 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
bc4598bc 2543
f0ee7acf
MR		 2544 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2545 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
9c4886e5 2546 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf
MR		 2547 skb_tstamp_tx(skb, &shhwtstamps);
2548 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2549 bdp = next;
2550 }
81183059 2551
4669bc90
DH		 2552 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2553 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2554
4669bc90 2555 for (i = 0; i < frags; i++) {
bc4598bc
JC		 2556 dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2557 bdp->length, DMA_TO_DEVICE);
4669bc90
DH		 2558 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2559 bdp = next_txbd(bdp, base, tx_ring_size);
2560 }
1da177e4 2561
d8a0f1b0
PG		 2562 bytes_sent += skb->len;
2563
acb600de 2564 dev_kfree_skb_any(skb);
0fd56bb5 2565
a12f801d 2566 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2567
4669bc90 2568 skb_dirtytx = (skb_dirtytx + 1) &
bc4598bc 2569 TX_RING_MOD_MASK(tx_ring_size);
4669bc90
DH		 2570
2571 howmany++;
a3bc1f11 2572 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2573 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2574 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2575 }
1da177e4 2576
4669bc90 2577 /* If we freed a buffer, we can restart transmission, if necessary */
5407b14c 2578 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
d8a0f1b0 2579 netif_wake_subqueue(dev, tqi);
1da177e4 2580
4669bc90 2581 /* Update dirty indicators */
a12f801d
SG		 2582 tx_queue->skb_dirtytx = skb_dirtytx;
2583 tx_queue->dirty_tx = bdp;
1da177e4 2584
d8a0f1b0
PG		 2585 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2586
d080cd63
DH		 2587 return howmany;
2588}
2589
f4983704 2590static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2591{
a6d0b91a
AV		 2592 unsigned long flags;
2593
fba4ed03
SG		 2594 spin_lock_irqsave(&gfargrp->grplock, flags);
2595 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2596 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2597 __napi_schedule(&gfargrp->napi);
8707bdd4 2598 } else {
0977f817 2599 /* Clear IEVENT, so interrupts aren't called again
8707bdd4
JP		 2600 * because of the packets that have already arrived.
2601 */
f4983704 2602 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2603 }
fba4ed03 2604 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2605
8c7396ae 2606}
1da177e4 2607
8c7396ae 2608/* Interrupt Handler for Transmit complete */
f4983704 2609static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2610{
f4983704 2611 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2612 return IRQ_HANDLED;
2613}
2614
a12f801d 2615static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
bc4598bc 2616 struct sk_buff *skb)
815b97c6 2617{
a12f801d 2618 struct net_device *dev = rx_queue->dev;
815b97c6 2619 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2620 dma_addr_t buf;
815b97c6 2621
8a102fe0
AV		 2622 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2623 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2624 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2625}
2626
2281a0f3 2627static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2628{
2629 struct gfar_private *priv = netdev_priv(dev);
acb600de 2630 struct sk_buff *skb;
1da177e4 2631
acbc0f03 2632 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2633 if (!skb)
1da177e4
LT		 2634 return NULL;
2635
acbc0f03 2636 gfar_align_skb(skb);
7f7f5316 2637
acbc0f03
EL		 2638 return skb;
2639}
2640
2281a0f3 2641struct sk_buff *gfar_new_skb(struct net_device *dev)
acbc0f03 2642{
acb600de 2643 return gfar_alloc_skb(dev);
1da177e4
LT		 2644}
2645
298e1a9e 2646static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2647{
298e1a9e 2648 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2649 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2650 struct gfar_extra_stats *estats = &priv->extra_stats;
2651
0977f817 2652 /* If the packet was truncated, none of the other errors matter */
1da177e4
LT		 2653 if (status & RXBD_TRUNCATED) {
2654 stats->rx_length_errors++;
2655
2656 estats->rx_trunc++;
2657
2658 return;
2659 }
2660 /* Count the errors, if there were any */
2661 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2662 stats->rx_length_errors++;
2663
2664 if (status & RXBD_LARGE)
2665 estats->rx_large++;
2666 else
2667 estats->rx_short++;
2668 }
2669 if (status & RXBD_NONOCTET) {
2670 stats->rx_frame_errors++;
2671 estats->rx_nonoctet++;
2672 }
2673 if (status & RXBD_CRCERR) {
2674 estats->rx_crcerr++;
2675 stats->rx_crc_errors++;
2676 }
2677 if (status & RXBD_OVERRUN) {
2678 estats->rx_overrun++;
2679 stats->rx_crc_errors++;
2680 }
2681}
2682
f4983704 2683irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2684{
f4983704 2685 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2686 return IRQ_HANDLED;
2687}
2688
0bbaf069
KG		 2689static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2690{
2691 /* If valid headers were found, and valid sums
2692 * were verified, then we tell the kernel that no
0977f817
JC		 2693 * checksumming is necessary. Otherwise, it is [FIXME]
2694 */
7f7f5316 2695 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2696 skb->ip_summed = CHECKSUM_UNNECESSARY;
2697 else
bc8acf2c 2698 skb_checksum_none_assert(skb);
0bbaf069
KG		 2699}
2700
2701
0977f817 2702/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
1da177e4 2703static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
cd754a57 2704 int amount_pull, struct napi_struct *napi)
1da177e4
LT		 2705{
2706 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2707 struct rxfcb *fcb = NULL;
1da177e4 2708
cd754a57 2709 gro_result_t ret;
1da177e4 2710
2c2db48a
DH		 2711 /* fcb is at the beginning if exists */
2712 fcb = (struct rxfcb *)skb->data;
0bbaf069 2713
0977f817
JC		 2714 /* Remove the FCB from the skb
2715 * Remove the padded bytes, if there are any
2716 */
f74dac08
SG		 2717 if (amount_pull) {
2718 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2719 skb_pull(skb, amount_pull);
f74dac08 2720 }
0bbaf069 2721
cc772ab7
MR		 2722 /* Get receive timestamp from the skb */
2723 if (priv->hwts_rx_en) {
2724 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2725 u64 *ns = (u64 *) skb->data;
bc4598bc 2726
cc772ab7
MR		 2727 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2728 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2729 }
2730
2731 if (priv->padding)
2732 skb_pull(skb, priv->padding);
2733
8b3afe95 2734 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2735 gfar_rx_checksum(skb, fcb);
0bbaf069 2736
2c2db48a
DH		 2737 /* Tell the skb what kind of packet this is */
2738 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2739
0977f817 2740 /* There's need to check for NETIF_F_HW_VLAN_RX here.
32f7fd44
JP		 2741 * Even if vlan rx accel is disabled, on some chips
2742 * RXFCB_VLN is pseudo randomly set.
2743 */
2744 if (dev->features & NETIF_F_HW_VLAN_RX &&
2745 fcb->flags & RXFCB_VLN)
87c288c6
JP		 2746 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2747
2c2db48a 2748 /* Send the packet up the stack */
cd754a57 2749 ret = napi_gro_receive(napi, skb);
0bbaf069 2750
cd754a57 2751 if (GRO_DROP == ret)
2c2db48a 2752 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2753
2754 return 0;
2755}
2756
2757/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2281a0f3
JC		 2758 * until the budget/quota has been reached. Returns the number
2759 * of frames handled
1da177e4 2760 */
a12f801d 2761int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2762{
a12f801d 2763 struct net_device *dev = rx_queue->dev;
31de198b 2764 struct rxbd8 *bdp, *base;
1da177e4 2765 struct sk_buff *skb;
2c2db48a
DH		 2766 int pkt_len;
2767 int amount_pull;
1da177e4
LT		 2768 int howmany = 0;
2769 struct gfar_private *priv = netdev_priv(dev);
2770
2771 /* Get the first full descriptor */
a12f801d
SG		 2772 bdp = rx_queue->cur_rx;
2773 base = rx_queue->rx_bd_base;
1da177e4 2774
cc772ab7 2775 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2c2db48a 2776
1da177e4 2777 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2778 struct sk_buff *newskb;
bc4598bc 2779
3b6330ce 2780 rmb();
815b97c6
AF		 2781
2782 /* Add another skb for the future */
2783 newskb = gfar_new_skb(dev);
2784
a12f801d 2785 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2786
4826857f 2787 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
bc4598bc 2788 priv->rx_buffer_size, DMA_FROM_DEVICE);
81183059 2789
63b88b90 2790 if (unlikely(!(bdp->status & RXBD_ERR) &&
bc4598bc 2791 bdp->length > priv->rx_buffer_size))
63b88b90
AV		 2792 bdp->status = RXBD_LARGE;
2793
815b97c6
AF		 2794 /* We drop the frame if we failed to allocate a new buffer */
2795 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
bc4598bc 2796 bdp->status & RXBD_ERR)) {
815b97c6
AF		 2797 count_errors(bdp->status, dev);
2798
2799 if (unlikely(!newskb))
2800 newskb = skb;
acbc0f03 2801 else if (skb)
acb600de 2802 dev_kfree_skb(skb);
815b97c6 2803 } else {
1da177e4 2804 /* Increment the number of packets */
a7f38041 2805 rx_queue->stats.rx_packets++;
1da177e4
LT		 2806 howmany++;
2807
2c2db48a
DH		 2808 if (likely(skb)) {
2809 pkt_len = bdp->length - ETH_FCS_LEN;
2810 /* Remove the FCS from the packet length */
2811 skb_put(skb, pkt_len);
a7f38041 2812 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2813 skb_record_rx_queue(skb, rx_queue->qindex);
cd754a57 2814 gfar_process_frame(dev, skb, amount_pull,
bc4598bc 2815 &rx_queue->grp->napi);
2c2db48a
DH		 2816
2817 } else {
59deab26 2818 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2819 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2820 priv->extra_stats.rx_skbmissing++;
2821 }
1da177e4 2822
1da177e4
LT		 2823 }
2824
a12f801d 2825 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2826
815b97c6 2827 /* Setup the new bdp */
a12f801d 2828 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2829
2830 /* Update to the next pointer */
a12f801d 2831 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2832
2833 /* update to point at the next skb */
bc4598bc
JC		 2834 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2835 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2836 }
2837
2838 /* Update the current rxbd pointer to be the next one */
a12f801d 2839 rx_queue->cur_rx = bdp;
1da177e4 2840
1da177e4
LT		 2841 return howmany;
2842}
2843
bea3348e 2844static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2845{
bc4598bc
JC		 2846 struct gfar_priv_grp *gfargrp =
2847 container_of(napi, struct gfar_priv_grp, napi);
fba4ed03 2848 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2849 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2850 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2851 struct gfar_priv_rx_q *rx_queue = NULL;
2852 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2853 int tx_cleaned = 0, i, left_over_budget = budget;
2854 unsigned long serviced_queues = 0;
fba4ed03 2855 int num_queues = 0;
d080cd63 2856
fba4ed03
SG		 2857 num_queues = gfargrp->num_rx_queues;
2858 budget_per_queue = budget/num_queues;
2859
8c7396ae 2860 /* Clear IEVENT, so interrupts aren't called again
0977f817
JC		 2861 * because of the packets that have already arrived
2862 */
f4983704 2863 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2864
fba4ed03 2865 while (num_queues && left_over_budget) {
fba4ed03
SG		 2866 budget_per_queue = left_over_budget/num_queues;
2867 left_over_budget = 0;
2868
984b3f57 2869 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2870 if (test_bit(i, &serviced_queues))
2871 continue;
2872 rx_queue = priv->rx_queue[i];
2873 tx_queue = priv->tx_queue[rx_queue->qindex];
2874
a3bc1f11 2875 tx_cleaned += gfar_clean_tx_ring(tx_queue);
bc4598bc
JC		 2876 rx_cleaned_per_queue =
2877 gfar_clean_rx_ring(rx_queue, budget_per_queue);
fba4ed03 2878 rx_cleaned += rx_cleaned_per_queue;
bc4598bc 2879 if (rx_cleaned_per_queue < budget_per_queue) {
fba4ed03 2880 left_over_budget = left_over_budget +
bc4598bc
JC		 2881 (budget_per_queue -
2882 rx_cleaned_per_queue);
fba4ed03
SG		 2883 set_bit(i, &serviced_queues);
2884 num_queues--;
2885 }
2886 }
2887 }
1da177e4 2888
42199884
AF		 2889 if (tx_cleaned)
2890 return budget;
2891
2892 if (rx_cleaned < budget) {
288379f0 2893 napi_complete(napi);
1da177e4
LT		 2894
2895 /* Clear the halt bit in RSTAT */
fba4ed03 2896 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2897
f4983704 2898 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4 2899
0977f817
JC		 2900 /* If we are coalescing interrupts, update the timer
2901 * Otherwise, clear it
2902 */
bc4598bc
JC		 2903 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2904 gfargrp->tx_bit_map);
1da177e4
LT		 2905 }
2906
42199884 2907 return rx_cleaned;
1da177e4 2908}
1da177e4 2909
f2d71c2d 2910#ifdef CONFIG_NET_POLL_CONTROLLER
0977f817 2911/* Polling 'interrupt' - used by things like netconsole to send skbs
f2d71c2d
VW		 2912 * without having to re-enable interrupts. It's not called while
2913 * the interrupt routine is executing.
2914 */
2915static void gfar_netpoll(struct net_device *dev)
2916{
2917 struct gfar_private *priv = netdev_priv(dev);
3a2e16c8 2918 int i;
f2d71c2d
VW		 2919
2920 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2921 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2922 for (i = 0; i < priv->num_grps; i++) {
2923 disable_irq(priv->gfargrp[i].interruptTransmit);
2924 disable_irq(priv->gfargrp[i].interruptReceive);
2925 disable_irq(priv->gfargrp[i].interruptError);
2926 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
bc4598bc 2927 &priv->gfargrp[i]);
46ceb60c
SG		 2928 enable_irq(priv->gfargrp[i].interruptError);
2929 enable_irq(priv->gfargrp[i].interruptReceive);
2930 enable_irq(priv->gfargrp[i].interruptTransmit);
2931 }
f2d71c2d 2932 } else {
46ceb60c
SG		 2933 for (i = 0; i < priv->num_grps; i++) {
2934 disable_irq(priv->gfargrp[i].interruptTransmit);
2935 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
bc4598bc 2936 &priv->gfargrp[i]);
46ceb60c 2937 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2938 }
f2d71c2d
VW		 2939 }
2940}
2941#endif
2942
1da177e4 2943/* The interrupt handler for devices with one interrupt */
f4983704 2944static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2945{
f4983704 2946 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2947
2948 /* Save ievent for future reference */
f4983704 2949 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2950
1da177e4 2951 /* Check for reception */
538cc7ee 2952 if (events & IEVENT_RX_MASK)
f4983704 2953 gfar_receive(irq, grp_id);
1da177e4
LT		 2954
2955 /* Check for transmit completion */
538cc7ee 2956 if (events & IEVENT_TX_MASK)
f4983704 2957 gfar_transmit(irq, grp_id);
1da177e4 2958
538cc7ee
SS		 2959 /* Check for errors */
2960 if (events & IEVENT_ERR_MASK)
f4983704 2961 gfar_error(irq, grp_id);
1da177e4
LT		 2962
2963 return IRQ_HANDLED;
2964}
2965
1da177e4
LT		 2966/* Called every time the controller might need to be made
2967 * aware of new link state. The PHY code conveys this
bb40dcbb 2968 * information through variables in the phydev structure, and this
1da177e4
LT		 2969 * function converts those variables into the appropriate
2970 * register values, and can bring down the device if needed.
2971 */
2972static void adjust_link(struct net_device *dev)
2973{
2974 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2975 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2976 unsigned long flags;
2977 struct phy_device *phydev = priv->phydev;
2978 int new_state = 0;
2979
fba4ed03
SG		 2980 local_irq_save(flags);
2981 lock_tx_qs(priv);
2982
bb40dcbb
AF		 2983 if (phydev->link) {
2984 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2985 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2986
1da177e4 2987 /* Now we make sure that we can be in full duplex mode.
0977f817
JC		 2988 * If not, we operate in half-duplex mode.
2989 */
bb40dcbb
AF		 2990 if (phydev->duplex != priv->oldduplex) {
2991 new_state = 1;
2992 if (!(phydev->duplex))
1da177e4 2993 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2994 else
1da177e4 2995 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2996
bb40dcbb 2997 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2998 }
2999
bb40dcbb
AF		 3000 if (phydev->speed != priv->oldspeed) {
3001 new_state = 1;
3002 switch (phydev->speed) {
1da177e4 3003 case 1000:
1da177e4
LT		 3004 tempval =
3005 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 3006
3007 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 3008 break;
3009 case 100:
3010 case 10:
1da177e4
LT		 3011 tempval =
3012 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 3013
3014 /* Reduced mode distinguishes
0977f817
JC		 3015 * between 10 and 100
3016 */
7f7f5316
AF		 3017 if (phydev->speed == SPEED_100)
3018 ecntrl |= ECNTRL_R100;
3019 else
3020 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 3021 break;
3022 default:
59deab26
JP		 3023 netif_warn(priv, link, dev,
3024 "Ack! Speed (%d) is not 10/100/1000!\n",
3025 phydev->speed);
1da177e4
LT		 3026 break;
3027 }
3028
bb40dcbb 3029 priv->oldspeed = phydev->speed;
1da177e4
LT		 3030 }
3031
bb40dcbb 3032 gfar_write(&regs->maccfg2, tempval);
7f7f5316 3033 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 3034
1da177e4 3035 if (!priv->oldlink) {
bb40dcbb 3036 new_state = 1;
1da177e4 3037 priv->oldlink = 1;
1da177e4 3038 }
bb40dcbb
AF		 3039 } else if (priv->oldlink) {
3040 new_state = 1;
3041 priv->oldlink = 0;
3042 priv->oldspeed = 0;
3043 priv->oldduplex = -1;
1da177e4 3044 }
1da177e4 3045
bb40dcbb
AF		 3046 if (new_state && netif_msg_link(priv))
3047 phy_print_status(phydev);
fba4ed03
SG		 3048 unlock_tx_qs(priv);
3049 local_irq_restore(flags);
bb40dcbb 3050}
1da177e4
LT		 3051
3052/* Update the hash table based on the current list of multicast
3053 * addresses we subscribe to. Also, change the promiscuity of
3054 * the device based on the flags (this function is called
0977f817
JC		 3055 * whenever dev->flags is changed
3056 */
1da177e4
LT		 3057static void gfar_set_multi(struct net_device *dev)
3058{
22bedad3 3059 struct netdev_hw_addr *ha;
1da177e4 3060 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3061 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3062 u32 tempval;
3063
a12f801d 3064 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3065 /* Set RCTRL to PROM */
3066 tempval = gfar_read(&regs->rctrl);
3067 tempval |= RCTRL_PROM;
3068 gfar_write(&regs->rctrl, tempval);
3069 } else {
3070 /* Set RCTRL to not PROM */
3071 tempval = gfar_read(&regs->rctrl);
3072 tempval &= ~(RCTRL_PROM);
3073 gfar_write(&regs->rctrl, tempval);
3074 }
6aa20a22 3075
a12f801d 3076 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3077 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3078 gfar_write(&regs->igaddr0, 0xffffffff);
3079 gfar_write(&regs->igaddr1, 0xffffffff);
3080 gfar_write(&regs->igaddr2, 0xffffffff);
3081 gfar_write(&regs->igaddr3, 0xffffffff);
3082 gfar_write(&regs->igaddr4, 0xffffffff);
3083 gfar_write(&regs->igaddr5, 0xffffffff);
3084 gfar_write(&regs->igaddr6, 0xffffffff);
3085 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3086 gfar_write(&regs->gaddr0, 0xffffffff);
3087 gfar_write(&regs->gaddr1, 0xffffffff);
3088 gfar_write(&regs->gaddr2, 0xffffffff);
3089 gfar_write(&regs->gaddr3, 0xffffffff);
3090 gfar_write(&regs->gaddr4, 0xffffffff);
3091 gfar_write(&regs->gaddr5, 0xffffffff);
3092 gfar_write(&regs->gaddr6, 0xffffffff);
3093 gfar_write(&regs->gaddr7, 0xffffffff);
3094 } else {
7f7f5316
AF		 3095 int em_num;
3096 int idx;
3097
1da177e4 3098 /* zero out the hash */
0bbaf069
KG		 3099 gfar_write(&regs->igaddr0, 0x0);
3100 gfar_write(&regs->igaddr1, 0x0);
3101 gfar_write(&regs->igaddr2, 0x0);
3102 gfar_write(&regs->igaddr3, 0x0);
3103 gfar_write(&regs->igaddr4, 0x0);
3104 gfar_write(&regs->igaddr5, 0x0);
3105 gfar_write(&regs->igaddr6, 0x0);
3106 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3107 gfar_write(&regs->gaddr0, 0x0);
3108 gfar_write(&regs->gaddr1, 0x0);
3109 gfar_write(&regs->gaddr2, 0x0);
3110 gfar_write(&regs->gaddr3, 0x0);
3111 gfar_write(&regs->gaddr4, 0x0);
3112 gfar_write(&regs->gaddr5, 0x0);
3113 gfar_write(&regs->gaddr6, 0x0);
3114 gfar_write(&regs->gaddr7, 0x0);
3115
7f7f5316
AF		 3116 /* If we have extended hash tables, we need to
3117 * clear the exact match registers to prepare for
0977f817
JC		 3118 * setting them
3119 */
7f7f5316
AF		 3120 if (priv->extended_hash) {
3121 em_num = GFAR_EM_NUM + 1;
3122 gfar_clear_exact_match(dev);
3123 idx = 1;
3124 } else {
3125 idx = 0;
3126 em_num = 0;
3127 }
3128
4cd24eaf 3129 if (netdev_mc_empty(dev))
1da177e4
LT		 3130 return;
3131
3132 /* Parse the list, and set the appropriate bits */
22bedad3 3133 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3134 if (idx < em_num) {
22bedad3 3135 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3136 idx++;
3137 } else
22bedad3 3138 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3139 }
3140 }
1da177e4
LT		 3141}
3142
7f7f5316
AF		 3143
3144/* Clears each of the exact match registers to zero, so they
0977f817
JC		 3145 * don't interfere with normal reception
3146 */
7f7f5316
AF		 3147static void gfar_clear_exact_match(struct net_device *dev)
3148{
3149 int idx;
6a3c910c 3150 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316 3151
bc4598bc 3152 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
b6bc7650 3153 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3154}
3155
1da177e4
LT		 3156/* Set the appropriate hash bit for the given addr */
3157/* The algorithm works like so:
3158 * 1) Take the Destination Address (ie the multicast address), and
3159 * do a CRC on it (little endian), and reverse the bits of the
3160 * result.
3161 * 2) Use the 8 most significant bits as a hash into a 256-entry
3162 * table. The table is controlled through 8 32-bit registers:
3163 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3164 * gaddr7. This means that the 3 most significant bits in the
3165 * hash index which gaddr register to use, and the 5 other bits
3166 * indicate which bit (assuming an IBM numbering scheme, which
3167 * for PowerPC (tm) is usually the case) in the register holds
0977f817
JC		 3168 * the entry.
3169 */
1da177e4
LT		 3170static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3171{
3172 u32 tempval;
3173 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3174 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3175 int width = priv->hash_width;
3176 u8 whichbit = (result >> (32 - width)) & 0x1f;
3177 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3178 u32 value = (1 << (31-whichbit));
3179
0bbaf069 3180 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3181 tempval |= value;
0bbaf069 3182 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3183}
3184
7f7f5316
AF		 3185
3186/* There are multiple MAC Address register pairs on some controllers
3187 * This function sets the numth pair to a given address
3188 */
b6bc7650
JP		 3189static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3190 const u8 *addr)
7f7f5316
AF		 3191{
3192 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3193 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3194 int idx;
6a3c910c 3195 char tmpbuf[ETH_ALEN];
7f7f5316 3196 u32 tempval;
f4983704 3197 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3198
3199 macptr += num*2;
3200
0977f817
JC		 3201 /* Now copy it into the mac registers backwards, cuz
3202 * little endian is silly
3203 */
6a3c910c
JP		 3204 for (idx = 0; idx < ETH_ALEN; idx++)
3205 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
7f7f5316
AF		 3206
3207 gfar_write(macptr, *((u32 *) (tmpbuf)));
3208
3209 tempval = *((u32 *) (tmpbuf + 4));
3210
3211 gfar_write(macptr+1, tempval);
3212}
3213
1da177e4 3214/* GFAR error interrupt handler */
f4983704 3215static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3216{
f4983704
SG		 3217 struct gfar_priv_grp *gfargrp = grp_id;
3218 struct gfar __iomem *regs = gfargrp->regs;
3219 struct gfar_private *priv= gfargrp->priv;
3220 struct net_device *dev = priv->ndev;
1da177e4
LT		 3221
3222 /* Save ievent for future reference */
f4983704 3223 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3224
3225 /* Clear IEVENT */
f4983704 3226 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3227
3228 /* Magic Packet is not an error. */
b31a1d8b 3229 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3230 (events & IEVENT_MAG))
3231 events &= ~IEVENT_MAG;
1da177e4
LT		 3232
3233 /* Hmm... */
0bbaf069 3234 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
bc4598bc
JC		 3235 netdev_dbg(dev,
3236 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
59deab26 3237 events, gfar_read(&regs->imask));
1da177e4
LT		 3238
3239 /* Update the error counters */
3240 if (events & IEVENT_TXE) {
09f75cd7 3241 dev->stats.tx_errors++;
1da177e4
LT		 3242
3243 if (events & IEVENT_LC)
09f75cd7 3244 dev->stats.tx_window_errors++;
1da177e4 3245 if (events & IEVENT_CRL)
09f75cd7 3246 dev->stats.tx_aborted_errors++;
1da177e4 3247 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3248 unsigned long flags;
3249
59deab26
JP		 3250 netif_dbg(priv, tx_err, dev,
3251 "TX FIFO underrun, packet dropped\n");
09f75cd7 3252 dev->stats.tx_dropped++;
1da177e4
LT		 3253 priv->extra_stats.tx_underrun++;
3254
836cf7fa
AV		 3255 local_irq_save(flags);
3256 lock_tx_qs(priv);
3257
1da177e4 3258 /* Reactivate the Tx Queues */
fba4ed03 3259 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3260
3261 unlock_tx_qs(priv);
3262 local_irq_restore(flags);
1da177e4 3263 }
59deab26 3264 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3265 }
3266 if (events & IEVENT_BSY) {
09f75cd7 3267 dev->stats.rx_errors++;
1da177e4
LT		 3268 priv->extra_stats.rx_bsy++;
3269
f4983704 3270 gfar_receive(irq, grp_id);
1da177e4 3271
59deab26
JP		 3272 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3273 gfar_read(&regs->rstat));
1da177e4
LT		 3274 }
3275 if (events & IEVENT_BABR) {
09f75cd7 3276 dev->stats.rx_errors++;
1da177e4
LT		 3277 priv->extra_stats.rx_babr++;
3278
59deab26 3279 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3280 }
3281 if (events & IEVENT_EBERR) {
3282 priv->extra_stats.eberr++;
59deab26 3283 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3284 }
59deab26
JP		 3285 if (events & IEVENT_RXC)
3286 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3287
3288 if (events & IEVENT_BABT) {
3289 priv->extra_stats.tx_babt++;
59deab26 3290 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3291 }
3292 return IRQ_HANDLED;
3293}
3294
b31a1d8b
AF		 3295static struct of_device_id gfar_match[] =
3296{
3297 {
3298 .type = "network",
3299 .compatible = "gianfar",
3300 },
46ceb60c
SG		 3301 {
3302 .compatible = "fsl,etsec2",
3303 },
b31a1d8b
AF		 3304 {},
3305};
e72701ac 3306MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3307
1da177e4 3308/* Structure for a device driver */
74888760 3309static struct platform_driver gfar_driver = {
4018294b
GL		 3310 .driver = {
3311 .name = "fsl-gianfar",
3312 .owner = THIS_MODULE,
3313 .pm = GFAR_PM_OPS,
3314 .of_match_table = gfar_match,
3315 },
1da177e4
LT		 3316 .probe = gfar_probe,
3317 .remove = gfar_remove,
3318};
3319
db62f684 3320module_platform_driver(gfar_driver);
Linux 6.x block layer and io_uring tree(s)