Commit | Line | Data |
---|---|---|
0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
20862788 | 12 | * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
1da177e4 LT |
73 | #include <linux/delay.h> |
74 | #include <linux/netdevice.h> | |
75 | #include <linux/etherdevice.h> | |
76 | #include <linux/skbuff.h> | |
0bbaf069 | 77 | #include <linux/if_vlan.h> |
1da177e4 LT |
78 | #include <linux/spinlock.h> |
79 | #include <linux/mm.h> | |
5af50730 RH |
80 | #include <linux/of_address.h> |
81 | #include <linux/of_irq.h> | |
fe192a49 | 82 | #include <linux/of_mdio.h> |
b31a1d8b | 83 | #include <linux/of_platform.h> |
0bbaf069 KG |
84 | #include <linux/ip.h> |
85 | #include <linux/tcp.h> | |
86 | #include <linux/udp.h> | |
9c07b884 | 87 | #include <linux/in.h> |
cc772ab7 | 88 | #include <linux/net_tstamp.h> |
1da177e4 LT |
89 | |
90 | #include <asm/io.h> | |
7d350977 | 91 | #include <asm/reg.h> |
2969b1f7 | 92 | #include <asm/mpc85xx.h> |
1da177e4 LT |
93 | #include <asm/irq.h> |
94 | #include <asm/uaccess.h> | |
95 | #include <linux/module.h> | |
1da177e4 LT |
96 | #include <linux/dma-mapping.h> |
97 | #include <linux/crc32.h> | |
bb40dcbb AF |
98 | #include <linux/mii.h> |
99 | #include <linux/phy.h> | |
b31a1d8b AF |
100 | #include <linux/phy_fixed.h> |
101 | #include <linux/of.h> | |
4b6ba8aa | 102 | #include <linux/of_net.h> |
1da177e4 LT |
103 | |
104 | #include "gianfar.h" | |
1da177e4 LT |
105 | |
106 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 107 | |
7f7f5316 | 108 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 109 | |
1da177e4 LT |
110 | static int gfar_enet_open(struct net_device *dev); |
111 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 112 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
113 | static void gfar_timeout(struct net_device *dev); |
114 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 115 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 116 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 117 | struct sk_buff *skb); |
1da177e4 LT |
118 | static int gfar_set_mac_address(struct net_device *dev); |
119 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
120 | static irqreturn_t gfar_error(int irq, void *dev_id); |
121 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
122 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 | 123 | static void adjust_link(struct net_device *dev); |
1da177e4 | 124 | static int init_phy(struct net_device *dev); |
74888760 | 125 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 126 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 127 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
128 | static void gfar_set_multi(struct net_device *dev); |
129 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 130 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 131 | static int gfar_poll(struct napi_struct *napi, int budget); |
5eaedf31 | 132 | static int gfar_poll_sq(struct napi_struct *napi, int budget); |
f2d71c2d VW |
133 | #ifdef CONFIG_NET_POLL_CONTROLLER |
134 | static void gfar_netpoll(struct net_device *dev); | |
135 | #endif | |
a12f801d | 136 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
c233cf40 | 137 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); |
61db26c6 CM |
138 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
139 | int amount_pull, struct napi_struct *napi); | |
c10650b6 | 140 | static void gfar_halt_nodisable(struct gfar_private *priv); |
7f7f5316 | 141 | static void gfar_clear_exact_match(struct net_device *dev); |
b6bc7650 JP |
142 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
143 | const u8 *addr); | |
26ccfc37 | 144 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 145 | |
1da177e4 LT |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
a12f801d | 150 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
151 | dma_addr_t buf) |
152 | { | |
8a102fe0 AV |
153 | u32 lstatus; |
154 | ||
155 | bdp->bufPtr = buf; | |
156 | ||
157 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 158 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
159 | lstatus |= BD_LFLAG(RXBD_WRAP); |
160 | ||
161 | eieio(); | |
162 | ||
163 | bdp->lstatus = lstatus; | |
164 | } | |
165 | ||
8728327e | 166 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 167 | { |
8728327e | 168 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
169 | struct gfar_priv_tx_q *tx_queue = NULL; |
170 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
171 | struct txbd8 *txbdp; |
172 | struct rxbd8 *rxbdp; | |
fba4ed03 | 173 | int i, j; |
a12f801d | 174 | |
fba4ed03 SG |
175 | for (i = 0; i < priv->num_tx_queues; i++) { |
176 | tx_queue = priv->tx_queue[i]; | |
177 | /* Initialize some variables in our dev structure */ | |
178 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
179 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
180 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
181 | tx_queue->skb_curtx = 0; | |
182 | tx_queue->skb_dirtytx = 0; | |
183 | ||
184 | /* Initialize Transmit Descriptor Ring */ | |
185 | txbdp = tx_queue->tx_bd_base; | |
186 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
187 | txbdp->lstatus = 0; | |
188 | txbdp->bufPtr = 0; | |
189 | txbdp++; | |
190 | } | |
8728327e | 191 | |
fba4ed03 SG |
192 | /* Set the last descriptor in the ring to indicate wrap */ |
193 | txbdp--; | |
194 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
195 | } |
196 | ||
fba4ed03 SG |
197 | for (i = 0; i < priv->num_rx_queues; i++) { |
198 | rx_queue = priv->rx_queue[i]; | |
199 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
200 | rx_queue->skb_currx = 0; | |
201 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 202 | |
fba4ed03 SG |
203 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
204 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 205 | |
fba4ed03 SG |
206 | if (skb) { |
207 | gfar_init_rxbdp(rx_queue, rxbdp, | |
208 | rxbdp->bufPtr); | |
209 | } else { | |
210 | skb = gfar_new_skb(ndev); | |
211 | if (!skb) { | |
59deab26 | 212 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
1eb8f7a7 | 213 | return -ENOMEM; |
fba4ed03 SG |
214 | } |
215 | rx_queue->rx_skbuff[j] = skb; | |
216 | ||
217 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 218 | } |
8728327e | 219 | |
fba4ed03 | 220 | rxbdp++; |
8728327e AV |
221 | } |
222 | ||
8728327e AV |
223 | } |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
229 | { | |
826aa4a0 | 230 | void *vaddr; |
fba4ed03 SG |
231 | dma_addr_t addr; |
232 | int i, j, k; | |
826aa4a0 | 233 | struct gfar_private *priv = netdev_priv(ndev); |
369ec162 | 234 | struct device *dev = priv->dev; |
a12f801d SG |
235 | struct gfar_priv_tx_q *tx_queue = NULL; |
236 | struct gfar_priv_rx_q *rx_queue = NULL; | |
237 | ||
fba4ed03 SG |
238 | priv->total_tx_ring_size = 0; |
239 | for (i = 0; i < priv->num_tx_queues; i++) | |
240 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
241 | ||
242 | priv->total_rx_ring_size = 0; | |
243 | for (i = 0; i < priv->num_rx_queues; i++) | |
244 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
245 | |
246 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 247 | vaddr = dma_alloc_coherent(dev, |
d0320f75 JP |
248 | (priv->total_tx_ring_size * |
249 | sizeof(struct txbd8)) + | |
250 | (priv->total_rx_ring_size * | |
251 | sizeof(struct rxbd8)), | |
252 | &addr, GFP_KERNEL); | |
253 | if (!vaddr) | |
826aa4a0 | 254 | return -ENOMEM; |
826aa4a0 | 255 | |
fba4ed03 SG |
256 | for (i = 0; i < priv->num_tx_queues; i++) { |
257 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 258 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
259 | tx_queue->tx_bd_dma_base = addr; |
260 | tx_queue->dev = ndev; | |
261 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
262 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
263 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 264 | } |
826aa4a0 | 265 | |
826aa4a0 | 266 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
267 | for (i = 0; i < priv->num_rx_queues; i++) { |
268 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 269 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
270 | rx_queue->rx_bd_dma_base = addr; |
271 | rx_queue->dev = ndev; | |
bc4598bc JC |
272 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
273 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 274 | } |
826aa4a0 AV |
275 | |
276 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
277 | for (i = 0; i < priv->num_tx_queues; i++) { |
278 | tx_queue = priv->tx_queue[i]; | |
14f8dc49 JP |
279 | tx_queue->tx_skbuff = |
280 | kmalloc_array(tx_queue->tx_ring_size, | |
281 | sizeof(*tx_queue->tx_skbuff), | |
282 | GFP_KERNEL); | |
283 | if (!tx_queue->tx_skbuff) | |
fba4ed03 | 284 | goto cleanup; |
826aa4a0 | 285 | |
fba4ed03 SG |
286 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
287 | tx_queue->tx_skbuff[k] = NULL; | |
288 | } | |
826aa4a0 | 289 | |
fba4ed03 SG |
290 | for (i = 0; i < priv->num_rx_queues; i++) { |
291 | rx_queue = priv->rx_queue[i]; | |
14f8dc49 JP |
292 | rx_queue->rx_skbuff = |
293 | kmalloc_array(rx_queue->rx_ring_size, | |
294 | sizeof(*rx_queue->rx_skbuff), | |
295 | GFP_KERNEL); | |
296 | if (!rx_queue->rx_skbuff) | |
fba4ed03 | 297 | goto cleanup; |
fba4ed03 SG |
298 | |
299 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
300 | rx_queue->rx_skbuff[j] = NULL; | |
301 | } | |
826aa4a0 | 302 | |
8728327e AV |
303 | if (gfar_init_bds(ndev)) |
304 | goto cleanup; | |
826aa4a0 AV |
305 | |
306 | return 0; | |
307 | ||
308 | cleanup: | |
309 | free_skb_resources(priv); | |
310 | return -ENOMEM; | |
311 | } | |
312 | ||
fba4ed03 SG |
313 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
314 | { | |
46ceb60c | 315 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 316 | u32 __iomem *baddr; |
fba4ed03 SG |
317 | int i; |
318 | ||
319 | baddr = ®s->tbase0; | |
bc4598bc | 320 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 321 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 322 | baddr += 2; |
fba4ed03 SG |
323 | } |
324 | ||
325 | baddr = ®s->rbase0; | |
bc4598bc | 326 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 327 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 328 | baddr += 2; |
fba4ed03 SG |
329 | } |
330 | } | |
331 | ||
a328ac92 | 332 | static void gfar_mac_rx_config(struct gfar_private *priv) |
826aa4a0 | 333 | { |
46ceb60c | 334 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 | 335 | u32 rctrl = 0; |
fba4ed03 | 336 | |
ba779711 CM |
337 | /* set this when rx hw offload (TOE) functions are being used */ |
338 | priv->uses_rxfcb = 0; | |
339 | ||
1ccb8389 | 340 | if (priv->rx_filer_enable) { |
fba4ed03 | 341 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
342 | /* Program the RIR0 reg with the required distribution */ |
343 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
344 | } | |
826aa4a0 | 345 | |
f5ae6279 | 346 | /* Restore PROMISC mode */ |
a328ac92 | 347 | if (priv->ndev->flags & IFF_PROMISC) |
f5ae6279 CM |
348 | rctrl |= RCTRL_PROM; |
349 | ||
a328ac92 | 350 | if (priv->ndev->features & NETIF_F_RXCSUM) { |
826aa4a0 | 351 | rctrl |= RCTRL_CHECKSUMMING; |
ba779711 CM |
352 | priv->uses_rxfcb = 1; |
353 | } | |
826aa4a0 AV |
354 | |
355 | if (priv->extended_hash) { | |
356 | rctrl |= RCTRL_EXTHASH; | |
826aa4a0 AV |
357 | rctrl |= RCTRL_EMEN; |
358 | } | |
359 | ||
360 | if (priv->padding) { | |
361 | rctrl &= ~RCTRL_PAL_MASK; | |
362 | rctrl |= RCTRL_PADDING(priv->padding); | |
363 | } | |
364 | ||
97553f7f | 365 | /* Enable HW time stamping if requested from user space */ |
ba779711 | 366 | if (priv->hwts_rx_en) { |
97553f7f | 367 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; |
ba779711 CM |
368 | priv->uses_rxfcb = 1; |
369 | } | |
97553f7f | 370 | |
a328ac92 | 371 | if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { |
b852b720 | 372 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
ba779711 CM |
373 | priv->uses_rxfcb = 1; |
374 | } | |
826aa4a0 AV |
375 | |
376 | /* Init rctrl based on our settings */ | |
377 | gfar_write(®s->rctrl, rctrl); | |
a328ac92 | 378 | } |
826aa4a0 | 379 | |
a328ac92 CM |
380 | static void gfar_mac_tx_config(struct gfar_private *priv) |
381 | { | |
382 | struct gfar __iomem *regs = priv->gfargrp[0].regs; | |
383 | u32 tctrl = 0; | |
384 | ||
385 | if (priv->ndev->features & NETIF_F_IP_CSUM) | |
826aa4a0 AV |
386 | tctrl |= TCTRL_INIT_CSUM; |
387 | ||
b98b8bab CM |
388 | if (priv->prio_sched_en) |
389 | tctrl |= TCTRL_TXSCHED_PRIO; | |
390 | else { | |
391 | tctrl |= TCTRL_TXSCHED_WRRS; | |
392 | gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); | |
393 | gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); | |
394 | } | |
fba4ed03 | 395 | |
826aa4a0 | 396 | gfar_write(®s->tctrl, tctrl); |
826aa4a0 AV |
397 | } |
398 | ||
a7f38041 SG |
399 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
400 | { | |
401 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
402 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
403 | unsigned long tx_packets = 0, tx_bytes = 0; | |
3a2e16c8 | 404 | int i; |
a7f38041 SG |
405 | |
406 | for (i = 0; i < priv->num_rx_queues; i++) { | |
407 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 408 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
409 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
410 | } | |
411 | ||
412 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 413 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
414 | dev->stats.rx_dropped = rx_dropped; |
415 | ||
416 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
417 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
418 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
419 | } |
420 | ||
bc4598bc | 421 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
422 | dev->stats.tx_packets = tx_packets; |
423 | ||
424 | return &dev->stats; | |
425 | } | |
426 | ||
26ccfc37 AF |
427 | static const struct net_device_ops gfar_netdev_ops = { |
428 | .ndo_open = gfar_enet_open, | |
429 | .ndo_start_xmit = gfar_start_xmit, | |
430 | .ndo_stop = gfar_close, | |
431 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 432 | .ndo_set_features = gfar_set_features, |
afc4b13d | 433 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
434 | .ndo_tx_timeout = gfar_timeout, |
435 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 436 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
437 | .ndo_set_mac_address = eth_mac_addr, |
438 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
439 | #ifdef CONFIG_NET_POLL_CONTROLLER |
440 | .ndo_poll_controller = gfar_netpoll, | |
441 | #endif | |
442 | }; | |
443 | ||
efeddce7 CM |
444 | static void gfar_ints_disable(struct gfar_private *priv) |
445 | { | |
446 | int i; | |
447 | for (i = 0; i < priv->num_grps; i++) { | |
448 | struct gfar __iomem *regs = priv->gfargrp[i].regs; | |
449 | /* Clear IEVENT */ | |
450 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
451 | ||
452 | /* Initialize IMASK */ | |
453 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
454 | } | |
455 | } | |
456 | ||
457 | static void gfar_ints_enable(struct gfar_private *priv) | |
458 | { | |
459 | int i; | |
460 | for (i = 0; i < priv->num_grps; i++) { | |
461 | struct gfar __iomem *regs = priv->gfargrp[i].regs; | |
462 | /* Unmask the interrupts we look for */ | |
463 | gfar_write(®s->imask, IMASK_DEFAULT); | |
464 | } | |
465 | } | |
466 | ||
fba4ed03 SG |
467 | void lock_rx_qs(struct gfar_private *priv) |
468 | { | |
3a2e16c8 | 469 | int i; |
fba4ed03 SG |
470 | |
471 | for (i = 0; i < priv->num_rx_queues; i++) | |
472 | spin_lock(&priv->rx_queue[i]->rxlock); | |
473 | } | |
474 | ||
475 | void lock_tx_qs(struct gfar_private *priv) | |
476 | { | |
3a2e16c8 | 477 | int i; |
fba4ed03 SG |
478 | |
479 | for (i = 0; i < priv->num_tx_queues; i++) | |
480 | spin_lock(&priv->tx_queue[i]->txlock); | |
481 | } | |
482 | ||
483 | void unlock_rx_qs(struct gfar_private *priv) | |
484 | { | |
3a2e16c8 | 485 | int i; |
fba4ed03 SG |
486 | |
487 | for (i = 0; i < priv->num_rx_queues; i++) | |
488 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
489 | } | |
490 | ||
491 | void unlock_tx_qs(struct gfar_private *priv) | |
492 | { | |
3a2e16c8 | 493 | int i; |
fba4ed03 SG |
494 | |
495 | for (i = 0; i < priv->num_tx_queues; i++) | |
496 | spin_unlock(&priv->tx_queue[i]->txlock); | |
497 | } | |
498 | ||
20862788 CM |
499 | static int gfar_alloc_tx_queues(struct gfar_private *priv) |
500 | { | |
501 | int i; | |
502 | ||
503 | for (i = 0; i < priv->num_tx_queues; i++) { | |
504 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), | |
505 | GFP_KERNEL); | |
506 | if (!priv->tx_queue[i]) | |
507 | return -ENOMEM; | |
508 | ||
509 | priv->tx_queue[i]->tx_skbuff = NULL; | |
510 | priv->tx_queue[i]->qindex = i; | |
511 | priv->tx_queue[i]->dev = priv->ndev; | |
512 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
513 | } | |
514 | return 0; | |
515 | } | |
516 | ||
517 | static int gfar_alloc_rx_queues(struct gfar_private *priv) | |
518 | { | |
519 | int i; | |
520 | ||
521 | for (i = 0; i < priv->num_rx_queues; i++) { | |
522 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), | |
523 | GFP_KERNEL); | |
524 | if (!priv->rx_queue[i]) | |
525 | return -ENOMEM; | |
526 | ||
527 | priv->rx_queue[i]->rx_skbuff = NULL; | |
528 | priv->rx_queue[i]->qindex = i; | |
529 | priv->rx_queue[i]->dev = priv->ndev; | |
530 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
531 | } | |
532 | return 0; | |
533 | } | |
534 | ||
535 | static void gfar_free_tx_queues(struct gfar_private *priv) | |
fba4ed03 | 536 | { |
3a2e16c8 | 537 | int i; |
fba4ed03 SG |
538 | |
539 | for (i = 0; i < priv->num_tx_queues; i++) | |
540 | kfree(priv->tx_queue[i]); | |
541 | } | |
542 | ||
20862788 | 543 | static void gfar_free_rx_queues(struct gfar_private *priv) |
fba4ed03 | 544 | { |
3a2e16c8 | 545 | int i; |
fba4ed03 SG |
546 | |
547 | for (i = 0; i < priv->num_rx_queues; i++) | |
548 | kfree(priv->rx_queue[i]); | |
549 | } | |
550 | ||
46ceb60c SG |
551 | static void unmap_group_regs(struct gfar_private *priv) |
552 | { | |
3a2e16c8 | 553 | int i; |
46ceb60c SG |
554 | |
555 | for (i = 0; i < MAXGROUPS; i++) | |
556 | if (priv->gfargrp[i].regs) | |
557 | iounmap(priv->gfargrp[i].regs); | |
558 | } | |
559 | ||
ee873fda CM |
560 | static void free_gfar_dev(struct gfar_private *priv) |
561 | { | |
562 | int i, j; | |
563 | ||
564 | for (i = 0; i < priv->num_grps; i++) | |
565 | for (j = 0; j < GFAR_NUM_IRQS; j++) { | |
566 | kfree(priv->gfargrp[i].irqinfo[j]); | |
567 | priv->gfargrp[i].irqinfo[j] = NULL; | |
568 | } | |
569 | ||
570 | free_netdev(priv->ndev); | |
571 | } | |
572 | ||
46ceb60c SG |
573 | static void disable_napi(struct gfar_private *priv) |
574 | { | |
3a2e16c8 | 575 | int i; |
46ceb60c SG |
576 | |
577 | for (i = 0; i < priv->num_grps; i++) | |
578 | napi_disable(&priv->gfargrp[i].napi); | |
579 | } | |
580 | ||
581 | static void enable_napi(struct gfar_private *priv) | |
582 | { | |
3a2e16c8 | 583 | int i; |
46ceb60c SG |
584 | |
585 | for (i = 0; i < priv->num_grps; i++) | |
586 | napi_enable(&priv->gfargrp[i].napi); | |
587 | } | |
588 | ||
589 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 590 | struct gfar_private *priv, const char *model) |
46ceb60c | 591 | { |
5fedcc14 | 592 | struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; |
46ceb60c | 593 | u32 *queue_mask; |
ee873fda CM |
594 | int i; |
595 | ||
7c1e7e99 PG |
596 | for (i = 0; i < GFAR_NUM_IRQS; i++) { |
597 | grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), | |
598 | GFP_KERNEL); | |
599 | if (!grp->irqinfo[i]) | |
ee873fda | 600 | return -ENOMEM; |
ee873fda | 601 | } |
46ceb60c | 602 | |
5fedcc14 CM |
603 | grp->regs = of_iomap(np, 0); |
604 | if (!grp->regs) | |
46ceb60c SG |
605 | return -ENOMEM; |
606 | ||
ee873fda | 607 | gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); |
46ceb60c SG |
608 | |
609 | /* If we aren't the FEC we have multiple interrupts */ | |
610 | if (model && strcasecmp(model, "FEC")) { | |
ee873fda CM |
611 | gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); |
612 | gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); | |
613 | if (gfar_irq(grp, TX)->irq == NO_IRQ || | |
614 | gfar_irq(grp, RX)->irq == NO_IRQ || | |
615 | gfar_irq(grp, ER)->irq == NO_IRQ) | |
46ceb60c | 616 | return -EINVAL; |
46ceb60c SG |
617 | } |
618 | ||
5fedcc14 CM |
619 | grp->priv = priv; |
620 | spin_lock_init(&grp->grplock); | |
bc4598bc JC |
621 | if (priv->mode == MQ_MG_MODE) { |
622 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
5fedcc14 | 623 | grp->rx_bit_map = queue_mask ? |
bc4598bc JC |
624 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
625 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
5fedcc14 | 626 | grp->tx_bit_map = queue_mask ? |
bc4598bc | 627 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
46ceb60c | 628 | } else { |
5fedcc14 CM |
629 | grp->rx_bit_map = 0xFF; |
630 | grp->tx_bit_map = 0xFF; | |
46ceb60c | 631 | } |
20862788 CM |
632 | |
633 | /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses | |
634 | * right to left, so we need to revert the 8 bits to get the q index | |
635 | */ | |
636 | grp->rx_bit_map = bitrev8(grp->rx_bit_map); | |
637 | grp->tx_bit_map = bitrev8(grp->tx_bit_map); | |
638 | ||
639 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
640 | * also assign queues to groups | |
641 | */ | |
642 | for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { | |
643 | grp->num_rx_queues++; | |
644 | grp->rstat |= (RSTAT_CLEAR_RHALT >> i); | |
645 | priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
646 | priv->rx_queue[i]->grp = grp; | |
647 | } | |
648 | ||
649 | for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { | |
650 | grp->num_tx_queues++; | |
651 | grp->tstat |= (TSTAT_CLEAR_THALT >> i); | |
652 | priv->tqueue |= (TQUEUE_EN0 >> i); | |
653 | priv->tx_queue[i]->grp = grp; | |
654 | } | |
655 | ||
46ceb60c SG |
656 | priv->num_grps++; |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
2dc11581 | 661 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 662 | { |
b31a1d8b AF |
663 | const char *model; |
664 | const char *ctype; | |
665 | const void *mac_addr; | |
fba4ed03 SG |
666 | int err = 0, i; |
667 | struct net_device *dev = NULL; | |
668 | struct gfar_private *priv = NULL; | |
61c7a080 | 669 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 670 | struct device_node *child = NULL; |
4d7902f2 AF |
671 | const u32 *stash; |
672 | const u32 *stash_len; | |
673 | const u32 *stash_idx; | |
fba4ed03 SG |
674 | unsigned int num_tx_qs, num_rx_qs; |
675 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
676 | |
677 | if (!np || !of_device_is_available(np)) | |
678 | return -ENODEV; | |
679 | ||
fba4ed03 SG |
680 | /* parse the num of tx and rx queues */ |
681 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
682 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
683 | ||
684 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
685 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
686 | num_tx_qs, MAX_TX_QS); | |
687 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
688 | return -EINVAL; |
689 | } | |
690 | ||
691 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
692 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
693 | ||
694 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
695 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
696 | num_rx_qs, MAX_RX_QS); | |
697 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
698 | return -EINVAL; |
699 | } | |
700 | ||
701 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
702 | dev = *pdev; | |
703 | if (NULL == dev) | |
704 | return -ENOMEM; | |
705 | ||
706 | priv = netdev_priv(dev); | |
fba4ed03 SG |
707 | priv->ndev = dev; |
708 | ||
fba4ed03 | 709 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 710 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 711 | priv->num_rx_queues = num_rx_qs; |
20862788 CM |
712 | |
713 | err = gfar_alloc_tx_queues(priv); | |
714 | if (err) | |
715 | goto tx_alloc_failed; | |
716 | ||
717 | err = gfar_alloc_rx_queues(priv); | |
718 | if (err) | |
719 | goto rx_alloc_failed; | |
b31a1d8b | 720 | |
0977f817 | 721 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
722 | INIT_LIST_HEAD(&priv->rx_list.list); |
723 | priv->rx_list.count = 0; | |
724 | mutex_init(&priv->rx_queue_access); | |
725 | ||
b31a1d8b AF |
726 | model = of_get_property(np, "model", NULL); |
727 | ||
46ceb60c SG |
728 | for (i = 0; i < MAXGROUPS; i++) |
729 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 730 | |
46ceb60c SG |
731 | /* Parse and initialize group specific information */ |
732 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
733 | priv->mode = MQ_MG_MODE; | |
734 | for_each_child_of_node(np, child) { | |
735 | err = gfar_parse_group(child, priv, model); | |
736 | if (err) | |
737 | goto err_grp_init; | |
b31a1d8b | 738 | } |
46ceb60c SG |
739 | } else { |
740 | priv->mode = SQ_SG_MODE; | |
741 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 742 | if (err) |
46ceb60c | 743 | goto err_grp_init; |
b31a1d8b AF |
744 | } |
745 | ||
4d7902f2 AF |
746 | stash = of_get_property(np, "bd-stash", NULL); |
747 | ||
a12f801d | 748 | if (stash) { |
4d7902f2 AF |
749 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
750 | priv->bd_stash_en = 1; | |
751 | } | |
752 | ||
753 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
754 | ||
755 | if (stash_len) | |
756 | priv->rx_stash_size = *stash_len; | |
757 | ||
758 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
759 | ||
760 | if (stash_idx) | |
761 | priv->rx_stash_index = *stash_idx; | |
762 | ||
763 | if (stash_len || stash_idx) | |
764 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
765 | ||
b31a1d8b | 766 | mac_addr = of_get_mac_address(np); |
bc4598bc | 767 | |
b31a1d8b | 768 | if (mac_addr) |
6a3c910c | 769 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
770 | |
771 | if (model && !strcasecmp(model, "TSEC")) | |
34018fd4 | 772 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | |
bc4598bc JC |
773 | FSL_GIANFAR_DEV_HAS_COALESCE | |
774 | FSL_GIANFAR_DEV_HAS_RMON | | |
775 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
776 | ||
b31a1d8b | 777 | if (model && !strcasecmp(model, "eTSEC")) |
34018fd4 | 778 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | |
bc4598bc JC |
779 | FSL_GIANFAR_DEV_HAS_COALESCE | |
780 | FSL_GIANFAR_DEV_HAS_RMON | | |
781 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
bc4598bc JC |
782 | FSL_GIANFAR_DEV_HAS_CSUM | |
783 | FSL_GIANFAR_DEV_HAS_VLAN | | |
784 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
785 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
786 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
787 | |
788 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
789 | ||
790 | /* We only care about rgmii-id. The rest are autodetected */ | |
791 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
792 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
793 | else | |
794 | priv->interface = PHY_INTERFACE_MODE_MII; | |
795 | ||
796 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
797 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
798 | ||
fe192a49 | 799 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
800 | |
801 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 802 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
803 | |
804 | return 0; | |
805 | ||
46ceb60c SG |
806 | err_grp_init: |
807 | unmap_group_regs(priv); | |
20862788 CM |
808 | rx_alloc_failed: |
809 | gfar_free_rx_queues(priv); | |
810 | tx_alloc_failed: | |
811 | gfar_free_tx_queues(priv); | |
ee873fda | 812 | free_gfar_dev(priv); |
b31a1d8b AF |
813 | return err; |
814 | } | |
815 | ||
ca0c88c2 | 816 | static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) |
cc772ab7 MR |
817 | { |
818 | struct hwtstamp_config config; | |
819 | struct gfar_private *priv = netdev_priv(netdev); | |
820 | ||
821 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
822 | return -EFAULT; | |
823 | ||
824 | /* reserved for future extensions */ | |
825 | if (config.flags) | |
826 | return -EINVAL; | |
827 | ||
f0ee7acf MR |
828 | switch (config.tx_type) { |
829 | case HWTSTAMP_TX_OFF: | |
830 | priv->hwts_tx_en = 0; | |
831 | break; | |
832 | case HWTSTAMP_TX_ON: | |
833 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
834 | return -ERANGE; | |
835 | priv->hwts_tx_en = 1; | |
836 | break; | |
837 | default: | |
cc772ab7 | 838 | return -ERANGE; |
f0ee7acf | 839 | } |
cc772ab7 MR |
840 | |
841 | switch (config.rx_filter) { | |
842 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
843 | if (priv->hwts_rx_en) { |
844 | stop_gfar(netdev); | |
845 | priv->hwts_rx_en = 0; | |
846 | startup_gfar(netdev); | |
847 | } | |
cc772ab7 MR |
848 | break; |
849 | default: | |
850 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
851 | return -ERANGE; | |
97553f7f MR |
852 | if (!priv->hwts_rx_en) { |
853 | stop_gfar(netdev); | |
854 | priv->hwts_rx_en = 1; | |
855 | startup_gfar(netdev); | |
856 | } | |
cc772ab7 MR |
857 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
858 | break; | |
859 | } | |
860 | ||
861 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
862 | -EFAULT : 0; | |
863 | } | |
864 | ||
ca0c88c2 BH |
865 | static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) |
866 | { | |
867 | struct hwtstamp_config config; | |
868 | struct gfar_private *priv = netdev_priv(netdev); | |
869 | ||
870 | config.flags = 0; | |
871 | config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; | |
872 | config.rx_filter = (priv->hwts_rx_en ? | |
873 | HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); | |
874 | ||
875 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
876 | -EFAULT : 0; | |
877 | } | |
878 | ||
0faac9f7 CW |
879 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
880 | { | |
881 | struct gfar_private *priv = netdev_priv(dev); | |
882 | ||
883 | if (!netif_running(dev)) | |
884 | return -EINVAL; | |
885 | ||
cc772ab7 | 886 | if (cmd == SIOCSHWTSTAMP) |
ca0c88c2 BH |
887 | return gfar_hwtstamp_set(dev, rq); |
888 | if (cmd == SIOCGHWTSTAMP) | |
889 | return gfar_hwtstamp_get(dev, rq); | |
cc772ab7 | 890 | |
0faac9f7 CW |
891 | if (!priv->phydev) |
892 | return -ENODEV; | |
893 | ||
28b04113 | 894 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
895 | } |
896 | ||
18294ad1 AV |
897 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
898 | u32 class) | |
7a8b3372 SG |
899 | { |
900 | u32 rqfpr = FPR_FILER_MASK; | |
901 | u32 rqfcr = 0x0; | |
902 | ||
903 | rqfar--; | |
904 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
905 | priv->ftp_rqfpr[rqfar] = rqfpr; |
906 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
907 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
908 | ||
909 | rqfar--; | |
910 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
911 | priv->ftp_rqfpr[rqfar] = rqfpr; |
912 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
913 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
914 | ||
915 | rqfar--; | |
916 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
917 | rqfpr = class; | |
6c43e046 WJB |
918 | priv->ftp_rqfcr[rqfar] = rqfcr; |
919 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
920 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
921 | ||
922 | rqfar--; | |
923 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
924 | rqfpr = class; | |
6c43e046 WJB |
925 | priv->ftp_rqfcr[rqfar] = rqfcr; |
926 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
927 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
928 | ||
929 | return rqfar; | |
930 | } | |
931 | ||
932 | static void gfar_init_filer_table(struct gfar_private *priv) | |
933 | { | |
934 | int i = 0x0; | |
935 | u32 rqfar = MAX_FILER_IDX; | |
936 | u32 rqfcr = 0x0; | |
937 | u32 rqfpr = FPR_FILER_MASK; | |
938 | ||
939 | /* Default rule */ | |
940 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
941 | priv->ftp_rqfcr[rqfar] = rqfcr; |
942 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
943 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
944 | ||
945 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
946 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
947 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
948 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
949 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
950 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
951 | ||
85dd08eb | 952 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
953 | priv->cur_filer_idx = rqfar; |
954 | ||
955 | /* Rest are masked rules */ | |
956 | rqfcr = RQFCR_CMP_NOMATCH; | |
957 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
958 | priv->ftp_rqfcr[i] = rqfcr; |
959 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
960 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
961 | } | |
962 | } | |
963 | ||
2969b1f7 | 964 | static void __gfar_detect_errata_83xx(struct gfar_private *priv) |
7d350977 | 965 | { |
7d350977 AV |
966 | unsigned int pvr = mfspr(SPRN_PVR); |
967 | unsigned int svr = mfspr(SPRN_SVR); | |
968 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
969 | unsigned int rev = svr & 0xffff; | |
970 | ||
971 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
972 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 973 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
974 | priv->errata |= GFAR_ERRATA_74; |
975 | ||
deb90eac AV |
976 | /* MPC8313 and MPC837x all rev */ |
977 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 978 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
979 | priv->errata |= GFAR_ERRATA_76; |
980 | ||
2969b1f7 CM |
981 | /* MPC8313 Rev < 2.0 */ |
982 | if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) | |
983 | priv->errata |= GFAR_ERRATA_12; | |
984 | } | |
985 | ||
986 | static void __gfar_detect_errata_85xx(struct gfar_private *priv) | |
987 | { | |
988 | unsigned int svr = mfspr(SPRN_SVR); | |
989 | ||
990 | if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)) | |
4363c2fd | 991 | priv->errata |= GFAR_ERRATA_12; |
53fad773 CM |
992 | if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) || |
993 | ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20))) | |
994 | priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */ | |
2969b1f7 CM |
995 | } |
996 | ||
997 | static void gfar_detect_errata(struct gfar_private *priv) | |
998 | { | |
999 | struct device *dev = &priv->ofdev->dev; | |
1000 | ||
1001 | /* no plans to fix */ | |
1002 | priv->errata |= GFAR_ERRATA_A002; | |
1003 | ||
1004 | if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)) | |
1005 | __gfar_detect_errata_85xx(priv); | |
1006 | else /* non-mpc85xx parts, i.e. e300 core based */ | |
1007 | __gfar_detect_errata_83xx(priv); | |
4363c2fd | 1008 | |
7d350977 AV |
1009 | if (priv->errata) |
1010 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
1011 | priv->errata); | |
1012 | } | |
1013 | ||
a328ac92 | 1014 | static void gfar_mac_reset(struct gfar_private *priv) |
20862788 CM |
1015 | { |
1016 | struct gfar __iomem *regs = priv->gfargrp[0].regs; | |
a328ac92 | 1017 | u32 tempval; |
20862788 CM |
1018 | |
1019 | /* Reset MAC layer */ | |
1020 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); | |
1021 | ||
1022 | /* We need to delay at least 3 TX clocks */ | |
a328ac92 | 1023 | udelay(3); |
20862788 CM |
1024 | |
1025 | /* the soft reset bit is not self-resetting, so we need to | |
1026 | * clear it before resuming normal operation | |
1027 | */ | |
1028 | gfar_write(®s->maccfg1, 0); | |
1029 | ||
a328ac92 CM |
1030 | udelay(3); |
1031 | ||
1032 | /* Initialize the max receive buffer length */ | |
1033 | gfar_write(®s->mrblr, priv->rx_buffer_size); | |
1034 | ||
1035 | /* Initialize the Minimum Frame Length Register */ | |
1036 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); | |
1037 | ||
20862788 CM |
1038 | /* Initialize MACCFG2. */ |
1039 | tempval = MACCFG2_INIT_SETTINGS; | |
1040 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1041 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1042 | gfar_write(®s->maccfg2, tempval); | |
1043 | ||
a328ac92 CM |
1044 | /* Clear mac addr hash registers */ |
1045 | gfar_write(®s->igaddr0, 0); | |
1046 | gfar_write(®s->igaddr1, 0); | |
1047 | gfar_write(®s->igaddr2, 0); | |
1048 | gfar_write(®s->igaddr3, 0); | |
1049 | gfar_write(®s->igaddr4, 0); | |
1050 | gfar_write(®s->igaddr5, 0); | |
1051 | gfar_write(®s->igaddr6, 0); | |
1052 | gfar_write(®s->igaddr7, 0); | |
1053 | ||
1054 | gfar_write(®s->gaddr0, 0); | |
1055 | gfar_write(®s->gaddr1, 0); | |
1056 | gfar_write(®s->gaddr2, 0); | |
1057 | gfar_write(®s->gaddr3, 0); | |
1058 | gfar_write(®s->gaddr4, 0); | |
1059 | gfar_write(®s->gaddr5, 0); | |
1060 | gfar_write(®s->gaddr6, 0); | |
1061 | gfar_write(®s->gaddr7, 0); | |
1062 | ||
1063 | if (priv->extended_hash) | |
1064 | gfar_clear_exact_match(priv->ndev); | |
1065 | ||
1066 | gfar_mac_rx_config(priv); | |
1067 | ||
1068 | gfar_mac_tx_config(priv); | |
1069 | ||
1070 | gfar_set_mac_address(priv->ndev); | |
1071 | ||
1072 | gfar_set_multi(priv->ndev); | |
1073 | ||
1074 | /* clear ievent and imask before configuring coalescing */ | |
1075 | gfar_ints_disable(priv); | |
1076 | ||
1077 | /* Configure the coalescing support */ | |
1078 | gfar_configure_coalescing_all(priv); | |
1079 | } | |
1080 | ||
1081 | static void gfar_hw_init(struct gfar_private *priv) | |
1082 | { | |
1083 | struct gfar __iomem *regs = priv->gfargrp[0].regs; | |
1084 | u32 attrs; | |
1085 | ||
1086 | /* Stop the DMA engine now, in case it was running before | |
1087 | * (The firmware could have used it, and left it running). | |
1088 | */ | |
1089 | gfar_halt(priv); | |
1090 | ||
1091 | gfar_mac_reset(priv); | |
1092 | ||
1093 | /* Zero out the rmon mib registers if it has them */ | |
1094 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { | |
1095 | memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib)); | |
1096 | ||
1097 | /* Mask off the CAM interrupts */ | |
1098 | gfar_write(®s->rmon.cam1, 0xffffffff); | |
1099 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1100 | } | |
1101 | ||
20862788 CM |
1102 | /* Initialize ECNTRL */ |
1103 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); | |
1104 | ||
34018fd4 CM |
1105 | /* Set the extraction length and index */ |
1106 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
1107 | ATTRELI_EI(priv->rx_stash_index); | |
1108 | ||
1109 | gfar_write(®s->attreli, attrs); | |
1110 | ||
1111 | /* Start with defaults, and add stashing | |
1112 | * depending on driver parameters | |
1113 | */ | |
1114 | attrs = ATTR_INIT_SETTINGS; | |
1115 | ||
1116 | if (priv->bd_stash_en) | |
1117 | attrs |= ATTR_BDSTASH; | |
1118 | ||
1119 | if (priv->rx_stash_size != 0) | |
1120 | attrs |= ATTR_BUFSTASH; | |
1121 | ||
1122 | gfar_write(®s->attr, attrs); | |
1123 | ||
1124 | /* FIFO configs */ | |
1125 | gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR); | |
1126 | gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE); | |
1127 | gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF); | |
1128 | ||
20862788 CM |
1129 | /* Program the interrupt steering regs, only for MG devices */ |
1130 | if (priv->num_grps > 1) | |
1131 | gfar_write_isrg(priv); | |
20862788 CM |
1132 | } |
1133 | ||
1134 | static void __init gfar_init_addr_hash_table(struct gfar_private *priv) | |
1135 | { | |
1136 | struct gfar __iomem *regs = priv->gfargrp[0].regs; | |
1137 | ||
1138 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { | |
1139 | priv->extended_hash = 1; | |
1140 | priv->hash_width = 9; | |
1141 | ||
1142 | priv->hash_regs[0] = ®s->igaddr0; | |
1143 | priv->hash_regs[1] = ®s->igaddr1; | |
1144 | priv->hash_regs[2] = ®s->igaddr2; | |
1145 | priv->hash_regs[3] = ®s->igaddr3; | |
1146 | priv->hash_regs[4] = ®s->igaddr4; | |
1147 | priv->hash_regs[5] = ®s->igaddr5; | |
1148 | priv->hash_regs[6] = ®s->igaddr6; | |
1149 | priv->hash_regs[7] = ®s->igaddr7; | |
1150 | priv->hash_regs[8] = ®s->gaddr0; | |
1151 | priv->hash_regs[9] = ®s->gaddr1; | |
1152 | priv->hash_regs[10] = ®s->gaddr2; | |
1153 | priv->hash_regs[11] = ®s->gaddr3; | |
1154 | priv->hash_regs[12] = ®s->gaddr4; | |
1155 | priv->hash_regs[13] = ®s->gaddr5; | |
1156 | priv->hash_regs[14] = ®s->gaddr6; | |
1157 | priv->hash_regs[15] = ®s->gaddr7; | |
1158 | ||
1159 | } else { | |
1160 | priv->extended_hash = 0; | |
1161 | priv->hash_width = 8; | |
1162 | ||
1163 | priv->hash_regs[0] = ®s->gaddr0; | |
1164 | priv->hash_regs[1] = ®s->gaddr1; | |
1165 | priv->hash_regs[2] = ®s->gaddr2; | |
1166 | priv->hash_regs[3] = ®s->gaddr3; | |
1167 | priv->hash_regs[4] = ®s->gaddr4; | |
1168 | priv->hash_regs[5] = ®s->gaddr5; | |
1169 | priv->hash_regs[6] = ®s->gaddr6; | |
1170 | priv->hash_regs[7] = ®s->gaddr7; | |
1171 | } | |
1172 | } | |
1173 | ||
bb40dcbb | 1174 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
1175 | * and anything else we need before we start |
1176 | */ | |
74888760 | 1177 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 | 1178 | { |
1da177e4 LT |
1179 | struct net_device *dev = NULL; |
1180 | struct gfar_private *priv = NULL; | |
20862788 | 1181 | int err = 0, i; |
1da177e4 | 1182 | |
fba4ed03 | 1183 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 1184 | |
fba4ed03 SG |
1185 | if (err) |
1186 | return err; | |
1da177e4 LT |
1187 | |
1188 | priv = netdev_priv(dev); | |
4826857f KG |
1189 | priv->ndev = dev; |
1190 | priv->ofdev = ofdev; | |
369ec162 | 1191 | priv->dev = &ofdev->dev; |
4826857f | 1192 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 1193 | |
d87eb127 | 1194 | spin_lock_init(&priv->bflock); |
ab939905 | 1195 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 1196 | |
8513fbd8 | 1197 | platform_set_drvdata(ofdev, priv); |
1da177e4 | 1198 | |
7d350977 AV |
1199 | gfar_detect_errata(priv); |
1200 | ||
1da177e4 | 1201 | /* Set the dev->base_addr to the gfar reg region */ |
20862788 | 1202 | dev->base_addr = (unsigned long) priv->gfargrp[0].regs; |
1da177e4 | 1203 | |
1da177e4 | 1204 | /* Fill in the dev structure */ |
1da177e4 | 1205 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1206 | dev->mtu = 1500; |
26ccfc37 | 1207 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1208 | dev->ethtool_ops = &gfar_ethtool_ops; |
1209 | ||
fba4ed03 | 1210 | /* Register for napi ...We are registering NAPI for each grp */ |
5eaedf31 CM |
1211 | if (priv->mode == SQ_SG_MODE) |
1212 | netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq, | |
bc4598bc | 1213 | GFAR_DEV_WEIGHT); |
5eaedf31 CM |
1214 | else |
1215 | for (i = 0; i < priv->num_grps; i++) | |
1216 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, | |
1217 | GFAR_DEV_WEIGHT); | |
a12f801d | 1218 | |
b31a1d8b | 1219 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1220 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1221 | NETIF_F_RXCSUM; |
8b3afe95 | 1222 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1223 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1224 | } |
0bbaf069 | 1225 | |
87c288c6 | 1226 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
f646968f PM |
1227 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | |
1228 | NETIF_F_HW_VLAN_CTAG_RX; | |
1229 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
87c288c6 | 1230 | } |
0bbaf069 | 1231 | |
20862788 | 1232 | gfar_init_addr_hash_table(priv); |
0bbaf069 | 1233 | |
532c37bc CM |
1234 | /* Insert receive time stamps into padding alignment bytes */ |
1235 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) | |
1236 | priv->padding = 8; | |
0bbaf069 | 1237 | |
cc772ab7 | 1238 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1239 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1240 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 LT |
1241 | |
1242 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; | |
1da177e4 | 1243 | |
a12f801d | 1244 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1245 | for (i = 0; i < priv->num_tx_queues; i++) { |
1246 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1247 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1248 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1249 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1250 | } | |
a12f801d | 1251 | |
fba4ed03 SG |
1252 | for (i = 0; i < priv->num_rx_queues; i++) { |
1253 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1254 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1255 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1256 | } | |
1da177e4 | 1257 | |
0977f817 | 1258 | /* always enable rx filer */ |
4aa3a715 | 1259 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1260 | /* Enable most messages by default */ |
1261 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
b98b8bab CM |
1262 | /* use pritority h/w tx queue scheduling for single queue devices */ |
1263 | if (priv->num_tx_queues == 1) | |
1264 | priv->prio_sched_en = 1; | |
0bbaf069 | 1265 | |
a328ac92 | 1266 | gfar_hw_init(priv); |
d3eab82b | 1267 | |
1da177e4 LT |
1268 | err = register_netdev(dev); |
1269 | ||
1270 | if (err) { | |
59deab26 | 1271 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1272 | goto register_fail; |
1273 | } | |
1274 | ||
a328ac92 CM |
1275 | /* Carrier starts down, phylib will bring it up */ |
1276 | netif_carrier_off(dev); | |
1277 | ||
2884e5cc | 1278 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1279 | priv->device_flags & |
1280 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1281 | |
c50a5d9a | 1282 | /* fill out IRQ number and name fields */ |
46ceb60c | 1283 | for (i = 0; i < priv->num_grps; i++) { |
ee873fda | 1284 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
46ceb60c | 1285 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
ee873fda | 1286 | sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", |
0015e551 | 1287 | dev->name, "_g", '0' + i, "_tx"); |
ee873fda | 1288 | sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", |
0015e551 | 1289 | dev->name, "_g", '0' + i, "_rx"); |
ee873fda | 1290 | sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", |
0015e551 | 1291 | dev->name, "_g", '0' + i, "_er"); |
46ceb60c | 1292 | } else |
ee873fda | 1293 | strcpy(gfar_irq(grp, TX)->name, dev->name); |
46ceb60c | 1294 | } |
c50a5d9a | 1295 | |
7a8b3372 SG |
1296 | /* Initialize the filer table */ |
1297 | gfar_init_filer_table(priv); | |
1298 | ||
1da177e4 | 1299 | /* Print out the device info */ |
59deab26 | 1300 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1301 | |
0977f817 JC |
1302 | /* Even more device info helps when determining which kernel |
1303 | * provided which set of benchmarks. | |
1304 | */ | |
59deab26 | 1305 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1306 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1307 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1308 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1309 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1310 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1311 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1312 | |
1313 | return 0; | |
1314 | ||
1315 | register_fail: | |
46ceb60c | 1316 | unmap_group_regs(priv); |
20862788 CM |
1317 | gfar_free_rx_queues(priv); |
1318 | gfar_free_tx_queues(priv); | |
fe192a49 GL |
1319 | if (priv->phy_node) |
1320 | of_node_put(priv->phy_node); | |
1321 | if (priv->tbi_node) | |
1322 | of_node_put(priv->tbi_node); | |
ee873fda | 1323 | free_gfar_dev(priv); |
bb40dcbb | 1324 | return err; |
1da177e4 LT |
1325 | } |
1326 | ||
2dc11581 | 1327 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1328 | { |
8513fbd8 | 1329 | struct gfar_private *priv = platform_get_drvdata(ofdev); |
1da177e4 | 1330 | |
fe192a49 GL |
1331 | if (priv->phy_node) |
1332 | of_node_put(priv->phy_node); | |
1333 | if (priv->tbi_node) | |
1334 | of_node_put(priv->tbi_node); | |
1335 | ||
d9d8e041 | 1336 | unregister_netdev(priv->ndev); |
46ceb60c | 1337 | unmap_group_regs(priv); |
20862788 CM |
1338 | gfar_free_rx_queues(priv); |
1339 | gfar_free_tx_queues(priv); | |
ee873fda | 1340 | free_gfar_dev(priv); |
1da177e4 LT |
1341 | |
1342 | return 0; | |
1343 | } | |
1344 | ||
d87eb127 | 1345 | #ifdef CONFIG_PM |
be926fc4 AV |
1346 | |
1347 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1348 | { |
be926fc4 AV |
1349 | struct gfar_private *priv = dev_get_drvdata(dev); |
1350 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1351 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1352 | unsigned long flags; |
1353 | u32 tempval; | |
1354 | ||
1355 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1356 | (priv->device_flags & |
1357 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1358 | |
be926fc4 | 1359 | netif_device_detach(ndev); |
d87eb127 | 1360 | |
be926fc4 | 1361 | if (netif_running(ndev)) { |
fba4ed03 SG |
1362 | |
1363 | local_irq_save(flags); | |
1364 | lock_tx_qs(priv); | |
1365 | lock_rx_qs(priv); | |
d87eb127 | 1366 | |
c10650b6 | 1367 | gfar_halt_nodisable(priv); |
d87eb127 SW |
1368 | |
1369 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1370 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1371 | |
1372 | tempval &= ~MACCFG1_TX_EN; | |
1373 | ||
1374 | if (!magic_packet) | |
1375 | tempval &= ~MACCFG1_RX_EN; | |
1376 | ||
f4983704 | 1377 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1378 | |
fba4ed03 SG |
1379 | unlock_rx_qs(priv); |
1380 | unlock_tx_qs(priv); | |
1381 | local_irq_restore(flags); | |
d87eb127 | 1382 | |
46ceb60c | 1383 | disable_napi(priv); |
d87eb127 SW |
1384 | |
1385 | if (magic_packet) { | |
1386 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1387 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1388 | |
1389 | /* Enable Magic Packet mode */ | |
f4983704 | 1390 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1391 | tempval |= MACCFG2_MPEN; |
f4983704 | 1392 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1393 | } else { |
1394 | phy_stop(priv->phydev); | |
1395 | } | |
1396 | } | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
be926fc4 | 1401 | static int gfar_resume(struct device *dev) |
d87eb127 | 1402 | { |
be926fc4 AV |
1403 | struct gfar_private *priv = dev_get_drvdata(dev); |
1404 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1405 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1406 | unsigned long flags; |
1407 | u32 tempval; | |
1408 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1409 | (priv->device_flags & |
1410 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1411 | |
be926fc4 AV |
1412 | if (!netif_running(ndev)) { |
1413 | netif_device_attach(ndev); | |
d87eb127 SW |
1414 | return 0; |
1415 | } | |
1416 | ||
1417 | if (!magic_packet && priv->phydev) | |
1418 | phy_start(priv->phydev); | |
1419 | ||
1420 | /* Disable Magic Packet mode, in case something | |
1421 | * else woke us up. | |
1422 | */ | |
fba4ed03 SG |
1423 | local_irq_save(flags); |
1424 | lock_tx_qs(priv); | |
1425 | lock_rx_qs(priv); | |
d87eb127 | 1426 | |
f4983704 | 1427 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1428 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1429 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1430 | |
c10650b6 | 1431 | gfar_start(priv); |
d87eb127 | 1432 | |
fba4ed03 SG |
1433 | unlock_rx_qs(priv); |
1434 | unlock_tx_qs(priv); | |
1435 | local_irq_restore(flags); | |
d87eb127 | 1436 | |
be926fc4 AV |
1437 | netif_device_attach(ndev); |
1438 | ||
46ceb60c | 1439 | enable_napi(priv); |
be926fc4 AV |
1440 | |
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | static int gfar_restore(struct device *dev) | |
1445 | { | |
1446 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1447 | struct net_device *ndev = priv->ndev; | |
1448 | ||
103cdd1d WD |
1449 | if (!netif_running(ndev)) { |
1450 | netif_device_attach(ndev); | |
1451 | ||
be926fc4 | 1452 | return 0; |
103cdd1d | 1453 | } |
be926fc4 | 1454 | |
1eb8f7a7 CM |
1455 | if (gfar_init_bds(ndev)) { |
1456 | free_skb_resources(priv); | |
1457 | return -ENOMEM; | |
1458 | } | |
1459 | ||
a328ac92 CM |
1460 | gfar_mac_reset(priv); |
1461 | ||
1462 | gfar_init_tx_rx_base(priv); | |
1463 | ||
c10650b6 | 1464 | gfar_start(priv); |
be926fc4 AV |
1465 | |
1466 | priv->oldlink = 0; | |
1467 | priv->oldspeed = 0; | |
1468 | priv->oldduplex = -1; | |
1469 | ||
1470 | if (priv->phydev) | |
1471 | phy_start(priv->phydev); | |
d87eb127 | 1472 | |
be926fc4 | 1473 | netif_device_attach(ndev); |
5ea681d4 | 1474 | enable_napi(priv); |
d87eb127 SW |
1475 | |
1476 | return 0; | |
1477 | } | |
be926fc4 AV |
1478 | |
1479 | static struct dev_pm_ops gfar_pm_ops = { | |
1480 | .suspend = gfar_suspend, | |
1481 | .resume = gfar_resume, | |
1482 | .freeze = gfar_suspend, | |
1483 | .thaw = gfar_resume, | |
1484 | .restore = gfar_restore, | |
1485 | }; | |
1486 | ||
1487 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1488 | ||
d87eb127 | 1489 | #else |
be926fc4 AV |
1490 | |
1491 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1492 | |
d87eb127 | 1493 | #endif |
1da177e4 | 1494 | |
e8a2b6a4 AF |
1495 | /* Reads the controller's registers to determine what interface |
1496 | * connects it to the PHY. | |
1497 | */ | |
1498 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1499 | { | |
1500 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1501 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1502 | u32 ecntrl; |
1503 | ||
f4983704 | 1504 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1505 | |
1506 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1507 | return PHY_INTERFACE_MODE_SGMII; | |
1508 | ||
1509 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1510 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1511 | return PHY_INTERFACE_MODE_RTBI; | |
1512 | else | |
1513 | return PHY_INTERFACE_MODE_TBI; | |
1514 | } | |
1515 | ||
1516 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1517 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1518 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1519 | } |
7132ab7f | 1520 | else { |
b31a1d8b | 1521 | phy_interface_t interface = priv->interface; |
7132ab7f | 1522 | |
0977f817 | 1523 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1524 | * be set by the device tree or platform code. |
1525 | */ | |
1526 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1527 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1528 | ||
e8a2b6a4 | 1529 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1530 | } |
e8a2b6a4 AF |
1531 | } |
1532 | ||
b31a1d8b | 1533 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1534 | return PHY_INTERFACE_MODE_GMII; |
1535 | ||
1536 | return PHY_INTERFACE_MODE_MII; | |
1537 | } | |
1538 | ||
1539 | ||
bb40dcbb AF |
1540 | /* Initializes driver's PHY state, and attaches to the PHY. |
1541 | * Returns 0 on success. | |
1da177e4 LT |
1542 | */ |
1543 | static int init_phy(struct net_device *dev) | |
1544 | { | |
1545 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1546 | uint gigabit_support = |
b31a1d8b | 1547 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
23402bdd | 1548 | GFAR_SUPPORTED_GBIT : 0; |
e8a2b6a4 | 1549 | phy_interface_t interface; |
1da177e4 LT |
1550 | |
1551 | priv->oldlink = 0; | |
1552 | priv->oldspeed = 0; | |
1553 | priv->oldduplex = -1; | |
1554 | ||
e8a2b6a4 AF |
1555 | interface = gfar_get_interface(dev); |
1556 | ||
1db780f8 AV |
1557 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1558 | interface); | |
1559 | if (!priv->phydev) | |
1560 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1561 | interface); | |
1562 | if (!priv->phydev) { | |
1563 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1564 | return -ENODEV; | |
fe192a49 | 1565 | } |
1da177e4 | 1566 | |
d3c12873 KJ |
1567 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1568 | gfar_configure_serdes(dev); | |
1569 | ||
bb40dcbb | 1570 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1571 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1572 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1573 | |
1574 | return 0; | |
1da177e4 LT |
1575 | } |
1576 | ||
0977f817 | 1577 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1578 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1579 | * through the MDIO bus on each controller, treating it as a | |
1580 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1581 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1582 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1583 | * value doesn't matter, as there are no other PHYs on the bus. | |
1584 | */ | |
d3c12873 KJ |
1585 | static void gfar_configure_serdes(struct net_device *dev) |
1586 | { | |
1587 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1588 | struct phy_device *tbiphy; |
1589 | ||
1590 | if (!priv->tbi_node) { | |
1591 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1592 | "device tree specify a tbi-handle\n"); | |
1593 | return; | |
1594 | } | |
c132419e | 1595 | |
fe192a49 GL |
1596 | tbiphy = of_phy_find_device(priv->tbi_node); |
1597 | if (!tbiphy) { | |
1598 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1599 | return; |
1600 | } | |
d3c12873 | 1601 | |
0977f817 | 1602 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1603 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1604 | * everything for us? Resetting it takes the link down and requires | |
1605 | * several seconds for it to come back. | |
1606 | */ | |
fe192a49 | 1607 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1608 | return; |
d3c12873 | 1609 | |
d0313587 | 1610 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1611 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1612 | |
fe192a49 | 1613 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1614 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1615 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1616 | |
bc4598bc JC |
1617 | phy_write(tbiphy, MII_BMCR, |
1618 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1619 | BMCR_SPEED1000); | |
d3c12873 KJ |
1620 | } |
1621 | ||
511d934f AV |
1622 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1623 | { | |
1624 | u32 res; | |
1625 | ||
0977f817 | 1626 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1627 | * actually wait for IEVENT_GRSC flag. |
1628 | */ | |
ad3660c2 | 1629 | if (!gfar_has_errata(priv, GFAR_ERRATA_A002)) |
511d934f AV |
1630 | return 0; |
1631 | ||
0977f817 | 1632 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1633 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1634 | * and the Rx can be safely reset. | |
1635 | */ | |
1636 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1637 | res &= 0x7f807f80; | |
1638 | if ((res & 0xffff) == (res >> 16)) | |
1639 | return 1; | |
1640 | ||
1641 | return 0; | |
1642 | } | |
0bbaf069 KG |
1643 | |
1644 | /* Halt the receive and transmit queues */ | |
c10650b6 | 1645 | static void gfar_halt_nodisable(struct gfar_private *priv) |
1da177e4 | 1646 | { |
efeddce7 | 1647 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
1648 | u32 tempval; |
1649 | ||
efeddce7 | 1650 | gfar_ints_disable(priv); |
1da177e4 | 1651 | |
1da177e4 | 1652 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1653 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1654 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1655 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1656 | int ret; |
1657 | ||
1da177e4 | 1658 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1659 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1660 | |
511d934f AV |
1661 | do { |
1662 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1663 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1664 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1665 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1666 | ret = __gfar_is_rx_idle(priv); | |
1667 | } while (!ret); | |
1da177e4 | 1668 | } |
d87eb127 | 1669 | } |
d87eb127 SW |
1670 | |
1671 | /* Halt the receive and transmit queues */ | |
c10650b6 | 1672 | void gfar_halt(struct gfar_private *priv) |
d87eb127 | 1673 | { |
46ceb60c | 1674 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1675 | u32 tempval; |
1da177e4 | 1676 | |
c10650b6 CM |
1677 | /* Dissable the Rx/Tx hw queues */ |
1678 | gfar_write(®s->rqueue, 0); | |
1679 | gfar_write(®s->tqueue, 0); | |
2a54adc3 | 1680 | |
c10650b6 CM |
1681 | mdelay(10); |
1682 | ||
1683 | gfar_halt_nodisable(priv); | |
1684 | ||
1685 | /* Disable Rx/Tx DMA */ | |
1da177e4 LT |
1686 | tempval = gfar_read(®s->maccfg1); |
1687 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1688 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1689 | } |
1690 | ||
46ceb60c SG |
1691 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1692 | { | |
ee873fda CM |
1693 | free_irq(gfar_irq(grp, TX)->irq, grp); |
1694 | free_irq(gfar_irq(grp, RX)->irq, grp); | |
1695 | free_irq(gfar_irq(grp, ER)->irq, grp); | |
46ceb60c SG |
1696 | } |
1697 | ||
0bbaf069 KG |
1698 | void stop_gfar(struct net_device *dev) |
1699 | { | |
1700 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1701 | unsigned long flags; |
46ceb60c | 1702 | int i; |
0bbaf069 | 1703 | |
bb40dcbb AF |
1704 | phy_stop(priv->phydev); |
1705 | ||
a12f801d | 1706 | |
0bbaf069 | 1707 | /* Lock it down */ |
fba4ed03 SG |
1708 | local_irq_save(flags); |
1709 | lock_tx_qs(priv); | |
1710 | lock_rx_qs(priv); | |
0bbaf069 | 1711 | |
c10650b6 | 1712 | gfar_halt(priv); |
1da177e4 | 1713 | |
fba4ed03 SG |
1714 | unlock_rx_qs(priv); |
1715 | unlock_tx_qs(priv); | |
1716 | local_irq_restore(flags); | |
1da177e4 LT |
1717 | |
1718 | /* Free the IRQs */ | |
b31a1d8b | 1719 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1720 | for (i = 0; i < priv->num_grps; i++) |
1721 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1722 | } else { |
46ceb60c | 1723 | for (i = 0; i < priv->num_grps; i++) |
ee873fda | 1724 | free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, |
bc4598bc | 1725 | &priv->gfargrp[i]); |
1da177e4 LT |
1726 | } |
1727 | ||
1728 | free_skb_resources(priv); | |
1da177e4 LT |
1729 | } |
1730 | ||
fba4ed03 | 1731 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1732 | { |
1da177e4 | 1733 | struct txbd8 *txbdp; |
fba4ed03 | 1734 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1735 | int i, j; |
1da177e4 | 1736 | |
a12f801d | 1737 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1738 | |
a12f801d SG |
1739 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1740 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1741 | continue; |
1da177e4 | 1742 | |
369ec162 | 1743 | dma_unmap_single(priv->dev, txbdp->bufPtr, |
bc4598bc | 1744 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1745 | txbdp->lstatus = 0; |
fba4ed03 | 1746 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1747 | j++) { |
4669bc90 | 1748 | txbdp++; |
369ec162 | 1749 | dma_unmap_page(priv->dev, txbdp->bufPtr, |
bc4598bc | 1750 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1751 | } |
ad5da7ab | 1752 | txbdp++; |
a12f801d SG |
1753 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1754 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1755 | } |
a12f801d | 1756 | kfree(tx_queue->tx_skbuff); |
1eb8f7a7 | 1757 | tx_queue->tx_skbuff = NULL; |
fba4ed03 | 1758 | } |
1da177e4 | 1759 | |
fba4ed03 SG |
1760 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1761 | { | |
1762 | struct rxbd8 *rxbdp; | |
1763 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1764 | int i; | |
1da177e4 | 1765 | |
fba4ed03 | 1766 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1767 | |
a12f801d SG |
1768 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1769 | if (rx_queue->rx_skbuff[i]) { | |
369ec162 CM |
1770 | dma_unmap_single(priv->dev, rxbdp->bufPtr, |
1771 | priv->rx_buffer_size, | |
bc4598bc | 1772 | DMA_FROM_DEVICE); |
a12f801d SG |
1773 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1774 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1775 | } |
e69edd21 AV |
1776 | rxbdp->lstatus = 0; |
1777 | rxbdp->bufPtr = 0; | |
1778 | rxbdp++; | |
1da177e4 | 1779 | } |
a12f801d | 1780 | kfree(rx_queue->rx_skbuff); |
1eb8f7a7 | 1781 | rx_queue->rx_skbuff = NULL; |
fba4ed03 | 1782 | } |
e69edd21 | 1783 | |
fba4ed03 | 1784 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1785 | * Then free tx_skbuff and rx_skbuff |
1786 | */ | |
fba4ed03 SG |
1787 | static void free_skb_resources(struct gfar_private *priv) |
1788 | { | |
1789 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1790 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1791 | int i; | |
1792 | ||
1793 | /* Go through all the buffer descriptors and free their data buffers */ | |
1794 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1795 | struct netdev_queue *txq; |
bc4598bc | 1796 | |
fba4ed03 | 1797 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1798 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1799 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1800 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1801 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1802 | } |
1803 | ||
1804 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1805 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1806 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1807 | free_skb_rx_queue(rx_queue); |
1808 | } | |
1809 | ||
369ec162 | 1810 | dma_free_coherent(priv->dev, |
bc4598bc JC |
1811 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1812 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1813 | priv->tx_queue[0]->tx_bd_base, | |
1814 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1815 | } |
1816 | ||
c10650b6 | 1817 | void gfar_start(struct gfar_private *priv) |
0bbaf069 | 1818 | { |
46ceb60c | 1819 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1820 | u32 tempval; |
46ceb60c | 1821 | int i = 0; |
0bbaf069 | 1822 | |
c10650b6 CM |
1823 | /* Enable Rx/Tx hw queues */ |
1824 | gfar_write(®s->rqueue, priv->rqueue); | |
1825 | gfar_write(®s->tqueue, priv->tqueue); | |
0bbaf069 KG |
1826 | |
1827 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1828 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1829 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1830 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1831 | |
0bbaf069 | 1832 | /* Make sure we aren't stopped */ |
f4983704 | 1833 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1834 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1835 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1836 | |
46ceb60c SG |
1837 | for (i = 0; i < priv->num_grps; i++) { |
1838 | regs = priv->gfargrp[i].regs; | |
1839 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1840 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1841 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
46ceb60c | 1842 | } |
12dea57b | 1843 | |
c10650b6 CM |
1844 | /* Enable Rx/Tx DMA */ |
1845 | tempval = gfar_read(®s->maccfg1); | |
1846 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1847 | gfar_write(®s->maccfg1, tempval); | |
1848 | ||
efeddce7 CM |
1849 | gfar_ints_enable(priv); |
1850 | ||
c10650b6 | 1851 | priv->ndev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1852 | } |
1853 | ||
800c644b | 1854 | static void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1855 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1856 | { |
46ceb60c | 1857 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1858 | u32 __iomem *baddr; |
815b97c6 | 1859 | |
46ceb60c | 1860 | if (priv->mode == MQ_MG_MODE) { |
5d9657d8 | 1861 | int i = 0; |
c6e1160e | 1862 | |
46ceb60c | 1863 | baddr = ®s->txic0; |
984b3f57 | 1864 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
9740e001 CM |
1865 | gfar_write(baddr + i, 0); |
1866 | if (likely(priv->tx_queue[i]->txcoalescing)) | |
46ceb60c | 1867 | gfar_write(baddr + i, priv->tx_queue[i]->txic); |
46ceb60c SG |
1868 | } |
1869 | ||
1870 | baddr = ®s->rxic0; | |
984b3f57 | 1871 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
9740e001 CM |
1872 | gfar_write(baddr + i, 0); |
1873 | if (likely(priv->rx_queue[i]->rxcoalescing)) | |
46ceb60c | 1874 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); |
46ceb60c | 1875 | } |
5d9657d8 | 1876 | } else { |
c6e1160e | 1877 | /* Backward compatible case -- even if we enable |
5d9657d8 CM |
1878 | * multiple queues, there's only single reg to program |
1879 | */ | |
1880 | gfar_write(®s->txic, 0); | |
1881 | if (likely(priv->tx_queue[0]->txcoalescing)) | |
1882 | gfar_write(®s->txic, priv->tx_queue[0]->txic); | |
1883 | ||
1884 | gfar_write(®s->rxic, 0); | |
1885 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) | |
1886 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); | |
46ceb60c SG |
1887 | } |
1888 | } | |
1889 | ||
800c644b CM |
1890 | void gfar_configure_coalescing_all(struct gfar_private *priv) |
1891 | { | |
1892 | gfar_configure_coalescing(priv, 0xFF, 0xFF); | |
1893 | } | |
1894 | ||
46ceb60c SG |
1895 | static int register_grp_irqs(struct gfar_priv_grp *grp) |
1896 | { | |
1897 | struct gfar_private *priv = grp->priv; | |
1898 | struct net_device *dev = priv->ndev; | |
1899 | int err; | |
1da177e4 | 1900 | |
1da177e4 | 1901 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1902 | * them. Otherwise, only register for the one |
1903 | */ | |
b31a1d8b | 1904 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1905 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1906 | * Transmit, and Receive |
1907 | */ | |
ee873fda CM |
1908 | err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, |
1909 | gfar_irq(grp, ER)->name, grp); | |
1910 | if (err < 0) { | |
59deab26 | 1911 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1912 | gfar_irq(grp, ER)->irq); |
46ceb60c | 1913 | |
2145f1af | 1914 | goto err_irq_fail; |
1da177e4 | 1915 | } |
ee873fda CM |
1916 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, |
1917 | gfar_irq(grp, TX)->name, grp); | |
1918 | if (err < 0) { | |
59deab26 | 1919 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1920 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1921 | goto tx_irq_fail; |
1922 | } | |
ee873fda CM |
1923 | err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, |
1924 | gfar_irq(grp, RX)->name, grp); | |
1925 | if (err < 0) { | |
59deab26 | 1926 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1927 | gfar_irq(grp, RX)->irq); |
1da177e4 LT |
1928 | goto rx_irq_fail; |
1929 | } | |
1930 | } else { | |
ee873fda CM |
1931 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, |
1932 | gfar_irq(grp, TX)->name, grp); | |
1933 | if (err < 0) { | |
59deab26 | 1934 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1935 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1936 | goto err_irq_fail; |
1937 | } | |
1938 | } | |
1939 | ||
46ceb60c SG |
1940 | return 0; |
1941 | ||
1942 | rx_irq_fail: | |
ee873fda | 1943 | free_irq(gfar_irq(grp, TX)->irq, grp); |
46ceb60c | 1944 | tx_irq_fail: |
ee873fda | 1945 | free_irq(gfar_irq(grp, ER)->irq, grp); |
46ceb60c SG |
1946 | err_irq_fail: |
1947 | return err; | |
1948 | ||
1949 | } | |
1950 | ||
1951 | /* Bring the controller up and running */ | |
1952 | int startup_gfar(struct net_device *ndev) | |
1953 | { | |
1954 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c SG |
1955 | int err, i, j; |
1956 | ||
a328ac92 | 1957 | gfar_mac_reset(priv); |
46ceb60c | 1958 | |
46ceb60c SG |
1959 | err = gfar_alloc_skb_resources(ndev); |
1960 | if (err) | |
1961 | return err; | |
1962 | ||
a328ac92 | 1963 | gfar_init_tx_rx_base(priv); |
46ceb60c SG |
1964 | |
1965 | for (i = 0; i < priv->num_grps; i++) { | |
1966 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1967 | if (err) { | |
1968 | for (j = 0; j < i; j++) | |
1969 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1970 | goto irq_fail; |
46ceb60c SG |
1971 | } |
1972 | } | |
1973 | ||
7f7f5316 | 1974 | /* Start the controller */ |
c10650b6 | 1975 | gfar_start(priv); |
1da177e4 | 1976 | |
826aa4a0 AV |
1977 | phy_start(priv->phydev); |
1978 | ||
1da177e4 LT |
1979 | return 0; |
1980 | ||
46ceb60c | 1981 | irq_fail: |
e69edd21 | 1982 | free_skb_resources(priv); |
1da177e4 LT |
1983 | return err; |
1984 | } | |
1985 | ||
0977f817 JC |
1986 | /* Called when something needs to use the ethernet device |
1987 | * Returns 0 for success. | |
1988 | */ | |
1da177e4 LT |
1989 | static int gfar_enet_open(struct net_device *dev) |
1990 | { | |
94e8cc35 | 1991 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1992 | int err; |
1993 | ||
46ceb60c | 1994 | enable_napi(priv); |
bea3348e | 1995 | |
1da177e4 LT |
1996 | err = init_phy(dev); |
1997 | ||
a12f801d | 1998 | if (err) { |
46ceb60c | 1999 | disable_napi(priv); |
1da177e4 | 2000 | return err; |
bea3348e | 2001 | } |
1da177e4 LT |
2002 | |
2003 | err = startup_gfar(dev); | |
db0e8e3f | 2004 | if (err) { |
46ceb60c | 2005 | disable_napi(priv); |
db0e8e3f AV |
2006 | return err; |
2007 | } | |
1da177e4 | 2008 | |
fba4ed03 | 2009 | netif_tx_start_all_queues(dev); |
1da177e4 | 2010 | |
2884e5cc AV |
2011 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
2012 | ||
1da177e4 LT |
2013 | return err; |
2014 | } | |
2015 | ||
54dc79fe | 2016 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 2017 | { |
54dc79fe | 2018 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
2019 | |
2020 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 2021 | |
0bbaf069 KG |
2022 | return fcb; |
2023 | } | |
2024 | ||
9c4886e5 | 2025 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 2026 | int fcb_length) |
0bbaf069 | 2027 | { |
0bbaf069 KG |
2028 | /* If we're here, it's a IP packet with a TCP or UDP |
2029 | * payload. We set it to checksum, using a pseudo-header | |
2030 | * we provide | |
2031 | */ | |
3a2e16c8 | 2032 | u8 flags = TXFCB_DEFAULT; |
0bbaf069 | 2033 | |
0977f817 JC |
2034 | /* Tell the controller what the protocol is |
2035 | * And provide the already calculated phcs | |
2036 | */ | |
eddc9ec5 | 2037 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 2038 | flags |= TXFCB_UDP; |
4bedb452 | 2039 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 2040 | } else |
8da32de5 | 2041 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2042 | |
2043 | /* l3os is the distance between the start of the | |
2044 | * frame (skb->data) and the start of the IP hdr. | |
2045 | * l4os is the distance between the start of the | |
0977f817 JC |
2046 | * l3 hdr and the l4 hdr |
2047 | */ | |
9c4886e5 | 2048 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2049 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2050 | |
7f7f5316 | 2051 | fcb->flags = flags; |
0bbaf069 KG |
2052 | } |
2053 | ||
7f7f5316 | 2054 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2055 | { |
7f7f5316 | 2056 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2057 | fcb->vlctl = vlan_tx_tag_get(skb); |
2058 | } | |
2059 | ||
4669bc90 | 2060 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2061 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2062 | { |
2063 | struct txbd8 *new_bd = bdp + stride; | |
2064 | ||
2065 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2066 | } | |
2067 | ||
2068 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2069 | int ring_size) |
4669bc90 DH |
2070 | { |
2071 | return skip_txbd(bdp, 1, base, ring_size); | |
2072 | } | |
2073 | ||
02d88fb4 CM |
2074 | /* eTSEC12: csum generation not supported for some fcb offsets */ |
2075 | static inline bool gfar_csum_errata_12(struct gfar_private *priv, | |
2076 | unsigned long fcb_addr) | |
2077 | { | |
2078 | return (gfar_has_errata(priv, GFAR_ERRATA_12) && | |
2079 | (fcb_addr % 0x20) > 0x18); | |
2080 | } | |
2081 | ||
2082 | /* eTSEC76: csum generation for frames larger than 2500 may | |
2083 | * cause excess delays before start of transmission | |
2084 | */ | |
2085 | static inline bool gfar_csum_errata_76(struct gfar_private *priv, | |
2086 | unsigned int len) | |
2087 | { | |
2088 | return (gfar_has_errata(priv, GFAR_ERRATA_76) && | |
2089 | (len > 2500)); | |
2090 | } | |
2091 | ||
0977f817 JC |
2092 | /* This is called by the kernel when a frame is ready for transmission. |
2093 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2094 | */ | |
1da177e4 LT |
2095 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2096 | { | |
2097 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2098 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2099 | struct netdev_queue *txq; |
f4983704 | 2100 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2101 | struct txfcb *fcb = NULL; |
f0ee7acf | 2102 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2103 | u32 lstatus; |
0d0cffdc CM |
2104 | int i, rq = 0; |
2105 | int do_tstamp, do_csum, do_vlan; | |
4669bc90 | 2106 | u32 bufaddr; |
fef6108d | 2107 | unsigned long flags; |
50ad076b | 2108 | unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; |
fba4ed03 SG |
2109 | |
2110 | rq = skb->queue_mapping; | |
2111 | tx_queue = priv->tx_queue[rq]; | |
2112 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2113 | base = tx_queue->tx_bd_base; |
46ceb60c | 2114 | regs = tx_queue->grp->regs; |
f0ee7acf | 2115 | |
0d0cffdc CM |
2116 | do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); |
2117 | do_vlan = vlan_tx_tag_present(skb); | |
2118 | do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && | |
2119 | priv->hwts_tx_en; | |
2120 | ||
2121 | if (do_csum || do_vlan) | |
2122 | fcb_len = GMAC_FCB_LEN; | |
2123 | ||
f0ee7acf | 2124 | /* check if time stamp should be generated */ |
0d0cffdc CM |
2125 | if (unlikely(do_tstamp)) |
2126 | fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; | |
4669bc90 | 2127 | |
5b28beaf | 2128 | /* make space for additional header when fcb is needed */ |
0d0cffdc | 2129 | if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { |
54dc79fe SH |
2130 | struct sk_buff *skb_new; |
2131 | ||
0d0cffdc | 2132 | skb_new = skb_realloc_headroom(skb, fcb_len); |
54dc79fe SH |
2133 | if (!skb_new) { |
2134 | dev->stats.tx_errors++; | |
bd14ba84 | 2135 | kfree_skb(skb); |
54dc79fe SH |
2136 | return NETDEV_TX_OK; |
2137 | } | |
db83d136 | 2138 | |
313b037c ED |
2139 | if (skb->sk) |
2140 | skb_set_owner_w(skb_new, skb->sk); | |
2141 | consume_skb(skb); | |
54dc79fe SH |
2142 | skb = skb_new; |
2143 | } | |
2144 | ||
4669bc90 DH |
2145 | /* total number of fragments in the SKB */ |
2146 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2147 | ||
f0ee7acf MR |
2148 | /* calculate the required number of TxBDs for this skb */ |
2149 | if (unlikely(do_tstamp)) | |
2150 | nr_txbds = nr_frags + 2; | |
2151 | else | |
2152 | nr_txbds = nr_frags + 1; | |
2153 | ||
4669bc90 | 2154 | /* check if there is space to queue this packet */ |
f0ee7acf | 2155 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2156 | /* no space, stop the queue */ |
fba4ed03 | 2157 | netif_tx_stop_queue(txq); |
4669bc90 | 2158 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2159 | return NETDEV_TX_BUSY; |
2160 | } | |
1da177e4 LT |
2161 | |
2162 | /* Update transmit stats */ | |
50ad076b CM |
2163 | bytes_sent = skb->len; |
2164 | tx_queue->stats.tx_bytes += bytes_sent; | |
2165 | /* keep Tx bytes on wire for BQL accounting */ | |
2166 | GFAR_CB(skb)->bytes_sent = bytes_sent; | |
1ac9ad13 | 2167 | tx_queue->stats.tx_packets++; |
1da177e4 | 2168 | |
a12f801d | 2169 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2170 | lstatus = txbdp->lstatus; |
2171 | ||
2172 | /* Time stamp insertion requires one additional TxBD */ | |
2173 | if (unlikely(do_tstamp)) | |
2174 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2175 | tx_queue->tx_ring_size); |
1da177e4 | 2176 | |
4669bc90 | 2177 | if (nr_frags == 0) { |
f0ee7acf MR |
2178 | if (unlikely(do_tstamp)) |
2179 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2180 | TXBD_INTERRUPT); |
f0ee7acf MR |
2181 | else |
2182 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2183 | } else { |
2184 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2185 | for (i = 0; i < nr_frags; i++) { | |
50ad076b | 2186 | unsigned int frag_len; |
4669bc90 | 2187 | /* Point at the next BD, wrapping as needed */ |
a12f801d | 2188 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 | 2189 | |
50ad076b | 2190 | frag_len = skb_shinfo(skb)->frags[i].size; |
4669bc90 | 2191 | |
50ad076b | 2192 | lstatus = txbdp->lstatus | frag_len | |
bc4598bc | 2193 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2194 | |
2195 | /* Handle the last BD specially */ | |
2196 | if (i == nr_frags - 1) | |
2197 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2198 | |
369ec162 | 2199 | bufaddr = skb_frag_dma_map(priv->dev, |
2234a722 IC |
2200 | &skb_shinfo(skb)->frags[i], |
2201 | 0, | |
50ad076b | 2202 | frag_len, |
2234a722 | 2203 | DMA_TO_DEVICE); |
4669bc90 DH |
2204 | |
2205 | /* set the TxBD length and buffer pointer */ | |
2206 | txbdp->bufPtr = bufaddr; | |
2207 | txbdp->lstatus = lstatus; | |
2208 | } | |
2209 | ||
2210 | lstatus = txbdp_start->lstatus; | |
2211 | } | |
1da177e4 | 2212 | |
9c4886e5 MR |
2213 | /* Add TxPAL between FCB and frame if required */ |
2214 | if (unlikely(do_tstamp)) { | |
2215 | skb_push(skb, GMAC_TXPAL_LEN); | |
2216 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2217 | } | |
2218 | ||
0d0cffdc CM |
2219 | /* Add TxFCB if required */ |
2220 | if (fcb_len) { | |
54dc79fe | 2221 | fcb = gfar_add_fcb(skb); |
02d88fb4 | 2222 | lstatus |= BD_LFLAG(TXBD_TOE); |
0d0cffdc CM |
2223 | } |
2224 | ||
2225 | /* Set up checksumming */ | |
2226 | if (do_csum) { | |
2227 | gfar_tx_checksum(skb, fcb, fcb_len); | |
02d88fb4 CM |
2228 | |
2229 | if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || | |
2230 | unlikely(gfar_csum_errata_76(priv, skb->len))) { | |
4363c2fd AD |
2231 | __skb_pull(skb, GMAC_FCB_LEN); |
2232 | skb_checksum_help(skb); | |
0d0cffdc CM |
2233 | if (do_vlan || do_tstamp) { |
2234 | /* put back a new fcb for vlan/tstamp TOE */ | |
2235 | fcb = gfar_add_fcb(skb); | |
2236 | } else { | |
2237 | /* Tx TOE not used */ | |
2238 | lstatus &= ~(BD_LFLAG(TXBD_TOE)); | |
2239 | fcb = NULL; | |
2240 | } | |
4363c2fd | 2241 | } |
0bbaf069 KG |
2242 | } |
2243 | ||
0d0cffdc | 2244 | if (do_vlan) |
54dc79fe | 2245 | gfar_tx_vlan(skb, fcb); |
0bbaf069 | 2246 | |
f0ee7acf MR |
2247 | /* Setup tx hardware time stamping if requested */ |
2248 | if (unlikely(do_tstamp)) { | |
2244d07b | 2249 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf | 2250 | fcb->ptp = 1; |
f0ee7acf MR |
2251 | } |
2252 | ||
369ec162 | 2253 | txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data, |
bc4598bc | 2254 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2255 | |
0977f817 | 2256 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2257 | * first TxBD points to the FCB and must have a data length of |
2258 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2259 | * the full frame length. | |
2260 | */ | |
2261 | if (unlikely(do_tstamp)) { | |
0d0cffdc | 2262 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len; |
f0ee7acf | 2263 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
0d0cffdc | 2264 | (skb_headlen(skb) - fcb_len); |
f0ee7acf MR |
2265 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2266 | } else { | |
2267 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2268 | } | |
1da177e4 | 2269 | |
50ad076b | 2270 | netdev_tx_sent_queue(txq, bytes_sent); |
d8a0f1b0 | 2271 | |
0977f817 | 2272 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2273 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2274 | * when we were reading the num_txbdfree and checking for available | |
2275 | * space, that's because outside of this function it can only grow, | |
2276 | * and once we've got needed space, it cannot suddenly disappear. | |
2277 | * | |
2278 | * The lock also protects us from gfar_error(), which can modify | |
2279 | * regs->tstat and thus retrigger the transfers, which is why we | |
2280 | * also must grab the lock before setting ready bit for the first | |
2281 | * to be transmitted BD. | |
2282 | */ | |
2283 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2284 | ||
0977f817 | 2285 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2286 | * semantics (it requires synchronization between cacheable and |
2287 | * uncacheable mappings, which eieio doesn't provide and which we | |
2288 | * don't need), thus requiring a more expensive sync instruction. At | |
2289 | * some point, the set of architecture-independent barrier functions | |
2290 | * should be expanded to include weaker barriers. | |
2291 | */ | |
3b6330ce | 2292 | eieio(); |
7f7f5316 | 2293 | |
4669bc90 DH |
2294 | txbdp_start->lstatus = lstatus; |
2295 | ||
0eddba52 AV |
2296 | eieio(); /* force lstatus write before tx_skbuff */ |
2297 | ||
2298 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2299 | ||
4669bc90 | 2300 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2301 | * (wrapping if necessary) |
2302 | */ | |
a12f801d | 2303 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2304 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2305 | |
a12f801d | 2306 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2307 | |
2308 | /* reduce TxBD free count */ | |
f0ee7acf | 2309 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2310 | |
2311 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2312 | * are full. We need to tell the kernel to stop sending us stuff. |
2313 | */ | |
a12f801d | 2314 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2315 | netif_tx_stop_queue(txq); |
1da177e4 | 2316 | |
09f75cd7 | 2317 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2318 | } |
2319 | ||
1da177e4 | 2320 | /* Tell the DMA to go go go */ |
fba4ed03 | 2321 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2322 | |
2323 | /* Unlock priv */ | |
a12f801d | 2324 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2325 | |
54dc79fe | 2326 | return NETDEV_TX_OK; |
1da177e4 LT |
2327 | } |
2328 | ||
2329 | /* Stops the kernel queue, and halts the controller */ | |
2330 | static int gfar_close(struct net_device *dev) | |
2331 | { | |
2332 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2333 | |
46ceb60c | 2334 | disable_napi(priv); |
bea3348e | 2335 | |
ab939905 | 2336 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2337 | stop_gfar(dev); |
2338 | ||
bb40dcbb AF |
2339 | /* Disconnect from the PHY */ |
2340 | phy_disconnect(priv->phydev); | |
2341 | priv->phydev = NULL; | |
1da177e4 | 2342 | |
fba4ed03 | 2343 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2344 | |
2345 | return 0; | |
2346 | } | |
2347 | ||
1da177e4 | 2348 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2349 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2350 | { |
7f7f5316 | 2351 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2352 | |
2353 | return 0; | |
2354 | } | |
2355 | ||
f3dc1586 SP |
2356 | /* Check if rx parser should be activated */ |
2357 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2358 | { | |
2359 | struct gfar __iomem *regs; | |
2360 | u32 tempval; | |
2361 | ||
2362 | regs = priv->gfargrp[0].regs; | |
2363 | ||
2364 | tempval = gfar_read(®s->rctrl); | |
2365 | /* If parse is no longer required, then disable parser */ | |
ba779711 | 2366 | if (tempval & RCTRL_REQ_PARSER) { |
f3dc1586 | 2367 | tempval |= RCTRL_PRSDEP_INIT; |
ba779711 CM |
2368 | priv->uses_rxfcb = 1; |
2369 | } else { | |
f3dc1586 | 2370 | tempval &= ~RCTRL_PRSDEP_INIT; |
ba779711 CM |
2371 | priv->uses_rxfcb = 0; |
2372 | } | |
f3dc1586 SP |
2373 | gfar_write(®s->rctrl, tempval); |
2374 | } | |
2375 | ||
0bbaf069 | 2376 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2377 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2378 | { |
2379 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2380 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2381 | unsigned long flags; |
2382 | u32 tempval; | |
2383 | ||
46ceb60c | 2384 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2385 | local_irq_save(flags); |
2386 | lock_rx_qs(priv); | |
0bbaf069 | 2387 | |
f646968f | 2388 | if (features & NETIF_F_HW_VLAN_CTAG_TX) { |
0bbaf069 | 2389 | /* Enable VLAN tag insertion */ |
f4983704 | 2390 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2391 | tempval |= TCTRL_VLINS; |
f4983704 | 2392 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2393 | } else { |
2394 | /* Disable VLAN tag insertion */ | |
f4983704 | 2395 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2396 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2397 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2398 | } |
0bbaf069 | 2399 | |
f646968f | 2400 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
87c288c6 JP |
2401 | /* Enable VLAN tag extraction */ |
2402 | tempval = gfar_read(®s->rctrl); | |
2403 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2404 | gfar_write(®s->rctrl, tempval); | |
ba779711 | 2405 | priv->uses_rxfcb = 1; |
87c288c6 | 2406 | } else { |
0bbaf069 | 2407 | /* Disable VLAN tag extraction */ |
f4983704 | 2408 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2409 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2410 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2411 | |
2412 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2413 | } |
2414 | ||
77ecaf2d DH |
2415 | gfar_change_mtu(dev, dev->mtu); |
2416 | ||
fba4ed03 SG |
2417 | unlock_rx_qs(priv); |
2418 | local_irq_restore(flags); | |
0bbaf069 KG |
2419 | } |
2420 | ||
1da177e4 LT |
2421 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2422 | { | |
2423 | int tempsize, tempval; | |
2424 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2425 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2426 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2427 | int frame_size = new_mtu + ETH_HLEN; |
2428 | ||
1da177e4 | 2429 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2430 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2431 | return -EINVAL; |
2432 | } | |
2433 | ||
ba779711 | 2434 | if (priv->uses_rxfcb) |
77ecaf2d DH |
2435 | frame_size += GMAC_FCB_LEN; |
2436 | ||
2437 | frame_size += priv->padding; | |
2438 | ||
bc4598bc JC |
2439 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2440 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2441 | |
2442 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2443 | * stopped, and we changed something |
2444 | */ | |
1da177e4 LT |
2445 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2446 | stop_gfar(dev); | |
2447 | ||
2448 | priv->rx_buffer_size = tempsize; | |
2449 | ||
2450 | dev->mtu = new_mtu; | |
2451 | ||
f4983704 SG |
2452 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2453 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2454 | |
2455 | /* If the mtu is larger than the max size for standard | |
2456 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2457 | * to allow huge frames, and to check the length |
2458 | */ | |
f4983704 | 2459 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2460 | |
7d350977 | 2461 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2462 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2463 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2464 | else | |
2465 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2466 | ||
f4983704 | 2467 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2468 | |
2469 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2470 | startup_gfar(dev); | |
2471 | ||
2472 | return 0; | |
2473 | } | |
2474 | ||
ab939905 | 2475 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2476 | * transmitted after a set amount of time. |
2477 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2478 | * starting over will fix the problem. |
2479 | */ | |
2480 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2481 | { |
ab939905 | 2482 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2483 | reset_task); |
4826857f | 2484 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2485 | |
2486 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2487 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2488 | stop_gfar(dev); |
2489 | startup_gfar(dev); | |
fba4ed03 | 2490 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2491 | } |
2492 | ||
263ba320 | 2493 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2494 | } |
2495 | ||
ab939905 SS |
2496 | static void gfar_timeout(struct net_device *dev) |
2497 | { | |
2498 | struct gfar_private *priv = netdev_priv(dev); | |
2499 | ||
2500 | dev->stats.tx_errors++; | |
2501 | schedule_work(&priv->reset_task); | |
2502 | } | |
2503 | ||
acbc0f03 EL |
2504 | static void gfar_align_skb(struct sk_buff *skb) |
2505 | { | |
2506 | /* We need the data buffer to be aligned properly. We will reserve | |
2507 | * as many bytes as needed to align the data properly | |
2508 | */ | |
2509 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2510 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2511 | } |
2512 | ||
1da177e4 | 2513 | /* Interrupt Handler for Transmit complete */ |
c233cf40 | 2514 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2515 | { |
a12f801d | 2516 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2517 | struct netdev_queue *txq; |
d080cd63 | 2518 | struct gfar_private *priv = netdev_priv(dev); |
f0ee7acf | 2519 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2520 | struct txbd8 *lbdp = NULL; |
a12f801d | 2521 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2522 | struct sk_buff *skb; |
2523 | int skb_dirtytx; | |
a12f801d | 2524 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2525 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2526 | int i; |
d080cd63 | 2527 | int howmany = 0; |
d8a0f1b0 PG |
2528 | int tqi = tx_queue->qindex; |
2529 | unsigned int bytes_sent = 0; | |
4669bc90 | 2530 | u32 lstatus; |
f0ee7acf | 2531 | size_t buflen; |
1da177e4 | 2532 | |
d8a0f1b0 | 2533 | txq = netdev_get_tx_queue(dev, tqi); |
a12f801d SG |
2534 | bdp = tx_queue->dirty_tx; |
2535 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2536 | |
a12f801d | 2537 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2538 | unsigned long flags; |
2539 | ||
4669bc90 | 2540 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2541 | |
0977f817 | 2542 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2543 | * Also, we need to dma_unmap_single() the TxPAL. |
2544 | */ | |
2244d07b | 2545 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2546 | nr_txbds = frags + 2; |
2547 | else | |
2548 | nr_txbds = frags + 1; | |
2549 | ||
2550 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2551 | |
4669bc90 | 2552 | lstatus = lbdp->lstatus; |
1da177e4 | 2553 | |
4669bc90 DH |
2554 | /* Only clean completed frames */ |
2555 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2556 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2557 | break; |
2558 | ||
2244d07b | 2559 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2560 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2561 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2562 | } else |
2563 | buflen = bdp->length; | |
2564 | ||
369ec162 | 2565 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2566 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2567 | |
2244d07b | 2568 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2569 | struct skb_shared_hwtstamps shhwtstamps; |
2570 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2571 | |
f0ee7acf MR |
2572 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2573 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2574 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2575 | skb_tstamp_tx(skb, &shhwtstamps); |
2576 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2577 | bdp = next; | |
2578 | } | |
81183059 | 2579 | |
4669bc90 DH |
2580 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2581 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2582 | |
4669bc90 | 2583 | for (i = 0; i < frags; i++) { |
369ec162 | 2584 | dma_unmap_page(priv->dev, bdp->bufPtr, |
bc4598bc | 2585 | bdp->length, DMA_TO_DEVICE); |
4669bc90 DH |
2586 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2587 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2588 | } | |
1da177e4 | 2589 | |
50ad076b | 2590 | bytes_sent += GFAR_CB(skb)->bytes_sent; |
d8a0f1b0 | 2591 | |
acb600de | 2592 | dev_kfree_skb_any(skb); |
0fd56bb5 | 2593 | |
a12f801d | 2594 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2595 | |
4669bc90 | 2596 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2597 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2598 | |
2599 | howmany++; | |
a3bc1f11 | 2600 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2601 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2602 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2603 | } |
1da177e4 | 2604 | |
4669bc90 | 2605 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2606 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2607 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2608 | |
4669bc90 | 2609 | /* Update dirty indicators */ |
a12f801d SG |
2610 | tx_queue->skb_dirtytx = skb_dirtytx; |
2611 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2612 | |
d8a0f1b0 | 2613 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
d080cd63 DH |
2614 | } |
2615 | ||
f4983704 | 2616 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2617 | { |
a6d0b91a AV |
2618 | unsigned long flags; |
2619 | ||
fba4ed03 SG |
2620 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2621 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2622 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2623 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2624 | } else { |
0977f817 | 2625 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2626 | * because of the packets that have already arrived. |
2627 | */ | |
f4983704 | 2628 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2629 | } |
fba4ed03 | 2630 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2631 | |
8c7396ae | 2632 | } |
1da177e4 | 2633 | |
8c7396ae | 2634 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2635 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2636 | { |
f4983704 | 2637 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2638 | return IRQ_HANDLED; |
2639 | } | |
2640 | ||
a12f801d | 2641 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2642 | struct sk_buff *skb) |
815b97c6 | 2643 | { |
a12f801d | 2644 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2645 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2646 | dma_addr_t buf; |
815b97c6 | 2647 | |
369ec162 | 2648 | buf = dma_map_single(priv->dev, skb->data, |
8a102fe0 | 2649 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
a12f801d | 2650 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2651 | } |
2652 | ||
2281a0f3 | 2653 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2654 | { |
2655 | struct gfar_private *priv = netdev_priv(dev); | |
acb600de | 2656 | struct sk_buff *skb; |
1da177e4 | 2657 | |
acbc0f03 | 2658 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2659 | if (!skb) |
1da177e4 LT |
2660 | return NULL; |
2661 | ||
acbc0f03 | 2662 | gfar_align_skb(skb); |
7f7f5316 | 2663 | |
acbc0f03 EL |
2664 | return skb; |
2665 | } | |
2666 | ||
2281a0f3 | 2667 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 | 2668 | { |
acb600de | 2669 | return gfar_alloc_skb(dev); |
1da177e4 LT |
2670 | } |
2671 | ||
298e1a9e | 2672 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2673 | { |
298e1a9e | 2674 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2675 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2676 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2677 | ||
0977f817 | 2678 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2679 | if (status & RXBD_TRUNCATED) { |
2680 | stats->rx_length_errors++; | |
2681 | ||
212079df | 2682 | atomic64_inc(&estats->rx_trunc); |
1da177e4 LT |
2683 | |
2684 | return; | |
2685 | } | |
2686 | /* Count the errors, if there were any */ | |
2687 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2688 | stats->rx_length_errors++; | |
2689 | ||
2690 | if (status & RXBD_LARGE) | |
212079df | 2691 | atomic64_inc(&estats->rx_large); |
1da177e4 | 2692 | else |
212079df | 2693 | atomic64_inc(&estats->rx_short); |
1da177e4 LT |
2694 | } |
2695 | if (status & RXBD_NONOCTET) { | |
2696 | stats->rx_frame_errors++; | |
212079df | 2697 | atomic64_inc(&estats->rx_nonoctet); |
1da177e4 LT |
2698 | } |
2699 | if (status & RXBD_CRCERR) { | |
212079df | 2700 | atomic64_inc(&estats->rx_crcerr); |
1da177e4 LT |
2701 | stats->rx_crc_errors++; |
2702 | } | |
2703 | if (status & RXBD_OVERRUN) { | |
212079df | 2704 | atomic64_inc(&estats->rx_overrun); |
1da177e4 LT |
2705 | stats->rx_crc_errors++; |
2706 | } | |
2707 | } | |
2708 | ||
f4983704 | 2709 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2710 | { |
f4983704 | 2711 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2712 | return IRQ_HANDLED; |
2713 | } | |
2714 | ||
0bbaf069 KG |
2715 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2716 | { | |
2717 | /* If valid headers were found, and valid sums | |
2718 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2719 | * checksumming is necessary. Otherwise, it is [FIXME] |
2720 | */ | |
7f7f5316 | 2721 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2722 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2723 | else | |
bc8acf2c | 2724 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2725 | } |
2726 | ||
2727 | ||
0977f817 | 2728 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
61db26c6 CM |
2729 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
2730 | int amount_pull, struct napi_struct *napi) | |
1da177e4 LT |
2731 | { |
2732 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2733 | struct rxfcb *fcb = NULL; |
1da177e4 | 2734 | |
2c2db48a DH |
2735 | /* fcb is at the beginning if exists */ |
2736 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2737 | |
0977f817 JC |
2738 | /* Remove the FCB from the skb |
2739 | * Remove the padded bytes, if there are any | |
2740 | */ | |
f74dac08 SG |
2741 | if (amount_pull) { |
2742 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2743 | skb_pull(skb, amount_pull); |
f74dac08 | 2744 | } |
0bbaf069 | 2745 | |
cc772ab7 MR |
2746 | /* Get receive timestamp from the skb */ |
2747 | if (priv->hwts_rx_en) { | |
2748 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2749 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2750 | |
cc772ab7 MR |
2751 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2752 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2753 | } | |
2754 | ||
2755 | if (priv->padding) | |
2756 | skb_pull(skb, priv->padding); | |
2757 | ||
8b3afe95 | 2758 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2759 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2760 | |
2c2db48a DH |
2761 | /* Tell the skb what kind of packet this is */ |
2762 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2763 | |
f646968f | 2764 | /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. |
32f7fd44 JP |
2765 | * Even if vlan rx accel is disabled, on some chips |
2766 | * RXFCB_VLN is pseudo randomly set. | |
2767 | */ | |
f646968f | 2768 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && |
32f7fd44 | 2769 | fcb->flags & RXFCB_VLN) |
e5905c83 | 2770 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl); |
87c288c6 | 2771 | |
2c2db48a | 2772 | /* Send the packet up the stack */ |
953d2768 | 2773 | napi_gro_receive(napi, skb); |
0bbaf069 | 2774 | |
1da177e4 LT |
2775 | } |
2776 | ||
2777 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2778 | * until the budget/quota has been reached. Returns the number |
2779 | * of frames handled | |
1da177e4 | 2780 | */ |
a12f801d | 2781 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2782 | { |
a12f801d | 2783 | struct net_device *dev = rx_queue->dev; |
31de198b | 2784 | struct rxbd8 *bdp, *base; |
1da177e4 | 2785 | struct sk_buff *skb; |
2c2db48a DH |
2786 | int pkt_len; |
2787 | int amount_pull; | |
1da177e4 LT |
2788 | int howmany = 0; |
2789 | struct gfar_private *priv = netdev_priv(dev); | |
2790 | ||
2791 | /* Get the first full descriptor */ | |
a12f801d SG |
2792 | bdp = rx_queue->cur_rx; |
2793 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2794 | |
ba779711 | 2795 | amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; |
2c2db48a | 2796 | |
1da177e4 | 2797 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2798 | struct sk_buff *newskb; |
bc4598bc | 2799 | |
3b6330ce | 2800 | rmb(); |
815b97c6 AF |
2801 | |
2802 | /* Add another skb for the future */ | |
2803 | newskb = gfar_new_skb(dev); | |
2804 | ||
a12f801d | 2805 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2806 | |
369ec162 | 2807 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2808 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2809 | |
63b88b90 | 2810 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2811 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2812 | bdp->status = RXBD_LARGE; |
2813 | ||
815b97c6 AF |
2814 | /* We drop the frame if we failed to allocate a new buffer */ |
2815 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2816 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2817 | count_errors(bdp->status, dev); |
2818 | ||
2819 | if (unlikely(!newskb)) | |
2820 | newskb = skb; | |
acbc0f03 | 2821 | else if (skb) |
acb600de | 2822 | dev_kfree_skb(skb); |
815b97c6 | 2823 | } else { |
1da177e4 | 2824 | /* Increment the number of packets */ |
a7f38041 | 2825 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2826 | howmany++; |
2827 | ||
2c2db48a DH |
2828 | if (likely(skb)) { |
2829 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2830 | /* Remove the FCS from the packet length */ | |
2831 | skb_put(skb, pkt_len); | |
a7f38041 | 2832 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2833 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2834 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2835 | &rx_queue->grp->napi); |
2c2db48a DH |
2836 | |
2837 | } else { | |
59deab26 | 2838 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2839 | rx_queue->stats.rx_dropped++; |
212079df | 2840 | atomic64_inc(&priv->extra_stats.rx_skbmissing); |
2c2db48a | 2841 | } |
1da177e4 | 2842 | |
1da177e4 LT |
2843 | } |
2844 | ||
a12f801d | 2845 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2846 | |
815b97c6 | 2847 | /* Setup the new bdp */ |
a12f801d | 2848 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2849 | |
2850 | /* Update to the next pointer */ | |
a12f801d | 2851 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2852 | |
2853 | /* update to point at the next skb */ | |
bc4598bc JC |
2854 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2855 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2856 | } |
2857 | ||
2858 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2859 | rx_queue->cur_rx = bdp; |
1da177e4 | 2860 | |
1da177e4 LT |
2861 | return howmany; |
2862 | } | |
2863 | ||
5eaedf31 CM |
2864 | static int gfar_poll_sq(struct napi_struct *napi, int budget) |
2865 | { | |
2866 | struct gfar_priv_grp *gfargrp = | |
2867 | container_of(napi, struct gfar_priv_grp, napi); | |
2868 | struct gfar __iomem *regs = gfargrp->regs; | |
2869 | struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0]; | |
2870 | struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0]; | |
2871 | int work_done = 0; | |
2872 | ||
2873 | /* Clear IEVENT, so interrupts aren't called again | |
2874 | * because of the packets that have already arrived | |
2875 | */ | |
2876 | gfar_write(®s->ievent, IEVENT_RTX_MASK); | |
2877 | ||
2878 | /* run Tx cleanup to completion */ | |
2879 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) | |
2880 | gfar_clean_tx_ring(tx_queue); | |
2881 | ||
2882 | work_done = gfar_clean_rx_ring(rx_queue, budget); | |
2883 | ||
2884 | if (work_done < budget) { | |
2885 | napi_complete(napi); | |
2886 | /* Clear the halt bit in RSTAT */ | |
2887 | gfar_write(®s->rstat, gfargrp->rstat); | |
2888 | ||
2889 | gfar_write(®s->imask, IMASK_DEFAULT); | |
2890 | ||
2891 | /* If we are coalescing interrupts, update the timer | |
2892 | * Otherwise, clear it | |
2893 | */ | |
2894 | gfar_write(®s->txic, 0); | |
2895 | if (likely(tx_queue->txcoalescing)) | |
2896 | gfar_write(®s->txic, tx_queue->txic); | |
2897 | ||
2898 | gfar_write(®s->rxic, 0); | |
2899 | if (unlikely(rx_queue->rxcoalescing)) | |
2900 | gfar_write(®s->rxic, rx_queue->rxic); | |
2901 | } | |
2902 | ||
2903 | return work_done; | |
2904 | } | |
2905 | ||
bea3348e | 2906 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2907 | { |
bc4598bc JC |
2908 | struct gfar_priv_grp *gfargrp = |
2909 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2910 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2911 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2912 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2913 | struct gfar_priv_rx_q *rx_queue = NULL; |
c233cf40 | 2914 | int work_done = 0, work_done_per_q = 0; |
39c0a0d5 | 2915 | int i, budget_per_q = 0; |
3ba405db | 2916 | int has_tx_work = 0; |
6be5ed3f CM |
2917 | unsigned long rstat_rxf; |
2918 | int num_act_queues; | |
fba4ed03 | 2919 | |
8c7396ae | 2920 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2921 | * because of the packets that have already arrived |
2922 | */ | |
f4983704 | 2923 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2924 | |
6be5ed3f CM |
2925 | rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; |
2926 | ||
2927 | num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); | |
2928 | if (num_act_queues) | |
2929 | budget_per_q = budget/num_act_queues; | |
2930 | ||
3ba405db CM |
2931 | for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { |
2932 | tx_queue = priv->tx_queue[i]; | |
2933 | /* run Tx cleanup to completion */ | |
2934 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { | |
2935 | gfar_clean_tx_ring(tx_queue); | |
2936 | has_tx_work = 1; | |
c233cf40 | 2937 | } |
3ba405db | 2938 | } |
fba4ed03 | 2939 | |
3ba405db CM |
2940 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
2941 | /* skip queue if not active */ | |
2942 | if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) | |
2943 | continue; | |
1da177e4 | 2944 | |
3ba405db CM |
2945 | rx_queue = priv->rx_queue[i]; |
2946 | work_done_per_q = | |
2947 | gfar_clean_rx_ring(rx_queue, budget_per_q); | |
2948 | work_done += work_done_per_q; | |
2949 | ||
2950 | /* finished processing this queue */ | |
2951 | if (work_done_per_q < budget_per_q) { | |
2952 | /* clear active queue hw indication */ | |
2953 | gfar_write(®s->rstat, | |
2954 | RSTAT_CLEAR_RXF0 >> i); | |
2955 | num_act_queues--; | |
2956 | ||
2957 | if (!num_act_queues) | |
2958 | break; | |
2959 | } | |
2960 | } | |
42199884 | 2961 | |
3ba405db | 2962 | if (!num_act_queues && !has_tx_work) { |
1da177e4 | 2963 | |
3ba405db | 2964 | napi_complete(napi); |
1da177e4 | 2965 | |
3ba405db CM |
2966 | /* Clear the halt bit in RSTAT */ |
2967 | gfar_write(®s->rstat, gfargrp->rstat); | |
1da177e4 | 2968 | |
3ba405db | 2969 | gfar_write(®s->imask, IMASK_DEFAULT); |
c233cf40 | 2970 | |
3ba405db CM |
2971 | /* If we are coalescing interrupts, update the timer |
2972 | * Otherwise, clear it | |
2973 | */ | |
2974 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, | |
2975 | gfargrp->tx_bit_map); | |
1da177e4 LT |
2976 | } |
2977 | ||
c233cf40 | 2978 | return work_done; |
1da177e4 | 2979 | } |
1da177e4 | 2980 | |
f2d71c2d | 2981 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2982 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2983 | * without having to re-enable interrupts. It's not called while |
2984 | * the interrupt routine is executing. | |
2985 | */ | |
2986 | static void gfar_netpoll(struct net_device *dev) | |
2987 | { | |
2988 | struct gfar_private *priv = netdev_priv(dev); | |
3a2e16c8 | 2989 | int i; |
f2d71c2d VW |
2990 | |
2991 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2992 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c | 2993 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
2994 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
2995 | ||
2996 | disable_irq(gfar_irq(grp, TX)->irq); | |
2997 | disable_irq(gfar_irq(grp, RX)->irq); | |
2998 | disable_irq(gfar_irq(grp, ER)->irq); | |
2999 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
3000 | enable_irq(gfar_irq(grp, ER)->irq); | |
3001 | enable_irq(gfar_irq(grp, RX)->irq); | |
3002 | enable_irq(gfar_irq(grp, TX)->irq); | |
46ceb60c | 3003 | } |
f2d71c2d | 3004 | } else { |
46ceb60c | 3005 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
3006 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
3007 | ||
3008 | disable_irq(gfar_irq(grp, TX)->irq); | |
3009 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
3010 | enable_irq(gfar_irq(grp, TX)->irq); | |
43de004b | 3011 | } |
f2d71c2d VW |
3012 | } |
3013 | } | |
3014 | #endif | |
3015 | ||
1da177e4 | 3016 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 3017 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 3018 | { |
f4983704 | 3019 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
3020 | |
3021 | /* Save ievent for future reference */ | |
f4983704 | 3022 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 3023 | |
1da177e4 | 3024 | /* Check for reception */ |
538cc7ee | 3025 | if (events & IEVENT_RX_MASK) |
f4983704 | 3026 | gfar_receive(irq, grp_id); |
1da177e4 LT |
3027 | |
3028 | /* Check for transmit completion */ | |
538cc7ee | 3029 | if (events & IEVENT_TX_MASK) |
f4983704 | 3030 | gfar_transmit(irq, grp_id); |
1da177e4 | 3031 | |
538cc7ee SS |
3032 | /* Check for errors */ |
3033 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 3034 | gfar_error(irq, grp_id); |
1da177e4 LT |
3035 | |
3036 | return IRQ_HANDLED; | |
3037 | } | |
3038 | ||
23402bdd CM |
3039 | static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) |
3040 | { | |
3041 | struct phy_device *phydev = priv->phydev; | |
3042 | u32 val = 0; | |
3043 | ||
3044 | if (!phydev->duplex) | |
3045 | return val; | |
3046 | ||
3047 | if (!priv->pause_aneg_en) { | |
3048 | if (priv->tx_pause_en) | |
3049 | val |= MACCFG1_TX_FLOW; | |
3050 | if (priv->rx_pause_en) | |
3051 | val |= MACCFG1_RX_FLOW; | |
3052 | } else { | |
3053 | u16 lcl_adv, rmt_adv; | |
3054 | u8 flowctrl; | |
3055 | /* get link partner capabilities */ | |
3056 | rmt_adv = 0; | |
3057 | if (phydev->pause) | |
3058 | rmt_adv = LPA_PAUSE_CAP; | |
3059 | if (phydev->asym_pause) | |
3060 | rmt_adv |= LPA_PAUSE_ASYM; | |
3061 | ||
3062 | lcl_adv = mii_advertise_flowctrl(phydev->advertising); | |
3063 | ||
3064 | flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); | |
3065 | if (flowctrl & FLOW_CTRL_TX) | |
3066 | val |= MACCFG1_TX_FLOW; | |
3067 | if (flowctrl & FLOW_CTRL_RX) | |
3068 | val |= MACCFG1_RX_FLOW; | |
3069 | } | |
3070 | ||
3071 | return val; | |
3072 | } | |
3073 | ||
1da177e4 LT |
3074 | /* Called every time the controller might need to be made |
3075 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 3076 | * information through variables in the phydev structure, and this |
1da177e4 LT |
3077 | * function converts those variables into the appropriate |
3078 | * register values, and can bring down the device if needed. | |
3079 | */ | |
3080 | static void adjust_link(struct net_device *dev) | |
3081 | { | |
3082 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3083 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
3084 | unsigned long flags; |
3085 | struct phy_device *phydev = priv->phydev; | |
3086 | int new_state = 0; | |
3087 | ||
fba4ed03 SG |
3088 | local_irq_save(flags); |
3089 | lock_tx_qs(priv); | |
3090 | ||
bb40dcbb | 3091 | if (phydev->link) { |
23402bdd | 3092 | u32 tempval1 = gfar_read(®s->maccfg1); |
bb40dcbb | 3093 | u32 tempval = gfar_read(®s->maccfg2); |
7f7f5316 | 3094 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 3095 | |
1da177e4 | 3096 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
3097 | * If not, we operate in half-duplex mode. |
3098 | */ | |
bb40dcbb AF |
3099 | if (phydev->duplex != priv->oldduplex) { |
3100 | new_state = 1; | |
3101 | if (!(phydev->duplex)) | |
1da177e4 | 3102 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 3103 | else |
1da177e4 | 3104 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 3105 | |
bb40dcbb | 3106 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
3107 | } |
3108 | ||
bb40dcbb AF |
3109 | if (phydev->speed != priv->oldspeed) { |
3110 | new_state = 1; | |
3111 | switch (phydev->speed) { | |
1da177e4 | 3112 | case 1000: |
1da177e4 LT |
3113 | tempval = |
3114 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
3115 | |
3116 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3117 | break; |
3118 | case 100: | |
3119 | case 10: | |
1da177e4 LT |
3120 | tempval = |
3121 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
3122 | |
3123 | /* Reduced mode distinguishes | |
0977f817 JC |
3124 | * between 10 and 100 |
3125 | */ | |
7f7f5316 AF |
3126 | if (phydev->speed == SPEED_100) |
3127 | ecntrl |= ECNTRL_R100; | |
3128 | else | |
3129 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3130 | break; |
3131 | default: | |
59deab26 JP |
3132 | netif_warn(priv, link, dev, |
3133 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3134 | phydev->speed); | |
1da177e4 LT |
3135 | break; |
3136 | } | |
3137 | ||
bb40dcbb | 3138 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3139 | } |
3140 | ||
23402bdd CM |
3141 | tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
3142 | tempval1 |= gfar_get_flowctrl_cfg(priv); | |
3143 | ||
3144 | gfar_write(®s->maccfg1, tempval1); | |
bb40dcbb | 3145 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3146 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3147 | |
1da177e4 | 3148 | if (!priv->oldlink) { |
bb40dcbb | 3149 | new_state = 1; |
1da177e4 | 3150 | priv->oldlink = 1; |
1da177e4 | 3151 | } |
bb40dcbb AF |
3152 | } else if (priv->oldlink) { |
3153 | new_state = 1; | |
3154 | priv->oldlink = 0; | |
3155 | priv->oldspeed = 0; | |
3156 | priv->oldduplex = -1; | |
1da177e4 | 3157 | } |
1da177e4 | 3158 | |
bb40dcbb AF |
3159 | if (new_state && netif_msg_link(priv)) |
3160 | phy_print_status(phydev); | |
fba4ed03 SG |
3161 | unlock_tx_qs(priv); |
3162 | local_irq_restore(flags); | |
bb40dcbb | 3163 | } |
1da177e4 LT |
3164 | |
3165 | /* Update the hash table based on the current list of multicast | |
3166 | * addresses we subscribe to. Also, change the promiscuity of | |
3167 | * the device based on the flags (this function is called | |
0977f817 JC |
3168 | * whenever dev->flags is changed |
3169 | */ | |
1da177e4 LT |
3170 | static void gfar_set_multi(struct net_device *dev) |
3171 | { | |
22bedad3 | 3172 | struct netdev_hw_addr *ha; |
1da177e4 | 3173 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3174 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3175 | u32 tempval; |
3176 | ||
a12f801d | 3177 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3178 | /* Set RCTRL to PROM */ |
3179 | tempval = gfar_read(®s->rctrl); | |
3180 | tempval |= RCTRL_PROM; | |
3181 | gfar_write(®s->rctrl, tempval); | |
3182 | } else { | |
3183 | /* Set RCTRL to not PROM */ | |
3184 | tempval = gfar_read(®s->rctrl); | |
3185 | tempval &= ~(RCTRL_PROM); | |
3186 | gfar_write(®s->rctrl, tempval); | |
3187 | } | |
6aa20a22 | 3188 | |
a12f801d | 3189 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3190 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3191 | gfar_write(®s->igaddr0, 0xffffffff); |
3192 | gfar_write(®s->igaddr1, 0xffffffff); | |
3193 | gfar_write(®s->igaddr2, 0xffffffff); | |
3194 | gfar_write(®s->igaddr3, 0xffffffff); | |
3195 | gfar_write(®s->igaddr4, 0xffffffff); | |
3196 | gfar_write(®s->igaddr5, 0xffffffff); | |
3197 | gfar_write(®s->igaddr6, 0xffffffff); | |
3198 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3199 | gfar_write(®s->gaddr0, 0xffffffff); |
3200 | gfar_write(®s->gaddr1, 0xffffffff); | |
3201 | gfar_write(®s->gaddr2, 0xffffffff); | |
3202 | gfar_write(®s->gaddr3, 0xffffffff); | |
3203 | gfar_write(®s->gaddr4, 0xffffffff); | |
3204 | gfar_write(®s->gaddr5, 0xffffffff); | |
3205 | gfar_write(®s->gaddr6, 0xffffffff); | |
3206 | gfar_write(®s->gaddr7, 0xffffffff); | |
3207 | } else { | |
7f7f5316 AF |
3208 | int em_num; |
3209 | int idx; | |
3210 | ||
1da177e4 | 3211 | /* zero out the hash */ |
0bbaf069 KG |
3212 | gfar_write(®s->igaddr0, 0x0); |
3213 | gfar_write(®s->igaddr1, 0x0); | |
3214 | gfar_write(®s->igaddr2, 0x0); | |
3215 | gfar_write(®s->igaddr3, 0x0); | |
3216 | gfar_write(®s->igaddr4, 0x0); | |
3217 | gfar_write(®s->igaddr5, 0x0); | |
3218 | gfar_write(®s->igaddr6, 0x0); | |
3219 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3220 | gfar_write(®s->gaddr0, 0x0); |
3221 | gfar_write(®s->gaddr1, 0x0); | |
3222 | gfar_write(®s->gaddr2, 0x0); | |
3223 | gfar_write(®s->gaddr3, 0x0); | |
3224 | gfar_write(®s->gaddr4, 0x0); | |
3225 | gfar_write(®s->gaddr5, 0x0); | |
3226 | gfar_write(®s->gaddr6, 0x0); | |
3227 | gfar_write(®s->gaddr7, 0x0); | |
3228 | ||
7f7f5316 AF |
3229 | /* If we have extended hash tables, we need to |
3230 | * clear the exact match registers to prepare for | |
0977f817 JC |
3231 | * setting them |
3232 | */ | |
7f7f5316 AF |
3233 | if (priv->extended_hash) { |
3234 | em_num = GFAR_EM_NUM + 1; | |
3235 | gfar_clear_exact_match(dev); | |
3236 | idx = 1; | |
3237 | } else { | |
3238 | idx = 0; | |
3239 | em_num = 0; | |
3240 | } | |
3241 | ||
4cd24eaf | 3242 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3243 | return; |
3244 | ||
3245 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3246 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3247 | if (idx < em_num) { |
22bedad3 | 3248 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3249 | idx++; |
3250 | } else | |
22bedad3 | 3251 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3252 | } |
3253 | } | |
1da177e4 LT |
3254 | } |
3255 | ||
7f7f5316 AF |
3256 | |
3257 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3258 | * don't interfere with normal reception |
3259 | */ | |
7f7f5316 AF |
3260 | static void gfar_clear_exact_match(struct net_device *dev) |
3261 | { | |
3262 | int idx; | |
6a3c910c | 3263 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3264 | |
bc4598bc | 3265 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3266 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3267 | } |
3268 | ||
1da177e4 LT |
3269 | /* Set the appropriate hash bit for the given addr */ |
3270 | /* The algorithm works like so: | |
3271 | * 1) Take the Destination Address (ie the multicast address), and | |
3272 | * do a CRC on it (little endian), and reverse the bits of the | |
3273 | * result. | |
3274 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3275 | * table. The table is controlled through 8 32-bit registers: | |
3276 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3277 | * gaddr7. This means that the 3 most significant bits in the | |
3278 | * hash index which gaddr register to use, and the 5 other bits | |
3279 | * indicate which bit (assuming an IBM numbering scheme, which | |
3280 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3281 | * the entry. |
3282 | */ | |
1da177e4 LT |
3283 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3284 | { | |
3285 | u32 tempval; | |
3286 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3287 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3288 | int width = priv->hash_width; |
3289 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3290 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3291 | u32 value = (1 << (31-whichbit)); |
3292 | ||
0bbaf069 | 3293 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3294 | tempval |= value; |
0bbaf069 | 3295 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3296 | } |
3297 | ||
7f7f5316 AF |
3298 | |
3299 | /* There are multiple MAC Address register pairs on some controllers | |
3300 | * This function sets the numth pair to a given address | |
3301 | */ | |
b6bc7650 JP |
3302 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3303 | const u8 *addr) | |
7f7f5316 AF |
3304 | { |
3305 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3306 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3307 | int idx; |
6a3c910c | 3308 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3309 | u32 tempval; |
f4983704 | 3310 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3311 | |
3312 | macptr += num*2; | |
3313 | ||
0977f817 JC |
3314 | /* Now copy it into the mac registers backwards, cuz |
3315 | * little endian is silly | |
3316 | */ | |
6a3c910c JP |
3317 | for (idx = 0; idx < ETH_ALEN; idx++) |
3318 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3319 | |
3320 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3321 | ||
3322 | tempval = *((u32 *) (tmpbuf + 4)); | |
3323 | ||
3324 | gfar_write(macptr+1, tempval); | |
3325 | } | |
3326 | ||
1da177e4 | 3327 | /* GFAR error interrupt handler */ |
f4983704 | 3328 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3329 | { |
f4983704 SG |
3330 | struct gfar_priv_grp *gfargrp = grp_id; |
3331 | struct gfar __iomem *regs = gfargrp->regs; | |
3332 | struct gfar_private *priv= gfargrp->priv; | |
3333 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3334 | |
3335 | /* Save ievent for future reference */ | |
f4983704 | 3336 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3337 | |
3338 | /* Clear IEVENT */ | |
f4983704 | 3339 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3340 | |
3341 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3342 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3343 | (events & IEVENT_MAG)) |
3344 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3345 | |
3346 | /* Hmm... */ | |
0bbaf069 | 3347 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3348 | netdev_dbg(dev, |
3349 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3350 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3351 | |
3352 | /* Update the error counters */ | |
3353 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3354 | dev->stats.tx_errors++; |
1da177e4 LT |
3355 | |
3356 | if (events & IEVENT_LC) | |
09f75cd7 | 3357 | dev->stats.tx_window_errors++; |
1da177e4 | 3358 | if (events & IEVENT_CRL) |
09f75cd7 | 3359 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3360 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3361 | unsigned long flags; |
3362 | ||
59deab26 JP |
3363 | netif_dbg(priv, tx_err, dev, |
3364 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3365 | dev->stats.tx_dropped++; |
212079df | 3366 | atomic64_inc(&priv->extra_stats.tx_underrun); |
1da177e4 | 3367 | |
836cf7fa AV |
3368 | local_irq_save(flags); |
3369 | lock_tx_qs(priv); | |
3370 | ||
1da177e4 | 3371 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3372 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3373 | |
3374 | unlock_tx_qs(priv); | |
3375 | local_irq_restore(flags); | |
1da177e4 | 3376 | } |
59deab26 | 3377 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3378 | } |
3379 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3380 | dev->stats.rx_errors++; |
212079df | 3381 | atomic64_inc(&priv->extra_stats.rx_bsy); |
1da177e4 | 3382 | |
f4983704 | 3383 | gfar_receive(irq, grp_id); |
1da177e4 | 3384 | |
59deab26 JP |
3385 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3386 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3387 | } |
3388 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3389 | dev->stats.rx_errors++; |
212079df | 3390 | atomic64_inc(&priv->extra_stats.rx_babr); |
1da177e4 | 3391 | |
59deab26 | 3392 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3393 | } |
3394 | if (events & IEVENT_EBERR) { | |
212079df | 3395 | atomic64_inc(&priv->extra_stats.eberr); |
59deab26 | 3396 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3397 | } |
59deab26 JP |
3398 | if (events & IEVENT_RXC) |
3399 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3400 | |
3401 | if (events & IEVENT_BABT) { | |
212079df | 3402 | atomic64_inc(&priv->extra_stats.tx_babt); |
59deab26 | 3403 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3404 | } |
3405 | return IRQ_HANDLED; | |
3406 | } | |
3407 | ||
b31a1d8b AF |
3408 | static struct of_device_id gfar_match[] = |
3409 | { | |
3410 | { | |
3411 | .type = "network", | |
3412 | .compatible = "gianfar", | |
3413 | }, | |
46ceb60c SG |
3414 | { |
3415 | .compatible = "fsl,etsec2", | |
3416 | }, | |
b31a1d8b AF |
3417 | {}, |
3418 | }; | |
e72701ac | 3419 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3420 | |
1da177e4 | 3421 | /* Structure for a device driver */ |
74888760 | 3422 | static struct platform_driver gfar_driver = { |
4018294b GL |
3423 | .driver = { |
3424 | .name = "fsl-gianfar", | |
3425 | .owner = THIS_MODULE, | |
3426 | .pm = GFAR_PM_OPS, | |
3427 | .of_match_table = gfar_match, | |
3428 | }, | |
1da177e4 LT |
3429 | .probe = gfar_probe, |
3430 | .remove = gfar_remove, | |
3431 | }; | |
3432 | ||
db62f684 | 3433 | module_platform_driver(gfar_driver); |