projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gianfar: Fix on-the-fly vlan and mtu updates
[linux-block.git] / drivers / net / ethernet / freescale / gianfar.c
CommitLineData
0977f817 1/* drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 2 *
3 * Gianfar Ethernet Driver
7f7f5316
AF		 4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
20862788 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
a12f801d 13 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
0bbaf069 27 *
b31a1d8b
AF		 28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
0bbaf069 38 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
bb40dcbb 42 * of frames or amount of time have passed). In NAPI, the
1da177e4 43 * interrupt handler will signal there is work to be done, and
0aa1538f 44 * exit. This method will start at the last known empty
0bbaf069 45 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
59deab26
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
1da177e4 67#include <linux/kernel.h>
1da177e4
LT		 68#include <linux/string.h>
69#include <linux/errno.h>
bb40dcbb 70#include <linux/unistd.h>
1da177e4
LT		 71#include <linux/slab.h>
72#include <linux/interrupt.h>
1da177e4
LT		 73#include <linux/delay.h>
74#include <linux/netdevice.h>
75#include <linux/etherdevice.h>
76#include <linux/skbuff.h>
0bbaf069 77#include <linux/if_vlan.h>
1da177e4
LT		 78#include <linux/spinlock.h>
79#include <linux/mm.h>
5af50730
RH		 80#include <linux/of_address.h>
81#include <linux/of_irq.h>
fe192a49 82#include <linux/of_mdio.h>
b31a1d8b 83#include <linux/of_platform.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
cc772ab7 88#include <linux/net_tstamp.h>
1da177e4
LT		 89
90#include <asm/io.h>
7d350977 91#include <asm/reg.h>
2969b1f7 92#include <asm/mpc85xx.h>
1da177e4
LT		 93#include <asm/irq.h>
94#include <asm/uaccess.h>
95#include <linux/module.h>
1da177e4
LT		 96#include <linux/dma-mapping.h>
97#include <linux/crc32.h>
bb40dcbb
AF		 98#include <linux/mii.h>
99#include <linux/phy.h>
b31a1d8b
AF		 100#include <linux/phy_fixed.h>
101#include <linux/of.h>
4b6ba8aa 102#include <linux/of_net.h>
1da177e4
LT		 103
104#include "gianfar.h"
1da177e4
LT		 105
106#define TX_TIMEOUT (1*HZ)
1da177e4 107
7f7f5316 108const char gfar_driver_version[] = "1.3";
1da177e4 109
1da177e4
LT		 110static int gfar_enet_open(struct net_device *dev);
111static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 112static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 113static void gfar_timeout(struct net_device *dev);
114static int gfar_close(struct net_device *dev);
815b97c6 115struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 116static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
bc4598bc 117 struct sk_buff *skb);
1da177e4
LT		 118static int gfar_set_mac_address(struct net_device *dev);
119static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 120static irqreturn_t gfar_error(int irq, void *dev_id);
121static irqreturn_t gfar_transmit(int irq, void *dev_id);
122static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4 123static void adjust_link(struct net_device *dev);
1da177e4 124static int init_phy(struct net_device *dev);
74888760 125static int gfar_probe(struct platform_device *ofdev);
2dc11581 126static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 127static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 128static void gfar_set_multi(struct net_device *dev);
129static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 130static void gfar_configure_serdes(struct net_device *dev);
bea3348e 131static int gfar_poll(struct napi_struct *napi, int budget);
5eaedf31 132static int gfar_poll_sq(struct napi_struct *napi, int budget);
f2d71c2d
VW		 133#ifdef CONFIG_NET_POLL_CONTROLLER
134static void gfar_netpoll(struct net_device *dev);
135#endif
a12f801d 136int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
c233cf40 137static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
61db26c6
CM		 138static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
139 int amount_pull, struct napi_struct *napi);
c10650b6 140static void gfar_halt_nodisable(struct gfar_private *priv);
7f7f5316 141static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 142static void gfar_set_mac_for_addr(struct net_device *dev, int num,
143 const u8 *addr);
26ccfc37 144static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 145
1da177e4
LT		 146MODULE_AUTHOR("Freescale Semiconductor, Inc");
147MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148MODULE_LICENSE("GPL");
149
a12f801d 150static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 151 dma_addr_t buf)
152{
8a102fe0
AV		 153 u32 lstatus;
154
155 bdp->bufPtr = buf;
156
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 159 lstatus |= BD_LFLAG(RXBD_WRAP);
160
161 eieio();
162
163 bdp->lstatus = lstatus;
164}
165
8728327e 166static int gfar_init_bds(struct net_device *ndev)
826aa4a0 167{
8728327e 168 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 171 struct txbd8 *txbdp;
172 struct rxbd8 *rxbdp;
fba4ed03 173 int i, j;
a12f801d 174
fba4ed03
SG		 175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
183
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
187 txbdp->lstatus = 0;
188 txbdp->bufPtr = 0;
189 txbdp++;
190 }
8728327e 191
fba4ed03
SG		 192 /* Set the last descriptor in the ring to indicate wrap */
193 txbdp--;
194 txbdp->status |= TXBD_WRAP;
8728327e
AV		 195 }
196
fba4ed03
SG		 197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
8728327e 202
fba4ed03
SG		 203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 205
fba4ed03
SG		 206 if (skb) {
207 gfar_init_rxbdp(rx_queue, rxbdp,
208 rxbdp->bufPtr);
209 } else {
210 skb = gfar_new_skb(ndev);
211 if (!skb) {
59deab26 212 netdev_err(ndev, "Can't allocate RX buffers\n");
1eb8f7a7 213 return -ENOMEM;
fba4ed03
SG		 214 }
215 rx_queue->rx_skbuff[j] = skb;
216
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 218 }
8728327e 219
fba4ed03 220 rxbdp++;
8728327e
AV		 221 }
222
8728327e
AV		 223 }
224
225 return 0;
226}
227
228static int gfar_alloc_skb_resources(struct net_device *ndev)
229{
826aa4a0 230 void *vaddr;
fba4ed03
SG		 231 dma_addr_t addr;
232 int i, j, k;
826aa4a0 233 struct gfar_private *priv = netdev_priv(ndev);
369ec162 234 struct device *dev = priv->dev;
a12f801d
SG		 235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
237
fba4ed03
SG		 238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
241
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 245
246 /* Allocate memory for the buffer descriptors */
8728327e 247 vaddr = dma_alloc_coherent(dev,
d0320f75
JP		 248 (priv->total_tx_ring_size *
249 sizeof(struct txbd8)) +
250 (priv->total_rx_ring_size *
251 sizeof(struct rxbd8)),
252 &addr, GFP_KERNEL);
253 if (!vaddr)
826aa4a0 254 return -ENOMEM;
826aa4a0 255
fba4ed03
SG		 256 for (i = 0; i < priv->num_tx_queues; i++) {
257 tx_queue = priv->tx_queue[i];
43d620c8 258 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 259 tx_queue->tx_bd_dma_base = addr;
260 tx_queue->dev = ndev;
261 /* enet DMA only understands physical addresses */
bc4598bc
JC		 262 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
263 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
fba4ed03 264 }
826aa4a0 265
826aa4a0 266 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 267 for (i = 0; i < priv->num_rx_queues; i++) {
268 rx_queue = priv->rx_queue[i];
43d620c8 269 rx_queue->rx_bd_base = vaddr;
fba4ed03
SG		 270 rx_queue->rx_bd_dma_base = addr;
271 rx_queue->dev = ndev;
bc4598bc
JC		 272 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
273 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
fba4ed03 274 }
826aa4a0
AV		 275
276 /* Setup the skbuff rings */
fba4ed03
SG		 277 for (i = 0; i < priv->num_tx_queues; i++) {
278 tx_queue = priv->tx_queue[i];
14f8dc49
JP		 279 tx_queue->tx_skbuff =
280 kmalloc_array(tx_queue->tx_ring_size,
281 sizeof(*tx_queue->tx_skbuff),
282 GFP_KERNEL);
283 if (!tx_queue->tx_skbuff)
fba4ed03 284 goto cleanup;
826aa4a0 285
fba4ed03
SG		 286 for (k = 0; k < tx_queue->tx_ring_size; k++)
287 tx_queue->tx_skbuff[k] = NULL;
288 }
826aa4a0 289
fba4ed03
SG		 290 for (i = 0; i < priv->num_rx_queues; i++) {
291 rx_queue = priv->rx_queue[i];
14f8dc49
JP		 292 rx_queue->rx_skbuff =
293 kmalloc_array(rx_queue->rx_ring_size,
294 sizeof(*rx_queue->rx_skbuff),
295 GFP_KERNEL);
296 if (!rx_queue->rx_skbuff)
fba4ed03 297 goto cleanup;
fba4ed03
SG		 298
299 for (j = 0; j < rx_queue->rx_ring_size; j++)
300 rx_queue->rx_skbuff[j] = NULL;
301 }
826aa4a0 302
8728327e
AV		 303 if (gfar_init_bds(ndev))
304 goto cleanup;
826aa4a0
AV		 305
306 return 0;
307
308cleanup:
309 free_skb_resources(priv);
310 return -ENOMEM;
311}
312
fba4ed03
SG		 313static void gfar_init_tx_rx_base(struct gfar_private *priv)
314{
46ceb60c 315 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 316 u32 __iomem *baddr;
fba4ed03
SG		 317 int i;
318
319 baddr = &regs->tbase0;
bc4598bc 320 for (i = 0; i < priv->num_tx_queues; i++) {
fba4ed03 321 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
bc4598bc 322 baddr += 2;
fba4ed03
SG		 323 }
324
325 baddr = &regs->rbase0;
bc4598bc 326 for (i = 0; i < priv->num_rx_queues; i++) {
fba4ed03 327 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
bc4598bc 328 baddr += 2;
fba4ed03
SG		 329 }
330}
331
88302648 332static void gfar_rx_buff_size_config(struct gfar_private *priv)
826aa4a0 333{
88302648 334 int frame_size = priv->ndev->mtu + ETH_HLEN;
fba4ed03 335
ba779711
CM		 336 /* set this when rx hw offload (TOE) functions are being used */
337 priv->uses_rxfcb = 0;
338
88302648
CM		 339 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
340 priv->uses_rxfcb = 1;
341
342 if (priv->hwts_rx_en)
343 priv->uses_rxfcb = 1;
344
345 if (priv->uses_rxfcb)
346 frame_size += GMAC_FCB_LEN;
347
348 frame_size += priv->padding;
349
350 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
351 INCREMENTAL_BUFFER_SIZE;
352
353 priv->rx_buffer_size = frame_size;
354}
355
356static void gfar_mac_rx_config(struct gfar_private *priv)
357{
358 struct gfar __iomem *regs = priv->gfargrp[0].regs;
359 u32 rctrl = 0;
360
1ccb8389 361 if (priv->rx_filer_enable) {
fba4ed03 362 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 363 /* Program the RIR0 reg with the required distribution */
364 gfar_write(&regs->rir0, DEFAULT_RIR0);
365 }
826aa4a0 366
f5ae6279 367 /* Restore PROMISC mode */
a328ac92 368 if (priv->ndev->flags & IFF_PROMISC)
f5ae6279
CM		 369 rctrl |= RCTRL_PROM;
370
88302648 371 if (priv->ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 372 rctrl |= RCTRL_CHECKSUMMING;
373
88302648
CM		 374 if (priv->extended_hash)
375 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
826aa4a0
AV		 376
377 if (priv->padding) {
378 rctrl &= ~RCTRL_PAL_MASK;
379 rctrl |= RCTRL_PADDING(priv->padding);
380 }
381
97553f7f 382 /* Enable HW time stamping if requested from user space */
88302648 383 if (priv->hwts_rx_en)
97553f7f
MR		 384 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
385
88302648 386 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
b852b720 387 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
826aa4a0
AV		 388
389 /* Init rctrl based on our settings */
390 gfar_write(&regs->rctrl, rctrl);
a328ac92 391}
826aa4a0 392
a328ac92
CM		 393static void gfar_mac_tx_config(struct gfar_private *priv)
394{
395 struct gfar __iomem *regs = priv->gfargrp[0].regs;
396 u32 tctrl = 0;
397
398 if (priv->ndev->features & NETIF_F_IP_CSUM)
826aa4a0
AV		 399 tctrl |= TCTRL_INIT_CSUM;
400
b98b8bab
CM		 401 if (priv->prio_sched_en)
402 tctrl |= TCTRL_TXSCHED_PRIO;
403 else {
404 tctrl |= TCTRL_TXSCHED_WRRS;
405 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
406 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
407 }
fba4ed03 408
88302648
CM		 409 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
410 tctrl |= TCTRL_VLINS;
411
826aa4a0 412 gfar_write(&regs->tctrl, tctrl);
826aa4a0
AV		 413}
414
a7f38041
SG		 415static struct net_device_stats *gfar_get_stats(struct net_device *dev)
416{
417 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 418 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
419 unsigned long tx_packets = 0, tx_bytes = 0;
3a2e16c8 420 int i;
a7f38041
SG		 421
422 for (i = 0; i < priv->num_rx_queues; i++) {
423 rx_packets += priv->rx_queue[i]->stats.rx_packets;
bc4598bc 424 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
a7f38041
SG		 425 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
426 }
427
428 dev->stats.rx_packets = rx_packets;
bc4598bc 429 dev->stats.rx_bytes = rx_bytes;
a7f38041
SG		 430 dev->stats.rx_dropped = rx_dropped;
431
432 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 433 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
434 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 435 }
436
bc4598bc 437 dev->stats.tx_bytes = tx_bytes;
a7f38041
SG		 438 dev->stats.tx_packets = tx_packets;
439
440 return &dev->stats;
441}
442
26ccfc37
AF		 443static const struct net_device_ops gfar_netdev_ops = {
444 .ndo_open = gfar_enet_open,
445 .ndo_start_xmit = gfar_start_xmit,
446 .ndo_stop = gfar_close,
447 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 448 .ndo_set_features = gfar_set_features,
afc4b13d 449 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 450 .ndo_tx_timeout = gfar_timeout,
451 .ndo_do_ioctl = gfar_ioctl,
a7f38041 452 .ndo_get_stats = gfar_get_stats,
240c102d
BH		 453 .ndo_set_mac_address = eth_mac_addr,
454 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 455#ifdef CONFIG_NET_POLL_CONTROLLER
456 .ndo_poll_controller = gfar_netpoll,
457#endif
458};
459
efeddce7
CM		 460static void gfar_ints_disable(struct gfar_private *priv)
461{
462 int i;
463 for (i = 0; i < priv->num_grps; i++) {
464 struct gfar __iomem *regs = priv->gfargrp[i].regs;
465 /* Clear IEVENT */
466 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
467
468 /* Initialize IMASK */
469 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
470 }
471}
472
473static void gfar_ints_enable(struct gfar_private *priv)
474{
475 int i;
476 for (i = 0; i < priv->num_grps; i++) {
477 struct gfar __iomem *regs = priv->gfargrp[i].regs;
478 /* Unmask the interrupts we look for */
479 gfar_write(&regs->imask, IMASK_DEFAULT);
480 }
481}
482
fba4ed03
SG		 483void lock_rx_qs(struct gfar_private *priv)
484{
3a2e16c8 485 int i;
fba4ed03
SG		 486
487 for (i = 0; i < priv->num_rx_queues; i++)
488 spin_lock(&priv->rx_queue[i]->rxlock);
489}
490
491void lock_tx_qs(struct gfar_private *priv)
492{
3a2e16c8 493 int i;
fba4ed03
SG		 494
495 for (i = 0; i < priv->num_tx_queues; i++)
496 spin_lock(&priv->tx_queue[i]->txlock);
497}
498
499void unlock_rx_qs(struct gfar_private *priv)
500{
3a2e16c8 501 int i;
fba4ed03
SG		 502
503 for (i = 0; i < priv->num_rx_queues; i++)
504 spin_unlock(&priv->rx_queue[i]->rxlock);
505}
506
507void unlock_tx_qs(struct gfar_private *priv)
508{
3a2e16c8 509 int i;
fba4ed03
SG		 510
511 for (i = 0; i < priv->num_tx_queues; i++)
512 spin_unlock(&priv->tx_queue[i]->txlock);
513}
514
20862788
CM		 515static int gfar_alloc_tx_queues(struct gfar_private *priv)
516{
517 int i;
518
519 for (i = 0; i < priv->num_tx_queues; i++) {
520 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
521 GFP_KERNEL);
522 if (!priv->tx_queue[i])
523 return -ENOMEM;
524
525 priv->tx_queue[i]->tx_skbuff = NULL;
526 priv->tx_queue[i]->qindex = i;
527 priv->tx_queue[i]->dev = priv->ndev;
528 spin_lock_init(&(priv->tx_queue[i]->txlock));
529 }
530 return 0;
531}
532
533static int gfar_alloc_rx_queues(struct gfar_private *priv)
534{
535 int i;
536
537 for (i = 0; i < priv->num_rx_queues; i++) {
538 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
539 GFP_KERNEL);
540 if (!priv->rx_queue[i])
541 return -ENOMEM;
542
543 priv->rx_queue[i]->rx_skbuff = NULL;
544 priv->rx_queue[i]->qindex = i;
545 priv->rx_queue[i]->dev = priv->ndev;
546 spin_lock_init(&(priv->rx_queue[i]->rxlock));
547 }
548 return 0;
549}
550
551static void gfar_free_tx_queues(struct gfar_private *priv)
fba4ed03 552{
3a2e16c8 553 int i;
fba4ed03
SG		 554
555 for (i = 0; i < priv->num_tx_queues; i++)
556 kfree(priv->tx_queue[i]);
557}
558
20862788 559static void gfar_free_rx_queues(struct gfar_private *priv)
fba4ed03 560{
3a2e16c8 561 int i;
fba4ed03
SG		 562
563 for (i = 0; i < priv->num_rx_queues; i++)
564 kfree(priv->rx_queue[i]);
565}
566
46ceb60c
SG		 567static void unmap_group_regs(struct gfar_private *priv)
568{
3a2e16c8 569 int i;
46ceb60c
SG		 570
571 for (i = 0; i < MAXGROUPS; i++)
572 if (priv->gfargrp[i].regs)
573 iounmap(priv->gfargrp[i].regs);
574}
575
ee873fda
CM		 576static void free_gfar_dev(struct gfar_private *priv)
577{
578 int i, j;
579
580 for (i = 0; i < priv->num_grps; i++)
581 for (j = 0; j < GFAR_NUM_IRQS; j++) {
582 kfree(priv->gfargrp[i].irqinfo[j]);
583 priv->gfargrp[i].irqinfo[j] = NULL;
584 }
585
586 free_netdev(priv->ndev);
587}
588
46ceb60c
SG		 589static void disable_napi(struct gfar_private *priv)
590{
3a2e16c8 591 int i;
46ceb60c
SG		 592
593 for (i = 0; i < priv->num_grps; i++)
594 napi_disable(&priv->gfargrp[i].napi);
595}
596
597static void enable_napi(struct gfar_private *priv)
598{
3a2e16c8 599 int i;
46ceb60c
SG		 600
601 for (i = 0; i < priv->num_grps; i++)
602 napi_enable(&priv->gfargrp[i].napi);
603}
604
605static int gfar_parse_group(struct device_node *np,
bc4598bc 606 struct gfar_private *priv, const char *model)
46ceb60c 607{
5fedcc14 608 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
46ceb60c 609 u32 *queue_mask;
ee873fda
CM		 610 int i;
611
7c1e7e99
PG		 612 for (i = 0; i < GFAR_NUM_IRQS; i++) {
613 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
614 GFP_KERNEL);
615 if (!grp->irqinfo[i])
ee873fda 616 return -ENOMEM;
ee873fda 617 }
46ceb60c 618
5fedcc14
CM		 619 grp->regs = of_iomap(np, 0);
620 if (!grp->regs)
46ceb60c
SG		 621 return -ENOMEM;
622
ee873fda 623 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
46ceb60c
SG		 624
625 /* If we aren't the FEC we have multiple interrupts */
626 if (model && strcasecmp(model, "FEC")) {
ee873fda
CM		 627 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
628 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
629 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
630 gfar_irq(grp, RX)->irq == NO_IRQ ||
631 gfar_irq(grp, ER)->irq == NO_IRQ)
46ceb60c 632 return -EINVAL;
46ceb60c
SG		 633 }
634
5fedcc14
CM		 635 grp->priv = priv;
636 spin_lock_init(&grp->grplock);
bc4598bc
JC		 637 if (priv->mode == MQ_MG_MODE) {
638 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
5fedcc14 639 grp->rx_bit_map = queue_mask ?
bc4598bc
JC		 640 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
641 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
5fedcc14 642 grp->tx_bit_map = queue_mask ?
bc4598bc 643 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
46ceb60c 644 } else {
5fedcc14
CM		 645 grp->rx_bit_map = 0xFF;
646 grp->tx_bit_map = 0xFF;
46ceb60c 647 }
20862788
CM		 648
649 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
650 * right to left, so we need to revert the 8 bits to get the q index
651 */
652 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
653 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
654
655 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
656 * also assign queues to groups
657 */
658 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
659 grp->num_rx_queues++;
660 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
661 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
662 priv->rx_queue[i]->grp = grp;
663 }
664
665 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
666 grp->num_tx_queues++;
667 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
668 priv->tqueue |= (TQUEUE_EN0 >> i);
669 priv->tx_queue[i]->grp = grp;
670 }
671
46ceb60c
SG		 672 priv->num_grps++;
673
674 return 0;
675}
676
2dc11581 677static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 678{
b31a1d8b
AF		 679 const char *model;
680 const char *ctype;
681 const void *mac_addr;
fba4ed03
SG		 682 int err = 0, i;
683 struct net_device *dev = NULL;
684 struct gfar_private *priv = NULL;
61c7a080 685 struct device_node *np = ofdev->dev.of_node;
46ceb60c 686 struct device_node *child = NULL;
4d7902f2
AF		 687 const u32 *stash;
688 const u32 *stash_len;
689 const u32 *stash_idx;
fba4ed03
SG		 690 unsigned int num_tx_qs, num_rx_qs;
691 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 692
693 if (!np || !of_device_is_available(np))
694 return -ENODEV;
695
fba4ed03
SG		 696 /* parse the num of tx and rx queues */
697 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
698 num_tx_qs = tx_queues ? *tx_queues : 1;
699
700 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 701 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
702 num_tx_qs, MAX_TX_QS);
703 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 704 return -EINVAL;
705 }
706
707 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
708 num_rx_qs = rx_queues ? *rx_queues : 1;
709
710 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 711 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
712 num_rx_qs, MAX_RX_QS);
713 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 714 return -EINVAL;
715 }
716
717 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
718 dev = *pdev;
719 if (NULL == dev)
720 return -ENOMEM;
721
722 priv = netdev_priv(dev);
fba4ed03
SG		 723 priv->ndev = dev;
724
fba4ed03 725 priv->num_tx_queues = num_tx_qs;
fe069123 726 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 727 priv->num_rx_queues = num_rx_qs;
20862788
CM		 728
729 err = gfar_alloc_tx_queues(priv);
730 if (err)
731 goto tx_alloc_failed;
732
733 err = gfar_alloc_rx_queues(priv);
734 if (err)
735 goto rx_alloc_failed;
b31a1d8b 736
0977f817 737 /* Init Rx queue filer rule set linked list */
4aa3a715
SP		 738 INIT_LIST_HEAD(&priv->rx_list.list);
739 priv->rx_list.count = 0;
740 mutex_init(&priv->rx_queue_access);
741
b31a1d8b
AF		 742 model = of_get_property(np, "model", NULL);
743
46ceb60c
SG		 744 for (i = 0; i < MAXGROUPS; i++)
745 priv->gfargrp[i].regs = NULL;
b31a1d8b 746
46ceb60c
SG		 747 /* Parse and initialize group specific information */
748 if (of_device_is_compatible(np, "fsl,etsec2")) {
749 priv->mode = MQ_MG_MODE;
750 for_each_child_of_node(np, child) {
751 err = gfar_parse_group(child, priv, model);
752 if (err)
753 goto err_grp_init;
b31a1d8b 754 }
46ceb60c
SG		 755 } else {
756 priv->mode = SQ_SG_MODE;
757 err = gfar_parse_group(np, priv, model);
bc4598bc 758 if (err)
46ceb60c 759 goto err_grp_init;
b31a1d8b
AF		 760 }
761
4d7902f2
AF		 762 stash = of_get_property(np, "bd-stash", NULL);
763
a12f801d 764 if (stash) {
4d7902f2
AF		 765 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
766 priv->bd_stash_en = 1;
767 }
768
769 stash_len = of_get_property(np, "rx-stash-len", NULL);
770
771 if (stash_len)
772 priv->rx_stash_size = *stash_len;
773
774 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
775
776 if (stash_idx)
777 priv->rx_stash_index = *stash_idx;
778
779 if (stash_len || stash_idx)
780 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
781
b31a1d8b 782 mac_addr = of_get_mac_address(np);
bc4598bc 783
b31a1d8b 784 if (mac_addr)
6a3c910c 785 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 786
787 if (model && !strcasecmp(model, "TSEC"))
34018fd4 788 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 789 FSL_GIANFAR_DEV_HAS_COALESCE |
790 FSL_GIANFAR_DEV_HAS_RMON |
791 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
792
b31a1d8b 793 if (model && !strcasecmp(model, "eTSEC"))
34018fd4 794 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 795 FSL_GIANFAR_DEV_HAS_COALESCE |
796 FSL_GIANFAR_DEV_HAS_RMON |
797 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
bc4598bc
JC		 798 FSL_GIANFAR_DEV_HAS_CSUM |
799 FSL_GIANFAR_DEV_HAS_VLAN |
800 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
801 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
802 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 803
804 ctype = of_get_property(np, "phy-connection-type", NULL);
805
806 /* We only care about rgmii-id. The rest are autodetected */
807 if (ctype && !strcmp(ctype, "rgmii-id"))
808 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
809 else
810 priv->interface = PHY_INTERFACE_MODE_MII;
811
812 if (of_get_property(np, "fsl,magic-packet", NULL))
813 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
814
fe192a49 815 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 816
817 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 818 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 819
820 return 0;
821
46ceb60c
SG		 822err_grp_init:
823 unmap_group_regs(priv);
20862788
CM		 824rx_alloc_failed:
825 gfar_free_rx_queues(priv);
826tx_alloc_failed:
827 gfar_free_tx_queues(priv);
ee873fda 828 free_gfar_dev(priv);
b31a1d8b
AF		 829 return err;
830}
831
ca0c88c2 832static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
cc772ab7
MR		 833{
834 struct hwtstamp_config config;
835 struct gfar_private *priv = netdev_priv(netdev);
836
837 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
838 return -EFAULT;
839
840 /* reserved for future extensions */
841 if (config.flags)
842 return -EINVAL;
843
f0ee7acf
MR		 844 switch (config.tx_type) {
845 case HWTSTAMP_TX_OFF:
846 priv->hwts_tx_en = 0;
847 break;
848 case HWTSTAMP_TX_ON:
849 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
850 return -ERANGE;
851 priv->hwts_tx_en = 1;
852 break;
853 default:
cc772ab7 854 return -ERANGE;
f0ee7acf 855 }
cc772ab7
MR		 856
857 switch (config.rx_filter) {
858 case HWTSTAMP_FILTER_NONE:
97553f7f
MR		 859 if (priv->hwts_rx_en) {
860 stop_gfar(netdev);
861 priv->hwts_rx_en = 0;
862 startup_gfar(netdev);
863 }
cc772ab7
MR		 864 break;
865 default:
866 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
867 return -ERANGE;
97553f7f
MR		 868 if (!priv->hwts_rx_en) {
869 stop_gfar(netdev);
870 priv->hwts_rx_en = 1;
871 startup_gfar(netdev);
872 }
cc772ab7
MR		 873 config.rx_filter = HWTSTAMP_FILTER_ALL;
874 break;
875 }
876
877 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
878 -EFAULT : 0;
879}
880
ca0c88c2
BH		 881static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
882{
883 struct hwtstamp_config config;
884 struct gfar_private *priv = netdev_priv(netdev);
885
886 config.flags = 0;
887 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
888 config.rx_filter = (priv->hwts_rx_en ?
889 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
890
891 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
892 -EFAULT : 0;
893}
894
0faac9f7
CW		 895static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
896{
897 struct gfar_private *priv = netdev_priv(dev);
898
899 if (!netif_running(dev))
900 return -EINVAL;
901
cc772ab7 902 if (cmd == SIOCSHWTSTAMP)
ca0c88c2
BH		 903 return gfar_hwtstamp_set(dev, rq);
904 if (cmd == SIOCGHWTSTAMP)
905 return gfar_hwtstamp_get(dev, rq);
cc772ab7 906
0faac9f7
CW		 907 if (!priv->phydev)
908 return -ENODEV;
909
28b04113 910 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 911}
912
18294ad1
AV		 913static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
914 u32 class)
7a8b3372
SG		 915{
916 u32 rqfpr = FPR_FILER_MASK;
917 u32 rqfcr = 0x0;
918
919 rqfar--;
920 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 921 priv->ftp_rqfpr[rqfar] = rqfpr;
922 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 923 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
924
925 rqfar--;
926 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 927 priv->ftp_rqfpr[rqfar] = rqfpr;
928 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 929 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
930
931 rqfar--;
932 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
933 rqfpr = class;
6c43e046
WJB		 934 priv->ftp_rqfcr[rqfar] = rqfcr;
935 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 936 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
937
938 rqfar--;
939 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
940 rqfpr = class;
6c43e046
WJB		 941 priv->ftp_rqfcr[rqfar] = rqfcr;
942 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 943 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
944
945 return rqfar;
946}
947
948static void gfar_init_filer_table(struct gfar_private *priv)
949{
950 int i = 0x0;
951 u32 rqfar = MAX_FILER_IDX;
952 u32 rqfcr = 0x0;
953 u32 rqfpr = FPR_FILER_MASK;
954
955 /* Default rule */
956 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 957 priv->ftp_rqfcr[rqfar] = rqfcr;
958 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 959 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
960
961 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
962 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
963 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
964 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
965 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
966 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
967
85dd08eb 968 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 969 priv->cur_filer_idx = rqfar;
970
971 /* Rest are masked rules */
972 rqfcr = RQFCR_CMP_NOMATCH;
973 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 974 priv->ftp_rqfcr[i] = rqfcr;
975 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 976 gfar_write_filer(priv, i, rqfcr, rqfpr);
977 }
978}
979
2969b1f7 980static void __gfar_detect_errata_83xx(struct gfar_private *priv)
7d350977 981{
7d350977
AV		 982 unsigned int pvr = mfspr(SPRN_PVR);
983 unsigned int svr = mfspr(SPRN_SVR);
984 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
985 unsigned int rev = svr & 0xffff;
986
987 /* MPC8313 Rev 2.0 and higher; All MPC837x */
988 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
bc4598bc 989 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
7d350977
AV		 990 priv->errata |= GFAR_ERRATA_74;
991
deb90eac
AV		 992 /* MPC8313 and MPC837x all rev */
993 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 994 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
deb90eac
AV		 995 priv->errata |= GFAR_ERRATA_76;
996
2969b1f7
CM		 997 /* MPC8313 Rev < 2.0 */
998 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
999 priv->errata |= GFAR_ERRATA_12;
1000}
1001
1002static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1003{
1004 unsigned int svr = mfspr(SPRN_SVR);
1005
1006 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
4363c2fd 1007 priv->errata |= GFAR_ERRATA_12;
53fad773
CM		 1008 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1009 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1010 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
2969b1f7
CM		 1011}
1012
1013static void gfar_detect_errata(struct gfar_private *priv)
1014{
1015 struct device *dev = &priv->ofdev->dev;
1016
1017 /* no plans to fix */
1018 priv->errata |= GFAR_ERRATA_A002;
1019
1020 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1021 __gfar_detect_errata_85xx(priv);
1022 else /* non-mpc85xx parts, i.e. e300 core based */
1023 __gfar_detect_errata_83xx(priv);
4363c2fd 1024
7d350977
AV		 1025 if (priv->errata)
1026 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1027 priv->errata);
1028}
1029
a328ac92 1030static void gfar_mac_reset(struct gfar_private *priv)
20862788
CM		 1031{
1032 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a328ac92 1033 u32 tempval;
20862788
CM		 1034
1035 /* Reset MAC layer */
1036 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1037
1038 /* We need to delay at least 3 TX clocks */
a328ac92 1039 udelay(3);
20862788
CM		 1040
1041 /* the soft reset bit is not self-resetting, so we need to
1042 * clear it before resuming normal operation
1043 */
1044 gfar_write(&regs->maccfg1, 0);
1045
a328ac92
CM		 1046 udelay(3);
1047
88302648
CM		 1048 /* Compute rx_buff_size based on config flags */
1049 gfar_rx_buff_size_config(priv);
1050
1051 /* Initialize the max receive frame/buffer lengths */
1052 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
a328ac92
CM		 1053 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1054
1055 /* Initialize the Minimum Frame Length Register */
1056 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1057
20862788
CM		 1058 /* Initialize MACCFG2. */
1059 tempval = MACCFG2_INIT_SETTINGS;
88302648
CM		 1060
1061 /* If the mtu is larger than the max size for standard
1062 * ethernet frames (ie, a jumbo frame), then set maccfg2
1063 * to allow huge frames, and to check the length
1064 */
1065 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1066 gfar_has_errata(priv, GFAR_ERRATA_74))
20862788 1067 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
88302648 1068
20862788
CM		 1069 gfar_write(&regs->maccfg2, tempval);
1070
a328ac92
CM		 1071 /* Clear mac addr hash registers */
1072 gfar_write(&regs->igaddr0, 0);
1073 gfar_write(&regs->igaddr1, 0);
1074 gfar_write(&regs->igaddr2, 0);
1075 gfar_write(&regs->igaddr3, 0);
1076 gfar_write(&regs->igaddr4, 0);
1077 gfar_write(&regs->igaddr5, 0);
1078 gfar_write(&regs->igaddr6, 0);
1079 gfar_write(&regs->igaddr7, 0);
1080
1081 gfar_write(&regs->gaddr0, 0);
1082 gfar_write(&regs->gaddr1, 0);
1083 gfar_write(&regs->gaddr2, 0);
1084 gfar_write(&regs->gaddr3, 0);
1085 gfar_write(&regs->gaddr4, 0);
1086 gfar_write(&regs->gaddr5, 0);
1087 gfar_write(&regs->gaddr6, 0);
1088 gfar_write(&regs->gaddr7, 0);
1089
1090 if (priv->extended_hash)
1091 gfar_clear_exact_match(priv->ndev);
1092
1093 gfar_mac_rx_config(priv);
1094
1095 gfar_mac_tx_config(priv);
1096
1097 gfar_set_mac_address(priv->ndev);
1098
1099 gfar_set_multi(priv->ndev);
1100
1101 /* clear ievent and imask before configuring coalescing */
1102 gfar_ints_disable(priv);
1103
1104 /* Configure the coalescing support */
1105 gfar_configure_coalescing_all(priv);
1106}
1107
1108static void gfar_hw_init(struct gfar_private *priv)
1109{
1110 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1111 u32 attrs;
1112
1113 /* Stop the DMA engine now, in case it was running before
1114 * (The firmware could have used it, and left it running).
1115 */
1116 gfar_halt(priv);
1117
1118 gfar_mac_reset(priv);
1119
1120 /* Zero out the rmon mib registers if it has them */
1121 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1122 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1123
1124 /* Mask off the CAM interrupts */
1125 gfar_write(&regs->rmon.cam1, 0xffffffff);
1126 gfar_write(&regs->rmon.cam2, 0xffffffff);
1127 }
1128
20862788
CM		 1129 /* Initialize ECNTRL */
1130 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1131
34018fd4
CM		 1132 /* Set the extraction length and index */
1133 attrs = ATTRELI_EL(priv->rx_stash_size) |
1134 ATTRELI_EI(priv->rx_stash_index);
1135
1136 gfar_write(&regs->attreli, attrs);
1137
1138 /* Start with defaults, and add stashing
1139 * depending on driver parameters
1140 */
1141 attrs = ATTR_INIT_SETTINGS;
1142
1143 if (priv->bd_stash_en)
1144 attrs |= ATTR_BDSTASH;
1145
1146 if (priv->rx_stash_size != 0)
1147 attrs |= ATTR_BUFSTASH;
1148
1149 gfar_write(&regs->attr, attrs);
1150
1151 /* FIFO configs */
1152 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1153 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1154 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1155
20862788
CM		 1156 /* Program the interrupt steering regs, only for MG devices */
1157 if (priv->num_grps > 1)
1158 gfar_write_isrg(priv);
20862788
CM		 1159}
1160
1161static void __init gfar_init_addr_hash_table(struct gfar_private *priv)
1162{
1163 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1164
1165 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1166 priv->extended_hash = 1;
1167 priv->hash_width = 9;
1168
1169 priv->hash_regs[0] = &regs->igaddr0;
1170 priv->hash_regs[1] = &regs->igaddr1;
1171 priv->hash_regs[2] = &regs->igaddr2;
1172 priv->hash_regs[3] = &regs->igaddr3;
1173 priv->hash_regs[4] = &regs->igaddr4;
1174 priv->hash_regs[5] = &regs->igaddr5;
1175 priv->hash_regs[6] = &regs->igaddr6;
1176 priv->hash_regs[7] = &regs->igaddr7;
1177 priv->hash_regs[8] = &regs->gaddr0;
1178 priv->hash_regs[9] = &regs->gaddr1;
1179 priv->hash_regs[10] = &regs->gaddr2;
1180 priv->hash_regs[11] = &regs->gaddr3;
1181 priv->hash_regs[12] = &regs->gaddr4;
1182 priv->hash_regs[13] = &regs->gaddr5;
1183 priv->hash_regs[14] = &regs->gaddr6;
1184 priv->hash_regs[15] = &regs->gaddr7;
1185
1186 } else {
1187 priv->extended_hash = 0;
1188 priv->hash_width = 8;
1189
1190 priv->hash_regs[0] = &regs->gaddr0;
1191 priv->hash_regs[1] = &regs->gaddr1;
1192 priv->hash_regs[2] = &regs->gaddr2;
1193 priv->hash_regs[3] = &regs->gaddr3;
1194 priv->hash_regs[4] = &regs->gaddr4;
1195 priv->hash_regs[5] = &regs->gaddr5;
1196 priv->hash_regs[6] = &regs->gaddr6;
1197 priv->hash_regs[7] = &regs->gaddr7;
1198 }
1199}
1200
bb40dcbb 1201/* Set up the ethernet device structure, private data,
0977f817
JC		 1202 * and anything else we need before we start
1203 */
74888760 1204static int gfar_probe(struct platform_device *ofdev)
1da177e4 1205{
1da177e4
LT		 1206 struct net_device *dev = NULL;
1207 struct gfar_private *priv = NULL;
20862788 1208 int err = 0, i;
1da177e4 1209
fba4ed03 1210 err = gfar_of_init(ofdev, &dev);
1da177e4 1211
fba4ed03
SG		 1212 if (err)
1213 return err;
1da177e4
LT		 1214
1215 priv = netdev_priv(dev);
4826857f
KG		 1216 priv->ndev = dev;
1217 priv->ofdev = ofdev;
369ec162 1218 priv->dev = &ofdev->dev;
4826857f 1219 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 1220
d87eb127 1221 spin_lock_init(&priv->bflock);
ab939905 1222 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 1223
8513fbd8 1224 platform_set_drvdata(ofdev, priv);
1da177e4 1225
7d350977
AV		 1226 gfar_detect_errata(priv);
1227
1da177e4 1228 /* Set the dev->base_addr to the gfar reg region */
20862788 1229 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1da177e4 1230
1da177e4 1231 /* Fill in the dev structure */
1da177e4 1232 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1233 dev->mtu = 1500;
26ccfc37 1234 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1235 dev->ethtool_ops = &gfar_ethtool_ops;
1236
fba4ed03 1237 /* Register for napi ...We are registering NAPI for each grp */
5eaedf31
CM		 1238 if (priv->mode == SQ_SG_MODE)
1239 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
bc4598bc 1240 GFAR_DEV_WEIGHT);
5eaedf31
CM		 1241 else
1242 for (i = 0; i < priv->num_grps; i++)
1243 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1244 GFAR_DEV_WEIGHT);
a12f801d 1245
b31a1d8b 1246 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95 1247 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1248 NETIF_F_RXCSUM;
8b3afe95 1249 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1250 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
8b3afe95 1251 }
0bbaf069 1252
87c288c6 1253 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
f646968f
PM		 1254 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1255 NETIF_F_HW_VLAN_CTAG_RX;
1256 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
87c288c6 1257 }
0bbaf069 1258
20862788 1259 gfar_init_addr_hash_table(priv);
0bbaf069 1260
532c37bc
CM		 1261 /* Insert receive time stamps into padding alignment bytes */
1262 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1263 priv->padding = 8;
0bbaf069 1264
cc772ab7 1265 if (dev->features & NETIF_F_IP_CSUM ||
bc4598bc 1266 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1267 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4
LT		 1268
1269 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1270
a12f801d 1271 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1272 for (i = 0; i < priv->num_tx_queues; i++) {
1273 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1274 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1275 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1276 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1277 }
a12f801d 1278
fba4ed03
SG		 1279 for (i = 0; i < priv->num_rx_queues; i++) {
1280 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1281 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1282 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1283 }
1da177e4 1284
0977f817 1285 /* always enable rx filer */
4aa3a715 1286 priv->rx_filer_enable = 1;
0bbaf069
KG		 1287 /* Enable most messages by default */
1288 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
b98b8bab
CM		 1289 /* use pritority h/w tx queue scheduling for single queue devices */
1290 if (priv->num_tx_queues == 1)
1291 priv->prio_sched_en = 1;
0bbaf069 1292
a328ac92 1293 gfar_hw_init(priv);
d3eab82b 1294
1da177e4
LT		 1295 err = register_netdev(dev);
1296
1297 if (err) {
59deab26 1298 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1299 goto register_fail;
1300 }
1301
a328ac92
CM		 1302 /* Carrier starts down, phylib will bring it up */
1303 netif_carrier_off(dev);
1304
2884e5cc 1305 device_init_wakeup(&dev->dev,
bc4598bc
JC		 1306 priv->device_flags &
1307 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
2884e5cc 1308
c50a5d9a 1309 /* fill out IRQ number and name fields */
46ceb60c 1310 for (i = 0; i < priv->num_grps; i++) {
ee873fda 1311 struct gfar_priv_grp *grp = &priv->gfargrp[i];
46ceb60c 1312 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
ee873fda 1313 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
0015e551 1314 dev->name, "_g", '0' + i, "_tx");
ee873fda 1315 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
0015e551 1316 dev->name, "_g", '0' + i, "_rx");
ee873fda 1317 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
0015e551 1318 dev->name, "_g", '0' + i, "_er");
46ceb60c 1319 } else
ee873fda 1320 strcpy(gfar_irq(grp, TX)->name, dev->name);
46ceb60c 1321 }
c50a5d9a 1322
7a8b3372
SG		 1323 /* Initialize the filer table */
1324 gfar_init_filer_table(priv);
1325
1da177e4 1326 /* Print out the device info */
59deab26 1327 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4 1328
0977f817
JC		 1329 /* Even more device info helps when determining which kernel
1330 * provided which set of benchmarks.
1331 */
59deab26 1332 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1333 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1334 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1335 i, priv->rx_queue[i]->rx_ring_size);
bc4598bc 1336 for (i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1337 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1338 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1339
1340 return 0;
1341
1342register_fail:
46ceb60c 1343 unmap_group_regs(priv);
20862788
CM		 1344 gfar_free_rx_queues(priv);
1345 gfar_free_tx_queues(priv);
fe192a49
GL		 1346 if (priv->phy_node)
1347 of_node_put(priv->phy_node);
1348 if (priv->tbi_node)
1349 of_node_put(priv->tbi_node);
ee873fda 1350 free_gfar_dev(priv);
bb40dcbb 1351 return err;
1da177e4
LT		 1352}
1353
2dc11581 1354static int gfar_remove(struct platform_device *ofdev)
1da177e4 1355{
8513fbd8 1356 struct gfar_private *priv = platform_get_drvdata(ofdev);
1da177e4 1357
fe192a49
GL		 1358 if (priv->phy_node)
1359 of_node_put(priv->phy_node);
1360 if (priv->tbi_node)
1361 of_node_put(priv->tbi_node);
1362
d9d8e041 1363 unregister_netdev(priv->ndev);
46ceb60c 1364 unmap_group_regs(priv);
20862788
CM		 1365 gfar_free_rx_queues(priv);
1366 gfar_free_tx_queues(priv);
ee873fda 1367 free_gfar_dev(priv);
1da177e4
LT		 1368
1369 return 0;
1370}
1371
d87eb127 1372#ifdef CONFIG_PM
be926fc4
AV		 1373
1374static int gfar_suspend(struct device *dev)
d87eb127 1375{
be926fc4
AV		 1376 struct gfar_private *priv = dev_get_drvdata(dev);
1377 struct net_device *ndev = priv->ndev;
46ceb60c 1378 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1379 unsigned long flags;
1380 u32 tempval;
1381
1382 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1383 (priv->device_flags &
1384 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1385
be926fc4 1386 netif_device_detach(ndev);
d87eb127 1387
be926fc4 1388 if (netif_running(ndev)) {
fba4ed03
SG		 1389
1390 local_irq_save(flags);
1391 lock_tx_qs(priv);
1392 lock_rx_qs(priv);
d87eb127 1393
c10650b6 1394 gfar_halt_nodisable(priv);
d87eb127
SW		 1395
1396 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1397 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1398
1399 tempval &= ~MACCFG1_TX_EN;
1400
1401 if (!magic_packet)
1402 tempval &= ~MACCFG1_RX_EN;
1403
f4983704 1404 gfar_write(&regs->maccfg1, tempval);
d87eb127 1405
fba4ed03
SG		 1406 unlock_rx_qs(priv);
1407 unlock_tx_qs(priv);
1408 local_irq_restore(flags);
d87eb127 1409
46ceb60c 1410 disable_napi(priv);
d87eb127
SW		 1411
1412 if (magic_packet) {
1413 /* Enable interrupt on Magic Packet */
f4983704 1414 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1415
1416 /* Enable Magic Packet mode */
f4983704 1417 tempval = gfar_read(&regs->maccfg2);
d87eb127 1418 tempval |= MACCFG2_MPEN;
f4983704 1419 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1420 } else {
1421 phy_stop(priv->phydev);
1422 }
1423 }
1424
1425 return 0;
1426}
1427
be926fc4 1428static int gfar_resume(struct device *dev)
d87eb127 1429{
be926fc4
AV		 1430 struct gfar_private *priv = dev_get_drvdata(dev);
1431 struct net_device *ndev = priv->ndev;
46ceb60c 1432 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1433 unsigned long flags;
1434 u32 tempval;
1435 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1436 (priv->device_flags &
1437 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1438
be926fc4
AV		 1439 if (!netif_running(ndev)) {
1440 netif_device_attach(ndev);
d87eb127
SW		 1441 return 0;
1442 }
1443
1444 if (!magic_packet && priv->phydev)
1445 phy_start(priv->phydev);
1446
1447 /* Disable Magic Packet mode, in case something
1448 * else woke us up.
1449 */
fba4ed03
SG		 1450 local_irq_save(flags);
1451 lock_tx_qs(priv);
1452 lock_rx_qs(priv);
d87eb127 1453
f4983704 1454 tempval = gfar_read(&regs->maccfg2);
d87eb127 1455 tempval &= ~MACCFG2_MPEN;
f4983704 1456 gfar_write(&regs->maccfg2, tempval);
d87eb127 1457
c10650b6 1458 gfar_start(priv);
d87eb127 1459
fba4ed03
SG		 1460 unlock_rx_qs(priv);
1461 unlock_tx_qs(priv);
1462 local_irq_restore(flags);
d87eb127 1463
be926fc4
AV		 1464 netif_device_attach(ndev);
1465
46ceb60c 1466 enable_napi(priv);
be926fc4
AV		 1467
1468 return 0;
1469}
1470
1471static int gfar_restore(struct device *dev)
1472{
1473 struct gfar_private *priv = dev_get_drvdata(dev);
1474 struct net_device *ndev = priv->ndev;
1475
103cdd1d
WD		 1476 if (!netif_running(ndev)) {
1477 netif_device_attach(ndev);
1478
be926fc4 1479 return 0;
103cdd1d 1480 }
be926fc4 1481
1eb8f7a7
CM		 1482 if (gfar_init_bds(ndev)) {
1483 free_skb_resources(priv);
1484 return -ENOMEM;
1485 }
1486
a328ac92
CM		 1487 gfar_mac_reset(priv);
1488
1489 gfar_init_tx_rx_base(priv);
1490
c10650b6 1491 gfar_start(priv);
be926fc4
AV		 1492
1493 priv->oldlink = 0;
1494 priv->oldspeed = 0;
1495 priv->oldduplex = -1;
1496
1497 if (priv->phydev)
1498 phy_start(priv->phydev);
d87eb127 1499
be926fc4 1500 netif_device_attach(ndev);
5ea681d4 1501 enable_napi(priv);
d87eb127
SW		 1502
1503 return 0;
1504}
be926fc4
AV		 1505
1506static struct dev_pm_ops gfar_pm_ops = {
1507 .suspend = gfar_suspend,
1508 .resume = gfar_resume,
1509 .freeze = gfar_suspend,
1510 .thaw = gfar_resume,
1511 .restore = gfar_restore,
1512};
1513
1514#define GFAR_PM_OPS (&gfar_pm_ops)
1515
d87eb127 1516#else
be926fc4
AV		 1517
1518#define GFAR_PM_OPS NULL
be926fc4 1519
d87eb127 1520#endif
1da177e4 1521
e8a2b6a4
AF		 1522/* Reads the controller's registers to determine what interface
1523 * connects it to the PHY.
1524 */
1525static phy_interface_t gfar_get_interface(struct net_device *dev)
1526{
1527 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1528 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1529 u32 ecntrl;
1530
f4983704 1531 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1532
1533 if (ecntrl & ECNTRL_SGMII_MODE)
1534 return PHY_INTERFACE_MODE_SGMII;
1535
1536 if (ecntrl & ECNTRL_TBI_MODE) {
1537 if (ecntrl & ECNTRL_REDUCED_MODE)
1538 return PHY_INTERFACE_MODE_RTBI;
1539 else
1540 return PHY_INTERFACE_MODE_TBI;
1541 }
1542
1543 if (ecntrl & ECNTRL_REDUCED_MODE) {
bc4598bc 1544 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
e8a2b6a4 1545 return PHY_INTERFACE_MODE_RMII;
bc4598bc 1546 }
7132ab7f 1547 else {
b31a1d8b 1548 phy_interface_t interface = priv->interface;
7132ab7f 1549
0977f817 1550 /* This isn't autodetected right now, so it must
7132ab7f
AF		 1551 * be set by the device tree or platform code.
1552 */
1553 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1554 return PHY_INTERFACE_MODE_RGMII_ID;
1555
e8a2b6a4 1556 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1557 }
e8a2b6a4
AF		 1558 }
1559
b31a1d8b 1560 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1561 return PHY_INTERFACE_MODE_GMII;
1562
1563 return PHY_INTERFACE_MODE_MII;
1564}
1565
1566
bb40dcbb
AF		 1567/* Initializes driver's PHY state, and attaches to the PHY.
1568 * Returns 0 on success.
1da177e4
LT		 1569 */
1570static int init_phy(struct net_device *dev)
1571{
1572 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1573 uint gigabit_support =
b31a1d8b 1574 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
23402bdd 1575 GFAR_SUPPORTED_GBIT : 0;
e8a2b6a4 1576 phy_interface_t interface;
1da177e4
LT		 1577
1578 priv->oldlink = 0;
1579 priv->oldspeed = 0;
1580 priv->oldduplex = -1;
1581
e8a2b6a4
AF		 1582 interface = gfar_get_interface(dev);
1583
1db780f8
AV		 1584 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1585 interface);
1586 if (!priv->phydev)
1587 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1588 interface);
1589 if (!priv->phydev) {
1590 dev_err(&dev->dev, "could not attach to PHY\n");
1591 return -ENODEV;
fe192a49 1592 }
1da177e4 1593
d3c12873
KJ		 1594 if (interface == PHY_INTERFACE_MODE_SGMII)
1595 gfar_configure_serdes(dev);
1596
bb40dcbb 1597 /* Remove any features not supported by the controller */
fe192a49
GL		 1598 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1599 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1600
1601 return 0;
1da177e4
LT		 1602}
1603
0977f817 1604/* Initialize TBI PHY interface for communicating with the
d0313587
PG		 1605 * SERDES lynx PHY on the chip. We communicate with this PHY
1606 * through the MDIO bus on each controller, treating it as a
1607 * "normal" PHY at the address found in the TBIPA register. We assume
1608 * that the TBIPA register is valid. Either the MDIO bus code will set
1609 * it to a value that doesn't conflict with other PHYs on the bus, or the
1610 * value doesn't matter, as there are no other PHYs on the bus.
1611 */
d3c12873
KJ		 1612static void gfar_configure_serdes(struct net_device *dev)
1613{
1614 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1615 struct phy_device *tbiphy;
1616
1617 if (!priv->tbi_node) {
1618 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1619 "device tree specify a tbi-handle\n");
1620 return;
1621 }
c132419e 1622
fe192a49
GL		 1623 tbiphy = of_phy_find_device(priv->tbi_node);
1624 if (!tbiphy) {
1625 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1626 return;
1627 }
d3c12873 1628
0977f817 1629 /* If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1630 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1631 * everything for us? Resetting it takes the link down and requires
1632 * several seconds for it to come back.
1633 */
fe192a49 1634 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1635 return;
d3c12873 1636
d0313587 1637 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1638 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1639
fe192a49 1640 phy_write(tbiphy, MII_ADVERTISE,
bc4598bc
JC		 1641 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1642 ADVERTISE_1000XPSE_ASYM);
d3c12873 1643
bc4598bc
JC		 1644 phy_write(tbiphy, MII_BMCR,
1645 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1646 BMCR_SPEED1000);
d3c12873
KJ		 1647}
1648
511d934f
AV		 1649static int __gfar_is_rx_idle(struct gfar_private *priv)
1650{
1651 u32 res;
1652
0977f817 1653 /* Normaly TSEC should not hang on GRS commands, so we should
511d934f
AV		 1654 * actually wait for IEVENT_GRSC flag.
1655 */
ad3660c2 1656 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
511d934f
AV		 1657 return 0;
1658
0977f817 1659 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
511d934f
AV		 1660 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1661 * and the Rx can be safely reset.
1662 */
1663 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1664 res &= 0x7f807f80;
1665 if ((res & 0xffff) == (res >> 16))
1666 return 1;
1667
1668 return 0;
1669}
0bbaf069
KG		 1670
1671/* Halt the receive and transmit queues */
c10650b6 1672static void gfar_halt_nodisable(struct gfar_private *priv)
1da177e4 1673{
efeddce7 1674 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 1675 u32 tempval;
1676
efeddce7 1677 gfar_ints_disable(priv);
1da177e4 1678
1da177e4 1679 /* Stop the DMA, and wait for it to stop */
f4983704 1680 tempval = gfar_read(&regs->dmactrl);
bc4598bc
JC		 1681 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1682 (DMACTRL_GRS | DMACTRL_GTS)) {
511d934f
AV		 1683 int ret;
1684
1da177e4 1685 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1686 gfar_write(&regs->dmactrl, tempval);
1da177e4 1687
511d934f
AV		 1688 do {
1689 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1690 (IEVENT_GRSC | IEVENT_GTSC)) ==
1691 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1692 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1693 ret = __gfar_is_rx_idle(priv);
1694 } while (!ret);
1da177e4 1695 }
d87eb127 1696}
d87eb127
SW		 1697
1698/* Halt the receive and transmit queues */
c10650b6 1699void gfar_halt(struct gfar_private *priv)
d87eb127 1700{
46ceb60c 1701 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1702 u32 tempval;
1da177e4 1703
c10650b6
CM		 1704 /* Dissable the Rx/Tx hw queues */
1705 gfar_write(&regs->rqueue, 0);
1706 gfar_write(&regs->tqueue, 0);
2a54adc3 1707
c10650b6
CM		 1708 mdelay(10);
1709
1710 gfar_halt_nodisable(priv);
1711
1712 /* Disable Rx/Tx DMA */
1da177e4
LT		 1713 tempval = gfar_read(&regs->maccfg1);
1714 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1715 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1716}
1717
46ceb60c
SG		 1718static void free_grp_irqs(struct gfar_priv_grp *grp)
1719{
ee873fda
CM		 1720 free_irq(gfar_irq(grp, TX)->irq, grp);
1721 free_irq(gfar_irq(grp, RX)->irq, grp);
1722 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 1723}
1724
0bbaf069
KG		 1725void stop_gfar(struct net_device *dev)
1726{
1727 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1728 unsigned long flags;
46ceb60c 1729 int i;
0bbaf069 1730
bb40dcbb
AF		 1731 phy_stop(priv->phydev);
1732
a12f801d 1733
0bbaf069 1734 /* Lock it down */
fba4ed03
SG		 1735 local_irq_save(flags);
1736 lock_tx_qs(priv);
1737 lock_rx_qs(priv);
0bbaf069 1738
c10650b6 1739 gfar_halt(priv);
1da177e4 1740
fba4ed03
SG		 1741 unlock_rx_qs(priv);
1742 unlock_tx_qs(priv);
1743 local_irq_restore(flags);
1da177e4
LT		 1744
1745 /* Free the IRQs */
b31a1d8b 1746 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1747 for (i = 0; i < priv->num_grps; i++)
1748 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1749 } else {
46ceb60c 1750 for (i = 0; i < priv->num_grps; i++)
ee873fda 1751 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
bc4598bc 1752 &priv->gfargrp[i]);
1da177e4
LT		 1753 }
1754
1755 free_skb_resources(priv);
1da177e4
LT		 1756}
1757
fba4ed03 1758static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1759{
1da177e4 1760 struct txbd8 *txbdp;
fba4ed03 1761 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1762 int i, j;
1da177e4 1763
a12f801d 1764 txbdp = tx_queue->tx_bd_base;
1da177e4 1765
a12f801d
SG		 1766 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1767 if (!tx_queue->tx_skbuff[i])
4669bc90 1768 continue;
1da177e4 1769
369ec162 1770 dma_unmap_single(priv->dev, txbdp->bufPtr,
bc4598bc 1771 txbdp->length, DMA_TO_DEVICE);
4669bc90 1772 txbdp->lstatus = 0;
fba4ed03 1773 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
bc4598bc 1774 j++) {
4669bc90 1775 txbdp++;
369ec162 1776 dma_unmap_page(priv->dev, txbdp->bufPtr,
bc4598bc 1777 txbdp->length, DMA_TO_DEVICE);
1da177e4 1778 }
ad5da7ab 1779 txbdp++;
a12f801d
SG		 1780 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1781 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1782 }
a12f801d 1783 kfree(tx_queue->tx_skbuff);
1eb8f7a7 1784 tx_queue->tx_skbuff = NULL;
fba4ed03 1785}
1da177e4 1786
fba4ed03
SG		 1787static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1788{
1789 struct rxbd8 *rxbdp;
1790 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1791 int i;
1da177e4 1792
fba4ed03 1793 rxbdp = rx_queue->rx_bd_base;
1da177e4 1794
a12f801d
SG		 1795 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1796 if (rx_queue->rx_skbuff[i]) {
369ec162
CM		 1797 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1798 priv->rx_buffer_size,
bc4598bc 1799 DMA_FROM_DEVICE);
a12f801d
SG		 1800 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1801 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1802 }
e69edd21
AV		 1803 rxbdp->lstatus = 0;
1804 rxbdp->bufPtr = 0;
1805 rxbdp++;
1da177e4 1806 }
a12f801d 1807 kfree(rx_queue->rx_skbuff);
1eb8f7a7 1808 rx_queue->rx_skbuff = NULL;
fba4ed03 1809}
e69edd21 1810
fba4ed03 1811/* If there are any tx skbs or rx skbs still around, free them.
0977f817
JC		 1812 * Then free tx_skbuff and rx_skbuff
1813 */
fba4ed03
SG		 1814static void free_skb_resources(struct gfar_private *priv)
1815{
1816 struct gfar_priv_tx_q *tx_queue = NULL;
1817 struct gfar_priv_rx_q *rx_queue = NULL;
1818 int i;
1819
1820 /* Go through all the buffer descriptors and free their data buffers */
1821 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 1822 struct netdev_queue *txq;
bc4598bc 1823
fba4ed03 1824 tx_queue = priv->tx_queue[i];
d8a0f1b0 1825 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
bc4598bc 1826 if (tx_queue->tx_skbuff)
fba4ed03 1827 free_skb_tx_queue(tx_queue);
d8a0f1b0 1828 netdev_tx_reset_queue(txq);
fba4ed03
SG		 1829 }
1830
1831 for (i = 0; i < priv->num_rx_queues; i++) {
1832 rx_queue = priv->rx_queue[i];
bc4598bc 1833 if (rx_queue->rx_skbuff)
fba4ed03
SG		 1834 free_skb_rx_queue(rx_queue);
1835 }
1836
369ec162 1837 dma_free_coherent(priv->dev,
bc4598bc
JC		 1838 sizeof(struct txbd8) * priv->total_tx_ring_size +
1839 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1840 priv->tx_queue[0]->tx_bd_base,
1841 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1842}
1843
c10650b6 1844void gfar_start(struct gfar_private *priv)
0bbaf069 1845{
46ceb60c 1846 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1847 u32 tempval;
46ceb60c 1848 int i = 0;
0bbaf069 1849
c10650b6
CM		 1850 /* Enable Rx/Tx hw queues */
1851 gfar_write(&regs->rqueue, priv->rqueue);
1852 gfar_write(&regs->tqueue, priv->tqueue);
0bbaf069
KG		 1853
1854 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1855 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1856 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1857 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1858
0bbaf069 1859 /* Make sure we aren't stopped */
f4983704 1860 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1861 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1862 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1863
46ceb60c
SG		 1864 for (i = 0; i < priv->num_grps; i++) {
1865 regs = priv->gfargrp[i].regs;
1866 /* Clear THLT/RHLT, so that the DMA starts polling now */
1867 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1868 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
46ceb60c 1869 }
12dea57b 1870
c10650b6
CM		 1871 /* Enable Rx/Tx DMA */
1872 tempval = gfar_read(&regs->maccfg1);
1873 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1874 gfar_write(&regs->maccfg1, tempval);
1875
efeddce7
CM		 1876 gfar_ints_enable(priv);
1877
c10650b6 1878 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1879}
1880
800c644b 1881static void gfar_configure_coalescing(struct gfar_private *priv,
bc4598bc 1882 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1883{
46ceb60c 1884 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1885 u32 __iomem *baddr;
815b97c6 1886
46ceb60c 1887 if (priv->mode == MQ_MG_MODE) {
5d9657d8 1888 int i = 0;
c6e1160e 1889
46ceb60c 1890 baddr = &regs->txic0;
984b3f57 1891 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
9740e001
CM		 1892 gfar_write(baddr + i, 0);
1893 if (likely(priv->tx_queue[i]->txcoalescing))
46ceb60c 1894 gfar_write(baddr + i, priv->tx_queue[i]->txic);
46ceb60c
SG		 1895 }
1896
1897 baddr = &regs->rxic0;
984b3f57 1898 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
9740e001
CM		 1899 gfar_write(baddr + i, 0);
1900 if (likely(priv->rx_queue[i]->rxcoalescing))
46ceb60c 1901 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
46ceb60c 1902 }
5d9657d8 1903 } else {
c6e1160e 1904 /* Backward compatible case -- even if we enable
5d9657d8
CM		 1905 * multiple queues, there's only single reg to program
1906 */
1907 gfar_write(&regs->txic, 0);
1908 if (likely(priv->tx_queue[0]->txcoalescing))
1909 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1910
1911 gfar_write(&regs->rxic, 0);
1912 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1913 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
46ceb60c
SG		 1914 }
1915}
1916
800c644b
CM		 1917void gfar_configure_coalescing_all(struct gfar_private *priv)
1918{
1919 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1920}
1921
46ceb60c
SG		 1922static int register_grp_irqs(struct gfar_priv_grp *grp)
1923{
1924 struct gfar_private *priv = grp->priv;
1925 struct net_device *dev = priv->ndev;
1926 int err;
1da177e4 1927
1da177e4 1928 /* If the device has multiple interrupts, register for
0977f817
JC		 1929 * them. Otherwise, only register for the one
1930 */
b31a1d8b 1931 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1932 /* Install our interrupt handlers for Error,
0977f817
JC		 1933 * Transmit, and Receive
1934 */
ee873fda
CM		 1935 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1936 gfar_irq(grp, ER)->name, grp);
1937 if (err < 0) {
59deab26 1938 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1939 gfar_irq(grp, ER)->irq);
46ceb60c 1940
2145f1af 1941 goto err_irq_fail;
1da177e4 1942 }
ee873fda
CM		 1943 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1944 gfar_irq(grp, TX)->name, grp);
1945 if (err < 0) {
59deab26 1946 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1947 gfar_irq(grp, TX)->irq);
1da177e4
LT		 1948 goto tx_irq_fail;
1949 }
ee873fda
CM		 1950 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1951 gfar_irq(grp, RX)->name, grp);
1952 if (err < 0) {
59deab26 1953 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1954 gfar_irq(grp, RX)->irq);
1da177e4
LT		 1955 goto rx_irq_fail;
1956 }
1957 } else {
ee873fda
CM		 1958 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1959 gfar_irq(grp, TX)->name, grp);
1960 if (err < 0) {
59deab26 1961 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1962 gfar_irq(grp, TX)->irq);
1da177e4
LT		 1963 goto err_irq_fail;
1964 }
1965 }
1966
46ceb60c
SG		 1967 return 0;
1968
1969rx_irq_fail:
ee873fda 1970 free_irq(gfar_irq(grp, TX)->irq, grp);
46ceb60c 1971tx_irq_fail:
ee873fda 1972 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 1973err_irq_fail:
1974 return err;
1975
1976}
1977
1978/* Bring the controller up and running */
1979int startup_gfar(struct net_device *ndev)
1980{
1981 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c
SG		 1982 int err, i, j;
1983
a328ac92 1984 gfar_mac_reset(priv);
46ceb60c 1985
46ceb60c
SG		 1986 err = gfar_alloc_skb_resources(ndev);
1987 if (err)
1988 return err;
1989
a328ac92 1990 gfar_init_tx_rx_base(priv);
46ceb60c
SG		 1991
1992 for (i = 0; i < priv->num_grps; i++) {
1993 err = register_grp_irqs(&priv->gfargrp[i]);
1994 if (err) {
1995 for (j = 0; j < i; j++)
1996 free_grp_irqs(&priv->gfargrp[j]);
ff76015f 1997 goto irq_fail;
46ceb60c
SG		 1998 }
1999 }
2000
7f7f5316 2001 /* Start the controller */
c10650b6 2002 gfar_start(priv);
1da177e4 2003
826aa4a0
AV		 2004 phy_start(priv->phydev);
2005
1da177e4
LT		 2006 return 0;
2007
46ceb60c 2008irq_fail:
e69edd21 2009 free_skb_resources(priv);
1da177e4
LT		 2010 return err;
2011}
2012
0977f817
JC		 2013/* Called when something needs to use the ethernet device
2014 * Returns 0 for success.
2015 */
1da177e4
LT		 2016static int gfar_enet_open(struct net_device *dev)
2017{
94e8cc35 2018 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 2019 int err;
2020
46ceb60c 2021 enable_napi(priv);
bea3348e 2022
1da177e4
LT		 2023 err = init_phy(dev);
2024
a12f801d 2025 if (err) {
46ceb60c 2026 disable_napi(priv);
1da177e4 2027 return err;
bea3348e 2028 }
1da177e4
LT		 2029
2030 err = startup_gfar(dev);
db0e8e3f 2031 if (err) {
46ceb60c 2032 disable_napi(priv);
db0e8e3f
AV		 2033 return err;
2034 }
1da177e4 2035
fba4ed03 2036 netif_tx_start_all_queues(dev);
1da177e4 2037
2884e5cc
AV		 2038 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2039
1da177e4
LT		 2040 return err;
2041}
2042
54dc79fe 2043static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 2044{
54dc79fe 2045 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 2046
2047 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 2048
0bbaf069
KG		 2049 return fcb;
2050}
2051
9c4886e5 2052static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
bc4598bc 2053 int fcb_length)
0bbaf069 2054{
0bbaf069
KG		 2055 /* If we're here, it's a IP packet with a TCP or UDP
2056 * payload. We set it to checksum, using a pseudo-header
2057 * we provide
2058 */
3a2e16c8 2059 u8 flags = TXFCB_DEFAULT;
0bbaf069 2060
0977f817
JC		 2061 /* Tell the controller what the protocol is
2062 * And provide the already calculated phcs
2063 */
eddc9ec5 2064 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2065 flags |= TXFCB_UDP;
4bedb452 2066 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 2067 } else
8da32de5 2068 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 2069
2070 /* l3os is the distance between the start of the
2071 * frame (skb->data) and the start of the IP hdr.
2072 * l4os is the distance between the start of the
0977f817
JC		 2073 * l3 hdr and the l4 hdr
2074 */
9c4886e5 2075 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
cfe1fc77 2076 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2077
7f7f5316 2078 fcb->flags = flags;
0bbaf069
KG		 2079}
2080
7f7f5316 2081void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2082{
7f7f5316 2083 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 2084 fcb->vlctl = vlan_tx_tag_get(skb);
2085}
2086
4669bc90 2087static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
bc4598bc 2088 struct txbd8 *base, int ring_size)
4669bc90
DH		 2089{
2090 struct txbd8 *new_bd = bdp + stride;
2091
2092 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2093}
2094
2095static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
bc4598bc 2096 int ring_size)
4669bc90
DH		 2097{
2098 return skip_txbd(bdp, 1, base, ring_size);
2099}
2100
02d88fb4
CM		 2101/* eTSEC12: csum generation not supported for some fcb offsets */
2102static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2103 unsigned long fcb_addr)
2104{
2105 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2106 (fcb_addr % 0x20) > 0x18);
2107}
2108
2109/* eTSEC76: csum generation for frames larger than 2500 may
2110 * cause excess delays before start of transmission
2111 */
2112static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2113 unsigned int len)
2114{
2115 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2116 (len > 2500));
2117}
2118
0977f817
JC		 2119/* This is called by the kernel when a frame is ready for transmission.
2120 * It is pointed to by the dev->hard_start_xmit function pointer
2121 */
1da177e4
LT		 2122static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2123{
2124 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2125 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2126 struct netdev_queue *txq;
f4983704 2127 struct gfar __iomem *regs = NULL;
0bbaf069 2128 struct txfcb *fcb = NULL;
f0ee7acf 2129 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2130 u32 lstatus;
0d0cffdc
CM		 2131 int i, rq = 0;
2132 int do_tstamp, do_csum, do_vlan;
4669bc90 2133 u32 bufaddr;
fef6108d 2134 unsigned long flags;
50ad076b 2135 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
fba4ed03
SG		 2136
2137 rq = skb->queue_mapping;
2138 tx_queue = priv->tx_queue[rq];
2139 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2140 base = tx_queue->tx_bd_base;
46ceb60c 2141 regs = tx_queue->grp->regs;
f0ee7acf 2142
0d0cffdc
CM		 2143 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2144 do_vlan = vlan_tx_tag_present(skb);
2145 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2146 priv->hwts_tx_en;
2147
2148 if (do_csum || do_vlan)
2149 fcb_len = GMAC_FCB_LEN;
2150
f0ee7acf 2151 /* check if time stamp should be generated */
0d0cffdc
CM		 2152 if (unlikely(do_tstamp))
2153 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
4669bc90 2154
5b28beaf 2155 /* make space for additional header when fcb is needed */
0d0cffdc 2156 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
54dc79fe
SH		 2157 struct sk_buff *skb_new;
2158
0d0cffdc 2159 skb_new = skb_realloc_headroom(skb, fcb_len);
54dc79fe
SH		 2160 if (!skb_new) {
2161 dev->stats.tx_errors++;
bd14ba84 2162 kfree_skb(skb);
54dc79fe
SH		 2163 return NETDEV_TX_OK;
2164 }
db83d136 2165
313b037c
ED		 2166 if (skb->sk)
2167 skb_set_owner_w(skb_new, skb->sk);
2168 consume_skb(skb);
54dc79fe
SH		 2169 skb = skb_new;
2170 }
2171
4669bc90
DH		 2172 /* total number of fragments in the SKB */
2173 nr_frags = skb_shinfo(skb)->nr_frags;
2174
f0ee7acf
MR		 2175 /* calculate the required number of TxBDs for this skb */
2176 if (unlikely(do_tstamp))
2177 nr_txbds = nr_frags + 2;
2178 else
2179 nr_txbds = nr_frags + 1;
2180
4669bc90 2181 /* check if there is space to queue this packet */
f0ee7acf 2182 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2183 /* no space, stop the queue */
fba4ed03 2184 netif_tx_stop_queue(txq);
4669bc90 2185 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2186 return NETDEV_TX_BUSY;
2187 }
1da177e4
LT		 2188
2189 /* Update transmit stats */
50ad076b
CM		 2190 bytes_sent = skb->len;
2191 tx_queue->stats.tx_bytes += bytes_sent;
2192 /* keep Tx bytes on wire for BQL accounting */
2193 GFAR_CB(skb)->bytes_sent = bytes_sent;
1ac9ad13 2194 tx_queue->stats.tx_packets++;
1da177e4 2195
a12f801d 2196 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2197 lstatus = txbdp->lstatus;
2198
2199 /* Time stamp insertion requires one additional TxBD */
2200 if (unlikely(do_tstamp))
2201 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
bc4598bc 2202 tx_queue->tx_ring_size);
1da177e4 2203
4669bc90 2204 if (nr_frags == 0) {
f0ee7acf
MR		 2205 if (unlikely(do_tstamp))
2206 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
bc4598bc 2207 TXBD_INTERRUPT);
f0ee7acf
MR		 2208 else
2209 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2210 } else {
2211 /* Place the fragment addresses and lengths into the TxBDs */
2212 for (i = 0; i < nr_frags; i++) {
50ad076b 2213 unsigned int frag_len;
4669bc90 2214 /* Point at the next BD, wrapping as needed */
a12f801d 2215 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2216
50ad076b 2217 frag_len = skb_shinfo(skb)->frags[i].size;
4669bc90 2218
50ad076b 2219 lstatus = txbdp->lstatus | frag_len |
bc4598bc 2220 BD_LFLAG(TXBD_READY);
4669bc90
DH		 2221
2222 /* Handle the last BD specially */
2223 if (i == nr_frags - 1)
2224 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2225
369ec162 2226 bufaddr = skb_frag_dma_map(priv->dev,
2234a722
IC		 2227 &skb_shinfo(skb)->frags[i],
2228 0,
50ad076b 2229 frag_len,
2234a722 2230 DMA_TO_DEVICE);
4669bc90
DH		 2231
2232 /* set the TxBD length and buffer pointer */
2233 txbdp->bufPtr = bufaddr;
2234 txbdp->lstatus = lstatus;
2235 }
2236
2237 lstatus = txbdp_start->lstatus;
2238 }
1da177e4 2239
9c4886e5
MR		 2240 /* Add TxPAL between FCB and frame if required */
2241 if (unlikely(do_tstamp)) {
2242 skb_push(skb, GMAC_TXPAL_LEN);
2243 memset(skb->data, 0, GMAC_TXPAL_LEN);
2244 }
2245
0d0cffdc
CM		 2246 /* Add TxFCB if required */
2247 if (fcb_len) {
54dc79fe 2248 fcb = gfar_add_fcb(skb);
02d88fb4 2249 lstatus |= BD_LFLAG(TXBD_TOE);
0d0cffdc
CM		 2250 }
2251
2252 /* Set up checksumming */
2253 if (do_csum) {
2254 gfar_tx_checksum(skb, fcb, fcb_len);
02d88fb4
CM		 2255
2256 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2257 unlikely(gfar_csum_errata_76(priv, skb->len))) {
4363c2fd
AD		 2258 __skb_pull(skb, GMAC_FCB_LEN);
2259 skb_checksum_help(skb);
0d0cffdc
CM		 2260 if (do_vlan || do_tstamp) {
2261 /* put back a new fcb for vlan/tstamp TOE */
2262 fcb = gfar_add_fcb(skb);
2263 } else {
2264 /* Tx TOE not used */
2265 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2266 fcb = NULL;
2267 }
4363c2fd 2268 }
0bbaf069
KG		 2269 }
2270
0d0cffdc 2271 if (do_vlan)
54dc79fe 2272 gfar_tx_vlan(skb, fcb);
0bbaf069 2273
f0ee7acf
MR		 2274 /* Setup tx hardware time stamping if requested */
2275 if (unlikely(do_tstamp)) {
2244d07b 2276 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf 2277 fcb->ptp = 1;
f0ee7acf
MR		 2278 }
2279
369ec162 2280 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
bc4598bc 2281 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2282
0977f817 2283 /* If time stamping is requested one additional TxBD must be set up. The
f0ee7acf
MR		 2284 * first TxBD points to the FCB and must have a data length of
2285 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2286 * the full frame length.
2287 */
2288 if (unlikely(do_tstamp)) {
0d0cffdc 2289 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
f0ee7acf 2290 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
0d0cffdc 2291 (skb_headlen(skb) - fcb_len);
f0ee7acf
MR		 2292 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2293 } else {
2294 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2295 }
1da177e4 2296
50ad076b 2297 netdev_tx_sent_queue(txq, bytes_sent);
d8a0f1b0 2298
0977f817 2299 /* We can work in parallel with gfar_clean_tx_ring(), except
a3bc1f11
AV		 2300 * when modifying num_txbdfree. Note that we didn't grab the lock
2301 * when we were reading the num_txbdfree and checking for available
2302 * space, that's because outside of this function it can only grow,
2303 * and once we've got needed space, it cannot suddenly disappear.
2304 *
2305 * The lock also protects us from gfar_error(), which can modify
2306 * regs->tstat and thus retrigger the transfers, which is why we
2307 * also must grab the lock before setting ready bit for the first
2308 * to be transmitted BD.
2309 */
2310 spin_lock_irqsave(&tx_queue->txlock, flags);
2311
0977f817 2312 /* The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2313 * semantics (it requires synchronization between cacheable and
2314 * uncacheable mappings, which eieio doesn't provide and which we
2315 * don't need), thus requiring a more expensive sync instruction. At
2316 * some point, the set of architecture-independent barrier functions
2317 * should be expanded to include weaker barriers.
2318 */
3b6330ce 2319 eieio();
7f7f5316 2320
4669bc90
DH		 2321 txbdp_start->lstatus = lstatus;
2322
0eddba52
AV		 2323 eieio(); /* force lstatus write before tx_skbuff */
2324
2325 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2326
4669bc90 2327 /* Update the current skb pointer to the next entry we will use
0977f817
JC		 2328 * (wrapping if necessary)
2329 */
a12f801d 2330 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
bc4598bc 2331 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2332
a12f801d 2333 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2334
2335 /* reduce TxBD free count */
f0ee7acf 2336 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2337
2338 /* If the next BD still needs to be cleaned up, then the bds
0977f817
JC		 2339 * are full. We need to tell the kernel to stop sending us stuff.
2340 */
a12f801d 2341 if (!tx_queue->num_txbdfree) {
fba4ed03 2342 netif_tx_stop_queue(txq);
1da177e4 2343
09f75cd7 2344 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2345 }
2346
1da177e4 2347 /* Tell the DMA to go go go */
fba4ed03 2348 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2349
2350 /* Unlock priv */
a12f801d 2351 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2352
54dc79fe 2353 return NETDEV_TX_OK;
1da177e4
LT		 2354}
2355
2356/* Stops the kernel queue, and halts the controller */
2357static int gfar_close(struct net_device *dev)
2358{
2359 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2360
46ceb60c 2361 disable_napi(priv);
bea3348e 2362
ab939905 2363 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2364 stop_gfar(dev);
2365
bb40dcbb
AF		 2366 /* Disconnect from the PHY */
2367 phy_disconnect(priv->phydev);
2368 priv->phydev = NULL;
1da177e4 2369
fba4ed03 2370 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2371
2372 return 0;
2373}
2374
1da177e4 2375/* Changes the mac address if the controller is not running. */
f162b9d5 2376static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2377{
7f7f5316 2378 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2379
2380 return 0;
2381}
2382
1da177e4
LT		 2383static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2384{
1da177e4 2385 struct gfar_private *priv = netdev_priv(dev);
0bbaf069
KG		 2386 int frame_size = new_mtu + ETH_HLEN;
2387
1da177e4 2388 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2389 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2390 return -EINVAL;
2391 }
2392
88302648 2393 if (dev->flags & IFF_UP)
1da177e4
LT		 2394 stop_gfar(dev);
2395
1da177e4
LT		 2396 dev->mtu = new_mtu;
2397
88302648 2398 if (dev->flags & IFF_UP)
1da177e4
LT		 2399 startup_gfar(dev);
2400
2401 return 0;
2402}
2403
ab939905 2404/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2405 * transmitted after a set amount of time.
2406 * For now, assume that clearing out all the structures, and
ab939905
SS		 2407 * starting over will fix the problem.
2408 */
2409static void gfar_reset_task(struct work_struct *work)
1da177e4 2410{
ab939905 2411 struct gfar_private *priv = container_of(work, struct gfar_private,
bc4598bc 2412 reset_task);
4826857f 2413 struct net_device *dev = priv->ndev;
1da177e4
LT		 2414
2415 if (dev->flags & IFF_UP) {
fba4ed03 2416 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2417 stop_gfar(dev);
2418 startup_gfar(dev);
fba4ed03 2419 netif_tx_start_all_queues(dev);
1da177e4
LT		 2420 }
2421
263ba320 2422 netif_tx_schedule_all(dev);
1da177e4
LT		 2423}
2424
ab939905
SS		 2425static void gfar_timeout(struct net_device *dev)
2426{
2427 struct gfar_private *priv = netdev_priv(dev);
2428
2429 dev->stats.tx_errors++;
2430 schedule_work(&priv->reset_task);
2431}
2432
acbc0f03
EL		 2433static void gfar_align_skb(struct sk_buff *skb)
2434{
2435 /* We need the data buffer to be aligned properly. We will reserve
2436 * as many bytes as needed to align the data properly
2437 */
2438 skb_reserve(skb, RXBUF_ALIGNMENT -
bc4598bc 2439 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
acbc0f03
EL		 2440}
2441
1da177e4 2442/* Interrupt Handler for Transmit complete */
c233cf40 2443static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2444{
a12f801d 2445 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2446 struct netdev_queue *txq;
d080cd63 2447 struct gfar_private *priv = netdev_priv(dev);
f0ee7acf 2448 struct txbd8 *bdp, *next = NULL;
4669bc90 2449 struct txbd8 *lbdp = NULL;
a12f801d 2450 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2451 struct sk_buff *skb;
2452 int skb_dirtytx;
a12f801d 2453 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2454 int frags = 0, nr_txbds = 0;
4669bc90 2455 int i;
d080cd63 2456 int howmany = 0;
d8a0f1b0
PG		 2457 int tqi = tx_queue->qindex;
2458 unsigned int bytes_sent = 0;
4669bc90 2459 u32 lstatus;
f0ee7acf 2460 size_t buflen;
1da177e4 2461
d8a0f1b0 2462 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2463 bdp = tx_queue->dirty_tx;
2464 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2465
a12f801d 2466 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2467 unsigned long flags;
2468
4669bc90 2469 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf 2470
0977f817 2471 /* When time stamping, one additional TxBD must be freed.
f0ee7acf
MR		 2472 * Also, we need to dma_unmap_single() the TxPAL.
2473 */
2244d07b 2474 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2475 nr_txbds = frags + 2;
2476 else
2477 nr_txbds = frags + 1;
2478
2479 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2480
4669bc90 2481 lstatus = lbdp->lstatus;
1da177e4 2482
4669bc90
DH		 2483 /* Only clean completed frames */
2484 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
bc4598bc 2485 (lstatus & BD_LENGTH_MASK))
4669bc90
DH		 2486 break;
2487
2244d07b 2488 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2489 next = next_txbd(bdp, base, tx_ring_size);
9c4886e5 2490 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf
MR		 2491 } else
2492 buflen = bdp->length;
2493
369ec162 2494 dma_unmap_single(priv->dev, bdp->bufPtr,
bc4598bc 2495 buflen, DMA_TO_DEVICE);
f0ee7acf 2496
2244d07b 2497 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2498 struct skb_shared_hwtstamps shhwtstamps;
2499 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
bc4598bc 2500
f0ee7acf
MR		 2501 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2502 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
9c4886e5 2503 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf
MR		 2504 skb_tstamp_tx(skb, &shhwtstamps);
2505 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2506 bdp = next;
2507 }
81183059 2508
4669bc90
DH		 2509 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2510 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2511
4669bc90 2512 for (i = 0; i < frags; i++) {
369ec162 2513 dma_unmap_page(priv->dev, bdp->bufPtr,
bc4598bc 2514 bdp->length, DMA_TO_DEVICE);
4669bc90
DH		 2515 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2516 bdp = next_txbd(bdp, base, tx_ring_size);
2517 }
1da177e4 2518
50ad076b 2519 bytes_sent += GFAR_CB(skb)->bytes_sent;
d8a0f1b0 2520
acb600de 2521 dev_kfree_skb_any(skb);
0fd56bb5 2522
a12f801d 2523 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2524
4669bc90 2525 skb_dirtytx = (skb_dirtytx + 1) &
bc4598bc 2526 TX_RING_MOD_MASK(tx_ring_size);
4669bc90
DH		 2527
2528 howmany++;
a3bc1f11 2529 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2530 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2531 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2532 }
1da177e4 2533
4669bc90 2534 /* If we freed a buffer, we can restart transmission, if necessary */
5407b14c 2535 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
d8a0f1b0 2536 netif_wake_subqueue(dev, tqi);
1da177e4 2537
4669bc90 2538 /* Update dirty indicators */
a12f801d
SG		 2539 tx_queue->skb_dirtytx = skb_dirtytx;
2540 tx_queue->dirty_tx = bdp;
1da177e4 2541
d8a0f1b0 2542 netdev_tx_completed_queue(txq, howmany, bytes_sent);
d080cd63
DH		 2543}
2544
f4983704 2545static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2546{
a6d0b91a
AV		 2547 unsigned long flags;
2548
fba4ed03
SG		 2549 spin_lock_irqsave(&gfargrp->grplock, flags);
2550 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2551 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2552 __napi_schedule(&gfargrp->napi);
8707bdd4 2553 } else {
0977f817 2554 /* Clear IEVENT, so interrupts aren't called again
8707bdd4
JP		 2555 * because of the packets that have already arrived.
2556 */
f4983704 2557 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2558 }
fba4ed03 2559 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2560
8c7396ae 2561}
1da177e4 2562
8c7396ae 2563/* Interrupt Handler for Transmit complete */
f4983704 2564static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2565{
f4983704 2566 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2567 return IRQ_HANDLED;
2568}
2569
a12f801d 2570static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
bc4598bc 2571 struct sk_buff *skb)
815b97c6 2572{
a12f801d 2573 struct net_device *dev = rx_queue->dev;
815b97c6 2574 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2575 dma_addr_t buf;
815b97c6 2576
369ec162 2577 buf = dma_map_single(priv->dev, skb->data,
8a102fe0 2578 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2579 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2580}
2581
2281a0f3 2582static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2583{
2584 struct gfar_private *priv = netdev_priv(dev);
acb600de 2585 struct sk_buff *skb;
1da177e4 2586
acbc0f03 2587 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2588 if (!skb)
1da177e4
LT		 2589 return NULL;
2590
acbc0f03 2591 gfar_align_skb(skb);
7f7f5316 2592
acbc0f03
EL		 2593 return skb;
2594}
2595
2281a0f3 2596struct sk_buff *gfar_new_skb(struct net_device *dev)
acbc0f03 2597{
acb600de 2598 return gfar_alloc_skb(dev);
1da177e4
LT		 2599}
2600
298e1a9e 2601static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2602{
298e1a9e 2603 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2604 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2605 struct gfar_extra_stats *estats = &priv->extra_stats;
2606
0977f817 2607 /* If the packet was truncated, none of the other errors matter */
1da177e4
LT		 2608 if (status & RXBD_TRUNCATED) {
2609 stats->rx_length_errors++;
2610
212079df 2611 atomic64_inc(&estats->rx_trunc);
1da177e4
LT		 2612
2613 return;
2614 }
2615 /* Count the errors, if there were any */
2616 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2617 stats->rx_length_errors++;
2618
2619 if (status & RXBD_LARGE)
212079df 2620 atomic64_inc(&estats->rx_large);
1da177e4 2621 else
212079df 2622 atomic64_inc(&estats->rx_short);
1da177e4
LT		 2623 }
2624 if (status & RXBD_NONOCTET) {
2625 stats->rx_frame_errors++;
212079df 2626 atomic64_inc(&estats->rx_nonoctet);
1da177e4
LT		 2627 }
2628 if (status & RXBD_CRCERR) {
212079df 2629 atomic64_inc(&estats->rx_crcerr);
1da177e4
LT		 2630 stats->rx_crc_errors++;
2631 }
2632 if (status & RXBD_OVERRUN) {
212079df 2633 atomic64_inc(&estats->rx_overrun);
1da177e4
LT		 2634 stats->rx_crc_errors++;
2635 }
2636}
2637
f4983704 2638irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2639{
f4983704 2640 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2641 return IRQ_HANDLED;
2642}
2643
0bbaf069
KG		 2644static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2645{
2646 /* If valid headers were found, and valid sums
2647 * were verified, then we tell the kernel that no
0977f817
JC		 2648 * checksumming is necessary. Otherwise, it is [FIXME]
2649 */
7f7f5316 2650 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2651 skb->ip_summed = CHECKSUM_UNNECESSARY;
2652 else
bc8acf2c 2653 skb_checksum_none_assert(skb);
0bbaf069
KG		 2654}
2655
2656
0977f817 2657/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
61db26c6
CM		 2658static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2659 int amount_pull, struct napi_struct *napi)
1da177e4
LT		 2660{
2661 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2662 struct rxfcb *fcb = NULL;
1da177e4 2663
2c2db48a
DH		 2664 /* fcb is at the beginning if exists */
2665 fcb = (struct rxfcb *)skb->data;
0bbaf069 2666
0977f817
JC		 2667 /* Remove the FCB from the skb
2668 * Remove the padded bytes, if there are any
2669 */
f74dac08
SG		 2670 if (amount_pull) {
2671 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2672 skb_pull(skb, amount_pull);
f74dac08 2673 }
0bbaf069 2674
cc772ab7
MR		 2675 /* Get receive timestamp from the skb */
2676 if (priv->hwts_rx_en) {
2677 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2678 u64 *ns = (u64 *) skb->data;
bc4598bc 2679
cc772ab7
MR		 2680 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2681 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2682 }
2683
2684 if (priv->padding)
2685 skb_pull(skb, priv->padding);
2686
8b3afe95 2687 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2688 gfar_rx_checksum(skb, fcb);
0bbaf069 2689
2c2db48a
DH		 2690 /* Tell the skb what kind of packet this is */
2691 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2692
f646968f 2693 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
32f7fd44
JP		 2694 * Even if vlan rx accel is disabled, on some chips
2695 * RXFCB_VLN is pseudo randomly set.
2696 */
f646968f 2697 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
32f7fd44 2698 fcb->flags & RXFCB_VLN)
e5905c83 2699 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
87c288c6 2700
2c2db48a 2701 /* Send the packet up the stack */
953d2768 2702 napi_gro_receive(napi, skb);
0bbaf069 2703
1da177e4
LT		 2704}
2705
2706/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2281a0f3
JC		 2707 * until the budget/quota has been reached. Returns the number
2708 * of frames handled
1da177e4 2709 */
a12f801d 2710int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2711{
a12f801d 2712 struct net_device *dev = rx_queue->dev;
31de198b 2713 struct rxbd8 *bdp, *base;
1da177e4 2714 struct sk_buff *skb;
2c2db48a
DH		 2715 int pkt_len;
2716 int amount_pull;
1da177e4
LT		 2717 int howmany = 0;
2718 struct gfar_private *priv = netdev_priv(dev);
2719
2720 /* Get the first full descriptor */
a12f801d
SG		 2721 bdp = rx_queue->cur_rx;
2722 base = rx_queue->rx_bd_base;
1da177e4 2723
ba779711 2724 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2c2db48a 2725
1da177e4 2726 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2727 struct sk_buff *newskb;
bc4598bc 2728
3b6330ce 2729 rmb();
815b97c6
AF		 2730
2731 /* Add another skb for the future */
2732 newskb = gfar_new_skb(dev);
2733
a12f801d 2734 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2735
369ec162 2736 dma_unmap_single(priv->dev, bdp->bufPtr,
bc4598bc 2737 priv->rx_buffer_size, DMA_FROM_DEVICE);
81183059 2738
63b88b90 2739 if (unlikely(!(bdp->status & RXBD_ERR) &&
bc4598bc 2740 bdp->length > priv->rx_buffer_size))
63b88b90
AV		 2741 bdp->status = RXBD_LARGE;
2742
815b97c6
AF		 2743 /* We drop the frame if we failed to allocate a new buffer */
2744 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
bc4598bc 2745 bdp->status & RXBD_ERR)) {
815b97c6
AF		 2746 count_errors(bdp->status, dev);
2747
2748 if (unlikely(!newskb))
2749 newskb = skb;
acbc0f03 2750 else if (skb)
acb600de 2751 dev_kfree_skb(skb);
815b97c6 2752 } else {
1da177e4 2753 /* Increment the number of packets */
a7f38041 2754 rx_queue->stats.rx_packets++;
1da177e4
LT		 2755 howmany++;
2756
2c2db48a
DH		 2757 if (likely(skb)) {
2758 pkt_len = bdp->length - ETH_FCS_LEN;
2759 /* Remove the FCS from the packet length */
2760 skb_put(skb, pkt_len);
a7f38041 2761 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2762 skb_record_rx_queue(skb, rx_queue->qindex);
cd754a57 2763 gfar_process_frame(dev, skb, amount_pull,
bc4598bc 2764 &rx_queue->grp->napi);
2c2db48a
DH		 2765
2766 } else {
59deab26 2767 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2768 rx_queue->stats.rx_dropped++;
212079df 2769 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2c2db48a 2770 }
1da177e4 2771
1da177e4
LT		 2772 }
2773
a12f801d 2774 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2775
815b97c6 2776 /* Setup the new bdp */
a12f801d 2777 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2778
2779 /* Update to the next pointer */
a12f801d 2780 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2781
2782 /* update to point at the next skb */
bc4598bc
JC		 2783 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2784 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2785 }
2786
2787 /* Update the current rxbd pointer to be the next one */
a12f801d 2788 rx_queue->cur_rx = bdp;
1da177e4 2789
1da177e4
LT		 2790 return howmany;
2791}
2792
5eaedf31
CM		 2793static int gfar_poll_sq(struct napi_struct *napi, int budget)
2794{
2795 struct gfar_priv_grp *gfargrp =
2796 container_of(napi, struct gfar_priv_grp, napi);
2797 struct gfar __iomem *regs = gfargrp->regs;
2798 struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
2799 struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
2800 int work_done = 0;
2801
2802 /* Clear IEVENT, so interrupts aren't called again
2803 * because of the packets that have already arrived
2804 */
2805 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2806
2807 /* run Tx cleanup to completion */
2808 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2809 gfar_clean_tx_ring(tx_queue);
2810
2811 work_done = gfar_clean_rx_ring(rx_queue, budget);
2812
2813 if (work_done < budget) {
2814 napi_complete(napi);
2815 /* Clear the halt bit in RSTAT */
2816 gfar_write(&regs->rstat, gfargrp->rstat);
2817
2818 gfar_write(&regs->imask, IMASK_DEFAULT);
2819
2820 /* If we are coalescing interrupts, update the timer
2821 * Otherwise, clear it
2822 */
2823 gfar_write(&regs->txic, 0);
2824 if (likely(tx_queue->txcoalescing))
2825 gfar_write(&regs->txic, tx_queue->txic);
2826
2827 gfar_write(&regs->rxic, 0);
2828 if (unlikely(rx_queue->rxcoalescing))
2829 gfar_write(&regs->rxic, rx_queue->rxic);
2830 }
2831
2832 return work_done;
2833}
2834
bea3348e 2835static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2836{
bc4598bc
JC		 2837 struct gfar_priv_grp *gfargrp =
2838 container_of(napi, struct gfar_priv_grp, napi);
fba4ed03 2839 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2840 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2841 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2842 struct gfar_priv_rx_q *rx_queue = NULL;
c233cf40 2843 int work_done = 0, work_done_per_q = 0;
39c0a0d5 2844 int i, budget_per_q = 0;
3ba405db 2845 int has_tx_work = 0;
6be5ed3f
CM		 2846 unsigned long rstat_rxf;
2847 int num_act_queues;
fba4ed03 2848
8c7396ae 2849 /* Clear IEVENT, so interrupts aren't called again
0977f817
JC		 2850 * because of the packets that have already arrived
2851 */
f4983704 2852 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2853
6be5ed3f
CM		 2854 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2855
2856 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2857 if (num_act_queues)
2858 budget_per_q = budget/num_act_queues;
2859
3ba405db
CM		 2860 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2861 tx_queue = priv->tx_queue[i];
2862 /* run Tx cleanup to completion */
2863 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2864 gfar_clean_tx_ring(tx_queue);
2865 has_tx_work = 1;
c233cf40 2866 }
3ba405db 2867 }
fba4ed03 2868
3ba405db
CM		 2869 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2870 /* skip queue if not active */
2871 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2872 continue;
1da177e4 2873
3ba405db
CM		 2874 rx_queue = priv->rx_queue[i];
2875 work_done_per_q =
2876 gfar_clean_rx_ring(rx_queue, budget_per_q);
2877 work_done += work_done_per_q;
2878
2879 /* finished processing this queue */
2880 if (work_done_per_q < budget_per_q) {
2881 /* clear active queue hw indication */
2882 gfar_write(&regs->rstat,
2883 RSTAT_CLEAR_RXF0 >> i);
2884 num_act_queues--;
2885
2886 if (!num_act_queues)
2887 break;
2888 }
2889 }
42199884 2890
3ba405db 2891 if (!num_act_queues && !has_tx_work) {
1da177e4 2892
3ba405db 2893 napi_complete(napi);
1da177e4 2894
3ba405db
CM		 2895 /* Clear the halt bit in RSTAT */
2896 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2897
3ba405db 2898 gfar_write(&regs->imask, IMASK_DEFAULT);
c233cf40 2899
3ba405db
CM		 2900 /* If we are coalescing interrupts, update the timer
2901 * Otherwise, clear it
2902 */
2903 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2904 gfargrp->tx_bit_map);
1da177e4
LT		 2905 }
2906
c233cf40 2907 return work_done;
1da177e4 2908}
1da177e4 2909
f2d71c2d 2910#ifdef CONFIG_NET_POLL_CONTROLLER
0977f817 2911/* Polling 'interrupt' - used by things like netconsole to send skbs
f2d71c2d
VW		 2912 * without having to re-enable interrupts. It's not called while
2913 * the interrupt routine is executing.
2914 */
2915static void gfar_netpoll(struct net_device *dev)
2916{
2917 struct gfar_private *priv = netdev_priv(dev);
3a2e16c8 2918 int i;
f2d71c2d
VW		 2919
2920 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2921 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c 2922 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 2923 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2924
2925 disable_irq(gfar_irq(grp, TX)->irq);
2926 disable_irq(gfar_irq(grp, RX)->irq);
2927 disable_irq(gfar_irq(grp, ER)->irq);
2928 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2929 enable_irq(gfar_irq(grp, ER)->irq);
2930 enable_irq(gfar_irq(grp, RX)->irq);
2931 enable_irq(gfar_irq(grp, TX)->irq);
46ceb60c 2932 }
f2d71c2d 2933 } else {
46ceb60c 2934 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 2935 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2936
2937 disable_irq(gfar_irq(grp, TX)->irq);
2938 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2939 enable_irq(gfar_irq(grp, TX)->irq);
43de004b 2940 }
f2d71c2d
VW		 2941 }
2942}
2943#endif
2944
1da177e4 2945/* The interrupt handler for devices with one interrupt */
f4983704 2946static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2947{
f4983704 2948 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2949
2950 /* Save ievent for future reference */
f4983704 2951 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2952
1da177e4 2953 /* Check for reception */
538cc7ee 2954 if (events & IEVENT_RX_MASK)
f4983704 2955 gfar_receive(irq, grp_id);
1da177e4
LT		 2956
2957 /* Check for transmit completion */
538cc7ee 2958 if (events & IEVENT_TX_MASK)
f4983704 2959 gfar_transmit(irq, grp_id);
1da177e4 2960
538cc7ee
SS		 2961 /* Check for errors */
2962 if (events & IEVENT_ERR_MASK)
f4983704 2963 gfar_error(irq, grp_id);
1da177e4
LT		 2964
2965 return IRQ_HANDLED;
2966}
2967
23402bdd
CM		 2968static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
2969{
2970 struct phy_device *phydev = priv->phydev;
2971 u32 val = 0;
2972
2973 if (!phydev->duplex)
2974 return val;
2975
2976 if (!priv->pause_aneg_en) {
2977 if (priv->tx_pause_en)
2978 val |= MACCFG1_TX_FLOW;
2979 if (priv->rx_pause_en)
2980 val |= MACCFG1_RX_FLOW;
2981 } else {
2982 u16 lcl_adv, rmt_adv;
2983 u8 flowctrl;
2984 /* get link partner capabilities */
2985 rmt_adv = 0;
2986 if (phydev->pause)
2987 rmt_adv = LPA_PAUSE_CAP;
2988 if (phydev->asym_pause)
2989 rmt_adv |= LPA_PAUSE_ASYM;
2990
2991 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
2992
2993 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
2994 if (flowctrl & FLOW_CTRL_TX)
2995 val |= MACCFG1_TX_FLOW;
2996 if (flowctrl & FLOW_CTRL_RX)
2997 val |= MACCFG1_RX_FLOW;
2998 }
2999
3000 return val;
3001}
3002
1da177e4
LT		 3003/* Called every time the controller might need to be made
3004 * aware of new link state. The PHY code conveys this
bb40dcbb 3005 * information through variables in the phydev structure, and this
1da177e4
LT		 3006 * function converts those variables into the appropriate
3007 * register values, and can bring down the device if needed.
3008 */
3009static void adjust_link(struct net_device *dev)
3010{
3011 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3012 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 3013 unsigned long flags;
3014 struct phy_device *phydev = priv->phydev;
3015 int new_state = 0;
3016
fba4ed03
SG		 3017 local_irq_save(flags);
3018 lock_tx_qs(priv);
3019
bb40dcbb 3020 if (phydev->link) {
23402bdd 3021 u32 tempval1 = gfar_read(&regs->maccfg1);
bb40dcbb 3022 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 3023 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 3024
1da177e4 3025 /* Now we make sure that we can be in full duplex mode.
0977f817
JC		 3026 * If not, we operate in half-duplex mode.
3027 */
bb40dcbb
AF		 3028 if (phydev->duplex != priv->oldduplex) {
3029 new_state = 1;
3030 if (!(phydev->duplex))
1da177e4 3031 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 3032 else
1da177e4 3033 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 3034
bb40dcbb 3035 priv->oldduplex = phydev->duplex;
1da177e4
LT		 3036 }
3037
bb40dcbb
AF		 3038 if (phydev->speed != priv->oldspeed) {
3039 new_state = 1;
3040 switch (phydev->speed) {
1da177e4 3041 case 1000:
1da177e4
LT		 3042 tempval =
3043 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 3044
3045 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 3046 break;
3047 case 100:
3048 case 10:
1da177e4
LT		 3049 tempval =
3050 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 3051
3052 /* Reduced mode distinguishes
0977f817
JC		 3053 * between 10 and 100
3054 */
7f7f5316
AF		 3055 if (phydev->speed == SPEED_100)
3056 ecntrl |= ECNTRL_R100;
3057 else
3058 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 3059 break;
3060 default:
59deab26
JP		 3061 netif_warn(priv, link, dev,
3062 "Ack! Speed (%d) is not 10/100/1000!\n",
3063 phydev->speed);
1da177e4
LT		 3064 break;
3065 }
3066
bb40dcbb 3067 priv->oldspeed = phydev->speed;
1da177e4
LT		 3068 }
3069
23402bdd
CM		 3070 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3071 tempval1 |= gfar_get_flowctrl_cfg(priv);
3072
3073 gfar_write(&regs->maccfg1, tempval1);
bb40dcbb 3074 gfar_write(&regs->maccfg2, tempval);
7f7f5316 3075 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 3076
1da177e4 3077 if (!priv->oldlink) {
bb40dcbb 3078 new_state = 1;
1da177e4 3079 priv->oldlink = 1;
1da177e4 3080 }
bb40dcbb
AF		 3081 } else if (priv->oldlink) {
3082 new_state = 1;
3083 priv->oldlink = 0;
3084 priv->oldspeed = 0;
3085 priv->oldduplex = -1;
1da177e4 3086 }
1da177e4 3087
bb40dcbb
AF		 3088 if (new_state && netif_msg_link(priv))
3089 phy_print_status(phydev);
fba4ed03
SG		 3090 unlock_tx_qs(priv);
3091 local_irq_restore(flags);
bb40dcbb 3092}
1da177e4
LT		 3093
3094/* Update the hash table based on the current list of multicast
3095 * addresses we subscribe to. Also, change the promiscuity of
3096 * the device based on the flags (this function is called
0977f817
JC		 3097 * whenever dev->flags is changed
3098 */
1da177e4
LT		 3099static void gfar_set_multi(struct net_device *dev)
3100{
22bedad3 3101 struct netdev_hw_addr *ha;
1da177e4 3102 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3103 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3104 u32 tempval;
3105
a12f801d 3106 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3107 /* Set RCTRL to PROM */
3108 tempval = gfar_read(&regs->rctrl);
3109 tempval |= RCTRL_PROM;
3110 gfar_write(&regs->rctrl, tempval);
3111 } else {
3112 /* Set RCTRL to not PROM */
3113 tempval = gfar_read(&regs->rctrl);
3114 tempval &= ~(RCTRL_PROM);
3115 gfar_write(&regs->rctrl, tempval);
3116 }
6aa20a22 3117
a12f801d 3118 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3119 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3120 gfar_write(&regs->igaddr0, 0xffffffff);
3121 gfar_write(&regs->igaddr1, 0xffffffff);
3122 gfar_write(&regs->igaddr2, 0xffffffff);
3123 gfar_write(&regs->igaddr3, 0xffffffff);
3124 gfar_write(&regs->igaddr4, 0xffffffff);
3125 gfar_write(&regs->igaddr5, 0xffffffff);
3126 gfar_write(&regs->igaddr6, 0xffffffff);
3127 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3128 gfar_write(&regs->gaddr0, 0xffffffff);
3129 gfar_write(&regs->gaddr1, 0xffffffff);
3130 gfar_write(&regs->gaddr2, 0xffffffff);
3131 gfar_write(&regs->gaddr3, 0xffffffff);
3132 gfar_write(&regs->gaddr4, 0xffffffff);
3133 gfar_write(&regs->gaddr5, 0xffffffff);
3134 gfar_write(&regs->gaddr6, 0xffffffff);
3135 gfar_write(&regs->gaddr7, 0xffffffff);
3136 } else {
7f7f5316
AF		 3137 int em_num;
3138 int idx;
3139
1da177e4 3140 /* zero out the hash */
0bbaf069
KG		 3141 gfar_write(&regs->igaddr0, 0x0);
3142 gfar_write(&regs->igaddr1, 0x0);
3143 gfar_write(&regs->igaddr2, 0x0);
3144 gfar_write(&regs->igaddr3, 0x0);
3145 gfar_write(&regs->igaddr4, 0x0);
3146 gfar_write(&regs->igaddr5, 0x0);
3147 gfar_write(&regs->igaddr6, 0x0);
3148 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3149 gfar_write(&regs->gaddr0, 0x0);
3150 gfar_write(&regs->gaddr1, 0x0);
3151 gfar_write(&regs->gaddr2, 0x0);
3152 gfar_write(&regs->gaddr3, 0x0);
3153 gfar_write(&regs->gaddr4, 0x0);
3154 gfar_write(&regs->gaddr5, 0x0);
3155 gfar_write(&regs->gaddr6, 0x0);
3156 gfar_write(&regs->gaddr7, 0x0);
3157
7f7f5316
AF		 3158 /* If we have extended hash tables, we need to
3159 * clear the exact match registers to prepare for
0977f817
JC		 3160 * setting them
3161 */
7f7f5316
AF		 3162 if (priv->extended_hash) {
3163 em_num = GFAR_EM_NUM + 1;
3164 gfar_clear_exact_match(dev);
3165 idx = 1;
3166 } else {
3167 idx = 0;
3168 em_num = 0;
3169 }
3170
4cd24eaf 3171 if (netdev_mc_empty(dev))
1da177e4
LT		 3172 return;
3173
3174 /* Parse the list, and set the appropriate bits */
22bedad3 3175 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3176 if (idx < em_num) {
22bedad3 3177 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3178 idx++;
3179 } else
22bedad3 3180 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3181 }
3182 }
1da177e4
LT		 3183}
3184
7f7f5316
AF		 3185
3186/* Clears each of the exact match registers to zero, so they
0977f817
JC		 3187 * don't interfere with normal reception
3188 */
7f7f5316
AF		 3189static void gfar_clear_exact_match(struct net_device *dev)
3190{
3191 int idx;
6a3c910c 3192 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316 3193
bc4598bc 3194 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
b6bc7650 3195 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3196}
3197
1da177e4
LT		 3198/* Set the appropriate hash bit for the given addr */
3199/* The algorithm works like so:
3200 * 1) Take the Destination Address (ie the multicast address), and
3201 * do a CRC on it (little endian), and reverse the bits of the
3202 * result.
3203 * 2) Use the 8 most significant bits as a hash into a 256-entry
3204 * table. The table is controlled through 8 32-bit registers:
3205 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3206 * gaddr7. This means that the 3 most significant bits in the
3207 * hash index which gaddr register to use, and the 5 other bits
3208 * indicate which bit (assuming an IBM numbering scheme, which
3209 * for PowerPC (tm) is usually the case) in the register holds
0977f817
JC		 3210 * the entry.
3211 */
1da177e4
LT		 3212static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3213{
3214 u32 tempval;
3215 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3216 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3217 int width = priv->hash_width;
3218 u8 whichbit = (result >> (32 - width)) & 0x1f;
3219 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3220 u32 value = (1 << (31-whichbit));
3221
0bbaf069 3222 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3223 tempval |= value;
0bbaf069 3224 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3225}
3226
7f7f5316
AF		 3227
3228/* There are multiple MAC Address register pairs on some controllers
3229 * This function sets the numth pair to a given address
3230 */
b6bc7650
JP		 3231static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3232 const u8 *addr)
7f7f5316
AF		 3233{
3234 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3235 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3236 int idx;
6a3c910c 3237 char tmpbuf[ETH_ALEN];
7f7f5316 3238 u32 tempval;
f4983704 3239 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3240
3241 macptr += num*2;
3242
0977f817
JC		 3243 /* Now copy it into the mac registers backwards, cuz
3244 * little endian is silly
3245 */
6a3c910c
JP		 3246 for (idx = 0; idx < ETH_ALEN; idx++)
3247 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
7f7f5316
AF		 3248
3249 gfar_write(macptr, *((u32 *) (tmpbuf)));
3250
3251 tempval = *((u32 *) (tmpbuf + 4));
3252
3253 gfar_write(macptr+1, tempval);
3254}
3255
1da177e4 3256/* GFAR error interrupt handler */
f4983704 3257static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3258{
f4983704
SG		 3259 struct gfar_priv_grp *gfargrp = grp_id;
3260 struct gfar __iomem *regs = gfargrp->regs;
3261 struct gfar_private *priv= gfargrp->priv;
3262 struct net_device *dev = priv->ndev;
1da177e4
LT		 3263
3264 /* Save ievent for future reference */
f4983704 3265 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3266
3267 /* Clear IEVENT */
f4983704 3268 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3269
3270 /* Magic Packet is not an error. */
b31a1d8b 3271 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3272 (events & IEVENT_MAG))
3273 events &= ~IEVENT_MAG;
1da177e4
LT		 3274
3275 /* Hmm... */
0bbaf069 3276 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
bc4598bc
JC		 3277 netdev_dbg(dev,
3278 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
59deab26 3279 events, gfar_read(&regs->imask));
1da177e4
LT		 3280
3281 /* Update the error counters */
3282 if (events & IEVENT_TXE) {
09f75cd7 3283 dev->stats.tx_errors++;
1da177e4
LT		 3284
3285 if (events & IEVENT_LC)
09f75cd7 3286 dev->stats.tx_window_errors++;
1da177e4 3287 if (events & IEVENT_CRL)
09f75cd7 3288 dev->stats.tx_aborted_errors++;
1da177e4 3289 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3290 unsigned long flags;
3291
59deab26
JP		 3292 netif_dbg(priv, tx_err, dev,
3293 "TX FIFO underrun, packet dropped\n");
09f75cd7 3294 dev->stats.tx_dropped++;
212079df 3295 atomic64_inc(&priv->extra_stats.tx_underrun);
1da177e4 3296
836cf7fa
AV		 3297 local_irq_save(flags);
3298 lock_tx_qs(priv);
3299
1da177e4 3300 /* Reactivate the Tx Queues */
fba4ed03 3301 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3302
3303 unlock_tx_qs(priv);
3304 local_irq_restore(flags);
1da177e4 3305 }
59deab26 3306 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3307 }
3308 if (events & IEVENT_BSY) {
09f75cd7 3309 dev->stats.rx_errors++;
212079df 3310 atomic64_inc(&priv->extra_stats.rx_bsy);
1da177e4 3311
f4983704 3312 gfar_receive(irq, grp_id);
1da177e4 3313
59deab26
JP		 3314 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3315 gfar_read(&regs->rstat));
1da177e4
LT		 3316 }
3317 if (events & IEVENT_BABR) {
09f75cd7 3318 dev->stats.rx_errors++;
212079df 3319 atomic64_inc(&priv->extra_stats.rx_babr);
1da177e4 3320
59deab26 3321 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3322 }
3323 if (events & IEVENT_EBERR) {
212079df 3324 atomic64_inc(&priv->extra_stats.eberr);
59deab26 3325 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3326 }
59deab26
JP		 3327 if (events & IEVENT_RXC)
3328 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3329
3330 if (events & IEVENT_BABT) {
212079df 3331 atomic64_inc(&priv->extra_stats.tx_babt);
59deab26 3332 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3333 }
3334 return IRQ_HANDLED;
3335}
3336
b31a1d8b
AF		 3337static struct of_device_id gfar_match[] =
3338{
3339 {
3340 .type = "network",
3341 .compatible = "gianfar",
3342 },
46ceb60c
SG		 3343 {
3344 .compatible = "fsl,etsec2",
3345 },
b31a1d8b
AF		 3346 {},
3347};
e72701ac 3348MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3349
1da177e4 3350/* Structure for a device driver */
74888760 3351static struct platform_driver gfar_driver = {
4018294b
GL		 3352 .driver = {
3353 .name = "fsl-gianfar",
3354 .owner = THIS_MODULE,
3355 .pm = GFAR_PM_OPS,
3356 .of_match_table = gfar_match,
3357 },
1da177e4
LT		 3358 .probe = gfar_probe,
3359 .remove = gfar_remove,
3360};
3361
db62f684 3362module_platform_driver(gfar_driver);
Linux 6.x block layer and io_uring tree(s)