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gianfar: Fix warning when CONFIG_PM off
[linux-block.git] / drivers / net / ethernet / freescale / gianfar.c
CommitLineData
0977f817 1/* drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 2 *
3 * Gianfar Ethernet Driver
7f7f5316
AF		 4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
20862788 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
a12f801d 13 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
0bbaf069 27 *
b31a1d8b
AF		 28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
0bbaf069 38 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
bb40dcbb 42 * of frames or amount of time have passed). In NAPI, the
1da177e4 43 * interrupt handler will signal there is work to be done, and
0aa1538f 44 * exit. This method will start at the last known empty
0bbaf069 45 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
59deab26
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
1da177e4 67#include <linux/kernel.h>
1da177e4
LT		 68#include <linux/string.h>
69#include <linux/errno.h>
bb40dcbb 70#include <linux/unistd.h>
1da177e4
LT		 71#include <linux/slab.h>
72#include <linux/interrupt.h>
1da177e4
LT		 73#include <linux/delay.h>
74#include <linux/netdevice.h>
75#include <linux/etherdevice.h>
76#include <linux/skbuff.h>
0bbaf069 77#include <linux/if_vlan.h>
1da177e4
LT		 78#include <linux/spinlock.h>
79#include <linux/mm.h>
5af50730
RH		 80#include <linux/of_address.h>
81#include <linux/of_irq.h>
fe192a49 82#include <linux/of_mdio.h>
b31a1d8b 83#include <linux/of_platform.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
cc772ab7 88#include <linux/net_tstamp.h>
1da177e4
LT		 89
90#include <asm/io.h>
d6ef0bcc 91#ifdef CONFIG_PPC
7d350977 92#include <asm/reg.h>
2969b1f7 93#include <asm/mpc85xx.h>
d6ef0bcc 94#endif
1da177e4
LT		 95#include <asm/irq.h>
96#include <asm/uaccess.h>
97#include <linux/module.h>
1da177e4
LT		 98#include <linux/dma-mapping.h>
99#include <linux/crc32.h>
bb40dcbb
AF		 100#include <linux/mii.h>
101#include <linux/phy.h>
b31a1d8b
AF		 102#include <linux/phy_fixed.h>
103#include <linux/of.h>
4b6ba8aa 104#include <linux/of_net.h>
fd31a952
CM		 105#include <linux/of_address.h>
106#include <linux/of_irq.h>
1da177e4
LT		 107
108#include "gianfar.h"
1da177e4
LT		 109
110#define TX_TIMEOUT (1*HZ)
1da177e4 111
7f7f5316 112const char gfar_driver_version[] = "1.3";
1da177e4 113
1da177e4
LT		 114static int gfar_enet_open(struct net_device *dev);
115static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 116static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 117static void gfar_timeout(struct net_device *dev);
118static int gfar_close(struct net_device *dev);
91c53f76
KH		 119static struct sk_buff *gfar_new_skb(struct net_device *dev,
120 dma_addr_t *bufaddr);
1da177e4
LT		 121static int gfar_set_mac_address(struct net_device *dev);
122static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 123static irqreturn_t gfar_error(int irq, void *dev_id);
124static irqreturn_t gfar_transmit(int irq, void *dev_id);
125static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4 126static void adjust_link(struct net_device *dev);
6ce29b0e 127static noinline void gfar_update_link_state(struct gfar_private *priv);
1da177e4 128static int init_phy(struct net_device *dev);
74888760 129static int gfar_probe(struct platform_device *ofdev);
2dc11581 130static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 131static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 132static void gfar_set_multi(struct net_device *dev);
133static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 134static void gfar_configure_serdes(struct net_device *dev);
aeb12c5e
CM		 135static int gfar_poll_rx(struct napi_struct *napi, int budget);
136static int gfar_poll_tx(struct napi_struct *napi, int budget);
137static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
f2d71c2d
VW		 139#ifdef CONFIG_NET_POLL_CONTROLLER
140static void gfar_netpoll(struct net_device *dev);
141#endif
a12f801d 142int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
c233cf40 143static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
61db26c6
CM		 144static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
145 int amount_pull, struct napi_struct *napi);
c10650b6 146static void gfar_halt_nodisable(struct gfar_private *priv);
7f7f5316 147static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 148static void gfar_set_mac_for_addr(struct net_device *dev, int num,
149 const u8 *addr);
26ccfc37 150static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 151
1da177e4
LT		 152MODULE_AUTHOR("Freescale Semiconductor, Inc");
153MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154MODULE_LICENSE("GPL");
155
a12f801d 156static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 157 dma_addr_t buf)
158{
8a102fe0
AV		 159 u32 lstatus;
160
a7312d58 161 bdp->bufPtr = cpu_to_be32(buf);
8a102fe0
AV		 162
163 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 164 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 165 lstatus |= BD_LFLAG(RXBD_WRAP);
166
d55398ba 167 gfar_wmb();
8a102fe0 168
a7312d58 169 bdp->lstatus = cpu_to_be32(lstatus);
8a102fe0
AV		 170}
171
8728327e 172static int gfar_init_bds(struct net_device *ndev)
826aa4a0 173{
8728327e 174 struct gfar_private *priv = netdev_priv(ndev);
45b679c9 175 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a12f801d
SG		 176 struct gfar_priv_tx_q *tx_queue = NULL;
177 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 178 struct txbd8 *txbdp;
179 struct rxbd8 *rxbdp;
03366a33 180 u32 __iomem *rfbptr;
fba4ed03 181 int i, j;
0a4b5a24 182 dma_addr_t bufaddr;
a12f801d 183
fba4ed03
SG		 184 for (i = 0; i < priv->num_tx_queues; i++) {
185 tx_queue = priv->tx_queue[i];
186 /* Initialize some variables in our dev structure */
187 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
188 tx_queue->dirty_tx = tx_queue->tx_bd_base;
189 tx_queue->cur_tx = tx_queue->tx_bd_base;
190 tx_queue->skb_curtx = 0;
191 tx_queue->skb_dirtytx = 0;
192
193 /* Initialize Transmit Descriptor Ring */
194 txbdp = tx_queue->tx_bd_base;
195 for (j = 0; j < tx_queue->tx_ring_size; j++) {
196 txbdp->lstatus = 0;
197 txbdp->bufPtr = 0;
198 txbdp++;
199 }
8728327e 200
fba4ed03
SG		 201 /* Set the last descriptor in the ring to indicate wrap */
202 txbdp--;
a7312d58
CM		 203 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
204 TXBD_WRAP);
8728327e
AV		 205 }
206
45b679c9 207 rfbptr = &regs->rfbptr0;
fba4ed03
SG		 208 for (i = 0; i < priv->num_rx_queues; i++) {
209 rx_queue = priv->rx_queue[i];
210 rx_queue->cur_rx = rx_queue->rx_bd_base;
211 rx_queue->skb_currx = 0;
212 rxbdp = rx_queue->rx_bd_base;
8728327e 213
fba4ed03
SG		 214 for (j = 0; j < rx_queue->rx_ring_size; j++) {
215 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 216
fba4ed03 217 if (skb) {
a7312d58 218 bufaddr = be32_to_cpu(rxbdp->bufPtr);
fba4ed03 219 } else {
0a4b5a24 220 skb = gfar_new_skb(ndev, &bufaddr);
fba4ed03 221 if (!skb) {
59deab26 222 netdev_err(ndev, "Can't allocate RX buffers\n");
1eb8f7a7 223 return -ENOMEM;
fba4ed03
SG		 224 }
225 rx_queue->rx_skbuff[j] = skb;
8728327e 226 }
8728327e 227
0a4b5a24 228 gfar_init_rxbdp(rx_queue, rxbdp, bufaddr);
fba4ed03 229 rxbdp++;
8728327e
AV		 230 }
231
45b679c9
MP		 232 rx_queue->rfbptr = rfbptr;
233 rfbptr += 2;
8728327e
AV		 234 }
235
236 return 0;
237}
238
239static int gfar_alloc_skb_resources(struct net_device *ndev)
240{
826aa4a0 241 void *vaddr;
fba4ed03
SG		 242 dma_addr_t addr;
243 int i, j, k;
826aa4a0 244 struct gfar_private *priv = netdev_priv(ndev);
369ec162 245 struct device *dev = priv->dev;
a12f801d
SG		 246 struct gfar_priv_tx_q *tx_queue = NULL;
247 struct gfar_priv_rx_q *rx_queue = NULL;
248
fba4ed03
SG		 249 priv->total_tx_ring_size = 0;
250 for (i = 0; i < priv->num_tx_queues; i++)
251 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
252
253 priv->total_rx_ring_size = 0;
254 for (i = 0; i < priv->num_rx_queues; i++)
255 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 256
257 /* Allocate memory for the buffer descriptors */
8728327e 258 vaddr = dma_alloc_coherent(dev,
d0320f75
JP		 259 (priv->total_tx_ring_size *
260 sizeof(struct txbd8)) +
261 (priv->total_rx_ring_size *
262 sizeof(struct rxbd8)),
263 &addr, GFP_KERNEL);
264 if (!vaddr)
826aa4a0 265 return -ENOMEM;
826aa4a0 266
fba4ed03
SG		 267 for (i = 0; i < priv->num_tx_queues; i++) {
268 tx_queue = priv->tx_queue[i];
43d620c8 269 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 270 tx_queue->tx_bd_dma_base = addr;
271 tx_queue->dev = ndev;
272 /* enet DMA only understands physical addresses */
bc4598bc
JC		 273 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
274 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
fba4ed03 275 }
826aa4a0 276
826aa4a0 277 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 278 for (i = 0; i < priv->num_rx_queues; i++) {
279 rx_queue = priv->rx_queue[i];
43d620c8 280 rx_queue->rx_bd_base = vaddr;
fba4ed03
SG		 281 rx_queue->rx_bd_dma_base = addr;
282 rx_queue->dev = ndev;
bc4598bc
JC		 283 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
284 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
fba4ed03 285 }
826aa4a0
AV		 286
287 /* Setup the skbuff rings */
fba4ed03
SG		 288 for (i = 0; i < priv->num_tx_queues; i++) {
289 tx_queue = priv->tx_queue[i];
14f8dc49
JP		 290 tx_queue->tx_skbuff =
291 kmalloc_array(tx_queue->tx_ring_size,
292 sizeof(*tx_queue->tx_skbuff),
293 GFP_KERNEL);
294 if (!tx_queue->tx_skbuff)
fba4ed03 295 goto cleanup;
826aa4a0 296
fba4ed03
SG		 297 for (k = 0; k < tx_queue->tx_ring_size; k++)
298 tx_queue->tx_skbuff[k] = NULL;
299 }
826aa4a0 300
fba4ed03
SG		 301 for (i = 0; i < priv->num_rx_queues; i++) {
302 rx_queue = priv->rx_queue[i];
14f8dc49
JP		 303 rx_queue->rx_skbuff =
304 kmalloc_array(rx_queue->rx_ring_size,
305 sizeof(*rx_queue->rx_skbuff),
306 GFP_KERNEL);
307 if (!rx_queue->rx_skbuff)
fba4ed03 308 goto cleanup;
fba4ed03
SG		 309
310 for (j = 0; j < rx_queue->rx_ring_size; j++)
311 rx_queue->rx_skbuff[j] = NULL;
312 }
826aa4a0 313
8728327e
AV		 314 if (gfar_init_bds(ndev))
315 goto cleanup;
826aa4a0
AV		 316
317 return 0;
318
319cleanup:
320 free_skb_resources(priv);
321 return -ENOMEM;
322}
323
fba4ed03
SG		 324static void gfar_init_tx_rx_base(struct gfar_private *priv)
325{
46ceb60c 326 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 327 u32 __iomem *baddr;
fba4ed03
SG		 328 int i;
329
330 baddr = &regs->tbase0;
bc4598bc 331 for (i = 0; i < priv->num_tx_queues; i++) {
fba4ed03 332 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
bc4598bc 333 baddr += 2;
fba4ed03
SG		 334 }
335
336 baddr = &regs->rbase0;
bc4598bc 337 for (i = 0; i < priv->num_rx_queues; i++) {
fba4ed03 338 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
bc4598bc 339 baddr += 2;
fba4ed03
SG		 340 }
341}
342
45b679c9
MP		 343static void gfar_init_rqprm(struct gfar_private *priv)
344{
345 struct gfar __iomem *regs = priv->gfargrp[0].regs;
346 u32 __iomem *baddr;
347 int i;
348
349 baddr = &regs->rqprm0;
350 for (i = 0; i < priv->num_rx_queues; i++) {
351 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
352 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
353 baddr++;
354 }
355}
356
88302648 357static void gfar_rx_buff_size_config(struct gfar_private *priv)
826aa4a0 358{
f5b720b8 359 int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN;
fba4ed03 360
ba779711
CM		 361 /* set this when rx hw offload (TOE) functions are being used */
362 priv->uses_rxfcb = 0;
363
88302648
CM		 364 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
365 priv->uses_rxfcb = 1;
366
367 if (priv->hwts_rx_en)
368 priv->uses_rxfcb = 1;
369
370 if (priv->uses_rxfcb)
371 frame_size += GMAC_FCB_LEN;
372
373 frame_size += priv->padding;
374
375 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
376 INCREMENTAL_BUFFER_SIZE;
377
378 priv->rx_buffer_size = frame_size;
379}
380
381static void gfar_mac_rx_config(struct gfar_private *priv)
382{
383 struct gfar __iomem *regs = priv->gfargrp[0].regs;
384 u32 rctrl = 0;
385
1ccb8389 386 if (priv->rx_filer_enable) {
fba4ed03 387 rctrl |= RCTRL_FILREN;
1ccb8389 388 /* Program the RIR0 reg with the required distribution */
71ff9e3d
CM		 389 if (priv->poll_mode == GFAR_SQ_POLLING)
390 gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
391 else /* GFAR_MQ_POLLING */
392 gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
1ccb8389 393 }
826aa4a0 394
f5ae6279 395 /* Restore PROMISC mode */
a328ac92 396 if (priv->ndev->flags & IFF_PROMISC)
f5ae6279
CM		 397 rctrl |= RCTRL_PROM;
398
88302648 399 if (priv->ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 400 rctrl |= RCTRL_CHECKSUMMING;
401
88302648
CM		 402 if (priv->extended_hash)
403 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
826aa4a0
AV		 404
405 if (priv->padding) {
406 rctrl &= ~RCTRL_PAL_MASK;
407 rctrl |= RCTRL_PADDING(priv->padding);
408 }
409
97553f7f 410 /* Enable HW time stamping if requested from user space */
88302648 411 if (priv->hwts_rx_en)
97553f7f
MR		 412 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
413
88302648 414 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
b852b720 415 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
826aa4a0 416
45b679c9
MP		 417 /* Clear the LFC bit */
418 gfar_write(&regs->rctrl, rctrl);
419 /* Init flow control threshold values */
420 gfar_init_rqprm(priv);
421 gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
422 rctrl |= RCTRL_LFC;
423
826aa4a0
AV		 424 /* Init rctrl based on our settings */
425 gfar_write(&regs->rctrl, rctrl);
a328ac92 426}
826aa4a0 427
a328ac92
CM		 428static void gfar_mac_tx_config(struct gfar_private *priv)
429{
430 struct gfar __iomem *regs = priv->gfargrp[0].regs;
431 u32 tctrl = 0;
432
433 if (priv->ndev->features & NETIF_F_IP_CSUM)
826aa4a0
AV		 434 tctrl |= TCTRL_INIT_CSUM;
435
b98b8bab
CM		 436 if (priv->prio_sched_en)
437 tctrl |= TCTRL_TXSCHED_PRIO;
438 else {
439 tctrl |= TCTRL_TXSCHED_WRRS;
440 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
441 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
442 }
fba4ed03 443
88302648
CM		 444 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
445 tctrl |= TCTRL_VLINS;
446
826aa4a0 447 gfar_write(&regs->tctrl, tctrl);
826aa4a0
AV		 448}
449
f19015ba
CM		 450static void gfar_configure_coalescing(struct gfar_private *priv,
451 unsigned long tx_mask, unsigned long rx_mask)
452{
453 struct gfar __iomem *regs = priv->gfargrp[0].regs;
454 u32 __iomem *baddr;
455
456 if (priv->mode == MQ_MG_MODE) {
457 int i = 0;
458
459 baddr = &regs->txic0;
460 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
461 gfar_write(baddr + i, 0);
462 if (likely(priv->tx_queue[i]->txcoalescing))
463 gfar_write(baddr + i, priv->tx_queue[i]->txic);
464 }
465
466 baddr = &regs->rxic0;
467 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
468 gfar_write(baddr + i, 0);
469 if (likely(priv->rx_queue[i]->rxcoalescing))
470 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
471 }
472 } else {
473 /* Backward compatible case -- even if we enable
474 * multiple queues, there's only single reg to program
475 */
476 gfar_write(&regs->txic, 0);
477 if (likely(priv->tx_queue[0]->txcoalescing))
478 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
479
480 gfar_write(&regs->rxic, 0);
481 if (unlikely(priv->rx_queue[0]->rxcoalescing))
482 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
483 }
484}
485
486void gfar_configure_coalescing_all(struct gfar_private *priv)
487{
488 gfar_configure_coalescing(priv, 0xFF, 0xFF);
489}
490
a7f38041
SG		 491static struct net_device_stats *gfar_get_stats(struct net_device *dev)
492{
493 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 494 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
495 unsigned long tx_packets = 0, tx_bytes = 0;
3a2e16c8 496 int i;
a7f38041
SG		 497
498 for (i = 0; i < priv->num_rx_queues; i++) {
499 rx_packets += priv->rx_queue[i]->stats.rx_packets;
bc4598bc 500 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
a7f38041
SG		 501 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
502 }
503
504 dev->stats.rx_packets = rx_packets;
bc4598bc 505 dev->stats.rx_bytes = rx_bytes;
a7f38041
SG		 506 dev->stats.rx_dropped = rx_dropped;
507
508 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 509 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
510 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 511 }
512
bc4598bc 513 dev->stats.tx_bytes = tx_bytes;
a7f38041
SG		 514 dev->stats.tx_packets = tx_packets;
515
516 return &dev->stats;
517}
518
3d23a05c
CM		 519static int gfar_set_mac_addr(struct net_device *dev, void *p)
520{
521 eth_mac_addr(dev, p);
522
523 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
524
525 return 0;
526}
527
26ccfc37
AF		 528static const struct net_device_ops gfar_netdev_ops = {
529 .ndo_open = gfar_enet_open,
530 .ndo_start_xmit = gfar_start_xmit,
531 .ndo_stop = gfar_close,
532 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 533 .ndo_set_features = gfar_set_features,
afc4b13d 534 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 535 .ndo_tx_timeout = gfar_timeout,
536 .ndo_do_ioctl = gfar_ioctl,
a7f38041 537 .ndo_get_stats = gfar_get_stats,
3d23a05c 538 .ndo_set_mac_address = gfar_set_mac_addr,
240c102d 539 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 540#ifdef CONFIG_NET_POLL_CONTROLLER
541 .ndo_poll_controller = gfar_netpoll,
542#endif
543};
544
efeddce7
CM		 545static void gfar_ints_disable(struct gfar_private *priv)
546{
547 int i;
548 for (i = 0; i < priv->num_grps; i++) {
549 struct gfar __iomem *regs = priv->gfargrp[i].regs;
550 /* Clear IEVENT */
551 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
552
553 /* Initialize IMASK */
554 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
555 }
556}
557
558static void gfar_ints_enable(struct gfar_private *priv)
559{
560 int i;
561 for (i = 0; i < priv->num_grps; i++) {
562 struct gfar __iomem *regs = priv->gfargrp[i].regs;
563 /* Unmask the interrupts we look for */
564 gfar_write(&regs->imask, IMASK_DEFAULT);
565 }
566}
567
84868305 568#ifdef CONFIG_PM
91c53f76 569static void lock_tx_qs(struct gfar_private *priv)
fba4ed03 570{
3a2e16c8 571 int i;
fba4ed03
SG		 572
573 for (i = 0; i < priv->num_tx_queues; i++)
574 spin_lock(&priv->tx_queue[i]->txlock);
575}
576
91c53f76 577static void unlock_tx_qs(struct gfar_private *priv)
fba4ed03 578{
3a2e16c8 579 int i;
fba4ed03
SG		 580
581 for (i = 0; i < priv->num_tx_queues; i++)
582 spin_unlock(&priv->tx_queue[i]->txlock);
583}
84868305 584#endif
fba4ed03 585
20862788
CM		 586static int gfar_alloc_tx_queues(struct gfar_private *priv)
587{
588 int i;
589
590 for (i = 0; i < priv->num_tx_queues; i++) {
591 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
592 GFP_KERNEL);
593 if (!priv->tx_queue[i])
594 return -ENOMEM;
595
596 priv->tx_queue[i]->tx_skbuff = NULL;
597 priv->tx_queue[i]->qindex = i;
598 priv->tx_queue[i]->dev = priv->ndev;
599 spin_lock_init(&(priv->tx_queue[i]->txlock));
600 }
601 return 0;
602}
603
604static int gfar_alloc_rx_queues(struct gfar_private *priv)
605{
606 int i;
607
608 for (i = 0; i < priv->num_rx_queues; i++) {
609 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
610 GFP_KERNEL);
611 if (!priv->rx_queue[i])
612 return -ENOMEM;
613
614 priv->rx_queue[i]->rx_skbuff = NULL;
615 priv->rx_queue[i]->qindex = i;
616 priv->rx_queue[i]->dev = priv->ndev;
20862788
CM		 617 }
618 return 0;
619}
620
621static void gfar_free_tx_queues(struct gfar_private *priv)
fba4ed03 622{
3a2e16c8 623 int i;
fba4ed03
SG		 624
625 for (i = 0; i < priv->num_tx_queues; i++)
626 kfree(priv->tx_queue[i]);
627}
628
20862788 629static void gfar_free_rx_queues(struct gfar_private *priv)
fba4ed03 630{
3a2e16c8 631 int i;
fba4ed03
SG		 632
633 for (i = 0; i < priv->num_rx_queues; i++)
634 kfree(priv->rx_queue[i]);
635}
636
46ceb60c
SG		 637static void unmap_group_regs(struct gfar_private *priv)
638{
3a2e16c8 639 int i;
46ceb60c
SG		 640
641 for (i = 0; i < MAXGROUPS; i++)
642 if (priv->gfargrp[i].regs)
643 iounmap(priv->gfargrp[i].regs);
644}
645
ee873fda
CM		 646static void free_gfar_dev(struct gfar_private *priv)
647{
648 int i, j;
649
650 for (i = 0; i < priv->num_grps; i++)
651 for (j = 0; j < GFAR_NUM_IRQS; j++) {
652 kfree(priv->gfargrp[i].irqinfo[j]);
653 priv->gfargrp[i].irqinfo[j] = NULL;
654 }
655
656 free_netdev(priv->ndev);
657}
658
46ceb60c
SG		 659static void disable_napi(struct gfar_private *priv)
660{
3a2e16c8 661 int i;
46ceb60c 662
aeb12c5e
CM		 663 for (i = 0; i < priv->num_grps; i++) {
664 napi_disable(&priv->gfargrp[i].napi_rx);
665 napi_disable(&priv->gfargrp[i].napi_tx);
666 }
46ceb60c
SG		 667}
668
669static void enable_napi(struct gfar_private *priv)
670{
3a2e16c8 671 int i;
46ceb60c 672
aeb12c5e
CM		 673 for (i = 0; i < priv->num_grps; i++) {
674 napi_enable(&priv->gfargrp[i].napi_rx);
675 napi_enable(&priv->gfargrp[i].napi_tx);
676 }
46ceb60c
SG		 677}
678
679static int gfar_parse_group(struct device_node *np,
bc4598bc 680 struct gfar_private *priv, const char *model)
46ceb60c 681{
5fedcc14 682 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
ee873fda
CM		 683 int i;
684
7c1e7e99
PG		 685 for (i = 0; i < GFAR_NUM_IRQS; i++) {
686 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
687 GFP_KERNEL);
688 if (!grp->irqinfo[i])
ee873fda 689 return -ENOMEM;
ee873fda 690 }
46ceb60c 691
5fedcc14
CM		 692 grp->regs = of_iomap(np, 0);
693 if (!grp->regs)
46ceb60c
SG		 694 return -ENOMEM;
695
ee873fda 696 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
46ceb60c
SG		 697
698 /* If we aren't the FEC we have multiple interrupts */
699 if (model && strcasecmp(model, "FEC")) {
ee873fda
CM		 700 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
701 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
702 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
703 gfar_irq(grp, RX)->irq == NO_IRQ ||
704 gfar_irq(grp, ER)->irq == NO_IRQ)
46ceb60c 705 return -EINVAL;
46ceb60c
SG		 706 }
707
5fedcc14
CM		 708 grp->priv = priv;
709 spin_lock_init(&grp->grplock);
bc4598bc 710 if (priv->mode == MQ_MG_MODE) {
55917641
JL		 711 u32 rxq_mask, txq_mask;
712 int ret;
713
714 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
715 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
716
717 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
718 if (!ret) {
719 grp->rx_bit_map = rxq_mask ?
720 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
721 }
722
723 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
724 if (!ret) {
725 grp->tx_bit_map = txq_mask ?
726 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
727 }
71ff9e3d
CM		 728
729 if (priv->poll_mode == GFAR_SQ_POLLING) {
730 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
731 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
732 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
71ff9e3d 733 }
46ceb60c 734 } else {
5fedcc14
CM		 735 grp->rx_bit_map = 0xFF;
736 grp->tx_bit_map = 0xFF;
46ceb60c 737 }
20862788
CM		 738
739 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
740 * right to left, so we need to revert the 8 bits to get the q index
741 */
742 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
743 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
744
745 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
746 * also assign queues to groups
747 */
748 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
71ff9e3d
CM		 749 if (!grp->rx_queue)
750 grp->rx_queue = priv->rx_queue[i];
20862788
CM		 751 grp->num_rx_queues++;
752 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
753 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
754 priv->rx_queue[i]->grp = grp;
755 }
756
757 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
71ff9e3d
CM		 758 if (!grp->tx_queue)
759 grp->tx_queue = priv->tx_queue[i];
20862788
CM		 760 grp->num_tx_queues++;
761 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
762 priv->tqueue |= (TQUEUE_EN0 >> i);
763 priv->tx_queue[i]->grp = grp;
764 }
765
46ceb60c
SG		 766 priv->num_grps++;
767
768 return 0;
769}
770
f50724cd
TW		 771static int gfar_of_group_count(struct device_node *np)
772{
773 struct device_node *child;
774 int num = 0;
775
776 for_each_available_child_of_node(np, child)
777 if (!of_node_cmp(child->name, "queue-group"))
778 num++;
779
780 return num;
781}
782
2dc11581 783static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 784{
b31a1d8b
AF		 785 const char *model;
786 const char *ctype;
787 const void *mac_addr;
fba4ed03
SG		 788 int err = 0, i;
789 struct net_device *dev = NULL;
790 struct gfar_private *priv = NULL;
61c7a080 791 struct device_node *np = ofdev->dev.of_node;
46ceb60c 792 struct device_node *child = NULL;
55917641
JL		 793 struct property *stash;
794 u32 stash_len = 0;
795 u32 stash_idx = 0;
fba4ed03 796 unsigned int num_tx_qs, num_rx_qs;
b338ce27 797 unsigned short mode, poll_mode;
b31a1d8b 798
4b222ca6 799 if (!np)
b31a1d8b
AF		 800 return -ENODEV;
801
b338ce27
CM		 802 if (of_device_is_compatible(np, "fsl,etsec2")) {
803 mode = MQ_MG_MODE;
804 poll_mode = GFAR_SQ_POLLING;
805 } else {
806 mode = SQ_SG_MODE;
807 poll_mode = GFAR_SQ_POLLING;
808 }
809
b338ce27 810 if (mode == SQ_SG_MODE) {
71ff9e3d
CM		 811 num_tx_qs = 1;
812 num_rx_qs = 1;
813 } else { /* MQ_MG_MODE */
c65d7533 814 /* get the actual number of supported groups */
f50724cd 815 unsigned int num_grps = gfar_of_group_count(np);
c65d7533
CM		 816
817 if (num_grps == 0 || num_grps > MAXGROUPS) {
818 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
819 num_grps);
820 pr_err("Cannot do alloc_etherdev, aborting\n");
821 return -EINVAL;
822 }
823
b338ce27 824 if (poll_mode == GFAR_SQ_POLLING) {
c65d7533
CM		 825 num_tx_qs = num_grps; /* one txq per int group */
826 num_rx_qs = num_grps; /* one rxq per int group */
71ff9e3d 827 } else { /* GFAR_MQ_POLLING */
55917641
JL		 828 u32 tx_queues, rx_queues;
829 int ret;
830
831 /* parse the num of HW tx and rx queues */
832 ret = of_property_read_u32(np, "fsl,num_tx_queues",
833 &tx_queues);
834 num_tx_qs = ret ? 1 : tx_queues;
835
836 ret = of_property_read_u32(np, "fsl,num_rx_queues",
837 &rx_queues);
838 num_rx_qs = ret ? 1 : rx_queues;
71ff9e3d
CM		 839 }
840 }
fba4ed03
SG		 841
842 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 843 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
844 num_tx_qs, MAX_TX_QS);
845 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 846 return -EINVAL;
847 }
848
fba4ed03 849 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 850 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
851 num_rx_qs, MAX_RX_QS);
852 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 853 return -EINVAL;
854 }
855
856 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
857 dev = *pdev;
858 if (NULL == dev)
859 return -ENOMEM;
860
861 priv = netdev_priv(dev);
fba4ed03
SG		 862 priv->ndev = dev;
863
b338ce27
CM		 864 priv->mode = mode;
865 priv->poll_mode = poll_mode;
866
fba4ed03 867 priv->num_tx_queues = num_tx_qs;
fe069123 868 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 869 priv->num_rx_queues = num_rx_qs;
20862788
CM		 870
871 err = gfar_alloc_tx_queues(priv);
872 if (err)
873 goto tx_alloc_failed;
874
875 err = gfar_alloc_rx_queues(priv);
876 if (err)
877 goto rx_alloc_failed;
b31a1d8b 878
55917641
JL		 879 err = of_property_read_string(np, "model", &model);
880 if (err) {
881 pr_err("Device model property missing, aborting\n");
882 goto rx_alloc_failed;
883 }
884
0977f817 885 /* Init Rx queue filer rule set linked list */
4aa3a715
SP		 886 INIT_LIST_HEAD(&priv->rx_list.list);
887 priv->rx_list.count = 0;
888 mutex_init(&priv->rx_queue_access);
889
46ceb60c
SG		 890 for (i = 0; i < MAXGROUPS; i++)
891 priv->gfargrp[i].regs = NULL;
b31a1d8b 892
46ceb60c 893 /* Parse and initialize group specific information */
b338ce27 894 if (priv->mode == MQ_MG_MODE) {
f50724cd
TW		 895 for_each_available_child_of_node(np, child) {
896 if (of_node_cmp(child->name, "queue-group"))
897 continue;
898
46ceb60c
SG		 899 err = gfar_parse_group(child, priv, model);
900 if (err)
901 goto err_grp_init;
b31a1d8b 902 }
b338ce27 903 } else { /* SQ_SG_MODE */
46ceb60c 904 err = gfar_parse_group(np, priv, model);
bc4598bc 905 if (err)
46ceb60c 906 goto err_grp_init;
b31a1d8b
AF		 907 }
908
55917641 909 stash = of_find_property(np, "bd-stash", NULL);
4d7902f2 910
a12f801d 911 if (stash) {
4d7902f2
AF		 912 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
913 priv->bd_stash_en = 1;
914 }
915
55917641 916 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
4d7902f2 917
55917641
JL		 918 if (err == 0)
919 priv->rx_stash_size = stash_len;
4d7902f2 920
55917641 921 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
4d7902f2 922
55917641
JL		 923 if (err == 0)
924 priv->rx_stash_index = stash_idx;
4d7902f2
AF		 925
926 if (stash_len || stash_idx)
927 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
928
b31a1d8b 929 mac_addr = of_get_mac_address(np);
bc4598bc 930
b31a1d8b 931 if (mac_addr)
6a3c910c 932 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 933
934 if (model && !strcasecmp(model, "TSEC"))
34018fd4 935 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 936 FSL_GIANFAR_DEV_HAS_COALESCE |
937 FSL_GIANFAR_DEV_HAS_RMON |
938 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
939
b31a1d8b 940 if (model && !strcasecmp(model, "eTSEC"))
34018fd4 941 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 942 FSL_GIANFAR_DEV_HAS_COALESCE |
943 FSL_GIANFAR_DEV_HAS_RMON |
944 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
bc4598bc
JC		 945 FSL_GIANFAR_DEV_HAS_CSUM |
946 FSL_GIANFAR_DEV_HAS_VLAN |
947 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
948 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
949 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b 950
55917641 951 err = of_property_read_string(np, "phy-connection-type", &ctype);
b31a1d8b
AF		 952
953 /* We only care about rgmii-id. The rest are autodetected */
55917641 954 if (err == 0 && !strcmp(ctype, "rgmii-id"))
b31a1d8b
AF		 955 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
956 else
957 priv->interface = PHY_INTERFACE_MODE_MII;
958
55917641 959 if (of_find_property(np, "fsl,magic-packet", NULL))
b31a1d8b
AF		 960 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
961
fe192a49 962 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b 963
be403645
FF		 964 /* In the case of a fixed PHY, the DT node associated
965 * to the PHY is the Ethernet MAC DT node.
966 */
6f2c9bd8 967 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
be403645
FF		 968 err = of_phy_register_fixed_link(np);
969 if (err)
970 goto err_grp_init;
971
6f2c9bd8 972 priv->phy_node = of_node_get(np);
be403645
FF		 973 }
974
b31a1d8b 975 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 976 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 977
978 return 0;
979
46ceb60c
SG		 980err_grp_init:
981 unmap_group_regs(priv);
20862788
CM		 982rx_alloc_failed:
983 gfar_free_rx_queues(priv);
984tx_alloc_failed:
985 gfar_free_tx_queues(priv);
ee873fda 986 free_gfar_dev(priv);
b31a1d8b
AF		 987 return err;
988}
989
ca0c88c2 990static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
cc772ab7
MR		 991{
992 struct hwtstamp_config config;
993 struct gfar_private *priv = netdev_priv(netdev);
994
995 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
996 return -EFAULT;
997
998 /* reserved for future extensions */
999 if (config.flags)
1000 return -EINVAL;
1001
f0ee7acf
MR		 1002 switch (config.tx_type) {
1003 case HWTSTAMP_TX_OFF:
1004 priv->hwts_tx_en = 0;
1005 break;
1006 case HWTSTAMP_TX_ON:
1007 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
1008 return -ERANGE;
1009 priv->hwts_tx_en = 1;
1010 break;
1011 default:
cc772ab7 1012 return -ERANGE;
f0ee7acf 1013 }
cc772ab7
MR		 1014
1015 switch (config.rx_filter) {
1016 case HWTSTAMP_FILTER_NONE:
97553f7f 1017 if (priv->hwts_rx_en) {
97553f7f 1018 priv->hwts_rx_en = 0;
0851133b 1019 reset_gfar(netdev);
97553f7f 1020 }
cc772ab7
MR		 1021 break;
1022 default:
1023 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
1024 return -ERANGE;
97553f7f 1025 if (!priv->hwts_rx_en) {
97553f7f 1026 priv->hwts_rx_en = 1;
0851133b 1027 reset_gfar(netdev);
97553f7f 1028 }
cc772ab7
MR		 1029 config.rx_filter = HWTSTAMP_FILTER_ALL;
1030 break;
1031 }
1032
1033 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1034 -EFAULT : 0;
1035}
1036
ca0c88c2
BH		 1037static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
1038{
1039 struct hwtstamp_config config;
1040 struct gfar_private *priv = netdev_priv(netdev);
1041
1042 config.flags = 0;
1043 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1044 config.rx_filter = (priv->hwts_rx_en ?
1045 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1046
1047 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1048 -EFAULT : 0;
1049}
1050
0faac9f7
CW		 1051static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1052{
1053 struct gfar_private *priv = netdev_priv(dev);
1054
1055 if (!netif_running(dev))
1056 return -EINVAL;
1057
cc772ab7 1058 if (cmd == SIOCSHWTSTAMP)
ca0c88c2
BH		 1059 return gfar_hwtstamp_set(dev, rq);
1060 if (cmd == SIOCGHWTSTAMP)
1061 return gfar_hwtstamp_get(dev, rq);
cc772ab7 1062
0faac9f7
CW		 1063 if (!priv->phydev)
1064 return -ENODEV;
1065
28b04113 1066 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 1067}
1068
18294ad1
AV		 1069static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1070 u32 class)
7a8b3372
SG		 1071{
1072 u32 rqfpr = FPR_FILER_MASK;
1073 u32 rqfcr = 0x0;
1074
1075 rqfar--;
1076 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 1077 priv->ftp_rqfpr[rqfar] = rqfpr;
1078 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 1079 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1080
1081 rqfar--;
1082 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 1083 priv->ftp_rqfpr[rqfar] = rqfpr;
1084 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 1085 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1086
1087 rqfar--;
1088 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1089 rqfpr = class;
6c43e046
WJB		 1090 priv->ftp_rqfcr[rqfar] = rqfcr;
1091 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1092 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1093
1094 rqfar--;
1095 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1096 rqfpr = class;
6c43e046
WJB		 1097 priv->ftp_rqfcr[rqfar] = rqfcr;
1098 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1099 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1100
1101 return rqfar;
1102}
1103
1104static void gfar_init_filer_table(struct gfar_private *priv)
1105{
1106 int i = 0x0;
1107 u32 rqfar = MAX_FILER_IDX;
1108 u32 rqfcr = 0x0;
1109 u32 rqfpr = FPR_FILER_MASK;
1110
1111 /* Default rule */
1112 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 1113 priv->ftp_rqfcr[rqfar] = rqfcr;
1114 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1115 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1116
1117 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1118 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1119 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1120 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1121 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1122 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1123
85dd08eb 1124 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 1125 priv->cur_filer_idx = rqfar;
1126
1127 /* Rest are masked rules */
1128 rqfcr = RQFCR_CMP_NOMATCH;
1129 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 1130 priv->ftp_rqfcr[i] = rqfcr;
1131 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 1132 gfar_write_filer(priv, i, rqfcr, rqfpr);
1133 }
1134}
1135
d6ef0bcc 1136#ifdef CONFIG_PPC
2969b1f7 1137static void __gfar_detect_errata_83xx(struct gfar_private *priv)
7d350977 1138{
7d350977
AV		 1139 unsigned int pvr = mfspr(SPRN_PVR);
1140 unsigned int svr = mfspr(SPRN_SVR);
1141 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1142 unsigned int rev = svr & 0xffff;
1143
1144 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1145 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
bc4598bc 1146 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
7d350977
AV		 1147 priv->errata |= GFAR_ERRATA_74;
1148
deb90eac
AV		 1149 /* MPC8313 and MPC837x all rev */
1150 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 1151 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
deb90eac
AV		 1152 priv->errata |= GFAR_ERRATA_76;
1153
2969b1f7
CM		 1154 /* MPC8313 Rev < 2.0 */
1155 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1156 priv->errata |= GFAR_ERRATA_12;
1157}
1158
1159static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1160{
1161 unsigned int svr = mfspr(SPRN_SVR);
1162
1163 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
4363c2fd 1164 priv->errata |= GFAR_ERRATA_12;
53fad773
CM		 1165 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1166 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1167 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
2969b1f7 1168}
d6ef0bcc 1169#endif
2969b1f7
CM		 1170
1171static void gfar_detect_errata(struct gfar_private *priv)
1172{
1173 struct device *dev = &priv->ofdev->dev;
1174
1175 /* no plans to fix */
1176 priv->errata |= GFAR_ERRATA_A002;
1177
d6ef0bcc 1178#ifdef CONFIG_PPC
2969b1f7
CM		 1179 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1180 __gfar_detect_errata_85xx(priv);
1181 else /* non-mpc85xx parts, i.e. e300 core based */
1182 __gfar_detect_errata_83xx(priv);
d6ef0bcc 1183#endif
4363c2fd 1184
7d350977
AV		 1185 if (priv->errata)
1186 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1187 priv->errata);
1188}
1189
0851133b 1190void gfar_mac_reset(struct gfar_private *priv)
20862788
CM		 1191{
1192 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a328ac92 1193 u32 tempval;
20862788
CM		 1194
1195 /* Reset MAC layer */
1196 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1197
1198 /* We need to delay at least 3 TX clocks */
a328ac92 1199 udelay(3);
20862788
CM		 1200
1201 /* the soft reset bit is not self-resetting, so we need to
1202 * clear it before resuming normal operation
1203 */
1204 gfar_write(&regs->maccfg1, 0);
1205
a328ac92
CM		 1206 udelay(3);
1207
88302648
CM		 1208 /* Compute rx_buff_size based on config flags */
1209 gfar_rx_buff_size_config(priv);
1210
1211 /* Initialize the max receive frame/buffer lengths */
1212 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
a328ac92
CM		 1213 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1214
1215 /* Initialize the Minimum Frame Length Register */
1216 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1217
20862788
CM		 1218 /* Initialize MACCFG2. */
1219 tempval = MACCFG2_INIT_SETTINGS;
88302648
CM		 1220
1221 /* If the mtu is larger than the max size for standard
1222 * ethernet frames (ie, a jumbo frame), then set maccfg2
1223 * to allow huge frames, and to check the length
1224 */
1225 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1226 gfar_has_errata(priv, GFAR_ERRATA_74))
20862788 1227 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
88302648 1228
20862788
CM		 1229 gfar_write(&regs->maccfg2, tempval);
1230
a328ac92
CM		 1231 /* Clear mac addr hash registers */
1232 gfar_write(&regs->igaddr0, 0);
1233 gfar_write(&regs->igaddr1, 0);
1234 gfar_write(&regs->igaddr2, 0);
1235 gfar_write(&regs->igaddr3, 0);
1236 gfar_write(&regs->igaddr4, 0);
1237 gfar_write(&regs->igaddr5, 0);
1238 gfar_write(&regs->igaddr6, 0);
1239 gfar_write(&regs->igaddr7, 0);
1240
1241 gfar_write(&regs->gaddr0, 0);
1242 gfar_write(&regs->gaddr1, 0);
1243 gfar_write(&regs->gaddr2, 0);
1244 gfar_write(&regs->gaddr3, 0);
1245 gfar_write(&regs->gaddr4, 0);
1246 gfar_write(&regs->gaddr5, 0);
1247 gfar_write(&regs->gaddr6, 0);
1248 gfar_write(&regs->gaddr7, 0);
1249
1250 if (priv->extended_hash)
1251 gfar_clear_exact_match(priv->ndev);
1252
1253 gfar_mac_rx_config(priv);
1254
1255 gfar_mac_tx_config(priv);
1256
1257 gfar_set_mac_address(priv->ndev);
1258
1259 gfar_set_multi(priv->ndev);
1260
1261 /* clear ievent and imask before configuring coalescing */
1262 gfar_ints_disable(priv);
1263
1264 /* Configure the coalescing support */
1265 gfar_configure_coalescing_all(priv);
1266}
1267
1268static void gfar_hw_init(struct gfar_private *priv)
1269{
1270 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1271 u32 attrs;
1272
1273 /* Stop the DMA engine now, in case it was running before
1274 * (The firmware could have used it, and left it running).
1275 */
1276 gfar_halt(priv);
1277
1278 gfar_mac_reset(priv);
1279
1280 /* Zero out the rmon mib registers if it has them */
1281 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1282 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1283
1284 /* Mask off the CAM interrupts */
1285 gfar_write(&regs->rmon.cam1, 0xffffffff);
1286 gfar_write(&regs->rmon.cam2, 0xffffffff);
1287 }
1288
20862788
CM		 1289 /* Initialize ECNTRL */
1290 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1291
34018fd4
CM		 1292 /* Set the extraction length and index */
1293 attrs = ATTRELI_EL(priv->rx_stash_size) |
1294 ATTRELI_EI(priv->rx_stash_index);
1295
1296 gfar_write(&regs->attreli, attrs);
1297
1298 /* Start with defaults, and add stashing
1299 * depending on driver parameters
1300 */
1301 attrs = ATTR_INIT_SETTINGS;
1302
1303 if (priv->bd_stash_en)
1304 attrs |= ATTR_BDSTASH;
1305
1306 if (priv->rx_stash_size != 0)
1307 attrs |= ATTR_BUFSTASH;
1308
1309 gfar_write(&regs->attr, attrs);
1310
1311 /* FIFO configs */
1312 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1313 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1314 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1315
20862788
CM		 1316 /* Program the interrupt steering regs, only for MG devices */
1317 if (priv->num_grps > 1)
1318 gfar_write_isrg(priv);
20862788
CM		 1319}
1320
898157ed 1321static void gfar_init_addr_hash_table(struct gfar_private *priv)
20862788
CM		 1322{
1323 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1324
1325 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1326 priv->extended_hash = 1;
1327 priv->hash_width = 9;
1328
1329 priv->hash_regs[0] = &regs->igaddr0;
1330 priv->hash_regs[1] = &regs->igaddr1;
1331 priv->hash_regs[2] = &regs->igaddr2;
1332 priv->hash_regs[3] = &regs->igaddr3;
1333 priv->hash_regs[4] = &regs->igaddr4;
1334 priv->hash_regs[5] = &regs->igaddr5;
1335 priv->hash_regs[6] = &regs->igaddr6;
1336 priv->hash_regs[7] = &regs->igaddr7;
1337 priv->hash_regs[8] = &regs->gaddr0;
1338 priv->hash_regs[9] = &regs->gaddr1;
1339 priv->hash_regs[10] = &regs->gaddr2;
1340 priv->hash_regs[11] = &regs->gaddr3;
1341 priv->hash_regs[12] = &regs->gaddr4;
1342 priv->hash_regs[13] = &regs->gaddr5;
1343 priv->hash_regs[14] = &regs->gaddr6;
1344 priv->hash_regs[15] = &regs->gaddr7;
1345
1346 } else {
1347 priv->extended_hash = 0;
1348 priv->hash_width = 8;
1349
1350 priv->hash_regs[0] = &regs->gaddr0;
1351 priv->hash_regs[1] = &regs->gaddr1;
1352 priv->hash_regs[2] = &regs->gaddr2;
1353 priv->hash_regs[3] = &regs->gaddr3;
1354 priv->hash_regs[4] = &regs->gaddr4;
1355 priv->hash_regs[5] = &regs->gaddr5;
1356 priv->hash_regs[6] = &regs->gaddr6;
1357 priv->hash_regs[7] = &regs->gaddr7;
1358 }
1359}
1360
bb40dcbb 1361/* Set up the ethernet device structure, private data,
0977f817
JC		 1362 * and anything else we need before we start
1363 */
74888760 1364static int gfar_probe(struct platform_device *ofdev)
1da177e4 1365{
1da177e4
LT		 1366 struct net_device *dev = NULL;
1367 struct gfar_private *priv = NULL;
20862788 1368 int err = 0, i;
1da177e4 1369
fba4ed03 1370 err = gfar_of_init(ofdev, &dev);
1da177e4 1371
fba4ed03
SG		 1372 if (err)
1373 return err;
1da177e4
LT		 1374
1375 priv = netdev_priv(dev);
4826857f
KG		 1376 priv->ndev = dev;
1377 priv->ofdev = ofdev;
369ec162 1378 priv->dev = &ofdev->dev;
4826857f 1379 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 1380
d87eb127 1381 spin_lock_init(&priv->bflock);
ab939905 1382 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 1383
8513fbd8 1384 platform_set_drvdata(ofdev, priv);
1da177e4 1385
7d350977
AV		 1386 gfar_detect_errata(priv);
1387
1da177e4 1388 /* Set the dev->base_addr to the gfar reg region */
20862788 1389 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1da177e4 1390
1da177e4 1391 /* Fill in the dev structure */
1da177e4 1392 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1393 dev->mtu = 1500;
26ccfc37 1394 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1395 dev->ethtool_ops = &gfar_ethtool_ops;
1396
fba4ed03 1397 /* Register for napi ...We are registering NAPI for each grp */
71ff9e3d
CM		 1398 for (i = 0; i < priv->num_grps; i++) {
1399 if (priv->poll_mode == GFAR_SQ_POLLING) {
1400 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1401 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1402 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1403 gfar_poll_tx_sq, 2);
1404 } else {
aeb12c5e
CM		 1405 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1406 gfar_poll_rx, GFAR_DEV_WEIGHT);
1407 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1408 gfar_poll_tx, 2);
1409 }
1410 }
a12f801d 1411
b31a1d8b 1412 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95 1413 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1414 NETIF_F_RXCSUM;
8b3afe95 1415 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1416 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
8b3afe95 1417 }
0bbaf069 1418
87c288c6 1419 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
f646968f
PM		 1420 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1421 NETIF_F_HW_VLAN_CTAG_RX;
1422 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
87c288c6 1423 }
0bbaf069 1424
3d23a05c
CM		 1425 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1426
20862788 1427 gfar_init_addr_hash_table(priv);
0bbaf069 1428
532c37bc
CM		 1429 /* Insert receive time stamps into padding alignment bytes */
1430 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1431 priv->padding = 8;
0bbaf069 1432
cc772ab7 1433 if (dev->features & NETIF_F_IP_CSUM ||
bc4598bc 1434 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1435 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4
LT		 1436
1437 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1438
a12f801d 1439 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1440 for (i = 0; i < priv->num_tx_queues; i++) {
1441 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1442 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1443 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1444 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1445 }
a12f801d 1446
fba4ed03
SG		 1447 for (i = 0; i < priv->num_rx_queues; i++) {
1448 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1449 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1450 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1451 }
1da177e4 1452
0977f817 1453 /* always enable rx filer */
4aa3a715 1454 priv->rx_filer_enable = 1;
0bbaf069
KG		 1455 /* Enable most messages by default */
1456 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
b98b8bab
CM		 1457 /* use pritority h/w tx queue scheduling for single queue devices */
1458 if (priv->num_tx_queues == 1)
1459 priv->prio_sched_en = 1;
0bbaf069 1460
0851133b
CM		 1461 set_bit(GFAR_DOWN, &priv->state);
1462
a328ac92 1463 gfar_hw_init(priv);
d3eab82b 1464
d4c642ea
FE		 1465 /* Carrier starts down, phylib will bring it up */
1466 netif_carrier_off(dev);
1467
1da177e4
LT		 1468 err = register_netdev(dev);
1469
1470 if (err) {
59deab26 1471 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1472 goto register_fail;
1473 }
1474
2884e5cc 1475 device_init_wakeup(&dev->dev,
bc4598bc
JC		 1476 priv->device_flags &
1477 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
2884e5cc 1478
c50a5d9a 1479 /* fill out IRQ number and name fields */
46ceb60c 1480 for (i = 0; i < priv->num_grps; i++) {
ee873fda 1481 struct gfar_priv_grp *grp = &priv->gfargrp[i];
46ceb60c 1482 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
ee873fda 1483 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
0015e551 1484 dev->name, "_g", '0' + i, "_tx");
ee873fda 1485 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
0015e551 1486 dev->name, "_g", '0' + i, "_rx");
ee873fda 1487 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
0015e551 1488 dev->name, "_g", '0' + i, "_er");
46ceb60c 1489 } else
ee873fda 1490 strcpy(gfar_irq(grp, TX)->name, dev->name);
46ceb60c 1491 }
c50a5d9a 1492
7a8b3372
SG		 1493 /* Initialize the filer table */
1494 gfar_init_filer_table(priv);
1495
1da177e4 1496 /* Print out the device info */
59deab26 1497 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4 1498
0977f817
JC		 1499 /* Even more device info helps when determining which kernel
1500 * provided which set of benchmarks.
1501 */
59deab26 1502 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1503 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1504 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1505 i, priv->rx_queue[i]->rx_ring_size);
bc4598bc 1506 for (i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1507 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1508 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1509
1510 return 0;
1511
1512register_fail:
46ceb60c 1513 unmap_group_regs(priv);
20862788
CM		 1514 gfar_free_rx_queues(priv);
1515 gfar_free_tx_queues(priv);
888c88b8
UKK		 1516 of_node_put(priv->phy_node);
1517 of_node_put(priv->tbi_node);
ee873fda 1518 free_gfar_dev(priv);
bb40dcbb 1519 return err;
1da177e4
LT		 1520}
1521
2dc11581 1522static int gfar_remove(struct platform_device *ofdev)
1da177e4 1523{
8513fbd8 1524 struct gfar_private *priv = platform_get_drvdata(ofdev);
1da177e4 1525
888c88b8
UKK		 1526 of_node_put(priv->phy_node);
1527 of_node_put(priv->tbi_node);
fe192a49 1528
d9d8e041 1529 unregister_netdev(priv->ndev);
46ceb60c 1530 unmap_group_regs(priv);
20862788
CM		 1531 gfar_free_rx_queues(priv);
1532 gfar_free_tx_queues(priv);
ee873fda 1533 free_gfar_dev(priv);
1da177e4
LT		 1534
1535 return 0;
1536}
1537
d87eb127 1538#ifdef CONFIG_PM
be926fc4
AV		 1539
1540static int gfar_suspend(struct device *dev)
d87eb127 1541{
be926fc4
AV		 1542 struct gfar_private *priv = dev_get_drvdata(dev);
1543 struct net_device *ndev = priv->ndev;
46ceb60c 1544 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1545 unsigned long flags;
1546 u32 tempval;
1547
1548 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1549 (priv->device_flags &
1550 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1551
be926fc4 1552 netif_device_detach(ndev);
d87eb127 1553
be926fc4 1554 if (netif_running(ndev)) {
fba4ed03
SG		 1555
1556 local_irq_save(flags);
1557 lock_tx_qs(priv);
d87eb127 1558
c10650b6 1559 gfar_halt_nodisable(priv);
d87eb127
SW		 1560
1561 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1562 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1563
1564 tempval &= ~MACCFG1_TX_EN;
1565
1566 if (!magic_packet)
1567 tempval &= ~MACCFG1_RX_EN;
1568
f4983704 1569 gfar_write(&regs->maccfg1, tempval);
d87eb127 1570
fba4ed03
SG		 1571 unlock_tx_qs(priv);
1572 local_irq_restore(flags);
d87eb127 1573
46ceb60c 1574 disable_napi(priv);
d87eb127
SW		 1575
1576 if (magic_packet) {
1577 /* Enable interrupt on Magic Packet */
f4983704 1578 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1579
1580 /* Enable Magic Packet mode */
f4983704 1581 tempval = gfar_read(&regs->maccfg2);
d87eb127 1582 tempval |= MACCFG2_MPEN;
f4983704 1583 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1584 } else {
1585 phy_stop(priv->phydev);
1586 }
1587 }
1588
1589 return 0;
1590}
1591
be926fc4 1592static int gfar_resume(struct device *dev)
d87eb127 1593{
be926fc4
AV		 1594 struct gfar_private *priv = dev_get_drvdata(dev);
1595 struct net_device *ndev = priv->ndev;
46ceb60c 1596 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1597 unsigned long flags;
1598 u32 tempval;
1599 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1600 (priv->device_flags &
1601 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1602
be926fc4
AV		 1603 if (!netif_running(ndev)) {
1604 netif_device_attach(ndev);
d87eb127
SW		 1605 return 0;
1606 }
1607
1608 if (!magic_packet && priv->phydev)
1609 phy_start(priv->phydev);
1610
1611 /* Disable Magic Packet mode, in case something
1612 * else woke us up.
1613 */
fba4ed03
SG		 1614 local_irq_save(flags);
1615 lock_tx_qs(priv);
d87eb127 1616
f4983704 1617 tempval = gfar_read(&regs->maccfg2);
d87eb127 1618 tempval &= ~MACCFG2_MPEN;
f4983704 1619 gfar_write(&regs->maccfg2, tempval);
d87eb127 1620
c10650b6 1621 gfar_start(priv);
d87eb127 1622
fba4ed03
SG		 1623 unlock_tx_qs(priv);
1624 local_irq_restore(flags);
d87eb127 1625
be926fc4
AV		 1626 netif_device_attach(ndev);
1627
46ceb60c 1628 enable_napi(priv);
be926fc4
AV		 1629
1630 return 0;
1631}
1632
1633static int gfar_restore(struct device *dev)
1634{
1635 struct gfar_private *priv = dev_get_drvdata(dev);
1636 struct net_device *ndev = priv->ndev;
1637
103cdd1d
WD		 1638 if (!netif_running(ndev)) {
1639 netif_device_attach(ndev);
1640
be926fc4 1641 return 0;
103cdd1d 1642 }
be926fc4 1643
1eb8f7a7
CM		 1644 if (gfar_init_bds(ndev)) {
1645 free_skb_resources(priv);
1646 return -ENOMEM;
1647 }
1648
a328ac92
CM		 1649 gfar_mac_reset(priv);
1650
1651 gfar_init_tx_rx_base(priv);
1652
c10650b6 1653 gfar_start(priv);
be926fc4
AV		 1654
1655 priv->oldlink = 0;
1656 priv->oldspeed = 0;
1657 priv->oldduplex = -1;
1658
1659 if (priv->phydev)
1660 phy_start(priv->phydev);
d87eb127 1661
be926fc4 1662 netif_device_attach(ndev);
5ea681d4 1663 enable_napi(priv);
d87eb127
SW		 1664
1665 return 0;
1666}
be926fc4
AV		 1667
1668static struct dev_pm_ops gfar_pm_ops = {
1669 .suspend = gfar_suspend,
1670 .resume = gfar_resume,
1671 .freeze = gfar_suspend,
1672 .thaw = gfar_resume,
1673 .restore = gfar_restore,
1674};
1675
1676#define GFAR_PM_OPS (&gfar_pm_ops)
1677
d87eb127 1678#else
be926fc4
AV		 1679
1680#define GFAR_PM_OPS NULL
be926fc4 1681
d87eb127 1682#endif
1da177e4 1683
e8a2b6a4
AF		 1684/* Reads the controller's registers to determine what interface
1685 * connects it to the PHY.
1686 */
1687static phy_interface_t gfar_get_interface(struct net_device *dev)
1688{
1689 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1690 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1691 u32 ecntrl;
1692
f4983704 1693 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1694
1695 if (ecntrl & ECNTRL_SGMII_MODE)
1696 return PHY_INTERFACE_MODE_SGMII;
1697
1698 if (ecntrl & ECNTRL_TBI_MODE) {
1699 if (ecntrl & ECNTRL_REDUCED_MODE)
1700 return PHY_INTERFACE_MODE_RTBI;
1701 else
1702 return PHY_INTERFACE_MODE_TBI;
1703 }
1704
1705 if (ecntrl & ECNTRL_REDUCED_MODE) {
bc4598bc 1706 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
e8a2b6a4 1707 return PHY_INTERFACE_MODE_RMII;
bc4598bc 1708 }
7132ab7f 1709 else {
b31a1d8b 1710 phy_interface_t interface = priv->interface;
7132ab7f 1711
0977f817 1712 /* This isn't autodetected right now, so it must
7132ab7f
AF		 1713 * be set by the device tree or platform code.
1714 */
1715 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1716 return PHY_INTERFACE_MODE_RGMII_ID;
1717
e8a2b6a4 1718 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1719 }
e8a2b6a4
AF		 1720 }
1721
b31a1d8b 1722 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1723 return PHY_INTERFACE_MODE_GMII;
1724
1725 return PHY_INTERFACE_MODE_MII;
1726}
1727
1728
bb40dcbb
AF		 1729/* Initializes driver's PHY state, and attaches to the PHY.
1730 * Returns 0 on success.
1da177e4
LT		 1731 */
1732static int init_phy(struct net_device *dev)
1733{
1734 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1735 uint gigabit_support =
b31a1d8b 1736 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
23402bdd 1737 GFAR_SUPPORTED_GBIT : 0;
e8a2b6a4 1738 phy_interface_t interface;
1da177e4
LT		 1739
1740 priv->oldlink = 0;
1741 priv->oldspeed = 0;
1742 priv->oldduplex = -1;
1743
e8a2b6a4
AF		 1744 interface = gfar_get_interface(dev);
1745
1db780f8
AV		 1746 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1747 interface);
1db780f8
AV		 1748 if (!priv->phydev) {
1749 dev_err(&dev->dev, "could not attach to PHY\n");
1750 return -ENODEV;
fe192a49 1751 }
1da177e4 1752
d3c12873
KJ		 1753 if (interface == PHY_INTERFACE_MODE_SGMII)
1754 gfar_configure_serdes(dev);
1755
bb40dcbb 1756 /* Remove any features not supported by the controller */
fe192a49
GL		 1757 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1758 priv->phydev->advertising = priv->phydev->supported;
1da177e4 1759
cf987afc
PMB		 1760 /* Add support for flow control, but don't advertise it by default */
1761 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1762
1da177e4 1763 return 0;
1da177e4
LT		 1764}
1765
0977f817 1766/* Initialize TBI PHY interface for communicating with the
d0313587
PG		 1767 * SERDES lynx PHY on the chip. We communicate with this PHY
1768 * through the MDIO bus on each controller, treating it as a
1769 * "normal" PHY at the address found in the TBIPA register. We assume
1770 * that the TBIPA register is valid. Either the MDIO bus code will set
1771 * it to a value that doesn't conflict with other PHYs on the bus, or the
1772 * value doesn't matter, as there are no other PHYs on the bus.
1773 */
d3c12873
KJ		 1774static void gfar_configure_serdes(struct net_device *dev)
1775{
1776 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1777 struct phy_device *tbiphy;
1778
1779 if (!priv->tbi_node) {
1780 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1781 "device tree specify a tbi-handle\n");
1782 return;
1783 }
c132419e 1784
fe192a49
GL		 1785 tbiphy = of_phy_find_device(priv->tbi_node);
1786 if (!tbiphy) {
1787 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1788 return;
1789 }
d3c12873 1790
0977f817 1791 /* If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1792 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1793 * everything for us? Resetting it takes the link down and requires
1794 * several seconds for it to come back.
1795 */
fe192a49 1796 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1797 return;
d3c12873 1798
d0313587 1799 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1800 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1801
fe192a49 1802 phy_write(tbiphy, MII_ADVERTISE,
bc4598bc
JC		 1803 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1804 ADVERTISE_1000XPSE_ASYM);
d3c12873 1805
bc4598bc
JC		 1806 phy_write(tbiphy, MII_BMCR,
1807 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1808 BMCR_SPEED1000);
d3c12873
KJ		 1809}
1810
511d934f
AV		 1811static int __gfar_is_rx_idle(struct gfar_private *priv)
1812{
1813 u32 res;
1814
0977f817 1815 /* Normaly TSEC should not hang on GRS commands, so we should
511d934f
AV		 1816 * actually wait for IEVENT_GRSC flag.
1817 */
ad3660c2 1818 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
511d934f
AV		 1819 return 0;
1820
0977f817 1821 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
511d934f
AV		 1822 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1823 * and the Rx can be safely reset.
1824 */
1825 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1826 res &= 0x7f807f80;
1827 if ((res & 0xffff) == (res >> 16))
1828 return 1;
1829
1830 return 0;
1831}
0bbaf069
KG		 1832
1833/* Halt the receive and transmit queues */
c10650b6 1834static void gfar_halt_nodisable(struct gfar_private *priv)
1da177e4 1835{
efeddce7 1836 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 1837 u32 tempval;
a4feee89
CM		 1838 unsigned int timeout;
1839 int stopped;
1da177e4 1840
efeddce7 1841 gfar_ints_disable(priv);
1da177e4 1842
a4feee89
CM		 1843 if (gfar_is_dma_stopped(priv))
1844 return;
1845
1da177e4 1846 /* Stop the DMA, and wait for it to stop */
f4983704 1847 tempval = gfar_read(&regs->dmactrl);
a4feee89
CM		 1848 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1849 gfar_write(&regs->dmactrl, tempval);
1850
1851retry:
1852 timeout = 1000;
1853 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1854 cpu_relax();
1855 timeout--;
1da177e4 1856 }
a4feee89
CM		 1857
1858 if (!timeout)
1859 stopped = gfar_is_dma_stopped(priv);
1860
1861 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1862 !__gfar_is_rx_idle(priv))
1863 goto retry;
d87eb127 1864}
d87eb127
SW		 1865
1866/* Halt the receive and transmit queues */
c10650b6 1867void gfar_halt(struct gfar_private *priv)
d87eb127 1868{
46ceb60c 1869 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1870 u32 tempval;
1da177e4 1871
c10650b6
CM		 1872 /* Dissable the Rx/Tx hw queues */
1873 gfar_write(&regs->rqueue, 0);
1874 gfar_write(&regs->tqueue, 0);
2a54adc3 1875
c10650b6
CM		 1876 mdelay(10);
1877
1878 gfar_halt_nodisable(priv);
1879
1880 /* Disable Rx/Tx DMA */
1da177e4
LT		 1881 tempval = gfar_read(&regs->maccfg1);
1882 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1883 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1884}
1885
1886void stop_gfar(struct net_device *dev)
1887{
1888 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1889
0851133b 1890 netif_tx_stop_all_queues(dev);
bb40dcbb 1891
4e857c58 1892 smp_mb__before_atomic();
0851133b 1893 set_bit(GFAR_DOWN, &priv->state);
4e857c58 1894 smp_mb__after_atomic();
a12f801d 1895
0851133b 1896 disable_napi(priv);
0bbaf069 1897
0851133b 1898 /* disable ints and gracefully shut down Rx/Tx DMA */
c10650b6 1899 gfar_halt(priv);
1da177e4 1900
0851133b 1901 phy_stop(priv->phydev);
1da177e4 1902
1da177e4 1903 free_skb_resources(priv);
1da177e4
LT		 1904}
1905
fba4ed03 1906static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1907{
1da177e4 1908 struct txbd8 *txbdp;
fba4ed03 1909 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1910 int i, j;
1da177e4 1911
a12f801d 1912 txbdp = tx_queue->tx_bd_base;
1da177e4 1913
a12f801d
SG		 1914 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1915 if (!tx_queue->tx_skbuff[i])
4669bc90 1916 continue;
1da177e4 1917
a7312d58
CM		 1918 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1919 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
4669bc90 1920 txbdp->lstatus = 0;
fba4ed03 1921 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
bc4598bc 1922 j++) {
4669bc90 1923 txbdp++;
a7312d58
CM		 1924 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1925 be16_to_cpu(txbdp->length),
1926 DMA_TO_DEVICE);
1da177e4 1927 }
ad5da7ab 1928 txbdp++;
a12f801d
SG		 1929 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1930 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1931 }
a12f801d 1932 kfree(tx_queue->tx_skbuff);
1eb8f7a7 1933 tx_queue->tx_skbuff = NULL;
fba4ed03 1934}
1da177e4 1935
fba4ed03
SG		 1936static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1937{
1938 struct rxbd8 *rxbdp;
1939 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1940 int i;
1da177e4 1941
fba4ed03 1942 rxbdp = rx_queue->rx_bd_base;
1da177e4 1943
a12f801d
SG		 1944 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1945 if (rx_queue->rx_skbuff[i]) {
a7312d58 1946 dma_unmap_single(priv->dev, be32_to_cpu(rxbdp->bufPtr),
369ec162 1947 priv->rx_buffer_size,
bc4598bc 1948 DMA_FROM_DEVICE);
a12f801d
SG		 1949 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1950 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1951 }
e69edd21
AV		 1952 rxbdp->lstatus = 0;
1953 rxbdp->bufPtr = 0;
1954 rxbdp++;
1da177e4 1955 }
a12f801d 1956 kfree(rx_queue->rx_skbuff);
1eb8f7a7 1957 rx_queue->rx_skbuff = NULL;
fba4ed03 1958}
e69edd21 1959
fba4ed03 1960/* If there are any tx skbs or rx skbs still around, free them.
0977f817
JC		 1961 * Then free tx_skbuff and rx_skbuff
1962 */
fba4ed03
SG		 1963static void free_skb_resources(struct gfar_private *priv)
1964{
1965 struct gfar_priv_tx_q *tx_queue = NULL;
1966 struct gfar_priv_rx_q *rx_queue = NULL;
1967 int i;
1968
1969 /* Go through all the buffer descriptors and free their data buffers */
1970 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 1971 struct netdev_queue *txq;
bc4598bc 1972
fba4ed03 1973 tx_queue = priv->tx_queue[i];
d8a0f1b0 1974 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
bc4598bc 1975 if (tx_queue->tx_skbuff)
fba4ed03 1976 free_skb_tx_queue(tx_queue);
d8a0f1b0 1977 netdev_tx_reset_queue(txq);
fba4ed03
SG		 1978 }
1979
1980 for (i = 0; i < priv->num_rx_queues; i++) {
1981 rx_queue = priv->rx_queue[i];
bc4598bc 1982 if (rx_queue->rx_skbuff)
fba4ed03
SG		 1983 free_skb_rx_queue(rx_queue);
1984 }
1985
369ec162 1986 dma_free_coherent(priv->dev,
bc4598bc
JC		 1987 sizeof(struct txbd8) * priv->total_tx_ring_size +
1988 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1989 priv->tx_queue[0]->tx_bd_base,
1990 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1991}
1992
c10650b6 1993void gfar_start(struct gfar_private *priv)
0bbaf069 1994{
46ceb60c 1995 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1996 u32 tempval;
46ceb60c 1997 int i = 0;
0bbaf069 1998
c10650b6
CM		 1999 /* Enable Rx/Tx hw queues */
2000 gfar_write(&regs->rqueue, priv->rqueue);
2001 gfar_write(&regs->tqueue, priv->tqueue);
0bbaf069
KG		 2002
2003 /* Initialize DMACTRL to have WWR and WOP */
f4983704 2004 tempval = gfar_read(&regs->dmactrl);
0bbaf069 2005 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 2006 gfar_write(&regs->dmactrl, tempval);
0bbaf069 2007
0bbaf069 2008 /* Make sure we aren't stopped */
f4983704 2009 tempval = gfar_read(&regs->dmactrl);
0bbaf069 2010 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 2011 gfar_write(&regs->dmactrl, tempval);
0bbaf069 2012
46ceb60c
SG		 2013 for (i = 0; i < priv->num_grps; i++) {
2014 regs = priv->gfargrp[i].regs;
2015 /* Clear THLT/RHLT, so that the DMA starts polling now */
2016 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2017 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
46ceb60c 2018 }
12dea57b 2019
c10650b6
CM		 2020 /* Enable Rx/Tx DMA */
2021 tempval = gfar_read(&regs->maccfg1);
2022 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2023 gfar_write(&regs->maccfg1, tempval);
2024
efeddce7
CM		 2025 gfar_ints_enable(priv);
2026
c10650b6 2027 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 2028}
2029
80ec396c
CM		 2030static void free_grp_irqs(struct gfar_priv_grp *grp)
2031{
2032 free_irq(gfar_irq(grp, TX)->irq, grp);
2033 free_irq(gfar_irq(grp, RX)->irq, grp);
2034 free_irq(gfar_irq(grp, ER)->irq, grp);
2035}
2036
46ceb60c
SG		 2037static int register_grp_irqs(struct gfar_priv_grp *grp)
2038{
2039 struct gfar_private *priv = grp->priv;
2040 struct net_device *dev = priv->ndev;
2041 int err;
1da177e4 2042
1da177e4 2043 /* If the device has multiple interrupts, register for
0977f817
JC		 2044 * them. Otherwise, only register for the one
2045 */
b31a1d8b 2046 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 2047 /* Install our interrupt handlers for Error,
0977f817
JC		 2048 * Transmit, and Receive
2049 */
ee873fda
CM		 2050 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2051 gfar_irq(grp, ER)->name, grp);
2052 if (err < 0) {
59deab26 2053 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2054 gfar_irq(grp, ER)->irq);
46ceb60c 2055
2145f1af 2056 goto err_irq_fail;
1da177e4 2057 }
ee873fda
CM		 2058 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2059 gfar_irq(grp, TX)->name, grp);
2060 if (err < 0) {
59deab26 2061 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2062 gfar_irq(grp, TX)->irq);
1da177e4
LT		 2063 goto tx_irq_fail;
2064 }
ee873fda
CM		 2065 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2066 gfar_irq(grp, RX)->name, grp);
2067 if (err < 0) {
59deab26 2068 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2069 gfar_irq(grp, RX)->irq);
1da177e4
LT		 2070 goto rx_irq_fail;
2071 }
2072 } else {
ee873fda
CM		 2073 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2074 gfar_irq(grp, TX)->name, grp);
2075 if (err < 0) {
59deab26 2076 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2077 gfar_irq(grp, TX)->irq);
1da177e4
LT		 2078 goto err_irq_fail;
2079 }
2080 }
2081
46ceb60c
SG		 2082 return 0;
2083
2084rx_irq_fail:
ee873fda 2085 free_irq(gfar_irq(grp, TX)->irq, grp);
46ceb60c 2086tx_irq_fail:
ee873fda 2087 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 2088err_irq_fail:
2089 return err;
2090
2091}
2092
80ec396c
CM		 2093static void gfar_free_irq(struct gfar_private *priv)
2094{
2095 int i;
2096
2097 /* Free the IRQs */
2098 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2099 for (i = 0; i < priv->num_grps; i++)
2100 free_grp_irqs(&priv->gfargrp[i]);
2101 } else {
2102 for (i = 0; i < priv->num_grps; i++)
2103 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2104 &priv->gfargrp[i]);
2105 }
2106}
2107
2108static int gfar_request_irq(struct gfar_private *priv)
2109{
2110 int err, i, j;
2111
2112 for (i = 0; i < priv->num_grps; i++) {
2113 err = register_grp_irqs(&priv->gfargrp[i]);
2114 if (err) {
2115 for (j = 0; j < i; j++)
2116 free_grp_irqs(&priv->gfargrp[j]);
2117 return err;
2118 }
2119 }
2120
2121 return 0;
2122}
2123
46ceb60c
SG		 2124/* Bring the controller up and running */
2125int startup_gfar(struct net_device *ndev)
2126{
2127 struct gfar_private *priv = netdev_priv(ndev);
80ec396c 2128 int err;
46ceb60c 2129
a328ac92 2130 gfar_mac_reset(priv);
46ceb60c 2131
46ceb60c
SG		 2132 err = gfar_alloc_skb_resources(ndev);
2133 if (err)
2134 return err;
2135
a328ac92 2136 gfar_init_tx_rx_base(priv);
46ceb60c 2137
4e857c58 2138 smp_mb__before_atomic();
0851133b 2139 clear_bit(GFAR_DOWN, &priv->state);
4e857c58 2140 smp_mb__after_atomic();
0851133b
CM		 2141
2142 /* Start Rx/Tx DMA and enable the interrupts */
c10650b6 2143 gfar_start(priv);
1da177e4 2144
826aa4a0
AV		 2145 phy_start(priv->phydev);
2146
0851133b
CM		 2147 enable_napi(priv);
2148
2149 netif_tx_wake_all_queues(ndev);
2150
1da177e4 2151 return 0;
1da177e4
LT		 2152}
2153
0977f817
JC		 2154/* Called when something needs to use the ethernet device
2155 * Returns 0 for success.
2156 */
1da177e4
LT		 2157static int gfar_enet_open(struct net_device *dev)
2158{
94e8cc35 2159 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 2160 int err;
2161
1da177e4 2162 err = init_phy(dev);
0851133b 2163 if (err)
1da177e4
LT		 2164 return err;
2165
80ec396c
CM		 2166 err = gfar_request_irq(priv);
2167 if (err)
2168 return err;
2169
1da177e4 2170 err = startup_gfar(dev);
0851133b 2171 if (err)
db0e8e3f 2172 return err;
1da177e4 2173
2884e5cc
AV		 2174 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2175
1da177e4
LT		 2176 return err;
2177}
2178
54dc79fe 2179static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 2180{
54dc79fe 2181 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 2182
2183 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 2184
0bbaf069
KG		 2185 return fcb;
2186}
2187
9c4886e5 2188static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
bc4598bc 2189 int fcb_length)
0bbaf069 2190{
0bbaf069
KG		 2191 /* If we're here, it's a IP packet with a TCP or UDP
2192 * payload. We set it to checksum, using a pseudo-header
2193 * we provide
2194 */
3a2e16c8 2195 u8 flags = TXFCB_DEFAULT;
0bbaf069 2196
0977f817
JC		 2197 /* Tell the controller what the protocol is
2198 * And provide the already calculated phcs
2199 */
eddc9ec5 2200 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2201 flags |= TXFCB_UDP;
26eb9374 2202 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
7f7f5316 2203 } else
26eb9374 2204 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
0bbaf069
KG		 2205
2206 /* l3os is the distance between the start of the
2207 * frame (skb->data) and the start of the IP hdr.
2208 * l4os is the distance between the start of the
0977f817
JC		 2209 * l3 hdr and the l4 hdr
2210 */
26eb9374 2211 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
cfe1fc77 2212 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2213
7f7f5316 2214 fcb->flags = flags;
0bbaf069
KG		 2215}
2216
7f7f5316 2217void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2218{
7f7f5316 2219 fcb->flags |= TXFCB_VLN;
26eb9374 2220 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
0bbaf069
KG		 2221}
2222
4669bc90 2223static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
bc4598bc 2224 struct txbd8 *base, int ring_size)
4669bc90
DH		 2225{
2226 struct txbd8 *new_bd = bdp + stride;
2227
2228 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2229}
2230
2231static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
bc4598bc 2232 int ring_size)
4669bc90
DH		 2233{
2234 return skip_txbd(bdp, 1, base, ring_size);
2235}
2236
02d88fb4
CM		 2237/* eTSEC12: csum generation not supported for some fcb offsets */
2238static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2239 unsigned long fcb_addr)
2240{
2241 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2242 (fcb_addr % 0x20) > 0x18);
2243}
2244
2245/* eTSEC76: csum generation for frames larger than 2500 may
2246 * cause excess delays before start of transmission
2247 */
2248static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2249 unsigned int len)
2250{
2251 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2252 (len > 2500));
2253}
2254
0977f817
JC		 2255/* This is called by the kernel when a frame is ready for transmission.
2256 * It is pointed to by the dev->hard_start_xmit function pointer
2257 */
1da177e4
LT		 2258static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2259{
2260 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2261 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2262 struct netdev_queue *txq;
f4983704 2263 struct gfar __iomem *regs = NULL;
0bbaf069 2264 struct txfcb *fcb = NULL;
f0ee7acf 2265 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2266 u32 lstatus;
0d0cffdc
CM		 2267 int i, rq = 0;
2268 int do_tstamp, do_csum, do_vlan;
4669bc90 2269 u32 bufaddr;
50ad076b 2270 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
fba4ed03
SG		 2271
2272 rq = skb->queue_mapping;
2273 tx_queue = priv->tx_queue[rq];
2274 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2275 base = tx_queue->tx_bd_base;
46ceb60c 2276 regs = tx_queue->grp->regs;
f0ee7acf 2277
0d0cffdc 2278 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
df8a39de 2279 do_vlan = skb_vlan_tag_present(skb);
0d0cffdc
CM		 2280 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2281 priv->hwts_tx_en;
2282
2283 if (do_csum || do_vlan)
2284 fcb_len = GMAC_FCB_LEN;
2285
f0ee7acf 2286 /* check if time stamp should be generated */
0d0cffdc
CM		 2287 if (unlikely(do_tstamp))
2288 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
4669bc90 2289
5b28beaf 2290 /* make space for additional header when fcb is needed */
0d0cffdc 2291 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
54dc79fe
SH		 2292 struct sk_buff *skb_new;
2293
0d0cffdc 2294 skb_new = skb_realloc_headroom(skb, fcb_len);
54dc79fe
SH		 2295 if (!skb_new) {
2296 dev->stats.tx_errors++;
c9974ad4 2297 dev_kfree_skb_any(skb);
54dc79fe
SH		 2298 return NETDEV_TX_OK;
2299 }
db83d136 2300
313b037c
ED		 2301 if (skb->sk)
2302 skb_set_owner_w(skb_new, skb->sk);
c9974ad4 2303 dev_consume_skb_any(skb);
54dc79fe
SH		 2304 skb = skb_new;
2305 }
2306
4669bc90
DH		 2307 /* total number of fragments in the SKB */
2308 nr_frags = skb_shinfo(skb)->nr_frags;
2309
f0ee7acf
MR		 2310 /* calculate the required number of TxBDs for this skb */
2311 if (unlikely(do_tstamp))
2312 nr_txbds = nr_frags + 2;
2313 else
2314 nr_txbds = nr_frags + 1;
2315
4669bc90 2316 /* check if there is space to queue this packet */
f0ee7acf 2317 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2318 /* no space, stop the queue */
fba4ed03 2319 netif_tx_stop_queue(txq);
4669bc90 2320 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2321 return NETDEV_TX_BUSY;
2322 }
1da177e4
LT		 2323
2324 /* Update transmit stats */
50ad076b
CM		 2325 bytes_sent = skb->len;
2326 tx_queue->stats.tx_bytes += bytes_sent;
2327 /* keep Tx bytes on wire for BQL accounting */
2328 GFAR_CB(skb)->bytes_sent = bytes_sent;
1ac9ad13 2329 tx_queue->stats.tx_packets++;
1da177e4 2330
a12f801d 2331 txbdp = txbdp_start = tx_queue->cur_tx;
a7312d58 2332 lstatus = be32_to_cpu(txbdp->lstatus);
f0ee7acf
MR		 2333
2334 /* Time stamp insertion requires one additional TxBD */
2335 if (unlikely(do_tstamp))
2336 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
bc4598bc 2337 tx_queue->tx_ring_size);
1da177e4 2338
4669bc90 2339 if (nr_frags == 0) {
a7312d58
CM		 2340 if (unlikely(do_tstamp)) {
2341 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2342
2343 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2344 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2345 } else {
f0ee7acf 2346 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
a7312d58 2347 }
4669bc90
DH		 2348 } else {
2349 /* Place the fragment addresses and lengths into the TxBDs */
2350 for (i = 0; i < nr_frags; i++) {
50ad076b 2351 unsigned int frag_len;
4669bc90 2352 /* Point at the next BD, wrapping as needed */
a12f801d 2353 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2354
50ad076b 2355 frag_len = skb_shinfo(skb)->frags[i].size;
4669bc90 2356
a7312d58 2357 lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
bc4598bc 2358 BD_LFLAG(TXBD_READY);
4669bc90
DH		 2359
2360 /* Handle the last BD specially */
2361 if (i == nr_frags - 1)
2362 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2363
369ec162 2364 bufaddr = skb_frag_dma_map(priv->dev,
2234a722
IC		 2365 &skb_shinfo(skb)->frags[i],
2366 0,
50ad076b 2367 frag_len,
2234a722 2368 DMA_TO_DEVICE);
0a4b5a24
KH		 2369 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2370 goto dma_map_err;
4669bc90
DH		 2371
2372 /* set the TxBD length and buffer pointer */
a7312d58
CM		 2373 txbdp->bufPtr = cpu_to_be32(bufaddr);
2374 txbdp->lstatus = cpu_to_be32(lstatus);
4669bc90
DH		 2375 }
2376
a7312d58 2377 lstatus = be32_to_cpu(txbdp_start->lstatus);
4669bc90 2378 }
1da177e4 2379
9c4886e5
MR		 2380 /* Add TxPAL between FCB and frame if required */
2381 if (unlikely(do_tstamp)) {
2382 skb_push(skb, GMAC_TXPAL_LEN);
2383 memset(skb->data, 0, GMAC_TXPAL_LEN);
2384 }
2385
0d0cffdc
CM		 2386 /* Add TxFCB if required */
2387 if (fcb_len) {
54dc79fe 2388 fcb = gfar_add_fcb(skb);
02d88fb4 2389 lstatus |= BD_LFLAG(TXBD_TOE);
0d0cffdc
CM		 2390 }
2391
2392 /* Set up checksumming */
2393 if (do_csum) {
2394 gfar_tx_checksum(skb, fcb, fcb_len);
02d88fb4
CM		 2395
2396 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2397 unlikely(gfar_csum_errata_76(priv, skb->len))) {
4363c2fd
AD		 2398 __skb_pull(skb, GMAC_FCB_LEN);
2399 skb_checksum_help(skb);
0d0cffdc
CM		 2400 if (do_vlan || do_tstamp) {
2401 /* put back a new fcb for vlan/tstamp TOE */
2402 fcb = gfar_add_fcb(skb);
2403 } else {
2404 /* Tx TOE not used */
2405 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2406 fcb = NULL;
2407 }
4363c2fd 2408 }
0bbaf069
KG		 2409 }
2410
0d0cffdc 2411 if (do_vlan)
54dc79fe 2412 gfar_tx_vlan(skb, fcb);
0bbaf069 2413
f0ee7acf
MR		 2414 /* Setup tx hardware time stamping if requested */
2415 if (unlikely(do_tstamp)) {
2244d07b 2416 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf 2417 fcb->ptp = 1;
f0ee7acf
MR		 2418 }
2419
0a4b5a24
KH		 2420 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2421 DMA_TO_DEVICE);
2422 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2423 goto dma_map_err;
2424
a7312d58 2425 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1da177e4 2426
0977f817 2427 /* If time stamping is requested one additional TxBD must be set up. The
f0ee7acf
MR		 2428 * first TxBD points to the FCB and must have a data length of
2429 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2430 * the full frame length.
2431 */
2432 if (unlikely(do_tstamp)) {
a7312d58
CM		 2433 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2434
2435 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2436 bufaddr += fcb_len;
2437 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2438 (skb_headlen(skb) - fcb_len);
2439
2440 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2441 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
f0ee7acf
MR		 2442 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2443 } else {
2444 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2445 }
1da177e4 2446
50ad076b 2447 netdev_tx_sent_queue(txq, bytes_sent);
d8a0f1b0 2448
d55398ba 2449 gfar_wmb();
7f7f5316 2450
a7312d58 2451 txbdp_start->lstatus = cpu_to_be32(lstatus);
4669bc90 2452
d55398ba 2453 gfar_wmb(); /* force lstatus write before tx_skbuff */
0eddba52
AV		 2454
2455 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2456
4669bc90 2457 /* Update the current skb pointer to the next entry we will use
0977f817
JC		 2458 * (wrapping if necessary)
2459 */
a12f801d 2460 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
bc4598bc 2461 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2462
a12f801d 2463 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2464
bc602280
CM		 2465 /* We can work in parallel with gfar_clean_tx_ring(), except
2466 * when modifying num_txbdfree. Note that we didn't grab the lock
2467 * when we were reading the num_txbdfree and checking for available
2468 * space, that's because outside of this function it can only grow.
2469 */
2470 spin_lock_bh(&tx_queue->txlock);
4669bc90 2471 /* reduce TxBD free count */
f0ee7acf 2472 tx_queue->num_txbdfree -= (nr_txbds);
bc602280 2473 spin_unlock_bh(&tx_queue->txlock);
1da177e4
LT		 2474
2475 /* If the next BD still needs to be cleaned up, then the bds
0977f817
JC		 2476 * are full. We need to tell the kernel to stop sending us stuff.
2477 */
a12f801d 2478 if (!tx_queue->num_txbdfree) {
fba4ed03 2479 netif_tx_stop_queue(txq);
1da177e4 2480
09f75cd7 2481 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2482 }
2483
1da177e4 2484 /* Tell the DMA to go go go */
fba4ed03 2485 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4 2486
54dc79fe 2487 return NETDEV_TX_OK;
0a4b5a24
KH		 2488
2489dma_map_err:
2490 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2491 if (do_tstamp)
2492 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2493 for (i = 0; i < nr_frags; i++) {
a7312d58 2494 lstatus = be32_to_cpu(txbdp->lstatus);
0a4b5a24
KH		 2495 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2496 break;
2497
a7312d58
CM		 2498 lstatus &= ~BD_LFLAG(TXBD_READY);
2499 txbdp->lstatus = cpu_to_be32(lstatus);
2500 bufaddr = be32_to_cpu(txbdp->bufPtr);
2501 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
0a4b5a24
KH		 2502 DMA_TO_DEVICE);
2503 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2504 }
2505 gfar_wmb();
2506 dev_kfree_skb_any(skb);
2507 return NETDEV_TX_OK;
1da177e4
LT		 2508}
2509
2510/* Stops the kernel queue, and halts the controller */
2511static int gfar_close(struct net_device *dev)
2512{
2513 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2514
ab939905 2515 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2516 stop_gfar(dev);
2517
bb40dcbb
AF		 2518 /* Disconnect from the PHY */
2519 phy_disconnect(priv->phydev);
2520 priv->phydev = NULL;
1da177e4 2521
80ec396c
CM		 2522 gfar_free_irq(priv);
2523
1da177e4
LT		 2524 return 0;
2525}
2526
1da177e4 2527/* Changes the mac address if the controller is not running. */
f162b9d5 2528static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2529{
7f7f5316 2530 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2531
2532 return 0;
2533}
2534
1da177e4
LT		 2535static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2536{
1da177e4 2537 struct gfar_private *priv = netdev_priv(dev);
0bbaf069
KG		 2538 int frame_size = new_mtu + ETH_HLEN;
2539
1da177e4 2540 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2541 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2542 return -EINVAL;
2543 }
2544
0851133b
CM		 2545 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2546 cpu_relax();
2547
88302648 2548 if (dev->flags & IFF_UP)
1da177e4
LT		 2549 stop_gfar(dev);
2550
1da177e4
LT		 2551 dev->mtu = new_mtu;
2552
88302648 2553 if (dev->flags & IFF_UP)
1da177e4
LT		 2554 startup_gfar(dev);
2555
0851133b
CM		 2556 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2557
1da177e4
LT		 2558 return 0;
2559}
2560
0851133b
CM		 2561void reset_gfar(struct net_device *ndev)
2562{
2563 struct gfar_private *priv = netdev_priv(ndev);
2564
2565 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2566 cpu_relax();
2567
2568 stop_gfar(ndev);
2569 startup_gfar(ndev);
2570
2571 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2572}
2573
ab939905 2574/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2575 * transmitted after a set amount of time.
2576 * For now, assume that clearing out all the structures, and
ab939905
SS		 2577 * starting over will fix the problem.
2578 */
2579static void gfar_reset_task(struct work_struct *work)
1da177e4 2580{
ab939905 2581 struct gfar_private *priv = container_of(work, struct gfar_private,
bc4598bc 2582 reset_task);
0851133b 2583 reset_gfar(priv->ndev);
1da177e4
LT		 2584}
2585
ab939905
SS		 2586static void gfar_timeout(struct net_device *dev)
2587{
2588 struct gfar_private *priv = netdev_priv(dev);
2589
2590 dev->stats.tx_errors++;
2591 schedule_work(&priv->reset_task);
2592}
2593
acbc0f03
EL		 2594static void gfar_align_skb(struct sk_buff *skb)
2595{
2596 /* We need the data buffer to be aligned properly. We will reserve
2597 * as many bytes as needed to align the data properly
2598 */
2599 skb_reserve(skb, RXBUF_ALIGNMENT -
bc4598bc 2600 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
acbc0f03
EL		 2601}
2602
1da177e4 2603/* Interrupt Handler for Transmit complete */
c233cf40 2604static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2605{
a12f801d 2606 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2607 struct netdev_queue *txq;
d080cd63 2608 struct gfar_private *priv = netdev_priv(dev);
f0ee7acf 2609 struct txbd8 *bdp, *next = NULL;
4669bc90 2610 struct txbd8 *lbdp = NULL;
a12f801d 2611 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2612 struct sk_buff *skb;
2613 int skb_dirtytx;
a12f801d 2614 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2615 int frags = 0, nr_txbds = 0;
4669bc90 2616 int i;
d080cd63 2617 int howmany = 0;
d8a0f1b0
PG		 2618 int tqi = tx_queue->qindex;
2619 unsigned int bytes_sent = 0;
4669bc90 2620 u32 lstatus;
f0ee7acf 2621 size_t buflen;
1da177e4 2622
d8a0f1b0 2623 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2624 bdp = tx_queue->dirty_tx;
2625 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2626
a12f801d 2627 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11 2628
4669bc90 2629 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf 2630
0977f817 2631 /* When time stamping, one additional TxBD must be freed.
f0ee7acf
MR		 2632 * Also, we need to dma_unmap_single() the TxPAL.
2633 */
2244d07b 2634 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2635 nr_txbds = frags + 2;
2636 else
2637 nr_txbds = frags + 1;
2638
2639 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2640
a7312d58 2641 lstatus = be32_to_cpu(lbdp->lstatus);
1da177e4 2642
4669bc90
DH		 2643 /* Only clean completed frames */
2644 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
bc4598bc 2645 (lstatus & BD_LENGTH_MASK))
4669bc90
DH		 2646 break;
2647
2244d07b 2648 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2649 next = next_txbd(bdp, base, tx_ring_size);
a7312d58
CM		 2650 buflen = be16_to_cpu(next->length) +
2651 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf 2652 } else
a7312d58 2653 buflen = be16_to_cpu(bdp->length);
f0ee7acf 2654
a7312d58 2655 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
bc4598bc 2656 buflen, DMA_TO_DEVICE);
f0ee7acf 2657
2244d07b 2658 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2659 struct skb_shared_hwtstamps shhwtstamps;
2660 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
bc4598bc 2661
f0ee7acf
MR		 2662 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2663 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
9c4886e5 2664 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf 2665 skb_tstamp_tx(skb, &shhwtstamps);
a7312d58 2666 gfar_clear_txbd_status(bdp);
f0ee7acf
MR		 2667 bdp = next;
2668 }
81183059 2669
a7312d58 2670 gfar_clear_txbd_status(bdp);
4669bc90 2671 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2672
4669bc90 2673 for (i = 0; i < frags; i++) {
a7312d58
CM		 2674 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2675 be16_to_cpu(bdp->length),
2676 DMA_TO_DEVICE);
2677 gfar_clear_txbd_status(bdp);
4669bc90
DH		 2678 bdp = next_txbd(bdp, base, tx_ring_size);
2679 }
1da177e4 2680
50ad076b 2681 bytes_sent += GFAR_CB(skb)->bytes_sent;
d8a0f1b0 2682
acb600de 2683 dev_kfree_skb_any(skb);
0fd56bb5 2684
a12f801d 2685 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2686
4669bc90 2687 skb_dirtytx = (skb_dirtytx + 1) &
bc4598bc 2688 TX_RING_MOD_MASK(tx_ring_size);
4669bc90
DH		 2689
2690 howmany++;
bc602280 2691 spin_lock(&tx_queue->txlock);
f0ee7acf 2692 tx_queue->num_txbdfree += nr_txbds;
bc602280 2693 spin_unlock(&tx_queue->txlock);
4669bc90 2694 }
1da177e4 2695
4669bc90 2696 /* If we freed a buffer, we can restart transmission, if necessary */
0851133b
CM		 2697 if (tx_queue->num_txbdfree &&
2698 netif_tx_queue_stopped(txq) &&
2699 !(test_bit(GFAR_DOWN, &priv->state)))
2700 netif_wake_subqueue(priv->ndev, tqi);
1da177e4 2701
4669bc90 2702 /* Update dirty indicators */
a12f801d
SG		 2703 tx_queue->skb_dirtytx = skb_dirtytx;
2704 tx_queue->dirty_tx = bdp;
1da177e4 2705
d8a0f1b0 2706 netdev_tx_completed_queue(txq, howmany, bytes_sent);
d080cd63
DH		 2707}
2708
2281a0f3 2709static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2710{
2711 struct gfar_private *priv = netdev_priv(dev);
acb600de 2712 struct sk_buff *skb;
1da177e4 2713
acbc0f03 2714 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2715 if (!skb)
1da177e4
LT		 2716 return NULL;
2717
acbc0f03 2718 gfar_align_skb(skb);
7f7f5316 2719
acbc0f03
EL		 2720 return skb;
2721}
2722
91c53f76 2723static struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr)
acbc0f03 2724{
0a4b5a24
KH		 2725 struct gfar_private *priv = netdev_priv(dev);
2726 struct sk_buff *skb;
2727 dma_addr_t addr;
2728
2729 skb = gfar_alloc_skb(dev);
2730 if (!skb)
2731 return NULL;
2732
2733 addr = dma_map_single(priv->dev, skb->data,
2734 priv->rx_buffer_size, DMA_FROM_DEVICE);
2735 if (unlikely(dma_mapping_error(priv->dev, addr))) {
2736 dev_kfree_skb_any(skb);
2737 return NULL;
2738 }
2739
2740 *bufaddr = addr;
2741 return skb;
1da177e4
LT		 2742}
2743
298e1a9e 2744static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2745{
298e1a9e 2746 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2747 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2748 struct gfar_extra_stats *estats = &priv->extra_stats;
2749
0977f817 2750 /* If the packet was truncated, none of the other errors matter */
1da177e4
LT		 2751 if (status & RXBD_TRUNCATED) {
2752 stats->rx_length_errors++;
2753
212079df 2754 atomic64_inc(&estats->rx_trunc);
1da177e4
LT		 2755
2756 return;
2757 }
2758 /* Count the errors, if there were any */
2759 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2760 stats->rx_length_errors++;
2761
2762 if (status & RXBD_LARGE)
212079df 2763 atomic64_inc(&estats->rx_large);
1da177e4 2764 else
212079df 2765 atomic64_inc(&estats->rx_short);
1da177e4
LT		 2766 }
2767 if (status & RXBD_NONOCTET) {
2768 stats->rx_frame_errors++;
212079df 2769 atomic64_inc(&estats->rx_nonoctet);
1da177e4
LT		 2770 }
2771 if (status & RXBD_CRCERR) {
212079df 2772 atomic64_inc(&estats->rx_crcerr);
1da177e4
LT		 2773 stats->rx_crc_errors++;
2774 }
2775 if (status & RXBD_OVERRUN) {
212079df 2776 atomic64_inc(&estats->rx_overrun);
1da177e4
LT		 2777 stats->rx_crc_errors++;
2778 }
2779}
2780
f4983704 2781irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2782{
aeb12c5e
CM		 2783 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2784 unsigned long flags;
2785 u32 imask;
2786
2787 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2788 spin_lock_irqsave(&grp->grplock, flags);
2789 imask = gfar_read(&grp->regs->imask);
2790 imask &= IMASK_RX_DISABLED;
2791 gfar_write(&grp->regs->imask, imask);
2792 spin_unlock_irqrestore(&grp->grplock, flags);
2793 __napi_schedule(&grp->napi_rx);
2794 } else {
2795 /* Clear IEVENT, so interrupts aren't called again
2796 * because of the packets that have already arrived.
2797 */
2798 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2799 }
2800
2801 return IRQ_HANDLED;
2802}
2803
2804/* Interrupt Handler for Transmit complete */
2805static irqreturn_t gfar_transmit(int irq, void *grp_id)
2806{
2807 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2808 unsigned long flags;
2809 u32 imask;
2810
2811 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2812 spin_lock_irqsave(&grp->grplock, flags);
2813 imask = gfar_read(&grp->regs->imask);
2814 imask &= IMASK_TX_DISABLED;
2815 gfar_write(&grp->regs->imask, imask);
2816 spin_unlock_irqrestore(&grp->grplock, flags);
2817 __napi_schedule(&grp->napi_tx);
2818 } else {
2819 /* Clear IEVENT, so interrupts aren't called again
2820 * because of the packets that have already arrived.
2821 */
2822 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2823 }
2824
1da177e4
LT		 2825 return IRQ_HANDLED;
2826}
2827
0bbaf069
KG		 2828static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2829{
2830 /* If valid headers were found, and valid sums
2831 * were verified, then we tell the kernel that no
0977f817
JC		 2832 * checksumming is necessary. Otherwise, it is [FIXME]
2833 */
26eb9374
CM		 2834 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2835 (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2836 skb->ip_summed = CHECKSUM_UNNECESSARY;
2837 else
bc8acf2c 2838 skb_checksum_none_assert(skb);
0bbaf069
KG		 2839}
2840
0977f817 2841/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
61db26c6
CM		 2842static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2843 int amount_pull, struct napi_struct *napi)
1da177e4
LT		 2844{
2845 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2846 struct rxfcb *fcb = NULL;
1da177e4 2847
2c2db48a
DH		 2848 /* fcb is at the beginning if exists */
2849 fcb = (struct rxfcb *)skb->data;
0bbaf069 2850
0977f817
JC		 2851 /* Remove the FCB from the skb
2852 * Remove the padded bytes, if there are any
2853 */
f74dac08
SG		 2854 if (amount_pull) {
2855 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2856 skb_pull(skb, amount_pull);
f74dac08 2857 }
0bbaf069 2858
cc772ab7
MR		 2859 /* Get receive timestamp from the skb */
2860 if (priv->hwts_rx_en) {
2861 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2862 u64 *ns = (u64 *) skb->data;
bc4598bc 2863
cc772ab7
MR		 2864 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2865 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2866 }
2867
2868 if (priv->padding)
2869 skb_pull(skb, priv->padding);
2870
8b3afe95 2871 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2872 gfar_rx_checksum(skb, fcb);
0bbaf069 2873
2c2db48a
DH		 2874 /* Tell the skb what kind of packet this is */
2875 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2876
f646968f 2877 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
32f7fd44
JP		 2878 * Even if vlan rx accel is disabled, on some chips
2879 * RXFCB_VLN is pseudo randomly set.
2880 */
f646968f 2881 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
26eb9374
CM		 2882 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2883 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2884 be16_to_cpu(fcb->vlctl));
87c288c6 2885
2c2db48a 2886 /* Send the packet up the stack */
953d2768 2887 napi_gro_receive(napi, skb);
0bbaf069 2888
1da177e4
LT		 2889}
2890
2891/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2281a0f3
JC		 2892 * until the budget/quota has been reached. Returns the number
2893 * of frames handled
1da177e4 2894 */
a12f801d 2895int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2896{
a12f801d 2897 struct net_device *dev = rx_queue->dev;
31de198b 2898 struct rxbd8 *bdp, *base;
1da177e4 2899 struct sk_buff *skb;
2c2db48a
DH		 2900 int pkt_len;
2901 int amount_pull;
1da177e4
LT		 2902 int howmany = 0;
2903 struct gfar_private *priv = netdev_priv(dev);
2904
2905 /* Get the first full descriptor */
a12f801d
SG		 2906 bdp = rx_queue->cur_rx;
2907 base = rx_queue->rx_bd_base;
1da177e4 2908
ba779711 2909 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2c2db48a 2910
a7312d58 2911 while (!(be16_to_cpu(bdp->status) & RXBD_EMPTY) && rx_work_limit--) {
815b97c6 2912 struct sk_buff *newskb;
0a4b5a24 2913 dma_addr_t bufaddr;
bc4598bc 2914
3b6330ce 2915 rmb();
815b97c6
AF		 2916
2917 /* Add another skb for the future */
0a4b5a24 2918 newskb = gfar_new_skb(dev, &bufaddr);
815b97c6 2919
a12f801d 2920 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2921
a7312d58 2922 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
bc4598bc 2923 priv->rx_buffer_size, DMA_FROM_DEVICE);
81183059 2924
a7312d58
CM		 2925 if (unlikely(!(be16_to_cpu(bdp->status) & RXBD_ERR) &&
2926 be16_to_cpu(bdp->length) > priv->rx_buffer_size))
2927 bdp->status = cpu_to_be16(RXBD_LARGE);
63b88b90 2928
815b97c6 2929 /* We drop the frame if we failed to allocate a new buffer */
a7312d58
CM		 2930 if (unlikely(!newskb ||
2931 !(be16_to_cpu(bdp->status) & RXBD_LAST) ||
2932 be16_to_cpu(bdp->status) & RXBD_ERR)) {
2933 count_errors(be16_to_cpu(bdp->status), dev);
815b97c6 2934
0a4b5a24 2935 if (unlikely(!newskb)) {
815b97c6 2936 newskb = skb;
a7312d58 2937 bufaddr = be32_to_cpu(bdp->bufPtr);
0a4b5a24 2938 } else if (skb)
acb600de 2939 dev_kfree_skb(skb);
815b97c6 2940 } else {
1da177e4 2941 /* Increment the number of packets */
a7f38041 2942 rx_queue->stats.rx_packets++;
1da177e4
LT		 2943 howmany++;
2944
2c2db48a 2945 if (likely(skb)) {
a7312d58
CM		 2946 pkt_len = be16_to_cpu(bdp->length) -
2947 ETH_FCS_LEN;
2c2db48a
DH		 2948 /* Remove the FCS from the packet length */
2949 skb_put(skb, pkt_len);
a7f38041 2950 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2951 skb_record_rx_queue(skb, rx_queue->qindex);
cd754a57 2952 gfar_process_frame(dev, skb, amount_pull,
aeb12c5e 2953 &rx_queue->grp->napi_rx);
2c2db48a
DH		 2954
2955 } else {
59deab26 2956 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2957 rx_queue->stats.rx_dropped++;
212079df 2958 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2c2db48a 2959 }
1da177e4 2960
1da177e4
LT		 2961 }
2962
a12f801d 2963 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2964
815b97c6 2965 /* Setup the new bdp */
0a4b5a24 2966 gfar_init_rxbdp(rx_queue, bdp, bufaddr);
1da177e4 2967
45b679c9
MP		 2968 /* Update Last Free RxBD pointer for LFC */
2969 if (unlikely(rx_queue->rfbptr && priv->tx_actual_en))
2970 gfar_write(rx_queue->rfbptr, (u32)bdp);
2971
1da177e4 2972 /* Update to the next pointer */
a12f801d 2973 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2974
2975 /* update to point at the next skb */
bc4598bc
JC		 2976 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2977 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2978 }
2979
2980 /* Update the current rxbd pointer to be the next one */
a12f801d 2981 rx_queue->cur_rx = bdp;
1da177e4 2982
1da177e4
LT		 2983 return howmany;
2984}
2985
aeb12c5e 2986static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
5eaedf31
CM		 2987{
2988 struct gfar_priv_grp *gfargrp =
aeb12c5e 2989 container_of(napi, struct gfar_priv_grp, napi_rx);
5eaedf31 2990 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 2991 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
5eaedf31
CM		 2992 int work_done = 0;
2993
2994 /* Clear IEVENT, so interrupts aren't called again
2995 * because of the packets that have already arrived
2996 */
aeb12c5e 2997 gfar_write(&regs->ievent, IEVENT_RX_MASK);
5eaedf31
CM		 2998
2999 work_done = gfar_clean_rx_ring(rx_queue, budget);
3000
3001 if (work_done < budget) {
aeb12c5e 3002 u32 imask;
5eaedf31
CM		 3003 napi_complete(napi);
3004 /* Clear the halt bit in RSTAT */
3005 gfar_write(&regs->rstat, gfargrp->rstat);
3006
aeb12c5e
CM		 3007 spin_lock_irq(&gfargrp->grplock);
3008 imask = gfar_read(&regs->imask);
3009 imask |= IMASK_RX_DEFAULT;
3010 gfar_write(&regs->imask, imask);
3011 spin_unlock_irq(&gfargrp->grplock);
5eaedf31
CM		 3012 }
3013
3014 return work_done;
3015}
3016
aeb12c5e 3017static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
1da177e4 3018{
bc4598bc 3019 struct gfar_priv_grp *gfargrp =
aeb12c5e
CM		 3020 container_of(napi, struct gfar_priv_grp, napi_tx);
3021 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 3022 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
aeb12c5e
CM		 3023 u32 imask;
3024
3025 /* Clear IEVENT, so interrupts aren't called again
3026 * because of the packets that have already arrived
3027 */
3028 gfar_write(&regs->ievent, IEVENT_TX_MASK);
3029
3030 /* run Tx cleanup to completion */
3031 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3032 gfar_clean_tx_ring(tx_queue);
3033
3034 napi_complete(napi);
3035
3036 spin_lock_irq(&gfargrp->grplock);
3037 imask = gfar_read(&regs->imask);
3038 imask |= IMASK_TX_DEFAULT;
3039 gfar_write(&regs->imask, imask);
3040 spin_unlock_irq(&gfargrp->grplock);
3041
3042 return 0;
3043}
3044
3045static int gfar_poll_rx(struct napi_struct *napi, int budget)
3046{
3047 struct gfar_priv_grp *gfargrp =
3048 container_of(napi, struct gfar_priv_grp, napi_rx);
fba4ed03 3049 struct gfar_private *priv = gfargrp->priv;
46ceb60c 3050 struct gfar __iomem *regs = gfargrp->regs;
fba4ed03 3051 struct gfar_priv_rx_q *rx_queue = NULL;
c233cf40 3052 int work_done = 0, work_done_per_q = 0;
39c0a0d5 3053 int i, budget_per_q = 0;
6be5ed3f
CM		 3054 unsigned long rstat_rxf;
3055 int num_act_queues;
fba4ed03 3056
8c7396ae 3057 /* Clear IEVENT, so interrupts aren't called again
0977f817
JC		 3058 * because of the packets that have already arrived
3059 */
aeb12c5e 3060 gfar_write(&regs->ievent, IEVENT_RX_MASK);
8c7396ae 3061
6be5ed3f
CM		 3062 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3063
3064 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3065 if (num_act_queues)
3066 budget_per_q = budget/num_act_queues;
3067
3ba405db
CM		 3068 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3069 /* skip queue if not active */
3070 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3071 continue;
1da177e4 3072
3ba405db
CM		 3073 rx_queue = priv->rx_queue[i];
3074 work_done_per_q =
3075 gfar_clean_rx_ring(rx_queue, budget_per_q);
3076 work_done += work_done_per_q;
3077
3078 /* finished processing this queue */
3079 if (work_done_per_q < budget_per_q) {
3080 /* clear active queue hw indication */
3081 gfar_write(&regs->rstat,
3082 RSTAT_CLEAR_RXF0 >> i);
3083 num_act_queues--;
3084
3085 if (!num_act_queues)
3086 break;
3087 }
3088 }
42199884 3089
aeb12c5e
CM		 3090 if (!num_act_queues) {
3091 u32 imask;
3ba405db 3092 napi_complete(napi);
1da177e4 3093
3ba405db
CM		 3094 /* Clear the halt bit in RSTAT */
3095 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 3096
aeb12c5e
CM		 3097 spin_lock_irq(&gfargrp->grplock);
3098 imask = gfar_read(&regs->imask);
3099 imask |= IMASK_RX_DEFAULT;
3100 gfar_write(&regs->imask, imask);
3101 spin_unlock_irq(&gfargrp->grplock);
1da177e4
LT		 3102 }
3103
c233cf40 3104 return work_done;
1da177e4 3105}
1da177e4 3106
aeb12c5e
CM		 3107static int gfar_poll_tx(struct napi_struct *napi, int budget)
3108{
3109 struct gfar_priv_grp *gfargrp =
3110 container_of(napi, struct gfar_priv_grp, napi_tx);
3111 struct gfar_private *priv = gfargrp->priv;
3112 struct gfar __iomem *regs = gfargrp->regs;
3113 struct gfar_priv_tx_q *tx_queue = NULL;
3114 int has_tx_work = 0;
3115 int i;
3116
3117 /* Clear IEVENT, so interrupts aren't called again
3118 * because of the packets that have already arrived
3119 */
3120 gfar_write(&regs->ievent, IEVENT_TX_MASK);
3121
3122 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3123 tx_queue = priv->tx_queue[i];
3124 /* run Tx cleanup to completion */
3125 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3126 gfar_clean_tx_ring(tx_queue);
3127 has_tx_work = 1;
3128 }
3129 }
3130
3131 if (!has_tx_work) {
3132 u32 imask;
3133 napi_complete(napi);
3134
3135 spin_lock_irq(&gfargrp->grplock);
3136 imask = gfar_read(&regs->imask);
3137 imask |= IMASK_TX_DEFAULT;
3138 gfar_write(&regs->imask, imask);
3139 spin_unlock_irq(&gfargrp->grplock);
3140 }
3141
3142 return 0;
3143}
3144
3145
f2d71c2d 3146#ifdef CONFIG_NET_POLL_CONTROLLER
0977f817 3147/* Polling 'interrupt' - used by things like netconsole to send skbs
f2d71c2d
VW		 3148 * without having to re-enable interrupts. It's not called while
3149 * the interrupt routine is executing.
3150 */
3151static void gfar_netpoll(struct net_device *dev)
3152{
3153 struct gfar_private *priv = netdev_priv(dev);
3a2e16c8 3154 int i;
f2d71c2d
VW		 3155
3156 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 3157 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c 3158 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3159 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3160
3161 disable_irq(gfar_irq(grp, TX)->irq);
3162 disable_irq(gfar_irq(grp, RX)->irq);
3163 disable_irq(gfar_irq(grp, ER)->irq);
3164 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3165 enable_irq(gfar_irq(grp, ER)->irq);
3166 enable_irq(gfar_irq(grp, RX)->irq);
3167 enable_irq(gfar_irq(grp, TX)->irq);
46ceb60c 3168 }
f2d71c2d 3169 } else {
46ceb60c 3170 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3171 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3172
3173 disable_irq(gfar_irq(grp, TX)->irq);
3174 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3175 enable_irq(gfar_irq(grp, TX)->irq);
43de004b 3176 }
f2d71c2d
VW		 3177 }
3178}
3179#endif
3180
1da177e4 3181/* The interrupt handler for devices with one interrupt */
f4983704 3182static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 3183{
f4983704 3184 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 3185
3186 /* Save ievent for future reference */
f4983704 3187 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 3188
1da177e4 3189 /* Check for reception */
538cc7ee 3190 if (events & IEVENT_RX_MASK)
f4983704 3191 gfar_receive(irq, grp_id);
1da177e4
LT		 3192
3193 /* Check for transmit completion */
538cc7ee 3194 if (events & IEVENT_TX_MASK)
f4983704 3195 gfar_transmit(irq, grp_id);
1da177e4 3196
538cc7ee
SS		 3197 /* Check for errors */
3198 if (events & IEVENT_ERR_MASK)
f4983704 3199 gfar_error(irq, grp_id);
1da177e4
LT		 3200
3201 return IRQ_HANDLED;
3202}
3203
1da177e4
LT		 3204/* Called every time the controller might need to be made
3205 * aware of new link state. The PHY code conveys this
bb40dcbb 3206 * information through variables in the phydev structure, and this
1da177e4
LT		 3207 * function converts those variables into the appropriate
3208 * register values, and can bring down the device if needed.
3209 */
3210static void adjust_link(struct net_device *dev)
3211{
3212 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 3213 struct phy_device *phydev = priv->phydev;
bb40dcbb 3214
6ce29b0e 3215 if (unlikely(phydev->link != priv->oldlink ||
0ae93b2c
GR		 3216 (phydev->link && (phydev->duplex != priv->oldduplex ||
3217 phydev->speed != priv->oldspeed))))
6ce29b0e 3218 gfar_update_link_state(priv);
bb40dcbb 3219}
1da177e4
LT		 3220
3221/* Update the hash table based on the current list of multicast
3222 * addresses we subscribe to. Also, change the promiscuity of
3223 * the device based on the flags (this function is called
0977f817
JC		 3224 * whenever dev->flags is changed
3225 */
1da177e4
LT		 3226static void gfar_set_multi(struct net_device *dev)
3227{
22bedad3 3228 struct netdev_hw_addr *ha;
1da177e4 3229 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3230 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3231 u32 tempval;
3232
a12f801d 3233 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3234 /* Set RCTRL to PROM */
3235 tempval = gfar_read(&regs->rctrl);
3236 tempval |= RCTRL_PROM;
3237 gfar_write(&regs->rctrl, tempval);
3238 } else {
3239 /* Set RCTRL to not PROM */
3240 tempval = gfar_read(&regs->rctrl);
3241 tempval &= ~(RCTRL_PROM);
3242 gfar_write(&regs->rctrl, tempval);
3243 }
6aa20a22 3244
a12f801d 3245 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3246 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3247 gfar_write(&regs->igaddr0, 0xffffffff);
3248 gfar_write(&regs->igaddr1, 0xffffffff);
3249 gfar_write(&regs->igaddr2, 0xffffffff);
3250 gfar_write(&regs->igaddr3, 0xffffffff);
3251 gfar_write(&regs->igaddr4, 0xffffffff);
3252 gfar_write(&regs->igaddr5, 0xffffffff);
3253 gfar_write(&regs->igaddr6, 0xffffffff);
3254 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3255 gfar_write(&regs->gaddr0, 0xffffffff);
3256 gfar_write(&regs->gaddr1, 0xffffffff);
3257 gfar_write(&regs->gaddr2, 0xffffffff);
3258 gfar_write(&regs->gaddr3, 0xffffffff);
3259 gfar_write(&regs->gaddr4, 0xffffffff);
3260 gfar_write(&regs->gaddr5, 0xffffffff);
3261 gfar_write(&regs->gaddr6, 0xffffffff);
3262 gfar_write(&regs->gaddr7, 0xffffffff);
3263 } else {
7f7f5316
AF		 3264 int em_num;
3265 int idx;
3266
1da177e4 3267 /* zero out the hash */
0bbaf069
KG		 3268 gfar_write(&regs->igaddr0, 0x0);
3269 gfar_write(&regs->igaddr1, 0x0);
3270 gfar_write(&regs->igaddr2, 0x0);
3271 gfar_write(&regs->igaddr3, 0x0);
3272 gfar_write(&regs->igaddr4, 0x0);
3273 gfar_write(&regs->igaddr5, 0x0);
3274 gfar_write(&regs->igaddr6, 0x0);
3275 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3276 gfar_write(&regs->gaddr0, 0x0);
3277 gfar_write(&regs->gaddr1, 0x0);
3278 gfar_write(&regs->gaddr2, 0x0);
3279 gfar_write(&regs->gaddr3, 0x0);
3280 gfar_write(&regs->gaddr4, 0x0);
3281 gfar_write(&regs->gaddr5, 0x0);
3282 gfar_write(&regs->gaddr6, 0x0);
3283 gfar_write(&regs->gaddr7, 0x0);
3284
7f7f5316
AF		 3285 /* If we have extended hash tables, we need to
3286 * clear the exact match registers to prepare for
0977f817
JC		 3287 * setting them
3288 */
7f7f5316
AF		 3289 if (priv->extended_hash) {
3290 em_num = GFAR_EM_NUM + 1;
3291 gfar_clear_exact_match(dev);
3292 idx = 1;
3293 } else {
3294 idx = 0;
3295 em_num = 0;
3296 }
3297
4cd24eaf 3298 if (netdev_mc_empty(dev))
1da177e4
LT		 3299 return;
3300
3301 /* Parse the list, and set the appropriate bits */
22bedad3 3302 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3303 if (idx < em_num) {
22bedad3 3304 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3305 idx++;
3306 } else
22bedad3 3307 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3308 }
3309 }
1da177e4
LT		 3310}
3311
7f7f5316
AF		 3312
3313/* Clears each of the exact match registers to zero, so they
0977f817
JC		 3314 * don't interfere with normal reception
3315 */
7f7f5316
AF		 3316static void gfar_clear_exact_match(struct net_device *dev)
3317{
3318 int idx;
6a3c910c 3319 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316 3320
bc4598bc 3321 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
b6bc7650 3322 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3323}
3324
1da177e4
LT		 3325/* Set the appropriate hash bit for the given addr */
3326/* The algorithm works like so:
3327 * 1) Take the Destination Address (ie the multicast address), and
3328 * do a CRC on it (little endian), and reverse the bits of the
3329 * result.
3330 * 2) Use the 8 most significant bits as a hash into a 256-entry
3331 * table. The table is controlled through 8 32-bit registers:
3332 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3333 * gaddr7. This means that the 3 most significant bits in the
3334 * hash index which gaddr register to use, and the 5 other bits
3335 * indicate which bit (assuming an IBM numbering scheme, which
3336 * for PowerPC (tm) is usually the case) in the register holds
0977f817
JC		 3337 * the entry.
3338 */
1da177e4
LT		 3339static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3340{
3341 u32 tempval;
3342 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3343 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3344 int width = priv->hash_width;
3345 u8 whichbit = (result >> (32 - width)) & 0x1f;
3346 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3347 u32 value = (1 << (31-whichbit));
3348
0bbaf069 3349 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3350 tempval |= value;
0bbaf069 3351 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3352}
3353
7f7f5316
AF		 3354
3355/* There are multiple MAC Address register pairs on some controllers
3356 * This function sets the numth pair to a given address
3357 */
b6bc7650
JP		 3358static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3359 const u8 *addr)
7f7f5316
AF		 3360{
3361 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3362 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3363 u32 tempval;
f4983704 3364 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3365
3366 macptr += num*2;
3367
83bfc3c4
CM		 3368 /* For a station address of 0x12345678ABCD in transmission
3369 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3370 * MACnADDR2 is set to 0x34120000.
0977f817 3371 */
83bfc3c4
CM		 3372 tempval = (addr[5] << 24) | (addr[4] << 16) |
3373 (addr[3] << 8) | addr[2];
7f7f5316 3374
83bfc3c4 3375 gfar_write(macptr, tempval);
7f7f5316 3376
83bfc3c4 3377 tempval = (addr[1] << 24) | (addr[0] << 16);
7f7f5316
AF		 3378
3379 gfar_write(macptr+1, tempval);
3380}
3381
1da177e4 3382/* GFAR error interrupt handler */
f4983704 3383static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3384{
f4983704
SG		 3385 struct gfar_priv_grp *gfargrp = grp_id;
3386 struct gfar __iomem *regs = gfargrp->regs;
3387 struct gfar_private *priv= gfargrp->priv;
3388 struct net_device *dev = priv->ndev;
1da177e4
LT		 3389
3390 /* Save ievent for future reference */
f4983704 3391 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3392
3393 /* Clear IEVENT */
f4983704 3394 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3395
3396 /* Magic Packet is not an error. */
b31a1d8b 3397 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3398 (events & IEVENT_MAG))
3399 events &= ~IEVENT_MAG;
1da177e4
LT		 3400
3401 /* Hmm... */
0bbaf069 3402 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
bc4598bc
JC		 3403 netdev_dbg(dev,
3404 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
59deab26 3405 events, gfar_read(&regs->imask));
1da177e4
LT		 3406
3407 /* Update the error counters */
3408 if (events & IEVENT_TXE) {
09f75cd7 3409 dev->stats.tx_errors++;
1da177e4
LT		 3410
3411 if (events & IEVENT_LC)
09f75cd7 3412 dev->stats.tx_window_errors++;
1da177e4 3413 if (events & IEVENT_CRL)
09f75cd7 3414 dev->stats.tx_aborted_errors++;
1da177e4 3415 if (events & IEVENT_XFUN) {
59deab26
JP		 3416 netif_dbg(priv, tx_err, dev,
3417 "TX FIFO underrun, packet dropped\n");
09f75cd7 3418 dev->stats.tx_dropped++;
212079df 3419 atomic64_inc(&priv->extra_stats.tx_underrun);
1da177e4 3420
bc602280 3421 schedule_work(&priv->reset_task);
1da177e4 3422 }
59deab26 3423 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3424 }
3425 if (events & IEVENT_BSY) {
09f75cd7 3426 dev->stats.rx_errors++;
212079df 3427 atomic64_inc(&priv->extra_stats.rx_bsy);
1da177e4 3428
f4983704 3429 gfar_receive(irq, grp_id);
1da177e4 3430
59deab26
JP		 3431 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3432 gfar_read(&regs->rstat));
1da177e4
LT		 3433 }
3434 if (events & IEVENT_BABR) {
09f75cd7 3435 dev->stats.rx_errors++;
212079df 3436 atomic64_inc(&priv->extra_stats.rx_babr);
1da177e4 3437
59deab26 3438 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3439 }
3440 if (events & IEVENT_EBERR) {
212079df 3441 atomic64_inc(&priv->extra_stats.eberr);
59deab26 3442 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3443 }
59deab26
JP		 3444 if (events & IEVENT_RXC)
3445 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3446
3447 if (events & IEVENT_BABT) {
212079df 3448 atomic64_inc(&priv->extra_stats.tx_babt);
59deab26 3449 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3450 }
3451 return IRQ_HANDLED;
3452}
3453
6ce29b0e
CM		 3454static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3455{
3456 struct phy_device *phydev = priv->phydev;
3457 u32 val = 0;
3458
3459 if (!phydev->duplex)
3460 return val;
3461
3462 if (!priv->pause_aneg_en) {
3463 if (priv->tx_pause_en)
3464 val |= MACCFG1_TX_FLOW;
3465 if (priv->rx_pause_en)
3466 val |= MACCFG1_RX_FLOW;
3467 } else {
3468 u16 lcl_adv, rmt_adv;
3469 u8 flowctrl;
3470 /* get link partner capabilities */
3471 rmt_adv = 0;
3472 if (phydev->pause)
3473 rmt_adv = LPA_PAUSE_CAP;
3474 if (phydev->asym_pause)
3475 rmt_adv |= LPA_PAUSE_ASYM;
3476
43ef8d29
PMB		 3477 lcl_adv = 0;
3478 if (phydev->advertising & ADVERTISED_Pause)
3479 lcl_adv |= ADVERTISE_PAUSE_CAP;
3480 if (phydev->advertising & ADVERTISED_Asym_Pause)
3481 lcl_adv |= ADVERTISE_PAUSE_ASYM;
6ce29b0e
CM		 3482
3483 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3484 if (flowctrl & FLOW_CTRL_TX)
3485 val |= MACCFG1_TX_FLOW;
3486 if (flowctrl & FLOW_CTRL_RX)
3487 val |= MACCFG1_RX_FLOW;
3488 }
3489
3490 return val;
3491}
3492
3493static noinline void gfar_update_link_state(struct gfar_private *priv)
3494{
3495 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3496 struct phy_device *phydev = priv->phydev;
45b679c9
MP		 3497 struct gfar_priv_rx_q *rx_queue = NULL;
3498 int i;
3499 struct rxbd8 *bdp;
6ce29b0e
CM		 3500
3501 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3502 return;
3503
3504 if (phydev->link) {
3505 u32 tempval1 = gfar_read(&regs->maccfg1);
3506 u32 tempval = gfar_read(&regs->maccfg2);
3507 u32 ecntrl = gfar_read(&regs->ecntrl);
45b679c9 3508 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
6ce29b0e
CM		 3509
3510 if (phydev->duplex != priv->oldduplex) {
3511 if (!(phydev->duplex))
3512 tempval &= ~(MACCFG2_FULL_DUPLEX);
3513 else
3514 tempval |= MACCFG2_FULL_DUPLEX;
3515
3516 priv->oldduplex = phydev->duplex;
3517 }
3518
3519 if (phydev->speed != priv->oldspeed) {
3520 switch (phydev->speed) {
3521 case 1000:
3522 tempval =
3523 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3524
3525 ecntrl &= ~(ECNTRL_R100);
3526 break;
3527 case 100:
3528 case 10:
3529 tempval =
3530 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3531
3532 /* Reduced mode distinguishes
3533 * between 10 and 100
3534 */
3535 if (phydev->speed == SPEED_100)
3536 ecntrl |= ECNTRL_R100;
3537 else
3538 ecntrl &= ~(ECNTRL_R100);
3539 break;
3540 default:
3541 netif_warn(priv, link, priv->ndev,
3542 "Ack! Speed (%d) is not 10/100/1000!\n",
3543 phydev->speed);
3544 break;
3545 }
3546
3547 priv->oldspeed = phydev->speed;
3548 }
3549
3550 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3551 tempval1 |= gfar_get_flowctrl_cfg(priv);
3552
45b679c9
MP		 3553 /* Turn last free buffer recording on */
3554 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3555 for (i = 0; i < priv->num_rx_queues; i++) {
3556 rx_queue = priv->rx_queue[i];
3557 bdp = rx_queue->cur_rx;
3558 /* skip to previous bd */
3559 bdp = skip_bd(bdp, rx_queue->rx_ring_size - 1,
3560 rx_queue->rx_bd_base,
3561 rx_queue->rx_ring_size);
3562
3563 if (rx_queue->rfbptr)
3564 gfar_write(rx_queue->rfbptr, (u32)bdp);
3565 }
3566
3567 priv->tx_actual_en = 1;
3568 }
3569
3570 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3571 priv->tx_actual_en = 0;
3572
6ce29b0e
CM		 3573 gfar_write(&regs->maccfg1, tempval1);
3574 gfar_write(&regs->maccfg2, tempval);
3575 gfar_write(&regs->ecntrl, ecntrl);
3576
3577 if (!priv->oldlink)
3578 priv->oldlink = 1;
3579
3580 } else if (priv->oldlink) {
3581 priv->oldlink = 0;
3582 priv->oldspeed = 0;
3583 priv->oldduplex = -1;
3584 }
3585
3586 if (netif_msg_link(priv))
3587 phy_print_status(phydev);
3588}
3589
94e5a2a8 3590static const struct of_device_id gfar_match[] =
b31a1d8b
AF		 3591{
3592 {
3593 .type = "network",
3594 .compatible = "gianfar",
3595 },
46ceb60c
SG		 3596 {
3597 .compatible = "fsl,etsec2",
3598 },
b31a1d8b
AF		 3599 {},
3600};
e72701ac 3601MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3602
1da177e4 3603/* Structure for a device driver */
74888760 3604static struct platform_driver gfar_driver = {
4018294b
GL		 3605 .driver = {
3606 .name = "fsl-gianfar",
4018294b
GL		 3607 .pm = GFAR_PM_OPS,
3608 .of_match_table = gfar_match,
3609 },
1da177e4
LT		 3610 .probe = gfar_probe,
3611 .remove = gfar_remove,
3612};
3613
db62f684 3614module_platform_driver(gfar_driver);
Linux 6.x block layer and io_uring tree(s)