Commit | Line | Data |
---|---|---|
0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
6c43e046 | 12 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/init.h> | |
74 | #include <linux/delay.h> | |
75 | #include <linux/netdevice.h> | |
76 | #include <linux/etherdevice.h> | |
77 | #include <linux/skbuff.h> | |
0bbaf069 | 78 | #include <linux/if_vlan.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/mm.h> | |
fe192a49 | 81 | #include <linux/of_mdio.h> |
b31a1d8b | 82 | #include <linux/of_platform.h> |
0bbaf069 KG |
83 | #include <linux/ip.h> |
84 | #include <linux/tcp.h> | |
85 | #include <linux/udp.h> | |
9c07b884 | 86 | #include <linux/in.h> |
cc772ab7 | 87 | #include <linux/net_tstamp.h> |
1da177e4 LT |
88 | |
89 | #include <asm/io.h> | |
7d350977 | 90 | #include <asm/reg.h> |
1da177e4 LT |
91 | #include <asm/irq.h> |
92 | #include <asm/uaccess.h> | |
93 | #include <linux/module.h> | |
1da177e4 LT |
94 | #include <linux/dma-mapping.h> |
95 | #include <linux/crc32.h> | |
bb40dcbb AF |
96 | #include <linux/mii.h> |
97 | #include <linux/phy.h> | |
b31a1d8b AF |
98 | #include <linux/phy_fixed.h> |
99 | #include <linux/of.h> | |
4b6ba8aa | 100 | #include <linux/of_net.h> |
1da177e4 LT |
101 | |
102 | #include "gianfar.h" | |
1da177e4 LT |
103 | |
104 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 105 | |
7f7f5316 | 106 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 107 | |
1da177e4 LT |
108 | static int gfar_enet_open(struct net_device *dev); |
109 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 110 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
111 | static void gfar_timeout(struct net_device *dev); |
112 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 113 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 114 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 115 | struct sk_buff *skb); |
1da177e4 LT |
116 | static int gfar_set_mac_address(struct net_device *dev); |
117 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
118 | static irqreturn_t gfar_error(int irq, void *dev_id); |
119 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
120 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
121 | static void adjust_link(struct net_device *dev); |
122 | static void init_registers(struct net_device *dev); | |
123 | static int init_phy(struct net_device *dev); | |
74888760 | 124 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 125 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 126 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
127 | static void gfar_set_multi(struct net_device *dev); |
128 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 129 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 130 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
131 | #ifdef CONFIG_NET_POLL_CONTROLLER |
132 | static void gfar_netpoll(struct net_device *dev); | |
133 | #endif | |
a12f801d | 134 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
c233cf40 | 135 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); |
61db26c6 CM |
136 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
137 | int amount_pull, struct napi_struct *napi); | |
7f7f5316 | 138 | void gfar_halt(struct net_device *dev); |
d87eb127 | 139 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
140 | void gfar_start(struct net_device *dev); |
141 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
142 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
143 | const u8 *addr); | |
26ccfc37 | 144 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 145 | |
1da177e4 LT |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
a12f801d | 150 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
151 | dma_addr_t buf) |
152 | { | |
8a102fe0 AV |
153 | u32 lstatus; |
154 | ||
155 | bdp->bufPtr = buf; | |
156 | ||
157 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 158 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
159 | lstatus |= BD_LFLAG(RXBD_WRAP); |
160 | ||
161 | eieio(); | |
162 | ||
163 | bdp->lstatus = lstatus; | |
164 | } | |
165 | ||
8728327e | 166 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 167 | { |
8728327e | 168 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
169 | struct gfar_priv_tx_q *tx_queue = NULL; |
170 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
171 | struct txbd8 *txbdp; |
172 | struct rxbd8 *rxbdp; | |
fba4ed03 | 173 | int i, j; |
a12f801d | 174 | |
fba4ed03 SG |
175 | for (i = 0; i < priv->num_tx_queues; i++) { |
176 | tx_queue = priv->tx_queue[i]; | |
177 | /* Initialize some variables in our dev structure */ | |
178 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
179 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
180 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
181 | tx_queue->skb_curtx = 0; | |
182 | tx_queue->skb_dirtytx = 0; | |
183 | ||
184 | /* Initialize Transmit Descriptor Ring */ | |
185 | txbdp = tx_queue->tx_bd_base; | |
186 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
187 | txbdp->lstatus = 0; | |
188 | txbdp->bufPtr = 0; | |
189 | txbdp++; | |
190 | } | |
8728327e | 191 | |
fba4ed03 SG |
192 | /* Set the last descriptor in the ring to indicate wrap */ |
193 | txbdp--; | |
194 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
195 | } |
196 | ||
fba4ed03 SG |
197 | for (i = 0; i < priv->num_rx_queues; i++) { |
198 | rx_queue = priv->rx_queue[i]; | |
199 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
200 | rx_queue->skb_currx = 0; | |
201 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 202 | |
fba4ed03 SG |
203 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
204 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 205 | |
fba4ed03 SG |
206 | if (skb) { |
207 | gfar_init_rxbdp(rx_queue, rxbdp, | |
208 | rxbdp->bufPtr); | |
209 | } else { | |
210 | skb = gfar_new_skb(ndev); | |
211 | if (!skb) { | |
59deab26 | 212 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
1eb8f7a7 | 213 | return -ENOMEM; |
fba4ed03 SG |
214 | } |
215 | rx_queue->rx_skbuff[j] = skb; | |
216 | ||
217 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 218 | } |
8728327e | 219 | |
fba4ed03 | 220 | rxbdp++; |
8728327e AV |
221 | } |
222 | ||
8728327e AV |
223 | } |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
229 | { | |
826aa4a0 | 230 | void *vaddr; |
fba4ed03 SG |
231 | dma_addr_t addr; |
232 | int i, j, k; | |
826aa4a0 | 233 | struct gfar_private *priv = netdev_priv(ndev); |
369ec162 | 234 | struct device *dev = priv->dev; |
a12f801d SG |
235 | struct gfar_priv_tx_q *tx_queue = NULL; |
236 | struct gfar_priv_rx_q *rx_queue = NULL; | |
237 | ||
fba4ed03 SG |
238 | priv->total_tx_ring_size = 0; |
239 | for (i = 0; i < priv->num_tx_queues; i++) | |
240 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
241 | ||
242 | priv->total_rx_ring_size = 0; | |
243 | for (i = 0; i < priv->num_rx_queues; i++) | |
244 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
245 | |
246 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 247 | vaddr = dma_alloc_coherent(dev, |
d0320f75 JP |
248 | (priv->total_tx_ring_size * |
249 | sizeof(struct txbd8)) + | |
250 | (priv->total_rx_ring_size * | |
251 | sizeof(struct rxbd8)), | |
252 | &addr, GFP_KERNEL); | |
253 | if (!vaddr) | |
826aa4a0 | 254 | return -ENOMEM; |
826aa4a0 | 255 | |
fba4ed03 SG |
256 | for (i = 0; i < priv->num_tx_queues; i++) { |
257 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 258 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
259 | tx_queue->tx_bd_dma_base = addr; |
260 | tx_queue->dev = ndev; | |
261 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
262 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
263 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 264 | } |
826aa4a0 | 265 | |
826aa4a0 | 266 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
267 | for (i = 0; i < priv->num_rx_queues; i++) { |
268 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 269 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
270 | rx_queue->rx_bd_dma_base = addr; |
271 | rx_queue->dev = ndev; | |
bc4598bc JC |
272 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
273 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 274 | } |
826aa4a0 AV |
275 | |
276 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
277 | for (i = 0; i < priv->num_tx_queues; i++) { |
278 | tx_queue = priv->tx_queue[i]; | |
14f8dc49 JP |
279 | tx_queue->tx_skbuff = |
280 | kmalloc_array(tx_queue->tx_ring_size, | |
281 | sizeof(*tx_queue->tx_skbuff), | |
282 | GFP_KERNEL); | |
283 | if (!tx_queue->tx_skbuff) | |
fba4ed03 | 284 | goto cleanup; |
826aa4a0 | 285 | |
fba4ed03 SG |
286 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
287 | tx_queue->tx_skbuff[k] = NULL; | |
288 | } | |
826aa4a0 | 289 | |
fba4ed03 SG |
290 | for (i = 0; i < priv->num_rx_queues; i++) { |
291 | rx_queue = priv->rx_queue[i]; | |
14f8dc49 JP |
292 | rx_queue->rx_skbuff = |
293 | kmalloc_array(rx_queue->rx_ring_size, | |
294 | sizeof(*rx_queue->rx_skbuff), | |
295 | GFP_KERNEL); | |
296 | if (!rx_queue->rx_skbuff) | |
fba4ed03 | 297 | goto cleanup; |
fba4ed03 SG |
298 | |
299 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
300 | rx_queue->rx_skbuff[j] = NULL; | |
301 | } | |
826aa4a0 | 302 | |
8728327e AV |
303 | if (gfar_init_bds(ndev)) |
304 | goto cleanup; | |
826aa4a0 AV |
305 | |
306 | return 0; | |
307 | ||
308 | cleanup: | |
309 | free_skb_resources(priv); | |
310 | return -ENOMEM; | |
311 | } | |
312 | ||
fba4ed03 SG |
313 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
314 | { | |
46ceb60c | 315 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 316 | u32 __iomem *baddr; |
fba4ed03 SG |
317 | int i; |
318 | ||
319 | baddr = ®s->tbase0; | |
bc4598bc | 320 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 321 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 322 | baddr += 2; |
fba4ed03 SG |
323 | } |
324 | ||
325 | baddr = ®s->rbase0; | |
bc4598bc | 326 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 327 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 328 | baddr += 2; |
fba4ed03 SG |
329 | } |
330 | } | |
331 | ||
826aa4a0 AV |
332 | static void gfar_init_mac(struct net_device *ndev) |
333 | { | |
334 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 335 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
336 | u32 rctrl = 0; |
337 | u32 tctrl = 0; | |
338 | u32 attrs = 0; | |
339 | ||
fba4ed03 SG |
340 | /* write the tx/rx base registers */ |
341 | gfar_init_tx_rx_base(priv); | |
32c513bc | 342 | |
826aa4a0 | 343 | /* Configure the coalescing support */ |
46ceb60c | 344 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
fba4ed03 | 345 | |
ba779711 CM |
346 | /* set this when rx hw offload (TOE) functions are being used */ |
347 | priv->uses_rxfcb = 0; | |
348 | ||
1ccb8389 | 349 | if (priv->rx_filer_enable) { |
fba4ed03 | 350 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
351 | /* Program the RIR0 reg with the required distribution */ |
352 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
353 | } | |
826aa4a0 | 354 | |
f5ae6279 CM |
355 | /* Restore PROMISC mode */ |
356 | if (ndev->flags & IFF_PROMISC) | |
357 | rctrl |= RCTRL_PROM; | |
358 | ||
ba779711 | 359 | if (ndev->features & NETIF_F_RXCSUM) { |
826aa4a0 | 360 | rctrl |= RCTRL_CHECKSUMMING; |
ba779711 CM |
361 | priv->uses_rxfcb = 1; |
362 | } | |
826aa4a0 AV |
363 | |
364 | if (priv->extended_hash) { | |
365 | rctrl |= RCTRL_EXTHASH; | |
366 | ||
367 | gfar_clear_exact_match(ndev); | |
368 | rctrl |= RCTRL_EMEN; | |
369 | } | |
370 | ||
371 | if (priv->padding) { | |
372 | rctrl &= ~RCTRL_PAL_MASK; | |
373 | rctrl |= RCTRL_PADDING(priv->padding); | |
374 | } | |
375 | ||
cc772ab7 MR |
376 | /* Insert receive time stamps into padding alignment bytes */ |
377 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
378 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 379 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
380 | priv->padding = 8; |
381 | } | |
382 | ||
97553f7f | 383 | /* Enable HW time stamping if requested from user space */ |
ba779711 | 384 | if (priv->hwts_rx_en) { |
97553f7f | 385 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; |
ba779711 CM |
386 | priv->uses_rxfcb = 1; |
387 | } | |
97553f7f | 388 | |
ba779711 | 389 | if (ndev->features & NETIF_F_HW_VLAN_RX) { |
b852b720 | 390 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
ba779711 CM |
391 | priv->uses_rxfcb = 1; |
392 | } | |
826aa4a0 AV |
393 | |
394 | /* Init rctrl based on our settings */ | |
395 | gfar_write(®s->rctrl, rctrl); | |
396 | ||
397 | if (ndev->features & NETIF_F_IP_CSUM) | |
398 | tctrl |= TCTRL_INIT_CSUM; | |
399 | ||
b98b8bab CM |
400 | if (priv->prio_sched_en) |
401 | tctrl |= TCTRL_TXSCHED_PRIO; | |
402 | else { | |
403 | tctrl |= TCTRL_TXSCHED_WRRS; | |
404 | gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); | |
405 | gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); | |
406 | } | |
fba4ed03 | 407 | |
826aa4a0 AV |
408 | gfar_write(®s->tctrl, tctrl); |
409 | ||
410 | /* Set the extraction length and index */ | |
411 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
412 | ATTRELI_EI(priv->rx_stash_index); | |
413 | ||
414 | gfar_write(®s->attreli, attrs); | |
415 | ||
416 | /* Start with defaults, and add stashing or locking | |
0977f817 JC |
417 | * depending on the approprate variables |
418 | */ | |
826aa4a0 AV |
419 | attrs = ATTR_INIT_SETTINGS; |
420 | ||
421 | if (priv->bd_stash_en) | |
422 | attrs |= ATTR_BDSTASH; | |
423 | ||
424 | if (priv->rx_stash_size != 0) | |
425 | attrs |= ATTR_BUFSTASH; | |
426 | ||
427 | gfar_write(®s->attr, attrs); | |
428 | ||
429 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
430 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
431 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
432 | } | |
433 | ||
a7f38041 SG |
434 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
435 | { | |
436 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
437 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
438 | unsigned long tx_packets = 0, tx_bytes = 0; | |
3a2e16c8 | 439 | int i; |
a7f38041 SG |
440 | |
441 | for (i = 0; i < priv->num_rx_queues; i++) { | |
442 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 443 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
444 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
445 | } | |
446 | ||
447 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 448 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
449 | dev->stats.rx_dropped = rx_dropped; |
450 | ||
451 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
452 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
453 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
454 | } |
455 | ||
bc4598bc | 456 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
457 | dev->stats.tx_packets = tx_packets; |
458 | ||
459 | return &dev->stats; | |
460 | } | |
461 | ||
26ccfc37 AF |
462 | static const struct net_device_ops gfar_netdev_ops = { |
463 | .ndo_open = gfar_enet_open, | |
464 | .ndo_start_xmit = gfar_start_xmit, | |
465 | .ndo_stop = gfar_close, | |
466 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 467 | .ndo_set_features = gfar_set_features, |
afc4b13d | 468 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
469 | .ndo_tx_timeout = gfar_timeout, |
470 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 471 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
472 | .ndo_set_mac_address = eth_mac_addr, |
473 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
474 | #ifdef CONFIG_NET_POLL_CONTROLLER |
475 | .ndo_poll_controller = gfar_netpoll, | |
476 | #endif | |
477 | }; | |
478 | ||
fba4ed03 SG |
479 | void lock_rx_qs(struct gfar_private *priv) |
480 | { | |
3a2e16c8 | 481 | int i; |
fba4ed03 SG |
482 | |
483 | for (i = 0; i < priv->num_rx_queues; i++) | |
484 | spin_lock(&priv->rx_queue[i]->rxlock); | |
485 | } | |
486 | ||
487 | void lock_tx_qs(struct gfar_private *priv) | |
488 | { | |
3a2e16c8 | 489 | int i; |
fba4ed03 SG |
490 | |
491 | for (i = 0; i < priv->num_tx_queues; i++) | |
492 | spin_lock(&priv->tx_queue[i]->txlock); | |
493 | } | |
494 | ||
495 | void unlock_rx_qs(struct gfar_private *priv) | |
496 | { | |
3a2e16c8 | 497 | int i; |
fba4ed03 SG |
498 | |
499 | for (i = 0; i < priv->num_rx_queues; i++) | |
500 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
501 | } | |
502 | ||
503 | void unlock_tx_qs(struct gfar_private *priv) | |
504 | { | |
3a2e16c8 | 505 | int i; |
fba4ed03 SG |
506 | |
507 | for (i = 0; i < priv->num_tx_queues; i++) | |
508 | spin_unlock(&priv->tx_queue[i]->txlock); | |
509 | } | |
510 | ||
fba4ed03 SG |
511 | static void free_tx_pointers(struct gfar_private *priv) |
512 | { | |
3a2e16c8 | 513 | int i; |
fba4ed03 SG |
514 | |
515 | for (i = 0; i < priv->num_tx_queues; i++) | |
516 | kfree(priv->tx_queue[i]); | |
517 | } | |
518 | ||
519 | static void free_rx_pointers(struct gfar_private *priv) | |
520 | { | |
3a2e16c8 | 521 | int i; |
fba4ed03 SG |
522 | |
523 | for (i = 0; i < priv->num_rx_queues; i++) | |
524 | kfree(priv->rx_queue[i]); | |
525 | } | |
526 | ||
46ceb60c SG |
527 | static void unmap_group_regs(struct gfar_private *priv) |
528 | { | |
3a2e16c8 | 529 | int i; |
46ceb60c SG |
530 | |
531 | for (i = 0; i < MAXGROUPS; i++) | |
532 | if (priv->gfargrp[i].regs) | |
533 | iounmap(priv->gfargrp[i].regs); | |
534 | } | |
535 | ||
ee873fda CM |
536 | static void free_gfar_dev(struct gfar_private *priv) |
537 | { | |
538 | int i, j; | |
539 | ||
540 | for (i = 0; i < priv->num_grps; i++) | |
541 | for (j = 0; j < GFAR_NUM_IRQS; j++) { | |
542 | kfree(priv->gfargrp[i].irqinfo[j]); | |
543 | priv->gfargrp[i].irqinfo[j] = NULL; | |
544 | } | |
545 | ||
546 | free_netdev(priv->ndev); | |
547 | } | |
548 | ||
46ceb60c SG |
549 | static void disable_napi(struct gfar_private *priv) |
550 | { | |
3a2e16c8 | 551 | int i; |
46ceb60c SG |
552 | |
553 | for (i = 0; i < priv->num_grps; i++) | |
554 | napi_disable(&priv->gfargrp[i].napi); | |
555 | } | |
556 | ||
557 | static void enable_napi(struct gfar_private *priv) | |
558 | { | |
3a2e16c8 | 559 | int i; |
46ceb60c SG |
560 | |
561 | for (i = 0; i < priv->num_grps; i++) | |
562 | napi_enable(&priv->gfargrp[i].napi); | |
563 | } | |
564 | ||
565 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 566 | struct gfar_private *priv, const char *model) |
46ceb60c | 567 | { |
5fedcc14 | 568 | struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; |
46ceb60c | 569 | u32 *queue_mask; |
ee873fda CM |
570 | int i; |
571 | ||
7c1e7e99 PG |
572 | for (i = 0; i < GFAR_NUM_IRQS; i++) { |
573 | grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), | |
574 | GFP_KERNEL); | |
575 | if (!grp->irqinfo[i]) | |
ee873fda | 576 | return -ENOMEM; |
ee873fda | 577 | } |
46ceb60c | 578 | |
5fedcc14 CM |
579 | grp->regs = of_iomap(np, 0); |
580 | if (!grp->regs) | |
46ceb60c SG |
581 | return -ENOMEM; |
582 | ||
ee873fda | 583 | gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); |
46ceb60c SG |
584 | |
585 | /* If we aren't the FEC we have multiple interrupts */ | |
586 | if (model && strcasecmp(model, "FEC")) { | |
ee873fda CM |
587 | gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); |
588 | gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); | |
589 | if (gfar_irq(grp, TX)->irq == NO_IRQ || | |
590 | gfar_irq(grp, RX)->irq == NO_IRQ || | |
591 | gfar_irq(grp, ER)->irq == NO_IRQ) | |
46ceb60c | 592 | return -EINVAL; |
46ceb60c SG |
593 | } |
594 | ||
5fedcc14 CM |
595 | grp->grp_id = priv->num_grps; |
596 | grp->priv = priv; | |
597 | spin_lock_init(&grp->grplock); | |
bc4598bc JC |
598 | if (priv->mode == MQ_MG_MODE) { |
599 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
5fedcc14 | 600 | grp->rx_bit_map = queue_mask ? |
bc4598bc JC |
601 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
602 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
5fedcc14 | 603 | grp->tx_bit_map = queue_mask ? |
bc4598bc | 604 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
46ceb60c | 605 | } else { |
5fedcc14 CM |
606 | grp->rx_bit_map = 0xFF; |
607 | grp->tx_bit_map = 0xFF; | |
46ceb60c SG |
608 | } |
609 | priv->num_grps++; | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
2dc11581 | 614 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 615 | { |
b31a1d8b AF |
616 | const char *model; |
617 | const char *ctype; | |
618 | const void *mac_addr; | |
fba4ed03 SG |
619 | int err = 0, i; |
620 | struct net_device *dev = NULL; | |
621 | struct gfar_private *priv = NULL; | |
61c7a080 | 622 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 623 | struct device_node *child = NULL; |
4d7902f2 AF |
624 | const u32 *stash; |
625 | const u32 *stash_len; | |
626 | const u32 *stash_idx; | |
fba4ed03 SG |
627 | unsigned int num_tx_qs, num_rx_qs; |
628 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
629 | |
630 | if (!np || !of_device_is_available(np)) | |
631 | return -ENODEV; | |
632 | ||
fba4ed03 SG |
633 | /* parse the num of tx and rx queues */ |
634 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
635 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
636 | ||
637 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
638 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
639 | num_tx_qs, MAX_TX_QS); | |
640 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
641 | return -EINVAL; |
642 | } | |
643 | ||
644 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
645 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
646 | ||
647 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
648 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
649 | num_rx_qs, MAX_RX_QS); | |
650 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
651 | return -EINVAL; |
652 | } | |
653 | ||
654 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
655 | dev = *pdev; | |
656 | if (NULL == dev) | |
657 | return -ENOMEM; | |
658 | ||
659 | priv = netdev_priv(dev); | |
fba4ed03 SG |
660 | priv->ndev = dev; |
661 | ||
fba4ed03 | 662 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 663 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 664 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 665 | priv->num_grps = 0x0; |
b31a1d8b | 666 | |
0977f817 | 667 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
668 | INIT_LIST_HEAD(&priv->rx_list.list); |
669 | priv->rx_list.count = 0; | |
670 | mutex_init(&priv->rx_queue_access); | |
671 | ||
b31a1d8b AF |
672 | model = of_get_property(np, "model", NULL); |
673 | ||
46ceb60c SG |
674 | for (i = 0; i < MAXGROUPS; i++) |
675 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 676 | |
46ceb60c SG |
677 | /* Parse and initialize group specific information */ |
678 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
679 | priv->mode = MQ_MG_MODE; | |
680 | for_each_child_of_node(np, child) { | |
681 | err = gfar_parse_group(child, priv, model); | |
682 | if (err) | |
683 | goto err_grp_init; | |
b31a1d8b | 684 | } |
46ceb60c SG |
685 | } else { |
686 | priv->mode = SQ_SG_MODE; | |
687 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 688 | if (err) |
46ceb60c | 689 | goto err_grp_init; |
b31a1d8b AF |
690 | } |
691 | ||
fba4ed03 SG |
692 | for (i = 0; i < priv->num_tx_queues; i++) |
693 | priv->tx_queue[i] = NULL; | |
694 | for (i = 0; i < priv->num_rx_queues; i++) | |
695 | priv->rx_queue[i] = NULL; | |
696 | ||
697 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
698 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
699 | GFP_KERNEL); | |
fba4ed03 SG |
700 | if (!priv->tx_queue[i]) { |
701 | err = -ENOMEM; | |
702 | goto tx_alloc_failed; | |
703 | } | |
704 | priv->tx_queue[i]->tx_skbuff = NULL; | |
705 | priv->tx_queue[i]->qindex = i; | |
706 | priv->tx_queue[i]->dev = dev; | |
707 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
708 | } | |
709 | ||
710 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
711 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
712 | GFP_KERNEL); | |
fba4ed03 SG |
713 | if (!priv->rx_queue[i]) { |
714 | err = -ENOMEM; | |
715 | goto rx_alloc_failed; | |
716 | } | |
717 | priv->rx_queue[i]->rx_skbuff = NULL; | |
718 | priv->rx_queue[i]->qindex = i; | |
719 | priv->rx_queue[i]->dev = dev; | |
720 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
721 | } | |
722 | ||
723 | ||
4d7902f2 AF |
724 | stash = of_get_property(np, "bd-stash", NULL); |
725 | ||
a12f801d | 726 | if (stash) { |
4d7902f2 AF |
727 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
728 | priv->bd_stash_en = 1; | |
729 | } | |
730 | ||
731 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
732 | ||
733 | if (stash_len) | |
734 | priv->rx_stash_size = *stash_len; | |
735 | ||
736 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
737 | ||
738 | if (stash_idx) | |
739 | priv->rx_stash_index = *stash_idx; | |
740 | ||
741 | if (stash_len || stash_idx) | |
742 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
743 | ||
b31a1d8b | 744 | mac_addr = of_get_mac_address(np); |
bc4598bc | 745 | |
b31a1d8b | 746 | if (mac_addr) |
6a3c910c | 747 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
748 | |
749 | if (model && !strcasecmp(model, "TSEC")) | |
bc4598bc JC |
750 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
751 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
752 | FSL_GIANFAR_DEV_HAS_RMON | | |
753 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
754 | ||
b31a1d8b | 755 | if (model && !strcasecmp(model, "eTSEC")) |
bc4598bc JC |
756 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
757 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
758 | FSL_GIANFAR_DEV_HAS_RMON | | |
759 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
760 | FSL_GIANFAR_DEV_HAS_PADDING | | |
761 | FSL_GIANFAR_DEV_HAS_CSUM | | |
762 | FSL_GIANFAR_DEV_HAS_VLAN | | |
763 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
764 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
765 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
766 | |
767 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
768 | ||
769 | /* We only care about rgmii-id. The rest are autodetected */ | |
770 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
771 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
772 | else | |
773 | priv->interface = PHY_INTERFACE_MODE_MII; | |
774 | ||
775 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
776 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
777 | ||
fe192a49 | 778 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
779 | |
780 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 781 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
782 | |
783 | return 0; | |
784 | ||
fba4ed03 SG |
785 | rx_alloc_failed: |
786 | free_rx_pointers(priv); | |
787 | tx_alloc_failed: | |
788 | free_tx_pointers(priv); | |
46ceb60c SG |
789 | err_grp_init: |
790 | unmap_group_regs(priv); | |
ee873fda | 791 | free_gfar_dev(priv); |
b31a1d8b AF |
792 | return err; |
793 | } | |
794 | ||
cc772ab7 | 795 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
bc4598bc | 796 | struct ifreq *ifr, int cmd) |
cc772ab7 MR |
797 | { |
798 | struct hwtstamp_config config; | |
799 | struct gfar_private *priv = netdev_priv(netdev); | |
800 | ||
801 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
802 | return -EFAULT; | |
803 | ||
804 | /* reserved for future extensions */ | |
805 | if (config.flags) | |
806 | return -EINVAL; | |
807 | ||
f0ee7acf MR |
808 | switch (config.tx_type) { |
809 | case HWTSTAMP_TX_OFF: | |
810 | priv->hwts_tx_en = 0; | |
811 | break; | |
812 | case HWTSTAMP_TX_ON: | |
813 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
814 | return -ERANGE; | |
815 | priv->hwts_tx_en = 1; | |
816 | break; | |
817 | default: | |
cc772ab7 | 818 | return -ERANGE; |
f0ee7acf | 819 | } |
cc772ab7 MR |
820 | |
821 | switch (config.rx_filter) { | |
822 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
823 | if (priv->hwts_rx_en) { |
824 | stop_gfar(netdev); | |
825 | priv->hwts_rx_en = 0; | |
826 | startup_gfar(netdev); | |
827 | } | |
cc772ab7 MR |
828 | break; |
829 | default: | |
830 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
831 | return -ERANGE; | |
97553f7f MR |
832 | if (!priv->hwts_rx_en) { |
833 | stop_gfar(netdev); | |
834 | priv->hwts_rx_en = 1; | |
835 | startup_gfar(netdev); | |
836 | } | |
cc772ab7 MR |
837 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
838 | break; | |
839 | } | |
840 | ||
841 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
842 | -EFAULT : 0; | |
843 | } | |
844 | ||
0faac9f7 CW |
845 | /* Ioctl MII Interface */ |
846 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
847 | { | |
848 | struct gfar_private *priv = netdev_priv(dev); | |
849 | ||
850 | if (!netif_running(dev)) | |
851 | return -EINVAL; | |
852 | ||
cc772ab7 MR |
853 | if (cmd == SIOCSHWTSTAMP) |
854 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
855 | ||
0faac9f7 CW |
856 | if (!priv->phydev) |
857 | return -ENODEV; | |
858 | ||
28b04113 | 859 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
860 | } |
861 | ||
fba4ed03 SG |
862 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
863 | { | |
864 | unsigned int new_bit_map = 0x0; | |
865 | int mask = 0x1 << (max_qs - 1), i; | |
bc4598bc | 866 | |
fba4ed03 SG |
867 | for (i = 0; i < max_qs; i++) { |
868 | if (bit_map & mask) | |
869 | new_bit_map = new_bit_map + (1 << i); | |
870 | mask = mask >> 0x1; | |
871 | } | |
872 | return new_bit_map; | |
873 | } | |
7a8b3372 | 874 | |
18294ad1 AV |
875 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
876 | u32 class) | |
7a8b3372 SG |
877 | { |
878 | u32 rqfpr = FPR_FILER_MASK; | |
879 | u32 rqfcr = 0x0; | |
880 | ||
881 | rqfar--; | |
882 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
883 | priv->ftp_rqfpr[rqfar] = rqfpr; |
884 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
885 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
886 | ||
887 | rqfar--; | |
888 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
889 | priv->ftp_rqfpr[rqfar] = rqfpr; |
890 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
891 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
892 | ||
893 | rqfar--; | |
894 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
895 | rqfpr = class; | |
6c43e046 WJB |
896 | priv->ftp_rqfcr[rqfar] = rqfcr; |
897 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
898 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
899 | ||
900 | rqfar--; | |
901 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
902 | rqfpr = class; | |
6c43e046 WJB |
903 | priv->ftp_rqfcr[rqfar] = rqfcr; |
904 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
905 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
906 | ||
907 | return rqfar; | |
908 | } | |
909 | ||
910 | static void gfar_init_filer_table(struct gfar_private *priv) | |
911 | { | |
912 | int i = 0x0; | |
913 | u32 rqfar = MAX_FILER_IDX; | |
914 | u32 rqfcr = 0x0; | |
915 | u32 rqfpr = FPR_FILER_MASK; | |
916 | ||
917 | /* Default rule */ | |
918 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
919 | priv->ftp_rqfcr[rqfar] = rqfcr; |
920 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
921 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
922 | ||
923 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
924 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
925 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
926 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
927 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
928 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
929 | ||
85dd08eb | 930 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
931 | priv->cur_filer_idx = rqfar; |
932 | ||
933 | /* Rest are masked rules */ | |
934 | rqfcr = RQFCR_CMP_NOMATCH; | |
935 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
936 | priv->ftp_rqfcr[i] = rqfcr; |
937 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
938 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
939 | } | |
940 | } | |
941 | ||
7d350977 AV |
942 | static void gfar_detect_errata(struct gfar_private *priv) |
943 | { | |
944 | struct device *dev = &priv->ofdev->dev; | |
945 | unsigned int pvr = mfspr(SPRN_PVR); | |
946 | unsigned int svr = mfspr(SPRN_SVR); | |
947 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
948 | unsigned int rev = svr & 0xffff; | |
949 | ||
950 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
951 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 952 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
953 | priv->errata |= GFAR_ERRATA_74; |
954 | ||
deb90eac AV |
955 | /* MPC8313 and MPC837x all rev */ |
956 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 957 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
958 | priv->errata |= GFAR_ERRATA_76; |
959 | ||
511d934f AV |
960 | /* MPC8313 and MPC837x all rev */ |
961 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 962 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
511d934f AV |
963 | priv->errata |= GFAR_ERRATA_A002; |
964 | ||
4363c2fd AD |
965 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
966 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
bc4598bc | 967 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) |
4363c2fd AD |
968 | priv->errata |= GFAR_ERRATA_12; |
969 | ||
7d350977 AV |
970 | if (priv->errata) |
971 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
972 | priv->errata); | |
973 | } | |
974 | ||
bb40dcbb | 975 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
976 | * and anything else we need before we start |
977 | */ | |
74888760 | 978 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
979 | { |
980 | u32 tempval; | |
981 | struct net_device *dev = NULL; | |
982 | struct gfar_private *priv = NULL; | |
f4983704 | 983 | struct gfar __iomem *regs = NULL; |
46ceb60c | 984 | int err = 0, i, grp_idx = 0; |
fba4ed03 | 985 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 986 | u32 isrg = 0; |
18294ad1 | 987 | u32 __iomem *baddr; |
1da177e4 | 988 | |
fba4ed03 | 989 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 990 | |
fba4ed03 SG |
991 | if (err) |
992 | return err; | |
1da177e4 LT |
993 | |
994 | priv = netdev_priv(dev); | |
4826857f KG |
995 | priv->ndev = dev; |
996 | priv->ofdev = ofdev; | |
369ec162 | 997 | priv->dev = &ofdev->dev; |
4826857f | 998 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 999 | |
d87eb127 | 1000 | spin_lock_init(&priv->bflock); |
ab939905 | 1001 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 1002 | |
b31a1d8b | 1003 | dev_set_drvdata(&ofdev->dev, priv); |
46ceb60c | 1004 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1005 | |
7d350977 AV |
1006 | gfar_detect_errata(priv); |
1007 | ||
0977f817 JC |
1008 | /* Stop the DMA engine now, in case it was running before |
1009 | * (The firmware could have used it, and left it running). | |
1010 | */ | |
257d938a | 1011 | gfar_halt(dev); |
1da177e4 LT |
1012 | |
1013 | /* Reset MAC layer */ | |
f4983704 | 1014 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 1015 | |
b98ac702 AF |
1016 | /* We need to delay at least 3 TX clocks */ |
1017 | udelay(2); | |
1018 | ||
1da177e4 | 1019 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 1020 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1021 | |
1022 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1023 | tempval = MACCFG2_INIT_SETTINGS; |
1024 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1025 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1026 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1027 | |
1028 | /* Initialize ECNTRL */ | |
f4983704 | 1029 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1030 | |
1da177e4 | 1031 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1032 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1033 | |
1da177e4 | 1034 | /* Fill in the dev structure */ |
1da177e4 | 1035 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1036 | dev->mtu = 1500; |
26ccfc37 | 1037 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1038 | dev->ethtool_ops = &gfar_ethtool_ops; |
1039 | ||
fba4ed03 | 1040 | /* Register for napi ...We are registering NAPI for each grp */ |
46ceb60c | 1041 | for (i = 0; i < priv->num_grps; i++) |
bc4598bc JC |
1042 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, |
1043 | GFAR_DEV_WEIGHT); | |
a12f801d | 1044 | |
b31a1d8b | 1045 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1046 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1047 | NETIF_F_RXCSUM; |
8b3afe95 | 1048 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1049 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1050 | } |
0bbaf069 | 1051 | |
87c288c6 JP |
1052 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
1053 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
e2c53be2 | 1054 | dev->features |= NETIF_F_HW_VLAN_RX; |
87c288c6 | 1055 | } |
0bbaf069 | 1056 | |
b31a1d8b | 1057 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1058 | priv->extended_hash = 1; |
1059 | priv->hash_width = 9; | |
1060 | ||
f4983704 SG |
1061 | priv->hash_regs[0] = ®s->igaddr0; |
1062 | priv->hash_regs[1] = ®s->igaddr1; | |
1063 | priv->hash_regs[2] = ®s->igaddr2; | |
1064 | priv->hash_regs[3] = ®s->igaddr3; | |
1065 | priv->hash_regs[4] = ®s->igaddr4; | |
1066 | priv->hash_regs[5] = ®s->igaddr5; | |
1067 | priv->hash_regs[6] = ®s->igaddr6; | |
1068 | priv->hash_regs[7] = ®s->igaddr7; | |
1069 | priv->hash_regs[8] = ®s->gaddr0; | |
1070 | priv->hash_regs[9] = ®s->gaddr1; | |
1071 | priv->hash_regs[10] = ®s->gaddr2; | |
1072 | priv->hash_regs[11] = ®s->gaddr3; | |
1073 | priv->hash_regs[12] = ®s->gaddr4; | |
1074 | priv->hash_regs[13] = ®s->gaddr5; | |
1075 | priv->hash_regs[14] = ®s->gaddr6; | |
1076 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1077 | |
1078 | } else { | |
1079 | priv->extended_hash = 0; | |
1080 | priv->hash_width = 8; | |
1081 | ||
f4983704 SG |
1082 | priv->hash_regs[0] = ®s->gaddr0; |
1083 | priv->hash_regs[1] = ®s->gaddr1; | |
1084 | priv->hash_regs[2] = ®s->gaddr2; | |
1085 | priv->hash_regs[3] = ®s->gaddr3; | |
1086 | priv->hash_regs[4] = ®s->gaddr4; | |
1087 | priv->hash_regs[5] = ®s->gaddr5; | |
1088 | priv->hash_regs[6] = ®s->gaddr6; | |
1089 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1090 | } |
1091 | ||
b31a1d8b | 1092 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1093 | priv->padding = DEFAULT_PADDING; |
1094 | else | |
1095 | priv->padding = 0; | |
1096 | ||
cc772ab7 | 1097 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1098 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1099 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 | 1100 | |
46ceb60c SG |
1101 | /* Program the isrg regs only if number of grps > 1 */ |
1102 | if (priv->num_grps > 1) { | |
1103 | baddr = ®s->isrg0; | |
1104 | for (i = 0; i < priv->num_grps; i++) { | |
1105 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1106 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1107 | gfar_write(baddr, isrg); | |
1108 | baddr++; | |
1109 | isrg = 0x0; | |
1110 | } | |
1111 | } | |
1112 | ||
fba4ed03 | 1113 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1114 | * but, for_each_set_bit parses from right to left, which |
0977f817 JC |
1115 | * basically reverses the queue numbers |
1116 | */ | |
46ceb60c | 1117 | for (i = 0; i< priv->num_grps; i++) { |
bc4598bc JC |
1118 | priv->gfargrp[i].tx_bit_map = |
1119 | reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1120 | priv->gfargrp[i].rx_bit_map = | |
1121 | reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
46ceb60c SG |
1122 | } |
1123 | ||
1124 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
0977f817 JC |
1125 | * also assign queues to groups |
1126 | */ | |
46ceb60c SG |
1127 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { |
1128 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
bc4598bc | 1129 | |
984b3f57 | 1130 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
bc4598bc | 1131 | priv->num_rx_queues) { |
46ceb60c SG |
1132 | priv->gfargrp[grp_idx].num_rx_queues++; |
1133 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1134 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1135 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1136 | } | |
1137 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
bc4598bc | 1138 | |
984b3f57 | 1139 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
bc4598bc | 1140 | priv->num_tx_queues) { |
46ceb60c SG |
1141 | priv->gfargrp[grp_idx].num_tx_queues++; |
1142 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1143 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1144 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1145 | } | |
1146 | priv->gfargrp[grp_idx].rstat = rstat; | |
1147 | priv->gfargrp[grp_idx].tstat = tstat; | |
1148 | rstat = tstat =0; | |
fba4ed03 | 1149 | } |
fba4ed03 SG |
1150 | |
1151 | gfar_write(®s->rqueue, rqueue); | |
1152 | gfar_write(®s->tqueue, tqueue); | |
1153 | ||
1da177e4 | 1154 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1155 | |
a12f801d | 1156 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1157 | for (i = 0; i < priv->num_tx_queues; i++) { |
1158 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1159 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1160 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1161 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1162 | } | |
a12f801d | 1163 | |
fba4ed03 SG |
1164 | for (i = 0; i < priv->num_rx_queues; i++) { |
1165 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1166 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1167 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1168 | } | |
1da177e4 | 1169 | |
0977f817 | 1170 | /* always enable rx filer */ |
4aa3a715 | 1171 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1172 | /* Enable most messages by default */ |
1173 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
b98b8bab CM |
1174 | /* use pritority h/w tx queue scheduling for single queue devices */ |
1175 | if (priv->num_tx_queues == 1) | |
1176 | priv->prio_sched_en = 1; | |
0bbaf069 | 1177 | |
d3eab82b TP |
1178 | /* Carrier starts down, phylib will bring it up */ |
1179 | netif_carrier_off(dev); | |
1180 | ||
1da177e4 LT |
1181 | err = register_netdev(dev); |
1182 | ||
1183 | if (err) { | |
59deab26 | 1184 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1185 | goto register_fail; |
1186 | } | |
1187 | ||
2884e5cc | 1188 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1189 | priv->device_flags & |
1190 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1191 | |
c50a5d9a | 1192 | /* fill out IRQ number and name fields */ |
46ceb60c | 1193 | for (i = 0; i < priv->num_grps; i++) { |
ee873fda | 1194 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
46ceb60c | 1195 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
ee873fda | 1196 | sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", |
0015e551 | 1197 | dev->name, "_g", '0' + i, "_tx"); |
ee873fda | 1198 | sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", |
0015e551 | 1199 | dev->name, "_g", '0' + i, "_rx"); |
ee873fda | 1200 | sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", |
0015e551 | 1201 | dev->name, "_g", '0' + i, "_er"); |
46ceb60c | 1202 | } else |
ee873fda | 1203 | strcpy(gfar_irq(grp, TX)->name, dev->name); |
46ceb60c | 1204 | } |
c50a5d9a | 1205 | |
7a8b3372 SG |
1206 | /* Initialize the filer table */ |
1207 | gfar_init_filer_table(priv); | |
1208 | ||
7f7f5316 AF |
1209 | /* Create all the sysfs files */ |
1210 | gfar_init_sysfs(dev); | |
1211 | ||
1da177e4 | 1212 | /* Print out the device info */ |
59deab26 | 1213 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1214 | |
0977f817 JC |
1215 | /* Even more device info helps when determining which kernel |
1216 | * provided which set of benchmarks. | |
1217 | */ | |
59deab26 | 1218 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1219 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1220 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1221 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1222 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1223 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1224 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1225 | |
1226 | return 0; | |
1227 | ||
1228 | register_fail: | |
46ceb60c | 1229 | unmap_group_regs(priv); |
fba4ed03 SG |
1230 | free_tx_pointers(priv); |
1231 | free_rx_pointers(priv); | |
fe192a49 GL |
1232 | if (priv->phy_node) |
1233 | of_node_put(priv->phy_node); | |
1234 | if (priv->tbi_node) | |
1235 | of_node_put(priv->tbi_node); | |
ee873fda | 1236 | free_gfar_dev(priv); |
bb40dcbb | 1237 | return err; |
1da177e4 LT |
1238 | } |
1239 | ||
2dc11581 | 1240 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1241 | { |
b31a1d8b | 1242 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 1243 | |
fe192a49 GL |
1244 | if (priv->phy_node) |
1245 | of_node_put(priv->phy_node); | |
1246 | if (priv->tbi_node) | |
1247 | of_node_put(priv->tbi_node); | |
1248 | ||
b31a1d8b | 1249 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 1250 | |
d9d8e041 | 1251 | unregister_netdev(priv->ndev); |
46ceb60c | 1252 | unmap_group_regs(priv); |
ee873fda | 1253 | free_gfar_dev(priv); |
1da177e4 LT |
1254 | |
1255 | return 0; | |
1256 | } | |
1257 | ||
d87eb127 | 1258 | #ifdef CONFIG_PM |
be926fc4 AV |
1259 | |
1260 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1261 | { |
be926fc4 AV |
1262 | struct gfar_private *priv = dev_get_drvdata(dev); |
1263 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1264 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1265 | unsigned long flags; |
1266 | u32 tempval; | |
1267 | ||
1268 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1269 | (priv->device_flags & |
1270 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1271 | |
be926fc4 | 1272 | netif_device_detach(ndev); |
d87eb127 | 1273 | |
be926fc4 | 1274 | if (netif_running(ndev)) { |
fba4ed03 SG |
1275 | |
1276 | local_irq_save(flags); | |
1277 | lock_tx_qs(priv); | |
1278 | lock_rx_qs(priv); | |
d87eb127 | 1279 | |
be926fc4 | 1280 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1281 | |
1282 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1283 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1284 | |
1285 | tempval &= ~MACCFG1_TX_EN; | |
1286 | ||
1287 | if (!magic_packet) | |
1288 | tempval &= ~MACCFG1_RX_EN; | |
1289 | ||
f4983704 | 1290 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1291 | |
fba4ed03 SG |
1292 | unlock_rx_qs(priv); |
1293 | unlock_tx_qs(priv); | |
1294 | local_irq_restore(flags); | |
d87eb127 | 1295 | |
46ceb60c | 1296 | disable_napi(priv); |
d87eb127 SW |
1297 | |
1298 | if (magic_packet) { | |
1299 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1300 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1301 | |
1302 | /* Enable Magic Packet mode */ | |
f4983704 | 1303 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1304 | tempval |= MACCFG2_MPEN; |
f4983704 | 1305 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1306 | } else { |
1307 | phy_stop(priv->phydev); | |
1308 | } | |
1309 | } | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
be926fc4 | 1314 | static int gfar_resume(struct device *dev) |
d87eb127 | 1315 | { |
be926fc4 AV |
1316 | struct gfar_private *priv = dev_get_drvdata(dev); |
1317 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1318 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1319 | unsigned long flags; |
1320 | u32 tempval; | |
1321 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1322 | (priv->device_flags & |
1323 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1324 | |
be926fc4 AV |
1325 | if (!netif_running(ndev)) { |
1326 | netif_device_attach(ndev); | |
d87eb127 SW |
1327 | return 0; |
1328 | } | |
1329 | ||
1330 | if (!magic_packet && priv->phydev) | |
1331 | phy_start(priv->phydev); | |
1332 | ||
1333 | /* Disable Magic Packet mode, in case something | |
1334 | * else woke us up. | |
1335 | */ | |
fba4ed03 SG |
1336 | local_irq_save(flags); |
1337 | lock_tx_qs(priv); | |
1338 | lock_rx_qs(priv); | |
d87eb127 | 1339 | |
f4983704 | 1340 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1341 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1342 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1343 | |
be926fc4 | 1344 | gfar_start(ndev); |
d87eb127 | 1345 | |
fba4ed03 SG |
1346 | unlock_rx_qs(priv); |
1347 | unlock_tx_qs(priv); | |
1348 | local_irq_restore(flags); | |
d87eb127 | 1349 | |
be926fc4 AV |
1350 | netif_device_attach(ndev); |
1351 | ||
46ceb60c | 1352 | enable_napi(priv); |
be926fc4 AV |
1353 | |
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | static int gfar_restore(struct device *dev) | |
1358 | { | |
1359 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1360 | struct net_device *ndev = priv->ndev; | |
1361 | ||
103cdd1d WD |
1362 | if (!netif_running(ndev)) { |
1363 | netif_device_attach(ndev); | |
1364 | ||
be926fc4 | 1365 | return 0; |
103cdd1d | 1366 | } |
be926fc4 | 1367 | |
1eb8f7a7 CM |
1368 | if (gfar_init_bds(ndev)) { |
1369 | free_skb_resources(priv); | |
1370 | return -ENOMEM; | |
1371 | } | |
1372 | ||
be926fc4 AV |
1373 | init_registers(ndev); |
1374 | gfar_set_mac_address(ndev); | |
1375 | gfar_init_mac(ndev); | |
1376 | gfar_start(ndev); | |
1377 | ||
1378 | priv->oldlink = 0; | |
1379 | priv->oldspeed = 0; | |
1380 | priv->oldduplex = -1; | |
1381 | ||
1382 | if (priv->phydev) | |
1383 | phy_start(priv->phydev); | |
d87eb127 | 1384 | |
be926fc4 | 1385 | netif_device_attach(ndev); |
5ea681d4 | 1386 | enable_napi(priv); |
d87eb127 SW |
1387 | |
1388 | return 0; | |
1389 | } | |
be926fc4 AV |
1390 | |
1391 | static struct dev_pm_ops gfar_pm_ops = { | |
1392 | .suspend = gfar_suspend, | |
1393 | .resume = gfar_resume, | |
1394 | .freeze = gfar_suspend, | |
1395 | .thaw = gfar_resume, | |
1396 | .restore = gfar_restore, | |
1397 | }; | |
1398 | ||
1399 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1400 | ||
d87eb127 | 1401 | #else |
be926fc4 AV |
1402 | |
1403 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1404 | |
d87eb127 | 1405 | #endif |
1da177e4 | 1406 | |
e8a2b6a4 AF |
1407 | /* Reads the controller's registers to determine what interface |
1408 | * connects it to the PHY. | |
1409 | */ | |
1410 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1411 | { | |
1412 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1413 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1414 | u32 ecntrl; |
1415 | ||
f4983704 | 1416 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1417 | |
1418 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1419 | return PHY_INTERFACE_MODE_SGMII; | |
1420 | ||
1421 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1422 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1423 | return PHY_INTERFACE_MODE_RTBI; | |
1424 | else | |
1425 | return PHY_INTERFACE_MODE_TBI; | |
1426 | } | |
1427 | ||
1428 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1429 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1430 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1431 | } |
7132ab7f | 1432 | else { |
b31a1d8b | 1433 | phy_interface_t interface = priv->interface; |
7132ab7f | 1434 | |
0977f817 | 1435 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1436 | * be set by the device tree or platform code. |
1437 | */ | |
1438 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1439 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1440 | ||
e8a2b6a4 | 1441 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1442 | } |
e8a2b6a4 AF |
1443 | } |
1444 | ||
b31a1d8b | 1445 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1446 | return PHY_INTERFACE_MODE_GMII; |
1447 | ||
1448 | return PHY_INTERFACE_MODE_MII; | |
1449 | } | |
1450 | ||
1451 | ||
bb40dcbb AF |
1452 | /* Initializes driver's PHY state, and attaches to the PHY. |
1453 | * Returns 0 on success. | |
1da177e4 LT |
1454 | */ |
1455 | static int init_phy(struct net_device *dev) | |
1456 | { | |
1457 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1458 | uint gigabit_support = |
b31a1d8b | 1459 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1460 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1461 | phy_interface_t interface; |
1da177e4 LT |
1462 | |
1463 | priv->oldlink = 0; | |
1464 | priv->oldspeed = 0; | |
1465 | priv->oldduplex = -1; | |
1466 | ||
e8a2b6a4 AF |
1467 | interface = gfar_get_interface(dev); |
1468 | ||
1db780f8 AV |
1469 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1470 | interface); | |
1471 | if (!priv->phydev) | |
1472 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1473 | interface); | |
1474 | if (!priv->phydev) { | |
1475 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1476 | return -ENODEV; | |
fe192a49 | 1477 | } |
1da177e4 | 1478 | |
d3c12873 KJ |
1479 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1480 | gfar_configure_serdes(dev); | |
1481 | ||
bb40dcbb | 1482 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1483 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1484 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1485 | |
1486 | return 0; | |
1da177e4 LT |
1487 | } |
1488 | ||
0977f817 | 1489 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1490 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1491 | * through the MDIO bus on each controller, treating it as a | |
1492 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1493 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1494 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1495 | * value doesn't matter, as there are no other PHYs on the bus. | |
1496 | */ | |
d3c12873 KJ |
1497 | static void gfar_configure_serdes(struct net_device *dev) |
1498 | { | |
1499 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1500 | struct phy_device *tbiphy; |
1501 | ||
1502 | if (!priv->tbi_node) { | |
1503 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1504 | "device tree specify a tbi-handle\n"); | |
1505 | return; | |
1506 | } | |
c132419e | 1507 | |
fe192a49 GL |
1508 | tbiphy = of_phy_find_device(priv->tbi_node); |
1509 | if (!tbiphy) { | |
1510 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1511 | return; |
1512 | } | |
d3c12873 | 1513 | |
0977f817 | 1514 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1515 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1516 | * everything for us? Resetting it takes the link down and requires | |
1517 | * several seconds for it to come back. | |
1518 | */ | |
fe192a49 | 1519 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1520 | return; |
d3c12873 | 1521 | |
d0313587 | 1522 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1523 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1524 | |
fe192a49 | 1525 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1526 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1527 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1528 | |
bc4598bc JC |
1529 | phy_write(tbiphy, MII_BMCR, |
1530 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1531 | BMCR_SPEED1000); | |
d3c12873 KJ |
1532 | } |
1533 | ||
1da177e4 LT |
1534 | static void init_registers(struct net_device *dev) |
1535 | { | |
1536 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1537 | struct gfar __iomem *regs = NULL; |
3a2e16c8 | 1538 | int i; |
1da177e4 | 1539 | |
46ceb60c SG |
1540 | for (i = 0; i < priv->num_grps; i++) { |
1541 | regs = priv->gfargrp[i].regs; | |
1542 | /* Clear IEVENT */ | |
1543 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1544 | |
46ceb60c SG |
1545 | /* Initialize IMASK */ |
1546 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1547 | } | |
1da177e4 | 1548 | |
46ceb60c | 1549 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1550 | /* Init hash registers to zero */ |
f4983704 SG |
1551 | gfar_write(®s->igaddr0, 0); |
1552 | gfar_write(®s->igaddr1, 0); | |
1553 | gfar_write(®s->igaddr2, 0); | |
1554 | gfar_write(®s->igaddr3, 0); | |
1555 | gfar_write(®s->igaddr4, 0); | |
1556 | gfar_write(®s->igaddr5, 0); | |
1557 | gfar_write(®s->igaddr6, 0); | |
1558 | gfar_write(®s->igaddr7, 0); | |
1559 | ||
1560 | gfar_write(®s->gaddr0, 0); | |
1561 | gfar_write(®s->gaddr1, 0); | |
1562 | gfar_write(®s->gaddr2, 0); | |
1563 | gfar_write(®s->gaddr3, 0); | |
1564 | gfar_write(®s->gaddr4, 0); | |
1565 | gfar_write(®s->gaddr5, 0); | |
1566 | gfar_write(®s->gaddr6, 0); | |
1567 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1568 | |
1da177e4 | 1569 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1570 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1571 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1572 | |
1573 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1574 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1575 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1576 | } |
1577 | ||
1578 | /* Initialize the max receive buffer length */ | |
f4983704 | 1579 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1580 | |
1da177e4 | 1581 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1582 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1583 | } |
1584 | ||
511d934f AV |
1585 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1586 | { | |
1587 | u32 res; | |
1588 | ||
0977f817 | 1589 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1590 | * actually wait for IEVENT_GRSC flag. |
1591 | */ | |
1592 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1593 | return 0; | |
1594 | ||
0977f817 | 1595 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1596 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1597 | * and the Rx can be safely reset. | |
1598 | */ | |
1599 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1600 | res &= 0x7f807f80; | |
1601 | if ((res & 0xffff) == (res >> 16)) | |
1602 | return 1; | |
1603 | ||
1604 | return 0; | |
1605 | } | |
0bbaf069 KG |
1606 | |
1607 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1608 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1609 | { |
1610 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1611 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1612 | u32 tempval; |
3a2e16c8 | 1613 | int i; |
1da177e4 | 1614 | |
46ceb60c SG |
1615 | for (i = 0; i < priv->num_grps; i++) { |
1616 | regs = priv->gfargrp[i].regs; | |
1617 | /* Mask all interrupts */ | |
1618 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1619 | |
46ceb60c SG |
1620 | /* Clear all interrupts */ |
1621 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1622 | } | |
1da177e4 | 1623 | |
46ceb60c | 1624 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1625 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1626 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1627 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1628 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1629 | int ret; |
1630 | ||
1da177e4 | 1631 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1632 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1633 | |
511d934f AV |
1634 | do { |
1635 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1636 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1637 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1638 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1639 | ret = __gfar_is_rx_idle(priv); | |
1640 | } while (!ret); | |
1da177e4 | 1641 | } |
d87eb127 | 1642 | } |
d87eb127 SW |
1643 | |
1644 | /* Halt the receive and transmit queues */ | |
1645 | void gfar_halt(struct net_device *dev) | |
1646 | { | |
1647 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1648 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1649 | u32 tempval; |
1da177e4 | 1650 | |
2a54adc3 SW |
1651 | gfar_halt_nodisable(dev); |
1652 | ||
1da177e4 LT |
1653 | /* Disable Rx and Tx */ |
1654 | tempval = gfar_read(®s->maccfg1); | |
1655 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1656 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1657 | } |
1658 | ||
46ceb60c SG |
1659 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1660 | { | |
ee873fda CM |
1661 | free_irq(gfar_irq(grp, TX)->irq, grp); |
1662 | free_irq(gfar_irq(grp, RX)->irq, grp); | |
1663 | free_irq(gfar_irq(grp, ER)->irq, grp); | |
46ceb60c SG |
1664 | } |
1665 | ||
0bbaf069 KG |
1666 | void stop_gfar(struct net_device *dev) |
1667 | { | |
1668 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1669 | unsigned long flags; |
46ceb60c | 1670 | int i; |
0bbaf069 | 1671 | |
bb40dcbb AF |
1672 | phy_stop(priv->phydev); |
1673 | ||
a12f801d | 1674 | |
0bbaf069 | 1675 | /* Lock it down */ |
fba4ed03 SG |
1676 | local_irq_save(flags); |
1677 | lock_tx_qs(priv); | |
1678 | lock_rx_qs(priv); | |
0bbaf069 | 1679 | |
0bbaf069 | 1680 | gfar_halt(dev); |
1da177e4 | 1681 | |
fba4ed03 SG |
1682 | unlock_rx_qs(priv); |
1683 | unlock_tx_qs(priv); | |
1684 | local_irq_restore(flags); | |
1da177e4 LT |
1685 | |
1686 | /* Free the IRQs */ | |
b31a1d8b | 1687 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1688 | for (i = 0; i < priv->num_grps; i++) |
1689 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1690 | } else { |
46ceb60c | 1691 | for (i = 0; i < priv->num_grps; i++) |
ee873fda | 1692 | free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, |
bc4598bc | 1693 | &priv->gfargrp[i]); |
1da177e4 LT |
1694 | } |
1695 | ||
1696 | free_skb_resources(priv); | |
1da177e4 LT |
1697 | } |
1698 | ||
fba4ed03 | 1699 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1700 | { |
1da177e4 | 1701 | struct txbd8 *txbdp; |
fba4ed03 | 1702 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1703 | int i, j; |
1da177e4 | 1704 | |
a12f801d | 1705 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1706 | |
a12f801d SG |
1707 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1708 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1709 | continue; |
1da177e4 | 1710 | |
369ec162 | 1711 | dma_unmap_single(priv->dev, txbdp->bufPtr, |
bc4598bc | 1712 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1713 | txbdp->lstatus = 0; |
fba4ed03 | 1714 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1715 | j++) { |
4669bc90 | 1716 | txbdp++; |
369ec162 | 1717 | dma_unmap_page(priv->dev, txbdp->bufPtr, |
bc4598bc | 1718 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1719 | } |
ad5da7ab | 1720 | txbdp++; |
a12f801d SG |
1721 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1722 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1723 | } |
a12f801d | 1724 | kfree(tx_queue->tx_skbuff); |
1eb8f7a7 | 1725 | tx_queue->tx_skbuff = NULL; |
fba4ed03 | 1726 | } |
1da177e4 | 1727 | |
fba4ed03 SG |
1728 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1729 | { | |
1730 | struct rxbd8 *rxbdp; | |
1731 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1732 | int i; | |
1da177e4 | 1733 | |
fba4ed03 | 1734 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1735 | |
a12f801d SG |
1736 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1737 | if (rx_queue->rx_skbuff[i]) { | |
369ec162 CM |
1738 | dma_unmap_single(priv->dev, rxbdp->bufPtr, |
1739 | priv->rx_buffer_size, | |
bc4598bc | 1740 | DMA_FROM_DEVICE); |
a12f801d SG |
1741 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1742 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1743 | } |
e69edd21 AV |
1744 | rxbdp->lstatus = 0; |
1745 | rxbdp->bufPtr = 0; | |
1746 | rxbdp++; | |
1da177e4 | 1747 | } |
a12f801d | 1748 | kfree(rx_queue->rx_skbuff); |
1eb8f7a7 | 1749 | rx_queue->rx_skbuff = NULL; |
fba4ed03 | 1750 | } |
e69edd21 | 1751 | |
fba4ed03 | 1752 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1753 | * Then free tx_skbuff and rx_skbuff |
1754 | */ | |
fba4ed03 SG |
1755 | static void free_skb_resources(struct gfar_private *priv) |
1756 | { | |
1757 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1758 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1759 | int i; | |
1760 | ||
1761 | /* Go through all the buffer descriptors and free their data buffers */ | |
1762 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1763 | struct netdev_queue *txq; |
bc4598bc | 1764 | |
fba4ed03 | 1765 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1766 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1767 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1768 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1769 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1770 | } |
1771 | ||
1772 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1773 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1774 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1775 | free_skb_rx_queue(rx_queue); |
1776 | } | |
1777 | ||
369ec162 | 1778 | dma_free_coherent(priv->dev, |
bc4598bc JC |
1779 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1780 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1781 | priv->tx_queue[0]->tx_bd_base, | |
1782 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1783 | } |
1784 | ||
0bbaf069 KG |
1785 | void gfar_start(struct net_device *dev) |
1786 | { | |
1787 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1788 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1789 | u32 tempval; |
46ceb60c | 1790 | int i = 0; |
0bbaf069 KG |
1791 | |
1792 | /* Enable Rx and Tx in MACCFG1 */ | |
1793 | tempval = gfar_read(®s->maccfg1); | |
1794 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1795 | gfar_write(®s->maccfg1, tempval); | |
1796 | ||
1797 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1798 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1799 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1800 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1801 | |
0bbaf069 | 1802 | /* Make sure we aren't stopped */ |
f4983704 | 1803 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1804 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1805 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1806 | |
46ceb60c SG |
1807 | for (i = 0; i < priv->num_grps; i++) { |
1808 | regs = priv->gfargrp[i].regs; | |
1809 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1810 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1811 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1812 | /* Unmask the interrupts we look for */ | |
1813 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1814 | } | |
12dea57b | 1815 | |
1ae5dc34 | 1816 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1817 | } |
1818 | ||
46ceb60c | 1819 | void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1820 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1821 | { |
46ceb60c | 1822 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1823 | u32 __iomem *baddr; |
815b97c6 | 1824 | |
46ceb60c | 1825 | if (priv->mode == MQ_MG_MODE) { |
5d9657d8 | 1826 | int i = 0; |
46ceb60c | 1827 | baddr = ®s->txic0; |
984b3f57 | 1828 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
9740e001 CM |
1829 | gfar_write(baddr + i, 0); |
1830 | if (likely(priv->tx_queue[i]->txcoalescing)) | |
46ceb60c | 1831 | gfar_write(baddr + i, priv->tx_queue[i]->txic); |
46ceb60c SG |
1832 | } |
1833 | ||
1834 | baddr = ®s->rxic0; | |
984b3f57 | 1835 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
9740e001 CM |
1836 | gfar_write(baddr + i, 0); |
1837 | if (likely(priv->rx_queue[i]->rxcoalescing)) | |
46ceb60c | 1838 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); |
46ceb60c | 1839 | } |
5d9657d8 CM |
1840 | } else { |
1841 | /* Backward compatible case ---- even if we enable | |
1842 | * multiple queues, there's only single reg to program | |
1843 | */ | |
1844 | gfar_write(®s->txic, 0); | |
1845 | if (likely(priv->tx_queue[0]->txcoalescing)) | |
1846 | gfar_write(®s->txic, priv->tx_queue[0]->txic); | |
1847 | ||
1848 | gfar_write(®s->rxic, 0); | |
1849 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) | |
1850 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); | |
46ceb60c SG |
1851 | } |
1852 | } | |
1853 | ||
1854 | static int register_grp_irqs(struct gfar_priv_grp *grp) | |
1855 | { | |
1856 | struct gfar_private *priv = grp->priv; | |
1857 | struct net_device *dev = priv->ndev; | |
1858 | int err; | |
1da177e4 | 1859 | |
1da177e4 | 1860 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1861 | * them. Otherwise, only register for the one |
1862 | */ | |
b31a1d8b | 1863 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1864 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1865 | * Transmit, and Receive |
1866 | */ | |
ee873fda CM |
1867 | err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, |
1868 | gfar_irq(grp, ER)->name, grp); | |
1869 | if (err < 0) { | |
59deab26 | 1870 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1871 | gfar_irq(grp, ER)->irq); |
46ceb60c | 1872 | |
2145f1af | 1873 | goto err_irq_fail; |
1da177e4 | 1874 | } |
ee873fda CM |
1875 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, |
1876 | gfar_irq(grp, TX)->name, grp); | |
1877 | if (err < 0) { | |
59deab26 | 1878 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1879 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1880 | goto tx_irq_fail; |
1881 | } | |
ee873fda CM |
1882 | err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, |
1883 | gfar_irq(grp, RX)->name, grp); | |
1884 | if (err < 0) { | |
59deab26 | 1885 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1886 | gfar_irq(grp, RX)->irq); |
1da177e4 LT |
1887 | goto rx_irq_fail; |
1888 | } | |
1889 | } else { | |
ee873fda CM |
1890 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, |
1891 | gfar_irq(grp, TX)->name, grp); | |
1892 | if (err < 0) { | |
59deab26 | 1893 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1894 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1895 | goto err_irq_fail; |
1896 | } | |
1897 | } | |
1898 | ||
46ceb60c SG |
1899 | return 0; |
1900 | ||
1901 | rx_irq_fail: | |
ee873fda | 1902 | free_irq(gfar_irq(grp, TX)->irq, grp); |
46ceb60c | 1903 | tx_irq_fail: |
ee873fda | 1904 | free_irq(gfar_irq(grp, ER)->irq, grp); |
46ceb60c SG |
1905 | err_irq_fail: |
1906 | return err; | |
1907 | ||
1908 | } | |
1909 | ||
1910 | /* Bring the controller up and running */ | |
1911 | int startup_gfar(struct net_device *ndev) | |
1912 | { | |
1913 | struct gfar_private *priv = netdev_priv(ndev); | |
1914 | struct gfar __iomem *regs = NULL; | |
1915 | int err, i, j; | |
1916 | ||
1917 | for (i = 0; i < priv->num_grps; i++) { | |
1918 | regs= priv->gfargrp[i].regs; | |
1919 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1920 | } | |
1921 | ||
1922 | regs= priv->gfargrp[0].regs; | |
1923 | err = gfar_alloc_skb_resources(ndev); | |
1924 | if (err) | |
1925 | return err; | |
1926 | ||
1927 | gfar_init_mac(ndev); | |
1928 | ||
1929 | for (i = 0; i < priv->num_grps; i++) { | |
1930 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1931 | if (err) { | |
1932 | for (j = 0; j < i; j++) | |
1933 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1934 | goto irq_fail; |
46ceb60c SG |
1935 | } |
1936 | } | |
1937 | ||
7f7f5316 | 1938 | /* Start the controller */ |
ccc05c6e | 1939 | gfar_start(ndev); |
1da177e4 | 1940 | |
826aa4a0 AV |
1941 | phy_start(priv->phydev); |
1942 | ||
46ceb60c SG |
1943 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
1944 | ||
1da177e4 LT |
1945 | return 0; |
1946 | ||
46ceb60c | 1947 | irq_fail: |
e69edd21 | 1948 | free_skb_resources(priv); |
1da177e4 LT |
1949 | return err; |
1950 | } | |
1951 | ||
0977f817 JC |
1952 | /* Called when something needs to use the ethernet device |
1953 | * Returns 0 for success. | |
1954 | */ | |
1da177e4 LT |
1955 | static int gfar_enet_open(struct net_device *dev) |
1956 | { | |
94e8cc35 | 1957 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1958 | int err; |
1959 | ||
46ceb60c | 1960 | enable_napi(priv); |
bea3348e | 1961 | |
1da177e4 LT |
1962 | /* Initialize a bunch of registers */ |
1963 | init_registers(dev); | |
1964 | ||
1965 | gfar_set_mac_address(dev); | |
1966 | ||
1967 | err = init_phy(dev); | |
1968 | ||
a12f801d | 1969 | if (err) { |
46ceb60c | 1970 | disable_napi(priv); |
1da177e4 | 1971 | return err; |
bea3348e | 1972 | } |
1da177e4 LT |
1973 | |
1974 | err = startup_gfar(dev); | |
db0e8e3f | 1975 | if (err) { |
46ceb60c | 1976 | disable_napi(priv); |
db0e8e3f AV |
1977 | return err; |
1978 | } | |
1da177e4 | 1979 | |
fba4ed03 | 1980 | netif_tx_start_all_queues(dev); |
1da177e4 | 1981 | |
2884e5cc AV |
1982 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1983 | ||
1da177e4 LT |
1984 | return err; |
1985 | } | |
1986 | ||
54dc79fe | 1987 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1988 | { |
54dc79fe | 1989 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1990 | |
1991 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1992 | |
0bbaf069 KG |
1993 | return fcb; |
1994 | } | |
1995 | ||
9c4886e5 | 1996 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 1997 | int fcb_length) |
0bbaf069 | 1998 | { |
0bbaf069 KG |
1999 | /* If we're here, it's a IP packet with a TCP or UDP |
2000 | * payload. We set it to checksum, using a pseudo-header | |
2001 | * we provide | |
2002 | */ | |
3a2e16c8 | 2003 | u8 flags = TXFCB_DEFAULT; |
0bbaf069 | 2004 | |
0977f817 JC |
2005 | /* Tell the controller what the protocol is |
2006 | * And provide the already calculated phcs | |
2007 | */ | |
eddc9ec5 | 2008 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 2009 | flags |= TXFCB_UDP; |
4bedb452 | 2010 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 2011 | } else |
8da32de5 | 2012 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2013 | |
2014 | /* l3os is the distance between the start of the | |
2015 | * frame (skb->data) and the start of the IP hdr. | |
2016 | * l4os is the distance between the start of the | |
0977f817 JC |
2017 | * l3 hdr and the l4 hdr |
2018 | */ | |
9c4886e5 | 2019 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2020 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2021 | |
7f7f5316 | 2022 | fcb->flags = flags; |
0bbaf069 KG |
2023 | } |
2024 | ||
7f7f5316 | 2025 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2026 | { |
7f7f5316 | 2027 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2028 | fcb->vlctl = vlan_tx_tag_get(skb); |
2029 | } | |
2030 | ||
4669bc90 | 2031 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2032 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2033 | { |
2034 | struct txbd8 *new_bd = bdp + stride; | |
2035 | ||
2036 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2037 | } | |
2038 | ||
2039 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2040 | int ring_size) |
4669bc90 DH |
2041 | { |
2042 | return skip_txbd(bdp, 1, base, ring_size); | |
2043 | } | |
2044 | ||
0977f817 JC |
2045 | /* This is called by the kernel when a frame is ready for transmission. |
2046 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2047 | */ | |
1da177e4 LT |
2048 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2049 | { | |
2050 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2051 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2052 | struct netdev_queue *txq; |
f4983704 | 2053 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2054 | struct txfcb *fcb = NULL; |
f0ee7acf | 2055 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2056 | u32 lstatus; |
f0ee7acf | 2057 | int i, rq = 0, do_tstamp = 0; |
4669bc90 | 2058 | u32 bufaddr; |
fef6108d | 2059 | unsigned long flags; |
9c4886e5 | 2060 | unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN; |
fba4ed03 | 2061 | |
0977f817 | 2062 | /* TOE=1 frames larger than 2500 bytes may see excess delays |
deb90eac AV |
2063 | * before start of transmission. |
2064 | */ | |
2065 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && | |
bc4598bc JC |
2066 | skb->ip_summed == CHECKSUM_PARTIAL && |
2067 | skb->len > 2500)) { | |
deb90eac AV |
2068 | int ret; |
2069 | ||
2070 | ret = skb_checksum_help(skb); | |
2071 | if (ret) | |
2072 | return ret; | |
2073 | } | |
2074 | ||
fba4ed03 SG |
2075 | rq = skb->queue_mapping; |
2076 | tx_queue = priv->tx_queue[rq]; | |
2077 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2078 | base = tx_queue->tx_bd_base; |
46ceb60c | 2079 | regs = tx_queue->grp->regs; |
f0ee7acf MR |
2080 | |
2081 | /* check if time stamp should be generated */ | |
2244d07b | 2082 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
bc4598bc | 2083 | priv->hwts_tx_en)) { |
f0ee7acf | 2084 | do_tstamp = 1; |
9c4886e5 MR |
2085 | fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
2086 | } | |
4669bc90 | 2087 | |
5b28beaf LY |
2088 | /* make space for additional header when fcb is needed */ |
2089 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
bc4598bc JC |
2090 | vlan_tx_tag_present(skb) || |
2091 | unlikely(do_tstamp)) && | |
2092 | (skb_headroom(skb) < fcb_length)) { | |
54dc79fe SH |
2093 | struct sk_buff *skb_new; |
2094 | ||
9c4886e5 | 2095 | skb_new = skb_realloc_headroom(skb, fcb_length); |
54dc79fe SH |
2096 | if (!skb_new) { |
2097 | dev->stats.tx_errors++; | |
bd14ba84 | 2098 | kfree_skb(skb); |
54dc79fe SH |
2099 | return NETDEV_TX_OK; |
2100 | } | |
db83d136 | 2101 | |
313b037c ED |
2102 | if (skb->sk) |
2103 | skb_set_owner_w(skb_new, skb->sk); | |
2104 | consume_skb(skb); | |
54dc79fe SH |
2105 | skb = skb_new; |
2106 | } | |
2107 | ||
4669bc90 DH |
2108 | /* total number of fragments in the SKB */ |
2109 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2110 | ||
f0ee7acf MR |
2111 | /* calculate the required number of TxBDs for this skb */ |
2112 | if (unlikely(do_tstamp)) | |
2113 | nr_txbds = nr_frags + 2; | |
2114 | else | |
2115 | nr_txbds = nr_frags + 1; | |
2116 | ||
4669bc90 | 2117 | /* check if there is space to queue this packet */ |
f0ee7acf | 2118 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2119 | /* no space, stop the queue */ |
fba4ed03 | 2120 | netif_tx_stop_queue(txq); |
4669bc90 | 2121 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2122 | return NETDEV_TX_BUSY; |
2123 | } | |
1da177e4 LT |
2124 | |
2125 | /* Update transmit stats */ | |
1ac9ad13 ED |
2126 | tx_queue->stats.tx_bytes += skb->len; |
2127 | tx_queue->stats.tx_packets++; | |
1da177e4 | 2128 | |
a12f801d | 2129 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2130 | lstatus = txbdp->lstatus; |
2131 | ||
2132 | /* Time stamp insertion requires one additional TxBD */ | |
2133 | if (unlikely(do_tstamp)) | |
2134 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2135 | tx_queue->tx_ring_size); |
1da177e4 | 2136 | |
4669bc90 | 2137 | if (nr_frags == 0) { |
f0ee7acf MR |
2138 | if (unlikely(do_tstamp)) |
2139 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2140 | TXBD_INTERRUPT); |
f0ee7acf MR |
2141 | else |
2142 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2143 | } else { |
2144 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2145 | for (i = 0; i < nr_frags; i++) { | |
2146 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2147 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2148 | |
2149 | length = skb_shinfo(skb)->frags[i].size; | |
2150 | ||
2151 | lstatus = txbdp->lstatus | length | | |
bc4598bc | 2152 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2153 | |
2154 | /* Handle the last BD specially */ | |
2155 | if (i == nr_frags - 1) | |
2156 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2157 | |
369ec162 | 2158 | bufaddr = skb_frag_dma_map(priv->dev, |
2234a722 IC |
2159 | &skb_shinfo(skb)->frags[i], |
2160 | 0, | |
2161 | length, | |
2162 | DMA_TO_DEVICE); | |
4669bc90 DH |
2163 | |
2164 | /* set the TxBD length and buffer pointer */ | |
2165 | txbdp->bufPtr = bufaddr; | |
2166 | txbdp->lstatus = lstatus; | |
2167 | } | |
2168 | ||
2169 | lstatus = txbdp_start->lstatus; | |
2170 | } | |
1da177e4 | 2171 | |
9c4886e5 MR |
2172 | /* Add TxPAL between FCB and frame if required */ |
2173 | if (unlikely(do_tstamp)) { | |
2174 | skb_push(skb, GMAC_TXPAL_LEN); | |
2175 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2176 | } | |
2177 | ||
0bbaf069 | 2178 | /* Set up checksumming */ |
12dea57b | 2179 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe | 2180 | fcb = gfar_add_fcb(skb); |
4363c2fd | 2181 | /* as specified by errata */ |
bc4598bc JC |
2182 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) && |
2183 | ((unsigned long)fcb % 0x20) > 0x18)) { | |
4363c2fd AD |
2184 | __skb_pull(skb, GMAC_FCB_LEN); |
2185 | skb_checksum_help(skb); | |
2186 | } else { | |
2187 | lstatus |= BD_LFLAG(TXBD_TOE); | |
9c4886e5 | 2188 | gfar_tx_checksum(skb, fcb, fcb_length); |
4363c2fd | 2189 | } |
0bbaf069 KG |
2190 | } |
2191 | ||
eab6d18d | 2192 | if (vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2193 | if (unlikely(NULL == fcb)) { |
2194 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2195 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2196 | } |
54dc79fe SH |
2197 | |
2198 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2199 | } |
2200 | ||
f0ee7acf MR |
2201 | /* Setup tx hardware time stamping if requested */ |
2202 | if (unlikely(do_tstamp)) { | |
2244d07b | 2203 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf MR |
2204 | if (fcb == NULL) |
2205 | fcb = gfar_add_fcb(skb); | |
2206 | fcb->ptp = 1; | |
2207 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2208 | } | |
2209 | ||
369ec162 | 2210 | txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data, |
bc4598bc | 2211 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2212 | |
0977f817 | 2213 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2214 | * first TxBD points to the FCB and must have a data length of |
2215 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2216 | * the full frame length. | |
2217 | */ | |
2218 | if (unlikely(do_tstamp)) { | |
9c4886e5 | 2219 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length; |
f0ee7acf | 2220 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
bc4598bc | 2221 | (skb_headlen(skb) - fcb_length); |
f0ee7acf MR |
2222 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2223 | } else { | |
2224 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2225 | } | |
1da177e4 | 2226 | |
d8a0f1b0 PG |
2227 | netdev_tx_sent_queue(txq, skb->len); |
2228 | ||
0977f817 | 2229 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2230 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2231 | * when we were reading the num_txbdfree and checking for available | |
2232 | * space, that's because outside of this function it can only grow, | |
2233 | * and once we've got needed space, it cannot suddenly disappear. | |
2234 | * | |
2235 | * The lock also protects us from gfar_error(), which can modify | |
2236 | * regs->tstat and thus retrigger the transfers, which is why we | |
2237 | * also must grab the lock before setting ready bit for the first | |
2238 | * to be transmitted BD. | |
2239 | */ | |
2240 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2241 | ||
0977f817 | 2242 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2243 | * semantics (it requires synchronization between cacheable and |
2244 | * uncacheable mappings, which eieio doesn't provide and which we | |
2245 | * don't need), thus requiring a more expensive sync instruction. At | |
2246 | * some point, the set of architecture-independent barrier functions | |
2247 | * should be expanded to include weaker barriers. | |
2248 | */ | |
3b6330ce | 2249 | eieio(); |
7f7f5316 | 2250 | |
4669bc90 DH |
2251 | txbdp_start->lstatus = lstatus; |
2252 | ||
0eddba52 AV |
2253 | eieio(); /* force lstatus write before tx_skbuff */ |
2254 | ||
2255 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2256 | ||
4669bc90 | 2257 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2258 | * (wrapping if necessary) |
2259 | */ | |
a12f801d | 2260 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2261 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2262 | |
a12f801d | 2263 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2264 | |
2265 | /* reduce TxBD free count */ | |
f0ee7acf | 2266 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2267 | |
2268 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2269 | * are full. We need to tell the kernel to stop sending us stuff. |
2270 | */ | |
a12f801d | 2271 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2272 | netif_tx_stop_queue(txq); |
1da177e4 | 2273 | |
09f75cd7 | 2274 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2275 | } |
2276 | ||
1da177e4 | 2277 | /* Tell the DMA to go go go */ |
fba4ed03 | 2278 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2279 | |
2280 | /* Unlock priv */ | |
a12f801d | 2281 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2282 | |
54dc79fe | 2283 | return NETDEV_TX_OK; |
1da177e4 LT |
2284 | } |
2285 | ||
2286 | /* Stops the kernel queue, and halts the controller */ | |
2287 | static int gfar_close(struct net_device *dev) | |
2288 | { | |
2289 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2290 | |
46ceb60c | 2291 | disable_napi(priv); |
bea3348e | 2292 | |
ab939905 | 2293 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2294 | stop_gfar(dev); |
2295 | ||
bb40dcbb AF |
2296 | /* Disconnect from the PHY */ |
2297 | phy_disconnect(priv->phydev); | |
2298 | priv->phydev = NULL; | |
1da177e4 | 2299 | |
fba4ed03 | 2300 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2301 | |
2302 | return 0; | |
2303 | } | |
2304 | ||
1da177e4 | 2305 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2306 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2307 | { |
7f7f5316 | 2308 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2309 | |
2310 | return 0; | |
2311 | } | |
2312 | ||
f3dc1586 SP |
2313 | /* Check if rx parser should be activated */ |
2314 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2315 | { | |
2316 | struct gfar __iomem *regs; | |
2317 | u32 tempval; | |
2318 | ||
2319 | regs = priv->gfargrp[0].regs; | |
2320 | ||
2321 | tempval = gfar_read(®s->rctrl); | |
2322 | /* If parse is no longer required, then disable parser */ | |
ba779711 | 2323 | if (tempval & RCTRL_REQ_PARSER) { |
f3dc1586 | 2324 | tempval |= RCTRL_PRSDEP_INIT; |
ba779711 CM |
2325 | priv->uses_rxfcb = 1; |
2326 | } else { | |
f3dc1586 | 2327 | tempval &= ~RCTRL_PRSDEP_INIT; |
ba779711 CM |
2328 | priv->uses_rxfcb = 0; |
2329 | } | |
f3dc1586 SP |
2330 | gfar_write(®s->rctrl, tempval); |
2331 | } | |
2332 | ||
0bbaf069 | 2333 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2334 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2335 | { |
2336 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2337 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2338 | unsigned long flags; |
2339 | u32 tempval; | |
2340 | ||
46ceb60c | 2341 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2342 | local_irq_save(flags); |
2343 | lock_rx_qs(priv); | |
0bbaf069 | 2344 | |
87c288c6 | 2345 | if (features & NETIF_F_HW_VLAN_TX) { |
0bbaf069 | 2346 | /* Enable VLAN tag insertion */ |
f4983704 | 2347 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2348 | tempval |= TCTRL_VLINS; |
f4983704 | 2349 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2350 | } else { |
2351 | /* Disable VLAN tag insertion */ | |
f4983704 | 2352 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2353 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2354 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2355 | } |
0bbaf069 | 2356 | |
87c288c6 JP |
2357 | if (features & NETIF_F_HW_VLAN_RX) { |
2358 | /* Enable VLAN tag extraction */ | |
2359 | tempval = gfar_read(®s->rctrl); | |
2360 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2361 | gfar_write(®s->rctrl, tempval); | |
ba779711 | 2362 | priv->uses_rxfcb = 1; |
87c288c6 | 2363 | } else { |
0bbaf069 | 2364 | /* Disable VLAN tag extraction */ |
f4983704 | 2365 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2366 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2367 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2368 | |
2369 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2370 | } |
2371 | ||
77ecaf2d DH |
2372 | gfar_change_mtu(dev, dev->mtu); |
2373 | ||
fba4ed03 SG |
2374 | unlock_rx_qs(priv); |
2375 | local_irq_restore(flags); | |
0bbaf069 KG |
2376 | } |
2377 | ||
1da177e4 LT |
2378 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2379 | { | |
2380 | int tempsize, tempval; | |
2381 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2382 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2383 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2384 | int frame_size = new_mtu + ETH_HLEN; |
2385 | ||
1da177e4 | 2386 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2387 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2388 | return -EINVAL; |
2389 | } | |
2390 | ||
ba779711 | 2391 | if (priv->uses_rxfcb) |
77ecaf2d DH |
2392 | frame_size += GMAC_FCB_LEN; |
2393 | ||
2394 | frame_size += priv->padding; | |
2395 | ||
bc4598bc JC |
2396 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2397 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2398 | |
2399 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2400 | * stopped, and we changed something |
2401 | */ | |
1da177e4 LT |
2402 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2403 | stop_gfar(dev); | |
2404 | ||
2405 | priv->rx_buffer_size = tempsize; | |
2406 | ||
2407 | dev->mtu = new_mtu; | |
2408 | ||
f4983704 SG |
2409 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2410 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2411 | |
2412 | /* If the mtu is larger than the max size for standard | |
2413 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2414 | * to allow huge frames, and to check the length |
2415 | */ | |
f4983704 | 2416 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2417 | |
7d350977 | 2418 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2419 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2420 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2421 | else | |
2422 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2423 | ||
f4983704 | 2424 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2425 | |
2426 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2427 | startup_gfar(dev); | |
2428 | ||
2429 | return 0; | |
2430 | } | |
2431 | ||
ab939905 | 2432 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2433 | * transmitted after a set amount of time. |
2434 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2435 | * starting over will fix the problem. |
2436 | */ | |
2437 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2438 | { |
ab939905 | 2439 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2440 | reset_task); |
4826857f | 2441 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2442 | |
2443 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2444 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2445 | stop_gfar(dev); |
2446 | startup_gfar(dev); | |
fba4ed03 | 2447 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2448 | } |
2449 | ||
263ba320 | 2450 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2451 | } |
2452 | ||
ab939905 SS |
2453 | static void gfar_timeout(struct net_device *dev) |
2454 | { | |
2455 | struct gfar_private *priv = netdev_priv(dev); | |
2456 | ||
2457 | dev->stats.tx_errors++; | |
2458 | schedule_work(&priv->reset_task); | |
2459 | } | |
2460 | ||
acbc0f03 EL |
2461 | static void gfar_align_skb(struct sk_buff *skb) |
2462 | { | |
2463 | /* We need the data buffer to be aligned properly. We will reserve | |
2464 | * as many bytes as needed to align the data properly | |
2465 | */ | |
2466 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2467 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2468 | } |
2469 | ||
1da177e4 | 2470 | /* Interrupt Handler for Transmit complete */ |
c233cf40 | 2471 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2472 | { |
a12f801d | 2473 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2474 | struct netdev_queue *txq; |
d080cd63 | 2475 | struct gfar_private *priv = netdev_priv(dev); |
a12f801d | 2476 | struct gfar_priv_rx_q *rx_queue = NULL; |
f0ee7acf | 2477 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2478 | struct txbd8 *lbdp = NULL; |
a12f801d | 2479 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2480 | struct sk_buff *skb; |
2481 | int skb_dirtytx; | |
a12f801d | 2482 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2483 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2484 | int i; |
d080cd63 | 2485 | int howmany = 0; |
d8a0f1b0 PG |
2486 | int tqi = tx_queue->qindex; |
2487 | unsigned int bytes_sent = 0; | |
4669bc90 | 2488 | u32 lstatus; |
f0ee7acf | 2489 | size_t buflen; |
1da177e4 | 2490 | |
d8a0f1b0 PG |
2491 | rx_queue = priv->rx_queue[tqi]; |
2492 | txq = netdev_get_tx_queue(dev, tqi); | |
a12f801d SG |
2493 | bdp = tx_queue->dirty_tx; |
2494 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2495 | |
a12f801d | 2496 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2497 | unsigned long flags; |
2498 | ||
4669bc90 | 2499 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2500 | |
0977f817 | 2501 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2502 | * Also, we need to dma_unmap_single() the TxPAL. |
2503 | */ | |
2244d07b | 2504 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2505 | nr_txbds = frags + 2; |
2506 | else | |
2507 | nr_txbds = frags + 1; | |
2508 | ||
2509 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2510 | |
4669bc90 | 2511 | lstatus = lbdp->lstatus; |
1da177e4 | 2512 | |
4669bc90 DH |
2513 | /* Only clean completed frames */ |
2514 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2515 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2516 | break; |
2517 | ||
2244d07b | 2518 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2519 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2520 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2521 | } else |
2522 | buflen = bdp->length; | |
2523 | ||
369ec162 | 2524 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2525 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2526 | |
2244d07b | 2527 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2528 | struct skb_shared_hwtstamps shhwtstamps; |
2529 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2530 | |
f0ee7acf MR |
2531 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2532 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2533 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2534 | skb_tstamp_tx(skb, &shhwtstamps); |
2535 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2536 | bdp = next; | |
2537 | } | |
81183059 | 2538 | |
4669bc90 DH |
2539 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2540 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2541 | |
4669bc90 | 2542 | for (i = 0; i < frags; i++) { |
369ec162 | 2543 | dma_unmap_page(priv->dev, bdp->bufPtr, |
bc4598bc | 2544 | bdp->length, DMA_TO_DEVICE); |
4669bc90 DH |
2545 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2546 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2547 | } | |
1da177e4 | 2548 | |
d8a0f1b0 PG |
2549 | bytes_sent += skb->len; |
2550 | ||
acb600de | 2551 | dev_kfree_skb_any(skb); |
0fd56bb5 | 2552 | |
a12f801d | 2553 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2554 | |
4669bc90 | 2555 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2556 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2557 | |
2558 | howmany++; | |
a3bc1f11 | 2559 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2560 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2561 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2562 | } |
1da177e4 | 2563 | |
4669bc90 | 2564 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2565 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2566 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2567 | |
4669bc90 | 2568 | /* Update dirty indicators */ |
a12f801d SG |
2569 | tx_queue->skb_dirtytx = skb_dirtytx; |
2570 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2571 | |
d8a0f1b0 | 2572 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
d080cd63 DH |
2573 | } |
2574 | ||
f4983704 | 2575 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2576 | { |
a6d0b91a AV |
2577 | unsigned long flags; |
2578 | ||
fba4ed03 SG |
2579 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2580 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2581 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2582 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2583 | } else { |
0977f817 | 2584 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2585 | * because of the packets that have already arrived. |
2586 | */ | |
f4983704 | 2587 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2588 | } |
fba4ed03 | 2589 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2590 | |
8c7396ae | 2591 | } |
1da177e4 | 2592 | |
8c7396ae | 2593 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2594 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2595 | { |
f4983704 | 2596 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2597 | return IRQ_HANDLED; |
2598 | } | |
2599 | ||
a12f801d | 2600 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2601 | struct sk_buff *skb) |
815b97c6 | 2602 | { |
a12f801d | 2603 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2604 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2605 | dma_addr_t buf; |
815b97c6 | 2606 | |
369ec162 | 2607 | buf = dma_map_single(priv->dev, skb->data, |
8a102fe0 | 2608 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
a12f801d | 2609 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2610 | } |
2611 | ||
2281a0f3 | 2612 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2613 | { |
2614 | struct gfar_private *priv = netdev_priv(dev); | |
acb600de | 2615 | struct sk_buff *skb; |
1da177e4 | 2616 | |
acbc0f03 | 2617 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2618 | if (!skb) |
1da177e4 LT |
2619 | return NULL; |
2620 | ||
acbc0f03 | 2621 | gfar_align_skb(skb); |
7f7f5316 | 2622 | |
acbc0f03 EL |
2623 | return skb; |
2624 | } | |
2625 | ||
2281a0f3 | 2626 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 | 2627 | { |
acb600de | 2628 | return gfar_alloc_skb(dev); |
1da177e4 LT |
2629 | } |
2630 | ||
298e1a9e | 2631 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2632 | { |
298e1a9e | 2633 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2634 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2635 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2636 | ||
0977f817 | 2637 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2638 | if (status & RXBD_TRUNCATED) { |
2639 | stats->rx_length_errors++; | |
2640 | ||
212079df | 2641 | atomic64_inc(&estats->rx_trunc); |
1da177e4 LT |
2642 | |
2643 | return; | |
2644 | } | |
2645 | /* Count the errors, if there were any */ | |
2646 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2647 | stats->rx_length_errors++; | |
2648 | ||
2649 | if (status & RXBD_LARGE) | |
212079df | 2650 | atomic64_inc(&estats->rx_large); |
1da177e4 | 2651 | else |
212079df | 2652 | atomic64_inc(&estats->rx_short); |
1da177e4 LT |
2653 | } |
2654 | if (status & RXBD_NONOCTET) { | |
2655 | stats->rx_frame_errors++; | |
212079df | 2656 | atomic64_inc(&estats->rx_nonoctet); |
1da177e4 LT |
2657 | } |
2658 | if (status & RXBD_CRCERR) { | |
212079df | 2659 | atomic64_inc(&estats->rx_crcerr); |
1da177e4 LT |
2660 | stats->rx_crc_errors++; |
2661 | } | |
2662 | if (status & RXBD_OVERRUN) { | |
212079df | 2663 | atomic64_inc(&estats->rx_overrun); |
1da177e4 LT |
2664 | stats->rx_crc_errors++; |
2665 | } | |
2666 | } | |
2667 | ||
f4983704 | 2668 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2669 | { |
f4983704 | 2670 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2671 | return IRQ_HANDLED; |
2672 | } | |
2673 | ||
0bbaf069 KG |
2674 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2675 | { | |
2676 | /* If valid headers were found, and valid sums | |
2677 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2678 | * checksumming is necessary. Otherwise, it is [FIXME] |
2679 | */ | |
7f7f5316 | 2680 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2681 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2682 | else | |
bc8acf2c | 2683 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2684 | } |
2685 | ||
2686 | ||
0977f817 | 2687 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
61db26c6 CM |
2688 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
2689 | int amount_pull, struct napi_struct *napi) | |
1da177e4 LT |
2690 | { |
2691 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2692 | struct rxfcb *fcb = NULL; |
1da177e4 | 2693 | |
cd754a57 | 2694 | gro_result_t ret; |
1da177e4 | 2695 | |
2c2db48a DH |
2696 | /* fcb is at the beginning if exists */ |
2697 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2698 | |
0977f817 JC |
2699 | /* Remove the FCB from the skb |
2700 | * Remove the padded bytes, if there are any | |
2701 | */ | |
f74dac08 SG |
2702 | if (amount_pull) { |
2703 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2704 | skb_pull(skb, amount_pull); |
f74dac08 | 2705 | } |
0bbaf069 | 2706 | |
cc772ab7 MR |
2707 | /* Get receive timestamp from the skb */ |
2708 | if (priv->hwts_rx_en) { | |
2709 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2710 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2711 | |
cc772ab7 MR |
2712 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2713 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2714 | } | |
2715 | ||
2716 | if (priv->padding) | |
2717 | skb_pull(skb, priv->padding); | |
2718 | ||
8b3afe95 | 2719 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2720 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2721 | |
2c2db48a DH |
2722 | /* Tell the skb what kind of packet this is */ |
2723 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2724 | |
0977f817 | 2725 | /* There's need to check for NETIF_F_HW_VLAN_RX here. |
32f7fd44 JP |
2726 | * Even if vlan rx accel is disabled, on some chips |
2727 | * RXFCB_VLN is pseudo randomly set. | |
2728 | */ | |
2729 | if (dev->features & NETIF_F_HW_VLAN_RX && | |
2730 | fcb->flags & RXFCB_VLN) | |
87c288c6 JP |
2731 | __vlan_hwaccel_put_tag(skb, fcb->vlctl); |
2732 | ||
2c2db48a | 2733 | /* Send the packet up the stack */ |
cd754a57 | 2734 | ret = napi_gro_receive(napi, skb); |
0bbaf069 | 2735 | |
bd9e89f2 | 2736 | if (unlikely(GRO_DROP == ret)) |
212079df | 2737 | atomic64_inc(&priv->extra_stats.kernel_dropped); |
1da177e4 LT |
2738 | } |
2739 | ||
2740 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2741 | * until the budget/quota has been reached. Returns the number |
2742 | * of frames handled | |
1da177e4 | 2743 | */ |
a12f801d | 2744 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2745 | { |
a12f801d | 2746 | struct net_device *dev = rx_queue->dev; |
31de198b | 2747 | struct rxbd8 *bdp, *base; |
1da177e4 | 2748 | struct sk_buff *skb; |
2c2db48a DH |
2749 | int pkt_len; |
2750 | int amount_pull; | |
1da177e4 LT |
2751 | int howmany = 0; |
2752 | struct gfar_private *priv = netdev_priv(dev); | |
2753 | ||
2754 | /* Get the first full descriptor */ | |
a12f801d SG |
2755 | bdp = rx_queue->cur_rx; |
2756 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2757 | |
ba779711 | 2758 | amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; |
2c2db48a | 2759 | |
1da177e4 | 2760 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2761 | struct sk_buff *newskb; |
bc4598bc | 2762 | |
3b6330ce | 2763 | rmb(); |
815b97c6 AF |
2764 | |
2765 | /* Add another skb for the future */ | |
2766 | newskb = gfar_new_skb(dev); | |
2767 | ||
a12f801d | 2768 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2769 | |
369ec162 | 2770 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2771 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2772 | |
63b88b90 | 2773 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2774 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2775 | bdp->status = RXBD_LARGE; |
2776 | ||
815b97c6 AF |
2777 | /* We drop the frame if we failed to allocate a new buffer */ |
2778 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2779 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2780 | count_errors(bdp->status, dev); |
2781 | ||
2782 | if (unlikely(!newskb)) | |
2783 | newskb = skb; | |
acbc0f03 | 2784 | else if (skb) |
acb600de | 2785 | dev_kfree_skb(skb); |
815b97c6 | 2786 | } else { |
1da177e4 | 2787 | /* Increment the number of packets */ |
a7f38041 | 2788 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2789 | howmany++; |
2790 | ||
2c2db48a DH |
2791 | if (likely(skb)) { |
2792 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2793 | /* Remove the FCS from the packet length */ | |
2794 | skb_put(skb, pkt_len); | |
a7f38041 | 2795 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2796 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2797 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2798 | &rx_queue->grp->napi); |
2c2db48a DH |
2799 | |
2800 | } else { | |
59deab26 | 2801 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2802 | rx_queue->stats.rx_dropped++; |
212079df | 2803 | atomic64_inc(&priv->extra_stats.rx_skbmissing); |
2c2db48a | 2804 | } |
1da177e4 | 2805 | |
1da177e4 LT |
2806 | } |
2807 | ||
a12f801d | 2808 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2809 | |
815b97c6 | 2810 | /* Setup the new bdp */ |
a12f801d | 2811 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2812 | |
2813 | /* Update to the next pointer */ | |
a12f801d | 2814 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2815 | |
2816 | /* update to point at the next skb */ | |
bc4598bc JC |
2817 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2818 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2819 | } |
2820 | ||
2821 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2822 | rx_queue->cur_rx = bdp; |
1da177e4 | 2823 | |
1da177e4 LT |
2824 | return howmany; |
2825 | } | |
2826 | ||
bea3348e | 2827 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2828 | { |
bc4598bc JC |
2829 | struct gfar_priv_grp *gfargrp = |
2830 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2831 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2832 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2833 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2834 | struct gfar_priv_rx_q *rx_queue = NULL; |
c233cf40 CM |
2835 | int work_done = 0, work_done_per_q = 0; |
2836 | int i, budget_per_q; | |
2837 | int has_tx_work; | |
6be5ed3f CM |
2838 | unsigned long rstat_rxf; |
2839 | int num_act_queues; | |
fba4ed03 | 2840 | |
8c7396ae | 2841 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2842 | * because of the packets that have already arrived |
2843 | */ | |
f4983704 | 2844 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2845 | |
6be5ed3f CM |
2846 | rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; |
2847 | ||
2848 | num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); | |
2849 | if (num_act_queues) | |
2850 | budget_per_q = budget/num_act_queues; | |
2851 | ||
c233cf40 CM |
2852 | while (1) { |
2853 | has_tx_work = 0; | |
2854 | for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { | |
2855 | tx_queue = priv->tx_queue[i]; | |
2856 | /* run Tx cleanup to completion */ | |
2857 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { | |
2858 | gfar_clean_tx_ring(tx_queue); | |
2859 | has_tx_work = 1; | |
2860 | } | |
2861 | } | |
fba4ed03 | 2862 | |
984b3f57 | 2863 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
6be5ed3f CM |
2864 | /* skip queue if not active */ |
2865 | if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) | |
fba4ed03 | 2866 | continue; |
c233cf40 | 2867 | |
fba4ed03 | 2868 | rx_queue = priv->rx_queue[i]; |
c233cf40 CM |
2869 | work_done_per_q = |
2870 | gfar_clean_rx_ring(rx_queue, budget_per_q); | |
2871 | work_done += work_done_per_q; | |
2872 | ||
2873 | /* finished processing this queue */ | |
2874 | if (work_done_per_q < budget_per_q) { | |
6be5ed3f CM |
2875 | /* clear active queue hw indication */ |
2876 | gfar_write(®s->rstat, | |
2877 | RSTAT_CLEAR_RXF0 >> i); | |
2878 | rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i); | |
2879 | num_act_queues--; | |
2880 | ||
2881 | if (!num_act_queues) | |
c233cf40 CM |
2882 | break; |
2883 | /* recompute budget per Rx queue */ | |
2884 | budget_per_q = | |
6be5ed3f | 2885 | (budget - work_done) / num_act_queues; |
fba4ed03 SG |
2886 | } |
2887 | } | |
1da177e4 | 2888 | |
c233cf40 CM |
2889 | if (work_done >= budget) |
2890 | break; | |
42199884 | 2891 | |
6be5ed3f | 2892 | if (!num_act_queues && !has_tx_work) { |
1da177e4 | 2893 | |
c233cf40 | 2894 | napi_complete(napi); |
1da177e4 | 2895 | |
c233cf40 CM |
2896 | /* Clear the halt bit in RSTAT */ |
2897 | gfar_write(®s->rstat, gfargrp->rstat); | |
1da177e4 | 2898 | |
c233cf40 CM |
2899 | gfar_write(®s->imask, IMASK_DEFAULT); |
2900 | ||
2901 | /* If we are coalescing interrupts, update the timer | |
2902 | * Otherwise, clear it | |
2903 | */ | |
2904 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, | |
2905 | gfargrp->tx_bit_map); | |
2906 | break; | |
2907 | } | |
1da177e4 LT |
2908 | } |
2909 | ||
c233cf40 | 2910 | return work_done; |
1da177e4 | 2911 | } |
1da177e4 | 2912 | |
f2d71c2d | 2913 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2914 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2915 | * without having to re-enable interrupts. It's not called while |
2916 | * the interrupt routine is executing. | |
2917 | */ | |
2918 | static void gfar_netpoll(struct net_device *dev) | |
2919 | { | |
2920 | struct gfar_private *priv = netdev_priv(dev); | |
3a2e16c8 | 2921 | int i; |
f2d71c2d VW |
2922 | |
2923 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2924 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c | 2925 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
2926 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
2927 | ||
2928 | disable_irq(gfar_irq(grp, TX)->irq); | |
2929 | disable_irq(gfar_irq(grp, RX)->irq); | |
2930 | disable_irq(gfar_irq(grp, ER)->irq); | |
2931 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
2932 | enable_irq(gfar_irq(grp, ER)->irq); | |
2933 | enable_irq(gfar_irq(grp, RX)->irq); | |
2934 | enable_irq(gfar_irq(grp, TX)->irq); | |
46ceb60c | 2935 | } |
f2d71c2d | 2936 | } else { |
46ceb60c | 2937 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
2938 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
2939 | ||
2940 | disable_irq(gfar_irq(grp, TX)->irq); | |
2941 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
2942 | enable_irq(gfar_irq(grp, TX)->irq); | |
43de004b | 2943 | } |
f2d71c2d VW |
2944 | } |
2945 | } | |
2946 | #endif | |
2947 | ||
1da177e4 | 2948 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2949 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2950 | { |
f4983704 | 2951 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2952 | |
2953 | /* Save ievent for future reference */ | |
f4983704 | 2954 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 2955 | |
1da177e4 | 2956 | /* Check for reception */ |
538cc7ee | 2957 | if (events & IEVENT_RX_MASK) |
f4983704 | 2958 | gfar_receive(irq, grp_id); |
1da177e4 LT |
2959 | |
2960 | /* Check for transmit completion */ | |
538cc7ee | 2961 | if (events & IEVENT_TX_MASK) |
f4983704 | 2962 | gfar_transmit(irq, grp_id); |
1da177e4 | 2963 | |
538cc7ee SS |
2964 | /* Check for errors */ |
2965 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 2966 | gfar_error(irq, grp_id); |
1da177e4 LT |
2967 | |
2968 | return IRQ_HANDLED; | |
2969 | } | |
2970 | ||
1da177e4 LT |
2971 | /* Called every time the controller might need to be made |
2972 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2973 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2974 | * function converts those variables into the appropriate |
2975 | * register values, and can bring down the device if needed. | |
2976 | */ | |
2977 | static void adjust_link(struct net_device *dev) | |
2978 | { | |
2979 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2980 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
2981 | unsigned long flags; |
2982 | struct phy_device *phydev = priv->phydev; | |
2983 | int new_state = 0; | |
2984 | ||
fba4ed03 SG |
2985 | local_irq_save(flags); |
2986 | lock_tx_qs(priv); | |
2987 | ||
bb40dcbb AF |
2988 | if (phydev->link) { |
2989 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2990 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2991 | |
1da177e4 | 2992 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
2993 | * If not, we operate in half-duplex mode. |
2994 | */ | |
bb40dcbb AF |
2995 | if (phydev->duplex != priv->oldduplex) { |
2996 | new_state = 1; | |
2997 | if (!(phydev->duplex)) | |
1da177e4 | 2998 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2999 | else |
1da177e4 | 3000 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 3001 | |
bb40dcbb | 3002 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
3003 | } |
3004 | ||
bb40dcbb AF |
3005 | if (phydev->speed != priv->oldspeed) { |
3006 | new_state = 1; | |
3007 | switch (phydev->speed) { | |
1da177e4 | 3008 | case 1000: |
1da177e4 LT |
3009 | tempval = |
3010 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
3011 | |
3012 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3013 | break; |
3014 | case 100: | |
3015 | case 10: | |
1da177e4 LT |
3016 | tempval = |
3017 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
3018 | |
3019 | /* Reduced mode distinguishes | |
0977f817 JC |
3020 | * between 10 and 100 |
3021 | */ | |
7f7f5316 AF |
3022 | if (phydev->speed == SPEED_100) |
3023 | ecntrl |= ECNTRL_R100; | |
3024 | else | |
3025 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3026 | break; |
3027 | default: | |
59deab26 JP |
3028 | netif_warn(priv, link, dev, |
3029 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3030 | phydev->speed); | |
1da177e4 LT |
3031 | break; |
3032 | } | |
3033 | ||
bb40dcbb | 3034 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3035 | } |
3036 | ||
bb40dcbb | 3037 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3038 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3039 | |
1da177e4 | 3040 | if (!priv->oldlink) { |
bb40dcbb | 3041 | new_state = 1; |
1da177e4 | 3042 | priv->oldlink = 1; |
1da177e4 | 3043 | } |
bb40dcbb AF |
3044 | } else if (priv->oldlink) { |
3045 | new_state = 1; | |
3046 | priv->oldlink = 0; | |
3047 | priv->oldspeed = 0; | |
3048 | priv->oldduplex = -1; | |
1da177e4 | 3049 | } |
1da177e4 | 3050 | |
bb40dcbb AF |
3051 | if (new_state && netif_msg_link(priv)) |
3052 | phy_print_status(phydev); | |
fba4ed03 SG |
3053 | unlock_tx_qs(priv); |
3054 | local_irq_restore(flags); | |
bb40dcbb | 3055 | } |
1da177e4 LT |
3056 | |
3057 | /* Update the hash table based on the current list of multicast | |
3058 | * addresses we subscribe to. Also, change the promiscuity of | |
3059 | * the device based on the flags (this function is called | |
0977f817 JC |
3060 | * whenever dev->flags is changed |
3061 | */ | |
1da177e4 LT |
3062 | static void gfar_set_multi(struct net_device *dev) |
3063 | { | |
22bedad3 | 3064 | struct netdev_hw_addr *ha; |
1da177e4 | 3065 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3066 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3067 | u32 tempval; |
3068 | ||
a12f801d | 3069 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3070 | /* Set RCTRL to PROM */ |
3071 | tempval = gfar_read(®s->rctrl); | |
3072 | tempval |= RCTRL_PROM; | |
3073 | gfar_write(®s->rctrl, tempval); | |
3074 | } else { | |
3075 | /* Set RCTRL to not PROM */ | |
3076 | tempval = gfar_read(®s->rctrl); | |
3077 | tempval &= ~(RCTRL_PROM); | |
3078 | gfar_write(®s->rctrl, tempval); | |
3079 | } | |
6aa20a22 | 3080 | |
a12f801d | 3081 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3082 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3083 | gfar_write(®s->igaddr0, 0xffffffff); |
3084 | gfar_write(®s->igaddr1, 0xffffffff); | |
3085 | gfar_write(®s->igaddr2, 0xffffffff); | |
3086 | gfar_write(®s->igaddr3, 0xffffffff); | |
3087 | gfar_write(®s->igaddr4, 0xffffffff); | |
3088 | gfar_write(®s->igaddr5, 0xffffffff); | |
3089 | gfar_write(®s->igaddr6, 0xffffffff); | |
3090 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3091 | gfar_write(®s->gaddr0, 0xffffffff); |
3092 | gfar_write(®s->gaddr1, 0xffffffff); | |
3093 | gfar_write(®s->gaddr2, 0xffffffff); | |
3094 | gfar_write(®s->gaddr3, 0xffffffff); | |
3095 | gfar_write(®s->gaddr4, 0xffffffff); | |
3096 | gfar_write(®s->gaddr5, 0xffffffff); | |
3097 | gfar_write(®s->gaddr6, 0xffffffff); | |
3098 | gfar_write(®s->gaddr7, 0xffffffff); | |
3099 | } else { | |
7f7f5316 AF |
3100 | int em_num; |
3101 | int idx; | |
3102 | ||
1da177e4 | 3103 | /* zero out the hash */ |
0bbaf069 KG |
3104 | gfar_write(®s->igaddr0, 0x0); |
3105 | gfar_write(®s->igaddr1, 0x0); | |
3106 | gfar_write(®s->igaddr2, 0x0); | |
3107 | gfar_write(®s->igaddr3, 0x0); | |
3108 | gfar_write(®s->igaddr4, 0x0); | |
3109 | gfar_write(®s->igaddr5, 0x0); | |
3110 | gfar_write(®s->igaddr6, 0x0); | |
3111 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3112 | gfar_write(®s->gaddr0, 0x0); |
3113 | gfar_write(®s->gaddr1, 0x0); | |
3114 | gfar_write(®s->gaddr2, 0x0); | |
3115 | gfar_write(®s->gaddr3, 0x0); | |
3116 | gfar_write(®s->gaddr4, 0x0); | |
3117 | gfar_write(®s->gaddr5, 0x0); | |
3118 | gfar_write(®s->gaddr6, 0x0); | |
3119 | gfar_write(®s->gaddr7, 0x0); | |
3120 | ||
7f7f5316 AF |
3121 | /* If we have extended hash tables, we need to |
3122 | * clear the exact match registers to prepare for | |
0977f817 JC |
3123 | * setting them |
3124 | */ | |
7f7f5316 AF |
3125 | if (priv->extended_hash) { |
3126 | em_num = GFAR_EM_NUM + 1; | |
3127 | gfar_clear_exact_match(dev); | |
3128 | idx = 1; | |
3129 | } else { | |
3130 | idx = 0; | |
3131 | em_num = 0; | |
3132 | } | |
3133 | ||
4cd24eaf | 3134 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3135 | return; |
3136 | ||
3137 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3138 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3139 | if (idx < em_num) { |
22bedad3 | 3140 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3141 | idx++; |
3142 | } else | |
22bedad3 | 3143 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3144 | } |
3145 | } | |
1da177e4 LT |
3146 | } |
3147 | ||
7f7f5316 AF |
3148 | |
3149 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3150 | * don't interfere with normal reception |
3151 | */ | |
7f7f5316 AF |
3152 | static void gfar_clear_exact_match(struct net_device *dev) |
3153 | { | |
3154 | int idx; | |
6a3c910c | 3155 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3156 | |
bc4598bc | 3157 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3158 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3159 | } |
3160 | ||
1da177e4 LT |
3161 | /* Set the appropriate hash bit for the given addr */ |
3162 | /* The algorithm works like so: | |
3163 | * 1) Take the Destination Address (ie the multicast address), and | |
3164 | * do a CRC on it (little endian), and reverse the bits of the | |
3165 | * result. | |
3166 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3167 | * table. The table is controlled through 8 32-bit registers: | |
3168 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3169 | * gaddr7. This means that the 3 most significant bits in the | |
3170 | * hash index which gaddr register to use, and the 5 other bits | |
3171 | * indicate which bit (assuming an IBM numbering scheme, which | |
3172 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3173 | * the entry. |
3174 | */ | |
1da177e4 LT |
3175 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3176 | { | |
3177 | u32 tempval; | |
3178 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3179 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3180 | int width = priv->hash_width; |
3181 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3182 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3183 | u32 value = (1 << (31-whichbit)); |
3184 | ||
0bbaf069 | 3185 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3186 | tempval |= value; |
0bbaf069 | 3187 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3188 | } |
3189 | ||
7f7f5316 AF |
3190 | |
3191 | /* There are multiple MAC Address register pairs on some controllers | |
3192 | * This function sets the numth pair to a given address | |
3193 | */ | |
b6bc7650 JP |
3194 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3195 | const u8 *addr) | |
7f7f5316 AF |
3196 | { |
3197 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3198 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3199 | int idx; |
6a3c910c | 3200 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3201 | u32 tempval; |
f4983704 | 3202 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3203 | |
3204 | macptr += num*2; | |
3205 | ||
0977f817 JC |
3206 | /* Now copy it into the mac registers backwards, cuz |
3207 | * little endian is silly | |
3208 | */ | |
6a3c910c JP |
3209 | for (idx = 0; idx < ETH_ALEN; idx++) |
3210 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3211 | |
3212 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3213 | ||
3214 | tempval = *((u32 *) (tmpbuf + 4)); | |
3215 | ||
3216 | gfar_write(macptr+1, tempval); | |
3217 | } | |
3218 | ||
1da177e4 | 3219 | /* GFAR error interrupt handler */ |
f4983704 | 3220 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3221 | { |
f4983704 SG |
3222 | struct gfar_priv_grp *gfargrp = grp_id; |
3223 | struct gfar __iomem *regs = gfargrp->regs; | |
3224 | struct gfar_private *priv= gfargrp->priv; | |
3225 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3226 | |
3227 | /* Save ievent for future reference */ | |
f4983704 | 3228 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3229 | |
3230 | /* Clear IEVENT */ | |
f4983704 | 3231 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3232 | |
3233 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3234 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3235 | (events & IEVENT_MAG)) |
3236 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3237 | |
3238 | /* Hmm... */ | |
0bbaf069 | 3239 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3240 | netdev_dbg(dev, |
3241 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3242 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3243 | |
3244 | /* Update the error counters */ | |
3245 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3246 | dev->stats.tx_errors++; |
1da177e4 LT |
3247 | |
3248 | if (events & IEVENT_LC) | |
09f75cd7 | 3249 | dev->stats.tx_window_errors++; |
1da177e4 | 3250 | if (events & IEVENT_CRL) |
09f75cd7 | 3251 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3252 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3253 | unsigned long flags; |
3254 | ||
59deab26 JP |
3255 | netif_dbg(priv, tx_err, dev, |
3256 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3257 | dev->stats.tx_dropped++; |
212079df | 3258 | atomic64_inc(&priv->extra_stats.tx_underrun); |
1da177e4 | 3259 | |
836cf7fa AV |
3260 | local_irq_save(flags); |
3261 | lock_tx_qs(priv); | |
3262 | ||
1da177e4 | 3263 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3264 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3265 | |
3266 | unlock_tx_qs(priv); | |
3267 | local_irq_restore(flags); | |
1da177e4 | 3268 | } |
59deab26 | 3269 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3270 | } |
3271 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3272 | dev->stats.rx_errors++; |
212079df | 3273 | atomic64_inc(&priv->extra_stats.rx_bsy); |
1da177e4 | 3274 | |
f4983704 | 3275 | gfar_receive(irq, grp_id); |
1da177e4 | 3276 | |
59deab26 JP |
3277 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3278 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3279 | } |
3280 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3281 | dev->stats.rx_errors++; |
212079df | 3282 | atomic64_inc(&priv->extra_stats.rx_babr); |
1da177e4 | 3283 | |
59deab26 | 3284 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3285 | } |
3286 | if (events & IEVENT_EBERR) { | |
212079df | 3287 | atomic64_inc(&priv->extra_stats.eberr); |
59deab26 | 3288 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3289 | } |
59deab26 JP |
3290 | if (events & IEVENT_RXC) |
3291 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3292 | |
3293 | if (events & IEVENT_BABT) { | |
212079df | 3294 | atomic64_inc(&priv->extra_stats.tx_babt); |
59deab26 | 3295 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3296 | } |
3297 | return IRQ_HANDLED; | |
3298 | } | |
3299 | ||
b31a1d8b AF |
3300 | static struct of_device_id gfar_match[] = |
3301 | { | |
3302 | { | |
3303 | .type = "network", | |
3304 | .compatible = "gianfar", | |
3305 | }, | |
46ceb60c SG |
3306 | { |
3307 | .compatible = "fsl,etsec2", | |
3308 | }, | |
b31a1d8b AF |
3309 | {}, |
3310 | }; | |
e72701ac | 3311 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3312 | |
1da177e4 | 3313 | /* Structure for a device driver */ |
74888760 | 3314 | static struct platform_driver gfar_driver = { |
4018294b GL |
3315 | .driver = { |
3316 | .name = "fsl-gianfar", | |
3317 | .owner = THIS_MODULE, | |
3318 | .pm = GFAR_PM_OPS, | |
3319 | .of_match_table = gfar_match, | |
3320 | }, | |
1da177e4 LT |
3321 | .probe = gfar_probe, |
3322 | .remove = gfar_remove, | |
3323 | }; | |
3324 | ||
db62f684 | 3325 | module_platform_driver(gfar_driver); |