[linux-2.6-block.git] / drivers / net / ethernet / freescale / fec_ptp.c

/*
 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
 *
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/fec.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_net.h>

#include "fec.h"

/* FEC 1588 register bits */
#define FEC_T_CTRL_SLAVE                0x00002000
#define FEC_T_CTRL_CAPTURE              0x00000800
#define FEC_T_CTRL_RESTART              0x00000200
#define FEC_T_CTRL_PERIOD_RST           0x00000030
#define FEC_T_CTRL_PERIOD_EN		0x00000010
#define FEC_T_CTRL_ENABLE               0x00000001

#define FEC_T_INC_MASK                  0x0000007f
#define FEC_T_INC_OFFSET                0
#define FEC_T_INC_CORR_MASK             0x00007f00
#define FEC_T_INC_CORR_OFFSET           8

#define FEC_T_CTRL_PINPER		0x00000080
#define FEC_T_TF0_MASK			0x00000001
#define FEC_T_TF0_OFFSET		0
#define FEC_T_TF1_MASK			0x00000002
#define FEC_T_TF1_OFFSET		1
#define FEC_T_TF2_MASK			0x00000004
#define FEC_T_TF2_OFFSET		2
#define FEC_T_TF3_MASK			0x00000008
#define FEC_T_TF3_OFFSET		3
#define FEC_T_TDRE_MASK			0x00000001
#define FEC_T_TDRE_OFFSET		0
#define FEC_T_TMODE_MASK		0x0000003C
#define FEC_T_TMODE_OFFSET		2
#define FEC_T_TIE_MASK			0x00000040
#define FEC_T_TIE_OFFSET		6
#define FEC_T_TF_MASK			0x00000080
#define FEC_T_TF_OFFSET			7

#define FEC_ATIME_CTRL		0x400
#define FEC_ATIME		0x404
#define FEC_ATIME_EVT_OFFSET	0x408
#define FEC_ATIME_EVT_PERIOD	0x40c
#define FEC_ATIME_CORR		0x410
#define FEC_ATIME_INC		0x414
#define FEC_TS_TIMESTAMP	0x418

#define FEC_TGSR		0x604
#define FEC_TCSR(n)		(0x608 + n * 0x08)
#define FEC_TCCR(n)		(0x60C + n * 0x08)
#define MAX_TIMER_CHANNEL	3
#define FEC_TMODE_TOGGLE	0x05
#define FEC_HIGH_PULSE		0x0F

#define FEC_CC_MULT	(1 << 31)
#define FEC_COUNTER_PERIOD	(1 << 31)
#define PPS_OUPUT_RELOAD_PERIOD	NSEC_PER_SEC
#define FEC_CHANNLE_0		0
#define DEFAULT_PPS_CHANNEL	FEC_CHANNLE_0

/**
 * fec_ptp_enable_pps
 * @fep: the fec_enet_private structure handle
 * @enable: enable the channel pps output
 *
 * This function enble the PPS ouput on the timer channel.
 */
static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
{
	unsigned long flags;
	u32 val, tempval;
	int inc;
	struct timespec ts;
	u64 ns;
	u32 remainder;
	val = 0;

	if (!(fep->hwts_tx_en || fep->hwts_rx_en)) {
		dev_err(&fep->pdev->dev, "No ptp stack is running\n");
		return -EINVAL;
	}

	if (fep->pps_enable == enable)
		return 0;

	fep->pps_channel = DEFAULT_PPS_CHANNEL;
	fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
	inc = fep->ptp_inc;

	spin_lock_irqsave(&fep->tmreg_lock, flags);

	if (enable) {
		/* clear capture or output compare interrupt status if have.
		 */
		writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));

		/* It is recommended to double check the TMODE field in the
		 * TCSR register to be cleared before the first compare counter
		 * is written into TCCR register. Just add a double check.
		 */
		val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
		do {
			val &= ~(FEC_T_TMODE_MASK);
			writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
			val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
		} while (val & FEC_T_TMODE_MASK);

		/* Dummy read counter to update the counter */
		timecounter_read(&fep->tc);
		/* We want to find the first compare event in the next
		 * second point. So we need to know what the ptp time
		 * is now and how many nanoseconds is ahead to get next second.
		 * The remaining nanosecond ahead before the next second would be
		 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds
		 * to current timer would be next second.
		 */
		tempval = readl(fep->hwp + FEC_ATIME_CTRL);
		tempval |= FEC_T_CTRL_CAPTURE;
		writel(tempval, fep->hwp + FEC_ATIME_CTRL);

		tempval = readl(fep->hwp + FEC_ATIME);
		/* Convert the ptp local counter to 1588 timestamp */
		ns = timecounter_cyc2time(&fep->tc, tempval);
		ts.tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
		ts.tv_nsec = remainder;

		/* The tempval is  less than 3 seconds, and  so val is less than
		 * 4 seconds. No overflow for 32bit calculation.
		 */
		val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval;

		/* Need to consider the situation that the current time is
		 * very close to the second point, which means NSEC_PER_SEC
		 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
		 * is still running when we calculate the first compare event, it is
		 * possible that the remaining nanoseonds run out before the compare
		 * counter is calculated and written into TCCR register. To avoid
		 * this possibility, we will set the compare event to be the next
		 * of next second. The current setting is 31-bit timer and wrap
		 * around over 2 seconds. So it is okay to set the next of next
		 * seond for the timer.
		 */
		val += NSEC_PER_SEC;

		/* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current
		 * ptp counter, which maybe cause 32-bit wrap. Since the
		 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second.
		 * We can ensure the wrap will not cause issue. If the offset
		 * is bigger than fep->cc.mask would be a error.
		 */
		val &= fep->cc.mask;
		writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));

		/* Calculate the second the compare event timestamp */
		fep->next_counter = (val + fep->reload_period) & fep->cc.mask;

		/* * Enable compare event when overflow */
		val = readl(fep->hwp + FEC_ATIME_CTRL);
		val |= FEC_T_CTRL_PINPER;
		writel(val, fep->hwp + FEC_ATIME_CTRL);

		/* Compare channel setting. */
		val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
		val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET);
		val &= ~(1 << FEC_T_TDRE_OFFSET);
		val &= ~(FEC_T_TMODE_MASK);
		val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET);
		writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));

		/* Write the second compare event timestamp and calculate
		 * the third timestamp. Refer the TCCR register detail in the spec.
		 */
		writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
		fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
	} else {
		writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
	}

	fep->pps_enable = enable;
	spin_unlock_irqrestore(&fep->tmreg_lock, flags);

	return 0;
}

/**
 * fec_ptp_read - read raw cycle counter (to be used by time counter)
 * @cc: the cyclecounter structure
 *
 * this function reads the cyclecounter registers and is called by the
 * cyclecounter structure used to construct a ns counter from the
 * arbitrary fixed point registers
 */
static cycle_t fec_ptp_read(const struct cyclecounter *cc)
{
	struct fec_enet_private *fep =
		container_of(cc, struct fec_enet_private, cc);
	const struct platform_device_id *id_entry =
		platform_get_device_id(fep->pdev);
	u32 tempval;

	tempval = readl(fep->hwp + FEC_ATIME_CTRL);
	tempval |= FEC_T_CTRL_CAPTURE;
	writel(tempval, fep->hwp + FEC_ATIME_CTRL);

	if (id_entry->driver_data & FEC_QUIRK_BUG_CAPTURE)
		udelay(1);

	return readl(fep->hwp + FEC_ATIME);
}

/**
 * fec_ptp_start_cyclecounter - create the cycle counter from hw
 * @ndev: network device
 *
 * this function initializes the timecounter and cyclecounter
 * structures for use in generated a ns counter from the arbitrary
 * fixed point cycles registers in the hardware.
 */
void fec_ptp_start_cyclecounter(struct net_device *ndev)
{
	struct fec_enet_private *fep = netdev_priv(ndev);
	unsigned long flags;
	int inc;

	inc = 1000000000 / fep->cycle_speed;

	/* grab the ptp lock */
	spin_lock_irqsave(&fep->tmreg_lock, flags);

	/* 1ns counter */
	writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);

	/* use 31-bit timer counter */
	writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);

	writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST,
		fep->hwp + FEC_ATIME_CTRL);

	memset(&fep->cc, 0, sizeof(fep->cc));
	fep->cc.read = fec_ptp_read;
	fep->cc.mask = CLOCKSOURCE_MASK(31);
	fep->cc.shift = 31;
	fep->cc.mult = FEC_CC_MULT;

	/* reset the ns time counter */
	timecounter_init(&fep->tc, &fep->cc, ktime_to_ns(ktime_get_real()));

	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
}

/**
 * fec_ptp_adjfreq - adjust ptp cycle frequency
 * @ptp: the ptp clock structure
 * @ppb: parts per billion adjustment from base
 *
 * Adjust the frequency of the ptp cycle counter by the
 * indicated ppb from the base frequency.
 *
 * Because ENET hardware frequency adjust is complex,
 * using software method to do that.
 */
static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
	unsigned long flags;
	int neg_adj = 0;
	u32 i, tmp;
	u32 corr_inc, corr_period;
	u32 corr_ns;
	u64 lhs, rhs;

	struct fec_enet_private *fep =
	    container_of(ptp, struct fec_enet_private, ptp_caps);

	if (ppb == 0)
		return 0;

	if (ppb < 0) {
		ppb = -ppb;
		neg_adj = 1;
	}

	/* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC;
	 * Try to find the corr_inc  between 1 to fep->ptp_inc to
	 * meet adjustment requirement.
	 */
	lhs = NSEC_PER_SEC;
	rhs = (u64)ppb * (u64)fep->ptp_inc;
	for (i = 1; i <= fep->ptp_inc; i++) {
		if (lhs >= rhs) {
			corr_inc = i;
			corr_period = div_u64(lhs, rhs);
			break;
		}
		lhs += NSEC_PER_SEC;
	}
	/* Not found? Set it to high value - double speed
	 * correct in every clock step.
	 */
	if (i > fep->ptp_inc) {
		corr_inc = fep->ptp_inc;
		corr_period = 1;
	}

	if (neg_adj)
		corr_ns = fep->ptp_inc - corr_inc;
	else
		corr_ns = fep->ptp_inc + corr_inc;

	spin_lock_irqsave(&fep->tmreg_lock, flags);

	tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
	tmp |= corr_ns << FEC_T_INC_CORR_OFFSET;
	writel(tmp, fep->hwp + FEC_ATIME_INC);
	writel(corr_period, fep->hwp + FEC_ATIME_CORR);
	/* dummy read to update the timer. */
	timecounter_read(&fep->tc);

	spin_unlock_irqrestore(&fep->tmreg_lock, flags);

	return 0;
}

/**
 * fec_ptp_adjtime
 * @ptp: the ptp clock structure
 * @delta: offset to adjust the cycle counter by
 *
 * adjust the timer by resetting the timecounter structure.
 */
static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	struct fec_enet_private *fep =
	    container_of(ptp, struct fec_enet_private, ptp_caps);
	unsigned long flags;

	spin_lock_irqsave(&fep->tmreg_lock, flags);
	timecounter_adjtime(&fep->tc, delta);
	spin_unlock_irqrestore(&fep->tmreg_lock, flags);

	return 0;
}

/**
 * fec_ptp_gettime
 * @ptp: the ptp clock structure
 * @ts: timespec structure to hold the current time value
 *
 * read the timecounter and return the correct value on ns,
 * after converting it into a struct timespec.
 */
static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
{
	struct fec_enet_private *adapter =
	    container_of(ptp, struct fec_enet_private, ptp_caps);
	u64 ns;
	u32 remainder;
	unsigned long flags;

	spin_lock_irqsave(&adapter->tmreg_lock, flags);
	ns = timecounter_read(&adapter->tc);
	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);

	ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
	ts->tv_nsec = remainder;

	return 0;
}

/**
 * fec_ptp_settime
 * @ptp: the ptp clock structure
 * @ts: the timespec containing the new time for the cycle counter
 *
 * reset the timecounter to use a new base value instead of the kernel
 * wall timer value.
 */
static int fec_ptp_settime(struct ptp_clock_info *ptp,
			   const struct timespec64 *ts)
{
	struct fec_enet_private *fep =
	    container_of(ptp, struct fec_enet_private, ptp_caps);

	u64 ns;
	unsigned long flags;
	u32 counter;

	mutex_lock(&fep->ptp_clk_mutex);
	/* Check the ptp clock */
	if (!fep->ptp_clk_on) {
		mutex_unlock(&fep->ptp_clk_mutex);
		return -EINVAL;
	}

	ns = ts->tv_sec * 1000000000ULL;
	ns += ts->tv_nsec;
	/* Get the timer value based on timestamp.
	 * Update the counter with the masked value.
	 */
	counter = ns & fep->cc.mask;

	spin_lock_irqsave(&fep->tmreg_lock, flags);
	writel(counter, fep->hwp + FEC_ATIME);
	timecounter_init(&fep->tc, &fep->cc, ns);
	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
	mutex_unlock(&fep->ptp_clk_mutex);
	return 0;
}

/**
 * fec_ptp_enable
 * @ptp: the ptp clock structure
 * @rq: the requested feature to change
 * @on: whether to enable or disable the feature
 *
 */
static int fec_ptp_enable(struct ptp_clock_info *ptp,
			  struct ptp_clock_request *rq, int on)
{
	struct fec_enet_private *fep =
	    container_of(ptp, struct fec_enet_private, ptp_caps);
	int ret = 0;

	if (rq->type == PTP_CLK_REQ_PPS) {
		ret = fec_ptp_enable_pps(fep, on);

		return ret;
	}
	return -EOPNOTSUPP;
}

/**
 * fec_ptp_hwtstamp_ioctl - control hardware time stamping
 * @ndev: pointer to net_device
 * @ifreq: ioctl data
 * @cmd: particular ioctl requested
 */
int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr)
{
	struct fec_enet_private *fep = netdev_priv(ndev);

	struct hwtstamp_config config;

	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
		return -EFAULT;

	/* reserved for future extensions */
	if (config.flags)
		return -EINVAL;

	switch (config.tx_type) {
	case HWTSTAMP_TX_OFF:
		fep->hwts_tx_en = 0;
		break;
	case HWTSTAMP_TX_ON:
		fep->hwts_tx_en = 1;
		break;
	default:
		return -ERANGE;
	}

	switch (config.rx_filter) {
	case HWTSTAMP_FILTER_NONE:
		if (fep->hwts_rx_en)
			fep->hwts_rx_en = 0;
		config.rx_filter = HWTSTAMP_FILTER_NONE;
		break;

	default:
		/*
		 * register RXMTRL must be set in order to do V1 packets,
		 * therefore it is not possible to time stamp both V1 Sync and
		 * Delay_Req messages and hardware does not support
		 * timestamping all packets => return error
		 */
		fep->hwts_rx_en = 1;
		config.rx_filter = HWTSTAMP_FILTER_ALL;
		break;
	}

	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
	    -EFAULT : 0;
}

int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr)
{
	struct fec_enet_private *fep = netdev_priv(ndev);
	struct hwtstamp_config config;

	config.flags = 0;
	config.tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
	config.rx_filter = (fep->hwts_rx_en ?
			    HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);

	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
		-EFAULT : 0;
}

/**
 * fec_time_keep - call timecounter_read every second to avoid timer overrun
 *                 because ENET just support 32bit counter, will timeout in 4s
 */
static void fec_time_keep(struct work_struct *work)
{
	struct delayed_work *dwork = to_delayed_work(work);
	struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep);
	u64 ns;
	unsigned long flags;

	mutex_lock(&fep->ptp_clk_mutex);
	if (fep->ptp_clk_on) {
		spin_lock_irqsave(&fep->tmreg_lock, flags);
		ns = timecounter_read(&fep->tc);
		spin_unlock_irqrestore(&fep->tmreg_lock, flags);
	}
	mutex_unlock(&fep->ptp_clk_mutex);

	schedule_delayed_work(&fep->time_keep, HZ);
}

/**
 * fec_ptp_init
 * @ndev: The FEC network adapter
 *
 * This function performs the required steps for enabling ptp
 * support. If ptp support has already been loaded it simply calls the
 * cyclecounter init routine and exits.
 */

void fec_ptp_init(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);
	struct fec_enet_private *fep = netdev_priv(ndev);

	fep->ptp_caps.owner = THIS_MODULE;
	snprintf(fep->ptp_caps.name, 16, "fec ptp");

	fep->ptp_caps.max_adj = 250000000;
	fep->ptp_caps.n_alarm = 0;
	fep->ptp_caps.n_ext_ts = 0;
	fep->ptp_caps.n_per_out = 0;
	fep->ptp_caps.n_pins = 0;
	fep->ptp_caps.pps = 1;
	fep->ptp_caps.adjfreq = fec_ptp_adjfreq;
	fep->ptp_caps.adjtime = fec_ptp_adjtime;
	fep->ptp_caps.gettime64 = fec_ptp_gettime;
	fep->ptp_caps.settime64 = fec_ptp_settime;
	fep->ptp_caps.enable = fec_ptp_enable;

	fep->cycle_speed = clk_get_rate(fep->clk_ptp);
	fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;

	spin_lock_init(&fep->tmreg_lock);

	fec_ptp_start_cyclecounter(ndev);

	INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);

	fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
	if (IS_ERR(fep->ptp_clock)) {
		fep->ptp_clock = NULL;
		pr_err("ptp_clock_register failed\n");
	}

	schedule_delayed_work(&fep->time_keep, HZ);
}

/**
 * fec_ptp_check_pps_event
 * @fep: the fec_enet_private structure handle
 *
 * This function check the pps event and reload the timer compare counter.
 */
uint fec_ptp_check_pps_event(struct fec_enet_private *fep)
{
	u32 val;
	u8 channel = fep->pps_channel;
	struct ptp_clock_event event;

	val = readl(fep->hwp + FEC_TCSR(channel));
	if (val & FEC_T_TF_MASK) {
		/* Write the next next compare(not the next according the spec)
		 * value to the register
		 */
		writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
		do {
			writel(val, fep->hwp + FEC_TCSR(channel));
		} while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);

		/* Update the counter; */
		fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;

		event.type = PTP_CLOCK_PPS;
		ptp_clock_event(fep->ptp_clock, &event);
		return 1;
	}

	return 0;
}
Commit	Line	Data
6605b730 FL	1	/*
	2	* Fast Ethernet Controller (ENET) PTP driver for MX6x.
	3	*
	4	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program; if not, write to the Free Software Foundation, Inc.,
	17	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	*/
	19
31b7720c JP	20	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31b7720c JP	21
6605b730 FL	22	#include <linux/module.h>
	23	#include <linux/kernel.h>
	24	#include <linux/string.h>
	25	#include <linux/ptrace.h>
	26	#include <linux/errno.h>
	27	#include <linux/ioport.h>
	28	#include <linux/slab.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/pci.h>
6605b730 FL	31	#include <linux/delay.h>
	32	#include <linux/netdevice.h>
	33	#include <linux/etherdevice.h>
	34	#include <linux/skbuff.h>
	35	#include <linux/spinlock.h>
	36	#include <linux/workqueue.h>
	37	#include <linux/bitops.h>
	38	#include <linux/io.h>
	39	#include <linux/irq.h>
	40	#include <linux/clk.h>
	41	#include <linux/platform_device.h>
	42	#include <linux/phy.h>
	43	#include <linux/fec.h>
	44	#include <linux/of.h>
	45	#include <linux/of_device.h>
	46	#include <linux/of_gpio.h>
	47	#include <linux/of_net.h>
	48
	49	#include "fec.h"
	50
	51	/* FEC 1588 register bits */
	52	#define FEC_T_CTRL_SLAVE 0x00002000
	53	#define FEC_T_CTRL_CAPTURE 0x00000800
	54	#define FEC_T_CTRL_RESTART 0x00000200
	55	#define FEC_T_CTRL_PERIOD_RST 0x00000030
	56	#define FEC_T_CTRL_PERIOD_EN 0x00000010
	57	#define FEC_T_CTRL_ENABLE 0x00000001
	58
	59	#define FEC_T_INC_MASK 0x0000007f
	60	#define FEC_T_INC_OFFSET 0
	61	#define FEC_T_INC_CORR_MASK 0x00007f00
	62	#define FEC_T_INC_CORR_OFFSET 8
	63
278d2404 LZ	64	#define FEC_T_CTRL_PINPER 0x00000080
	65	#define FEC_T_TF0_MASK 0x00000001
	66	#define FEC_T_TF0_OFFSET 0
	67	#define FEC_T_TF1_MASK 0x00000002
	68	#define FEC_T_TF1_OFFSET 1
	69	#define FEC_T_TF2_MASK 0x00000004
	70	#define FEC_T_TF2_OFFSET 2
	71	#define FEC_T_TF3_MASK 0x00000008
	72	#define FEC_T_TF3_OFFSET 3
	73	#define FEC_T_TDRE_MASK 0x00000001
	74	#define FEC_T_TDRE_OFFSET 0
	75	#define FEC_T_TMODE_MASK 0x0000003C
	76	#define FEC_T_TMODE_OFFSET 2
	77	#define FEC_T_TIE_MASK 0x00000040
	78	#define FEC_T_TIE_OFFSET 6
	79	#define FEC_T_TF_MASK 0x00000080
	80	#define FEC_T_TF_OFFSET 7
	81
6605b730 FL	82	#define FEC_ATIME_CTRL 0x400
	83	#define FEC_ATIME 0x404
	84	#define FEC_ATIME_EVT_OFFSET 0x408
	85	#define FEC_ATIME_EVT_PERIOD 0x40c
	86	#define FEC_ATIME_CORR 0x410
	87	#define FEC_ATIME_INC 0x414
	88	#define FEC_TS_TIMESTAMP 0x418
	89
278d2404 LZ	90	#define FEC_TGSR 0x604
	91	#define FEC_TCSR(n) (0x608 + n * 0x08)
	92	#define FEC_TCCR(n) (0x60C + n * 0x08)
	93	#define MAX_TIMER_CHANNEL 3
	94	#define FEC_TMODE_TOGGLE 0x05
	95	#define FEC_HIGH_PULSE 0x0F
	96
6605b730	97	#define FEC_CC_MULT (1 << 31)
f28460b2	98	#define FEC_COUNTER_PERIOD (1 << 31)
278d2404 LZ	99	#define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC
	100	#define FEC_CHANNLE_0 0
	101	#define DEFAULT_PPS_CHANNEL FEC_CHANNLE_0
	102
	103	/**
	104	* fec_ptp_enable_pps
	105	* @fep: the fec_enet_private structure handle
	106	* @enable: enable the channel pps output
	107	*
	108	* This function enble the PPS ouput on the timer channel.
	109	*/
	110	static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
	111	{
	112	unsigned long flags;
	113	u32 val, tempval;
	114	int inc;
	115	struct timespec ts;
	116	u64 ns;
	117	u32 remainder;
	118	val = 0;
	119
	120	if (!(fep->hwts_tx_en \|\| fep->hwts_rx_en)) {
	121	dev_err(&fep->pdev->dev, "No ptp stack is running\n");
	122	return -EINVAL;
	123	}
	124
	125	if (fep->pps_enable == enable)
	126	return 0;
	127
	128	fep->pps_channel = DEFAULT_PPS_CHANNEL;
	129	fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
	130	inc = fep->ptp_inc;
	131
	132	spin_lock_irqsave(&fep->tmreg_lock, flags);
	133
	134	if (enable) {
	135	/* clear capture or output compare interrupt status if have.
	136	*/
	137	writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
	138
dbedd44e	139	/* It is recommended to double check the TMODE field in the
278d2404 LZ	140	* TCSR register to be cleared before the first compare counter
	141	* is written into TCCR register. Just add a double check.
	142	*/
	143	val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
	144	do {
	145	val &= ~(FEC_T_TMODE_MASK);
	146	writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
	147	val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
	148	} while (val & FEC_T_TMODE_MASK);
	149
	150	/* Dummy read counter to update the counter */
	151	timecounter_read(&fep->tc);
	152	/* We want to find the first compare event in the next
	153	* second point. So we need to know what the ptp time
	154	* is now and how many nanoseconds is ahead to get next second.
	155	* The remaining nanosecond ahead before the next second would be
	156	* NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds
	157	* to current timer would be next second.
	158	*/
	159	tempval = readl(fep->hwp + FEC_ATIME_CTRL);
	160	tempval \|= FEC_T_CTRL_CAPTURE;
	161	writel(tempval, fep->hwp + FEC_ATIME_CTRL);
	162
	163	tempval = readl(fep->hwp + FEC_ATIME);
	164	/* Convert the ptp local counter to 1588 timestamp */
	165	ns = timecounter_cyc2time(&fep->tc, tempval);
	166	ts.tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
	167	ts.tv_nsec = remainder;
	168
	169	/* The tempval is less than 3 seconds, and so val is less than
	170	* 4 seconds. No overflow for 32bit calculation.
	171	*/
	172	val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval;
	173
	174	/* Need to consider the situation that the current time is
	175	* very close to the second point, which means NSEC_PER_SEC
	176	* - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
	177	* is still running when we calculate the first compare event, it is
	178	* possible that the remaining nanoseonds run out before the compare
	179	* counter is calculated and written into TCCR register. To avoid
	180	* this possibility, we will set the compare event to be the next
	181	* of next second. The current setting is 31-bit timer and wrap
	182	* around over 2 seconds. So it is okay to set the next of next
	183	* seond for the timer.
	184	*/
	185	val += NSEC_PER_SEC;
	186
	187	/* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current
	188	* ptp counter, which maybe cause 32-bit wrap. Since the
	189	* (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second.
	190	* We can ensure the wrap will not cause issue. If the offset
	191	* is bigger than fep->cc.mask would be a error.
	192	*/
	193	val &= fep->cc.mask;
	194	writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
	195
	196	/* Calculate the second the compare event timestamp */
	197	fep->next_counter = (val + fep->reload_period) & fep->cc.mask;
	198
	199	/* * Enable compare event when overflow */
	200	val = readl(fep->hwp + FEC_ATIME_CTRL);
	201	val \|= FEC_T_CTRL_PINPER;
	202	writel(val, fep->hwp + FEC_ATIME_CTRL);
	203
204	/* Compare channel setting. */
205	val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
206	val \|= (1 << FEC_T_TF_OFFSET \| 1 << FEC_T_TIE_OFFSET);
207	val &= ~(1 << FEC_T_TDRE_OFFSET);
208	val &= ~(FEC_T_TMODE_MASK);
209	val \|= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET);
210	writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
211
212	/* Write the second compare event timestamp and calculate
213	* the third timestamp. Refer the TCCR register detail in the spec.
214	*/
215	writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
216	fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
217	} else {
218	writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
219	}
220
221	fep->pps_enable = enable;
222	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
223
224	return 0;
225	}
226
6605b730 FL	227	/**
	228	* fec_ptp_read - read raw cycle counter (to be used by time counter)
	229	* @cc: the cyclecounter structure
	230	*
	231	* this function reads the cyclecounter registers and is called by the
	232	* cyclecounter structure used to construct a ns counter from the
	233	* arbitrary fixed point registers
	234	*/
	235	static cycle_t fec_ptp_read(const struct cyclecounter *cc)
	236	{
	237	struct fec_enet_private *fep =
	238	container_of(cc, struct fec_enet_private, cc);
28b5f058 NA	239	const struct platform_device_id *id_entry =
28b5f058 NA	240	platform_get_device_id(fep->pdev);
6605b730 FL	241	u32 tempval;
	242
	243	tempval = readl(fep->hwp + FEC_ATIME_CTRL);
	244	tempval \|= FEC_T_CTRL_CAPTURE;
	245	writel(tempval, fep->hwp + FEC_ATIME_CTRL);
	246
28b5f058 NA	247	if (id_entry->driver_data & FEC_QUIRK_BUG_CAPTURE)
	248	udelay(1);
	249
6605b730 FL	250	return readl(fep->hwp + FEC_ATIME);
	251	}
	252
	253	/**
	254	* fec_ptp_start_cyclecounter - create the cycle counter from hw
	255	* @ndev: network device
	256	*
	257	* this function initializes the timecounter and cyclecounter
	258	* structures for use in generated a ns counter from the arbitrary
	259	* fixed point cycles registers in the hardware.
	260	*/
	261	void fec_ptp_start_cyclecounter(struct net_device *ndev)
	262	{
	263	struct fec_enet_private *fep = netdev_priv(ndev);
	264	unsigned long flags;
	265	int inc;
	266
85bd1798	267	inc = 1000000000 / fep->cycle_speed;
6605b730 FL	268
	269	/* grab the ptp lock */
	270	spin_lock_irqsave(&fep->tmreg_lock, flags);
	271
	272	/* 1ns counter */
	273	writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
	274
f28460b2 LZ	275	/* use 31-bit timer counter */
f28460b2 LZ	276	writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
6605b730	277
f28460b2 LZ	278	writel(FEC_T_CTRL_ENABLE \| FEC_T_CTRL_PERIOD_RST,
f28460b2 LZ	279	fep->hwp + FEC_ATIME_CTRL);
6605b730 FL	280
	281	memset(&fep->cc, 0, sizeof(fep->cc));
	282	fep->cc.read = fec_ptp_read;
f28460b2	283	fep->cc.mask = CLOCKSOURCE_MASK(31);
6605b730 FL	284	fep->cc.shift = 31;
	285	fep->cc.mult = FEC_CC_MULT;
	286
	287	/* reset the ns time counter */
	288	timecounter_init(&fep->tc, &fep->cc, ktime_to_ns(ktime_get_real()));
	289
	290	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
	291	}
	292
	293	/**
	294	* fec_ptp_adjfreq - adjust ptp cycle frequency
	295	* @ptp: the ptp clock structure
	296	* @ppb: parts per billion adjustment from base
	297	*
	298	* Adjust the frequency of the ptp cycle counter by the
	299	* indicated ppb from the base frequency.
	300	*
	301	* Because ENET hardware frequency adjust is complex,
	302	* using software method to do that.
	303	*/
	304	static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
	305	{
6605b730 FL	306	unsigned long flags;
6605b730 FL	307	int neg_adj = 0;
89bddcda LZ	308	u32 i, tmp;
	309	u32 corr_inc, corr_period;
	310	u32 corr_ns;
	311	u64 lhs, rhs;
6605b730 FL	312
	313	struct fec_enet_private *fep =
	314	container_of(ptp, struct fec_enet_private, ptp_caps);
	315
89bddcda LZ	316	if (ppb == 0)
	317	return 0;
	318
6605b730 FL	319	if (ppb < 0) {
	320	ppb = -ppb;
	321	neg_adj = 1;
	322	}
	323
89bddcda LZ	324	/* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC;
	325	* Try to find the corr_inc between 1 to fep->ptp_inc to
	326	* meet adjustment requirement.
	327	*/
	328	lhs = NSEC_PER_SEC;
	329	rhs = (u64)ppb * (u64)fep->ptp_inc;
	330	for (i = 1; i <= fep->ptp_inc; i++) {
	331	if (lhs >= rhs) {
	332	corr_inc = i;
	333	corr_period = div_u64(lhs, rhs);
	334	break;
	335	}
	336	lhs += NSEC_PER_SEC;
	337	}
	338	/* Not found? Set it to high value - double speed
	339	* correct in every clock step.
	340	*/
	341	if (i > fep->ptp_inc) {
	342	corr_inc = fep->ptp_inc;
	343	corr_period = 1;
	344	}
	345
	346	if (neg_adj)
	347	corr_ns = fep->ptp_inc - corr_inc;
	348	else
	349	corr_ns = fep->ptp_inc + corr_inc;
7da716ae	350
6605b730	351	spin_lock_irqsave(&fep->tmreg_lock, flags);
6605b730	352
89bddcda LZ	353	tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
	354	tmp \|= corr_ns << FEC_T_INC_CORR_OFFSET;
	355	writel(tmp, fep->hwp + FEC_ATIME_INC);
	356	writel(corr_period, fep->hwp + FEC_ATIME_CORR);
	357	/* dummy read to update the timer. */
	358	timecounter_read(&fep->tc);
6605b730 FL	359
	360	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
	361
	362	return 0;
	363	}
	364
	365	/**
	366	* fec_ptp_adjtime
	367	* @ptp: the ptp clock structure
	368	* @delta: offset to adjust the cycle counter by
	369	*
	370	* adjust the timer by resetting the timecounter structure.
	371	*/
	372	static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
	373	{
	374	struct fec_enet_private *fep =
	375	container_of(ptp, struct fec_enet_private, ptp_caps);
	376	unsigned long flags;
6605b730 FL	377
6605b730 FL	378	spin_lock_irqsave(&fep->tmreg_lock, flags);
59e16961	379	timecounter_adjtime(&fep->tc, delta);
6605b730 FL	380	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
	381
	382	return 0;
	383	}
	384
	385	/**
	386	* fec_ptp_gettime
	387	* @ptp: the ptp clock structure
	388	* @ts: timespec structure to hold the current time value
	389	*
	390	* read the timecounter and return the correct value on ns,
	391	* after converting it into a struct timespec.
	392	*/
241926bc	393	static int fec_ptp_gettime(struct ptp_clock_info ptp, struct timespec64 ts)
6605b730 FL	394	{
	395	struct fec_enet_private *adapter =
	396	container_of(ptp, struct fec_enet_private, ptp_caps);
	397	u64 ns;
	398	u32 remainder;
	399	unsigned long flags;
	400
	401	spin_lock_irqsave(&adapter->tmreg_lock, flags);
	402	ns = timecounter_read(&adapter->tc);
	403	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
	404
	405	ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
	406	ts->tv_nsec = remainder;
	407
	408	return 0;
	409	}
	410
	411	/**
	412	* fec_ptp_settime
	413	* @ptp: the ptp clock structure
	414	* @ts: the timespec containing the new time for the cycle counter
	415	*
	416	* reset the timecounter to use a new base value instead of the kernel
	417	* wall timer value.
	418	*/
	419	static int fec_ptp_settime(struct ptp_clock_info *ptp,
241926bc	420	const struct timespec64 *ts)
6605b730 FL	421	{
	422	struct fec_enet_private *fep =
	423	container_of(ptp, struct fec_enet_private, ptp_caps);
	424
	425	u64 ns;
	426	unsigned long flags;
89bddcda	427	u32 counter;
6605b730	428
91c0d987 NA	429	mutex_lock(&fep->ptp_clk_mutex);
	430	/* Check the ptp clock */
	431	if (!fep->ptp_clk_on) {
	432	mutex_unlock(&fep->ptp_clk_mutex);
	433	return -EINVAL;
	434	}
	435
6605b730 FL	436	ns = ts->tv_sec * 1000000000ULL;
6605b730 FL	437	ns += ts->tv_nsec;
89bddcda LZ	438	/* Get the timer value based on timestamp.
	439	* Update the counter with the masked value.
	440	*/
	441	counter = ns & fep->cc.mask;
6605b730 FL	442
6605b730 FL	443	spin_lock_irqsave(&fep->tmreg_lock, flags);
89bddcda	444	writel(counter, fep->hwp + FEC_ATIME);
6605b730 FL	445	timecounter_init(&fep->tc, &fep->cc, ns);
6605b730 FL	446	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
91c0d987	447	mutex_unlock(&fep->ptp_clk_mutex);
6605b730 FL	448	return 0;
	449	}
	450
	451	/**
	452	* fec_ptp_enable
	453	* @ptp: the ptp clock structure
	454	* @rq: the requested feature to change
	455	* @on: whether to enable or disable the feature
	456	*
	457	*/
	458	static int fec_ptp_enable(struct ptp_clock_info *ptp,
	459	struct ptp_clock_request *rq, int on)
	460	{
278d2404 LZ	461	struct fec_enet_private *fep =
	462	container_of(ptp, struct fec_enet_private, ptp_caps);
	463	int ret = 0;
	464
	465	if (rq->type == PTP_CLK_REQ_PPS) {
	466	ret = fec_ptp_enable_pps(fep, on);
	467
	468	return ret;
	469	}
6605b730 FL	470	return -EOPNOTSUPP;
	471	}
	472
	473	/**
	474	* fec_ptp_hwtstamp_ioctl - control hardware time stamping
	475	* @ndev: pointer to net_device
	476	* @ifreq: ioctl data
	477	* @cmd: particular ioctl requested
	478	*/
1d5244d0	479	int fec_ptp_set(struct net_device ndev, struct ifreq ifr)
6605b730 FL	480	{
	481	struct fec_enet_private *fep = netdev_priv(ndev);
	482
	483	struct hwtstamp_config config;
	484
	485	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
	486	return -EFAULT;
	487
	488	/* reserved for future extensions */
	489	if (config.flags)
	490	return -EINVAL;
	491
	492	switch (config.tx_type) {
	493	case HWTSTAMP_TX_OFF:
	494	fep->hwts_tx_en = 0;
	495	break;
	496	case HWTSTAMP_TX_ON:
	497	fep->hwts_tx_en = 1;
	498	break;
	499	default:
	500	return -ERANGE;
	501	}
	502
	503	switch (config.rx_filter) {
	504	case HWTSTAMP_FILTER_NONE:
	505	if (fep->hwts_rx_en)
	506	fep->hwts_rx_en = 0;
	507	config.rx_filter = HWTSTAMP_FILTER_NONE;
	508	break;
	509
	510	default:
	511	/*
	512	* register RXMTRL must be set in order to do V1 packets,
	513	* therefore it is not possible to time stamp both V1 Sync and
	514	* Delay_Req messages and hardware does not support
	515	* timestamping all packets => return error
	516	*/
	517	fep->hwts_rx_en = 1;
	518	config.rx_filter = HWTSTAMP_FILTER_ALL;
	519	break;
	520	}
	521
	522	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
	523	-EFAULT : 0;
	524	}
	525
1d5244d0 BH	526	int fec_ptp_get(struct net_device ndev, struct ifreq ifr)
	527	{
	528	struct fec_enet_private *fep = netdev_priv(ndev);
	529	struct hwtstamp_config config;
	530
	531	config.flags = 0;
	532	config.tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
	533	config.rx_filter = (fep->hwts_rx_en ?
	534	HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
	535
	536	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
	537	-EFAULT : 0;
	538	}
	539
6605b730 FL	540	/**
	541	* fec_time_keep - call timecounter_read every second to avoid timer overrun
	542	* because ENET just support 32bit counter, will timeout in 4s
	543	*/
91c0d987	544	static void fec_time_keep(struct work_struct *work)
6605b730	545	{
91c0d987 NA	546	struct delayed_work *dwork = to_delayed_work(work);
91c0d987 NA	547	struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep);
6605b730 FL	548	u64 ns;
	549	unsigned long flags;
	550
91c0d987 NA	551	mutex_lock(&fep->ptp_clk_mutex);
	552	if (fep->ptp_clk_on) {
	553	spin_lock_irqsave(&fep->tmreg_lock, flags);
	554	ns = timecounter_read(&fep->tc);
	555	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
	556	}
	557	mutex_unlock(&fep->ptp_clk_mutex);
6605b730	558
91c0d987	559	schedule_delayed_work(&fep->time_keep, HZ);
6605b730 FL	560	}
	561
	562	/**
	563	* fec_ptp_init
	564	* @ndev: The FEC network adapter
	565	*
	566	* This function performs the required steps for enabling ptp
	567	* support. If ptp support has already been loaded it simply calls the
	568	* cyclecounter init routine and exits.
	569	*/
	570
ca162a82	571	void fec_ptp_init(struct platform_device *pdev)
6605b730	572	{
ca162a82	573	struct net_device *ndev = platform_get_drvdata(pdev);
6605b730 FL	574	struct fec_enet_private *fep = netdev_priv(ndev);
	575
	576	fep->ptp_caps.owner = THIS_MODULE;
	577	snprintf(fep->ptp_caps.name, 16, "fec ptp");
	578
	579	fep->ptp_caps.max_adj = 250000000;
	580	fep->ptp_caps.n_alarm = 0;
	581	fep->ptp_caps.n_ext_ts = 0;
	582	fep->ptp_caps.n_per_out = 0;
4986b4f0	583	fep->ptp_caps.n_pins = 0;
278d2404	584	fep->ptp_caps.pps = 1;
6605b730 FL	585	fep->ptp_caps.adjfreq = fec_ptp_adjfreq;
6605b730 FL	586	fep->ptp_caps.adjtime = fec_ptp_adjtime;
241926bc RC	587	fep->ptp_caps.gettime64 = fec_ptp_gettime;
241926bc RC	588	fep->ptp_caps.settime64 = fec_ptp_settime;
6605b730 FL	589	fep->ptp_caps.enable = fec_ptp_enable;
6605b730 FL	590
85bd1798	591	fep->cycle_speed = clk_get_rate(fep->clk_ptp);
89bddcda	592	fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;
85bd1798	593
6605b730 FL	594	spin_lock_init(&fep->tmreg_lock);
	595
	596	fec_ptp_start_cyclecounter(ndev);
	597
91c0d987	598	INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);
6605b730 FL	599
	600	fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
	601	if (IS_ERR(fep->ptp_clock)) {
	602	fep->ptp_clock = NULL;
	603	pr_err("ptp_clock_register failed\n");
6605b730	604	}
91c0d987 NA	605
91c0d987 NA	606	schedule_delayed_work(&fep->time_keep, HZ);
6605b730	607	}
278d2404 LZ	608
	609	/**
	610	* fec_ptp_check_pps_event
	611	* @fep: the fec_enet_private structure handle
	612	*
	613	* This function check the pps event and reload the timer compare counter.
	614	*/
	615	uint fec_ptp_check_pps_event(struct fec_enet_private *fep)
	616	{
	617	u32 val;
	618	u8 channel = fep->pps_channel;
	619	struct ptp_clock_event event;
	620
	621	val = readl(fep->hwp + FEC_TCSR(channel));
	622	if (val & FEC_T_TF_MASK) {
	623	/* Write the next next compare(not the next according the spec)
	624	* value to the register
	625	*/
	626	writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
	627	do {
	628	writel(val, fep->hwp + FEC_TCSR(channel));
	629	} while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);
	630
	631	/* Update the counter; */
	632	fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
	633
	634	event.type = PTP_CLOCK_PPS;
	635	ptp_clock_event(fep->ptp_clock, &event);
	636	return 1;
	637	}
	638
	639	return 0;
	640	}