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defxx: fix build warning
[linux-2.6-block.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
8fff755e 27#include <linux/pm_runtime.h>
1da177e4
LT		 28#include <linux/ptrace.h>
29#include <linux/errno.h>
30#include <linux/ioport.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
4c09eed9
JB		 37#include <linux/in.h>
38#include <linux/ip.h>
39#include <net/ip.h>
79f33912 40#include <net/tso.h>
4c09eed9
JB		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/icmp.h>
1da177e4
LT		 44#include <linux/spinlock.h>
45#include <linux/workqueue.h>
46#include <linux/bitops.h>
6f501b17
SH		 47#include <linux/io.h>
48#include <linux/irq.h>
196719ec 49#include <linux/clk.h>
ead73183 50#include <linux/platform_device.h>
7f854420 51#include <linux/mdio.h>
e6b043d5 52#include <linux/phy.h>
5eb32bd0 53#include <linux/fec.h>
ca2cc333
SG		 54#include <linux/of.h>
55#include <linux/of_device.h>
56#include <linux/of_gpio.h>
407066f8 57#include <linux/of_mdio.h>
ca2cc333 58#include <linux/of_net.h>
5fa9c0fe 59#include <linux/regulator/consumer.h>
cdffcf1b 60#include <linux/if_vlan.h>
a68ab98e 61#include <linux/pinctrl/consumer.h>
c259c132 62#include <linux/prefetch.h>
1da177e4 63
080853af 64#include <asm/cacheflush.h>
196719ec 65
1da177e4 66#include "fec.h"
1da177e4 67
772e42b0 68static void set_multicast_list(struct net_device *ndev);
d851b47b 69static void fec_enet_itr_coal_init(struct net_device *ndev);
772e42b0 70
b5680e0b
SG		 71#define DRIVER_NAME "fec"
72
4d494cdc
FD		 73#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
74
baa70a5c
FL		 75/* Pause frame feild and FIFO threshold */
76#define FEC_ENET_FCE (1 << 5)
77#define FEC_ENET_RSEM_V 0x84
78#define FEC_ENET_RSFL_V 16
79#define FEC_ENET_RAEM_V 0x8
80#define FEC_ENET_RAFL_V 0x8
81#define FEC_ENET_OPD_V 0xFFF0
8fff755e 82#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
baa70a5c 83
b5680e0b
SG		 84static struct platform_device_id fec_devtype[] = {
85 {
0ca1e290 86 /* keep it for coldfire */
b5680e0b
SG		 87 .name = DRIVER_NAME,
88 .driver_data = 0,
0ca1e290
SG		 89 }, {
90 .name = "imx25-fec",
18803495 91 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
0ca1e290
SG		 92 }, {
93 .name = "imx27-fec",
18803495 94 .driver_data = FEC_QUIRK_HAS_RACC,
b5680e0b
SG		 95 }, {
96 .name = "imx28-fec",
3d125f9c 97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
18803495 98 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
230dec61
SG		 99 }, {
100 .name = "imx6q-fec",
ff43da86 101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 102 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
18803495
GU		 103 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
104 FEC_QUIRK_HAS_RACC,
ca7c4a45 105 }, {
36803542 106 .name = "mvf600-fec",
18803495 107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
95a77470
FD		 108 }, {
109 .name = "imx6sx-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
f88c7ede 112 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
18803495
GU		 113 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
114 FEC_QUIRK_HAS_RACC,
0ca1e290
SG		 115 }, {
116 /* sentinel */
117 }
b5680e0b 118};
0ca1e290 119MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 120
ca2cc333 121enum imx_fec_type {
a7dd3219 122 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 123 IMX27_FEC, /* runs on i.mx27/35/51 */
124 IMX28_FEC,
230dec61 125 IMX6Q_FEC,
36803542 126 MVF600_FEC,
ba593e00 127 IMX6SX_FEC,
ca2cc333
SG		 128};
129
130static const struct of_device_id fec_dt_ids[] = {
131 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
132 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
133 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 134 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 135 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ba593e00 136 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
ca2cc333
SG		 137 { /* sentinel */ }
138};
139MODULE_DEVICE_TABLE(of, fec_dt_ids);
140
49da97dc
SG		 141static unsigned char macaddr[ETH_ALEN];
142module_param_array(macaddr, byte, NULL, 0);
143MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 144
49da97dc 145#if defined(CONFIG_M5272)
1da177e4
LT		 146/*
147 * Some hardware gets it MAC address out of local flash memory.
148 * if this is non-zero then assume it is the address to get MAC from.
149 */
150#if defined(CONFIG_NETtel)
151#define FEC_FLASHMAC 0xf0006006
152#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
153#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 154#elif defined(CONFIG_CANCam)
155#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 156#elif defined (CONFIG_M5272C3)
157#define FEC_FLASHMAC (0xffe04000 + 4)
158#elif defined(CONFIG_MOD5272)
a7dd3219 159#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 160#else
161#define FEC_FLASHMAC 0
162#endif
43be6366 163#endif /* CONFIG_M5272 */
ead73183 164
cdffcf1b 165/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 166 */
cdffcf1b 167#define PKT_MAXBUF_SIZE 1522
1da177e4 168#define PKT_MINBUF_SIZE 64
cdffcf1b 169#define PKT_MAXBLR_SIZE 1536
1da177e4 170
4c09eed9
JB		 171/* FEC receive acceleration */
172#define FEC_RACC_IPDIS (1 << 1)
173#define FEC_RACC_PRODIS (1 << 2)
174#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
175
1da177e4 176/*
6b265293 177 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 178 * size bits. Other FEC hardware does not, so we need to take that into
179 * account when setting it.
180 */
562d2f8c 181#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 182 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 183#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
184#else
185#define OPT_FRAME_SIZE 0
186#endif
187
e6b043d5
BW		 188/* FEC MII MMFR bits definition */
189#define FEC_MMFR_ST (1 << 30)
190#define FEC_MMFR_OP_READ (2 << 28)
191#define FEC_MMFR_OP_WRITE (1 << 28)
192#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
193#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
194#define FEC_MMFR_TA (2 << 16)
195#define FEC_MMFR_DATA(v) (v & 0xffff)
de40ed31
NA		 196/* FEC ECR bits definition */
197#define FEC_ECR_MAGICEN (1 << 2)
198#define FEC_ECR_SLEEP (1 << 3)
1da177e4 199
c3b084c2 200#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 201
22f6b860
SH		 202/* Transmitter timeout */
203#define TX_TIMEOUT (2 * HZ)
1da177e4 204
baa70a5c
FL		 205#define FEC_PAUSE_FLAG_AUTONEG 0x1
206#define FEC_PAUSE_FLAG_ENABLE 0x2
de40ed31
NA		 207#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
208#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
209#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
baa70a5c 210
1b7bde6d
NA		 211#define COPYBREAK_DEFAULT 256
212
79f33912
NA		 213#define TSO_HEADER_SIZE 128
214/* Max number of allowed TCP segments for software TSO */
215#define FEC_MAX_TSO_SEGS 100
216#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
217
218#define IS_TSO_HEADER(txq, addr) \
219 ((addr >= txq->tso_hdrs_dma) && \
220 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
221
e163cc97
LW		 222static int mii_cnt;
223
36e24e2e 224static inline
4d494cdc
FD		 225struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
226 struct fec_enet_private *fep,
227 int queue_id)
ff43da86 228{
36e24e2e
DFB		 229 struct bufdesc *new_bd = bdp + 1;
230 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
4d494cdc
FD		 231 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
232 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
36e24e2e
DFB		 233 struct bufdesc_ex *ex_base;
234 struct bufdesc *base;
235 int ring_size;
236
4d494cdc
FD		 237 if (bdp >= txq->tx_bd_base) {
238 base = txq->tx_bd_base;
239 ring_size = txq->tx_ring_size;
240 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
36e24e2e 241 } else {
4d494cdc
FD		 242 base = rxq->rx_bd_base;
243 ring_size = rxq->rx_ring_size;
244 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
36e24e2e
DFB		 245 }
246
247 if (fep->bufdesc_ex)
248 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
249 ex_base : ex_new_bd);
ff43da86 250 else
36e24e2e
DFB		 251 return (new_bd >= (base + ring_size)) ?
252 base : new_bd;
ff43da86
FL		 253}
254
36e24e2e 255static inline
4d494cdc
FD		 256struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
257 struct fec_enet_private *fep,
258 int queue_id)
ff43da86 259{
36e24e2e
DFB		 260 struct bufdesc *new_bd = bdp - 1;
261 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
4d494cdc
FD		 262 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
263 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
36e24e2e
DFB		 264 struct bufdesc_ex *ex_base;
265 struct bufdesc *base;
266 int ring_size;
267
4d494cdc
FD		 268 if (bdp >= txq->tx_bd_base) {
269 base = txq->tx_bd_base;
270 ring_size = txq->tx_ring_size;
271 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
36e24e2e 272 } else {
4d494cdc
FD		 273 base = rxq->rx_bd_base;
274 ring_size = rxq->rx_ring_size;
275 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
36e24e2e
DFB		 276 }
277
278 if (fep->bufdesc_ex)
279 return (struct bufdesc *)((ex_new_bd < ex_base) ?
280 (ex_new_bd + ring_size) : ex_new_bd);
ff43da86 281 else
36e24e2e 282 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
ff43da86
FL		 283}
284
61a4427b
NA		 285static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
286 struct fec_enet_private *fep)
287{
288 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
289}
290
4d494cdc
FD		 291static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
292 struct fec_enet_priv_tx_q *txq)
6e909283
NA		 293{
294 int entries;
295
4d494cdc
FD		 296 entries = ((const char *)txq->dirty_tx -
297 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
6e909283 298
4d494cdc 299 return entries > 0 ? entries : entries + txq->tx_ring_size;
6e909283
NA		 300}
301
c20e599b 302static void swap_buffer(void *bufaddr, int len)
b5680e0b
SG		 303{
304 int i;
305 unsigned int *buf = bufaddr;
306
7b487d07 307 for (i = 0; i < len; i += 4, buf++)
e453789a 308 swab32s(buf);
b5680e0b
SG		 309}
310
1310b544
LW		 311static void swap_buffer2(void *dst_buf, void *src_buf, int len)
312{
313 int i;
314 unsigned int *src = src_buf;
315 unsigned int *dst = dst_buf;
316
317 for (i = 0; i < len; i += 4, src++, dst++)
318 *dst = swab32p(src);
319}
320
344756f6
RK		 321static void fec_dump(struct net_device *ndev)
322{
323 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 324 struct bufdesc *bdp;
325 struct fec_enet_priv_tx_q *txq;
326 int index = 0;
344756f6
RK		 327
328 netdev_info(ndev, "TX ring dump\n");
329 pr_info("Nr SC addr len SKB\n");
330
4d494cdc
FD		 331 txq = fep->tx_queue[0];
332 bdp = txq->tx_bd_base;
333
344756f6 334 do {
5cfa3039 335 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
344756f6 336 index,
4d494cdc
FD		 337 bdp == txq->cur_tx ? 'S' : ' ',
338 bdp == txq->dirty_tx ? 'H' : ' ',
5cfa3039
JB		 339 fec16_to_cpu(bdp->cbd_sc),
340 fec32_to_cpu(bdp->cbd_bufaddr),
341 fec16_to_cpu(bdp->cbd_datlen),
4d494cdc
FD		 342 txq->tx_skbuff[index]);
343 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
344756f6 344 index++;
4d494cdc 345 } while (bdp != txq->tx_bd_base);
344756f6
RK		 346}
347
62a02c98
FD		 348static inline bool is_ipv4_pkt(struct sk_buff *skb)
349{
350 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
351}
352
4c09eed9
JB		 353static int
354fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
355{
356 /* Only run for packets requiring a checksum. */
357 if (skb->ip_summed != CHECKSUM_PARTIAL)
358 return 0;
359
360 if (unlikely(skb_cow_head(skb, 0)))
361 return -1;
362
62a02c98
FD		 363 if (is_ipv4_pkt(skb))
364 ip_hdr(skb)->check = 0;
4c09eed9
JB		 365 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
366
367 return 0;
368}
369
c4bc44c6 370static struct bufdesc *
4d494cdc
FD		 371fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
372 struct sk_buff *skb,
373 struct net_device *ndev)
1da177e4 374{
c556167f 375 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 376 struct bufdesc *bdp = txq->cur_tx;
6e909283
NA		 377 struct bufdesc_ex *ebdp;
378 int nr_frags = skb_shinfo(skb)->nr_frags;
4d494cdc 379 unsigned short queue = skb_get_queue_mapping(skb);
6e909283
NA		 380 int frag, frag_len;
381 unsigned short status;
382 unsigned int estatus = 0;
383 skb_frag_t *this_frag;
de5fb0a0 384 unsigned int index;
6e909283 385 void *bufaddr;
d6bf3143 386 dma_addr_t addr;
6e909283 387 int i;
1da177e4 388
6e909283
NA		 389 for (frag = 0; frag < nr_frags; frag++) {
390 this_frag = &skb_shinfo(skb)->frags[frag];
4d494cdc 391 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
6e909283
NA		 392 ebdp = (struct bufdesc_ex *)bdp;
393
5cfa3039 394 status = fec16_to_cpu(bdp->cbd_sc);
6e909283
NA		 395 status &= ~BD_ENET_TX_STATS;
396 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
397 frag_len = skb_shinfo(skb)->frags[frag].size;
398
399 /* Handle the last BD specially */
400 if (frag == nr_frags - 1) {
401 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
402 if (fep->bufdesc_ex) {
403 estatus |= BD_ENET_TX_INT;
404 if (unlikely(skb_shinfo(skb)->tx_flags &
405 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
406 estatus |= BD_ENET_TX_TS;
407 }
408 }
409
410 if (fep->bufdesc_ex) {
6b7e4008 411 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 412 estatus |= FEC_TX_BD_FTYPE(queue);
6e909283
NA		 413 if (skb->ip_summed == CHECKSUM_PARTIAL)
414 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
415 ebdp->cbd_bdu = 0;
5cfa3039 416 ebdp->cbd_esc = cpu_to_fec32(estatus);
6e909283
NA		 417 }
418
419 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
420
4d494cdc 421 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
41ef84ce 422 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 423 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 424 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
425 bufaddr = txq->tx_bounce[index];
6e909283 426
6b7e4008 427 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 428 swap_buffer(bufaddr, frag_len);
429 }
430
d6bf3143
RK		 431 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
432 DMA_TO_DEVICE);
433 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 434 dev_kfree_skb_any(skb);
435 if (net_ratelimit())
436 netdev_err(ndev, "Tx DMA memory map failed\n");
437 goto dma_mapping_error;
438 }
439
5cfa3039
JB		 440 bdp->cbd_bufaddr = cpu_to_fec32(addr);
441 bdp->cbd_datlen = cpu_to_fec16(frag_len);
442 bdp->cbd_sc = cpu_to_fec16(status);
6e909283
NA		 443 }
444
c4bc44c6 445 return bdp;
6e909283 446dma_mapping_error:
4d494cdc 447 bdp = txq->cur_tx;
6e909283 448 for (i = 0; i < frag; i++) {
4d494cdc 449 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
5cfa3039
JB		 450 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
451 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
6e909283 452 }
c4bc44c6 453 return ERR_PTR(-ENOMEM);
6e909283 454}
1da177e4 455
4d494cdc
FD		 456static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
457 struct sk_buff *skb, struct net_device *ndev)
6e909283
NA		 458{
459 struct fec_enet_private *fep = netdev_priv(ndev);
6e909283
NA		 460 int nr_frags = skb_shinfo(skb)->nr_frags;
461 struct bufdesc *bdp, *last_bdp;
462 void *bufaddr;
d6bf3143 463 dma_addr_t addr;
6e909283
NA		 464 unsigned short status;
465 unsigned short buflen;
4d494cdc 466 unsigned short queue;
6e909283
NA		 467 unsigned int estatus = 0;
468 unsigned int index;
79f33912 469 int entries_free;
22f6b860 470
4d494cdc 471 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
79f33912
NA		 472 if (entries_free < MAX_SKB_FRAGS + 1) {
473 dev_kfree_skb_any(skb);
474 if (net_ratelimit())
475 netdev_err(ndev, "NOT enough BD for SG!\n");
476 return NETDEV_TX_OK;
477 }
478
4c09eed9
JB		 479 /* Protocol checksum off-load for TCP and UDP. */
480 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 481 dev_kfree_skb_any(skb);
4c09eed9
JB		 482 return NETDEV_TX_OK;
483 }
484
6e909283 485 /* Fill in a Tx ring entry */
4d494cdc 486 bdp = txq->cur_tx;
c4bc44c6 487 last_bdp = bdp;
5cfa3039 488 status = fec16_to_cpu(bdp->cbd_sc);
0e702ab3 489 status &= ~BD_ENET_TX_STATS;
1da177e4 490
22f6b860 491 /* Set buffer length and buffer pointer */
9555b31e 492 bufaddr = skb->data;
6e909283 493 buflen = skb_headlen(skb);
1da177e4 494
4d494cdc
FD		 495 queue = skb_get_queue_mapping(skb);
496 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
41ef84ce 497 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 498 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 499 memcpy(txq->tx_bounce[index], skb->data, buflen);
500 bufaddr = txq->tx_bounce[index];
1da177e4 501
6b7e4008 502 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 503 swap_buffer(bufaddr, buflen);
504 }
6aa20a22 505
d6bf3143
RK		 506 /* Push the data cache so the CPM does not get stale memory data. */
507 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
508 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 509 dev_kfree_skb_any(skb);
510 if (net_ratelimit())
511 netdev_err(ndev, "Tx DMA memory map failed\n");
512 return NETDEV_TX_OK;
513 }
1da177e4 514
6e909283 515 if (nr_frags) {
c4bc44c6
KH		 516 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
517 if (IS_ERR(last_bdp))
518 return NETDEV_TX_OK;
6e909283
NA		 519 } else {
520 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
521 if (fep->bufdesc_ex) {
522 estatus = BD_ENET_TX_INT;
523 if (unlikely(skb_shinfo(skb)->tx_flags &
524 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
525 estatus |= BD_ENET_TX_TS;
526 }
527 }
528
ff43da86
FL		 529 if (fep->bufdesc_ex) {
530
531 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 532
ff43da86 533 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 534 fep->hwts_tx_en))
6605b730 535 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 536
6b7e4008 537 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213
NA		 538 estatus |= FEC_TX_BD_FTYPE(queue);
539
6e909283
NA		 540 if (skb->ip_summed == CHECKSUM_PARTIAL)
541 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
542
543 ebdp->cbd_bdu = 0;
5cfa3039 544 ebdp->cbd_esc = cpu_to_fec32(estatus);
6605b730 545 }
03191656 546
4d494cdc 547 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
6e909283 548 /* Save skb pointer */
4d494cdc 549 txq->tx_skbuff[index] = skb;
6e909283 550
5cfa3039
JB		 551 bdp->cbd_datlen = cpu_to_fec16(buflen);
552 bdp->cbd_bufaddr = cpu_to_fec32(addr);
6e909283 553
fb8ef788
DFB		 554 /* Send it on its way. Tell FEC it's ready, interrupt when done,
555 * it's the last BD of the frame, and to put the CRC on the end.
556 */
6e909283 557 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
5cfa3039 558 bdp->cbd_sc = cpu_to_fec16(status);
fb8ef788 559
22f6b860 560 /* If this was the last BD in the ring, start at the beginning again. */
4d494cdc 561 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
1da177e4 562
7a2a8451
ED		 563 skb_tx_timestamp(skb);
564
c4bc44c6
KH		 565 /* Make sure the update to bdp and tx_skbuff are performed before
566 * cur_tx.
567 */
568 wmb();
4d494cdc 569 txq->cur_tx = bdp;
de5fb0a0 570
de5fb0a0 571 /* Trigger transmission start */
4d494cdc 572 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
1da177e4 573
6e909283 574 return 0;
1da177e4
LT		 575}
576
79f33912 577static int
4d494cdc
FD		 578fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
579 struct net_device *ndev,
580 struct bufdesc *bdp, int index, char *data,
581 int size, bool last_tcp, bool is_last)
61a4427b
NA		 582{
583 struct fec_enet_private *fep = netdev_priv(ndev);
61cd2ebb 584 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
befe8213 585 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 586 unsigned short status;
587 unsigned int estatus = 0;
d6bf3143 588 dma_addr_t addr;
61a4427b 589
5cfa3039 590 status = fec16_to_cpu(bdp->cbd_sc);
79f33912 591 status &= ~BD_ENET_TX_STATS;
61a4427b 592
79f33912 593 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912 594
41ef84ce 595 if (((unsigned long) data) & fep->tx_align ||
6b7e4008 596 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 597 memcpy(txq->tx_bounce[index], data, size);
598 data = txq->tx_bounce[index];
79f33912 599
6b7e4008 600 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 601 swap_buffer(data, size);
602 }
603
d6bf3143
RK		 604 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
605 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 606 dev_kfree_skb_any(skb);
6e909283 607 if (net_ratelimit())
79f33912 608 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 609 return NETDEV_TX_BUSY;
610 }
611
5cfa3039
JB		 612 bdp->cbd_datlen = cpu_to_fec16(size);
613 bdp->cbd_bufaddr = cpu_to_fec32(addr);
d6bf3143 614
79f33912 615 if (fep->bufdesc_ex) {
6b7e4008 616 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 617 estatus |= FEC_TX_BD_FTYPE(queue);
79f33912
NA		 618 if (skb->ip_summed == CHECKSUM_PARTIAL)
619 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
620 ebdp->cbd_bdu = 0;
5cfa3039 621 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 622 }
623
624 /* Handle the last BD specially */
625 if (last_tcp)
626 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
627 if (is_last) {
628 status |= BD_ENET_TX_INTR;
629 if (fep->bufdesc_ex)
5cfa3039 630 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
79f33912
NA		 631 }
632
5cfa3039 633 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 634
635 return 0;
636}
637
638static int
4d494cdc
FD		 639fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
640 struct sk_buff *skb, struct net_device *ndev,
641 struct bufdesc *bdp, int index)
79f33912
NA		 642{
643 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912 644 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
61cd2ebb 645 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
befe8213 646 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 647 void *bufaddr;
648 unsigned long dmabuf;
649 unsigned short status;
650 unsigned int estatus = 0;
651
5cfa3039 652 status = fec16_to_cpu(bdp->cbd_sc);
79f33912
NA		 653 status &= ~BD_ENET_TX_STATS;
654 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
655
4d494cdc
FD		 656 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
657 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
41ef84ce 658 if (((unsigned long)bufaddr) & fep->tx_align ||
6b7e4008 659 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 660 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
661 bufaddr = txq->tx_bounce[index];
79f33912 662
6b7e4008 663 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 664 swap_buffer(bufaddr, hdr_len);
665
666 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
667 hdr_len, DMA_TO_DEVICE);
668 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
669 dev_kfree_skb_any(skb);
670 if (net_ratelimit())
671 netdev_err(ndev, "Tx DMA memory map failed\n");
672 return NETDEV_TX_BUSY;
673 }
674 }
675
5cfa3039
JB		 676 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
677 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
79f33912
NA		 678
679 if (fep->bufdesc_ex) {
6b7e4008 680 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 681 estatus |= FEC_TX_BD_FTYPE(queue);
79f33912
NA		 682 if (skb->ip_summed == CHECKSUM_PARTIAL)
683 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
684 ebdp->cbd_bdu = 0;
5cfa3039 685 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 686 }
687
5cfa3039 688 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 689
690 return 0;
691}
692
4d494cdc
FD		 693static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
694 struct sk_buff *skb,
695 struct net_device *ndev)
79f33912
NA		 696{
697 struct fec_enet_private *fep = netdev_priv(ndev);
698 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
699 int total_len, data_left;
4d494cdc
FD		 700 struct bufdesc *bdp = txq->cur_tx;
701 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 702 struct tso_t tso;
703 unsigned int index = 0;
704 int ret;
705
4d494cdc 706 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
79f33912
NA		 707 dev_kfree_skb_any(skb);
708 if (net_ratelimit())
709 netdev_err(ndev, "NOT enough BD for TSO!\n");
710 return NETDEV_TX_OK;
711 }
712
713 /* Protocol checksum off-load for TCP and UDP. */
714 if (fec_enet_clear_csum(skb, ndev)) {
715 dev_kfree_skb_any(skb);
716 return NETDEV_TX_OK;
717 }
718
719 /* Initialize the TSO handler, and prepare the first payload */
720 tso_start(skb, &tso);
721
722 total_len = skb->len - hdr_len;
723 while (total_len > 0) {
724 char *hdr;
725
4d494cdc 726 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
79f33912
NA		 727 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
728 total_len -= data_left;
729
730 /* prepare packet headers: MAC + IP + TCP */
4d494cdc 731 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
79f33912 732 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
4d494cdc 733 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
79f33912
NA		 734 if (ret)
735 goto err_release;
736
737 while (data_left > 0) {
738 int size;
739
740 size = min_t(int, tso.size, data_left);
4d494cdc
FD		 741 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
742 index = fec_enet_get_bd_index(txq->tx_bd_base,
743 bdp, fep);
744 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
745 bdp, index,
746 tso.data, size,
747 size == data_left,
79f33912
NA		 748 total_len == 0);
749 if (ret)
750 goto err_release;
751
752 data_left -= size;
753 tso_build_data(skb, &tso, size);
754 }
755
4d494cdc 756 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
79f33912
NA		 757 }
758
759 /* Save skb pointer */
4d494cdc 760 txq->tx_skbuff[index] = skb;
79f33912 761
79f33912 762 skb_tx_timestamp(skb);
4d494cdc 763 txq->cur_tx = bdp;
79f33912
NA		 764
765 /* Trigger transmission start */
6b7e4008 766 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
37d6017b
FD		 767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
768 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
769 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
770 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
771 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
79f33912
NA		 772
773 return 0;
774
775err_release:
776 /* TODO: Release all used data descriptors for TSO */
777 return ret;
778}
779
780static netdev_tx_t
781fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
782{
783 struct fec_enet_private *fep = netdev_priv(ndev);
784 int entries_free;
4d494cdc
FD		 785 unsigned short queue;
786 struct fec_enet_priv_tx_q *txq;
787 struct netdev_queue *nq;
79f33912
NA		 788 int ret;
789
4d494cdc
FD		 790 queue = skb_get_queue_mapping(skb);
791 txq = fep->tx_queue[queue];
792 nq = netdev_get_tx_queue(ndev, queue);
793
79f33912 794 if (skb_is_gso(skb))
4d494cdc 795 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
79f33912 796 else
4d494cdc 797 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
6e909283
NA		 798 if (ret)
799 return ret;
61a4427b 800
4d494cdc
FD		 801 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
802 if (entries_free <= txq->tx_stop_threshold)
803 netif_tx_stop_queue(nq);
61a4427b
NA		 804
805 return NETDEV_TX_OK;
806}
807
14109a59
FL		 808/* Init RX & TX buffer descriptors
809 */
810static void fec_enet_bd_init(struct net_device *dev)
811{
812 struct fec_enet_private *fep = netdev_priv(dev);
4d494cdc
FD		 813 struct fec_enet_priv_tx_q *txq;
814 struct fec_enet_priv_rx_q *rxq;
14109a59
FL		 815 struct bufdesc *bdp;
816 unsigned int i;
59d0f746 817 unsigned int q;
14109a59 818
59d0f746
FL		 819 for (q = 0; q < fep->num_rx_queues; q++) {
820 /* Initialize the receive buffer descriptors. */
821 rxq = fep->rx_queue[q];
822 bdp = rxq->rx_bd_base;
4d494cdc 823
59d0f746 824 for (i = 0; i < rxq->rx_ring_size; i++) {
14109a59 825
59d0f746
FL		 826 /* Initialize the BD for every fragment in the page. */
827 if (bdp->cbd_bufaddr)
5cfa3039 828 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
59d0f746 829 else
5cfa3039 830 bdp->cbd_sc = cpu_to_fec16(0);
59d0f746
FL		 831 bdp = fec_enet_get_nextdesc(bdp, fep, q);
832 }
833
834 /* Set the last buffer to wrap */
835 bdp = fec_enet_get_prevdesc(bdp, fep, q);
5cfa3039 836 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746
FL		 837
838 rxq->cur_rx = rxq->rx_bd_base;
839 }
840
841 for (q = 0; q < fep->num_tx_queues; q++) {
842 /* ...and the same for transmit */
843 txq = fep->tx_queue[q];
844 bdp = txq->tx_bd_base;
845 txq->cur_tx = bdp;
846
847 for (i = 0; i < txq->tx_ring_size; i++) {
848 /* Initialize the BD for every fragment in the page. */
5cfa3039 849 bdp->cbd_sc = cpu_to_fec16(0);
59d0f746
FL		 850 if (txq->tx_skbuff[i]) {
851 dev_kfree_skb_any(txq->tx_skbuff[i]);
852 txq->tx_skbuff[i] = NULL;
853 }
5cfa3039 854 bdp->cbd_bufaddr = cpu_to_fec32(0);
59d0f746
FL		 855 bdp = fec_enet_get_nextdesc(bdp, fep, q);
856 }
857
858 /* Set the last buffer to wrap */
859 bdp = fec_enet_get_prevdesc(bdp, fep, q);
5cfa3039 860 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 861 txq->dirty_tx = bdp;
14109a59 862 }
59d0f746 863}
14109a59 864
ce99d0d3
FL		 865static void fec_enet_active_rxring(struct net_device *ndev)
866{
867 struct fec_enet_private *fep = netdev_priv(ndev);
868 int i;
869
870 for (i = 0; i < fep->num_rx_queues; i++)
871 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
872}
873
59d0f746
FL		 874static void fec_enet_enable_ring(struct net_device *ndev)
875{
876 struct fec_enet_private *fep = netdev_priv(ndev);
877 struct fec_enet_priv_tx_q *txq;
878 struct fec_enet_priv_rx_q *rxq;
879 int i;
14109a59 880
59d0f746
FL		 881 for (i = 0; i < fep->num_rx_queues; i++) {
882 rxq = fep->rx_queue[i];
883 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
d543a762 884 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
14109a59 885
59d0f746
FL		 886 /* enable DMA1/2 */
887 if (i)
888 writel(RCMR_MATCHEN | RCMR_CMP(i),
889 fep->hwp + FEC_RCMR(i));
890 }
14109a59 891
59d0f746
FL		 892 for (i = 0; i < fep->num_tx_queues; i++) {
893 txq = fep->tx_queue[i];
894 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
895
896 /* enable DMA1/2 */
897 if (i)
898 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
899 fep->hwp + FEC_DMA_CFG(i));
14109a59 900 }
59d0f746 901}
14109a59 902
59d0f746
FL		 903static void fec_enet_reset_skb(struct net_device *ndev)
904{
905 struct fec_enet_private *fep = netdev_priv(ndev);
906 struct fec_enet_priv_tx_q *txq;
907 int i, j;
908
909 for (i = 0; i < fep->num_tx_queues; i++) {
910 txq = fep->tx_queue[i];
911
912 for (j = 0; j < txq->tx_ring_size; j++) {
913 if (txq->tx_skbuff[j]) {
914 dev_kfree_skb_any(txq->tx_skbuff[j]);
915 txq->tx_skbuff[j] = NULL;
916 }
917 }
918 }
14109a59
FL		 919}
920
dbc64a8e
RK		 921/*
922 * This function is called to start or restart the FEC during a link
923 * change, transmit timeout, or to reconfigure the FEC. The network
924 * packet processing for this device must be stopped before this call.
45993653 925 */
1da177e4 926static void
ef83337d 927fec_restart(struct net_device *ndev)
1da177e4 928{
c556167f 929 struct fec_enet_private *fep = netdev_priv(ndev);
4c09eed9 930 u32 val;
cd1f402c
UKK		 931 u32 temp_mac[2];
932 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 933 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 934
106c314c
FD		 935 /* Whack a reset. We should wait for this.
936 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
937 * instead of reset MAC itself.
938 */
6b7e4008 939 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 940 writel(0, fep->hwp + FEC_ECNTRL);
941 } else {
942 writel(1, fep->hwp + FEC_ECNTRL);
943 udelay(10);
944 }
1da177e4 945
45993653
UKK		 946 /*
947 * enet-mac reset will reset mac address registers too,
948 * so need to reconfigure it.
949 */
6b7e4008 950 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
45993653 951 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
5cfa3039
JB		 952 writel((__force u32)cpu_to_be32(temp_mac[0]),
953 fep->hwp + FEC_ADDR_LOW);
954 writel((__force u32)cpu_to_be32(temp_mac[1]),
955 fep->hwp + FEC_ADDR_HIGH);
45993653 956 }
1da177e4 957
45993653 958 /* Clear any outstanding interrupt. */
e17f7fec 959 writel(0xffffffff, fep->hwp + FEC_IEVENT);
1da177e4 960
14109a59
FL		 961 fec_enet_bd_init(ndev);
962
59d0f746 963 fec_enet_enable_ring(ndev);
45993653 964
59d0f746
FL		 965 /* Reset tx SKB buffers. */
966 fec_enet_reset_skb(ndev);
97b72e43 967
45993653 968 /* Enable MII mode */
ef83337d 969 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 970 /* FD enable */
45993653
UKK		 971 writel(0x04, fep->hwp + FEC_X_CNTRL);
972 } else {
cd1f402c
UKK		 973 /* No Rcv on Xmit */
974 rcntl |= 0x02;
45993653
UKK		 975 writel(0x0, fep->hwp + FEC_X_CNTRL);
976 }
cd1f402c 977
45993653
UKK		 978 /* Set MII speed */
979 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
980
d1391930 981#if !defined(CONFIG_M5272)
18803495
GU		 982 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
983 /* set RX checksum */
984 val = readl(fep->hwp + FEC_RACC);
985 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
986 val |= FEC_RACC_OPTIONS;
987 else
988 val &= ~FEC_RACC_OPTIONS;
989 writel(val, fep->hwp + FEC_RACC);
990 }
d1391930 991#endif
4c09eed9 992
45993653
UKK		 993 /*
994 * The phy interface and speed need to get configured
995 * differently on enet-mac.
996 */
6b7e4008 997 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 998 /* Enable flow control and length check */
999 rcntl |= 0x40000000 | 0x00000020;
45993653 1000
230dec61 1001 /* RGMII, RMII or MII */
e813bb2b
MP		 1002 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1003 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1004 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1005 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
230dec61
SG		 1006 rcntl |= (1 << 6);
1007 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 1008 rcntl |= (1 << 8);
45993653 1009 else
cd1f402c 1010 rcntl &= ~(1 << 8);
45993653 1011
230dec61
SG		 1012 /* 1G, 100M or 10M */
1013 if (fep->phy_dev) {
1014 if (fep->phy_dev->speed == SPEED_1000)
1015 ecntl |= (1 << 5);
1016 else if (fep->phy_dev->speed == SPEED_100)
1017 rcntl &= ~(1 << 9);
1018 else
1019 rcntl |= (1 << 9);
1020 }
45993653
UKK		 1021 } else {
1022#ifdef FEC_MIIGSK_ENR
6b7e4008 1023 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
8d82f219 1024 u32 cfgr;
45993653
UKK		 1025 /* disable the gasket and wait */
1026 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1027 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1028 udelay(1);
1029
1030 /*
1031 * configure the gasket:
1032 * RMII, 50 MHz, no loopback, no echo
0ca1e290 1033 * MII, 25 MHz, no loopback, no echo
45993653 1034 */
8d82f219
EB		 1035 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1036 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1037 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1038 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1039 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 1040
1041 /* re-enable the gasket */
1042 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 1043 }
45993653
UKK		 1044#endif
1045 }
baa70a5c 1046
d1391930 1047#if !defined(CONFIG_M5272)
baa70a5c
FL		 1048 /* enable pause frame*/
1049 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1050 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1051 fep->phy_dev && fep->phy_dev->pause)) {
1052 rcntl |= FEC_ENET_FCE;
1053
4c09eed9 1054 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 1055 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1056 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1057 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1058 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1059
1060 /* OPD */
1061 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1062 } else {
1063 rcntl &= ~FEC_ENET_FCE;
1064 }
d1391930 1065#endif /* !defined(CONFIG_M5272) */
baa70a5c 1066
cd1f402c 1067 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 1068
84fe6182
SW		 1069 /* Setup multicast filter. */
1070 set_multicast_list(ndev);
1071#ifndef CONFIG_M5272
1072 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1073 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1074#endif
1075
6b7e4008 1076 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61
SG		 1077 /* enable ENET endian swap */
1078 ecntl |= (1 << 8);
1079 /* enable ENET store and forward mode */
1080 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1081 }
1082
ff43da86
FL		 1083 if (fep->bufdesc_ex)
1084 ecntl |= (1 << 4);
6605b730 1085
38ae92dc 1086#ifndef CONFIG_M5272
b9eef55c
JB		 1087 /* Enable the MIB statistic event counters */
1088 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1089#endif
1090
45993653 1091 /* And last, enable the transmit and receive processing */
230dec61 1092 writel(ecntl, fep->hwp + FEC_ECNTRL);
ce99d0d3 1093 fec_enet_active_rxring(ndev);
45993653 1094
ff43da86
FL		 1095 if (fep->bufdesc_ex)
1096 fec_ptp_start_cyclecounter(ndev);
1097
45993653 1098 /* Enable interrupts we wish to service */
0c5a3aef
NA		 1099 if (fep->link)
1100 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1101 else
1102 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
d851b47b
FD		 1103
1104 /* Init the interrupt coalescing */
1105 fec_enet_itr_coal_init(ndev);
1106
45993653
UKK		 1107}
1108
1109static void
1110fec_stop(struct net_device *ndev)
1111{
1112 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 1113 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
42431dc2 1114 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
de40ed31 1115 u32 val;
45993653
UKK		 1116
1117 /* We cannot expect a graceful transmit stop without link !!! */
1118 if (fep->link) {
1119 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1120 udelay(10);
1121 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1122 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1123 }
1124
106c314c
FD		 1125 /* Whack a reset. We should wait for this.
1126 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1127 * instead of reset MAC itself.
1128 */
de40ed31
NA		 1129 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1130 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1131 writel(0, fep->hwp + FEC_ECNTRL);
1132 } else {
1133 writel(1, fep->hwp + FEC_ECNTRL);
1134 udelay(10);
1135 }
1136 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
106c314c 1137 } else {
de40ed31
NA		 1138 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1139 val = readl(fep->hwp + FEC_ECNTRL);
1140 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1141 writel(val, fep->hwp + FEC_ECNTRL);
1142
1143 if (pdata && pdata->sleep_mode_enable)
1144 pdata->sleep_mode_enable(true);
106c314c 1145 }
45993653 1146 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
230dec61
SG		 1147
1148 /* We have to keep ENET enabled to have MII interrupt stay working */
de40ed31
NA		 1149 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1150 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
230dec61 1151 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1152 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1153 }
1da177e4
LT		 1154}
1155
1156
45993653
UKK		 1157static void
1158fec_timeout(struct net_device *ndev)
1159{
1160 struct fec_enet_private *fep = netdev_priv(ndev);
1161
344756f6
RK		 1162 fec_dump(ndev);
1163
45993653
UKK		 1164 ndev->stats.tx_errors++;
1165
36cdc743 1166 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1167}
1168
36cdc743 1169static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1170{
1171 struct fec_enet_private *fep =
36cdc743 1172 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1173 struct net_device *ndev = fep->netdev;
54309fa6 1174
36cdc743
RK		 1175 rtnl_lock();
1176 if (netif_device_present(ndev) || netif_running(ndev)) {
1177 napi_disable(&fep->napi);
1178 netif_tx_lock_bh(ndev);
1179 fec_restart(ndev);
1180 netif_wake_queue(ndev);
1181 netif_tx_unlock_bh(ndev);
1182 napi_enable(&fep->napi);
54309fa6 1183 }
36cdc743 1184 rtnl_unlock();
45993653
UKK		 1185}
1186
bfd4ecdd
RK		 1187static void
1188fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1189 struct skb_shared_hwtstamps *hwtstamps)
1190{
1191 unsigned long flags;
1192 u64 ns;
1193
1194 spin_lock_irqsave(&fep->tmreg_lock, flags);
1195 ns = timecounter_cyc2time(&fep->tc, ts);
1196 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1197
1198 memset(hwtstamps, 0, sizeof(*hwtstamps));
1199 hwtstamps->hwtstamp = ns_to_ktime(ns);
1200}
1201
1da177e4 1202static void
4d494cdc 1203fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1da177e4
LT		 1204{
1205 struct fec_enet_private *fep;
a2fe37b6 1206 struct bufdesc *bdp;
0e702ab3 1207 unsigned short status;
1da177e4 1208 struct sk_buff *skb;
4d494cdc
FD		 1209 struct fec_enet_priv_tx_q *txq;
1210 struct netdev_queue *nq;
de5fb0a0 1211 int index = 0;
79f33912 1212 int entries_free;
1da177e4 1213
c556167f 1214 fep = netdev_priv(ndev);
4d494cdc
FD		 1215
1216 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1217
1218 txq = fep->tx_queue[queue_id];
1219 /* get next bdp of dirty_tx */
1220 nq = netdev_get_tx_queue(ndev, queue_id);
1221 bdp = txq->dirty_tx;
1da177e4 1222
de5fb0a0 1223 /* get next bdp of dirty_tx */
4d494cdc 1224 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
de5fb0a0 1225
c4bc44c6
KH		 1226 while (bdp != READ_ONCE(txq->cur_tx)) {
1227 /* Order the load of cur_tx and cbd_sc */
1228 rmb();
5cfa3039 1229 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
c4bc44c6 1230 if (status & BD_ENET_TX_READY)
f0b3fbea
SH		 1231 break;
1232
a2fe37b6 1233 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
2b995f63 1234
a2fe37b6 1235 skb = txq->tx_skbuff[index];
2b995f63 1236 txq->tx_skbuff[index] = NULL;
5cfa3039
JB		 1237 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1238 dma_unmap_single(&fep->pdev->dev,
1239 fec32_to_cpu(bdp->cbd_bufaddr),
1240 fec16_to_cpu(bdp->cbd_datlen),
1241 DMA_TO_DEVICE);
1242 bdp->cbd_bufaddr = cpu_to_fec32(0);
a2fe37b6
FE		 1243 if (!skb) {
1244 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1245 continue;
1246 }
de5fb0a0 1247
1da177e4 1248 /* Check for errors. */
0e702ab3 1249 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1250 BD_ENET_TX_RL | BD_ENET_TX_UN |
1251 BD_ENET_TX_CSL)) {
c556167f 1252 ndev->stats.tx_errors++;
0e702ab3 1253 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1254 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1255 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1256 ndev->stats.tx_window_errors++;
0e702ab3 1257 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1258 ndev->stats.tx_aborted_errors++;
0e702ab3 1259 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1260 ndev->stats.tx_fifo_errors++;
0e702ab3 1261 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1262 ndev->stats.tx_carrier_errors++;
1da177e4 1263 } else {
c556167f 1264 ndev->stats.tx_packets++;
6e909283 1265 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1266 }
1267
ff43da86
FL		 1268 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1269 fep->bufdesc_ex) {
6605b730 1270 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1271 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1272
5cfa3039 1273 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
6605b730
FL		 1274 skb_tstamp_tx(skb, &shhwtstamps);
1275 }
ff43da86 1276
1da177e4
LT		 1277 /* Deferred means some collisions occurred during transmit,
1278 * but we eventually sent the packet OK.
1279 */
0e702ab3 1280 if (status & BD_ENET_TX_DEF)
c556167f 1281 ndev->stats.collisions++;
6aa20a22 1282
22f6b860 1283 /* Free the sk buffer associated with this last transmit */
1da177e4 1284 dev_kfree_skb_any(skb);
de5fb0a0 1285
c4bc44c6
KH		 1286 /* Make sure the update to bdp and tx_skbuff are performed
1287 * before dirty_tx
1288 */
1289 wmb();
4d494cdc 1290 txq->dirty_tx = bdp;
6aa20a22 1291
22f6b860 1292 /* Update pointer to next buffer descriptor to be transmitted */
4d494cdc 1293 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
6aa20a22 1294
22f6b860 1295 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1296 */
79f33912 1297 if (netif_queue_stopped(ndev)) {
4d494cdc
FD		 1298 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1299 if (entries_free >= txq->tx_wake_threshold)
1300 netif_tx_wake_queue(nq);
79f33912 1301 }
1da177e4 1302 }
ccea2968
RK		 1303
1304 /* ERR006538: Keep the transmitter going */
4d494cdc
FD		 1305 if (bdp != txq->cur_tx &&
1306 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1307 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1308}
1309
1310static void
1311fec_enet_tx(struct net_device *ndev)
1312{
1313 struct fec_enet_private *fep = netdev_priv(ndev);
1314 u16 queue_id;
1315 /* First process class A queue, then Class B and Best Effort queue */
1316 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1317 clear_bit(queue_id, &fep->work_tx);
1318 fec_enet_tx_queue(ndev, queue_id);
1319 }
1320 return;
1da177e4
LT		 1321}
1322
1b7bde6d
NA		 1323static int
1324fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1325{
1326 struct fec_enet_private *fep = netdev_priv(ndev);
1327 int off;
1328
1329 off = ((unsigned long)skb->data) & fep->rx_align;
1330 if (off)
1331 skb_reserve(skb, fep->rx_align + 1 - off);
1332
5cfa3039
JB		 1333 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1334 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1b7bde6d
NA		 1335 if (net_ratelimit())
1336 netdev_err(ndev, "Rx DMA memory map failed\n");
1337 return -ENOMEM;
1338 }
1339
1340 return 0;
1341}
1342
1343static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310b544 1344 struct bufdesc *bdp, u32 length, bool swap)
1b7bde6d
NA		 1345{
1346 struct fec_enet_private *fep = netdev_priv(ndev);
1347 struct sk_buff *new_skb;
1348
1349 if (length > fep->rx_copybreak)
1350 return false;
1351
1352 new_skb = netdev_alloc_skb(ndev, length);
1353 if (!new_skb)
1354 return false;
1355
5cfa3039
JB		 1356 dma_sync_single_for_cpu(&fep->pdev->dev,
1357 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1358 FEC_ENET_RX_FRSIZE - fep->rx_align,
1359 DMA_FROM_DEVICE);
1310b544
LW		 1360 if (!swap)
1361 memcpy(new_skb->data, (*skb)->data, length);
1362 else
1363 swap_buffer2(new_skb->data, (*skb)->data, length);
1b7bde6d
NA		 1364 *skb = new_skb;
1365
1366 return true;
1367}
1368
1da177e4
LT		 1369/* During a receive, the cur_rx points to the current incoming buffer.
1370 * When we update through the ring, if the next incoming buffer has
1371 * not been given to the system, we just set the empty indicator,
1372 * effectively tossing the packet.
1373 */
dc975382 1374static int
4d494cdc 1375fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1da177e4 1376{
c556167f 1377 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 1378 struct fec_enet_priv_rx_q *rxq;
2e28532f 1379 struct bufdesc *bdp;
0e702ab3 1380 unsigned short status;
1b7bde6d
NA		 1381 struct sk_buff *skb_new = NULL;
1382 struct sk_buff *skb;
1da177e4
LT		 1383 ushort pkt_len;
1384 __u8 *data;
dc975382 1385 int pkt_received = 0;
cdffcf1b
JB		 1386 struct bufdesc_ex *ebdp = NULL;
1387 bool vlan_packet_rcvd = false;
1388 u16 vlan_tag;
d842a31f 1389 int index = 0;
1b7bde6d 1390 bool is_copybreak;
6b7e4008 1391 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
6aa20a22 1392
0e702ab3
GU		 1393#ifdef CONFIG_M532x
1394 flush_cache_all();
6aa20a22 1395#endif
4d494cdc
FD		 1396 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1397 rxq = fep->rx_queue[queue_id];
1da177e4 1398
1da177e4
LT		 1399 /* First, grab all of the stats for the incoming packet.
1400 * These get messed up if we get called due to a busy condition.
1401 */
4d494cdc 1402 bdp = rxq->cur_rx;
1da177e4 1403
5cfa3039 1404 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1da177e4 1405
dc975382
FL		 1406 if (pkt_received >= budget)
1407 break;
1408 pkt_received++;
1409
22f6b860
SH		 1410 /* Since we have allocated space to hold a complete frame,
1411 * the last indicator should be set.
1412 */
1413 if ((status & BD_ENET_RX_LAST) == 0)
31b7720c 1414 netdev_err(ndev, "rcv is not +last\n");
1da177e4 1415
ed63f1dc 1416 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
db3421c1 1417
22f6b860
SH		 1418 /* Check for errors. */
1419 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1da177e4 1420 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
c556167f 1421 ndev->stats.rx_errors++;
22f6b860
SH		 1422 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1423 /* Frame too long or too short. */
c556167f 1424 ndev->stats.rx_length_errors++;
22f6b860
SH		 1425 }
1426 if (status & BD_ENET_RX_NO) /* Frame alignment */
c556167f 1427 ndev->stats.rx_frame_errors++;
22f6b860 1428 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1429 ndev->stats.rx_crc_errors++;
22f6b860 1430 if (status & BD_ENET_RX_OV) /* FIFO overrun */
c556167f 1431 ndev->stats.rx_fifo_errors++;
1da177e4 1432 }
1da177e4 1433
22f6b860
SH		 1434 /* Report late collisions as a frame error.
1435 * On this error, the BD is closed, but we don't know what we
1436 * have in the buffer. So, just drop this frame on the floor.
1437 */
1438 if (status & BD_ENET_RX_CL) {
c556167f
UKK		 1439 ndev->stats.rx_errors++;
1440 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1441 goto rx_processing_done;
1442 }
1da177e4 1443
22f6b860 1444 /* Process the incoming frame. */
c556167f 1445 ndev->stats.rx_packets++;
5cfa3039 1446 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
c556167f 1447 ndev->stats.rx_bytes += pkt_len;
1da177e4 1448
4d494cdc 1449 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1b7bde6d 1450 skb = rxq->rx_skbuff[index];
ccdc4f19 1451
1b7bde6d
NA		 1452 /* The packet length includes FCS, but we don't want to
1453 * include that when passing upstream as it messes up
1454 * bridging applications.
1455 */
1310b544
LW		 1456 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1457 need_swap);
1b7bde6d
NA		 1458 if (!is_copybreak) {
1459 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1460 if (unlikely(!skb_new)) {
1461 ndev->stats.rx_dropped++;
1462 goto rx_processing_done;
1463 }
5cfa3039
JB		 1464 dma_unmap_single(&fep->pdev->dev,
1465 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1466 FEC_ENET_RX_FRSIZE - fep->rx_align,
1467 DMA_FROM_DEVICE);
1468 }
1469
1470 prefetch(skb->data - NET_IP_ALIGN);
1471 skb_put(skb, pkt_len - 4);
1472 data = skb->data;
1310b544 1473 if (!is_copybreak && need_swap)
b5680e0b
SG		 1474 swap_buffer(data, pkt_len);
1475
cdffcf1b
JB		 1476 /* Extract the enhanced buffer descriptor */
1477 ebdp = NULL;
1478 if (fep->bufdesc_ex)
1479 ebdp = (struct bufdesc_ex *)bdp;
1480
1481 /* If this is a VLAN packet remove the VLAN Tag */
1482 vlan_packet_rcvd = false;
1483 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
5cfa3039
JB		 1484 fep->bufdesc_ex &&
1485 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
cdffcf1b
JB		 1486 /* Push and remove the vlan tag */
1487 struct vlan_hdr *vlan_header =
1488 (struct vlan_hdr *) (data + ETH_HLEN);
1489 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
cdffcf1b
JB		 1490
1491 vlan_packet_rcvd = true;
1b7bde6d 1492
af5cbc98 1493 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1b7bde6d 1494 skb_pull(skb, VLAN_HLEN);
cdffcf1b
JB		 1495 }
1496
1b7bde6d 1497 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 1498
1b7bde6d
NA		 1499 /* Get receive timestamp from the skb */
1500 if (fep->hwts_rx_en && fep->bufdesc_ex)
5cfa3039 1501 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1b7bde6d
NA		 1502 skb_hwtstamps(skb));
1503
1504 if (fep->bufdesc_ex &&
1505 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
5cfa3039 1506 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1b7bde6d
NA		 1507 /* don't check it */
1508 skb->ip_summed = CHECKSUM_UNNECESSARY;
1509 } else {
1510 skb_checksum_none_assert(skb);
4c09eed9 1511 }
1b7bde6d 1512 }
4c09eed9 1513
1b7bde6d
NA		 1514 /* Handle received VLAN packets */
1515 if (vlan_packet_rcvd)
1516 __vlan_hwaccel_put_tag(skb,
1517 htons(ETH_P_8021Q),
1518 vlan_tag);
cdffcf1b 1519
1b7bde6d
NA		 1520 napi_gro_receive(&fep->napi, skb);
1521
1522 if (is_copybreak) {
5cfa3039
JB		 1523 dma_sync_single_for_device(&fep->pdev->dev,
1524 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1525 FEC_ENET_RX_FRSIZE - fep->rx_align,
1526 DMA_FROM_DEVICE);
1527 } else {
1528 rxq->rx_skbuff[index] = skb_new;
1529 fec_enet_new_rxbdp(ndev, bdp, skb_new);
22f6b860 1530 }
f0b3fbea 1531
22f6b860
SH		 1532rx_processing_done:
1533 /* Clear the status flags for this buffer */
1534 status &= ~BD_ENET_RX_STATS;
1da177e4 1535
22f6b860
SH		 1536 /* Mark the buffer empty */
1537 status |= BD_ENET_RX_EMPTY;
5cfa3039 1538 bdp->cbd_sc = cpu_to_fec16(status);
6aa20a22 1539
ff43da86
FL		 1540 if (fep->bufdesc_ex) {
1541 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1542
5cfa3039 1543 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 1544 ebdp->cbd_prot = 0;
1545 ebdp->cbd_bdu = 0;
1546 }
6605b730 1547
22f6b860 1548 /* Update BD pointer to next entry */
4d494cdc 1549 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
36e24e2e 1550
22f6b860
SH		 1551 /* Doing this here will keep the FEC running while we process
1552 * incoming frames. On a heavily loaded network, we should be
1553 * able to keep up at the expense of system resources.
1554 */
4d494cdc 1555 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
22f6b860 1556 }
4d494cdc
FD		 1557 rxq->cur_rx = bdp;
1558 return pkt_received;
1559}
1da177e4 1560
4d494cdc
FD		 1561static int
1562fec_enet_rx(struct net_device *ndev, int budget)
1563{
1564 int pkt_received = 0;
1565 u16 queue_id;
1566 struct fec_enet_private *fep = netdev_priv(ndev);
1567
1568 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1569 clear_bit(queue_id, &fep->work_rx);
1570 pkt_received += fec_enet_rx_queue(ndev,
1571 budget - pkt_received, queue_id);
1572 }
dc975382 1573 return pkt_received;
1da177e4
LT		 1574}
1575
4d494cdc
FD		 1576static bool
1577fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1578{
1579 if (int_events == 0)
1580 return false;
1581
1582 if (int_events & FEC_ENET_RXF)
1583 fep->work_rx |= (1 << 2);
ce99d0d3
FL		 1584 if (int_events & FEC_ENET_RXF_1)
1585 fep->work_rx |= (1 << 0);
1586 if (int_events & FEC_ENET_RXF_2)
1587 fep->work_rx |= (1 << 1);
4d494cdc
FD		 1588
1589 if (int_events & FEC_ENET_TXF)
1590 fep->work_tx |= (1 << 2);
ce99d0d3
FL		 1591 if (int_events & FEC_ENET_TXF_1)
1592 fep->work_tx |= (1 << 0);
1593 if (int_events & FEC_ENET_TXF_2)
1594 fep->work_tx |= (1 << 1);
4d494cdc
FD		 1595
1596 return true;
1597}
1598
45993653
UKK		 1599static irqreturn_t
1600fec_enet_interrupt(int irq, void *dev_id)
1601{
1602 struct net_device *ndev = dev_id;
1603 struct fec_enet_private *fep = netdev_priv(ndev);
1604 uint int_events;
1605 irqreturn_t ret = IRQ_NONE;
1606
7a16807c 1607 int_events = readl(fep->hwp + FEC_IEVENT);
94191fd6 1608 writel(int_events, fep->hwp + FEC_IEVENT);
4d494cdc 1609 fec_enet_collect_events(fep, int_events);
45993653 1610
61615cd2 1611 if ((fep->work_tx || fep->work_rx) && fep->link) {
7a16807c 1612 ret = IRQ_HANDLED;
dc975382 1613
94191fd6
NA		 1614 if (napi_schedule_prep(&fep->napi)) {
1615 /* Disable the NAPI interrupts */
1616 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1617 __napi_schedule(&fep->napi);
1618 }
7a16807c 1619 }
45993653 1620
7a16807c
RK		 1621 if (int_events & FEC_ENET_MII) {
1622 ret = IRQ_HANDLED;
1623 complete(&fep->mdio_done);
1624 }
45993653 1625
81f35ffd
PZ		 1626 if (fep->ptp_clock)
1627 fec_ptp_check_pps_event(fep);
278d2404 1628
45993653
UKK		 1629 return ret;
1630}
1631
dc975382
FL		 1632static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1633{
1634 struct net_device *ndev = napi->dev;
dc975382 1635 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1636 int pkts;
1637
7a16807c 1638 pkts = fec_enet_rx(ndev, budget);
45993653 1639
de5fb0a0
FL		 1640 fec_enet_tx(ndev);
1641
dc975382
FL		 1642 if (pkts < budget) {
1643 napi_complete(napi);
1644 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1645 }
1646 return pkts;
1647}
45993653 1648
e6b043d5 1649/* ------------------------------------------------------------------------- */
0c7768a0 1650static void fec_get_mac(struct net_device *ndev)
1da177e4 1651{
c556167f 1652 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1653 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1654 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1655
49da97dc
SG		 1656 /*
1657 * try to get mac address in following order:
1658 *
1659 * 1) module parameter via kernel command line in form
1660 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1661 */
1662 iap = macaddr;
1663
ca2cc333
SG		 1664 /*
1665 * 2) from device tree data
1666 */
1667 if (!is_valid_ether_addr(iap)) {
1668 struct device_node *np = fep->pdev->dev.of_node;
1669 if (np) {
1670 const char *mac = of_get_mac_address(np);
1671 if (mac)
1672 iap = (unsigned char *) mac;
1673 }
1674 }
ca2cc333 1675
49da97dc 1676 /*
ca2cc333 1677 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1678 */
1679 if (!is_valid_ether_addr(iap)) {
1680#ifdef CONFIG_M5272
1681 if (FEC_FLASHMAC)
1682 iap = (unsigned char *)FEC_FLASHMAC;
1683#else
1684 if (pdata)
589efdc7 1685 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1686#endif
1687 }
1688
1689 /*
ca2cc333 1690 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1691 */
1692 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1693 *((__be32 *) &tmpaddr[0]) =
1694 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1695 *((__be16 *) &tmpaddr[4]) =
1696 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1697 iap = &tmpaddr[0];
1da177e4
LT		 1698 }
1699
ff5b2fab
LS		 1700 /*
1701 * 5) random mac address
1702 */
1703 if (!is_valid_ether_addr(iap)) {
1704 /* Report it and use a random ethernet address instead */
1705 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1706 eth_hw_addr_random(ndev);
1707 netdev_info(ndev, "Using random MAC address: %pM\n",
1708 ndev->dev_addr);
1709 return;
1710 }
1711
c556167f 1712 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1713
49da97dc
SG		 1714 /* Adjust MAC if using macaddr */
1715 if (iap == macaddr)
43af940c 1716 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1717}
1718
e6b043d5 1719/* ------------------------------------------------------------------------- */
1da177e4 1720
e6b043d5
BW		 1721/*
1722 * Phy section
1723 */
c556167f 1724static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1725{
c556167f 1726 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1727 struct phy_device *phy_dev = fep->phy_dev;
e6b043d5 1728 int status_change = 0;
1da177e4 1729
e6b043d5
BW		 1730 /* Prevent a state halted on mii error */
1731 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1732 phy_dev->state = PHY_RESUMING;
54309fa6 1733 return;
e6b043d5 1734 }
1da177e4 1735
8ce5624f
RK		 1736 /*
1737 * If the netdev is down, or is going down, we're not interested
1738 * in link state events, so just mark our idea of the link as down
1739 * and ignore the event.
1740 */
1741 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1742 fep->link = 0;
1743 } else if (phy_dev->link) {
d97e7497 1744 if (!fep->link) {
6ea0722f 1745 fep->link = phy_dev->link;
e6b043d5
BW		 1746 status_change = 1;
1747 }
1da177e4 1748
ef83337d
RK		 1749 if (fep->full_duplex != phy_dev->duplex) {
1750 fep->full_duplex = phy_dev->duplex;
d97e7497 1751 status_change = 1;
ef83337d 1752 }
d97e7497
LS		 1753
1754 if (phy_dev->speed != fep->speed) {
1755 fep->speed = phy_dev->speed;
1756 status_change = 1;
1757 }
1758
1759 /* if any of the above changed restart the FEC */
dbc64a8e 1760 if (status_change) {
dbc64a8e 1761 napi_disable(&fep->napi);
dbc64a8e 1762 netif_tx_lock_bh(ndev);
ef83337d 1763 fec_restart(ndev);
dbc64a8e 1764 netif_wake_queue(ndev);
6af42d42 1765 netif_tx_unlock_bh(ndev);
dbc64a8e 1766 napi_enable(&fep->napi);
dbc64a8e 1767 }
d97e7497
LS		 1768 } else {
1769 if (fep->link) {
f208ce10
RK		 1770 napi_disable(&fep->napi);
1771 netif_tx_lock_bh(ndev);
c556167f 1772 fec_stop(ndev);
f208ce10
RK		 1773 netif_tx_unlock_bh(ndev);
1774 napi_enable(&fep->napi);
8d7ed0f0 1775 fep->link = phy_dev->link;
d97e7497
LS		 1776 status_change = 1;
1777 }
1da177e4 1778 }
6aa20a22 1779
e6b043d5
BW		 1780 if (status_change)
1781 phy_print_status(phy_dev);
1782}
1da177e4 1783
e6b043d5 1784static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1785{
e6b043d5 1786 struct fec_enet_private *fep = bus->priv;
8fff755e 1787 struct device *dev = &fep->pdev->dev;
97b72e43 1788 unsigned long time_left;
8fff755e
AL		 1789 int ret = 0;
1790
1791 ret = pm_runtime_get_sync(dev);
b0c6ce24 1792 if (ret < 0)
8fff755e 1793 return ret;
1da177e4 1794
e6b043d5 1795 fep->mii_timeout = 0;
aac27c7a 1796 reinit_completion(&fep->mdio_done);
e6b043d5
BW		 1797
1798 /* start a read op */
1799 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1800 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1801 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1802
1803 /* wait for end of transfer */
97b72e43
BS		 1804 time_left = wait_for_completion_timeout(&fep->mdio_done,
1805 usecs_to_jiffies(FEC_MII_TIMEOUT));
1806 if (time_left == 0) {
1807 fep->mii_timeout = 1;
31b7720c 1808 netdev_err(fep->netdev, "MDIO read timeout\n");
8fff755e
AL		 1809 ret = -ETIMEDOUT;
1810 goto out;
1da177e4 1811 }
1da177e4 1812
8fff755e
AL		 1813 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1814
1815out:
1816 pm_runtime_mark_last_busy(dev);
1817 pm_runtime_put_autosuspend(dev);
1818
1819 return ret;
7dd6a2aa 1820}
6aa20a22 1821
e6b043d5
BW		 1822static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1823 u16 value)
1da177e4 1824{
e6b043d5 1825 struct fec_enet_private *fep = bus->priv;
8fff755e 1826 struct device *dev = &fep->pdev->dev;
97b72e43 1827 unsigned long time_left;
42ea4457 1828 int ret;
8fff755e
AL		 1829
1830 ret = pm_runtime_get_sync(dev);
b0c6ce24 1831 if (ret < 0)
8fff755e 1832 return ret;
42ea4457
MS		 1833 else
1834 ret = 0;
1da177e4 1835
e6b043d5 1836 fep->mii_timeout = 0;
aac27c7a 1837 reinit_completion(&fep->mdio_done);
1da177e4 1838
862f0982
SG		 1839 /* start a write op */
1840 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1841 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1842 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1843 fep->hwp + FEC_MII_DATA);
1844
1845 /* wait for end of transfer */
97b72e43
BS		 1846 time_left = wait_for_completion_timeout(&fep->mdio_done,
1847 usecs_to_jiffies(FEC_MII_TIMEOUT));
1848 if (time_left == 0) {
1849 fep->mii_timeout = 1;
31b7720c 1850 netdev_err(fep->netdev, "MDIO write timeout\n");
8fff755e 1851 ret = -ETIMEDOUT;
e6b043d5 1852 }
1da177e4 1853
8fff755e
AL		 1854 pm_runtime_mark_last_busy(dev);
1855 pm_runtime_put_autosuspend(dev);
1856
1857 return ret;
e6b043d5 1858}
1da177e4 1859
e8fcfcd5
NA		 1860static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1861{
1862 struct fec_enet_private *fep = netdev_priv(ndev);
1863 int ret;
1864
1865 if (enable) {
1866 ret = clk_prepare_enable(fep->clk_ahb);
1867 if (ret)
1868 return ret;
e8fcfcd5
NA		 1869 if (fep->clk_enet_out) {
1870 ret = clk_prepare_enable(fep->clk_enet_out);
1871 if (ret)
1872 goto failed_clk_enet_out;
1873 }
1874 if (fep->clk_ptp) {
91c0d987 1875 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1876 ret = clk_prepare_enable(fep->clk_ptp);
91c0d987
NA		 1877 if (ret) {
1878 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1879 goto failed_clk_ptp;
91c0d987
NA		 1880 } else {
1881 fep->ptp_clk_on = true;
1882 }
1883 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1884 }
9b5330ed
FD		 1885 if (fep->clk_ref) {
1886 ret = clk_prepare_enable(fep->clk_ref);
1887 if (ret)
1888 goto failed_clk_ref;
1889 }
e8fcfcd5
NA		 1890 } else {
1891 clk_disable_unprepare(fep->clk_ahb);
e8fcfcd5
NA		 1892 if (fep->clk_enet_out)
1893 clk_disable_unprepare(fep->clk_enet_out);
91c0d987
NA		 1894 if (fep->clk_ptp) {
1895 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1896 clk_disable_unprepare(fep->clk_ptp);
91c0d987
NA		 1897 fep->ptp_clk_on = false;
1898 mutex_unlock(&fep->ptp_clk_mutex);
1899 }
9b5330ed
FD		 1900 if (fep->clk_ref)
1901 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1902 }
1903
1904 return 0;
9b5330ed
FD		 1905
1906failed_clk_ref:
1907 if (fep->clk_ref)
1908 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1909failed_clk_ptp:
1910 if (fep->clk_enet_out)
1911 clk_disable_unprepare(fep->clk_enet_out);
1912failed_clk_enet_out:
e8fcfcd5
NA		 1913 clk_disable_unprepare(fep->clk_ahb);
1914
1915 return ret;
1916}
1917
c556167f 1918static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1919{
c556167f 1920 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1921 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1922 char mdio_bus_id[MII_BUS_ID_SIZE];
1923 char phy_name[MII_BUS_ID_SIZE + 3];
1924 int phy_id;
43af940c 1925 int dev_id = fep->dev_id;
562d2f8c 1926
418bd0d4
BW		 1927 fep->phy_dev = NULL;
1928
407066f8
UKK		 1929 if (fep->phy_node) {
1930 phy_dev = of_phy_connect(ndev, fep->phy_node,
1931 &fec_enet_adjust_link, 0,
1932 fep->phy_interface);
213a9922
NA		 1933 if (!phy_dev)
1934 return -ENODEV;
407066f8
UKK		 1935 } else {
1936 /* check for attached phy */
1937 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
7f854420 1938 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
407066f8
UKK		 1939 continue;
1940 if (dev_id--)
1941 continue;
949bdd20 1942 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
407066f8
UKK		 1943 break;
1944 }
1da177e4 1945
407066f8
UKK		 1946 if (phy_id >= PHY_MAX_ADDR) {
1947 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
949bdd20 1948 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
407066f8
UKK		 1949 phy_id = 0;
1950 }
1951
1952 snprintf(phy_name, sizeof(phy_name),
1953 PHY_ID_FMT, mdio_bus_id, phy_id);
1954 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1955 fep->phy_interface);
6fcc040f
GU		 1956 }
1957
6fcc040f 1958 if (IS_ERR(phy_dev)) {
31b7720c 1959 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1960 return PTR_ERR(phy_dev);
e6b043d5 1961 }
1da177e4 1962
e6b043d5 1963 /* mask with MAC supported features */
6b7e4008 1964 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
230dec61 1965 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1966 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1967#if !defined(CONFIG_M5272)
baa70a5c 1968 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1969#endif
baa70a5c 1970 }
230dec61
SG		 1971 else
1972 phy_dev->supported &= PHY_BASIC_FEATURES;
1973
e6b043d5 1974 phy_dev->advertising = phy_dev->supported;
1da177e4 1975
e6b043d5
BW		 1976 fep->phy_dev = phy_dev;
1977 fep->link = 0;
1978 fep->full_duplex = 0;
1da177e4 1979
2220943a 1980 phy_attached_info(phy_dev);
418bd0d4 1981
e6b043d5 1982 return 0;
1da177e4
LT		 1983}
1984
e6b043d5 1985static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1986{
b5680e0b 1987 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1988 struct net_device *ndev = platform_get_drvdata(pdev);
1989 struct fec_enet_private *fep = netdev_priv(ndev);
407066f8 1990 struct device_node *node;
e7f4dc35 1991 int err = -ENXIO;
63c60732 1992 u32 mii_speed, holdtime;
6b265293 1993
b5680e0b 1994 /*
3d125f9c 1995 * The i.MX28 dual fec interfaces are not equal.
b5680e0b
SG		 1996 * Here are the differences:
1997 *
1998 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1999 * - fec0 acts as the 1588 time master while fec1 is slave
2000 * - external phys can only be configured by fec0
2001 *
2002 * That is to say fec1 can not work independently. It only works
2003 * when fec0 is working. The reason behind this design is that the
2004 * second interface is added primarily for Switch mode.
2005 *
2006 * Because of the last point above, both phys are attached on fec0
2007 * mdio interface in board design, and need to be configured by
2008 * fec0 mii_bus.
2009 */
3d125f9c 2010 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
b5680e0b 2011 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 2012 if (mii_cnt && fec0_mii_bus) {
2013 fep->mii_bus = fec0_mii_bus;
2014 mii_cnt++;
2015 return 0;
2016 }
2017 return -ENOENT;
b5680e0b
SG		 2018 }
2019
e6b043d5 2020 fep->mii_timeout = 0;
1da177e4 2021
e6b043d5
BW		 2022 /*
2023 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 2024 *
2025 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2026 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2027 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2028 * document.
e6b043d5 2029 */
63c60732 2030 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
6b7e4008 2031 if (fep->quirks & FEC_QUIRK_ENET_MAC)
63c60732
UKK		 2032 mii_speed--;
2033 if (mii_speed > 63) {
2034 dev_err(&pdev->dev,
2035 "fec clock (%lu) to fast to get right mii speed\n",
2036 clk_get_rate(fep->clk_ipg));
2037 err = -EINVAL;
2038 goto err_out;
2039 }
2040
2041 /*
2042 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2043 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2044 * versions are RAZ there, so just ignore the difference and write the
2045 * register always.
2046 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2047 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2048 * output.
2049 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2050 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2051 * holdtime cannot result in a value greater than 3.
2052 */
2053 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2054
2055 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2056
e6b043d5 2057 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 2058
e6b043d5
BW		 2059 fep->mii_bus = mdiobus_alloc();
2060 if (fep->mii_bus == NULL) {
2061 err = -ENOMEM;
2062 goto err_out;
1da177e4
LT		 2063 }
2064
e6b043d5
BW		 2065 fep->mii_bus->name = "fec_enet_mii_bus";
2066 fep->mii_bus->read = fec_enet_mdio_read;
2067 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 2068 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2069 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 2070 fep->mii_bus->priv = fep;
2071 fep->mii_bus->parent = &pdev->dev;
2072
407066f8
UKK		 2073 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2074 if (node) {
2075 err = of_mdiobus_register(fep->mii_bus, node);
2076 of_node_put(node);
2077 } else {
2078 err = mdiobus_register(fep->mii_bus);
2079 }
2080
2081 if (err)
e7f4dc35 2082 goto err_out_free_mdiobus;
1da177e4 2083
e163cc97
LW		 2084 mii_cnt++;
2085
b5680e0b 2086 /* save fec0 mii_bus */
3d125f9c 2087 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
b5680e0b
SG		 2088 fec0_mii_bus = fep->mii_bus;
2089
e6b043d5 2090 return 0;
1da177e4 2091
e6b043d5
BW		 2092err_out_free_mdiobus:
2093 mdiobus_free(fep->mii_bus);
2094err_out:
2095 return err;
1da177e4
LT		 2096}
2097
e6b043d5 2098static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 2099{
e163cc97
LW		 2100 if (--mii_cnt == 0) {
2101 mdiobus_unregister(fep->mii_bus);
e163cc97
LW		 2102 mdiobus_free(fep->mii_bus);
2103 }
1da177e4
LT		 2104}
2105
c556167f 2106static int fec_enet_get_settings(struct net_device *ndev,
e6b043d5 2107 struct ethtool_cmd *cmd)
1da177e4 2108{
c556167f 2109 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2110 struct phy_device *phydev = fep->phy_dev;
1da177e4 2111
e6b043d5
BW		 2112 if (!phydev)
2113 return -ENODEV;
1da177e4 2114
e6b043d5 2115 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 2116}
2117
c556167f 2118static int fec_enet_set_settings(struct net_device *ndev,
e6b043d5 2119 struct ethtool_cmd *cmd)
1da177e4 2120{
c556167f 2121 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2122 struct phy_device *phydev = fep->phy_dev;
1da177e4 2123
e6b043d5
BW		 2124 if (!phydev)
2125 return -ENODEV;
1da177e4 2126
e6b043d5 2127 return phy_ethtool_sset(phydev, cmd);
1da177e4
LT		 2128}
2129
c556167f 2130static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 2131 struct ethtool_drvinfo *info)
1da177e4 2132{
c556167f 2133 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 2134
7826d43f
JP		 2135 strlcpy(info->driver, fep->pdev->dev.driver->name,
2136 sizeof(info->driver));
2137 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2138 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 2139}
2140
db65f35f
PR		 2141static int fec_enet_get_regs_len(struct net_device *ndev)
2142{
2143 struct fec_enet_private *fep = netdev_priv(ndev);
2144 struct resource *r;
2145 int s = 0;
2146
2147 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2148 if (r)
2149 s = resource_size(r);
2150
2151 return s;
2152}
2153
2154/* List of registers that can be safety be read to dump them with ethtool */
2155#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2156 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
2157 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
2158static u32 fec_enet_register_offset[] = {
2159 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2160 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2161 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2162 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2163 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2164 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2165 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2166 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2167 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2168 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2169 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2170 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2171 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2172 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2173 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2174 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2175 RMON_T_P_GTE2048, RMON_T_OCTETS,
2176 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2177 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2178 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2179 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2180 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2181 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2182 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2183 RMON_R_P_GTE2048, RMON_R_OCTETS,
2184 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2185 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2186};
2187#else
2188static u32 fec_enet_register_offset[] = {
2189 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2190 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2191 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2192 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2193 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2194 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2195 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2196 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2197 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2198};
2199#endif
2200
2201static void fec_enet_get_regs(struct net_device *ndev,
2202 struct ethtool_regs *regs, void *regbuf)
2203{
2204 struct fec_enet_private *fep = netdev_priv(ndev);
2205 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2206 u32 *buf = (u32 *)regbuf;
2207 u32 i, off;
2208
2209 memset(buf, 0, regs->len);
2210
2211 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2212 off = fec_enet_register_offset[i] / 4;
2213 buf[off] = readl(&theregs[off]);
2214 }
2215}
2216
5ebae489
FL		 2217static int fec_enet_get_ts_info(struct net_device *ndev,
2218 struct ethtool_ts_info *info)
2219{
2220 struct fec_enet_private *fep = netdev_priv(ndev);
2221
2222 if (fep->bufdesc_ex) {
2223
2224 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2225 SOF_TIMESTAMPING_RX_SOFTWARE |
2226 SOF_TIMESTAMPING_SOFTWARE |
2227 SOF_TIMESTAMPING_TX_HARDWARE |
2228 SOF_TIMESTAMPING_RX_HARDWARE |
2229 SOF_TIMESTAMPING_RAW_HARDWARE;
2230 if (fep->ptp_clock)
2231 info->phc_index = ptp_clock_index(fep->ptp_clock);
2232 else
2233 info->phc_index = -1;
2234
2235 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2236 (1 << HWTSTAMP_TX_ON);
2237
2238 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2239 (1 << HWTSTAMP_FILTER_ALL);
2240 return 0;
2241 } else {
2242 return ethtool_op_get_ts_info(ndev, info);
2243 }
2244}
2245
d1391930
GR		 2246#if !defined(CONFIG_M5272)
2247
baa70a5c
FL		 2248static void fec_enet_get_pauseparam(struct net_device *ndev,
2249 struct ethtool_pauseparam *pause)
2250{
2251 struct fec_enet_private *fep = netdev_priv(ndev);
2252
2253 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2254 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2255 pause->rx_pause = pause->tx_pause;
2256}
2257
2258static int fec_enet_set_pauseparam(struct net_device *ndev,
2259 struct ethtool_pauseparam *pause)
2260{
2261 struct fec_enet_private *fep = netdev_priv(ndev);
2262
0b146ca8
RK		 2263 if (!fep->phy_dev)
2264 return -ENODEV;
2265
baa70a5c
FL		 2266 if (pause->tx_pause != pause->rx_pause) {
2267 netdev_info(ndev,
2268 "hardware only support enable/disable both tx and rx");
2269 return -EINVAL;
2270 }
2271
2272 fep->pause_flag = 0;
2273
2274 /* tx pause must be same as rx pause */
2275 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2276 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2277
2278 if (pause->rx_pause || pause->autoneg) {
2279 fep->phy_dev->supported |= ADVERTISED_Pause;
2280 fep->phy_dev->advertising |= ADVERTISED_Pause;
2281 } else {
2282 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2283 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2284 }
2285
2286 if (pause->autoneg) {
2287 if (netif_running(ndev))
2288 fec_stop(ndev);
2289 phy_start_aneg(fep->phy_dev);
2290 }
dbc64a8e 2291 if (netif_running(ndev)) {
dbc64a8e 2292 napi_disable(&fep->napi);
dbc64a8e 2293 netif_tx_lock_bh(ndev);
ef83337d 2294 fec_restart(ndev);
dbc64a8e 2295 netif_wake_queue(ndev);
6af42d42 2296 netif_tx_unlock_bh(ndev);
dbc64a8e 2297 napi_enable(&fep->napi);
dbc64a8e 2298 }
baa70a5c
FL		 2299
2300 return 0;
2301}
2302
38ae92dc
CH		 2303static const struct fec_stat {
2304 char name[ETH_GSTRING_LEN];
2305 u16 offset;
2306} fec_stats[] = {
2307 /* RMON TX */
2308 { "tx_dropped", RMON_T_DROP },
2309 { "tx_packets", RMON_T_PACKETS },
2310 { "tx_broadcast", RMON_T_BC_PKT },
2311 { "tx_multicast", RMON_T_MC_PKT },
2312 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2313 { "tx_undersize", RMON_T_UNDERSIZE },
2314 { "tx_oversize", RMON_T_OVERSIZE },
2315 { "tx_fragment", RMON_T_FRAG },
2316 { "tx_jabber", RMON_T_JAB },
2317 { "tx_collision", RMON_T_COL },
2318 { "tx_64byte", RMON_T_P64 },
2319 { "tx_65to127byte", RMON_T_P65TO127 },
2320 { "tx_128to255byte", RMON_T_P128TO255 },
2321 { "tx_256to511byte", RMON_T_P256TO511 },
2322 { "tx_512to1023byte", RMON_T_P512TO1023 },
2323 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2324 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2325 { "tx_octets", RMON_T_OCTETS },
2326
2327 /* IEEE TX */
2328 { "IEEE_tx_drop", IEEE_T_DROP },
2329 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2330 { "IEEE_tx_1col", IEEE_T_1COL },
2331 { "IEEE_tx_mcol", IEEE_T_MCOL },
2332 { "IEEE_tx_def", IEEE_T_DEF },
2333 { "IEEE_tx_lcol", IEEE_T_LCOL },
2334 { "IEEE_tx_excol", IEEE_T_EXCOL },
2335 { "IEEE_tx_macerr", IEEE_T_MACERR },
2336 { "IEEE_tx_cserr", IEEE_T_CSERR },
2337 { "IEEE_tx_sqe", IEEE_T_SQE },
2338 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2339 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2340
2341 /* RMON RX */
2342 { "rx_packets", RMON_R_PACKETS },
2343 { "rx_broadcast", RMON_R_BC_PKT },
2344 { "rx_multicast", RMON_R_MC_PKT },
2345 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2346 { "rx_undersize", RMON_R_UNDERSIZE },
2347 { "rx_oversize", RMON_R_OVERSIZE },
2348 { "rx_fragment", RMON_R_FRAG },
2349 { "rx_jabber", RMON_R_JAB },
2350 { "rx_64byte", RMON_R_P64 },
2351 { "rx_65to127byte", RMON_R_P65TO127 },
2352 { "rx_128to255byte", RMON_R_P128TO255 },
2353 { "rx_256to511byte", RMON_R_P256TO511 },
2354 { "rx_512to1023byte", RMON_R_P512TO1023 },
2355 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2356 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2357 { "rx_octets", RMON_R_OCTETS },
2358
2359 /* IEEE RX */
2360 { "IEEE_rx_drop", IEEE_R_DROP },
2361 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2362 { "IEEE_rx_crc", IEEE_R_CRC },
2363 { "IEEE_rx_align", IEEE_R_ALIGN },
2364 { "IEEE_rx_macerr", IEEE_R_MACERR },
2365 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2366 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2367};
2368
2369static void fec_enet_get_ethtool_stats(struct net_device *dev,
2370 struct ethtool_stats *stats, u64 *data)
2371{
2372 struct fec_enet_private *fep = netdev_priv(dev);
2373 int i;
2374
2375 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2376 data[i] = readl(fep->hwp + fec_stats[i].offset);
2377}
2378
2379static void fec_enet_get_strings(struct net_device *netdev,
2380 u32 stringset, u8 *data)
2381{
2382 int i;
2383 switch (stringset) {
2384 case ETH_SS_STATS:
2385 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2386 memcpy(data + i * ETH_GSTRING_LEN,
2387 fec_stats[i].name, ETH_GSTRING_LEN);
2388 break;
2389 }
2390}
2391
2392static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2393{
2394 switch (sset) {
2395 case ETH_SS_STATS:
2396 return ARRAY_SIZE(fec_stats);
2397 default:
2398 return -EOPNOTSUPP;
2399 }
2400}
d1391930 2401#endif /* !defined(CONFIG_M5272) */
38ae92dc 2402
32bc9b46
CH		 2403static int fec_enet_nway_reset(struct net_device *dev)
2404{
2405 struct fec_enet_private *fep = netdev_priv(dev);
2406 struct phy_device *phydev = fep->phy_dev;
2407
2408 if (!phydev)
2409 return -ENODEV;
2410
2411 return genphy_restart_aneg(phydev);
2412}
2413
d851b47b
FD		 2414/* ITR clock source is enet system clock (clk_ahb).
2415 * TCTT unit is cycle_ns * 64 cycle
2416 * So, the ICTT value = X us / (cycle_ns * 64)
2417 */
2418static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2419{
2420 struct fec_enet_private *fep = netdev_priv(ndev);
2421
2422 return us * (fep->itr_clk_rate / 64000) / 1000;
2423}
2424
2425/* Set threshold for interrupt coalescing */
2426static void fec_enet_itr_coal_set(struct net_device *ndev)
2427{
2428 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2429 int rx_itr, tx_itr;
2430
6b7e4008 2431 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2432 return;
2433
2434 /* Must be greater than zero to avoid unpredictable behavior */
2435 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2436 !fep->tx_time_itr || !fep->tx_pkts_itr)
2437 return;
2438
2439 /* Select enet system clock as Interrupt Coalescing
2440 * timer Clock Source
2441 */
2442 rx_itr = FEC_ITR_CLK_SEL;
2443 tx_itr = FEC_ITR_CLK_SEL;
2444
2445 /* set ICFT and ICTT */
2446 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2447 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2448 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2449 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2450
2451 rx_itr |= FEC_ITR_EN;
2452 tx_itr |= FEC_ITR_EN;
2453
2454 writel(tx_itr, fep->hwp + FEC_TXIC0);
2455 writel(rx_itr, fep->hwp + FEC_RXIC0);
2456 writel(tx_itr, fep->hwp + FEC_TXIC1);
2457 writel(rx_itr, fep->hwp + FEC_RXIC1);
2458 writel(tx_itr, fep->hwp + FEC_TXIC2);
2459 writel(rx_itr, fep->hwp + FEC_RXIC2);
2460}
2461
2462static int
2463fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2464{
2465 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b 2466
6b7e4008 2467 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2468 return -EOPNOTSUPP;
2469
2470 ec->rx_coalesce_usecs = fep->rx_time_itr;
2471 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2472
2473 ec->tx_coalesce_usecs = fep->tx_time_itr;
2474 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2475
2476 return 0;
2477}
2478
2479static int
2480fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2481{
2482 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2483 unsigned int cycle;
2484
6b7e4008 2485 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2486 return -EOPNOTSUPP;
2487
2488 if (ec->rx_max_coalesced_frames > 255) {
2489 pr_err("Rx coalesced frames exceed hardware limiation");
2490 return -EINVAL;
2491 }
2492
2493 if (ec->tx_max_coalesced_frames > 255) {
2494 pr_err("Tx coalesced frame exceed hardware limiation");
2495 return -EINVAL;
2496 }
2497
2498 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2499 if (cycle > 0xFFFF) {
2500 pr_err("Rx coalesed usec exceeed hardware limiation");
2501 return -EINVAL;
2502 }
2503
2504 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2505 if (cycle > 0xFFFF) {
2506 pr_err("Rx coalesed usec exceeed hardware limiation");
2507 return -EINVAL;
2508 }
2509
2510 fep->rx_time_itr = ec->rx_coalesce_usecs;
2511 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2512
2513 fep->tx_time_itr = ec->tx_coalesce_usecs;
2514 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2515
2516 fec_enet_itr_coal_set(ndev);
2517
2518 return 0;
2519}
2520
2521static void fec_enet_itr_coal_init(struct net_device *ndev)
2522{
2523 struct ethtool_coalesce ec;
2524
2525 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2526 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2527
2528 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2529 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2530
2531 fec_enet_set_coalesce(ndev, &ec);
2532}
2533
1b7bde6d
NA		 2534static int fec_enet_get_tunable(struct net_device *netdev,
2535 const struct ethtool_tunable *tuna,
2536 void *data)
2537{
2538 struct fec_enet_private *fep = netdev_priv(netdev);
2539 int ret = 0;
2540
2541 switch (tuna->id) {
2542 case ETHTOOL_RX_COPYBREAK:
2543 *(u32 *)data = fep->rx_copybreak;
2544 break;
2545 default:
2546 ret = -EINVAL;
2547 break;
2548 }
2549
2550 return ret;
2551}
2552
2553static int fec_enet_set_tunable(struct net_device *netdev,
2554 const struct ethtool_tunable *tuna,
2555 const void *data)
2556{
2557 struct fec_enet_private *fep = netdev_priv(netdev);
2558 int ret = 0;
2559
2560 switch (tuna->id) {
2561 case ETHTOOL_RX_COPYBREAK:
2562 fep->rx_copybreak = *(u32 *)data;
2563 break;
2564 default:
2565 ret = -EINVAL;
2566 break;
2567 }
2568
2569 return ret;
2570}
2571
de40ed31
NA		 2572static void
2573fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2574{
2575 struct fec_enet_private *fep = netdev_priv(ndev);
2576
2577 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2578 wol->supported = WAKE_MAGIC;
2579 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2580 } else {
2581 wol->supported = wol->wolopts = 0;
2582 }
2583}
2584
2585static int
2586fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2587{
2588 struct fec_enet_private *fep = netdev_priv(ndev);
2589
2590 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2591 return -EINVAL;
2592
2593 if (wol->wolopts & ~WAKE_MAGIC)
2594 return -EINVAL;
2595
2596 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2597 if (device_may_wakeup(&ndev->dev)) {
2598 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2599 if (fep->irq[0] > 0)
2600 enable_irq_wake(fep->irq[0]);
2601 } else {
2602 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2603 if (fep->irq[0] > 0)
2604 disable_irq_wake(fep->irq[0]);
2605 }
2606
2607 return 0;
2608}
2609
9b07be4b 2610static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5
BW		 2611 .get_settings = fec_enet_get_settings,
2612 .set_settings = fec_enet_set_settings,
2613 .get_drvinfo = fec_enet_get_drvinfo,
db65f35f
PR		 2614 .get_regs_len = fec_enet_get_regs_len,
2615 .get_regs = fec_enet_get_regs,
32bc9b46 2616 .nway_reset = fec_enet_nway_reset,
c1d7c48f 2617 .get_link = ethtool_op_get_link,
d851b47b
FD		 2618 .get_coalesce = fec_enet_get_coalesce,
2619 .set_coalesce = fec_enet_set_coalesce,
38ae92dc 2620#ifndef CONFIG_M5272
c1d7c48f
RK		 2621 .get_pauseparam = fec_enet_get_pauseparam,
2622 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2623 .get_strings = fec_enet_get_strings,
c1d7c48f 2624 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2625 .get_sset_count = fec_enet_get_sset_count,
2626#endif
c1d7c48f 2627 .get_ts_info = fec_enet_get_ts_info,
1b7bde6d
NA		 2628 .get_tunable = fec_enet_get_tunable,
2629 .set_tunable = fec_enet_set_tunable,
de40ed31
NA		 2630 .get_wol = fec_enet_get_wol,
2631 .set_wol = fec_enet_set_wol,
e6b043d5 2632};
1da177e4 2633
c556167f 2634static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2635{
c556167f 2636 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2637 struct phy_device *phydev = fep->phy_dev;
1da177e4 2638
c556167f 2639 if (!netif_running(ndev))
e6b043d5 2640 return -EINVAL;
1da177e4 2641
e6b043d5
BW		 2642 if (!phydev)
2643 return -ENODEV;
2644
1d5244d0
BH		 2645 if (fep->bufdesc_ex) {
2646 if (cmd == SIOCSHWTSTAMP)
2647 return fec_ptp_set(ndev, rq);
2648 if (cmd == SIOCGHWTSTAMP)
2649 return fec_ptp_get(ndev, rq);
2650 }
ff43da86 2651
28b04113 2652 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2653}
2654
c556167f 2655static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2656{
c556167f 2657 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2658 unsigned int i;
f0b3fbea
SH		 2659 struct sk_buff *skb;
2660 struct bufdesc *bdp;
4d494cdc
FD		 2661 struct fec_enet_priv_tx_q *txq;
2662 struct fec_enet_priv_rx_q *rxq;
59d0f746
FL		 2663 unsigned int q;
2664
2665 for (q = 0; q < fep->num_rx_queues; q++) {
2666 rxq = fep->rx_queue[q];
2667 bdp = rxq->rx_bd_base;
2668 for (i = 0; i < rxq->rx_ring_size; i++) {
2669 skb = rxq->rx_skbuff[i];
2670 rxq->rx_skbuff[i] = NULL;
2671 if (skb) {
2672 dma_unmap_single(&fep->pdev->dev,
5cfa3039 2673 fec32_to_cpu(bdp->cbd_bufaddr),
b64bf4b7 2674 FEC_ENET_RX_FRSIZE - fep->rx_align,
59d0f746
FL		 2675 DMA_FROM_DEVICE);
2676 dev_kfree_skb(skb);
2677 }
2678 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2679 }
2680 }
4d494cdc 2681
59d0f746
FL		 2682 for (q = 0; q < fep->num_tx_queues; q++) {
2683 txq = fep->tx_queue[q];
2684 bdp = txq->tx_bd_base;
2685 for (i = 0; i < txq->tx_ring_size; i++) {
2686 kfree(txq->tx_bounce[i]);
2687 txq->tx_bounce[i] = NULL;
2688 skb = txq->tx_skbuff[i];
2689 txq->tx_skbuff[i] = NULL;
f0b3fbea 2690 dev_kfree_skb(skb);
730ee360 2691 }
f0b3fbea 2692 }
59d0f746 2693}
f0b3fbea 2694
59d0f746
FL		 2695static void fec_enet_free_queue(struct net_device *ndev)
2696{
2697 struct fec_enet_private *fep = netdev_priv(ndev);
2698 int i;
2699 struct fec_enet_priv_tx_q *txq;
2700
2701 for (i = 0; i < fep->num_tx_queues; i++)
2702 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2703 txq = fep->tx_queue[i];
2704 dma_free_coherent(NULL,
2705 txq->tx_ring_size * TSO_HEADER_SIZE,
2706 txq->tso_hdrs,
2707 txq->tso_hdrs_dma);
2708 }
2709
2710 for (i = 0; i < fep->num_rx_queues; i++)
1b4b32c6 2711 kfree(fep->rx_queue[i]);
59d0f746 2712 for (i = 0; i < fep->num_tx_queues; i++)
1b4b32c6 2713 kfree(fep->tx_queue[i]);
59d0f746
FL		 2714}
2715
2716static int fec_enet_alloc_queue(struct net_device *ndev)
2717{
2718 struct fec_enet_private *fep = netdev_priv(ndev);
2719 int i;
2720 int ret = 0;
2721 struct fec_enet_priv_tx_q *txq;
2722
2723 for (i = 0; i < fep->num_tx_queues; i++) {
2724 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2725 if (!txq) {
2726 ret = -ENOMEM;
2727 goto alloc_failed;
2728 }
2729
2730 fep->tx_queue[i] = txq;
2731 txq->tx_ring_size = TX_RING_SIZE;
2732 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2733
2734 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2735 txq->tx_wake_threshold =
2736 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2737
2738 txq->tso_hdrs = dma_alloc_coherent(NULL,
2739 txq->tx_ring_size * TSO_HEADER_SIZE,
2740 &txq->tso_hdrs_dma,
2741 GFP_KERNEL);
2742 if (!txq->tso_hdrs) {
2743 ret = -ENOMEM;
2744 goto alloc_failed;
2745 }
8b7c9efa 2746 }
59d0f746
FL		 2747
2748 for (i = 0; i < fep->num_rx_queues; i++) {
2749 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2750 GFP_KERNEL);
2751 if (!fep->rx_queue[i]) {
2752 ret = -ENOMEM;
2753 goto alloc_failed;
2754 }
2755
2756 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2757 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2758 }
2759 return ret;
2760
2761alloc_failed:
2762 fec_enet_free_queue(ndev);
2763 return ret;
f0b3fbea
SH		 2764}
2765
59d0f746
FL		 2766static int
2767fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
f0b3fbea 2768{
c556167f 2769 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2770 unsigned int i;
f0b3fbea
SH		 2771 struct sk_buff *skb;
2772 struct bufdesc *bdp;
4d494cdc 2773 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2774
59d0f746 2775 rxq = fep->rx_queue[queue];
4d494cdc
FD		 2776 bdp = rxq->rx_bd_base;
2777 for (i = 0; i < rxq->rx_ring_size; i++) {
b72061a3 2778 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2779 if (!skb)
2780 goto err_alloc;
f0b3fbea 2781
1b7bde6d 2782 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
730ee360 2783 dev_kfree_skb(skb);
ffdce2cc 2784 goto err_alloc;
d842a31f 2785 }
730ee360 2786
4d494cdc 2787 rxq->rx_skbuff[i] = skb;
5cfa3039 2788 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
ff43da86
FL		 2789
2790 if (fep->bufdesc_ex) {
2791 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2792 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 2793 }
2794
59d0f746 2795 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
f0b3fbea
SH		 2796 }
2797
2798 /* Set the last buffer to wrap. */
59d0f746 2799 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
5cfa3039 2800 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 2801 return 0;
f0b3fbea 2802
59d0f746
FL		 2803 err_alloc:
2804 fec_enet_free_buffers(ndev);
2805 return -ENOMEM;
2806}
2807
2808static int
2809fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2810{
2811 struct fec_enet_private *fep = netdev_priv(ndev);
2812 unsigned int i;
2813 struct bufdesc *bdp;
2814 struct fec_enet_priv_tx_q *txq;
2815
2816 txq = fep->tx_queue[queue];
4d494cdc
FD		 2817 bdp = txq->tx_bd_base;
2818 for (i = 0; i < txq->tx_ring_size; i++) {
2819 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2820 if (!txq->tx_bounce[i])
ffdce2cc 2821 goto err_alloc;
f0b3fbea 2822
5cfa3039
JB		 2823 bdp->cbd_sc = cpu_to_fec16(0);
2824 bdp->cbd_bufaddr = cpu_to_fec32(0);
6605b730 2825
ff43da86
FL		 2826 if (fep->bufdesc_ex) {
2827 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2828 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
ff43da86
FL		 2829 }
2830
59d0f746 2831 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
f0b3fbea
SH		 2832 }
2833
2834 /* Set the last buffer to wrap. */
59d0f746 2835 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
5cfa3039 2836 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
f0b3fbea
SH		 2837
2838 return 0;
ffdce2cc
RK		 2839
2840 err_alloc:
2841 fec_enet_free_buffers(ndev);
2842 return -ENOMEM;
f0b3fbea
SH		 2843}
2844
59d0f746
FL		 2845static int fec_enet_alloc_buffers(struct net_device *ndev)
2846{
2847 struct fec_enet_private *fep = netdev_priv(ndev);
2848 unsigned int i;
2849
2850 for (i = 0; i < fep->num_rx_queues; i++)
2851 if (fec_enet_alloc_rxq_buffers(ndev, i))
2852 return -ENOMEM;
2853
2854 for (i = 0; i < fep->num_tx_queues; i++)
2855 if (fec_enet_alloc_txq_buffers(ndev, i))
2856 return -ENOMEM;
2857 return 0;
2858}
2859
1da177e4 2860static int
c556167f 2861fec_enet_open(struct net_device *ndev)
1da177e4 2862{
c556167f 2863 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2864 int ret;
1da177e4 2865
8fff755e 2866 ret = pm_runtime_get_sync(&fep->pdev->dev);
b0c6ce24 2867 if (ret < 0)
8fff755e
AL		 2868 return ret;
2869
5bbde4d2 2870 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2871 ret = fec_enet_clk_enable(ndev, true);
2872 if (ret)
8fff755e 2873 goto clk_enable;
e8fcfcd5 2874
1da177e4
LT		 2875 /* I should reset the ring buffers here, but I don't yet know
2876 * a simple way to do that.
2877 */
1da177e4 2878
c556167f 2879 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea 2880 if (ret)
681d2421 2881 goto err_enet_alloc;
f0b3fbea 2882
55dd2753
NA		 2883 /* Init MAC prior to mii bus probe */
2884 fec_restart(ndev);
2885
418bd0d4 2886 /* Probe and connect to PHY when open the interface */
c556167f 2887 ret = fec_enet_mii_probe(ndev);
681d2421
FE		 2888 if (ret)
2889 goto err_enet_mii_probe;
ce5eaf02
RK		 2890
2891 napi_enable(&fep->napi);
e6b043d5 2892 phy_start(fep->phy_dev);
4d494cdc
FD		 2893 netif_tx_start_all_queues(ndev);
2894
de40ed31
NA		 2895 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2896 FEC_WOL_FLAG_ENABLE);
2897
22f6b860 2898 return 0;
681d2421
FE		 2899
2900err_enet_mii_probe:
2901 fec_enet_free_buffers(ndev);
2902err_enet_alloc:
2903 fec_enet_clk_enable(ndev, false);
8fff755e
AL		 2904clk_enable:
2905 pm_runtime_mark_last_busy(&fep->pdev->dev);
2906 pm_runtime_put_autosuspend(&fep->pdev->dev);
681d2421
FE		 2907 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2908 return ret;
1da177e4
LT		 2909}
2910
2911static int
c556167f 2912fec_enet_close(struct net_device *ndev)
1da177e4 2913{
c556167f 2914 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2915
d76cfae9
RK		 2916 phy_stop(fep->phy_dev);
2917
31a6de34
RK		 2918 if (netif_device_present(ndev)) {
2919 napi_disable(&fep->napi);
2920 netif_tx_disable(ndev);
8bbbd3c1 2921 fec_stop(ndev);
31a6de34 2922 }
1da177e4 2923
635cf17c 2924 phy_disconnect(fep->phy_dev);
0b146ca8 2925 fep->phy_dev = NULL;
418bd0d4 2926
e8fcfcd5 2927 fec_enet_clk_enable(ndev, false);
5bbde4d2 2928 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
8fff755e
AL		 2929 pm_runtime_mark_last_busy(&fep->pdev->dev);
2930 pm_runtime_put_autosuspend(&fep->pdev->dev);
2931
db8880bc 2932 fec_enet_free_buffers(ndev);
f0b3fbea 2933
1da177e4
LT		 2934 return 0;
2935}
2936
1da177e4
LT		 2937/* Set or clear the multicast filter for this adaptor.
2938 * Skeleton taken from sunlance driver.
2939 * The CPM Ethernet implementation allows Multicast as well as individual
2940 * MAC address filtering. Some of the drivers check to make sure it is
2941 * a group multicast address, and discard those that are not. I guess I
2942 * will do the same for now, but just remove the test if you want
2943 * individual filtering as well (do the upper net layers want or support
2944 * this kind of feature?).
2945 */
2946
2947#define HASH_BITS 6 /* #bits in hash */
2948#define CRC32_POLY 0xEDB88320
2949
c556167f 2950static void set_multicast_list(struct net_device *ndev)
1da177e4 2951{
c556167f 2952 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2953 struct netdev_hw_addr *ha;
48e2f183 2954 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2955 unsigned char hash;
2956
c556167f 2957 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2958 tmp = readl(fep->hwp + FEC_R_CNTRL);
2959 tmp |= 0x8;
2960 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2961 return;
2962 }
1da177e4 2963
4e831836
SH		 2964 tmp = readl(fep->hwp + FEC_R_CNTRL);
2965 tmp &= ~0x8;
2966 writel(tmp, fep->hwp + FEC_R_CNTRL);
2967
c556167f 2968 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2969 /* Catch all multicast addresses, so set the
2970 * filter to all 1's
2971 */
2972 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2973 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2974
2975 return;
2976 }
2977
2978 /* Clear filter and add the addresses in hash register
2979 */
2980 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2981 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2982
c556167f 2983 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2984 /* calculate crc32 value of mac address */
2985 crc = 0xffffffff;
2986
c556167f 2987 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2988 data = ha->addr[i];
4e831836
SH		 2989 for (bit = 0; bit < 8; bit++, data >>= 1) {
2990 crc = (crc >> 1) ^
2991 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2992 }
2993 }
4e831836
SH		 2994
2995 /* only upper 6 bits (HASH_BITS) are used
2996 * which point to specific bit in he hash registers
2997 */
2998 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2999
3000 if (hash > 31) {
3001 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3002 tmp |= 1 << (hash - 32);
3003 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3004 } else {
3005 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3006 tmp |= 1 << hash;
3007 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3008 }
1da177e4
LT		 3009 }
3010}
3011
22f6b860 3012/* Set a MAC change in hardware. */
009fda83 3013static int
c556167f 3014fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 3015{
c556167f 3016 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 3017 struct sockaddr *addr = p;
3018
44934fac
LS		 3019 if (addr) {
3020 if (!is_valid_ether_addr(addr->sa_data))
3021 return -EADDRNOTAVAIL;
3022 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3023 }
1da177e4 3024
9638d19e
NA		 3025 /* Add netif status check here to avoid system hang in below case:
3026 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3027 * After ethx down, fec all clocks are gated off and then register
3028 * access causes system hang.
3029 */
3030 if (!netif_running(ndev))
3031 return 0;
3032
c556167f
UKK		 3033 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3034 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 3035 fep->hwp + FEC_ADDR_LOW);
c556167f 3036 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 3037 fep->hwp + FEC_ADDR_HIGH);
009fda83 3038 return 0;
1da177e4
LT		 3039}
3040
7f5c6add 3041#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 3042/**
3043 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 3044 * @dev: The FEC network adapter
3045 *
3046 * Polled functionality used by netconsole and others in non interrupt mode
3047 *
3048 */
47a5247f 3049static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 3050{
3051 int i;
3052 struct fec_enet_private *fep = netdev_priv(dev);
3053
3054 for (i = 0; i < FEC_IRQ_NUM; i++) {
3055 if (fep->irq[i] > 0) {
3056 disable_irq(fep->irq[i]);
3057 fec_enet_interrupt(fep->irq[i], dev);
3058 enable_irq(fep->irq[i]);
3059 }
3060 }
3061}
3062#endif
3063
5bc26726 3064static inline void fec_enet_set_netdev_features(struct net_device *netdev,
4c09eed9
JB		 3065 netdev_features_t features)
3066{
3067 struct fec_enet_private *fep = netdev_priv(netdev);
3068 netdev_features_t changed = features ^ netdev->features;
3069
3070 netdev->features = features;
3071
3072 /* Receive checksum has been changed */
3073 if (changed & NETIF_F_RXCSUM) {
3074 if (features & NETIF_F_RXCSUM)
3075 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3076 else
3077 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 3078 }
5bc26726
NA		 3079}
3080
3081static int fec_set_features(struct net_device *netdev,
3082 netdev_features_t features)
3083{
3084 struct fec_enet_private *fep = netdev_priv(netdev);
3085 netdev_features_t changed = features ^ netdev->features;
4c09eed9 3086
5b40f709 3087 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
5bc26726
NA		 3088 napi_disable(&fep->napi);
3089 netif_tx_lock_bh(netdev);
3090 fec_stop(netdev);
3091 fec_enet_set_netdev_features(netdev, features);
ef83337d 3092 fec_restart(netdev);
4d494cdc 3093 netif_tx_wake_all_queues(netdev);
8506fa1d
RK		 3094 netif_tx_unlock_bh(netdev);
3095 napi_enable(&fep->napi);
5bc26726
NA		 3096 } else {
3097 fec_enet_set_netdev_features(netdev, features);
4c09eed9
JB		 3098 }
3099
3100 return 0;
3101}
3102
009fda83
SH		 3103static const struct net_device_ops fec_netdev_ops = {
3104 .ndo_open = fec_enet_open,
3105 .ndo_stop = fec_enet_close,
3106 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 3107 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 3108 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 3109 .ndo_validate_addr = eth_validate_addr,
3110 .ndo_tx_timeout = fec_timeout,
3111 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 3112 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 3113#ifdef CONFIG_NET_POLL_CONTROLLER
3114 .ndo_poll_controller = fec_poll_controller,
3115#endif
4c09eed9 3116 .ndo_set_features = fec_set_features,
009fda83
SH		 3117};
3118
1da177e4
LT		 3119 /*
3120 * XXX: We need to clean up on failure exits here.
ead73183 3121 *
1da177e4 3122 */
c556167f 3123static int fec_enet_init(struct net_device *ndev)
1da177e4 3124{
c556167f 3125 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 3126 struct fec_enet_priv_tx_q *txq;
3127 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 3128 struct bufdesc *cbd_base;
4d494cdc 3129 dma_addr_t bd_dma;
55d0218a 3130 int bd_size;
59d0f746 3131 unsigned int i;
55d0218a 3132
41ef84ce
FD		 3133#if defined(CONFIG_ARM)
3134 fep->rx_align = 0xf;
3135 fep->tx_align = 0xf;
3136#else
3137 fep->rx_align = 0x3;
3138 fep->tx_align = 0x3;
3139#endif
3140
59d0f746 3141 fec_enet_alloc_queue(ndev);
79f33912 3142
55d0218a
NA		 3143 if (fep->bufdesc_ex)
3144 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3145 else
3146 fep->bufdesc_size = sizeof(struct bufdesc);
4d494cdc 3147 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
55d0218a 3148 fep->bufdesc_size;
1da177e4 3149
8d4dd5cf 3150 /* Allocate memory for buffer descriptors. */
c0a1a0a6
LS		 3151 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3152 GFP_KERNEL);
4d494cdc 3153 if (!cbd_base) {
79f33912
NA		 3154 return -ENOMEM;
3155 }
3156
4d494cdc 3157 memset(cbd_base, 0, bd_size);
1da177e4 3158
49da97dc 3159 /* Get the Ethernet address */
c556167f 3160 fec_get_mac(ndev);
44934fac
LS		 3161 /* make sure MAC we just acquired is programmed into the hw */
3162 fec_set_mac_address(ndev, NULL);
1da177e4 3163
8d4dd5cf 3164 /* Set receive and transmit descriptor base. */
59d0f746
FL		 3165 for (i = 0; i < fep->num_rx_queues; i++) {
3166 rxq = fep->rx_queue[i];
3167 rxq->index = i;
3168 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3169 rxq->bd_dma = bd_dma;
3170 if (fep->bufdesc_ex) {
3171 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3172 cbd_base = (struct bufdesc *)
3173 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3174 } else {
3175 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3176 cbd_base += rxq->rx_ring_size;
3177 }
3178 }
3179
3180 for (i = 0; i < fep->num_tx_queues; i++) {
3181 txq = fep->tx_queue[i];
3182 txq->index = i;
3183 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3184 txq->bd_dma = bd_dma;
3185 if (fep->bufdesc_ex) {
3186 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3187 cbd_base = (struct bufdesc *)
3188 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3189 } else {
3190 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3191 cbd_base += txq->tx_ring_size;
3192 }
3193 }
4d494cdc 3194
1da177e4 3195
22f6b860 3196 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 3197 ndev->watchdog_timeo = TX_TIMEOUT;
3198 ndev->netdev_ops = &fec_netdev_ops;
3199 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 3200
dc975382 3201 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 3202 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 3203
6b7e4008 3204 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 3205 /* enable hw VLAN support */
3206 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 3207
6b7e4008 3208 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 3209 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3210
48496255
SG		 3211 /* enable hw accelerator */
3212 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 3213 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 3214 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3215 }
4c09eed9 3216
6b7e4008 3217 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
41ef84ce
FD		 3218 fep->tx_align = 0;
3219 fep->rx_align = 0x3f;
3220 }
3221
09d1e541
NA		 3222 ndev->hw_features = ndev->features;
3223
ef83337d 3224 fec_restart(ndev);
1da177e4 3225
1da177e4
LT		 3226 return 0;
3227}
3228
ca2cc333 3229#ifdef CONFIG_OF
33897cc8 3230static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3231{
3232 int err, phy_reset;
a3caad0a 3233 int msec = 1;
ca2cc333
SG		 3234 struct device_node *np = pdev->dev.of_node;
3235
3236 if (!np)
a9b2c8ef 3237 return;
ca2cc333 3238
a3caad0a
SG		 3239 of_property_read_u32(np, "phy-reset-duration", &msec);
3240 /* A sane reset duration should not be longer than 1s */
3241 if (msec > 1000)
3242 msec = 1;
3243
ca2cc333 3244 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 3245 if (!gpio_is_valid(phy_reset))
3246 return;
3247
119fc007
SG		 3248 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3249 GPIOF_OUT_INIT_LOW, "phy-reset");
ca2cc333 3250 if (err) {
07dcf8e9 3251 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 3252 return;
ca2cc333 3253 }
a3caad0a 3254 msleep(msec);
f4444574 3255 gpio_set_value_cansleep(phy_reset, 1);
ca2cc333
SG		 3256}
3257#else /* CONFIG_OF */
0c7768a0 3258static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3259{
3260 /*
3261 * In case of platform probe, the reset has been done
3262 * by machine code.
3263 */
ca2cc333
SG		 3264}
3265#endif /* CONFIG_OF */
3266
9fc095f1
FD		 3267static void
3268fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3269{
3270 struct device_node *np = pdev->dev.of_node;
9fc095f1
FD		 3271
3272 *num_tx = *num_rx = 1;
3273
3274 if (!np || !of_device_is_available(np))
3275 return;
3276
3277 /* parse the num of tx and rx queues */
73b1c90d 3278 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
b7bd75cf 3279
73b1c90d 3280 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
9fc095f1
FD		 3281
3282 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
b7bd75cf
FL		 3283 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3284 *num_tx);
9fc095f1
FD		 3285 *num_tx = 1;
3286 return;
3287 }
3288
3289 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
b7bd75cf
FL		 3290 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3291 *num_rx);
9fc095f1
FD		 3292 *num_rx = 1;
3293 return;
3294 }
3295
3296}
3297
33897cc8 3298static int
ead73183
SH		 3299fec_probe(struct platform_device *pdev)
3300{
3301 struct fec_enet_private *fep;
5eb32bd0 3302 struct fec_platform_data *pdata;
ead73183
SH		 3303 struct net_device *ndev;
3304 int i, irq, ret = 0;
3305 struct resource *r;
ca2cc333 3306 const struct of_device_id *of_id;
43af940c 3307 static int dev_id;
407066f8 3308 struct device_node *np = pdev->dev.of_node, *phy_node;
b7bd75cf
FL		 3309 int num_tx_qs;
3310 int num_rx_qs;
ca2cc333 3311
9fc095f1
FD		 3312 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3313
ead73183 3314 /* Init network device */
9fc095f1
FD		 3315 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3316 num_tx_qs, num_rx_qs);
83e519b6
FE		 3317 if (!ndev)
3318 return -ENOMEM;
ead73183
SH		 3319
3320 SET_NETDEV_DEV(ndev, &pdev->dev);
3321
3322 /* setup board info structure */
3323 fep = netdev_priv(ndev);
ead73183 3324
6b7e4008
LW		 3325 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3326 if (of_id)
3327 pdev->id_entry = of_id->data;
3328 fep->quirks = pdev->id_entry->driver_data;
3329
0c818594 3330 fep->netdev = ndev;
9fc095f1
FD		 3331 fep->num_rx_queues = num_rx_qs;
3332 fep->num_tx_queues = num_tx_qs;
3333
d1391930 3334#if !defined(CONFIG_M5272)
baa70a5c 3335 /* default enable pause frame auto negotiation */
6b7e4008 3336 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
baa70a5c 3337 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 3338#endif
baa70a5c 3339
5bbde4d2
NA		 3340 /* Select default pin state */
3341 pinctrl_pm_select_default_state(&pdev->dev);
3342
399db75b 3343 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 3344 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3345 if (IS_ERR(fep->hwp)) {
3346 ret = PTR_ERR(fep->hwp);
3347 goto failed_ioremap;
3348 }
3349
e6b043d5 3350 fep->pdev = pdev;
43af940c 3351 fep->dev_id = dev_id++;
ead73183 3352
ead73183
SH		 3353 platform_set_drvdata(pdev, ndev);
3354
de40ed31
NA		 3355 if (of_get_property(np, "fsl,magic-packet", NULL))
3356 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3357
407066f8
UKK		 3358 phy_node = of_parse_phandle(np, "phy-handle", 0);
3359 if (!phy_node && of_phy_is_fixed_link(np)) {
3360 ret = of_phy_register_fixed_link(np);
3361 if (ret < 0) {
3362 dev_err(&pdev->dev,
3363 "broken fixed-link specification\n");
3364 goto failed_phy;
3365 }
3366 phy_node = of_node_get(np);
3367 }
3368 fep->phy_node = phy_node;
3369
6c5f7808 3370 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 3371 if (ret < 0) {
94660ba0 3372 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 3373 if (pdata)
3374 fep->phy_interface = pdata->phy;
3375 else
3376 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3377 } else {
3378 fep->phy_interface = ret;
3379 }
3380
f4d40de3
SH		 3381 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3382 if (IS_ERR(fep->clk_ipg)) {
3383 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 3384 goto failed_clk;
3385 }
f4d40de3
SH		 3386
3387 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3388 if (IS_ERR(fep->clk_ahb)) {
3389 ret = PTR_ERR(fep->clk_ahb);
3390 goto failed_clk;
3391 }
3392
d851b47b
FD		 3393 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3394
daa7d392
WS		 3395 /* enet_out is optional, depends on board */
3396 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3397 if (IS_ERR(fep->clk_enet_out))
3398 fep->clk_enet_out = NULL;
3399
91c0d987
NA		 3400 fep->ptp_clk_on = false;
3401 mutex_init(&fep->ptp_clk_mutex);
9b5330ed
FD		 3402
3403 /* clk_ref is optional, depends on board */
3404 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3405 if (IS_ERR(fep->clk_ref))
3406 fep->clk_ref = NULL;
3407
6b7e4008 3408 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730
FL		 3409 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3410 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 3411 fep->clk_ptp = NULL;
217b5844 3412 fep->bufdesc_ex = false;
6605b730 3413 }
6605b730 3414
e8fcfcd5 3415 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 3416 if (ret)
3417 goto failed_clk;
3418
8fff755e
AL		 3419 ret = clk_prepare_enable(fep->clk_ipg);
3420 if (ret)
3421 goto failed_clk_ipg;
3422
f4e9f3d2
FE		 3423 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3424 if (!IS_ERR(fep->reg_phy)) {
3425 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 3426 if (ret) {
3427 dev_err(&pdev->dev,
3428 "Failed to enable phy regulator: %d\n", ret);
3429 goto failed_regulator;
3430 }
f6a4d607
FE		 3431 } else {
3432 fep->reg_phy = NULL;
5fa9c0fe
SG		 3433 }
3434
8fff755e
AL		 3435 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3436 pm_runtime_use_autosuspend(&pdev->dev);
14d2b7c1 3437 pm_runtime_get_noresume(&pdev->dev);
8fff755e
AL		 3438 pm_runtime_set_active(&pdev->dev);
3439 pm_runtime_enable(&pdev->dev);
3440
2ca9b2aa
SG		 3441 fec_reset_phy(pdev);
3442
e2f8d555 3443 if (fep->bufdesc_ex)
ca162a82 3444 fec_ptp_init(pdev);
e2f8d555
FE		 3445
3446 ret = fec_enet_init(ndev);
3447 if (ret)
3448 goto failed_init;
3449
3450 for (i = 0; i < FEC_IRQ_NUM; i++) {
3451 irq = platform_get_irq(pdev, i);
3452 if (irq < 0) {
3453 if (i)
3454 break;
3455 ret = irq;
3456 goto failed_irq;
3457 }
0d9b2ab1 3458 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 3459 0, pdev->name, ndev);
0d9b2ab1 3460 if (ret)
e2f8d555 3461 goto failed_irq;
de40ed31
NA		 3462
3463 fep->irq[i] = irq;
e2f8d555
FE		 3464 }
3465
b4d39b53 3466 init_completion(&fep->mdio_done);
e6b043d5
BW		 3467 ret = fec_enet_mii_init(pdev);
3468 if (ret)
3469 goto failed_mii_init;
3470
03c698c9
OS		 3471 /* Carrier starts down, phylib will bring it up */
3472 netif_carrier_off(ndev);
e8fcfcd5 3473 fec_enet_clk_enable(ndev, false);
5bbde4d2 3474 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 3475
ead73183
SH		 3476 ret = register_netdev(ndev);
3477 if (ret)
3478 goto failed_register;
3479
de40ed31
NA		 3480 device_init_wakeup(&ndev->dev, fep->wol_flag &
3481 FEC_WOL_HAS_MAGIC_PACKET);
3482
eb1d0640
FE		 3483 if (fep->bufdesc_ex && fep->ptp_clock)
3484 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3485
1b7bde6d 3486 fep->rx_copybreak = COPYBREAK_DEFAULT;
36cdc743 3487 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
8fff755e
AL		 3488
3489 pm_runtime_mark_last_busy(&pdev->dev);
3490 pm_runtime_put_autosuspend(&pdev->dev);
3491
ead73183
SH		 3492 return 0;
3493
3494failed_register:
e6b043d5
BW		 3495 fec_enet_mii_remove(fep);
3496failed_mii_init:
7a2bbd8d 3497failed_irq:
7a2bbd8d 3498failed_init:
32cba57b 3499 fec_ptp_stop(pdev);
f6a4d607
FE		 3500 if (fep->reg_phy)
3501 regulator_disable(fep->reg_phy);
5fa9c0fe 3502failed_regulator:
8fff755e
AL		 3503 clk_disable_unprepare(fep->clk_ipg);
3504failed_clk_ipg:
e8fcfcd5 3505 fec_enet_clk_enable(ndev, false);
ead73183 3506failed_clk:
407066f8
UKK		 3507failed_phy:
3508 of_node_put(phy_node);
ead73183
SH		 3509failed_ioremap:
3510 free_netdev(ndev);
3511
3512 return ret;
3513}
3514
33897cc8 3515static int
ead73183
SH		 3516fec_drv_remove(struct platform_device *pdev)
3517{
3518 struct net_device *ndev = platform_get_drvdata(pdev);
3519 struct fec_enet_private *fep = netdev_priv(ndev);
3520
36cdc743 3521 cancel_work_sync(&fep->tx_timeout_work);
32cba57b 3522 fec_ptp_stop(pdev);
e163cc97 3523 unregister_netdev(ndev);
e6b043d5 3524 fec_enet_mii_remove(fep);
f6a4d607
FE		 3525 if (fep->reg_phy)
3526 regulator_disable(fep->reg_phy);
407066f8 3527 of_node_put(fep->phy_node);
ead73183 3528 free_netdev(ndev);
28e2188e 3529
ead73183
SH		 3530 return 0;
3531}
3532
dd66d386 3533static int __maybe_unused fec_suspend(struct device *dev)
ead73183 3534{
87cad5c3 3535 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3536 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 3537
da1774e5 3538 rtnl_lock();
04e5216d 3539 if (netif_running(ndev)) {
de40ed31
NA		 3540 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3541 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
d76cfae9 3542 phy_stop(fep->phy_dev);
31a6de34
RK		 3543 napi_disable(&fep->napi);
3544 netif_tx_lock_bh(ndev);
04e5216d 3545 netif_device_detach(ndev);
31a6de34
RK		 3546 netif_tx_unlock_bh(ndev);
3547 fec_stop(ndev);
f4c4a4e0 3548 fec_enet_clk_enable(ndev, false);
de40ed31
NA		 3549 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3550 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
ead73183 3551 }
da1774e5
RK		 3552 rtnl_unlock();
3553
de40ed31 3554 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
238f7bc7
FE		 3555 regulator_disable(fep->reg_phy);
3556
858eeb7d
NA		 3557 /* SOC supply clock to phy, when clock is disabled, phy link down
3558 * SOC control phy regulator, when regulator is disabled, phy link down
3559 */
3560 if (fep->clk_enet_out || fep->reg_phy)
3561 fep->link = 0;
3562
ead73183
SH		 3563 return 0;
3564}
3565
dd66d386 3566static int __maybe_unused fec_resume(struct device *dev)
ead73183 3567{
87cad5c3 3568 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3569 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 3570 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
238f7bc7 3571 int ret;
de40ed31 3572 int val;
238f7bc7 3573
de40ed31 3574 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
238f7bc7
FE		 3575 ret = regulator_enable(fep->reg_phy);
3576 if (ret)
3577 return ret;
3578 }
ead73183 3579
da1774e5 3580 rtnl_lock();
04e5216d 3581 if (netif_running(ndev)) {
f4c4a4e0
NA		 3582 ret = fec_enet_clk_enable(ndev, true);
3583 if (ret) {
3584 rtnl_unlock();
3585 goto failed_clk;
3586 }
de40ed31
NA		 3587 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3588 if (pdata && pdata->sleep_mode_enable)
3589 pdata->sleep_mode_enable(false);
3590 val = readl(fep->hwp + FEC_ECNTRL);
3591 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3592 writel(val, fep->hwp + FEC_ECNTRL);
3593 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3594 } else {
3595 pinctrl_pm_select_default_state(&fep->pdev->dev);
3596 }
ef83337d 3597 fec_restart(ndev);
31a6de34 3598 netif_tx_lock_bh(ndev);
6af42d42 3599 netif_device_attach(ndev);
dbc64a8e 3600 netif_tx_unlock_bh(ndev);
6af42d42 3601 napi_enable(&fep->napi);
d76cfae9 3602 phy_start(fep->phy_dev);
ead73183 3603 }
da1774e5 3604 rtnl_unlock();
04e5216d 3605
ead73183 3606 return 0;
13a097bd 3607
e8fcfcd5 3608failed_clk:
13a097bd
FE		 3609 if (fep->reg_phy)
3610 regulator_disable(fep->reg_phy);
3611 return ret;
ead73183
SH		 3612}
3613
8fff755e
AL		 3614static int __maybe_unused fec_runtime_suspend(struct device *dev)
3615{
3616 struct net_device *ndev = dev_get_drvdata(dev);
3617 struct fec_enet_private *fep = netdev_priv(ndev);
3618
3619 clk_disable_unprepare(fep->clk_ipg);
3620
3621 return 0;
3622}
3623
3624static int __maybe_unused fec_runtime_resume(struct device *dev)
3625{
3626 struct net_device *ndev = dev_get_drvdata(dev);
3627 struct fec_enet_private *fep = netdev_priv(ndev);
3628
3629 return clk_prepare_enable(fep->clk_ipg);
3630}
3631
3632static const struct dev_pm_ops fec_pm_ops = {
3633 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3634 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3635};
59d4289b 3636
ead73183
SH		 3637static struct platform_driver fec_driver = {
3638 .driver = {
b5680e0b 3639 .name = DRIVER_NAME,
87cad5c3 3640 .pm = &fec_pm_ops,
ca2cc333 3641 .of_match_table = fec_dt_ids,
ead73183 3642 },
b5680e0b 3643 .id_table = fec_devtype,
87cad5c3 3644 .probe = fec_probe,
33897cc8 3645 .remove = fec_drv_remove,
ead73183
SH		 3646};
3647
aaca2377 3648module_platform_driver(fec_driver);
1da177e4 3649
f8c0aca9 3650MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 3651MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)