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bpf: fix bpf_perf_event_read() loop upper bound
[linux-2.6-block.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
8fff755e 27#include <linux/pm_runtime.h>
1da177e4
LT		 28#include <linux/ptrace.h>
29#include <linux/errno.h>
30#include <linux/ioport.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
4c09eed9
JB		 37#include <linux/in.h>
38#include <linux/ip.h>
39#include <net/ip.h>
79f33912 40#include <net/tso.h>
4c09eed9
JB		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/icmp.h>
1da177e4
LT		 44#include <linux/spinlock.h>
45#include <linux/workqueue.h>
46#include <linux/bitops.h>
6f501b17
SH		 47#include <linux/io.h>
48#include <linux/irq.h>
196719ec 49#include <linux/clk.h>
ead73183 50#include <linux/platform_device.h>
e6b043d5 51#include <linux/phy.h>
5eb32bd0 52#include <linux/fec.h>
ca2cc333
SG		 53#include <linux/of.h>
54#include <linux/of_device.h>
55#include <linux/of_gpio.h>
407066f8 56#include <linux/of_mdio.h>
ca2cc333 57#include <linux/of_net.h>
5fa9c0fe 58#include <linux/regulator/consumer.h>
cdffcf1b 59#include <linux/if_vlan.h>
a68ab98e 60#include <linux/pinctrl/consumer.h>
c259c132 61#include <linux/prefetch.h>
1da177e4 62
080853af 63#include <asm/cacheflush.h>
196719ec 64
1da177e4 65#include "fec.h"
1da177e4 66
772e42b0 67static void set_multicast_list(struct net_device *ndev);
d851b47b 68static void fec_enet_itr_coal_init(struct net_device *ndev);
772e42b0 69
b5680e0b
SG		 70#define DRIVER_NAME "fec"
71
4d494cdc
FD		 72#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
73
baa70a5c
FL		 74/* Pause frame feild and FIFO threshold */
75#define FEC_ENET_FCE (1 << 5)
76#define FEC_ENET_RSEM_V 0x84
77#define FEC_ENET_RSFL_V 16
78#define FEC_ENET_RAEM_V 0x8
79#define FEC_ENET_RAFL_V 0x8
80#define FEC_ENET_OPD_V 0xFFF0
8fff755e 81#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
baa70a5c 82
b5680e0b
SG		 83static struct platform_device_id fec_devtype[] = {
84 {
0ca1e290 85 /* keep it for coldfire */
b5680e0b
SG		 86 .name = DRIVER_NAME,
87 .driver_data = 0,
0ca1e290
SG		 88 }, {
89 .name = "imx25-fec",
18803495 90 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
0ca1e290
SG		 91 }, {
92 .name = "imx27-fec",
18803495 93 .driver_data = FEC_QUIRK_HAS_RACC,
b5680e0b
SG		 94 }, {
95 .name = "imx28-fec",
3d125f9c 96 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
18803495 97 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
230dec61
SG		 98 }, {
99 .name = "imx6q-fec",
ff43da86 100 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 101 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
18803495
GU		 102 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
103 FEC_QUIRK_HAS_RACC,
ca7c4a45 104 }, {
36803542 105 .name = "mvf600-fec",
18803495 106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
95a77470
FD		 107 }, {
108 .name = "imx6sx-fec",
109 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
f88c7ede 111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
18803495
GU		 112 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
113 FEC_QUIRK_HAS_RACC,
0ca1e290
SG		 114 }, {
115 /* sentinel */
116 }
b5680e0b 117};
0ca1e290 118MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 119
ca2cc333 120enum imx_fec_type {
a7dd3219 121 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 122 IMX27_FEC, /* runs on i.mx27/35/51 */
123 IMX28_FEC,
230dec61 124 IMX6Q_FEC,
36803542 125 MVF600_FEC,
ba593e00 126 IMX6SX_FEC,
ca2cc333
SG		 127};
128
129static const struct of_device_id fec_dt_ids[] = {
130 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
131 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
132 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 133 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 134 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ba593e00 135 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
ca2cc333
SG		 136 { /* sentinel */ }
137};
138MODULE_DEVICE_TABLE(of, fec_dt_ids);
139
49da97dc
SG		 140static unsigned char macaddr[ETH_ALEN];
141module_param_array(macaddr, byte, NULL, 0);
142MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 143
49da97dc 144#if defined(CONFIG_M5272)
1da177e4
LT		 145/*
146 * Some hardware gets it MAC address out of local flash memory.
147 * if this is non-zero then assume it is the address to get MAC from.
148 */
149#if defined(CONFIG_NETtel)
150#define FEC_FLASHMAC 0xf0006006
151#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
152#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 153#elif defined(CONFIG_CANCam)
154#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 155#elif defined (CONFIG_M5272C3)
156#define FEC_FLASHMAC (0xffe04000 + 4)
157#elif defined(CONFIG_MOD5272)
a7dd3219 158#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 159#else
160#define FEC_FLASHMAC 0
161#endif
43be6366 162#endif /* CONFIG_M5272 */
ead73183 163
cdffcf1b 164/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 165 */
cdffcf1b 166#define PKT_MAXBUF_SIZE 1522
1da177e4 167#define PKT_MINBUF_SIZE 64
cdffcf1b 168#define PKT_MAXBLR_SIZE 1536
1da177e4 169
4c09eed9
JB		 170/* FEC receive acceleration */
171#define FEC_RACC_IPDIS (1 << 1)
172#define FEC_RACC_PRODIS (1 << 2)
173#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
174
1da177e4 175/*
6b265293 176 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 177 * size bits. Other FEC hardware does not, so we need to take that into
178 * account when setting it.
179 */
562d2f8c 180#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 181 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 182#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
183#else
184#define OPT_FRAME_SIZE 0
185#endif
186
e6b043d5
BW		 187/* FEC MII MMFR bits definition */
188#define FEC_MMFR_ST (1 << 30)
189#define FEC_MMFR_OP_READ (2 << 28)
190#define FEC_MMFR_OP_WRITE (1 << 28)
191#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
192#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
193#define FEC_MMFR_TA (2 << 16)
194#define FEC_MMFR_DATA(v) (v & 0xffff)
de40ed31
NA		 195/* FEC ECR bits definition */
196#define FEC_ECR_MAGICEN (1 << 2)
197#define FEC_ECR_SLEEP (1 << 3)
1da177e4 198
c3b084c2 199#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 200
22f6b860
SH		 201/* Transmitter timeout */
202#define TX_TIMEOUT (2 * HZ)
1da177e4 203
baa70a5c
FL		 204#define FEC_PAUSE_FLAG_AUTONEG 0x1
205#define FEC_PAUSE_FLAG_ENABLE 0x2
de40ed31
NA		 206#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
207#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
208#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
baa70a5c 209
1b7bde6d
NA		 210#define COPYBREAK_DEFAULT 256
211
79f33912
NA		 212#define TSO_HEADER_SIZE 128
213/* Max number of allowed TCP segments for software TSO */
214#define FEC_MAX_TSO_SEGS 100
215#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
216
217#define IS_TSO_HEADER(txq, addr) \
218 ((addr >= txq->tso_hdrs_dma) && \
219 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
220
e163cc97
LW		 221static int mii_cnt;
222
36e24e2e 223static inline
4d494cdc
FD		 224struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
225 struct fec_enet_private *fep,
226 int queue_id)
ff43da86 227{
36e24e2e
DFB		 228 struct bufdesc *new_bd = bdp + 1;
229 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
4d494cdc
FD		 230 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
231 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
36e24e2e
DFB		 232 struct bufdesc_ex *ex_base;
233 struct bufdesc *base;
234 int ring_size;
235
4d494cdc
FD		 236 if (bdp >= txq->tx_bd_base) {
237 base = txq->tx_bd_base;
238 ring_size = txq->tx_ring_size;
239 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
36e24e2e 240 } else {
4d494cdc
FD		 241 base = rxq->rx_bd_base;
242 ring_size = rxq->rx_ring_size;
243 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
36e24e2e
DFB		 244 }
245
246 if (fep->bufdesc_ex)
247 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
248 ex_base : ex_new_bd);
ff43da86 249 else
36e24e2e
DFB		 250 return (new_bd >= (base + ring_size)) ?
251 base : new_bd;
ff43da86
FL		 252}
253
36e24e2e 254static inline
4d494cdc
FD		 255struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
256 struct fec_enet_private *fep,
257 int queue_id)
ff43da86 258{
36e24e2e
DFB		 259 struct bufdesc *new_bd = bdp - 1;
260 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
4d494cdc
FD		 261 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
262 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
36e24e2e
DFB		 263 struct bufdesc_ex *ex_base;
264 struct bufdesc *base;
265 int ring_size;
266
4d494cdc
FD		 267 if (bdp >= txq->tx_bd_base) {
268 base = txq->tx_bd_base;
269 ring_size = txq->tx_ring_size;
270 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
36e24e2e 271 } else {
4d494cdc
FD		 272 base = rxq->rx_bd_base;
273 ring_size = rxq->rx_ring_size;
274 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
36e24e2e
DFB		 275 }
276
277 if (fep->bufdesc_ex)
278 return (struct bufdesc *)((ex_new_bd < ex_base) ?
279 (ex_new_bd + ring_size) : ex_new_bd);
ff43da86 280 else
36e24e2e 281 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
ff43da86
FL		 282}
283
61a4427b
NA		 284static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
285 struct fec_enet_private *fep)
286{
287 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
288}
289
4d494cdc
FD		 290static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
291 struct fec_enet_priv_tx_q *txq)
6e909283
NA		 292{
293 int entries;
294
4d494cdc
FD		 295 entries = ((const char *)txq->dirty_tx -
296 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
6e909283 297
4d494cdc 298 return entries > 0 ? entries : entries + txq->tx_ring_size;
6e909283
NA		 299}
300
c20e599b 301static void swap_buffer(void *bufaddr, int len)
b5680e0b
SG		 302{
303 int i;
304 unsigned int *buf = bufaddr;
305
7b487d07 306 for (i = 0; i < len; i += 4, buf++)
e453789a 307 swab32s(buf);
b5680e0b
SG		 308}
309
1310b544
LW		 310static void swap_buffer2(void *dst_buf, void *src_buf, int len)
311{
312 int i;
313 unsigned int *src = src_buf;
314 unsigned int *dst = dst_buf;
315
316 for (i = 0; i < len; i += 4, src++, dst++)
317 *dst = swab32p(src);
318}
319
344756f6
RK		 320static void fec_dump(struct net_device *ndev)
321{
322 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 323 struct bufdesc *bdp;
324 struct fec_enet_priv_tx_q *txq;
325 int index = 0;
344756f6
RK		 326
327 netdev_info(ndev, "TX ring dump\n");
328 pr_info("Nr SC addr len SKB\n");
329
4d494cdc
FD		 330 txq = fep->tx_queue[0];
331 bdp = txq->tx_bd_base;
332
344756f6
RK		 333 do {
334 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
335 index,
4d494cdc
FD		 336 bdp == txq->cur_tx ? 'S' : ' ',
337 bdp == txq->dirty_tx ? 'H' : ' ',
344756f6 338 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
4d494cdc
FD		 339 txq->tx_skbuff[index]);
340 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
344756f6 341 index++;
4d494cdc 342 } while (bdp != txq->tx_bd_base);
344756f6
RK		 343}
344
62a02c98
FD		 345static inline bool is_ipv4_pkt(struct sk_buff *skb)
346{
347 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
348}
349
4c09eed9
JB		 350static int
351fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
352{
353 /* Only run for packets requiring a checksum. */
354 if (skb->ip_summed != CHECKSUM_PARTIAL)
355 return 0;
356
357 if (unlikely(skb_cow_head(skb, 0)))
358 return -1;
359
62a02c98
FD		 360 if (is_ipv4_pkt(skb))
361 ip_hdr(skb)->check = 0;
4c09eed9
JB		 362 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
363
364 return 0;
365}
366
c4bc44c6 367static struct bufdesc *
4d494cdc
FD		 368fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
369 struct sk_buff *skb,
370 struct net_device *ndev)
1da177e4 371{
c556167f 372 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 373 struct bufdesc *bdp = txq->cur_tx;
6e909283
NA		 374 struct bufdesc_ex *ebdp;
375 int nr_frags = skb_shinfo(skb)->nr_frags;
4d494cdc 376 unsigned short queue = skb_get_queue_mapping(skb);
6e909283
NA		 377 int frag, frag_len;
378 unsigned short status;
379 unsigned int estatus = 0;
380 skb_frag_t *this_frag;
de5fb0a0 381 unsigned int index;
6e909283 382 void *bufaddr;
d6bf3143 383 dma_addr_t addr;
6e909283 384 int i;
1da177e4 385
6e909283
NA		 386 for (frag = 0; frag < nr_frags; frag++) {
387 this_frag = &skb_shinfo(skb)->frags[frag];
4d494cdc 388 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
6e909283
NA		 389 ebdp = (struct bufdesc_ex *)bdp;
390
391 status = bdp->cbd_sc;
392 status &= ~BD_ENET_TX_STATS;
393 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
394 frag_len = skb_shinfo(skb)->frags[frag].size;
395
396 /* Handle the last BD specially */
397 if (frag == nr_frags - 1) {
398 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
399 if (fep->bufdesc_ex) {
400 estatus |= BD_ENET_TX_INT;
401 if (unlikely(skb_shinfo(skb)->tx_flags &
402 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
403 estatus |= BD_ENET_TX_TS;
404 }
405 }
406
407 if (fep->bufdesc_ex) {
6b7e4008 408 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 409 estatus |= FEC_TX_BD_FTYPE(queue);
6e909283
NA		 410 if (skb->ip_summed == CHECKSUM_PARTIAL)
411 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
412 ebdp->cbd_bdu = 0;
413 ebdp->cbd_esc = estatus;
414 }
415
416 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
417
4d494cdc 418 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
41ef84ce 419 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 420 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 421 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
422 bufaddr = txq->tx_bounce[index];
6e909283 423
6b7e4008 424 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 425 swap_buffer(bufaddr, frag_len);
426 }
427
d6bf3143
RK		 428 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
429 DMA_TO_DEVICE);
430 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 431 dev_kfree_skb_any(skb);
432 if (net_ratelimit())
433 netdev_err(ndev, "Tx DMA memory map failed\n");
434 goto dma_mapping_error;
435 }
436
d6bf3143 437 bdp->cbd_bufaddr = addr;
6e909283
NA		 438 bdp->cbd_datlen = frag_len;
439 bdp->cbd_sc = status;
440 }
441
c4bc44c6 442 return bdp;
6e909283 443dma_mapping_error:
4d494cdc 444 bdp = txq->cur_tx;
6e909283 445 for (i = 0; i < frag; i++) {
4d494cdc 446 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
6e909283
NA		 447 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
448 bdp->cbd_datlen, DMA_TO_DEVICE);
449 }
c4bc44c6 450 return ERR_PTR(-ENOMEM);
6e909283 451}
1da177e4 452
4d494cdc
FD		 453static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
454 struct sk_buff *skb, struct net_device *ndev)
6e909283
NA		 455{
456 struct fec_enet_private *fep = netdev_priv(ndev);
6e909283
NA		 457 int nr_frags = skb_shinfo(skb)->nr_frags;
458 struct bufdesc *bdp, *last_bdp;
459 void *bufaddr;
d6bf3143 460 dma_addr_t addr;
6e909283
NA		 461 unsigned short status;
462 unsigned short buflen;
4d494cdc 463 unsigned short queue;
6e909283
NA		 464 unsigned int estatus = 0;
465 unsigned int index;
79f33912 466 int entries_free;
22f6b860 467
4d494cdc 468 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
79f33912
NA		 469 if (entries_free < MAX_SKB_FRAGS + 1) {
470 dev_kfree_skb_any(skb);
471 if (net_ratelimit())
472 netdev_err(ndev, "NOT enough BD for SG!\n");
473 return NETDEV_TX_OK;
474 }
475
4c09eed9
JB		 476 /* Protocol checksum off-load for TCP and UDP. */
477 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 478 dev_kfree_skb_any(skb);
4c09eed9
JB		 479 return NETDEV_TX_OK;
480 }
481
6e909283 482 /* Fill in a Tx ring entry */
4d494cdc 483 bdp = txq->cur_tx;
c4bc44c6 484 last_bdp = bdp;
6e909283 485 status = bdp->cbd_sc;
0e702ab3 486 status &= ~BD_ENET_TX_STATS;
1da177e4 487
22f6b860 488 /* Set buffer length and buffer pointer */
9555b31e 489 bufaddr = skb->data;
6e909283 490 buflen = skb_headlen(skb);
1da177e4 491
4d494cdc
FD		 492 queue = skb_get_queue_mapping(skb);
493 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
41ef84ce 494 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 495 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 496 memcpy(txq->tx_bounce[index], skb->data, buflen);
497 bufaddr = txq->tx_bounce[index];
1da177e4 498
6b7e4008 499 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 500 swap_buffer(bufaddr, buflen);
501 }
6aa20a22 502
d6bf3143
RK		 503 /* Push the data cache so the CPM does not get stale memory data. */
504 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
505 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 506 dev_kfree_skb_any(skb);
507 if (net_ratelimit())
508 netdev_err(ndev, "Tx DMA memory map failed\n");
509 return NETDEV_TX_OK;
510 }
1da177e4 511
6e909283 512 if (nr_frags) {
c4bc44c6
KH		 513 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
514 if (IS_ERR(last_bdp))
515 return NETDEV_TX_OK;
6e909283
NA		 516 } else {
517 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
518 if (fep->bufdesc_ex) {
519 estatus = BD_ENET_TX_INT;
520 if (unlikely(skb_shinfo(skb)->tx_flags &
521 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
522 estatus |= BD_ENET_TX_TS;
523 }
524 }
525
ff43da86
FL		 526 if (fep->bufdesc_ex) {
527
528 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 529
ff43da86 530 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 531 fep->hwts_tx_en))
6605b730 532 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 533
6b7e4008 534 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213
NA		 535 estatus |= FEC_TX_BD_FTYPE(queue);
536
6e909283
NA		 537 if (skb->ip_summed == CHECKSUM_PARTIAL)
538 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
539
540 ebdp->cbd_bdu = 0;
541 ebdp->cbd_esc = estatus;
6605b730 542 }
03191656 543
4d494cdc 544 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
6e909283 545 /* Save skb pointer */
4d494cdc 546 txq->tx_skbuff[index] = skb;
6e909283
NA		 547
548 bdp->cbd_datlen = buflen;
d6bf3143 549 bdp->cbd_bufaddr = addr;
6e909283 550
fb8ef788
DFB		 551 /* Send it on its way. Tell FEC it's ready, interrupt when done,
552 * it's the last BD of the frame, and to put the CRC on the end.
553 */
6e909283 554 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
fb8ef788
DFB		 555 bdp->cbd_sc = status;
556
22f6b860 557 /* If this was the last BD in the ring, start at the beginning again. */
4d494cdc 558 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
1da177e4 559
7a2a8451
ED		 560 skb_tx_timestamp(skb);
561
c4bc44c6
KH		 562 /* Make sure the update to bdp and tx_skbuff are performed before
563 * cur_tx.
564 */
565 wmb();
4d494cdc 566 txq->cur_tx = bdp;
de5fb0a0 567
de5fb0a0 568 /* Trigger transmission start */
4d494cdc 569 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
1da177e4 570
6e909283 571 return 0;
1da177e4
LT		 572}
573
79f33912 574static int
4d494cdc
FD		 575fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
576 struct net_device *ndev,
577 struct bufdesc *bdp, int index, char *data,
578 int size, bool last_tcp, bool is_last)
61a4427b
NA		 579{
580 struct fec_enet_private *fep = netdev_priv(ndev);
61cd2ebb 581 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
befe8213 582 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 583 unsigned short status;
584 unsigned int estatus = 0;
d6bf3143 585 dma_addr_t addr;
61a4427b
NA		 586
587 status = bdp->cbd_sc;
79f33912 588 status &= ~BD_ENET_TX_STATS;
61a4427b 589
79f33912 590 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912 591
41ef84ce 592 if (((unsigned long) data) & fep->tx_align ||
6b7e4008 593 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 594 memcpy(txq->tx_bounce[index], data, size);
595 data = txq->tx_bounce[index];
79f33912 596
6b7e4008 597 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 598 swap_buffer(data, size);
599 }
600
d6bf3143
RK		 601 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
602 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 603 dev_kfree_skb_any(skb);
6e909283 604 if (net_ratelimit())
79f33912 605 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 606 return NETDEV_TX_BUSY;
607 }
608
d6bf3143
RK		 609 bdp->cbd_datlen = size;
610 bdp->cbd_bufaddr = addr;
611
79f33912 612 if (fep->bufdesc_ex) {
6b7e4008 613 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 614 estatus |= FEC_TX_BD_FTYPE(queue);
79f33912
NA		 615 if (skb->ip_summed == CHECKSUM_PARTIAL)
616 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
617 ebdp->cbd_bdu = 0;
618 ebdp->cbd_esc = estatus;
619 }
620
621 /* Handle the last BD specially */
622 if (last_tcp)
623 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
624 if (is_last) {
625 status |= BD_ENET_TX_INTR;
626 if (fep->bufdesc_ex)
627 ebdp->cbd_esc |= BD_ENET_TX_INT;
628 }
629
630 bdp->cbd_sc = status;
631
632 return 0;
633}
634
635static int
4d494cdc
FD		 636fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
637 struct sk_buff *skb, struct net_device *ndev,
638 struct bufdesc *bdp, int index)
79f33912
NA		 639{
640 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912 641 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
61cd2ebb 642 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
befe8213 643 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 644 void *bufaddr;
645 unsigned long dmabuf;
646 unsigned short status;
647 unsigned int estatus = 0;
648
649 status = bdp->cbd_sc;
650 status &= ~BD_ENET_TX_STATS;
651 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
652
4d494cdc
FD		 653 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
654 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
41ef84ce 655 if (((unsigned long)bufaddr) & fep->tx_align ||
6b7e4008 656 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 657 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
658 bufaddr = txq->tx_bounce[index];
79f33912 659
6b7e4008 660 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 661 swap_buffer(bufaddr, hdr_len);
662
663 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
664 hdr_len, DMA_TO_DEVICE);
665 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
666 dev_kfree_skb_any(skb);
667 if (net_ratelimit())
668 netdev_err(ndev, "Tx DMA memory map failed\n");
669 return NETDEV_TX_BUSY;
670 }
671 }
672
673 bdp->cbd_bufaddr = dmabuf;
674 bdp->cbd_datlen = hdr_len;
675
676 if (fep->bufdesc_ex) {
6b7e4008 677 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 678 estatus |= FEC_TX_BD_FTYPE(queue);
79f33912
NA		 679 if (skb->ip_summed == CHECKSUM_PARTIAL)
680 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
681 ebdp->cbd_bdu = 0;
682 ebdp->cbd_esc = estatus;
683 }
684
685 bdp->cbd_sc = status;
686
687 return 0;
688}
689
4d494cdc
FD		 690static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
691 struct sk_buff *skb,
692 struct net_device *ndev)
79f33912
NA		 693{
694 struct fec_enet_private *fep = netdev_priv(ndev);
695 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
696 int total_len, data_left;
4d494cdc
FD		 697 struct bufdesc *bdp = txq->cur_tx;
698 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 699 struct tso_t tso;
700 unsigned int index = 0;
701 int ret;
702
4d494cdc 703 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
79f33912
NA		 704 dev_kfree_skb_any(skb);
705 if (net_ratelimit())
706 netdev_err(ndev, "NOT enough BD for TSO!\n");
707 return NETDEV_TX_OK;
708 }
709
710 /* Protocol checksum off-load for TCP and UDP. */
711 if (fec_enet_clear_csum(skb, ndev)) {
712 dev_kfree_skb_any(skb);
713 return NETDEV_TX_OK;
714 }
715
716 /* Initialize the TSO handler, and prepare the first payload */
717 tso_start(skb, &tso);
718
719 total_len = skb->len - hdr_len;
720 while (total_len > 0) {
721 char *hdr;
722
4d494cdc 723 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
79f33912
NA		 724 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
725 total_len -= data_left;
726
727 /* prepare packet headers: MAC + IP + TCP */
4d494cdc 728 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
79f33912 729 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
4d494cdc 730 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
79f33912
NA		 731 if (ret)
732 goto err_release;
733
734 while (data_left > 0) {
735 int size;
736
737 size = min_t(int, tso.size, data_left);
4d494cdc
FD		 738 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
739 index = fec_enet_get_bd_index(txq->tx_bd_base,
740 bdp, fep);
741 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
742 bdp, index,
743 tso.data, size,
744 size == data_left,
79f33912
NA		 745 total_len == 0);
746 if (ret)
747 goto err_release;
748
749 data_left -= size;
750 tso_build_data(skb, &tso, size);
751 }
752
4d494cdc 753 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
79f33912
NA		 754 }
755
756 /* Save skb pointer */
4d494cdc 757 txq->tx_skbuff[index] = skb;
79f33912 758
79f33912 759 skb_tx_timestamp(skb);
4d494cdc 760 txq->cur_tx = bdp;
79f33912
NA		 761
762 /* Trigger transmission start */
6b7e4008 763 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
37d6017b
FD		 764 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
765 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
766 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
768 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
79f33912
NA		 769
770 return 0;
771
772err_release:
773 /* TODO: Release all used data descriptors for TSO */
774 return ret;
775}
776
777static netdev_tx_t
778fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
779{
780 struct fec_enet_private *fep = netdev_priv(ndev);
781 int entries_free;
4d494cdc
FD		 782 unsigned short queue;
783 struct fec_enet_priv_tx_q *txq;
784 struct netdev_queue *nq;
79f33912
NA		 785 int ret;
786
4d494cdc
FD		 787 queue = skb_get_queue_mapping(skb);
788 txq = fep->tx_queue[queue];
789 nq = netdev_get_tx_queue(ndev, queue);
790
79f33912 791 if (skb_is_gso(skb))
4d494cdc 792 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
79f33912 793 else
4d494cdc 794 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
6e909283
NA		 795 if (ret)
796 return ret;
61a4427b 797
4d494cdc
FD		 798 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
799 if (entries_free <= txq->tx_stop_threshold)
800 netif_tx_stop_queue(nq);
61a4427b
NA		 801
802 return NETDEV_TX_OK;
803}
804
14109a59
FL		 805/* Init RX & TX buffer descriptors
806 */
807static void fec_enet_bd_init(struct net_device *dev)
808{
809 struct fec_enet_private *fep = netdev_priv(dev);
4d494cdc
FD		 810 struct fec_enet_priv_tx_q *txq;
811 struct fec_enet_priv_rx_q *rxq;
14109a59
FL		 812 struct bufdesc *bdp;
813 unsigned int i;
59d0f746 814 unsigned int q;
14109a59 815
59d0f746
FL		 816 for (q = 0; q < fep->num_rx_queues; q++) {
817 /* Initialize the receive buffer descriptors. */
818 rxq = fep->rx_queue[q];
819 bdp = rxq->rx_bd_base;
4d494cdc 820
59d0f746 821 for (i = 0; i < rxq->rx_ring_size; i++) {
14109a59 822
59d0f746
FL		 823 /* Initialize the BD for every fragment in the page. */
824 if (bdp->cbd_bufaddr)
825 bdp->cbd_sc = BD_ENET_RX_EMPTY;
826 else
827 bdp->cbd_sc = 0;
828 bdp = fec_enet_get_nextdesc(bdp, fep, q);
829 }
830
831 /* Set the last buffer to wrap */
832 bdp = fec_enet_get_prevdesc(bdp, fep, q);
833 bdp->cbd_sc |= BD_SC_WRAP;
834
835 rxq->cur_rx = rxq->rx_bd_base;
836 }
837
838 for (q = 0; q < fep->num_tx_queues; q++) {
839 /* ...and the same for transmit */
840 txq = fep->tx_queue[q];
841 bdp = txq->tx_bd_base;
842 txq->cur_tx = bdp;
843
844 for (i = 0; i < txq->tx_ring_size; i++) {
845 /* Initialize the BD for every fragment in the page. */
14109a59 846 bdp->cbd_sc = 0;
59d0f746
FL		 847 if (txq->tx_skbuff[i]) {
848 dev_kfree_skb_any(txq->tx_skbuff[i]);
849 txq->tx_skbuff[i] = NULL;
850 }
851 bdp->cbd_bufaddr = 0;
852 bdp = fec_enet_get_nextdesc(bdp, fep, q);
853 }
854
855 /* Set the last buffer to wrap */
856 bdp = fec_enet_get_prevdesc(bdp, fep, q);
857 bdp->cbd_sc |= BD_SC_WRAP;
858 txq->dirty_tx = bdp;
14109a59 859 }
59d0f746 860}
14109a59 861
ce99d0d3
FL		 862static void fec_enet_active_rxring(struct net_device *ndev)
863{
864 struct fec_enet_private *fep = netdev_priv(ndev);
865 int i;
866
867 for (i = 0; i < fep->num_rx_queues; i++)
868 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
869}
870
59d0f746
FL		 871static void fec_enet_enable_ring(struct net_device *ndev)
872{
873 struct fec_enet_private *fep = netdev_priv(ndev);
874 struct fec_enet_priv_tx_q *txq;
875 struct fec_enet_priv_rx_q *rxq;
876 int i;
14109a59 877
59d0f746
FL		 878 for (i = 0; i < fep->num_rx_queues; i++) {
879 rxq = fep->rx_queue[i];
880 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
d543a762 881 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
14109a59 882
59d0f746
FL		 883 /* enable DMA1/2 */
884 if (i)
885 writel(RCMR_MATCHEN | RCMR_CMP(i),
886 fep->hwp + FEC_RCMR(i));
887 }
14109a59 888
59d0f746
FL		 889 for (i = 0; i < fep->num_tx_queues; i++) {
890 txq = fep->tx_queue[i];
891 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
892
893 /* enable DMA1/2 */
894 if (i)
895 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
896 fep->hwp + FEC_DMA_CFG(i));
14109a59 897 }
59d0f746 898}
14109a59 899
59d0f746
FL		 900static void fec_enet_reset_skb(struct net_device *ndev)
901{
902 struct fec_enet_private *fep = netdev_priv(ndev);
903 struct fec_enet_priv_tx_q *txq;
904 int i, j;
905
906 for (i = 0; i < fep->num_tx_queues; i++) {
907 txq = fep->tx_queue[i];
908
909 for (j = 0; j < txq->tx_ring_size; j++) {
910 if (txq->tx_skbuff[j]) {
911 dev_kfree_skb_any(txq->tx_skbuff[j]);
912 txq->tx_skbuff[j] = NULL;
913 }
914 }
915 }
14109a59
FL		 916}
917
dbc64a8e
RK		 918/*
919 * This function is called to start or restart the FEC during a link
920 * change, transmit timeout, or to reconfigure the FEC. The network
921 * packet processing for this device must be stopped before this call.
45993653 922 */
1da177e4 923static void
ef83337d 924fec_restart(struct net_device *ndev)
1da177e4 925{
c556167f 926 struct fec_enet_private *fep = netdev_priv(ndev);
4c09eed9 927 u32 val;
cd1f402c
UKK		 928 u32 temp_mac[2];
929 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 930 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 931
106c314c
FD		 932 /* Whack a reset. We should wait for this.
933 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
934 * instead of reset MAC itself.
935 */
6b7e4008 936 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 937 writel(0, fep->hwp + FEC_ECNTRL);
938 } else {
939 writel(1, fep->hwp + FEC_ECNTRL);
940 udelay(10);
941 }
1da177e4 942
45993653
UKK		 943 /*
944 * enet-mac reset will reset mac address registers too,
945 * so need to reconfigure it.
946 */
6b7e4008 947 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
45993653
UKK		 948 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
949 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
950 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
951 }
1da177e4 952
45993653 953 /* Clear any outstanding interrupt. */
e17f7fec 954 writel(0xffffffff, fep->hwp + FEC_IEVENT);
1da177e4 955
14109a59
FL		 956 fec_enet_bd_init(ndev);
957
59d0f746 958 fec_enet_enable_ring(ndev);
45993653 959
59d0f746
FL		 960 /* Reset tx SKB buffers. */
961 fec_enet_reset_skb(ndev);
97b72e43 962
45993653 963 /* Enable MII mode */
ef83337d 964 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 965 /* FD enable */
45993653
UKK		 966 writel(0x04, fep->hwp + FEC_X_CNTRL);
967 } else {
cd1f402c
UKK		 968 /* No Rcv on Xmit */
969 rcntl |= 0x02;
45993653
UKK		 970 writel(0x0, fep->hwp + FEC_X_CNTRL);
971 }
cd1f402c 972
45993653
UKK		 973 /* Set MII speed */
974 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
975
d1391930 976#if !defined(CONFIG_M5272)
18803495
GU		 977 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
978 /* set RX checksum */
979 val = readl(fep->hwp + FEC_RACC);
980 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
981 val |= FEC_RACC_OPTIONS;
982 else
983 val &= ~FEC_RACC_OPTIONS;
984 writel(val, fep->hwp + FEC_RACC);
985 }
d1391930 986#endif
4c09eed9 987
45993653
UKK		 988 /*
989 * The phy interface and speed need to get configured
990 * differently on enet-mac.
991 */
6b7e4008 992 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 993 /* Enable flow control and length check */
994 rcntl |= 0x40000000 | 0x00000020;
45993653 995
230dec61 996 /* RGMII, RMII or MII */
e813bb2b
MP		 997 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
998 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
999 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1000 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
230dec61
SG		 1001 rcntl |= (1 << 6);
1002 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 1003 rcntl |= (1 << 8);
45993653 1004 else
cd1f402c 1005 rcntl &= ~(1 << 8);
45993653 1006
230dec61
SG		 1007 /* 1G, 100M or 10M */
1008 if (fep->phy_dev) {
1009 if (fep->phy_dev->speed == SPEED_1000)
1010 ecntl |= (1 << 5);
1011 else if (fep->phy_dev->speed == SPEED_100)
1012 rcntl &= ~(1 << 9);
1013 else
1014 rcntl |= (1 << 9);
1015 }
45993653
UKK		 1016 } else {
1017#ifdef FEC_MIIGSK_ENR
6b7e4008 1018 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
8d82f219 1019 u32 cfgr;
45993653
UKK		 1020 /* disable the gasket and wait */
1021 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1022 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1023 udelay(1);
1024
1025 /*
1026 * configure the gasket:
1027 * RMII, 50 MHz, no loopback, no echo
0ca1e290 1028 * MII, 25 MHz, no loopback, no echo
45993653 1029 */
8d82f219
EB		 1030 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1031 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1032 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1033 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1034 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 1035
1036 /* re-enable the gasket */
1037 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 1038 }
45993653
UKK		 1039#endif
1040 }
baa70a5c 1041
d1391930 1042#if !defined(CONFIG_M5272)
baa70a5c
FL		 1043 /* enable pause frame*/
1044 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1045 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1046 fep->phy_dev && fep->phy_dev->pause)) {
1047 rcntl |= FEC_ENET_FCE;
1048
4c09eed9 1049 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 1050 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1051 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1052 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1053 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1054
1055 /* OPD */
1056 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1057 } else {
1058 rcntl &= ~FEC_ENET_FCE;
1059 }
d1391930 1060#endif /* !defined(CONFIG_M5272) */
baa70a5c 1061
cd1f402c 1062 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 1063
84fe6182
SW		 1064 /* Setup multicast filter. */
1065 set_multicast_list(ndev);
1066#ifndef CONFIG_M5272
1067 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1068 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1069#endif
1070
6b7e4008 1071 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61
SG		 1072 /* enable ENET endian swap */
1073 ecntl |= (1 << 8);
1074 /* enable ENET store and forward mode */
1075 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1076 }
1077
ff43da86
FL		 1078 if (fep->bufdesc_ex)
1079 ecntl |= (1 << 4);
6605b730 1080
38ae92dc 1081#ifndef CONFIG_M5272
b9eef55c
JB		 1082 /* Enable the MIB statistic event counters */
1083 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1084#endif
1085
45993653 1086 /* And last, enable the transmit and receive processing */
230dec61 1087 writel(ecntl, fep->hwp + FEC_ECNTRL);
ce99d0d3 1088 fec_enet_active_rxring(ndev);
45993653 1089
ff43da86
FL		 1090 if (fep->bufdesc_ex)
1091 fec_ptp_start_cyclecounter(ndev);
1092
45993653 1093 /* Enable interrupts we wish to service */
0c5a3aef
NA		 1094 if (fep->link)
1095 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1096 else
1097 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
d851b47b
FD		 1098
1099 /* Init the interrupt coalescing */
1100 fec_enet_itr_coal_init(ndev);
1101
45993653
UKK		 1102}
1103
1104static void
1105fec_stop(struct net_device *ndev)
1106{
1107 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 1108 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
42431dc2 1109 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
de40ed31 1110 u32 val;
45993653
UKK		 1111
1112 /* We cannot expect a graceful transmit stop without link !!! */
1113 if (fep->link) {
1114 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1115 udelay(10);
1116 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1117 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1118 }
1119
106c314c
FD		 1120 /* Whack a reset. We should wait for this.
1121 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1122 * instead of reset MAC itself.
1123 */
de40ed31
NA		 1124 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1125 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1126 writel(0, fep->hwp + FEC_ECNTRL);
1127 } else {
1128 writel(1, fep->hwp + FEC_ECNTRL);
1129 udelay(10);
1130 }
1131 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
106c314c 1132 } else {
de40ed31
NA		 1133 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1134 val = readl(fep->hwp + FEC_ECNTRL);
1135 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1136 writel(val, fep->hwp + FEC_ECNTRL);
1137
1138 if (pdata && pdata->sleep_mode_enable)
1139 pdata->sleep_mode_enable(true);
106c314c 1140 }
45993653 1141 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
230dec61
SG		 1142
1143 /* We have to keep ENET enabled to have MII interrupt stay working */
de40ed31
NA		 1144 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1145 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
230dec61 1146 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1147 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1148 }
1da177e4
LT		 1149}
1150
1151
45993653
UKK		 1152static void
1153fec_timeout(struct net_device *ndev)
1154{
1155 struct fec_enet_private *fep = netdev_priv(ndev);
1156
344756f6
RK		 1157 fec_dump(ndev);
1158
45993653
UKK		 1159 ndev->stats.tx_errors++;
1160
36cdc743 1161 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1162}
1163
36cdc743 1164static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1165{
1166 struct fec_enet_private *fep =
36cdc743 1167 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1168 struct net_device *ndev = fep->netdev;
54309fa6 1169
36cdc743
RK		 1170 rtnl_lock();
1171 if (netif_device_present(ndev) || netif_running(ndev)) {
1172 napi_disable(&fep->napi);
1173 netif_tx_lock_bh(ndev);
1174 fec_restart(ndev);
1175 netif_wake_queue(ndev);
1176 netif_tx_unlock_bh(ndev);
1177 napi_enable(&fep->napi);
54309fa6 1178 }
36cdc743 1179 rtnl_unlock();
45993653
UKK		 1180}
1181
bfd4ecdd
RK		 1182static void
1183fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1184 struct skb_shared_hwtstamps *hwtstamps)
1185{
1186 unsigned long flags;
1187 u64 ns;
1188
1189 spin_lock_irqsave(&fep->tmreg_lock, flags);
1190 ns = timecounter_cyc2time(&fep->tc, ts);
1191 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1192
1193 memset(hwtstamps, 0, sizeof(*hwtstamps));
1194 hwtstamps->hwtstamp = ns_to_ktime(ns);
1195}
1196
1da177e4 1197static void
4d494cdc 1198fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1da177e4
LT		 1199{
1200 struct fec_enet_private *fep;
a2fe37b6 1201 struct bufdesc *bdp;
0e702ab3 1202 unsigned short status;
1da177e4 1203 struct sk_buff *skb;
4d494cdc
FD		 1204 struct fec_enet_priv_tx_q *txq;
1205 struct netdev_queue *nq;
de5fb0a0 1206 int index = 0;
79f33912 1207 int entries_free;
1da177e4 1208
c556167f 1209 fep = netdev_priv(ndev);
4d494cdc
FD		 1210
1211 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1212
1213 txq = fep->tx_queue[queue_id];
1214 /* get next bdp of dirty_tx */
1215 nq = netdev_get_tx_queue(ndev, queue_id);
1216 bdp = txq->dirty_tx;
1da177e4 1217
de5fb0a0 1218 /* get next bdp of dirty_tx */
4d494cdc 1219 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
de5fb0a0 1220
c4bc44c6
KH		 1221 while (bdp != READ_ONCE(txq->cur_tx)) {
1222 /* Order the load of cur_tx and cbd_sc */
1223 rmb();
1224 status = READ_ONCE(bdp->cbd_sc);
1225 if (status & BD_ENET_TX_READY)
f0b3fbea
SH		 1226 break;
1227
a2fe37b6 1228 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
2b995f63 1229
a2fe37b6 1230 skb = txq->tx_skbuff[index];
2b995f63 1231 txq->tx_skbuff[index] = NULL;
a2fe37b6
FE		 1232 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1233 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1234 bdp->cbd_datlen, DMA_TO_DEVICE);
1235 bdp->cbd_bufaddr = 0;
1236 if (!skb) {
1237 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1238 continue;
1239 }
de5fb0a0 1240
1da177e4 1241 /* Check for errors. */
0e702ab3 1242 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1243 BD_ENET_TX_RL | BD_ENET_TX_UN |
1244 BD_ENET_TX_CSL)) {
c556167f 1245 ndev->stats.tx_errors++;
0e702ab3 1246 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1247 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1248 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1249 ndev->stats.tx_window_errors++;
0e702ab3 1250 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1251 ndev->stats.tx_aborted_errors++;
0e702ab3 1252 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1253 ndev->stats.tx_fifo_errors++;
0e702ab3 1254 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1255 ndev->stats.tx_carrier_errors++;
1da177e4 1256 } else {
c556167f 1257 ndev->stats.tx_packets++;
6e909283 1258 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1259 }
1260
ff43da86
FL		 1261 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1262 fep->bufdesc_ex) {
6605b730 1263 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1264 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1265
bfd4ecdd 1266 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
6605b730
FL		 1267 skb_tstamp_tx(skb, &shhwtstamps);
1268 }
ff43da86 1269
1da177e4
LT		 1270 /* Deferred means some collisions occurred during transmit,
1271 * but we eventually sent the packet OK.
1272 */
0e702ab3 1273 if (status & BD_ENET_TX_DEF)
c556167f 1274 ndev->stats.collisions++;
6aa20a22 1275
22f6b860 1276 /* Free the sk buffer associated with this last transmit */
1da177e4 1277 dev_kfree_skb_any(skb);
de5fb0a0 1278
c4bc44c6
KH		 1279 /* Make sure the update to bdp and tx_skbuff are performed
1280 * before dirty_tx
1281 */
1282 wmb();
4d494cdc 1283 txq->dirty_tx = bdp;
6aa20a22 1284
22f6b860 1285 /* Update pointer to next buffer descriptor to be transmitted */
4d494cdc 1286 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
6aa20a22 1287
22f6b860 1288 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1289 */
79f33912 1290 if (netif_queue_stopped(ndev)) {
4d494cdc
FD		 1291 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1292 if (entries_free >= txq->tx_wake_threshold)
1293 netif_tx_wake_queue(nq);
79f33912 1294 }
1da177e4 1295 }
ccea2968
RK		 1296
1297 /* ERR006538: Keep the transmitter going */
4d494cdc
FD		 1298 if (bdp != txq->cur_tx &&
1299 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1300 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1301}
1302
1303static void
1304fec_enet_tx(struct net_device *ndev)
1305{
1306 struct fec_enet_private *fep = netdev_priv(ndev);
1307 u16 queue_id;
1308 /* First process class A queue, then Class B and Best Effort queue */
1309 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1310 clear_bit(queue_id, &fep->work_tx);
1311 fec_enet_tx_queue(ndev, queue_id);
1312 }
1313 return;
1da177e4
LT		 1314}
1315
1b7bde6d
NA		 1316static int
1317fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1318{
1319 struct fec_enet_private *fep = netdev_priv(ndev);
1320 int off;
1321
1322 off = ((unsigned long)skb->data) & fep->rx_align;
1323 if (off)
1324 skb_reserve(skb, fep->rx_align + 1 - off);
1325
1326 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1327 FEC_ENET_RX_FRSIZE - fep->rx_align,
1328 DMA_FROM_DEVICE);
1329 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1330 if (net_ratelimit())
1331 netdev_err(ndev, "Rx DMA memory map failed\n");
1332 return -ENOMEM;
1333 }
1334
1335 return 0;
1336}
1337
1338static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310b544 1339 struct bufdesc *bdp, u32 length, bool swap)
1b7bde6d
NA		 1340{
1341 struct fec_enet_private *fep = netdev_priv(ndev);
1342 struct sk_buff *new_skb;
1343
1344 if (length > fep->rx_copybreak)
1345 return false;
1346
1347 new_skb = netdev_alloc_skb(ndev, length);
1348 if (!new_skb)
1349 return false;
1350
1351 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1352 FEC_ENET_RX_FRSIZE - fep->rx_align,
1353 DMA_FROM_DEVICE);
1310b544
LW		 1354 if (!swap)
1355 memcpy(new_skb->data, (*skb)->data, length);
1356 else
1357 swap_buffer2(new_skb->data, (*skb)->data, length);
1b7bde6d
NA		 1358 *skb = new_skb;
1359
1360 return true;
1361}
1362
1da177e4
LT		 1363/* During a receive, the cur_rx points to the current incoming buffer.
1364 * When we update through the ring, if the next incoming buffer has
1365 * not been given to the system, we just set the empty indicator,
1366 * effectively tossing the packet.
1367 */
dc975382 1368static int
4d494cdc 1369fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1da177e4 1370{
c556167f 1371 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 1372 struct fec_enet_priv_rx_q *rxq;
2e28532f 1373 struct bufdesc *bdp;
0e702ab3 1374 unsigned short status;
1b7bde6d
NA		 1375 struct sk_buff *skb_new = NULL;
1376 struct sk_buff *skb;
1da177e4
LT		 1377 ushort pkt_len;
1378 __u8 *data;
dc975382 1379 int pkt_received = 0;
cdffcf1b
JB		 1380 struct bufdesc_ex *ebdp = NULL;
1381 bool vlan_packet_rcvd = false;
1382 u16 vlan_tag;
d842a31f 1383 int index = 0;
1b7bde6d 1384 bool is_copybreak;
6b7e4008 1385 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
6aa20a22 1386
0e702ab3
GU		 1387#ifdef CONFIG_M532x
1388 flush_cache_all();
6aa20a22 1389#endif
4d494cdc
FD		 1390 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1391 rxq = fep->rx_queue[queue_id];
1da177e4 1392
1da177e4
LT		 1393 /* First, grab all of the stats for the incoming packet.
1394 * These get messed up if we get called due to a busy condition.
1395 */
4d494cdc 1396 bdp = rxq->cur_rx;
1da177e4 1397
22f6b860 1398 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1da177e4 1399
dc975382
FL		 1400 if (pkt_received >= budget)
1401 break;
1402 pkt_received++;
1403
22f6b860
SH		 1404 /* Since we have allocated space to hold a complete frame,
1405 * the last indicator should be set.
1406 */
1407 if ((status & BD_ENET_RX_LAST) == 0)
31b7720c 1408 netdev_err(ndev, "rcv is not +last\n");
1da177e4 1409
db3421c1 1410
22f6b860
SH		 1411 /* Check for errors. */
1412 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1da177e4 1413 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
c556167f 1414 ndev->stats.rx_errors++;
22f6b860
SH		 1415 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1416 /* Frame too long or too short. */
c556167f 1417 ndev->stats.rx_length_errors++;
22f6b860
SH		 1418 }
1419 if (status & BD_ENET_RX_NO) /* Frame alignment */
c556167f 1420 ndev->stats.rx_frame_errors++;
22f6b860 1421 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1422 ndev->stats.rx_crc_errors++;
22f6b860 1423 if (status & BD_ENET_RX_OV) /* FIFO overrun */
c556167f 1424 ndev->stats.rx_fifo_errors++;
1da177e4 1425 }
1da177e4 1426
22f6b860
SH		 1427 /* Report late collisions as a frame error.
1428 * On this error, the BD is closed, but we don't know what we
1429 * have in the buffer. So, just drop this frame on the floor.
1430 */
1431 if (status & BD_ENET_RX_CL) {
c556167f
UKK		 1432 ndev->stats.rx_errors++;
1433 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1434 goto rx_processing_done;
1435 }
1da177e4 1436
22f6b860 1437 /* Process the incoming frame. */
c556167f 1438 ndev->stats.rx_packets++;
22f6b860 1439 pkt_len = bdp->cbd_datlen;
c556167f 1440 ndev->stats.rx_bytes += pkt_len;
1da177e4 1441
4d494cdc 1442 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1b7bde6d 1443 skb = rxq->rx_skbuff[index];
ccdc4f19 1444
1b7bde6d
NA		 1445 /* The packet length includes FCS, but we don't want to
1446 * include that when passing upstream as it messes up
1447 * bridging applications.
1448 */
1310b544
LW		 1449 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1450 need_swap);
1b7bde6d
NA		 1451 if (!is_copybreak) {
1452 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1453 if (unlikely(!skb_new)) {
1454 ndev->stats.rx_dropped++;
1455 goto rx_processing_done;
1456 }
1457 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1458 FEC_ENET_RX_FRSIZE - fep->rx_align,
1459 DMA_FROM_DEVICE);
1460 }
1461
1462 prefetch(skb->data - NET_IP_ALIGN);
1463 skb_put(skb, pkt_len - 4);
1464 data = skb->data;
1310b544 1465 if (!is_copybreak && need_swap)
b5680e0b
SG		 1466 swap_buffer(data, pkt_len);
1467
cdffcf1b
JB		 1468 /* Extract the enhanced buffer descriptor */
1469 ebdp = NULL;
1470 if (fep->bufdesc_ex)
1471 ebdp = (struct bufdesc_ex *)bdp;
1472
1473 /* If this is a VLAN packet remove the VLAN Tag */
1474 vlan_packet_rcvd = false;
1475 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
4d494cdc 1476 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
cdffcf1b
JB		 1477 /* Push and remove the vlan tag */
1478 struct vlan_hdr *vlan_header =
1479 (struct vlan_hdr *) (data + ETH_HLEN);
1480 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
cdffcf1b
JB		 1481
1482 vlan_packet_rcvd = true;
1b7bde6d 1483
af5cbc98 1484 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1b7bde6d 1485 skb_pull(skb, VLAN_HLEN);
cdffcf1b
JB		 1486 }
1487
1b7bde6d 1488 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 1489
1b7bde6d
NA		 1490 /* Get receive timestamp from the skb */
1491 if (fep->hwts_rx_en && fep->bufdesc_ex)
1492 fec_enet_hwtstamp(fep, ebdp->ts,
1493 skb_hwtstamps(skb));
1494
1495 if (fep->bufdesc_ex &&
1496 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1497 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1498 /* don't check it */
1499 skb->ip_summed = CHECKSUM_UNNECESSARY;
1500 } else {
1501 skb_checksum_none_assert(skb);
4c09eed9 1502 }
1b7bde6d 1503 }
4c09eed9 1504
1b7bde6d
NA		 1505 /* Handle received VLAN packets */
1506 if (vlan_packet_rcvd)
1507 __vlan_hwaccel_put_tag(skb,
1508 htons(ETH_P_8021Q),
1509 vlan_tag);
cdffcf1b 1510
1b7bde6d
NA		 1511 napi_gro_receive(&fep->napi, skb);
1512
1513 if (is_copybreak) {
1514 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1515 FEC_ENET_RX_FRSIZE - fep->rx_align,
1516 DMA_FROM_DEVICE);
1517 } else {
1518 rxq->rx_skbuff[index] = skb_new;
1519 fec_enet_new_rxbdp(ndev, bdp, skb_new);
22f6b860 1520 }
f0b3fbea 1521
22f6b860
SH		 1522rx_processing_done:
1523 /* Clear the status flags for this buffer */
1524 status &= ~BD_ENET_RX_STATS;
1da177e4 1525
22f6b860
SH		 1526 /* Mark the buffer empty */
1527 status |= BD_ENET_RX_EMPTY;
1528 bdp->cbd_sc = status;
6aa20a22 1529
ff43da86
FL		 1530 if (fep->bufdesc_ex) {
1531 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1532
1533 ebdp->cbd_esc = BD_ENET_RX_INT;
1534 ebdp->cbd_prot = 0;
1535 ebdp->cbd_bdu = 0;
1536 }
6605b730 1537
22f6b860 1538 /* Update BD pointer to next entry */
4d494cdc 1539 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
36e24e2e 1540
22f6b860
SH		 1541 /* Doing this here will keep the FEC running while we process
1542 * incoming frames. On a heavily loaded network, we should be
1543 * able to keep up at the expense of system resources.
1544 */
4d494cdc 1545 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
22f6b860 1546 }
4d494cdc
FD		 1547 rxq->cur_rx = bdp;
1548 return pkt_received;
1549}
1da177e4 1550
4d494cdc
FD		 1551static int
1552fec_enet_rx(struct net_device *ndev, int budget)
1553{
1554 int pkt_received = 0;
1555 u16 queue_id;
1556 struct fec_enet_private *fep = netdev_priv(ndev);
1557
1558 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1559 clear_bit(queue_id, &fep->work_rx);
1560 pkt_received += fec_enet_rx_queue(ndev,
1561 budget - pkt_received, queue_id);
1562 }
dc975382 1563 return pkt_received;
1da177e4
LT		 1564}
1565
4d494cdc
FD		 1566static bool
1567fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1568{
1569 if (int_events == 0)
1570 return false;
1571
1572 if (int_events & FEC_ENET_RXF)
1573 fep->work_rx |= (1 << 2);
ce99d0d3
FL		 1574 if (int_events & FEC_ENET_RXF_1)
1575 fep->work_rx |= (1 << 0);
1576 if (int_events & FEC_ENET_RXF_2)
1577 fep->work_rx |= (1 << 1);
4d494cdc
FD		 1578
1579 if (int_events & FEC_ENET_TXF)
1580 fep->work_tx |= (1 << 2);
ce99d0d3
FL		 1581 if (int_events & FEC_ENET_TXF_1)
1582 fep->work_tx |= (1 << 0);
1583 if (int_events & FEC_ENET_TXF_2)
1584 fep->work_tx |= (1 << 1);
4d494cdc
FD		 1585
1586 return true;
1587}
1588
45993653
UKK		 1589static irqreturn_t
1590fec_enet_interrupt(int irq, void *dev_id)
1591{
1592 struct net_device *ndev = dev_id;
1593 struct fec_enet_private *fep = netdev_priv(ndev);
1594 uint int_events;
1595 irqreturn_t ret = IRQ_NONE;
1596
7a16807c 1597 int_events = readl(fep->hwp + FEC_IEVENT);
94191fd6 1598 writel(int_events, fep->hwp + FEC_IEVENT);
4d494cdc 1599 fec_enet_collect_events(fep, int_events);
45993653 1600
61615cd2 1601 if ((fep->work_tx || fep->work_rx) && fep->link) {
7a16807c 1602 ret = IRQ_HANDLED;
dc975382 1603
94191fd6
NA		 1604 if (napi_schedule_prep(&fep->napi)) {
1605 /* Disable the NAPI interrupts */
1606 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1607 __napi_schedule(&fep->napi);
1608 }
7a16807c 1609 }
45993653 1610
7a16807c
RK		 1611 if (int_events & FEC_ENET_MII) {
1612 ret = IRQ_HANDLED;
1613 complete(&fep->mdio_done);
1614 }
45993653 1615
81f35ffd
PZ		 1616 if (fep->ptp_clock)
1617 fec_ptp_check_pps_event(fep);
278d2404 1618
45993653
UKK		 1619 return ret;
1620}
1621
dc975382
FL		 1622static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1623{
1624 struct net_device *ndev = napi->dev;
dc975382 1625 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1626 int pkts;
1627
7a16807c 1628 pkts = fec_enet_rx(ndev, budget);
45993653 1629
de5fb0a0
FL		 1630 fec_enet_tx(ndev);
1631
dc975382
FL		 1632 if (pkts < budget) {
1633 napi_complete(napi);
1634 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1635 }
1636 return pkts;
1637}
45993653 1638
e6b043d5 1639/* ------------------------------------------------------------------------- */
0c7768a0 1640static void fec_get_mac(struct net_device *ndev)
1da177e4 1641{
c556167f 1642 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1643 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1644 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1645
49da97dc
SG		 1646 /*
1647 * try to get mac address in following order:
1648 *
1649 * 1) module parameter via kernel command line in form
1650 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1651 */
1652 iap = macaddr;
1653
ca2cc333
SG		 1654 /*
1655 * 2) from device tree data
1656 */
1657 if (!is_valid_ether_addr(iap)) {
1658 struct device_node *np = fep->pdev->dev.of_node;
1659 if (np) {
1660 const char *mac = of_get_mac_address(np);
1661 if (mac)
1662 iap = (unsigned char *) mac;
1663 }
1664 }
ca2cc333 1665
49da97dc 1666 /*
ca2cc333 1667 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1668 */
1669 if (!is_valid_ether_addr(iap)) {
1670#ifdef CONFIG_M5272
1671 if (FEC_FLASHMAC)
1672 iap = (unsigned char *)FEC_FLASHMAC;
1673#else
1674 if (pdata)
589efdc7 1675 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1676#endif
1677 }
1678
1679 /*
ca2cc333 1680 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1681 */
1682 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1683 *((__be32 *) &tmpaddr[0]) =
1684 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1685 *((__be16 *) &tmpaddr[4]) =
1686 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1687 iap = &tmpaddr[0];
1da177e4
LT		 1688 }
1689
ff5b2fab
LS		 1690 /*
1691 * 5) random mac address
1692 */
1693 if (!is_valid_ether_addr(iap)) {
1694 /* Report it and use a random ethernet address instead */
1695 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1696 eth_hw_addr_random(ndev);
1697 netdev_info(ndev, "Using random MAC address: %pM\n",
1698 ndev->dev_addr);
1699 return;
1700 }
1701
c556167f 1702 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1703
49da97dc
SG		 1704 /* Adjust MAC if using macaddr */
1705 if (iap == macaddr)
43af940c 1706 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1707}
1708
e6b043d5 1709/* ------------------------------------------------------------------------- */
1da177e4 1710
e6b043d5
BW		 1711/*
1712 * Phy section
1713 */
c556167f 1714static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1715{
c556167f 1716 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1717 struct phy_device *phy_dev = fep->phy_dev;
e6b043d5 1718 int status_change = 0;
1da177e4 1719
e6b043d5
BW		 1720 /* Prevent a state halted on mii error */
1721 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1722 phy_dev->state = PHY_RESUMING;
54309fa6 1723 return;
e6b043d5 1724 }
1da177e4 1725
8ce5624f
RK		 1726 /*
1727 * If the netdev is down, or is going down, we're not interested
1728 * in link state events, so just mark our idea of the link as down
1729 * and ignore the event.
1730 */
1731 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1732 fep->link = 0;
1733 } else if (phy_dev->link) {
d97e7497 1734 if (!fep->link) {
6ea0722f 1735 fep->link = phy_dev->link;
e6b043d5
BW		 1736 status_change = 1;
1737 }
1da177e4 1738
ef83337d
RK		 1739 if (fep->full_duplex != phy_dev->duplex) {
1740 fep->full_duplex = phy_dev->duplex;
d97e7497 1741 status_change = 1;
ef83337d 1742 }
d97e7497
LS		 1743
1744 if (phy_dev->speed != fep->speed) {
1745 fep->speed = phy_dev->speed;
1746 status_change = 1;
1747 }
1748
1749 /* if any of the above changed restart the FEC */
dbc64a8e 1750 if (status_change) {
dbc64a8e 1751 napi_disable(&fep->napi);
dbc64a8e 1752 netif_tx_lock_bh(ndev);
ef83337d 1753 fec_restart(ndev);
dbc64a8e 1754 netif_wake_queue(ndev);
6af42d42 1755 netif_tx_unlock_bh(ndev);
dbc64a8e 1756 napi_enable(&fep->napi);
dbc64a8e 1757 }
d97e7497
LS		 1758 } else {
1759 if (fep->link) {
f208ce10
RK		 1760 napi_disable(&fep->napi);
1761 netif_tx_lock_bh(ndev);
c556167f 1762 fec_stop(ndev);
f208ce10
RK		 1763 netif_tx_unlock_bh(ndev);
1764 napi_enable(&fep->napi);
8d7ed0f0 1765 fep->link = phy_dev->link;
d97e7497
LS		 1766 status_change = 1;
1767 }
1da177e4 1768 }
6aa20a22 1769
e6b043d5
BW		 1770 if (status_change)
1771 phy_print_status(phy_dev);
1772}
1da177e4 1773
e6b043d5 1774static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1775{
e6b043d5 1776 struct fec_enet_private *fep = bus->priv;
8fff755e 1777 struct device *dev = &fep->pdev->dev;
97b72e43 1778 unsigned long time_left;
8fff755e
AL		 1779 int ret = 0;
1780
1781 ret = pm_runtime_get_sync(dev);
1782 if (IS_ERR_VALUE(ret))
1783 return ret;
1da177e4 1784
e6b043d5 1785 fep->mii_timeout = 0;
97b72e43 1786 init_completion(&fep->mdio_done);
e6b043d5
BW		 1787
1788 /* start a read op */
1789 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1790 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1791 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1792
1793 /* wait for end of transfer */
97b72e43
BS		 1794 time_left = wait_for_completion_timeout(&fep->mdio_done,
1795 usecs_to_jiffies(FEC_MII_TIMEOUT));
1796 if (time_left == 0) {
1797 fep->mii_timeout = 1;
31b7720c 1798 netdev_err(fep->netdev, "MDIO read timeout\n");
8fff755e
AL		 1799 ret = -ETIMEDOUT;
1800 goto out;
1da177e4 1801 }
1da177e4 1802
8fff755e
AL		 1803 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1804
1805out:
1806 pm_runtime_mark_last_busy(dev);
1807 pm_runtime_put_autosuspend(dev);
1808
1809 return ret;
7dd6a2aa 1810}
6aa20a22 1811
e6b043d5
BW		 1812static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1813 u16 value)
1da177e4 1814{
e6b043d5 1815 struct fec_enet_private *fep = bus->priv;
8fff755e 1816 struct device *dev = &fep->pdev->dev;
97b72e43 1817 unsigned long time_left;
8fff755e
AL		 1818 int ret = 0;
1819
1820 ret = pm_runtime_get_sync(dev);
1821 if (IS_ERR_VALUE(ret))
1822 return ret;
1da177e4 1823
e6b043d5 1824 fep->mii_timeout = 0;
97b72e43 1825 init_completion(&fep->mdio_done);
1da177e4 1826
862f0982
SG		 1827 /* start a write op */
1828 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1829 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1830 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1831 fep->hwp + FEC_MII_DATA);
1832
1833 /* wait for end of transfer */
97b72e43
BS		 1834 time_left = wait_for_completion_timeout(&fep->mdio_done,
1835 usecs_to_jiffies(FEC_MII_TIMEOUT));
1836 if (time_left == 0) {
1837 fep->mii_timeout = 1;
31b7720c 1838 netdev_err(fep->netdev, "MDIO write timeout\n");
8fff755e 1839 ret = -ETIMEDOUT;
e6b043d5 1840 }
1da177e4 1841
8fff755e
AL		 1842 pm_runtime_mark_last_busy(dev);
1843 pm_runtime_put_autosuspend(dev);
1844
1845 return ret;
e6b043d5 1846}
1da177e4 1847
e8fcfcd5
NA		 1848static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1849{
1850 struct fec_enet_private *fep = netdev_priv(ndev);
1851 int ret;
1852
1853 if (enable) {
1854 ret = clk_prepare_enable(fep->clk_ahb);
1855 if (ret)
1856 return ret;
e8fcfcd5
NA		 1857 if (fep->clk_enet_out) {
1858 ret = clk_prepare_enable(fep->clk_enet_out);
1859 if (ret)
1860 goto failed_clk_enet_out;
1861 }
1862 if (fep->clk_ptp) {
91c0d987 1863 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1864 ret = clk_prepare_enable(fep->clk_ptp);
91c0d987
NA		 1865 if (ret) {
1866 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1867 goto failed_clk_ptp;
91c0d987
NA		 1868 } else {
1869 fep->ptp_clk_on = true;
1870 }
1871 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1872 }
9b5330ed
FD		 1873 if (fep->clk_ref) {
1874 ret = clk_prepare_enable(fep->clk_ref);
1875 if (ret)
1876 goto failed_clk_ref;
1877 }
e8fcfcd5
NA		 1878 } else {
1879 clk_disable_unprepare(fep->clk_ahb);
e8fcfcd5
NA		 1880 if (fep->clk_enet_out)
1881 clk_disable_unprepare(fep->clk_enet_out);
91c0d987
NA		 1882 if (fep->clk_ptp) {
1883 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1884 clk_disable_unprepare(fep->clk_ptp);
91c0d987
NA		 1885 fep->ptp_clk_on = false;
1886 mutex_unlock(&fep->ptp_clk_mutex);
1887 }
9b5330ed
FD		 1888 if (fep->clk_ref)
1889 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1890 }
1891
1892 return 0;
9b5330ed
FD		 1893
1894failed_clk_ref:
1895 if (fep->clk_ref)
1896 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1897failed_clk_ptp:
1898 if (fep->clk_enet_out)
1899 clk_disable_unprepare(fep->clk_enet_out);
1900failed_clk_enet_out:
e8fcfcd5
NA		 1901 clk_disable_unprepare(fep->clk_ahb);
1902
1903 return ret;
1904}
1905
c556167f 1906static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1907{
c556167f 1908 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1909 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1910 char mdio_bus_id[MII_BUS_ID_SIZE];
1911 char phy_name[MII_BUS_ID_SIZE + 3];
1912 int phy_id;
43af940c 1913 int dev_id = fep->dev_id;
562d2f8c 1914
418bd0d4
BW		 1915 fep->phy_dev = NULL;
1916
407066f8
UKK		 1917 if (fep->phy_node) {
1918 phy_dev = of_phy_connect(ndev, fep->phy_node,
1919 &fec_enet_adjust_link, 0,
1920 fep->phy_interface);
213a9922
NA		 1921 if (!phy_dev)
1922 return -ENODEV;
407066f8
UKK		 1923 } else {
1924 /* check for attached phy */
1925 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1926 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1927 continue;
1928 if (fep->mii_bus->phy_map[phy_id] == NULL)
1929 continue;
1930 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1931 continue;
1932 if (dev_id--)
1933 continue;
949bdd20 1934 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
407066f8
UKK		 1935 break;
1936 }
1da177e4 1937
407066f8
UKK		 1938 if (phy_id >= PHY_MAX_ADDR) {
1939 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
949bdd20 1940 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
407066f8
UKK		 1941 phy_id = 0;
1942 }
1943
1944 snprintf(phy_name, sizeof(phy_name),
1945 PHY_ID_FMT, mdio_bus_id, phy_id);
1946 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1947 fep->phy_interface);
6fcc040f
GU		 1948 }
1949
6fcc040f 1950 if (IS_ERR(phy_dev)) {
31b7720c 1951 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1952 return PTR_ERR(phy_dev);
e6b043d5 1953 }
1da177e4 1954
e6b043d5 1955 /* mask with MAC supported features */
6b7e4008 1956 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
230dec61 1957 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1958 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1959#if !defined(CONFIG_M5272)
baa70a5c 1960 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1961#endif
baa70a5c 1962 }
230dec61
SG		 1963 else
1964 phy_dev->supported &= PHY_BASIC_FEATURES;
1965
e6b043d5 1966 phy_dev->advertising = phy_dev->supported;
1da177e4 1967
e6b043d5
BW		 1968 fep->phy_dev = phy_dev;
1969 fep->link = 0;
1970 fep->full_duplex = 0;
1da177e4 1971
31b7720c
JP		 1972 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1973 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1974 fep->phy_dev->irq);
418bd0d4 1975
e6b043d5 1976 return 0;
1da177e4
LT		 1977}
1978
e6b043d5 1979static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1980{
b5680e0b 1981 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1982 struct net_device *ndev = platform_get_drvdata(pdev);
1983 struct fec_enet_private *fep = netdev_priv(ndev);
407066f8 1984 struct device_node *node;
e6b043d5 1985 int err = -ENXIO, i;
63c60732 1986 u32 mii_speed, holdtime;
6b265293 1987
b5680e0b 1988 /*
3d125f9c 1989 * The i.MX28 dual fec interfaces are not equal.
b5680e0b
SG		 1990 * Here are the differences:
1991 *
1992 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1993 * - fec0 acts as the 1588 time master while fec1 is slave
1994 * - external phys can only be configured by fec0
1995 *
1996 * That is to say fec1 can not work independently. It only works
1997 * when fec0 is working. The reason behind this design is that the
1998 * second interface is added primarily for Switch mode.
1999 *
2000 * Because of the last point above, both phys are attached on fec0
2001 * mdio interface in board design, and need to be configured by
2002 * fec0 mii_bus.
2003 */
3d125f9c 2004 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
b5680e0b 2005 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 2006 if (mii_cnt && fec0_mii_bus) {
2007 fep->mii_bus = fec0_mii_bus;
2008 mii_cnt++;
2009 return 0;
2010 }
2011 return -ENOENT;
b5680e0b
SG		 2012 }
2013
e6b043d5 2014 fep->mii_timeout = 0;
1da177e4 2015
e6b043d5
BW		 2016 /*
2017 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 2018 *
2019 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2020 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2021 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2022 * document.
e6b043d5 2023 */
63c60732 2024 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
6b7e4008 2025 if (fep->quirks & FEC_QUIRK_ENET_MAC)
63c60732
UKK		 2026 mii_speed--;
2027 if (mii_speed > 63) {
2028 dev_err(&pdev->dev,
2029 "fec clock (%lu) to fast to get right mii speed\n",
2030 clk_get_rate(fep->clk_ipg));
2031 err = -EINVAL;
2032 goto err_out;
2033 }
2034
2035 /*
2036 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2037 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2038 * versions are RAZ there, so just ignore the difference and write the
2039 * register always.
2040 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2041 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2042 * output.
2043 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2044 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2045 * holdtime cannot result in a value greater than 3.
2046 */
2047 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2048
2049 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2050
e6b043d5 2051 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 2052
e6b043d5
BW		 2053 fep->mii_bus = mdiobus_alloc();
2054 if (fep->mii_bus == NULL) {
2055 err = -ENOMEM;
2056 goto err_out;
1da177e4
LT		 2057 }
2058
e6b043d5
BW		 2059 fep->mii_bus->name = "fec_enet_mii_bus";
2060 fep->mii_bus->read = fec_enet_mdio_read;
2061 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 2062 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2063 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 2064 fep->mii_bus->priv = fep;
2065 fep->mii_bus->parent = &pdev->dev;
2066
2067 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2068 if (!fep->mii_bus->irq) {
2069 err = -ENOMEM;
2070 goto err_out_free_mdiobus;
1da177e4
LT		 2071 }
2072
e6b043d5
BW		 2073 for (i = 0; i < PHY_MAX_ADDR; i++)
2074 fep->mii_bus->irq[i] = PHY_POLL;
1da177e4 2075
407066f8
UKK		 2076 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2077 if (node) {
2078 err = of_mdiobus_register(fep->mii_bus, node);
2079 of_node_put(node);
2080 } else {
2081 err = mdiobus_register(fep->mii_bus);
2082 }
2083
2084 if (err)
e6b043d5 2085 goto err_out_free_mdio_irq;
1da177e4 2086
e163cc97
LW		 2087 mii_cnt++;
2088
b5680e0b 2089 /* save fec0 mii_bus */
3d125f9c 2090 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
b5680e0b
SG		 2091 fec0_mii_bus = fep->mii_bus;
2092
e6b043d5 2093 return 0;
1da177e4 2094
e6b043d5
BW		 2095err_out_free_mdio_irq:
2096 kfree(fep->mii_bus->irq);
2097err_out_free_mdiobus:
2098 mdiobus_free(fep->mii_bus);
2099err_out:
2100 return err;
1da177e4
LT		 2101}
2102
e6b043d5 2103static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 2104{
e163cc97
LW		 2105 if (--mii_cnt == 0) {
2106 mdiobus_unregister(fep->mii_bus);
2107 kfree(fep->mii_bus->irq);
2108 mdiobus_free(fep->mii_bus);
2109 }
1da177e4
LT		 2110}
2111
c556167f 2112static int fec_enet_get_settings(struct net_device *ndev,
e6b043d5 2113 struct ethtool_cmd *cmd)
1da177e4 2114{
c556167f 2115 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2116 struct phy_device *phydev = fep->phy_dev;
1da177e4 2117
e6b043d5
BW		 2118 if (!phydev)
2119 return -ENODEV;
1da177e4 2120
e6b043d5 2121 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 2122}
2123
c556167f 2124static int fec_enet_set_settings(struct net_device *ndev,
e6b043d5 2125 struct ethtool_cmd *cmd)
1da177e4 2126{
c556167f 2127 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2128 struct phy_device *phydev = fep->phy_dev;
1da177e4 2129
e6b043d5
BW		 2130 if (!phydev)
2131 return -ENODEV;
1da177e4 2132
e6b043d5 2133 return phy_ethtool_sset(phydev, cmd);
1da177e4
LT		 2134}
2135
c556167f 2136static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 2137 struct ethtool_drvinfo *info)
1da177e4 2138{
c556167f 2139 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 2140
7826d43f
JP		 2141 strlcpy(info->driver, fep->pdev->dev.driver->name,
2142 sizeof(info->driver));
2143 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2144 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 2145}
2146
db65f35f
PR		 2147static int fec_enet_get_regs_len(struct net_device *ndev)
2148{
2149 struct fec_enet_private *fep = netdev_priv(ndev);
2150 struct resource *r;
2151 int s = 0;
2152
2153 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2154 if (r)
2155 s = resource_size(r);
2156
2157 return s;
2158}
2159
2160/* List of registers that can be safety be read to dump them with ethtool */
2161#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2162 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
2163 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
2164static u32 fec_enet_register_offset[] = {
2165 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2166 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2167 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2168 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2169 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2170 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2171 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2172 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2173 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2174 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2175 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2176 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2177 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2178 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2179 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2180 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2181 RMON_T_P_GTE2048, RMON_T_OCTETS,
2182 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2183 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2184 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2185 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2186 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2187 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2188 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2189 RMON_R_P_GTE2048, RMON_R_OCTETS,
2190 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2191 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2192};
2193#else
2194static u32 fec_enet_register_offset[] = {
2195 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2196 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2197 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2198 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2199 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2200 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2201 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2202 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2203 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2204};
2205#endif
2206
2207static void fec_enet_get_regs(struct net_device *ndev,
2208 struct ethtool_regs *regs, void *regbuf)
2209{
2210 struct fec_enet_private *fep = netdev_priv(ndev);
2211 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2212 u32 *buf = (u32 *)regbuf;
2213 u32 i, off;
2214
2215 memset(buf, 0, regs->len);
2216
2217 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2218 off = fec_enet_register_offset[i] / 4;
2219 buf[off] = readl(&theregs[off]);
2220 }
2221}
2222
5ebae489
FL		 2223static int fec_enet_get_ts_info(struct net_device *ndev,
2224 struct ethtool_ts_info *info)
2225{
2226 struct fec_enet_private *fep = netdev_priv(ndev);
2227
2228 if (fep->bufdesc_ex) {
2229
2230 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2231 SOF_TIMESTAMPING_RX_SOFTWARE |
2232 SOF_TIMESTAMPING_SOFTWARE |
2233 SOF_TIMESTAMPING_TX_HARDWARE |
2234 SOF_TIMESTAMPING_RX_HARDWARE |
2235 SOF_TIMESTAMPING_RAW_HARDWARE;
2236 if (fep->ptp_clock)
2237 info->phc_index = ptp_clock_index(fep->ptp_clock);
2238 else
2239 info->phc_index = -1;
2240
2241 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2242 (1 << HWTSTAMP_TX_ON);
2243
2244 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2245 (1 << HWTSTAMP_FILTER_ALL);
2246 return 0;
2247 } else {
2248 return ethtool_op_get_ts_info(ndev, info);
2249 }
2250}
2251
d1391930
GR		 2252#if !defined(CONFIG_M5272)
2253
baa70a5c
FL		 2254static void fec_enet_get_pauseparam(struct net_device *ndev,
2255 struct ethtool_pauseparam *pause)
2256{
2257 struct fec_enet_private *fep = netdev_priv(ndev);
2258
2259 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2260 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2261 pause->rx_pause = pause->tx_pause;
2262}
2263
2264static int fec_enet_set_pauseparam(struct net_device *ndev,
2265 struct ethtool_pauseparam *pause)
2266{
2267 struct fec_enet_private *fep = netdev_priv(ndev);
2268
0b146ca8
RK		 2269 if (!fep->phy_dev)
2270 return -ENODEV;
2271
baa70a5c
FL		 2272 if (pause->tx_pause != pause->rx_pause) {
2273 netdev_info(ndev,
2274 "hardware only support enable/disable both tx and rx");
2275 return -EINVAL;
2276 }
2277
2278 fep->pause_flag = 0;
2279
2280 /* tx pause must be same as rx pause */
2281 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2282 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2283
2284 if (pause->rx_pause || pause->autoneg) {
2285 fep->phy_dev->supported |= ADVERTISED_Pause;
2286 fep->phy_dev->advertising |= ADVERTISED_Pause;
2287 } else {
2288 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2289 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2290 }
2291
2292 if (pause->autoneg) {
2293 if (netif_running(ndev))
2294 fec_stop(ndev);
2295 phy_start_aneg(fep->phy_dev);
2296 }
dbc64a8e 2297 if (netif_running(ndev)) {
dbc64a8e 2298 napi_disable(&fep->napi);
dbc64a8e 2299 netif_tx_lock_bh(ndev);
ef83337d 2300 fec_restart(ndev);
dbc64a8e 2301 netif_wake_queue(ndev);
6af42d42 2302 netif_tx_unlock_bh(ndev);
dbc64a8e 2303 napi_enable(&fep->napi);
dbc64a8e 2304 }
baa70a5c
FL		 2305
2306 return 0;
2307}
2308
38ae92dc
CH		 2309static const struct fec_stat {
2310 char name[ETH_GSTRING_LEN];
2311 u16 offset;
2312} fec_stats[] = {
2313 /* RMON TX */
2314 { "tx_dropped", RMON_T_DROP },
2315 { "tx_packets", RMON_T_PACKETS },
2316 { "tx_broadcast", RMON_T_BC_PKT },
2317 { "tx_multicast", RMON_T_MC_PKT },
2318 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2319 { "tx_undersize", RMON_T_UNDERSIZE },
2320 { "tx_oversize", RMON_T_OVERSIZE },
2321 { "tx_fragment", RMON_T_FRAG },
2322 { "tx_jabber", RMON_T_JAB },
2323 { "tx_collision", RMON_T_COL },
2324 { "tx_64byte", RMON_T_P64 },
2325 { "tx_65to127byte", RMON_T_P65TO127 },
2326 { "tx_128to255byte", RMON_T_P128TO255 },
2327 { "tx_256to511byte", RMON_T_P256TO511 },
2328 { "tx_512to1023byte", RMON_T_P512TO1023 },
2329 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2330 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2331 { "tx_octets", RMON_T_OCTETS },
2332
2333 /* IEEE TX */
2334 { "IEEE_tx_drop", IEEE_T_DROP },
2335 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2336 { "IEEE_tx_1col", IEEE_T_1COL },
2337 { "IEEE_tx_mcol", IEEE_T_MCOL },
2338 { "IEEE_tx_def", IEEE_T_DEF },
2339 { "IEEE_tx_lcol", IEEE_T_LCOL },
2340 { "IEEE_tx_excol", IEEE_T_EXCOL },
2341 { "IEEE_tx_macerr", IEEE_T_MACERR },
2342 { "IEEE_tx_cserr", IEEE_T_CSERR },
2343 { "IEEE_tx_sqe", IEEE_T_SQE },
2344 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2345 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2346
2347 /* RMON RX */
2348 { "rx_packets", RMON_R_PACKETS },
2349 { "rx_broadcast", RMON_R_BC_PKT },
2350 { "rx_multicast", RMON_R_MC_PKT },
2351 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2352 { "rx_undersize", RMON_R_UNDERSIZE },
2353 { "rx_oversize", RMON_R_OVERSIZE },
2354 { "rx_fragment", RMON_R_FRAG },
2355 { "rx_jabber", RMON_R_JAB },
2356 { "rx_64byte", RMON_R_P64 },
2357 { "rx_65to127byte", RMON_R_P65TO127 },
2358 { "rx_128to255byte", RMON_R_P128TO255 },
2359 { "rx_256to511byte", RMON_R_P256TO511 },
2360 { "rx_512to1023byte", RMON_R_P512TO1023 },
2361 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2362 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2363 { "rx_octets", RMON_R_OCTETS },
2364
2365 /* IEEE RX */
2366 { "IEEE_rx_drop", IEEE_R_DROP },
2367 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2368 { "IEEE_rx_crc", IEEE_R_CRC },
2369 { "IEEE_rx_align", IEEE_R_ALIGN },
2370 { "IEEE_rx_macerr", IEEE_R_MACERR },
2371 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2372 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2373};
2374
2375static void fec_enet_get_ethtool_stats(struct net_device *dev,
2376 struct ethtool_stats *stats, u64 *data)
2377{
2378 struct fec_enet_private *fep = netdev_priv(dev);
2379 int i;
2380
2381 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2382 data[i] = readl(fep->hwp + fec_stats[i].offset);
2383}
2384
2385static void fec_enet_get_strings(struct net_device *netdev,
2386 u32 stringset, u8 *data)
2387{
2388 int i;
2389 switch (stringset) {
2390 case ETH_SS_STATS:
2391 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2392 memcpy(data + i * ETH_GSTRING_LEN,
2393 fec_stats[i].name, ETH_GSTRING_LEN);
2394 break;
2395 }
2396}
2397
2398static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2399{
2400 switch (sset) {
2401 case ETH_SS_STATS:
2402 return ARRAY_SIZE(fec_stats);
2403 default:
2404 return -EOPNOTSUPP;
2405 }
2406}
d1391930 2407#endif /* !defined(CONFIG_M5272) */
38ae92dc 2408
32bc9b46
CH		 2409static int fec_enet_nway_reset(struct net_device *dev)
2410{
2411 struct fec_enet_private *fep = netdev_priv(dev);
2412 struct phy_device *phydev = fep->phy_dev;
2413
2414 if (!phydev)
2415 return -ENODEV;
2416
2417 return genphy_restart_aneg(phydev);
2418}
2419
d851b47b
FD		 2420/* ITR clock source is enet system clock (clk_ahb).
2421 * TCTT unit is cycle_ns * 64 cycle
2422 * So, the ICTT value = X us / (cycle_ns * 64)
2423 */
2424static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2425{
2426 struct fec_enet_private *fep = netdev_priv(ndev);
2427
2428 return us * (fep->itr_clk_rate / 64000) / 1000;
2429}
2430
2431/* Set threshold for interrupt coalescing */
2432static void fec_enet_itr_coal_set(struct net_device *ndev)
2433{
2434 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2435 int rx_itr, tx_itr;
2436
6b7e4008 2437 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2438 return;
2439
2440 /* Must be greater than zero to avoid unpredictable behavior */
2441 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2442 !fep->tx_time_itr || !fep->tx_pkts_itr)
2443 return;
2444
2445 /* Select enet system clock as Interrupt Coalescing
2446 * timer Clock Source
2447 */
2448 rx_itr = FEC_ITR_CLK_SEL;
2449 tx_itr = FEC_ITR_CLK_SEL;
2450
2451 /* set ICFT and ICTT */
2452 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2453 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2454 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2455 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2456
2457 rx_itr |= FEC_ITR_EN;
2458 tx_itr |= FEC_ITR_EN;
2459
2460 writel(tx_itr, fep->hwp + FEC_TXIC0);
2461 writel(rx_itr, fep->hwp + FEC_RXIC0);
2462 writel(tx_itr, fep->hwp + FEC_TXIC1);
2463 writel(rx_itr, fep->hwp + FEC_RXIC1);
2464 writel(tx_itr, fep->hwp + FEC_TXIC2);
2465 writel(rx_itr, fep->hwp + FEC_RXIC2);
2466}
2467
2468static int
2469fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2470{
2471 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b 2472
6b7e4008 2473 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2474 return -EOPNOTSUPP;
2475
2476 ec->rx_coalesce_usecs = fep->rx_time_itr;
2477 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2478
2479 ec->tx_coalesce_usecs = fep->tx_time_itr;
2480 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2481
2482 return 0;
2483}
2484
2485static int
2486fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2487{
2488 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2489 unsigned int cycle;
2490
6b7e4008 2491 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2492 return -EOPNOTSUPP;
2493
2494 if (ec->rx_max_coalesced_frames > 255) {
2495 pr_err("Rx coalesced frames exceed hardware limiation");
2496 return -EINVAL;
2497 }
2498
2499 if (ec->tx_max_coalesced_frames > 255) {
2500 pr_err("Tx coalesced frame exceed hardware limiation");
2501 return -EINVAL;
2502 }
2503
2504 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2505 if (cycle > 0xFFFF) {
2506 pr_err("Rx coalesed usec exceeed hardware limiation");
2507 return -EINVAL;
2508 }
2509
2510 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2511 if (cycle > 0xFFFF) {
2512 pr_err("Rx coalesed usec exceeed hardware limiation");
2513 return -EINVAL;
2514 }
2515
2516 fep->rx_time_itr = ec->rx_coalesce_usecs;
2517 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2518
2519 fep->tx_time_itr = ec->tx_coalesce_usecs;
2520 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2521
2522 fec_enet_itr_coal_set(ndev);
2523
2524 return 0;
2525}
2526
2527static void fec_enet_itr_coal_init(struct net_device *ndev)
2528{
2529 struct ethtool_coalesce ec;
2530
2531 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2532 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2533
2534 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2535 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2536
2537 fec_enet_set_coalesce(ndev, &ec);
2538}
2539
1b7bde6d
NA		 2540static int fec_enet_get_tunable(struct net_device *netdev,
2541 const struct ethtool_tunable *tuna,
2542 void *data)
2543{
2544 struct fec_enet_private *fep = netdev_priv(netdev);
2545 int ret = 0;
2546
2547 switch (tuna->id) {
2548 case ETHTOOL_RX_COPYBREAK:
2549 *(u32 *)data = fep->rx_copybreak;
2550 break;
2551 default:
2552 ret = -EINVAL;
2553 break;
2554 }
2555
2556 return ret;
2557}
2558
2559static int fec_enet_set_tunable(struct net_device *netdev,
2560 const struct ethtool_tunable *tuna,
2561 const void *data)
2562{
2563 struct fec_enet_private *fep = netdev_priv(netdev);
2564 int ret = 0;
2565
2566 switch (tuna->id) {
2567 case ETHTOOL_RX_COPYBREAK:
2568 fep->rx_copybreak = *(u32 *)data;
2569 break;
2570 default:
2571 ret = -EINVAL;
2572 break;
2573 }
2574
2575 return ret;
2576}
2577
de40ed31
NA		 2578static void
2579fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2580{
2581 struct fec_enet_private *fep = netdev_priv(ndev);
2582
2583 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2584 wol->supported = WAKE_MAGIC;
2585 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2586 } else {
2587 wol->supported = wol->wolopts = 0;
2588 }
2589}
2590
2591static int
2592fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2593{
2594 struct fec_enet_private *fep = netdev_priv(ndev);
2595
2596 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2597 return -EINVAL;
2598
2599 if (wol->wolopts & ~WAKE_MAGIC)
2600 return -EINVAL;
2601
2602 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2603 if (device_may_wakeup(&ndev->dev)) {
2604 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2605 if (fep->irq[0] > 0)
2606 enable_irq_wake(fep->irq[0]);
2607 } else {
2608 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2609 if (fep->irq[0] > 0)
2610 disable_irq_wake(fep->irq[0]);
2611 }
2612
2613 return 0;
2614}
2615
9b07be4b 2616static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5
BW		 2617 .get_settings = fec_enet_get_settings,
2618 .set_settings = fec_enet_set_settings,
2619 .get_drvinfo = fec_enet_get_drvinfo,
db65f35f
PR		 2620 .get_regs_len = fec_enet_get_regs_len,
2621 .get_regs = fec_enet_get_regs,
32bc9b46 2622 .nway_reset = fec_enet_nway_reset,
c1d7c48f 2623 .get_link = ethtool_op_get_link,
d851b47b
FD		 2624 .get_coalesce = fec_enet_get_coalesce,
2625 .set_coalesce = fec_enet_set_coalesce,
38ae92dc 2626#ifndef CONFIG_M5272
c1d7c48f
RK		 2627 .get_pauseparam = fec_enet_get_pauseparam,
2628 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2629 .get_strings = fec_enet_get_strings,
c1d7c48f 2630 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2631 .get_sset_count = fec_enet_get_sset_count,
2632#endif
c1d7c48f 2633 .get_ts_info = fec_enet_get_ts_info,
1b7bde6d
NA		 2634 .get_tunable = fec_enet_get_tunable,
2635 .set_tunable = fec_enet_set_tunable,
de40ed31
NA		 2636 .get_wol = fec_enet_get_wol,
2637 .set_wol = fec_enet_set_wol,
e6b043d5 2638};
1da177e4 2639
c556167f 2640static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2641{
c556167f 2642 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2643 struct phy_device *phydev = fep->phy_dev;
1da177e4 2644
c556167f 2645 if (!netif_running(ndev))
e6b043d5 2646 return -EINVAL;
1da177e4 2647
e6b043d5
BW		 2648 if (!phydev)
2649 return -ENODEV;
2650
1d5244d0
BH		 2651 if (fep->bufdesc_ex) {
2652 if (cmd == SIOCSHWTSTAMP)
2653 return fec_ptp_set(ndev, rq);
2654 if (cmd == SIOCGHWTSTAMP)
2655 return fec_ptp_get(ndev, rq);
2656 }
ff43da86 2657
28b04113 2658 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2659}
2660
c556167f 2661static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2662{
c556167f 2663 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2664 unsigned int i;
f0b3fbea
SH		 2665 struct sk_buff *skb;
2666 struct bufdesc *bdp;
4d494cdc
FD		 2667 struct fec_enet_priv_tx_q *txq;
2668 struct fec_enet_priv_rx_q *rxq;
59d0f746
FL		 2669 unsigned int q;
2670
2671 for (q = 0; q < fep->num_rx_queues; q++) {
2672 rxq = fep->rx_queue[q];
2673 bdp = rxq->rx_bd_base;
2674 for (i = 0; i < rxq->rx_ring_size; i++) {
2675 skb = rxq->rx_skbuff[i];
2676 rxq->rx_skbuff[i] = NULL;
2677 if (skb) {
2678 dma_unmap_single(&fep->pdev->dev,
2679 bdp->cbd_bufaddr,
b64bf4b7 2680 FEC_ENET_RX_FRSIZE - fep->rx_align,
59d0f746
FL		 2681 DMA_FROM_DEVICE);
2682 dev_kfree_skb(skb);
2683 }
2684 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2685 }
2686 }
4d494cdc 2687
59d0f746
FL		 2688 for (q = 0; q < fep->num_tx_queues; q++) {
2689 txq = fep->tx_queue[q];
2690 bdp = txq->tx_bd_base;
2691 for (i = 0; i < txq->tx_ring_size; i++) {
2692 kfree(txq->tx_bounce[i]);
2693 txq->tx_bounce[i] = NULL;
2694 skb = txq->tx_skbuff[i];
2695 txq->tx_skbuff[i] = NULL;
f0b3fbea 2696 dev_kfree_skb(skb);
730ee360 2697 }
f0b3fbea 2698 }
59d0f746 2699}
f0b3fbea 2700
59d0f746
FL		 2701static void fec_enet_free_queue(struct net_device *ndev)
2702{
2703 struct fec_enet_private *fep = netdev_priv(ndev);
2704 int i;
2705 struct fec_enet_priv_tx_q *txq;
2706
2707 for (i = 0; i < fep->num_tx_queues; i++)
2708 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2709 txq = fep->tx_queue[i];
2710 dma_free_coherent(NULL,
2711 txq->tx_ring_size * TSO_HEADER_SIZE,
2712 txq->tso_hdrs,
2713 txq->tso_hdrs_dma);
2714 }
2715
2716 for (i = 0; i < fep->num_rx_queues; i++)
1b4b32c6 2717 kfree(fep->rx_queue[i]);
59d0f746 2718 for (i = 0; i < fep->num_tx_queues; i++)
1b4b32c6 2719 kfree(fep->tx_queue[i]);
59d0f746
FL		 2720}
2721
2722static int fec_enet_alloc_queue(struct net_device *ndev)
2723{
2724 struct fec_enet_private *fep = netdev_priv(ndev);
2725 int i;
2726 int ret = 0;
2727 struct fec_enet_priv_tx_q *txq;
2728
2729 for (i = 0; i < fep->num_tx_queues; i++) {
2730 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2731 if (!txq) {
2732 ret = -ENOMEM;
2733 goto alloc_failed;
2734 }
2735
2736 fep->tx_queue[i] = txq;
2737 txq->tx_ring_size = TX_RING_SIZE;
2738 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2739
2740 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2741 txq->tx_wake_threshold =
2742 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2743
2744 txq->tso_hdrs = dma_alloc_coherent(NULL,
2745 txq->tx_ring_size * TSO_HEADER_SIZE,
2746 &txq->tso_hdrs_dma,
2747 GFP_KERNEL);
2748 if (!txq->tso_hdrs) {
2749 ret = -ENOMEM;
2750 goto alloc_failed;
2751 }
8b7c9efa 2752 }
59d0f746
FL		 2753
2754 for (i = 0; i < fep->num_rx_queues; i++) {
2755 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2756 GFP_KERNEL);
2757 if (!fep->rx_queue[i]) {
2758 ret = -ENOMEM;
2759 goto alloc_failed;
2760 }
2761
2762 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2763 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2764 }
2765 return ret;
2766
2767alloc_failed:
2768 fec_enet_free_queue(ndev);
2769 return ret;
f0b3fbea
SH		 2770}
2771
59d0f746
FL		 2772static int
2773fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
f0b3fbea 2774{
c556167f 2775 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2776 unsigned int i;
f0b3fbea
SH		 2777 struct sk_buff *skb;
2778 struct bufdesc *bdp;
4d494cdc 2779 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2780
59d0f746 2781 rxq = fep->rx_queue[queue];
4d494cdc
FD		 2782 bdp = rxq->rx_bd_base;
2783 for (i = 0; i < rxq->rx_ring_size; i++) {
b72061a3 2784 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2785 if (!skb)
2786 goto err_alloc;
f0b3fbea 2787
1b7bde6d 2788 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
730ee360 2789 dev_kfree_skb(skb);
ffdce2cc 2790 goto err_alloc;
d842a31f 2791 }
730ee360 2792
4d494cdc 2793 rxq->rx_skbuff[i] = skb;
f0b3fbea 2794 bdp->cbd_sc = BD_ENET_RX_EMPTY;
ff43da86
FL		 2795
2796 if (fep->bufdesc_ex) {
2797 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2798 ebdp->cbd_esc = BD_ENET_RX_INT;
2799 }
2800
59d0f746 2801 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
f0b3fbea
SH		 2802 }
2803
2804 /* Set the last buffer to wrap. */
59d0f746 2805 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
f0b3fbea 2806 bdp->cbd_sc |= BD_SC_WRAP;
59d0f746 2807 return 0;
f0b3fbea 2808
59d0f746
FL		 2809 err_alloc:
2810 fec_enet_free_buffers(ndev);
2811 return -ENOMEM;
2812}
2813
2814static int
2815fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2816{
2817 struct fec_enet_private *fep = netdev_priv(ndev);
2818 unsigned int i;
2819 struct bufdesc *bdp;
2820 struct fec_enet_priv_tx_q *txq;
2821
2822 txq = fep->tx_queue[queue];
4d494cdc
FD		 2823 bdp = txq->tx_bd_base;
2824 for (i = 0; i < txq->tx_ring_size; i++) {
2825 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2826 if (!txq->tx_bounce[i])
ffdce2cc 2827 goto err_alloc;
f0b3fbea
SH		 2828
2829 bdp->cbd_sc = 0;
2830 bdp->cbd_bufaddr = 0;
6605b730 2831
ff43da86
FL		 2832 if (fep->bufdesc_ex) {
2833 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
96d2222b 2834 ebdp->cbd_esc = BD_ENET_TX_INT;
ff43da86
FL		 2835 }
2836
59d0f746 2837 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
f0b3fbea
SH		 2838 }
2839
2840 /* Set the last buffer to wrap. */
59d0f746 2841 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
f0b3fbea
SH		 2842 bdp->cbd_sc |= BD_SC_WRAP;
2843
2844 return 0;
ffdce2cc
RK		 2845
2846 err_alloc:
2847 fec_enet_free_buffers(ndev);
2848 return -ENOMEM;
f0b3fbea
SH		 2849}
2850
59d0f746
FL		 2851static int fec_enet_alloc_buffers(struct net_device *ndev)
2852{
2853 struct fec_enet_private *fep = netdev_priv(ndev);
2854 unsigned int i;
2855
2856 for (i = 0; i < fep->num_rx_queues; i++)
2857 if (fec_enet_alloc_rxq_buffers(ndev, i))
2858 return -ENOMEM;
2859
2860 for (i = 0; i < fep->num_tx_queues; i++)
2861 if (fec_enet_alloc_txq_buffers(ndev, i))
2862 return -ENOMEM;
2863 return 0;
2864}
2865
1da177e4 2866static int
c556167f 2867fec_enet_open(struct net_device *ndev)
1da177e4 2868{
c556167f 2869 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2870 int ret;
1da177e4 2871
8fff755e
AL		 2872 ret = pm_runtime_get_sync(&fep->pdev->dev);
2873 if (IS_ERR_VALUE(ret))
2874 return ret;
2875
5bbde4d2 2876 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2877 ret = fec_enet_clk_enable(ndev, true);
2878 if (ret)
8fff755e 2879 goto clk_enable;
e8fcfcd5 2880
1da177e4
LT		 2881 /* I should reset the ring buffers here, but I don't yet know
2882 * a simple way to do that.
2883 */
1da177e4 2884
c556167f 2885 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea 2886 if (ret)
681d2421 2887 goto err_enet_alloc;
f0b3fbea 2888
55dd2753
NA		 2889 /* Init MAC prior to mii bus probe */
2890 fec_restart(ndev);
2891
418bd0d4 2892 /* Probe and connect to PHY when open the interface */
c556167f 2893 ret = fec_enet_mii_probe(ndev);
681d2421
FE		 2894 if (ret)
2895 goto err_enet_mii_probe;
ce5eaf02
RK		 2896
2897 napi_enable(&fep->napi);
e6b043d5 2898 phy_start(fep->phy_dev);
4d494cdc
FD		 2899 netif_tx_start_all_queues(ndev);
2900
de40ed31
NA		 2901 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2902 FEC_WOL_FLAG_ENABLE);
2903
22f6b860 2904 return 0;
681d2421
FE		 2905
2906err_enet_mii_probe:
2907 fec_enet_free_buffers(ndev);
2908err_enet_alloc:
2909 fec_enet_clk_enable(ndev, false);
8fff755e
AL		 2910clk_enable:
2911 pm_runtime_mark_last_busy(&fep->pdev->dev);
2912 pm_runtime_put_autosuspend(&fep->pdev->dev);
681d2421
FE		 2913 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2914 return ret;
1da177e4
LT		 2915}
2916
2917static int
c556167f 2918fec_enet_close(struct net_device *ndev)
1da177e4 2919{
c556167f 2920 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2921
d76cfae9
RK		 2922 phy_stop(fep->phy_dev);
2923
31a6de34
RK		 2924 if (netif_device_present(ndev)) {
2925 napi_disable(&fep->napi);
2926 netif_tx_disable(ndev);
8bbbd3c1 2927 fec_stop(ndev);
31a6de34 2928 }
1da177e4 2929
635cf17c 2930 phy_disconnect(fep->phy_dev);
0b146ca8 2931 fep->phy_dev = NULL;
418bd0d4 2932
e8fcfcd5 2933 fec_enet_clk_enable(ndev, false);
5bbde4d2 2934 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
8fff755e
AL		 2935 pm_runtime_mark_last_busy(&fep->pdev->dev);
2936 pm_runtime_put_autosuspend(&fep->pdev->dev);
2937
db8880bc 2938 fec_enet_free_buffers(ndev);
f0b3fbea 2939
1da177e4
LT		 2940 return 0;
2941}
2942
1da177e4
LT		 2943/* Set or clear the multicast filter for this adaptor.
2944 * Skeleton taken from sunlance driver.
2945 * The CPM Ethernet implementation allows Multicast as well as individual
2946 * MAC address filtering. Some of the drivers check to make sure it is
2947 * a group multicast address, and discard those that are not. I guess I
2948 * will do the same for now, but just remove the test if you want
2949 * individual filtering as well (do the upper net layers want or support
2950 * this kind of feature?).
2951 */
2952
2953#define HASH_BITS 6 /* #bits in hash */
2954#define CRC32_POLY 0xEDB88320
2955
c556167f 2956static void set_multicast_list(struct net_device *ndev)
1da177e4 2957{
c556167f 2958 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2959 struct netdev_hw_addr *ha;
48e2f183 2960 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2961 unsigned char hash;
2962
c556167f 2963 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2964 tmp = readl(fep->hwp + FEC_R_CNTRL);
2965 tmp |= 0x8;
2966 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2967 return;
2968 }
1da177e4 2969
4e831836
SH		 2970 tmp = readl(fep->hwp + FEC_R_CNTRL);
2971 tmp &= ~0x8;
2972 writel(tmp, fep->hwp + FEC_R_CNTRL);
2973
c556167f 2974 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2975 /* Catch all multicast addresses, so set the
2976 * filter to all 1's
2977 */
2978 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2979 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2980
2981 return;
2982 }
2983
2984 /* Clear filter and add the addresses in hash register
2985 */
2986 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2987 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2988
c556167f 2989 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2990 /* calculate crc32 value of mac address */
2991 crc = 0xffffffff;
2992
c556167f 2993 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2994 data = ha->addr[i];
4e831836
SH		 2995 for (bit = 0; bit < 8; bit++, data >>= 1) {
2996 crc = (crc >> 1) ^
2997 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2998 }
2999 }
4e831836
SH		 3000
3001 /* only upper 6 bits (HASH_BITS) are used
3002 * which point to specific bit in he hash registers
3003 */
3004 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
3005
3006 if (hash > 31) {
3007 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3008 tmp |= 1 << (hash - 32);
3009 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3010 } else {
3011 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3012 tmp |= 1 << hash;
3013 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3014 }
1da177e4
LT		 3015 }
3016}
3017
22f6b860 3018/* Set a MAC change in hardware. */
009fda83 3019static int
c556167f 3020fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 3021{
c556167f 3022 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 3023 struct sockaddr *addr = p;
3024
44934fac
LS		 3025 if (addr) {
3026 if (!is_valid_ether_addr(addr->sa_data))
3027 return -EADDRNOTAVAIL;
3028 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3029 }
1da177e4 3030
c556167f
UKK		 3031 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3032 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 3033 fep->hwp + FEC_ADDR_LOW);
c556167f 3034 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 3035 fep->hwp + FEC_ADDR_HIGH);
009fda83 3036 return 0;
1da177e4
LT		 3037}
3038
7f5c6add 3039#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 3040/**
3041 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 3042 * @dev: The FEC network adapter
3043 *
3044 * Polled functionality used by netconsole and others in non interrupt mode
3045 *
3046 */
47a5247f 3047static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 3048{
3049 int i;
3050 struct fec_enet_private *fep = netdev_priv(dev);
3051
3052 for (i = 0; i < FEC_IRQ_NUM; i++) {
3053 if (fep->irq[i] > 0) {
3054 disable_irq(fep->irq[i]);
3055 fec_enet_interrupt(fep->irq[i], dev);
3056 enable_irq(fep->irq[i]);
3057 }
3058 }
3059}
3060#endif
3061
8506fa1d 3062#define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
5bc26726 3063static inline void fec_enet_set_netdev_features(struct net_device *netdev,
4c09eed9
JB		 3064 netdev_features_t features)
3065{
3066 struct fec_enet_private *fep = netdev_priv(netdev);
3067 netdev_features_t changed = features ^ netdev->features;
3068
3069 netdev->features = features;
3070
3071 /* Receive checksum has been changed */
3072 if (changed & NETIF_F_RXCSUM) {
3073 if (features & NETIF_F_RXCSUM)
3074 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3075 else
3076 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 3077 }
5bc26726
NA		 3078}
3079
3080static int fec_set_features(struct net_device *netdev,
3081 netdev_features_t features)
3082{
3083 struct fec_enet_private *fep = netdev_priv(netdev);
3084 netdev_features_t changed = features ^ netdev->features;
4c09eed9 3085
8506fa1d 3086 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
5bc26726
NA		 3087 napi_disable(&fep->napi);
3088 netif_tx_lock_bh(netdev);
3089 fec_stop(netdev);
3090 fec_enet_set_netdev_features(netdev, features);
ef83337d 3091 fec_restart(netdev);
4d494cdc 3092 netif_tx_wake_all_queues(netdev);
8506fa1d
RK		 3093 netif_tx_unlock_bh(netdev);
3094 napi_enable(&fep->napi);
5bc26726
NA		 3095 } else {
3096 fec_enet_set_netdev_features(netdev, features);
4c09eed9
JB		 3097 }
3098
3099 return 0;
3100}
3101
009fda83
SH		 3102static const struct net_device_ops fec_netdev_ops = {
3103 .ndo_open = fec_enet_open,
3104 .ndo_stop = fec_enet_close,
3105 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 3106 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 3107 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 3108 .ndo_validate_addr = eth_validate_addr,
3109 .ndo_tx_timeout = fec_timeout,
3110 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 3111 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 3112#ifdef CONFIG_NET_POLL_CONTROLLER
3113 .ndo_poll_controller = fec_poll_controller,
3114#endif
4c09eed9 3115 .ndo_set_features = fec_set_features,
009fda83
SH		 3116};
3117
1da177e4
LT		 3118 /*
3119 * XXX: We need to clean up on failure exits here.
ead73183 3120 *
1da177e4 3121 */
c556167f 3122static int fec_enet_init(struct net_device *ndev)
1da177e4 3123{
c556167f 3124 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 3125 struct fec_enet_priv_tx_q *txq;
3126 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 3127 struct bufdesc *cbd_base;
4d494cdc 3128 dma_addr_t bd_dma;
55d0218a 3129 int bd_size;
59d0f746 3130 unsigned int i;
55d0218a 3131
41ef84ce
FD		 3132#if defined(CONFIG_ARM)
3133 fep->rx_align = 0xf;
3134 fep->tx_align = 0xf;
3135#else
3136 fep->rx_align = 0x3;
3137 fep->tx_align = 0x3;
3138#endif
3139
59d0f746 3140 fec_enet_alloc_queue(ndev);
79f33912 3141
55d0218a
NA		 3142 if (fep->bufdesc_ex)
3143 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3144 else
3145 fep->bufdesc_size = sizeof(struct bufdesc);
4d494cdc 3146 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
55d0218a 3147 fep->bufdesc_size;
1da177e4 3148
8d4dd5cf 3149 /* Allocate memory for buffer descriptors. */
c0a1a0a6
LS		 3150 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3151 GFP_KERNEL);
4d494cdc 3152 if (!cbd_base) {
79f33912
NA		 3153 return -ENOMEM;
3154 }
3155
4d494cdc 3156 memset(cbd_base, 0, bd_size);
1da177e4 3157
49da97dc 3158 /* Get the Ethernet address */
c556167f 3159 fec_get_mac(ndev);
44934fac
LS		 3160 /* make sure MAC we just acquired is programmed into the hw */
3161 fec_set_mac_address(ndev, NULL);
1da177e4 3162
8d4dd5cf 3163 /* Set receive and transmit descriptor base. */
59d0f746
FL		 3164 for (i = 0; i < fep->num_rx_queues; i++) {
3165 rxq = fep->rx_queue[i];
3166 rxq->index = i;
3167 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3168 rxq->bd_dma = bd_dma;
3169 if (fep->bufdesc_ex) {
3170 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3171 cbd_base = (struct bufdesc *)
3172 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3173 } else {
3174 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3175 cbd_base += rxq->rx_ring_size;
3176 }
3177 }
3178
3179 for (i = 0; i < fep->num_tx_queues; i++) {
3180 txq = fep->tx_queue[i];
3181 txq->index = i;
3182 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3183 txq->bd_dma = bd_dma;
3184 if (fep->bufdesc_ex) {
3185 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3186 cbd_base = (struct bufdesc *)
3187 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3188 } else {
3189 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3190 cbd_base += txq->tx_ring_size;
3191 }
3192 }
4d494cdc 3193
1da177e4 3194
22f6b860 3195 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 3196 ndev->watchdog_timeo = TX_TIMEOUT;
3197 ndev->netdev_ops = &fec_netdev_ops;
3198 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 3199
dc975382 3200 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 3201 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 3202
6b7e4008 3203 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 3204 /* enable hw VLAN support */
3205 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 3206
6b7e4008 3207 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 3208 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3209
48496255
SG		 3210 /* enable hw accelerator */
3211 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 3212 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 3213 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3214 }
4c09eed9 3215
6b7e4008 3216 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
41ef84ce
FD		 3217 fep->tx_align = 0;
3218 fep->rx_align = 0x3f;
3219 }
3220
09d1e541
NA		 3221 ndev->hw_features = ndev->features;
3222
ef83337d 3223 fec_restart(ndev);
1da177e4 3224
1da177e4
LT		 3225 return 0;
3226}
3227
ca2cc333 3228#ifdef CONFIG_OF
33897cc8 3229static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3230{
3231 int err, phy_reset;
a3caad0a 3232 int msec = 1;
ca2cc333
SG		 3233 struct device_node *np = pdev->dev.of_node;
3234
3235 if (!np)
a9b2c8ef 3236 return;
ca2cc333 3237
a3caad0a
SG		 3238 of_property_read_u32(np, "phy-reset-duration", &msec);
3239 /* A sane reset duration should not be longer than 1s */
3240 if (msec > 1000)
3241 msec = 1;
3242
ca2cc333 3243 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 3244 if (!gpio_is_valid(phy_reset))
3245 return;
3246
119fc007
SG		 3247 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3248 GPIOF_OUT_INIT_LOW, "phy-reset");
ca2cc333 3249 if (err) {
07dcf8e9 3250 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 3251 return;
ca2cc333 3252 }
a3caad0a 3253 msleep(msec);
ca2cc333 3254 gpio_set_value(phy_reset, 1);
ca2cc333
SG		 3255}
3256#else /* CONFIG_OF */
0c7768a0 3257static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3258{
3259 /*
3260 * In case of platform probe, the reset has been done
3261 * by machine code.
3262 */
ca2cc333
SG		 3263}
3264#endif /* CONFIG_OF */
3265
9fc095f1
FD		 3266static void
3267fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3268{
3269 struct device_node *np = pdev->dev.of_node;
3270 int err;
3271
3272 *num_tx = *num_rx = 1;
3273
3274 if (!np || !of_device_is_available(np))
3275 return;
3276
3277 /* parse the num of tx and rx queues */
3278 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
b7bd75cf 3279 if (err)
9fc095f1 3280 *num_tx = 1;
b7bd75cf
FL		 3281
3282 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3283 if (err)
9fc095f1 3284 *num_rx = 1;
9fc095f1
FD		 3285
3286 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
b7bd75cf
FL		 3287 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3288 *num_tx);
9fc095f1
FD		 3289 *num_tx = 1;
3290 return;
3291 }
3292
3293 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
b7bd75cf
FL		 3294 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3295 *num_rx);
9fc095f1
FD		 3296 *num_rx = 1;
3297 return;
3298 }
3299
3300}
3301
33897cc8 3302static int
ead73183
SH		 3303fec_probe(struct platform_device *pdev)
3304{
3305 struct fec_enet_private *fep;
5eb32bd0 3306 struct fec_platform_data *pdata;
ead73183
SH		 3307 struct net_device *ndev;
3308 int i, irq, ret = 0;
3309 struct resource *r;
ca2cc333 3310 const struct of_device_id *of_id;
43af940c 3311 static int dev_id;
407066f8 3312 struct device_node *np = pdev->dev.of_node, *phy_node;
b7bd75cf
FL		 3313 int num_tx_qs;
3314 int num_rx_qs;
ca2cc333 3315
9fc095f1
FD		 3316 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3317
ead73183 3318 /* Init network device */
9fc095f1
FD		 3319 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3320 num_tx_qs, num_rx_qs);
83e519b6
FE		 3321 if (!ndev)
3322 return -ENOMEM;
ead73183
SH		 3323
3324 SET_NETDEV_DEV(ndev, &pdev->dev);
3325
3326 /* setup board info structure */
3327 fep = netdev_priv(ndev);
ead73183 3328
6b7e4008
LW		 3329 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3330 if (of_id)
3331 pdev->id_entry = of_id->data;
3332 fep->quirks = pdev->id_entry->driver_data;
3333
0c818594 3334 fep->netdev = ndev;
9fc095f1
FD		 3335 fep->num_rx_queues = num_rx_qs;
3336 fep->num_tx_queues = num_tx_qs;
3337
d1391930 3338#if !defined(CONFIG_M5272)
baa70a5c 3339 /* default enable pause frame auto negotiation */
6b7e4008 3340 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
baa70a5c 3341 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 3342#endif
baa70a5c 3343
5bbde4d2
NA		 3344 /* Select default pin state */
3345 pinctrl_pm_select_default_state(&pdev->dev);
3346
399db75b 3347 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 3348 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3349 if (IS_ERR(fep->hwp)) {
3350 ret = PTR_ERR(fep->hwp);
3351 goto failed_ioremap;
3352 }
3353
e6b043d5 3354 fep->pdev = pdev;
43af940c 3355 fep->dev_id = dev_id++;
ead73183 3356
ead73183
SH		 3357 platform_set_drvdata(pdev, ndev);
3358
de40ed31
NA		 3359 if (of_get_property(np, "fsl,magic-packet", NULL))
3360 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3361
407066f8
UKK		 3362 phy_node = of_parse_phandle(np, "phy-handle", 0);
3363 if (!phy_node && of_phy_is_fixed_link(np)) {
3364 ret = of_phy_register_fixed_link(np);
3365 if (ret < 0) {
3366 dev_err(&pdev->dev,
3367 "broken fixed-link specification\n");
3368 goto failed_phy;
3369 }
3370 phy_node = of_node_get(np);
3371 }
3372 fep->phy_node = phy_node;
3373
6c5f7808 3374 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 3375 if (ret < 0) {
94660ba0 3376 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 3377 if (pdata)
3378 fep->phy_interface = pdata->phy;
3379 else
3380 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3381 } else {
3382 fep->phy_interface = ret;
3383 }
3384
f4d40de3
SH		 3385 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3386 if (IS_ERR(fep->clk_ipg)) {
3387 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 3388 goto failed_clk;
3389 }
f4d40de3
SH		 3390
3391 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3392 if (IS_ERR(fep->clk_ahb)) {
3393 ret = PTR_ERR(fep->clk_ahb);
3394 goto failed_clk;
3395 }
3396
d851b47b
FD		 3397 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3398
daa7d392
WS		 3399 /* enet_out is optional, depends on board */
3400 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3401 if (IS_ERR(fep->clk_enet_out))
3402 fep->clk_enet_out = NULL;
3403
91c0d987
NA		 3404 fep->ptp_clk_on = false;
3405 mutex_init(&fep->ptp_clk_mutex);
9b5330ed
FD		 3406
3407 /* clk_ref is optional, depends on board */
3408 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3409 if (IS_ERR(fep->clk_ref))
3410 fep->clk_ref = NULL;
3411
6b7e4008 3412 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730
FL		 3413 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3414 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 3415 fep->clk_ptp = NULL;
217b5844 3416 fep->bufdesc_ex = false;
6605b730 3417 }
6605b730 3418
e8fcfcd5 3419 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 3420 if (ret)
3421 goto failed_clk;
3422
8fff755e
AL		 3423 ret = clk_prepare_enable(fep->clk_ipg);
3424 if (ret)
3425 goto failed_clk_ipg;
3426
f4e9f3d2
FE		 3427 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3428 if (!IS_ERR(fep->reg_phy)) {
3429 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 3430 if (ret) {
3431 dev_err(&pdev->dev,
3432 "Failed to enable phy regulator: %d\n", ret);
3433 goto failed_regulator;
3434 }
f6a4d607
FE		 3435 } else {
3436 fep->reg_phy = NULL;
5fa9c0fe
SG		 3437 }
3438
8fff755e
AL		 3439 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3440 pm_runtime_use_autosuspend(&pdev->dev);
3441 pm_runtime_set_active(&pdev->dev);
3442 pm_runtime_enable(&pdev->dev);
3443
2ca9b2aa
SG		 3444 fec_reset_phy(pdev);
3445
e2f8d555 3446 if (fep->bufdesc_ex)
ca162a82 3447 fec_ptp_init(pdev);
e2f8d555
FE		 3448
3449 ret = fec_enet_init(ndev);
3450 if (ret)
3451 goto failed_init;
3452
3453 for (i = 0; i < FEC_IRQ_NUM; i++) {
3454 irq = platform_get_irq(pdev, i);
3455 if (irq < 0) {
3456 if (i)
3457 break;
3458 ret = irq;
3459 goto failed_irq;
3460 }
0d9b2ab1 3461 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 3462 0, pdev->name, ndev);
0d9b2ab1 3463 if (ret)
e2f8d555 3464 goto failed_irq;
de40ed31
NA		 3465
3466 fep->irq[i] = irq;
e2f8d555
FE		 3467 }
3468
b4d39b53 3469 init_completion(&fep->mdio_done);
e6b043d5
BW		 3470 ret = fec_enet_mii_init(pdev);
3471 if (ret)
3472 goto failed_mii_init;
3473
03c698c9
OS		 3474 /* Carrier starts down, phylib will bring it up */
3475 netif_carrier_off(ndev);
e8fcfcd5 3476 fec_enet_clk_enable(ndev, false);
5bbde4d2 3477 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 3478
ead73183
SH		 3479 ret = register_netdev(ndev);
3480 if (ret)
3481 goto failed_register;
3482
de40ed31
NA		 3483 device_init_wakeup(&ndev->dev, fep->wol_flag &
3484 FEC_WOL_HAS_MAGIC_PACKET);
3485
eb1d0640
FE		 3486 if (fep->bufdesc_ex && fep->ptp_clock)
3487 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3488
1b7bde6d 3489 fep->rx_copybreak = COPYBREAK_DEFAULT;
36cdc743 3490 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
8fff755e
AL		 3491
3492 pm_runtime_mark_last_busy(&pdev->dev);
3493 pm_runtime_put_autosuspend(&pdev->dev);
3494
ead73183
SH		 3495 return 0;
3496
3497failed_register:
e6b043d5
BW		 3498 fec_enet_mii_remove(fep);
3499failed_mii_init:
7a2bbd8d 3500failed_irq:
7a2bbd8d 3501failed_init:
32cba57b 3502 fec_ptp_stop(pdev);
f6a4d607
FE		 3503 if (fep->reg_phy)
3504 regulator_disable(fep->reg_phy);
5fa9c0fe 3505failed_regulator:
8fff755e
AL		 3506 clk_disable_unprepare(fep->clk_ipg);
3507failed_clk_ipg:
e8fcfcd5 3508 fec_enet_clk_enable(ndev, false);
ead73183 3509failed_clk:
407066f8
UKK		 3510failed_phy:
3511 of_node_put(phy_node);
ead73183
SH		 3512failed_ioremap:
3513 free_netdev(ndev);
3514
3515 return ret;
3516}
3517
33897cc8 3518static int
ead73183
SH		 3519fec_drv_remove(struct platform_device *pdev)
3520{
3521 struct net_device *ndev = platform_get_drvdata(pdev);
3522 struct fec_enet_private *fep = netdev_priv(ndev);
3523
36cdc743 3524 cancel_work_sync(&fep->tx_timeout_work);
32cba57b 3525 fec_ptp_stop(pdev);
e163cc97 3526 unregister_netdev(ndev);
e6b043d5 3527 fec_enet_mii_remove(fep);
f6a4d607
FE		 3528 if (fep->reg_phy)
3529 regulator_disable(fep->reg_phy);
407066f8 3530 of_node_put(fep->phy_node);
ead73183 3531 free_netdev(ndev);
28e2188e 3532
ead73183
SH		 3533 return 0;
3534}
3535
dd66d386 3536static int __maybe_unused fec_suspend(struct device *dev)
ead73183 3537{
87cad5c3 3538 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3539 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 3540
da1774e5 3541 rtnl_lock();
04e5216d 3542 if (netif_running(ndev)) {
de40ed31
NA		 3543 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3544 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
d76cfae9 3545 phy_stop(fep->phy_dev);
31a6de34
RK		 3546 napi_disable(&fep->napi);
3547 netif_tx_lock_bh(ndev);
04e5216d 3548 netif_device_detach(ndev);
31a6de34
RK		 3549 netif_tx_unlock_bh(ndev);
3550 fec_stop(ndev);
f4c4a4e0 3551 fec_enet_clk_enable(ndev, false);
de40ed31
NA		 3552 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3553 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
ead73183 3554 }
da1774e5
RK		 3555 rtnl_unlock();
3556
de40ed31 3557 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
238f7bc7
FE		 3558 regulator_disable(fep->reg_phy);
3559
858eeb7d
NA		 3560 /* SOC supply clock to phy, when clock is disabled, phy link down
3561 * SOC control phy regulator, when regulator is disabled, phy link down
3562 */
3563 if (fep->clk_enet_out || fep->reg_phy)
3564 fep->link = 0;
3565
ead73183
SH		 3566 return 0;
3567}
3568
dd66d386 3569static int __maybe_unused fec_resume(struct device *dev)
ead73183 3570{
87cad5c3 3571 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3572 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 3573 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
238f7bc7 3574 int ret;
de40ed31 3575 int val;
238f7bc7 3576
de40ed31 3577 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
238f7bc7
FE		 3578 ret = regulator_enable(fep->reg_phy);
3579 if (ret)
3580 return ret;
3581 }
ead73183 3582
da1774e5 3583 rtnl_lock();
04e5216d 3584 if (netif_running(ndev)) {
f4c4a4e0
NA		 3585 ret = fec_enet_clk_enable(ndev, true);
3586 if (ret) {
3587 rtnl_unlock();
3588 goto failed_clk;
3589 }
de40ed31
NA		 3590 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3591 if (pdata && pdata->sleep_mode_enable)
3592 pdata->sleep_mode_enable(false);
3593 val = readl(fep->hwp + FEC_ECNTRL);
3594 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3595 writel(val, fep->hwp + FEC_ECNTRL);
3596 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3597 } else {
3598 pinctrl_pm_select_default_state(&fep->pdev->dev);
3599 }
ef83337d 3600 fec_restart(ndev);
31a6de34 3601 netif_tx_lock_bh(ndev);
6af42d42 3602 netif_device_attach(ndev);
dbc64a8e 3603 netif_tx_unlock_bh(ndev);
6af42d42 3604 napi_enable(&fep->napi);
d76cfae9 3605 phy_start(fep->phy_dev);
ead73183 3606 }
da1774e5 3607 rtnl_unlock();
04e5216d 3608
ead73183 3609 return 0;
13a097bd 3610
e8fcfcd5 3611failed_clk:
13a097bd
FE		 3612 if (fep->reg_phy)
3613 regulator_disable(fep->reg_phy);
3614 return ret;
ead73183
SH		 3615}
3616
8fff755e
AL		 3617static int __maybe_unused fec_runtime_suspend(struct device *dev)
3618{
3619 struct net_device *ndev = dev_get_drvdata(dev);
3620 struct fec_enet_private *fep = netdev_priv(ndev);
3621
3622 clk_disable_unprepare(fep->clk_ipg);
3623
3624 return 0;
3625}
3626
3627static int __maybe_unused fec_runtime_resume(struct device *dev)
3628{
3629 struct net_device *ndev = dev_get_drvdata(dev);
3630 struct fec_enet_private *fep = netdev_priv(ndev);
3631
3632 return clk_prepare_enable(fep->clk_ipg);
3633}
3634
3635static const struct dev_pm_ops fec_pm_ops = {
3636 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3637 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3638};
59d4289b 3639
ead73183
SH		 3640static struct platform_driver fec_driver = {
3641 .driver = {
b5680e0b 3642 .name = DRIVER_NAME,
87cad5c3 3643 .pm = &fec_pm_ops,
ca2cc333 3644 .of_match_table = fec_dt_ids,
ead73183 3645 },
b5680e0b 3646 .id_table = fec_devtype,
87cad5c3 3647 .probe = fec_probe,
33897cc8 3648 .remove = fec_drv_remove,
ead73183
SH		 3649};
3650
aaca2377 3651module_platform_driver(fec_driver);
1da177e4 3652
f8c0aca9 3653MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 3654MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)