[linux-2.6-block.git] / drivers / net / ethernet / freescale / fec.h

/****************************************************************************/

/*
 *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
 *		   processors.
 *
 *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
 *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
 */

/****************************************************************************/
#ifndef FEC_H
#define	FEC_H
/****************************************************************************/

#include <linux/clocksource.h>
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>

#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
    defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
/*
 *	Just figures, Motorola would have to change the offsets for
 *	registers in the same peripheral device on different models
 *	of the ColdFire!
 */
#define FEC_IEVENT		0x004 /* Interrupt event reg */
#define FEC_IMASK		0x008 /* Interrupt mask reg */
#define FEC_R_DES_ACTIVE	0x010 /* Receive descriptor reg */
#define FEC_X_DES_ACTIVE	0x014 /* Transmit descriptor reg */
#define FEC_ECNTRL		0x024 /* Ethernet control reg */
#define FEC_MII_DATA		0x040 /* MII manage frame reg */
#define FEC_MII_SPEED		0x044 /* MII speed control reg */
#define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
#define FEC_R_CNTRL		0x084 /* Receive control reg */
#define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
#define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
#define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
#define FEC_OPD			0x0ec /* Opcode + Pause duration */
#define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
#define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
#define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
#define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
#define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
#define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
#define FEC_R_FSTART		0x150 /* FIFO receive start reg */
#define FEC_R_DES_START		0x180 /* Receive descriptor ring */
#define FEC_X_DES_START		0x184 /* Transmit descriptor ring */
#define FEC_R_BUFF_SIZE		0x188 /* Maximum receive buff size */
#define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
#define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
#define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
#define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
#define FEC_RACC		0x1C4 /* Receive Accelerator function */
#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
#define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */

#define BM_MIIGSK_CFGR_MII		0x00
#define BM_MIIGSK_CFGR_RMII		0x01
#define BM_MIIGSK_CFGR_FRCONT_10M	0x40

#else

#define FEC_ECNTRL		0x000 /* Ethernet control reg */
#define FEC_IEVENT		0x004 /* Interrupt even reg */
#define FEC_IMASK		0x008 /* Interrupt mask reg */
#define FEC_IVEC		0x00c /* Interrupt vec status reg */
#define FEC_R_DES_ACTIVE	0x010 /* Receive descriptor reg */
#define FEC_X_DES_ACTIVE	0x014 /* Transmit descriptor reg */
#define FEC_MII_DATA		0x040 /* MII manage frame reg */
#define FEC_MII_SPEED		0x044 /* MII speed control reg */
#define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
#define FEC_R_FSTART		0x090 /* FIFO receive start reg */
#define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
#define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
#define FEC_R_CNTRL		0x104 /* Receive control reg */
#define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
#define FEC_X_CNTRL		0x144 /* Transmit Control reg */
#define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
#define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
#define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
#define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
#define FEC_R_DES_START		0x3d0 /* Receive descriptor ring */
#define FEC_X_DES_START		0x3d4 /* Transmit descriptor ring */
#define FEC_R_BUFF_SIZE		0x3d8 /* Maximum receive buff size */
#define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */

#endif /* CONFIG_M5272 */


/*
 *	Define the buffer descriptor structure.
 */
#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
struct bufdesc {
	unsigned short cbd_datlen;	/* Data length */
	unsigned short cbd_sc;	/* Control and status info */
	unsigned long cbd_bufaddr;	/* Buffer address */
};
#else
struct bufdesc {
	unsigned short	cbd_sc;			/* Control and status info */
	unsigned short	cbd_datlen;		/* Data length */
	unsigned long	cbd_bufaddr;		/* Buffer address */
};
#endif

struct bufdesc_ex {
	struct bufdesc desc;
	unsigned long cbd_esc;
	unsigned long cbd_prot;
	unsigned long cbd_bdu;
	unsigned long ts;
	unsigned short res0[4];
};

/*
 *	The following definitions courtesy of commproc.h, which where
 *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
 */
#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
#define BD_SC_CM        ((ushort)0x0200)        /* Continuous mode */
#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
#define BD_SC_CD        ((ushort)0x0001)        /* ?? */

/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
#define BD_ENET_RX_WRAP         ((ushort)0x2000)
#define BD_ENET_RX_INTR         ((ushort)0x1000)
#define BD_ENET_RX_LAST         ((ushort)0x0800)
#define BD_ENET_RX_FIRST        ((ushort)0x0400)
#define BD_ENET_RX_MISS         ((ushort)0x0100)
#define BD_ENET_RX_LG           ((ushort)0x0020)
#define BD_ENET_RX_NO           ((ushort)0x0010)
#define BD_ENET_RX_SH           ((ushort)0x0008)
#define BD_ENET_RX_CR           ((ushort)0x0004)
#define BD_ENET_RX_OV           ((ushort)0x0002)
#define BD_ENET_RX_CL           ((ushort)0x0001)
#define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */

/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY        ((ushort)0x8000)
#define BD_ENET_TX_PAD          ((ushort)0x4000)
#define BD_ENET_TX_WRAP         ((ushort)0x2000)
#define BD_ENET_TX_INTR         ((ushort)0x1000)
#define BD_ENET_TX_LAST         ((ushort)0x0800)
#define BD_ENET_TX_TC           ((ushort)0x0400)
#define BD_ENET_TX_DEF          ((ushort)0x0200)
#define BD_ENET_TX_HB           ((ushort)0x0100)
#define BD_ENET_TX_LC           ((ushort)0x0080)
#define BD_ENET_TX_RL           ((ushort)0x0040)
#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
#define BD_ENET_TX_UN           ((ushort)0x0002)
#define BD_ENET_TX_CSL          ((ushort)0x0001)
#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */

/*enhanced buffer descriptor control/status used by Ethernet transmit*/
#define BD_ENET_TX_INT          0x40000000
#define BD_ENET_TX_TS           0x20000000
#define BD_ENET_TX_PINS         0x10000000
#define BD_ENET_TX_IINS         0x08000000


/* This device has up to three irqs on some platforms */
#define FEC_IRQ_NUM		3

/* The number of Tx and Rx buffers.  These are allocated from the page
 * pool.  The code may assume these are power of two, so it it best
 * to keep them that size.
 * We don't need to allocate pages for the transmitter.  We just use
 * the skbuffer directly.
 */

#define FEC_ENET_RX_PAGES	8
#define FEC_ENET_RX_FRSIZE	2048
#define FEC_ENET_RX_FRPPG	(PAGE_SIZE / FEC_ENET_RX_FRSIZE)
#define RX_RING_SIZE		(FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
#define FEC_ENET_TX_FRSIZE	2048
#define FEC_ENET_TX_FRPPG	(PAGE_SIZE / FEC_ENET_TX_FRSIZE)
#define TX_RING_SIZE		16	/* Must be power of two */
#define TX_RING_MOD_MASK	15	/*   for this to work */

#define BD_ENET_RX_INT          0x00800000
#define BD_ENET_RX_PTP          ((ushort)0x0400)
#define BD_ENET_RX_ICE		0x00000020
#define BD_ENET_RX_PCR		0x00000010
#define FLAG_RX_CSUM_ENABLED	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
#define FLAG_RX_CSUM_ERROR	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)

struct fec_enet_delayed_work {
	struct delayed_work delay_work;
	bool timeout;
};

/* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
 * tx_bd_base always point to the base of the buffer descriptors.  The
 * cur_rx and cur_tx point to the currently available buffer.
 * The dirty_tx tracks the current buffer that is being sent by the
 * controller.  The cur_tx and dirty_tx are equal under both completely
 * empty and completely full conditions.  The empty/ready indicator in
 * the buffer descriptor determines the actual condition.
 */
struct fec_enet_private {
	/* Hardware registers of the FEC device */
	void __iomem *hwp;

	struct net_device *netdev;

	struct clk *clk_ipg;
	struct clk *clk_ahb;
	struct clk *clk_enet_out;
	struct clk *clk_ptp;

	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
	unsigned char *tx_bounce[TX_RING_SIZE];
	struct	sk_buff *tx_skbuff[TX_RING_SIZE];
	struct	sk_buff *rx_skbuff[RX_RING_SIZE];

	/* CPM dual port RAM relative addresses */
	dma_addr_t	bd_dma;
	/* Address of Rx and Tx buffers */
	struct bufdesc	*rx_bd_base;
	struct bufdesc	*tx_bd_base;
	/* The next free ring entry */
	struct bufdesc	*cur_rx, *cur_tx;
	/* The ring entries to be free()ed */
	struct bufdesc	*dirty_tx;

	struct	platform_device *pdev;

	int	opened;
	int	dev_id;

	/* Phylib and MDIO interface */
	struct	mii_bus *mii_bus;
	struct	phy_device *phy_dev;
	int	mii_timeout;
	uint	phy_speed;
	phy_interface_t	phy_interface;
	int	link;
	int	full_duplex;
	int	speed;
	struct	completion mdio_done;
	int	irq[FEC_IRQ_NUM];
	int	bufdesc_ex;
	int	pause_flag;

	struct	napi_struct napi;
	int	csum_flags;

	struct ptp_clock *ptp_clock;
	struct ptp_clock_info ptp_caps;
	unsigned long last_overflow_check;
	spinlock_t tmreg_lock;
	struct cyclecounter cc;
	struct timecounter tc;
	int rx_hwtstamp_filter;
	u32 base_incval;
	u32 cycle_speed;
	int hwts_rx_en;
	int hwts_tx_en;
	struct timer_list time_keep;
	struct fec_enet_delayed_work delay_work;
	struct regulator *reg_phy;
};

void fec_ptp_init(struct net_device *ndev, struct platform_device *pdev);
void fec_ptp_start_cyclecounter(struct net_device *ndev);
int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd);

/****************************************************************************/
#endif /* FEC_H */
Commit	Line	Data
1da177e4 LT	1	/****************************************************************************/
	2
	3	/*
7a77d918 GU	4	* fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
7a77d918 GU	5	* processors.
1da177e4	6	*
7a77d918	7	* (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
1da177e4 LT	8	* (C) Copyright 2000-2001, Lineo (www.lineo.com)
	9	*/
	10
	11	/****************************************************************************/
	12	#ifndef FEC_H
	13	#define FEC_H
	14	/****************************************************************************/
	15
6605b730 FL	16	#include <linux/clocksource.h>
	17	#include <linux/net_tstamp.h>
	18	#include <linux/ptp_clock_kernel.h>
6605b730	19
7a77d918	20	#if defined(CONFIG_M523x) \|\| defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
b5680e0b SG	21	defined(CONFIG_M520x) \|\| defined(CONFIG_M532x) \|\| \
b5680e0b SG	22	defined(CONFIG_ARCH_MXC) \|\| defined(CONFIG_SOC_IMX28)
1da177e4 LT	23	/*
	24	* Just figures, Motorola would have to change the offsets for
	25	* registers in the same peripheral device on different models
	26	* of the ColdFire!
	27	*/
f44d6305 SH	28	#define FEC_IEVENT 0x004 /* Interrupt event reg */
	29	#define FEC_IMASK 0x008 /* Interrupt mask reg */
	30	#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
	31	#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
	32	#define FEC_ECNTRL 0x024 /* Ethernet control reg */
	33	#define FEC_MII_DATA 0x040 /* MII manage frame reg */
	34	#define FEC_MII_SPEED 0x044 /* MII speed control reg */
	35	#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
	36	#define FEC_R_CNTRL 0x084 /* Receive control reg */
	37	#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
	38	#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
	39	#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
	40	#define FEC_OPD 0x0ec /* Opcode + Pause duration */
	41	#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
	42	#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
	43	#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
	44	#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
	45	#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
	46	#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
	47	#define FEC_R_FSTART 0x150 /* FIFO receive start reg */
	48	#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
	49	#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
	50	#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
baa70a5c FL	51	#define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
	52	#define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
	53	#define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
	54	#define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
4c09eed9	55	#define FEC_RACC 0x1C4 /* Receive Accelerator function */
5eb32bd0 BS	56	#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
5eb32bd0 BS	57	#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
1da177e4	58
8d82f219 EB	59	#define BM_MIIGSK_CFGR_MII 0x00
	60	#define BM_MIIGSK_CFGR_RMII 0x01
	61	#define BM_MIIGSK_CFGR_FRCONT_10M 0x40
	62
1da177e4 LT	63	#else
1da177e4 LT	64
9ff1a91c GU	65	#define FEC_ECNTRL 0x000 /* Ethernet control reg */
	66	#define FEC_IEVENT 0x004 /* Interrupt even reg */
	67	#define FEC_IMASK 0x008 /* Interrupt mask reg */
	68	#define FEC_IVEC 0x00c /* Interrupt vec status reg */
	69	#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
5ca1ea23	70	#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
f44d6305 SH	71	#define FEC_MII_DATA 0x040 /* MII manage frame reg */
	72	#define FEC_MII_SPEED 0x044 /* MII speed control reg */
	73	#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
	74	#define FEC_R_FSTART 0x090 /* FIFO receive start reg */
	75	#define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
	76	#define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
	77	#define FEC_R_CNTRL 0x104 /* Receive control reg */
	78	#define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
	79	#define FEC_X_CNTRL 0x144 /* Transmit Control reg */
	80	#define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
	81	#define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
	82	#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
	83	#define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
	84	#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */
	85	#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */
	86	#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */
	87	#define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
1da177e4 LT	88
	89	#endif /* CONFIG_M5272 */
	90
	91
	92	/*
	93	* Define the buffer descriptor structure.
	94	*/
b5680e0b	95	#if defined(CONFIG_ARCH_MXC) \|\| defined(CONFIG_SOC_IMX28)
2e28532f	96	struct bufdesc {
196719ec SH	97	unsigned short cbd_datlen; /* Data length */
	98	unsigned short cbd_sc; /* Control and status info */
	99	unsigned long cbd_bufaddr; /* Buffer address */
ff43da86	100	};
acac8406 FL	101	#else
	102	struct bufdesc {
	103	unsigned short cbd_sc; /* Control and status info */
	104	unsigned short cbd_datlen; /* Data length */
	105	unsigned long cbd_bufaddr; /* Buffer address */
	106	};
	107	#endif
ff43da86 FL	108
	109	struct bufdesc_ex {
	110	struct bufdesc desc;
6605b730 FL	111	unsigned long cbd_esc;
	112	unsigned long cbd_prot;
	113	unsigned long cbd_bdu;
	114	unsigned long ts;
	115	unsigned short res0[4];
2e28532f	116	};
ff43da86	117
1da177e4 LT	118	/*
	119	* The following definitions courtesy of commproc.h, which where
	120	* Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
	121	*/
25985edc	122	#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
1da177e4 LT	123	#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
	124	#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
	125	#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
25985edc	126	#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
1da177e4 LT	127	#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
	128	#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
	129	#define BD_SC_BR ((ushort)0x0020) /* Break received */
	130	#define BD_SC_FR ((ushort)0x0010) /* Framing error */
	131	#define BD_SC_PR ((ushort)0x0008) /* Parity error */
	132	#define BD_SC_OV ((ushort)0x0002) /* Overrun */
	133	#define BD_SC_CD ((ushort)0x0001) /* ?? */
	134
	135	/* Buffer descriptor control/status used by Ethernet receive.
	136	*/
	137	#define BD_ENET_RX_EMPTY ((ushort)0x8000)
	138	#define BD_ENET_RX_WRAP ((ushort)0x2000)
	139	#define BD_ENET_RX_INTR ((ushort)0x1000)
	140	#define BD_ENET_RX_LAST ((ushort)0x0800)
	141	#define BD_ENET_RX_FIRST ((ushort)0x0400)
	142	#define BD_ENET_RX_MISS ((ushort)0x0100)
	143	#define BD_ENET_RX_LG ((ushort)0x0020)
	144	#define BD_ENET_RX_NO ((ushort)0x0010)
	145	#define BD_ENET_RX_SH ((ushort)0x0008)
	146	#define BD_ENET_RX_CR ((ushort)0x0004)
	147	#define BD_ENET_RX_OV ((ushort)0x0002)
	148	#define BD_ENET_RX_CL ((ushort)0x0001)
	149	#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
	150
	151	/* Buffer descriptor control/status used by Ethernet transmit.
	152	*/
	153	#define BD_ENET_TX_READY ((ushort)0x8000)
	154	#define BD_ENET_TX_PAD ((ushort)0x4000)
	155	#define BD_ENET_TX_WRAP ((ushort)0x2000)
	156	#define BD_ENET_TX_INTR ((ushort)0x1000)
	157	#define BD_ENET_TX_LAST ((ushort)0x0800)
	158	#define BD_ENET_TX_TC ((ushort)0x0400)
	159	#define BD_ENET_TX_DEF ((ushort)0x0200)
	160	#define BD_ENET_TX_HB ((ushort)0x0100)
	161	#define BD_ENET_TX_LC ((ushort)0x0080)
	162	#define BD_ENET_TX_RL ((ushort)0x0040)
	163	#define BD_ENET_TX_RCMASK ((ushort)0x003c)
	164	#define BD_ENET_TX_UN ((ushort)0x0002)
	165	#define BD_ENET_TX_CSL ((ushort)0x0001)
	166	#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
	167
4c09eed9	168	/enhanced buffer descriptor control/status used by Ethernet transmit/
405f257f FL	169	#define BD_ENET_TX_INT 0x40000000
405f257f FL	170	#define BD_ENET_TX_TS 0x20000000
4c09eed9 JB	171	#define BD_ENET_TX_PINS 0x10000000
4c09eed9 JB	172	#define BD_ENET_TX_IINS 0x08000000
405f257f FL	173
	174
	175	/* This device has up to three irqs on some platforms */
	176	#define FEC_IRQ_NUM 3
	177
	178	/* The number of Tx and Rx buffers. These are allocated from the page
	179	* pool. The code may assume these are power of two, so it it best
	180	* to keep them that size.
	181	* We don't need to allocate pages for the transmitter. We just use
	182	* the skbuffer directly.
	183	*/
	184
	185	#define FEC_ENET_RX_PAGES 8
	186	#define FEC_ENET_RX_FRSIZE 2048
	187	#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
	188	#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
	189	#define FEC_ENET_TX_FRSIZE 2048
	190	#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
	191	#define TX_RING_SIZE 16 /* Must be power of two */
	192	#define TX_RING_MOD_MASK 15 /* for this to work */
	193
	194	#define BD_ENET_RX_INT 0x00800000
	195	#define BD_ENET_RX_PTP ((ushort)0x0400)
4c09eed9 JB	196	#define BD_ENET_RX_ICE 0x00000020
	197	#define BD_ENET_RX_PCR 0x00000010
	198	#define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE \| BD_ENET_RX_PCR)
	199	#define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE \| BD_ENET_RX_PCR)
405f257f	200
54309fa6 FL	201	struct fec_enet_delayed_work {
	202	struct delayed_work delay_work;
	203	bool timeout;
	204	};
	205
405f257f FL	206	/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
	207	* tx_bd_base always point to the base of the buffer descriptors. The
	208	* cur_rx and cur_tx point to the currently available buffer.
	209	* The dirty_tx tracks the current buffer that is being sent by the
	210	* controller. The cur_tx and dirty_tx are equal under both completely
	211	* empty and completely full conditions. The empty/ready indicator in
	212	* the buffer descriptor determines the actual condition.
	213	*/
	214	struct fec_enet_private {
	215	/* Hardware registers of the FEC device */
	216	void __iomem *hwp;
	217
	218	struct net_device *netdev;
	219
	220	struct clk *clk_ipg;
	221	struct clk *clk_ahb;
daa7d392	222	struct clk *clk_enet_out;
6605b730	223	struct clk *clk_ptp;
405f257f FL	224
	225	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
	226	unsigned char *tx_bounce[TX_RING_SIZE];
	227	struct sk_buff *tx_skbuff[TX_RING_SIZE];
	228	struct sk_buff *rx_skbuff[RX_RING_SIZE];
405f257f FL	229
	230	/* CPM dual port RAM relative addresses */
	231	dma_addr_t bd_dma;
	232	/* Address of Rx and Tx buffers */
	233	struct bufdesc *rx_bd_base;
	234	struct bufdesc *tx_bd_base;
	235	/* The next free ring entry */
	236	struct bufdesc cur_rx, cur_tx;
	237	/* The ring entries to be free()ed */
	238	struct bufdesc *dirty_tx;
	239
405f257f FL	240	struct platform_device *pdev;
	241
	242	int opened;
	243	int dev_id;
	244
	245	/* Phylib and MDIO interface */
	246	struct mii_bus *mii_bus;
	247	struct phy_device *phy_dev;
	248	int mii_timeout;
	249	uint phy_speed;
	250	phy_interface_t phy_interface;
	251	int link;
	252	int full_duplex;
d97e7497	253	int speed;
405f257f FL	254	struct completion mdio_done;
405f257f FL	255	int irq[FEC_IRQ_NUM];
ff43da86	256	int bufdesc_ex;
baa70a5c	257	int pause_flag;
6605b730	258
dc975382	259	struct napi_struct napi;
4c09eed9	260	int csum_flags;
dc975382	261
6605b730 FL	262	struct ptp_clock *ptp_clock;
	263	struct ptp_clock_info ptp_caps;
	264	unsigned long last_overflow_check;
	265	spinlock_t tmreg_lock;
	266	struct cyclecounter cc;
	267	struct timecounter tc;
	268	int rx_hwtstamp_filter;
	269	u32 base_incval;
	270	u32 cycle_speed;
	271	int hwts_rx_en;
	272	int hwts_tx_en;
	273	struct timer_list time_keep;
54309fa6	274	struct fec_enet_delayed_work delay_work;
f4e9f3d2	275	struct regulator *reg_phy;
405f257f	276	};
1da177e4	277
6605b730 FL	278	void fec_ptp_init(struct net_device ndev, struct platform_device pdev);
	279	void fec_ptp_start_cyclecounter(struct net_device *ndev);
	280	int fec_ptp_ioctl(struct net_device ndev, struct ifreq ifr, int cmd);
6605b730	281
1da177e4 LT	282	/****************************************************************************/
1da177e4 LT	283	#endif /* FEC_H */