Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/bitops.h> | |
6f501b17 SH |
41 | #include <linux/io.h> |
42 | #include <linux/irq.h> | |
196719ec | 43 | #include <linux/clk.h> |
ead73183 | 44 | #include <linux/platform_device.h> |
e6b043d5 | 45 | #include <linux/phy.h> |
5eb32bd0 | 46 | #include <linux/fec.h> |
ca2cc333 SG |
47 | #include <linux/of.h> |
48 | #include <linux/of_device.h> | |
49 | #include <linux/of_gpio.h> | |
50 | #include <linux/of_net.h> | |
b2bccee1 | 51 | #include <linux/pinctrl/consumer.h> |
5fa9c0fe | 52 | #include <linux/regulator/consumer.h> |
1da177e4 | 53 | |
080853af | 54 | #include <asm/cacheflush.h> |
196719ec | 55 | |
b5680e0b | 56 | #ifndef CONFIG_ARM |
1da177e4 LT |
57 | #include <asm/coldfire.h> |
58 | #include <asm/mcfsim.h> | |
196719ec | 59 | #endif |
6f501b17 | 60 | |
1da177e4 | 61 | #include "fec.h" |
1da177e4 | 62 | |
085e79ed | 63 | #if defined(CONFIG_ARM) |
196719ec SH |
64 | #define FEC_ALIGNMENT 0xf |
65 | #else | |
66 | #define FEC_ALIGNMENT 0x3 | |
67 | #endif | |
68 | ||
b5680e0b | 69 | #define DRIVER_NAME "fec" |
dc975382 | 70 | #define FEC_NAPI_WEIGHT 64 |
b5680e0b | 71 | |
baa70a5c FL |
72 | /* Pause frame feild and FIFO threshold */ |
73 | #define FEC_ENET_FCE (1 << 5) | |
74 | #define FEC_ENET_RSEM_V 0x84 | |
75 | #define FEC_ENET_RSFL_V 16 | |
76 | #define FEC_ENET_RAEM_V 0x8 | |
77 | #define FEC_ENET_RAFL_V 0x8 | |
78 | #define FEC_ENET_OPD_V 0xFFF0 | |
79 | ||
b5680e0b SG |
80 | /* Controller is ENET-MAC */ |
81 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
82 | /* Controller needs driver to swap frame */ | |
83 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
84 | /* Controller uses gasket */ |
85 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
86 | /* Controller has GBIT support */ |
87 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
ff43da86 FL |
88 | /* Controller has extend desc buffer */ |
89 | #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) | |
b5680e0b SG |
90 | |
91 | static struct platform_device_id fec_devtype[] = { | |
92 | { | |
0ca1e290 | 93 | /* keep it for coldfire */ |
b5680e0b SG |
94 | .name = DRIVER_NAME, |
95 | .driver_data = 0, | |
0ca1e290 SG |
96 | }, { |
97 | .name = "imx25-fec", | |
98 | .driver_data = FEC_QUIRK_USE_GASKET, | |
99 | }, { | |
100 | .name = "imx27-fec", | |
101 | .driver_data = 0, | |
b5680e0b SG |
102 | }, { |
103 | .name = "imx28-fec", | |
104 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
105 | }, { |
106 | .name = "imx6q-fec", | |
ff43da86 FL |
107 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
108 | FEC_QUIRK_HAS_BUFDESC_EX, | |
0ca1e290 SG |
109 | }, { |
110 | /* sentinel */ | |
111 | } | |
b5680e0b | 112 | }; |
0ca1e290 | 113 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 114 | |
ca2cc333 | 115 | enum imx_fec_type { |
a7dd3219 | 116 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
117 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
118 | IMX28_FEC, | |
230dec61 | 119 | IMX6Q_FEC, |
ca2cc333 SG |
120 | }; |
121 | ||
122 | static const struct of_device_id fec_dt_ids[] = { | |
123 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
124 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
125 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 126 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
ca2cc333 SG |
127 | { /* sentinel */ } |
128 | }; | |
129 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
130 | ||
49da97dc SG |
131 | static unsigned char macaddr[ETH_ALEN]; |
132 | module_param_array(macaddr, byte, NULL, 0); | |
133 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 134 | |
49da97dc | 135 | #if defined(CONFIG_M5272) |
1da177e4 LT |
136 | /* |
137 | * Some hardware gets it MAC address out of local flash memory. | |
138 | * if this is non-zero then assume it is the address to get MAC from. | |
139 | */ | |
140 | #if defined(CONFIG_NETtel) | |
141 | #define FEC_FLASHMAC 0xf0006006 | |
142 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
143 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
144 | #elif defined(CONFIG_CANCam) |
145 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
146 | #elif defined (CONFIG_M5272C3) |
147 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
148 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 149 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
150 | #else |
151 | #define FEC_FLASHMAC 0 | |
152 | #endif | |
43be6366 | 153 | #endif /* CONFIG_M5272 */ |
ead73183 | 154 | |
ff43da86 | 155 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) |
6b265293 | 156 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
157 | #endif |
158 | ||
22f6b860 | 159 | /* Interrupt events/masks. */ |
1da177e4 LT |
160 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
161 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
162 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
163 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
164 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
165 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
166 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
167 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
168 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
169 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
170 | ||
4bee1f9a | 171 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
dc975382 | 172 | #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) |
4bee1f9a | 173 | |
1da177e4 LT |
174 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
175 | */ | |
176 | #define PKT_MAXBUF_SIZE 1518 | |
177 | #define PKT_MINBUF_SIZE 64 | |
178 | #define PKT_MAXBLR_SIZE 1520 | |
179 | ||
1da177e4 | 180 | /* |
6b265293 | 181 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
182 | * size bits. Other FEC hardware does not, so we need to take that into |
183 | * account when setting it. | |
184 | */ | |
562d2f8c | 185 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 186 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
187 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
188 | #else | |
189 | #define OPT_FRAME_SIZE 0 | |
190 | #endif | |
191 | ||
e6b043d5 BW |
192 | /* FEC MII MMFR bits definition */ |
193 | #define FEC_MMFR_ST (1 << 30) | |
194 | #define FEC_MMFR_OP_READ (2 << 28) | |
195 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
196 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
197 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
198 | #define FEC_MMFR_TA (2 << 16) | |
199 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 200 | |
c3b084c2 | 201 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 202 | |
22f6b860 SH |
203 | /* Transmitter timeout */ |
204 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 205 | |
baa70a5c FL |
206 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
207 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
208 | ||
e163cc97 LW |
209 | static int mii_cnt; |
210 | ||
ff43da86 FL |
211 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) |
212 | { | |
213 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
214 | if (is_ex) | |
215 | return (struct bufdesc *)(ex + 1); | |
216 | else | |
217 | return bdp + 1; | |
218 | } | |
219 | ||
220 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) | |
221 | { | |
222 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
223 | if (is_ex) | |
224 | return (struct bufdesc *)(ex - 1); | |
225 | else | |
226 | return bdp - 1; | |
227 | } | |
228 | ||
b5680e0b SG |
229 | static void *swap_buffer(void *bufaddr, int len) |
230 | { | |
231 | int i; | |
232 | unsigned int *buf = bufaddr; | |
233 | ||
234 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
235 | *buf = cpu_to_be32(*buf); | |
236 | ||
237 | return bufaddr; | |
238 | } | |
239 | ||
c7621cb3 | 240 | static netdev_tx_t |
c556167f | 241 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 242 | { |
c556167f | 243 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
244 | const struct platform_device_id *id_entry = |
245 | platform_get_device_id(fep->pdev); | |
2e28532f | 246 | struct bufdesc *bdp; |
9555b31e | 247 | void *bufaddr; |
0e702ab3 | 248 | unsigned short status; |
de5fb0a0 | 249 | unsigned int index; |
1da177e4 | 250 | |
1da177e4 LT |
251 | if (!fep->link) { |
252 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 253 | return NETDEV_TX_BUSY; |
1da177e4 LT |
254 | } |
255 | ||
256 | /* Fill in a Tx ring entry */ | |
257 | bdp = fep->cur_tx; | |
258 | ||
0e702ab3 | 259 | status = bdp->cbd_sc; |
22f6b860 | 260 | |
0e702ab3 | 261 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 262 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 263 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 264 | */ |
c556167f | 265 | printk("%s: tx queue full!.\n", ndev->name); |
5b548140 | 266 | return NETDEV_TX_BUSY; |
1da177e4 | 267 | } |
1da177e4 | 268 | |
22f6b860 | 269 | /* Clear all of the status flags */ |
0e702ab3 | 270 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 271 | |
22f6b860 | 272 | /* Set buffer length and buffer pointer */ |
9555b31e | 273 | bufaddr = skb->data; |
1da177e4 LT |
274 | bdp->cbd_datlen = skb->len; |
275 | ||
276 | /* | |
22f6b860 SH |
277 | * On some FEC implementations data must be aligned on |
278 | * 4-byte boundaries. Use bounce buffers to copy data | |
279 | * and get it aligned. Ugh. | |
1da177e4 | 280 | */ |
de5fb0a0 FL |
281 | if (fep->bufdesc_ex) |
282 | index = (struct bufdesc_ex *)bdp - | |
283 | (struct bufdesc_ex *)fep->tx_bd_base; | |
284 | else | |
285 | index = bdp - fep->tx_bd_base; | |
286 | ||
9555b31e | 287 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
8a73b0bc | 288 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 289 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
290 | } |
291 | ||
b5680e0b SG |
292 | /* |
293 | * Some design made an incorrect assumption on endian mode of | |
294 | * the system that it's running on. As the result, driver has to | |
295 | * swap every frame going to and coming from the controller. | |
296 | */ | |
297 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
298 | swap_buffer(bufaddr, skb->len); | |
299 | ||
22f6b860 | 300 | /* Save skb pointer */ |
de5fb0a0 | 301 | fep->tx_skbuff[index] = skb; |
6aa20a22 | 302 | |
1da177e4 LT |
303 | /* Push the data cache so the CPM does not get stale memory |
304 | * data. | |
305 | */ | |
d1ab1f54 | 306 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 307 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 308 | |
0e702ab3 GU |
309 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
310 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 311 | */ |
0e702ab3 | 312 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 313 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 314 | bdp->cbd_sc = status; |
1da177e4 | 315 | |
ff43da86 FL |
316 | if (fep->bufdesc_ex) { |
317 | ||
318 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
319 | ebdp->cbd_bdu = 0; | |
320 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
6605b730 | 321 | fep->hwts_tx_en)) { |
ff43da86 | 322 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
6605b730 | 323 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
ff43da86 | 324 | } else { |
6605b730 | 325 | |
ff43da86 FL |
326 | ebdp->cbd_esc = BD_ENET_TX_INT; |
327 | } | |
6605b730 | 328 | } |
22f6b860 SH |
329 | /* If this was the last BD in the ring, start at the beginning again. */ |
330 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 331 | bdp = fep->tx_bd_base; |
22f6b860 | 332 | else |
ff43da86 | 333 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
1da177e4 | 334 | |
de5fb0a0 FL |
335 | fep->cur_tx = bdp; |
336 | ||
337 | if (fep->cur_tx == fep->dirty_tx) | |
c556167f | 338 | netif_stop_queue(ndev); |
1da177e4 | 339 | |
de5fb0a0 FL |
340 | /* Trigger transmission start */ |
341 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
1da177e4 | 342 | |
18a03b97 RC |
343 | skb_tx_timestamp(skb); |
344 | ||
6ed10654 | 345 | return NETDEV_TX_OK; |
1da177e4 LT |
346 | } |
347 | ||
45993653 UKK |
348 | /* This function is called to start or restart the FEC during a link |
349 | * change. This only happens when switching between half and full | |
350 | * duplex. | |
351 | */ | |
1da177e4 | 352 | static void |
45993653 | 353 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 354 | { |
c556167f | 355 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
356 | const struct platform_device_id *id_entry = |
357 | platform_get_device_id(fep->pdev); | |
358 | int i; | |
cd1f402c UKK |
359 | u32 temp_mac[2]; |
360 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 361 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 362 | |
45993653 UKK |
363 | /* Whack a reset. We should wait for this. */ |
364 | writel(1, fep->hwp + FEC_ECNTRL); | |
365 | udelay(10); | |
1da177e4 | 366 | |
45993653 UKK |
367 | /* |
368 | * enet-mac reset will reset mac address registers too, | |
369 | * so need to reconfigure it. | |
370 | */ | |
371 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
372 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
373 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
374 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
375 | } | |
1da177e4 | 376 | |
45993653 UKK |
377 | /* Clear any outstanding interrupt. */ |
378 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 379 | |
45993653 UKK |
380 | /* Reset all multicast. */ |
381 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
382 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
383 | #ifndef CONFIG_M5272 | |
384 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
385 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
386 | #endif | |
1da177e4 | 387 | |
45993653 UKK |
388 | /* Set maximum receive buffer size. */ |
389 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 390 | |
45993653 UKK |
391 | /* Set receive and transmit descriptor base. */ |
392 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
ff43da86 FL |
393 | if (fep->bufdesc_ex) |
394 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) | |
395 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
396 | else | |
397 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) | |
398 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
45993653 | 399 | |
45993653 UKK |
400 | fep->cur_rx = fep->rx_bd_base; |
401 | ||
45993653 UKK |
402 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
403 | if (fep->tx_skbuff[i]) { | |
404 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
405 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 406 | } |
45993653 | 407 | } |
97b72e43 | 408 | |
45993653 UKK |
409 | /* Enable MII mode */ |
410 | if (duplex) { | |
cd1f402c | 411 | /* FD enable */ |
45993653 UKK |
412 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
413 | } else { | |
cd1f402c UKK |
414 | /* No Rcv on Xmit */ |
415 | rcntl |= 0x02; | |
45993653 UKK |
416 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
417 | } | |
cd1f402c | 418 | |
45993653 UKK |
419 | fep->full_duplex = duplex; |
420 | ||
421 | /* Set MII speed */ | |
422 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
423 | ||
424 | /* | |
425 | * The phy interface and speed need to get configured | |
426 | * differently on enet-mac. | |
427 | */ | |
428 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
429 | /* Enable flow control and length check */ |
430 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 431 | |
230dec61 SG |
432 | /* RGMII, RMII or MII */ |
433 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
434 | rcntl |= (1 << 6); | |
435 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 436 | rcntl |= (1 << 8); |
45993653 | 437 | else |
cd1f402c | 438 | rcntl &= ~(1 << 8); |
45993653 | 439 | |
230dec61 SG |
440 | /* 1G, 100M or 10M */ |
441 | if (fep->phy_dev) { | |
442 | if (fep->phy_dev->speed == SPEED_1000) | |
443 | ecntl |= (1 << 5); | |
444 | else if (fep->phy_dev->speed == SPEED_100) | |
445 | rcntl &= ~(1 << 9); | |
446 | else | |
447 | rcntl |= (1 << 9); | |
448 | } | |
45993653 UKK |
449 | } else { |
450 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 451 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 452 | u32 cfgr; |
45993653 UKK |
453 | /* disable the gasket and wait */ |
454 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
455 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
456 | udelay(1); | |
457 | ||
458 | /* | |
459 | * configure the gasket: | |
460 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 461 | * MII, 25 MHz, no loopback, no echo |
45993653 | 462 | */ |
8d82f219 EB |
463 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
464 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
465 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
466 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
467 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
468 | |
469 | /* re-enable the gasket */ | |
470 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 471 | } |
45993653 UKK |
472 | #endif |
473 | } | |
baa70a5c FL |
474 | |
475 | /* enable pause frame*/ | |
476 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
477 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
478 | fep->phy_dev && fep->phy_dev->pause)) { | |
479 | rcntl |= FEC_ENET_FCE; | |
480 | ||
481 | /* set FIFO thresh hold parameter to reduce overrun */ | |
482 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); | |
483 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
484 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
485 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
486 | ||
487 | /* OPD */ | |
488 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
489 | } else { | |
490 | rcntl &= ~FEC_ENET_FCE; | |
491 | } | |
492 | ||
cd1f402c | 493 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 494 | |
230dec61 SG |
495 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
496 | /* enable ENET endian swap */ | |
497 | ecntl |= (1 << 8); | |
498 | /* enable ENET store and forward mode */ | |
499 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
500 | } | |
501 | ||
ff43da86 FL |
502 | if (fep->bufdesc_ex) |
503 | ecntl |= (1 << 4); | |
6605b730 | 504 | |
45993653 | 505 | /* And last, enable the transmit and receive processing */ |
230dec61 | 506 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
507 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
508 | ||
ff43da86 FL |
509 | if (fep->bufdesc_ex) |
510 | fec_ptp_start_cyclecounter(ndev); | |
511 | ||
45993653 UKK |
512 | /* Enable interrupts we wish to service */ |
513 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
514 | } | |
515 | ||
516 | static void | |
517 | fec_stop(struct net_device *ndev) | |
518 | { | |
519 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
520 | const struct platform_device_id *id_entry = |
521 | platform_get_device_id(fep->pdev); | |
42431dc2 | 522 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
523 | |
524 | /* We cannot expect a graceful transmit stop without link !!! */ | |
525 | if (fep->link) { | |
526 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
527 | udelay(10); | |
528 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
529 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
530 | } | |
531 | ||
532 | /* Whack a reset. We should wait for this. */ | |
533 | writel(1, fep->hwp + FEC_ECNTRL); | |
534 | udelay(10); | |
535 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
536 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
537 | |
538 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 539 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 540 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
541 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
542 | } | |
1da177e4 LT |
543 | } |
544 | ||
545 | ||
45993653 UKK |
546 | static void |
547 | fec_timeout(struct net_device *ndev) | |
548 | { | |
549 | struct fec_enet_private *fep = netdev_priv(ndev); | |
550 | ||
551 | ndev->stats.tx_errors++; | |
552 | ||
553 | fec_restart(ndev, fep->full_duplex); | |
554 | netif_wake_queue(ndev); | |
555 | } | |
556 | ||
1da177e4 | 557 | static void |
c556167f | 558 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
559 | { |
560 | struct fec_enet_private *fep; | |
2e28532f | 561 | struct bufdesc *bdp; |
0e702ab3 | 562 | unsigned short status; |
1da177e4 | 563 | struct sk_buff *skb; |
de5fb0a0 | 564 | int index = 0; |
1da177e4 | 565 | |
c556167f | 566 | fep = netdev_priv(ndev); |
1da177e4 LT |
567 | bdp = fep->dirty_tx; |
568 | ||
de5fb0a0 FL |
569 | /* get next bdp of dirty_tx */ |
570 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
571 | bdp = fep->tx_bd_base; | |
572 | else | |
573 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
574 | ||
0e702ab3 | 575 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
de5fb0a0 FL |
576 | |
577 | /* current queue is empty */ | |
578 | if (bdp == fep->cur_tx) | |
f0b3fbea SH |
579 | break; |
580 | ||
de5fb0a0 FL |
581 | if (fep->bufdesc_ex) |
582 | index = (struct bufdesc_ex *)bdp - | |
583 | (struct bufdesc_ex *)fep->tx_bd_base; | |
584 | else | |
585 | index = bdp - fep->tx_bd_base; | |
586 | ||
d1ab1f54 UKK |
587 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
588 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 589 | bdp->cbd_bufaddr = 0; |
1da177e4 | 590 | |
de5fb0a0 FL |
591 | skb = fep->tx_skbuff[index]; |
592 | ||
1da177e4 | 593 | /* Check for errors. */ |
0e702ab3 | 594 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
595 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
596 | BD_ENET_TX_CSL)) { | |
c556167f | 597 | ndev->stats.tx_errors++; |
0e702ab3 | 598 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 599 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 600 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 601 | ndev->stats.tx_window_errors++; |
0e702ab3 | 602 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 603 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 604 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 605 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 606 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 607 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 608 | } else { |
c556167f | 609 | ndev->stats.tx_packets++; |
1da177e4 LT |
610 | } |
611 | ||
ff43da86 FL |
612 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
613 | fep->bufdesc_ex) { | |
6605b730 FL |
614 | struct skb_shared_hwtstamps shhwtstamps; |
615 | unsigned long flags; | |
ff43da86 | 616 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 FL |
617 | |
618 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
619 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
620 | shhwtstamps.hwtstamp = ns_to_ktime( | |
ff43da86 | 621 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
622 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
623 | skb_tstamp_tx(skb, &shhwtstamps); | |
624 | } | |
ff43da86 | 625 | |
0e702ab3 | 626 | if (status & BD_ENET_TX_READY) |
1da177e4 | 627 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 628 | |
1da177e4 LT |
629 | /* Deferred means some collisions occurred during transmit, |
630 | * but we eventually sent the packet OK. | |
631 | */ | |
0e702ab3 | 632 | if (status & BD_ENET_TX_DEF) |
c556167f | 633 | ndev->stats.collisions++; |
6aa20a22 | 634 | |
22f6b860 | 635 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 636 | dev_kfree_skb_any(skb); |
de5fb0a0 FL |
637 | fep->tx_skbuff[index] = NULL; |
638 | ||
639 | fep->dirty_tx = bdp; | |
6aa20a22 | 640 | |
22f6b860 | 641 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 642 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
643 | bdp = fep->tx_bd_base; |
644 | else | |
ff43da86 | 645 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
6aa20a22 | 646 | |
22f6b860 | 647 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 648 | */ |
de5fb0a0 | 649 | if (fep->dirty_tx != fep->cur_tx) { |
c556167f UKK |
650 | if (netif_queue_stopped(ndev)) |
651 | netif_wake_queue(ndev); | |
1da177e4 LT |
652 | } |
653 | } | |
de5fb0a0 | 654 | return; |
1da177e4 LT |
655 | } |
656 | ||
657 | ||
658 | /* During a receive, the cur_rx points to the current incoming buffer. | |
659 | * When we update through the ring, if the next incoming buffer has | |
660 | * not been given to the system, we just set the empty indicator, | |
661 | * effectively tossing the packet. | |
662 | */ | |
dc975382 FL |
663 | static int |
664 | fec_enet_rx(struct net_device *ndev, int budget) | |
1da177e4 | 665 | { |
c556167f | 666 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
667 | const struct platform_device_id *id_entry = |
668 | platform_get_device_id(fep->pdev); | |
2e28532f | 669 | struct bufdesc *bdp; |
0e702ab3 | 670 | unsigned short status; |
1da177e4 LT |
671 | struct sk_buff *skb; |
672 | ushort pkt_len; | |
673 | __u8 *data; | |
dc975382 | 674 | int pkt_received = 0; |
6aa20a22 | 675 | |
0e702ab3 GU |
676 | #ifdef CONFIG_M532x |
677 | flush_cache_all(); | |
6aa20a22 | 678 | #endif |
1da177e4 | 679 | |
1da177e4 LT |
680 | /* First, grab all of the stats for the incoming packet. |
681 | * These get messed up if we get called due to a busy condition. | |
682 | */ | |
683 | bdp = fep->cur_rx; | |
684 | ||
22f6b860 | 685 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 686 | |
dc975382 FL |
687 | if (pkt_received >= budget) |
688 | break; | |
689 | pkt_received++; | |
690 | ||
22f6b860 SH |
691 | /* Since we have allocated space to hold a complete frame, |
692 | * the last indicator should be set. | |
693 | */ | |
694 | if ((status & BD_ENET_RX_LAST) == 0) | |
695 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 696 | |
22f6b860 SH |
697 | if (!fep->opened) |
698 | goto rx_processing_done; | |
1da177e4 | 699 | |
22f6b860 SH |
700 | /* Check for errors. */ |
701 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 702 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 703 | ndev->stats.rx_errors++; |
22f6b860 SH |
704 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
705 | /* Frame too long or too short. */ | |
c556167f | 706 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
707 | } |
708 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 709 | ndev->stats.rx_frame_errors++; |
22f6b860 | 710 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 711 | ndev->stats.rx_crc_errors++; |
22f6b860 | 712 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 713 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 714 | } |
1da177e4 | 715 | |
22f6b860 SH |
716 | /* Report late collisions as a frame error. |
717 | * On this error, the BD is closed, but we don't know what we | |
718 | * have in the buffer. So, just drop this frame on the floor. | |
719 | */ | |
720 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
721 | ndev->stats.rx_errors++; |
722 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
723 | goto rx_processing_done; |
724 | } | |
1da177e4 | 725 | |
22f6b860 | 726 | /* Process the incoming frame. */ |
c556167f | 727 | ndev->stats.rx_packets++; |
22f6b860 | 728 | pkt_len = bdp->cbd_datlen; |
c556167f | 729 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 730 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 731 | |
d1ab1f54 UKK |
732 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
733 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 734 | |
b5680e0b SG |
735 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
736 | swap_buffer(data, pkt_len); | |
737 | ||
22f6b860 SH |
738 | /* This does 16 byte alignment, exactly what we need. |
739 | * The packet length includes FCS, but we don't want to | |
740 | * include that when passing upstream as it messes up | |
741 | * bridging applications. | |
742 | */ | |
b72061a3 | 743 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 744 | |
8549889c | 745 | if (unlikely(!skb)) { |
22f6b860 | 746 | printk("%s: Memory squeeze, dropping packet.\n", |
c556167f UKK |
747 | ndev->name); |
748 | ndev->stats.rx_dropped++; | |
22f6b860 | 749 | } else { |
8549889c | 750 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
751 | skb_put(skb, pkt_len - 4); /* Make room */ |
752 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 753 | skb->protocol = eth_type_trans(skb, ndev); |
ff43da86 | 754 | |
6605b730 | 755 | /* Get receive timestamp from the skb */ |
ff43da86 | 756 | if (fep->hwts_rx_en && fep->bufdesc_ex) { |
6605b730 FL |
757 | struct skb_shared_hwtstamps *shhwtstamps = |
758 | skb_hwtstamps(skb); | |
759 | unsigned long flags; | |
ff43da86 FL |
760 | struct bufdesc_ex *ebdp = |
761 | (struct bufdesc_ex *)bdp; | |
6605b730 FL |
762 | |
763 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
764 | ||
765 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
766 | shhwtstamps->hwtstamp = ns_to_ktime( | |
ff43da86 | 767 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
768 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
769 | } | |
ff43da86 | 770 | |
18a03b97 | 771 | if (!skb_defer_rx_timestamp(skb)) |
dc975382 | 772 | napi_gro_receive(&fep->napi, skb); |
22f6b860 | 773 | } |
f0b3fbea | 774 | |
d1ab1f54 UKK |
775 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
776 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
777 | rx_processing_done: |
778 | /* Clear the status flags for this buffer */ | |
779 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 780 | |
22f6b860 SH |
781 | /* Mark the buffer empty */ |
782 | status |= BD_ENET_RX_EMPTY; | |
783 | bdp->cbd_sc = status; | |
6aa20a22 | 784 | |
ff43da86 FL |
785 | if (fep->bufdesc_ex) { |
786 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
787 | ||
788 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
789 | ebdp->cbd_prot = 0; | |
790 | ebdp->cbd_bdu = 0; | |
791 | } | |
6605b730 | 792 | |
22f6b860 SH |
793 | /* Update BD pointer to next entry */ |
794 | if (status & BD_ENET_RX_WRAP) | |
795 | bdp = fep->rx_bd_base; | |
796 | else | |
ff43da86 | 797 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
22f6b860 SH |
798 | /* Doing this here will keep the FEC running while we process |
799 | * incoming frames. On a heavily loaded network, we should be | |
800 | * able to keep up at the expense of system resources. | |
801 | */ | |
802 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
803 | } | |
2e28532f | 804 | fep->cur_rx = bdp; |
1da177e4 | 805 | |
dc975382 | 806 | return pkt_received; |
1da177e4 LT |
807 | } |
808 | ||
45993653 UKK |
809 | static irqreturn_t |
810 | fec_enet_interrupt(int irq, void *dev_id) | |
811 | { | |
812 | struct net_device *ndev = dev_id; | |
813 | struct fec_enet_private *fep = netdev_priv(ndev); | |
814 | uint int_events; | |
815 | irqreturn_t ret = IRQ_NONE; | |
816 | ||
817 | do { | |
818 | int_events = readl(fep->hwp + FEC_IEVENT); | |
819 | writel(int_events, fep->hwp + FEC_IEVENT); | |
820 | ||
de5fb0a0 | 821 | if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { |
45993653 | 822 | ret = IRQ_HANDLED; |
dc975382 FL |
823 | |
824 | /* Disable the RX interrupt */ | |
825 | if (napi_schedule_prep(&fep->napi)) { | |
826 | writel(FEC_RX_DISABLED_IMASK, | |
827 | fep->hwp + FEC_IMASK); | |
828 | __napi_schedule(&fep->napi); | |
829 | } | |
45993653 UKK |
830 | } |
831 | ||
45993653 UKK |
832 | if (int_events & FEC_ENET_MII) { |
833 | ret = IRQ_HANDLED; | |
834 | complete(&fep->mdio_done); | |
835 | } | |
836 | } while (int_events); | |
837 | ||
838 | return ret; | |
839 | } | |
840 | ||
dc975382 FL |
841 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
842 | { | |
843 | struct net_device *ndev = napi->dev; | |
844 | int pkts = fec_enet_rx(ndev, budget); | |
845 | struct fec_enet_private *fep = netdev_priv(ndev); | |
45993653 | 846 | |
de5fb0a0 FL |
847 | fec_enet_tx(ndev); |
848 | ||
dc975382 FL |
849 | if (pkts < budget) { |
850 | napi_complete(napi); | |
851 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
852 | } | |
853 | return pkts; | |
854 | } | |
45993653 | 855 | |
e6b043d5 | 856 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 857 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 858 | { |
c556167f | 859 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 860 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 861 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 862 | |
49da97dc SG |
863 | /* |
864 | * try to get mac address in following order: | |
865 | * | |
866 | * 1) module parameter via kernel command line in form | |
867 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
868 | */ | |
869 | iap = macaddr; | |
870 | ||
ca2cc333 SG |
871 | #ifdef CONFIG_OF |
872 | /* | |
873 | * 2) from device tree data | |
874 | */ | |
875 | if (!is_valid_ether_addr(iap)) { | |
876 | struct device_node *np = fep->pdev->dev.of_node; | |
877 | if (np) { | |
878 | const char *mac = of_get_mac_address(np); | |
879 | if (mac) | |
880 | iap = (unsigned char *) mac; | |
881 | } | |
882 | } | |
883 | #endif | |
884 | ||
49da97dc | 885 | /* |
ca2cc333 | 886 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
887 | */ |
888 | if (!is_valid_ether_addr(iap)) { | |
889 | #ifdef CONFIG_M5272 | |
890 | if (FEC_FLASHMAC) | |
891 | iap = (unsigned char *)FEC_FLASHMAC; | |
892 | #else | |
893 | if (pdata) | |
589efdc7 | 894 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
895 | #endif |
896 | } | |
897 | ||
898 | /* | |
ca2cc333 | 899 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
900 | */ |
901 | if (!is_valid_ether_addr(iap)) { | |
902 | *((unsigned long *) &tmpaddr[0]) = | |
903 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
904 | *((unsigned short *) &tmpaddr[4]) = | |
905 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 906 | iap = &tmpaddr[0]; |
1da177e4 LT |
907 | } |
908 | ||
c556167f | 909 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 910 | |
49da97dc SG |
911 | /* Adjust MAC if using macaddr */ |
912 | if (iap == macaddr) | |
43af940c | 913 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
914 | } |
915 | ||
e6b043d5 | 916 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 917 | |
e6b043d5 BW |
918 | /* |
919 | * Phy section | |
920 | */ | |
c556167f | 921 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 922 | { |
c556167f | 923 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 BW |
924 | struct phy_device *phy_dev = fep->phy_dev; |
925 | unsigned long flags; | |
1da177e4 | 926 | |
e6b043d5 | 927 | int status_change = 0; |
1da177e4 | 928 | |
e6b043d5 | 929 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 930 | |
e6b043d5 BW |
931 | /* Prevent a state halted on mii error */ |
932 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
933 | phy_dev->state = PHY_RESUMING; | |
934 | goto spin_unlock; | |
935 | } | |
1da177e4 | 936 | |
e6b043d5 | 937 | if (phy_dev->link) { |
d97e7497 | 938 | if (!fep->link) { |
6ea0722f | 939 | fep->link = phy_dev->link; |
e6b043d5 BW |
940 | status_change = 1; |
941 | } | |
1da177e4 | 942 | |
d97e7497 LS |
943 | if (fep->full_duplex != phy_dev->duplex) |
944 | status_change = 1; | |
945 | ||
946 | if (phy_dev->speed != fep->speed) { | |
947 | fep->speed = phy_dev->speed; | |
948 | status_change = 1; | |
949 | } | |
950 | ||
951 | /* if any of the above changed restart the FEC */ | |
952 | if (status_change) | |
c556167f | 953 | fec_restart(ndev, phy_dev->duplex); |
d97e7497 LS |
954 | } else { |
955 | if (fep->link) { | |
c556167f | 956 | fec_stop(ndev); |
d97e7497 LS |
957 | status_change = 1; |
958 | } | |
1da177e4 | 959 | } |
6aa20a22 | 960 | |
e6b043d5 BW |
961 | spin_unlock: |
962 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 963 | |
e6b043d5 BW |
964 | if (status_change) |
965 | phy_print_status(phy_dev); | |
966 | } | |
1da177e4 | 967 | |
e6b043d5 | 968 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 969 | { |
e6b043d5 | 970 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 971 | unsigned long time_left; |
1da177e4 | 972 | |
e6b043d5 | 973 | fep->mii_timeout = 0; |
97b72e43 | 974 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
975 | |
976 | /* start a read op */ | |
977 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
978 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
979 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
980 | ||
981 | /* wait for end of transfer */ | |
97b72e43 BS |
982 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
983 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
984 | if (time_left == 0) { | |
985 | fep->mii_timeout = 1; | |
986 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
987 | return -ETIMEDOUT; | |
1da177e4 | 988 | } |
1da177e4 | 989 | |
e6b043d5 BW |
990 | /* return value */ |
991 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 992 | } |
6aa20a22 | 993 | |
e6b043d5 BW |
994 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
995 | u16 value) | |
1da177e4 | 996 | { |
e6b043d5 | 997 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 998 | unsigned long time_left; |
1da177e4 | 999 | |
e6b043d5 | 1000 | fep->mii_timeout = 0; |
97b72e43 | 1001 | init_completion(&fep->mdio_done); |
1da177e4 | 1002 | |
862f0982 SG |
1003 | /* start a write op */ |
1004 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1005 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1006 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1007 | fep->hwp + FEC_MII_DATA); | |
1008 | ||
1009 | /* wait for end of transfer */ | |
97b72e43 BS |
1010 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1011 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1012 | if (time_left == 0) { | |
1013 | fep->mii_timeout = 1; | |
1014 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
1015 | return -ETIMEDOUT; | |
e6b043d5 | 1016 | } |
1da177e4 | 1017 | |
e6b043d5 BW |
1018 | return 0; |
1019 | } | |
1da177e4 | 1020 | |
e6b043d5 | 1021 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 1022 | { |
e6b043d5 | 1023 | return 0; |
1da177e4 LT |
1024 | } |
1025 | ||
c556167f | 1026 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1027 | { |
c556167f | 1028 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
1029 | const struct platform_device_id *id_entry = |
1030 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1031 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1032 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1033 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1034 | int phy_id; | |
43af940c | 1035 | int dev_id = fep->dev_id; |
562d2f8c | 1036 | |
418bd0d4 BW |
1037 | fep->phy_dev = NULL; |
1038 | ||
6fcc040f GU |
1039 | /* check for attached phy */ |
1040 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
1041 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
1042 | continue; | |
1043 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
1044 | continue; | |
1045 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
1046 | continue; | |
b5680e0b SG |
1047 | if (dev_id--) |
1048 | continue; | |
6fcc040f GU |
1049 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
1050 | break; | |
e6b043d5 | 1051 | } |
1da177e4 | 1052 | |
6fcc040f | 1053 | if (phy_id >= PHY_MAX_ADDR) { |
a7dd3219 LW |
1054 | printk(KERN_INFO |
1055 | "%s: no PHY, assuming direct connection to switch\n", | |
1056 | ndev->name); | |
ea51ade9 | 1057 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
1058 | phy_id = 0; |
1059 | } | |
1060 | ||
a7ed07d5 | 1061 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
f9a8f83b | 1062 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
230dec61 | 1063 | fep->phy_interface); |
6fcc040f | 1064 | if (IS_ERR(phy_dev)) { |
c556167f | 1065 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); |
6fcc040f | 1066 | return PTR_ERR(phy_dev); |
e6b043d5 | 1067 | } |
1da177e4 | 1068 | |
e6b043d5 | 1069 | /* mask with MAC supported features */ |
baa70a5c | 1070 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1071 | phy_dev->supported &= PHY_GBIT_FEATURES; |
baa70a5c FL |
1072 | phy_dev->supported |= SUPPORTED_Pause; |
1073 | } | |
230dec61 SG |
1074 | else |
1075 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1076 | ||
e6b043d5 | 1077 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1078 | |
e6b043d5 BW |
1079 | fep->phy_dev = phy_dev; |
1080 | fep->link = 0; | |
1081 | fep->full_duplex = 0; | |
1da177e4 | 1082 | |
a7dd3219 LW |
1083 | printk(KERN_INFO |
1084 | "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
1085 | ndev->name, | |
418bd0d4 BW |
1086 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
1087 | fep->phy_dev->irq); | |
1088 | ||
e6b043d5 | 1089 | return 0; |
1da177e4 LT |
1090 | } |
1091 | ||
e6b043d5 | 1092 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1093 | { |
b5680e0b | 1094 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1095 | struct net_device *ndev = platform_get_drvdata(pdev); |
1096 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1097 | const struct platform_device_id *id_entry = |
1098 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1099 | int err = -ENXIO, i; |
6b265293 | 1100 | |
b5680e0b SG |
1101 | /* |
1102 | * The dual fec interfaces are not equivalent with enet-mac. | |
1103 | * Here are the differences: | |
1104 | * | |
1105 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1106 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1107 | * - external phys can only be configured by fec0 | |
1108 | * | |
1109 | * That is to say fec1 can not work independently. It only works | |
1110 | * when fec0 is working. The reason behind this design is that the | |
1111 | * second interface is added primarily for Switch mode. | |
1112 | * | |
1113 | * Because of the last point above, both phys are attached on fec0 | |
1114 | * mdio interface in board design, and need to be configured by | |
1115 | * fec0 mii_bus. | |
1116 | */ | |
43af940c | 1117 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1118 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1119 | if (mii_cnt && fec0_mii_bus) { |
1120 | fep->mii_bus = fec0_mii_bus; | |
1121 | mii_cnt++; | |
1122 | return 0; | |
1123 | } | |
1124 | return -ENOENT; | |
b5680e0b SG |
1125 | } |
1126 | ||
e6b043d5 | 1127 | fep->mii_timeout = 0; |
1da177e4 | 1128 | |
e6b043d5 BW |
1129 | /* |
1130 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1131 | * |
1132 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1133 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1134 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1135 | * document. | |
e6b043d5 | 1136 | */ |
f4d40de3 | 1137 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1138 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1139 | fep->phy_speed--; | |
1140 | fep->phy_speed <<= 1; | |
e6b043d5 | 1141 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1142 | |
e6b043d5 BW |
1143 | fep->mii_bus = mdiobus_alloc(); |
1144 | if (fep->mii_bus == NULL) { | |
1145 | err = -ENOMEM; | |
1146 | goto err_out; | |
1da177e4 LT |
1147 | } |
1148 | ||
e6b043d5 BW |
1149 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1150 | fep->mii_bus->read = fec_enet_mdio_read; | |
1151 | fep->mii_bus->write = fec_enet_mdio_write; | |
1152 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1153 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1154 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1155 | fep->mii_bus->priv = fep; |
1156 | fep->mii_bus->parent = &pdev->dev; | |
1157 | ||
1158 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1159 | if (!fep->mii_bus->irq) { | |
1160 | err = -ENOMEM; | |
1161 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1162 | } |
1163 | ||
e6b043d5 BW |
1164 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1165 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1166 | |
e6b043d5 BW |
1167 | if (mdiobus_register(fep->mii_bus)) |
1168 | goto err_out_free_mdio_irq; | |
1da177e4 | 1169 | |
e163cc97 LW |
1170 | mii_cnt++; |
1171 | ||
b5680e0b SG |
1172 | /* save fec0 mii_bus */ |
1173 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1174 | fec0_mii_bus = fep->mii_bus; | |
1175 | ||
e6b043d5 | 1176 | return 0; |
1da177e4 | 1177 | |
e6b043d5 BW |
1178 | err_out_free_mdio_irq: |
1179 | kfree(fep->mii_bus->irq); | |
1180 | err_out_free_mdiobus: | |
1181 | mdiobus_free(fep->mii_bus); | |
1182 | err_out: | |
1183 | return err; | |
1da177e4 LT |
1184 | } |
1185 | ||
e6b043d5 | 1186 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1187 | { |
e163cc97 LW |
1188 | if (--mii_cnt == 0) { |
1189 | mdiobus_unregister(fep->mii_bus); | |
1190 | kfree(fep->mii_bus->irq); | |
1191 | mdiobus_free(fep->mii_bus); | |
1192 | } | |
1da177e4 LT |
1193 | } |
1194 | ||
c556167f | 1195 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1196 | struct ethtool_cmd *cmd) |
1da177e4 | 1197 | { |
c556167f | 1198 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1199 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1200 | |
e6b043d5 BW |
1201 | if (!phydev) |
1202 | return -ENODEV; | |
1da177e4 | 1203 | |
e6b043d5 | 1204 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1205 | } |
1206 | ||
c556167f | 1207 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1208 | struct ethtool_cmd *cmd) |
1da177e4 | 1209 | { |
c556167f | 1210 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1211 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1212 | |
e6b043d5 BW |
1213 | if (!phydev) |
1214 | return -ENODEV; | |
1da177e4 | 1215 | |
e6b043d5 | 1216 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1217 | } |
1218 | ||
c556167f | 1219 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1220 | struct ethtool_drvinfo *info) |
1da177e4 | 1221 | { |
c556167f | 1222 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1223 | |
7826d43f JP |
1224 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
1225 | sizeof(info->driver)); | |
1226 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
1227 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1228 | } |
1229 | ||
5ebae489 FL |
1230 | static int fec_enet_get_ts_info(struct net_device *ndev, |
1231 | struct ethtool_ts_info *info) | |
1232 | { | |
1233 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1234 | ||
1235 | if (fep->bufdesc_ex) { | |
1236 | ||
1237 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1238 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1239 | SOF_TIMESTAMPING_SOFTWARE | | |
1240 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1241 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1242 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1243 | if (fep->ptp_clock) | |
1244 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
1245 | else | |
1246 | info->phc_index = -1; | |
1247 | ||
1248 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
1249 | (1 << HWTSTAMP_TX_ON); | |
1250 | ||
1251 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
1252 | (1 << HWTSTAMP_FILTER_ALL); | |
1253 | return 0; | |
1254 | } else { | |
1255 | return ethtool_op_get_ts_info(ndev, info); | |
1256 | } | |
1257 | } | |
1258 | ||
baa70a5c FL |
1259 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
1260 | struct ethtool_pauseparam *pause) | |
1261 | { | |
1262 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1263 | ||
1264 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
1265 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
1266 | pause->rx_pause = pause->tx_pause; | |
1267 | } | |
1268 | ||
1269 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
1270 | struct ethtool_pauseparam *pause) | |
1271 | { | |
1272 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1273 | ||
1274 | if (pause->tx_pause != pause->rx_pause) { | |
1275 | netdev_info(ndev, | |
1276 | "hardware only support enable/disable both tx and rx"); | |
1277 | return -EINVAL; | |
1278 | } | |
1279 | ||
1280 | fep->pause_flag = 0; | |
1281 | ||
1282 | /* tx pause must be same as rx pause */ | |
1283 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
1284 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
1285 | ||
1286 | if (pause->rx_pause || pause->autoneg) { | |
1287 | fep->phy_dev->supported |= ADVERTISED_Pause; | |
1288 | fep->phy_dev->advertising |= ADVERTISED_Pause; | |
1289 | } else { | |
1290 | fep->phy_dev->supported &= ~ADVERTISED_Pause; | |
1291 | fep->phy_dev->advertising &= ~ADVERTISED_Pause; | |
1292 | } | |
1293 | ||
1294 | if (pause->autoneg) { | |
1295 | if (netif_running(ndev)) | |
1296 | fec_stop(ndev); | |
1297 | phy_start_aneg(fep->phy_dev); | |
1298 | } | |
1299 | if (netif_running(ndev)) | |
1300 | fec_restart(ndev, 0); | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
9b07be4b | 1305 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
baa70a5c FL |
1306 | .get_pauseparam = fec_enet_get_pauseparam, |
1307 | .set_pauseparam = fec_enet_set_pauseparam, | |
e6b043d5 BW |
1308 | .get_settings = fec_enet_get_settings, |
1309 | .set_settings = fec_enet_set_settings, | |
1310 | .get_drvinfo = fec_enet_get_drvinfo, | |
1311 | .get_link = ethtool_op_get_link, | |
5ebae489 | 1312 | .get_ts_info = fec_enet_get_ts_info, |
e6b043d5 | 1313 | }; |
1da177e4 | 1314 | |
c556167f | 1315 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1316 | { |
c556167f | 1317 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1318 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1319 | |
c556167f | 1320 | if (!netif_running(ndev)) |
e6b043d5 | 1321 | return -EINVAL; |
1da177e4 | 1322 | |
e6b043d5 BW |
1323 | if (!phydev) |
1324 | return -ENODEV; | |
1325 | ||
ff43da86 | 1326 | if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) |
6605b730 | 1327 | return fec_ptp_ioctl(ndev, rq, cmd); |
ff43da86 | 1328 | |
28b04113 | 1329 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1330 | } |
1331 | ||
c556167f | 1332 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1333 | { |
c556167f | 1334 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1335 | int i; |
1336 | struct sk_buff *skb; | |
1337 | struct bufdesc *bdp; | |
1338 | ||
1339 | bdp = fep->rx_bd_base; | |
1340 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1341 | skb = fep->rx_skbuff[i]; | |
1342 | ||
1343 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1344 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1345 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1346 | if (skb) | |
1347 | dev_kfree_skb(skb); | |
ff43da86 | 1348 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1349 | } |
1350 | ||
1351 | bdp = fep->tx_bd_base; | |
1352 | for (i = 0; i < TX_RING_SIZE; i++) | |
1353 | kfree(fep->tx_bounce[i]); | |
1354 | } | |
1355 | ||
c556167f | 1356 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1357 | { |
c556167f | 1358 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1359 | int i; |
1360 | struct sk_buff *skb; | |
1361 | struct bufdesc *bdp; | |
1362 | ||
1363 | bdp = fep->rx_bd_base; | |
1364 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1365 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1366 | if (!skb) { |
c556167f | 1367 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1368 | return -ENOMEM; |
1369 | } | |
1370 | fep->rx_skbuff[i] = skb; | |
1371 | ||
d1ab1f54 | 1372 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1373 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1374 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
ff43da86 FL |
1375 | |
1376 | if (fep->bufdesc_ex) { | |
1377 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1378 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1379 | } | |
1380 | ||
1381 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1382 | } |
1383 | ||
1384 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1385 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1386 | bdp->cbd_sc |= BD_SC_WRAP; |
1387 | ||
1388 | bdp = fep->tx_bd_base; | |
1389 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1390 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1391 | ||
1392 | bdp->cbd_sc = 0; | |
1393 | bdp->cbd_bufaddr = 0; | |
6605b730 | 1394 | |
ff43da86 FL |
1395 | if (fep->bufdesc_ex) { |
1396 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1397 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1398 | } | |
1399 | ||
1400 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1401 | } |
1402 | ||
1403 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1404 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1405 | bdp->cbd_sc |= BD_SC_WRAP; |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
1da177e4 | 1410 | static int |
c556167f | 1411 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1412 | { |
c556167f | 1413 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1414 | int ret; |
1da177e4 | 1415 | |
dc975382 FL |
1416 | napi_enable(&fep->napi); |
1417 | ||
1da177e4 LT |
1418 | /* I should reset the ring buffers here, but I don't yet know |
1419 | * a simple way to do that. | |
1420 | */ | |
1da177e4 | 1421 | |
c556167f | 1422 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1423 | if (ret) |
1424 | return ret; | |
1425 | ||
418bd0d4 | 1426 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1427 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1428 | if (ret) { |
c556167f | 1429 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1430 | return ret; |
1431 | } | |
e6b043d5 | 1432 | phy_start(fep->phy_dev); |
c556167f | 1433 | netif_start_queue(ndev); |
1da177e4 | 1434 | fep->opened = 1; |
22f6b860 | 1435 | return 0; |
1da177e4 LT |
1436 | } |
1437 | ||
1438 | static int | |
c556167f | 1439 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1440 | { |
c556167f | 1441 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1442 | |
22f6b860 | 1443 | /* Don't know what to do yet. */ |
3f104c38 | 1444 | napi_disable(&fep->napi); |
1da177e4 | 1445 | fep->opened = 0; |
c556167f UKK |
1446 | netif_stop_queue(ndev); |
1447 | fec_stop(ndev); | |
1da177e4 | 1448 | |
e497ba82 UKK |
1449 | if (fep->phy_dev) { |
1450 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1451 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1452 | } |
418bd0d4 | 1453 | |
db8880bc | 1454 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1455 | |
1da177e4 LT |
1456 | return 0; |
1457 | } | |
1458 | ||
1da177e4 LT |
1459 | /* Set or clear the multicast filter for this adaptor. |
1460 | * Skeleton taken from sunlance driver. | |
1461 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1462 | * MAC address filtering. Some of the drivers check to make sure it is | |
1463 | * a group multicast address, and discard those that are not. I guess I | |
1464 | * will do the same for now, but just remove the test if you want | |
1465 | * individual filtering as well (do the upper net layers want or support | |
1466 | * this kind of feature?). | |
1467 | */ | |
1468 | ||
1469 | #define HASH_BITS 6 /* #bits in hash */ | |
1470 | #define CRC32_POLY 0xEDB88320 | |
1471 | ||
c556167f | 1472 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1473 | { |
c556167f | 1474 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1475 | struct netdev_hw_addr *ha; |
48e2f183 | 1476 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1477 | unsigned char hash; |
1478 | ||
c556167f | 1479 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1480 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1481 | tmp |= 0x8; | |
1482 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1483 | return; |
1484 | } | |
1da177e4 | 1485 | |
4e831836 SH |
1486 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1487 | tmp &= ~0x8; | |
1488 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1489 | ||
c556167f | 1490 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1491 | /* Catch all multicast addresses, so set the |
1492 | * filter to all 1's | |
1493 | */ | |
1494 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1495 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1496 | ||
1497 | return; | |
1498 | } | |
1499 | ||
1500 | /* Clear filter and add the addresses in hash register | |
1501 | */ | |
1502 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1503 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1504 | ||
c556167f | 1505 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1506 | /* calculate crc32 value of mac address */ |
1507 | crc = 0xffffffff; | |
1508 | ||
c556167f | 1509 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1510 | data = ha->addr[i]; |
4e831836 SH |
1511 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1512 | crc = (crc >> 1) ^ | |
1513 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1514 | } |
1515 | } | |
4e831836 SH |
1516 | |
1517 | /* only upper 6 bits (HASH_BITS) are used | |
1518 | * which point to specific bit in he hash registers | |
1519 | */ | |
1520 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1521 | ||
1522 | if (hash > 31) { | |
1523 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1524 | tmp |= 1 << (hash - 32); | |
1525 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1526 | } else { | |
1527 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1528 | tmp |= 1 << hash; | |
1529 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1530 | } | |
1da177e4 LT |
1531 | } |
1532 | } | |
1533 | ||
22f6b860 | 1534 | /* Set a MAC change in hardware. */ |
009fda83 | 1535 | static int |
c556167f | 1536 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1537 | { |
c556167f | 1538 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1539 | struct sockaddr *addr = p; |
1540 | ||
1541 | if (!is_valid_ether_addr(addr->sa_data)) | |
1542 | return -EADDRNOTAVAIL; | |
1543 | ||
c556167f | 1544 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1545 | |
c556167f UKK |
1546 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1547 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1548 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1549 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1550 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1551 | return 0; |
1da177e4 LT |
1552 | } |
1553 | ||
7f5c6add | 1554 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1555 | /** |
1556 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1557 | * @dev: The FEC network adapter |
1558 | * | |
1559 | * Polled functionality used by netconsole and others in non interrupt mode | |
1560 | * | |
1561 | */ | |
1562 | void fec_poll_controller(struct net_device *dev) | |
1563 | { | |
1564 | int i; | |
1565 | struct fec_enet_private *fep = netdev_priv(dev); | |
1566 | ||
1567 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1568 | if (fep->irq[i] > 0) { | |
1569 | disable_irq(fep->irq[i]); | |
1570 | fec_enet_interrupt(fep->irq[i], dev); | |
1571 | enable_irq(fep->irq[i]); | |
1572 | } | |
1573 | } | |
1574 | } | |
1575 | #endif | |
1576 | ||
009fda83 SH |
1577 | static const struct net_device_ops fec_netdev_ops = { |
1578 | .ndo_open = fec_enet_open, | |
1579 | .ndo_stop = fec_enet_close, | |
1580 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1581 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1582 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1583 | .ndo_validate_addr = eth_validate_addr, |
1584 | .ndo_tx_timeout = fec_timeout, | |
1585 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1586 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1587 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1588 | .ndo_poll_controller = fec_poll_controller, | |
1589 | #endif | |
009fda83 SH |
1590 | }; |
1591 | ||
1da177e4 LT |
1592 | /* |
1593 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1594 | * |
1da177e4 | 1595 | */ |
c556167f | 1596 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1597 | { |
c556167f | 1598 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1599 | struct bufdesc *cbd_base; |
633e7533 | 1600 | struct bufdesc *bdp; |
f0b3fbea | 1601 | int i; |
1da177e4 | 1602 | |
8d4dd5cf SH |
1603 | /* Allocate memory for buffer descriptors. */ |
1604 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1605 | GFP_KERNEL); | |
1606 | if (!cbd_base) { | |
562d2f8c GU |
1607 | printk("FEC: allocate descriptor memory failed?\n"); |
1608 | return -ENOMEM; | |
1609 | } | |
1610 | ||
3b2b74ca | 1611 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1612 | |
c556167f | 1613 | fep->netdev = ndev; |
1da177e4 | 1614 | |
49da97dc | 1615 | /* Get the Ethernet address */ |
c556167f | 1616 | fec_get_mac(ndev); |
1da177e4 | 1617 | |
8d4dd5cf | 1618 | /* Set receive and transmit descriptor base. */ |
1da177e4 | 1619 | fep->rx_bd_base = cbd_base; |
ff43da86 FL |
1620 | if (fep->bufdesc_ex) |
1621 | fep->tx_bd_base = (struct bufdesc *) | |
1622 | (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); | |
1623 | else | |
1624 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1da177e4 | 1625 | |
22f6b860 | 1626 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1627 | ndev->watchdog_timeo = TX_TIMEOUT; |
1628 | ndev->netdev_ops = &fec_netdev_ops; | |
1629 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 1630 | |
dc975382 FL |
1631 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
1632 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); | |
1633 | ||
633e7533 RH |
1634 | /* Initialize the receive buffer descriptors. */ |
1635 | bdp = fep->rx_bd_base; | |
1636 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1637 | ||
1638 | /* Initialize the BD for every fragment in the page. */ | |
1639 | bdp->cbd_sc = 0; | |
ff43da86 | 1640 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
633e7533 RH |
1641 | } |
1642 | ||
1643 | /* Set the last buffer to wrap */ | |
ff43da86 | 1644 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
633e7533 RH |
1645 | bdp->cbd_sc |= BD_SC_WRAP; |
1646 | ||
1647 | /* ...and the same for transmit */ | |
1648 | bdp = fep->tx_bd_base; | |
de5fb0a0 | 1649 | fep->cur_tx = bdp; |
633e7533 RH |
1650 | for (i = 0; i < TX_RING_SIZE; i++) { |
1651 | ||
1652 | /* Initialize the BD for every fragment in the page. */ | |
1653 | bdp->cbd_sc = 0; | |
1654 | bdp->cbd_bufaddr = 0; | |
ff43da86 | 1655 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
633e7533 RH |
1656 | } |
1657 | ||
1658 | /* Set the last buffer to wrap */ | |
ff43da86 | 1659 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
633e7533 | 1660 | bdp->cbd_sc |= BD_SC_WRAP; |
de5fb0a0 | 1661 | fep->dirty_tx = bdp; |
633e7533 | 1662 | |
c556167f | 1663 | fec_restart(ndev, 0); |
1da177e4 | 1664 | |
1da177e4 LT |
1665 | return 0; |
1666 | } | |
1667 | ||
ca2cc333 | 1668 | #ifdef CONFIG_OF |
33897cc8 | 1669 | static int fec_get_phy_mode_dt(struct platform_device *pdev) |
ca2cc333 SG |
1670 | { |
1671 | struct device_node *np = pdev->dev.of_node; | |
1672 | ||
1673 | if (np) | |
1674 | return of_get_phy_mode(np); | |
1675 | ||
1676 | return -ENODEV; | |
1677 | } | |
1678 | ||
33897cc8 | 1679 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1680 | { |
1681 | int err, phy_reset; | |
a3caad0a | 1682 | int msec = 1; |
ca2cc333 SG |
1683 | struct device_node *np = pdev->dev.of_node; |
1684 | ||
1685 | if (!np) | |
a9b2c8ef | 1686 | return; |
ca2cc333 | 1687 | |
a3caad0a SG |
1688 | of_property_read_u32(np, "phy-reset-duration", &msec); |
1689 | /* A sane reset duration should not be longer than 1s */ | |
1690 | if (msec > 1000) | |
1691 | msec = 1; | |
1692 | ||
ca2cc333 | 1693 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
1694 | if (!gpio_is_valid(phy_reset)) |
1695 | return; | |
1696 | ||
119fc007 SG |
1697 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
1698 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 1699 | if (err) { |
07dcf8e9 | 1700 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 1701 | return; |
ca2cc333 | 1702 | } |
a3caad0a | 1703 | msleep(msec); |
ca2cc333 | 1704 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
1705 | } |
1706 | #else /* CONFIG_OF */ | |
0c7768a0 | 1707 | static int fec_get_phy_mode_dt(struct platform_device *pdev) |
ca2cc333 SG |
1708 | { |
1709 | return -ENODEV; | |
1710 | } | |
1711 | ||
0c7768a0 | 1712 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1713 | { |
1714 | /* | |
1715 | * In case of platform probe, the reset has been done | |
1716 | * by machine code. | |
1717 | */ | |
ca2cc333 SG |
1718 | } |
1719 | #endif /* CONFIG_OF */ | |
1720 | ||
33897cc8 | 1721 | static int |
ead73183 SH |
1722 | fec_probe(struct platform_device *pdev) |
1723 | { | |
1724 | struct fec_enet_private *fep; | |
5eb32bd0 | 1725 | struct fec_platform_data *pdata; |
ead73183 SH |
1726 | struct net_device *ndev; |
1727 | int i, irq, ret = 0; | |
1728 | struct resource *r; | |
ca2cc333 | 1729 | const struct of_device_id *of_id; |
43af940c | 1730 | static int dev_id; |
b2bccee1 | 1731 | struct pinctrl *pinctrl; |
5fa9c0fe | 1732 | struct regulator *reg_phy; |
ca2cc333 SG |
1733 | |
1734 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
1735 | if (of_id) | |
1736 | pdev->id_entry = of_id->data; | |
ead73183 SH |
1737 | |
1738 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1739 | if (!r) | |
1740 | return -ENXIO; | |
1741 | ||
1742 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1743 | if (!r) | |
1744 | return -EBUSY; | |
1745 | ||
1746 | /* Init network device */ | |
1747 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
28e2188e UKK |
1748 | if (!ndev) { |
1749 | ret = -ENOMEM; | |
1750 | goto failed_alloc_etherdev; | |
1751 | } | |
ead73183 SH |
1752 | |
1753 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1754 | ||
1755 | /* setup board info structure */ | |
1756 | fep = netdev_priv(ndev); | |
ead73183 | 1757 | |
baa70a5c FL |
1758 | /* default enable pause frame auto negotiation */ |
1759 | if (pdev->id_entry && | |
1760 | (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) | |
1761 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; | |
1762 | ||
24e531b4 | 1763 | fep->hwp = ioremap(r->start, resource_size(r)); |
e6b043d5 | 1764 | fep->pdev = pdev; |
43af940c | 1765 | fep->dev_id = dev_id++; |
ead73183 | 1766 | |
ff43da86 FL |
1767 | fep->bufdesc_ex = 0; |
1768 | ||
24e531b4 | 1769 | if (!fep->hwp) { |
ead73183 SH |
1770 | ret = -ENOMEM; |
1771 | goto failed_ioremap; | |
1772 | } | |
1773 | ||
1774 | platform_set_drvdata(pdev, ndev); | |
1775 | ||
ca2cc333 SG |
1776 | ret = fec_get_phy_mode_dt(pdev); |
1777 | if (ret < 0) { | |
1778 | pdata = pdev->dev.platform_data; | |
1779 | if (pdata) | |
1780 | fep->phy_interface = pdata->phy; | |
1781 | else | |
1782 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
1783 | } else { | |
1784 | fep->phy_interface = ret; | |
1785 | } | |
1786 | ||
b2bccee1 SG |
1787 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1788 | if (IS_ERR(pinctrl)) { | |
1789 | ret = PTR_ERR(pinctrl); | |
1790 | goto failed_pin; | |
1791 | } | |
1792 | ||
f4d40de3 SH |
1793 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1794 | if (IS_ERR(fep->clk_ipg)) { | |
1795 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
1796 | goto failed_clk; |
1797 | } | |
f4d40de3 SH |
1798 | |
1799 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1800 | if (IS_ERR(fep->clk_ahb)) { | |
1801 | ret = PTR_ERR(fep->clk_ahb); | |
1802 | goto failed_clk; | |
1803 | } | |
1804 | ||
6605b730 | 1805 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
e2f8d555 FE |
1806 | fep->bufdesc_ex = |
1807 | pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; | |
6605b730 FL |
1808 | if (IS_ERR(fep->clk_ptp)) { |
1809 | ret = PTR_ERR(fep->clk_ptp); | |
ff43da86 | 1810 | fep->bufdesc_ex = 0; |
6605b730 | 1811 | } |
6605b730 | 1812 | |
f4d40de3 SH |
1813 | clk_prepare_enable(fep->clk_ahb); |
1814 | clk_prepare_enable(fep->clk_ipg); | |
ff43da86 FL |
1815 | if (!IS_ERR(fep->clk_ptp)) |
1816 | clk_prepare_enable(fep->clk_ptp); | |
1817 | ||
5fa9c0fe SG |
1818 | reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
1819 | if (!IS_ERR(reg_phy)) { | |
1820 | ret = regulator_enable(reg_phy); | |
1821 | if (ret) { | |
1822 | dev_err(&pdev->dev, | |
1823 | "Failed to enable phy regulator: %d\n", ret); | |
1824 | goto failed_regulator; | |
1825 | } | |
1826 | } | |
1827 | ||
2ca9b2aa SG |
1828 | fec_reset_phy(pdev); |
1829 | ||
e2f8d555 FE |
1830 | if (fep->bufdesc_ex) |
1831 | fec_ptp_init(ndev, pdev); | |
1832 | ||
1833 | ret = fec_enet_init(ndev); | |
1834 | if (ret) | |
1835 | goto failed_init; | |
1836 | ||
1837 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1838 | irq = platform_get_irq(pdev, i); | |
1839 | if (irq < 0) { | |
1840 | if (i) | |
1841 | break; | |
1842 | ret = irq; | |
1843 | goto failed_irq; | |
1844 | } | |
1845 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1846 | if (ret) { | |
1847 | while (--i >= 0) { | |
1848 | irq = platform_get_irq(pdev, i); | |
1849 | free_irq(irq, ndev); | |
1850 | } | |
1851 | goto failed_irq; | |
1852 | } | |
1853 | } | |
1854 | ||
e6b043d5 BW |
1855 | ret = fec_enet_mii_init(pdev); |
1856 | if (ret) | |
1857 | goto failed_mii_init; | |
1858 | ||
03c698c9 OS |
1859 | /* Carrier starts down, phylib will bring it up */ |
1860 | netif_carrier_off(ndev); | |
1861 | ||
ead73183 SH |
1862 | ret = register_netdev(ndev); |
1863 | if (ret) | |
1864 | goto failed_register; | |
1865 | ||
1866 | return 0; | |
1867 | ||
1868 | failed_register: | |
e6b043d5 BW |
1869 | fec_enet_mii_remove(fep); |
1870 | failed_mii_init: | |
e2f8d555 FE |
1871 | failed_init: |
1872 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1873 | irq = platform_get_irq(pdev, i); | |
1874 | if (irq > 0) | |
1875 | free_irq(irq, ndev); | |
1876 | } | |
1877 | failed_irq: | |
5fa9c0fe | 1878 | failed_regulator: |
f4d40de3 SH |
1879 | clk_disable_unprepare(fep->clk_ahb); |
1880 | clk_disable_unprepare(fep->clk_ipg); | |
ff43da86 FL |
1881 | if (!IS_ERR(fep->clk_ptp)) |
1882 | clk_disable_unprepare(fep->clk_ptp); | |
b2bccee1 | 1883 | failed_pin: |
ead73183 | 1884 | failed_clk: |
24e531b4 | 1885 | iounmap(fep->hwp); |
ead73183 SH |
1886 | failed_ioremap: |
1887 | free_netdev(ndev); | |
28e2188e UKK |
1888 | failed_alloc_etherdev: |
1889 | release_mem_region(r->start, resource_size(r)); | |
ead73183 SH |
1890 | |
1891 | return ret; | |
1892 | } | |
1893 | ||
33897cc8 | 1894 | static int |
ead73183 SH |
1895 | fec_drv_remove(struct platform_device *pdev) |
1896 | { | |
1897 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1898 | struct fec_enet_private *fep = netdev_priv(ndev); | |
28e2188e | 1899 | struct resource *r; |
e163cc97 | 1900 | int i; |
ead73183 | 1901 | |
e163cc97 | 1902 | unregister_netdev(ndev); |
e6b043d5 | 1903 | fec_enet_mii_remove(fep); |
6605b730 FL |
1904 | del_timer_sync(&fep->time_keep); |
1905 | clk_disable_unprepare(fep->clk_ptp); | |
1906 | if (fep->ptp_clock) | |
1907 | ptp_clock_unregister(fep->ptp_clock); | |
f4d40de3 SH |
1908 | clk_disable_unprepare(fep->clk_ahb); |
1909 | clk_disable_unprepare(fep->clk_ipg); | |
7f7d6c28 FE |
1910 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
1911 | int irq = platform_get_irq(pdev, i); | |
1912 | if (irq > 0) | |
1913 | free_irq(irq, ndev); | |
1914 | } | |
24e531b4 | 1915 | iounmap(fep->hwp); |
ead73183 | 1916 | free_netdev(ndev); |
28e2188e UKK |
1917 | |
1918 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1919 | BUG_ON(!r); | |
1920 | release_mem_region(r->start, resource_size(r)); | |
1921 | ||
b3cde36c UKK |
1922 | platform_set_drvdata(pdev, NULL); |
1923 | ||
ead73183 SH |
1924 | return 0; |
1925 | } | |
1926 | ||
59d4289b | 1927 | #ifdef CONFIG_PM |
ead73183 | 1928 | static int |
87cad5c3 | 1929 | fec_suspend(struct device *dev) |
ead73183 | 1930 | { |
87cad5c3 | 1931 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1932 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1933 | |
04e5216d UKK |
1934 | if (netif_running(ndev)) { |
1935 | fec_stop(ndev); | |
1936 | netif_device_detach(ndev); | |
ead73183 | 1937 | } |
f4d40de3 SH |
1938 | clk_disable_unprepare(fep->clk_ahb); |
1939 | clk_disable_unprepare(fep->clk_ipg); | |
04e5216d | 1940 | |
ead73183 SH |
1941 | return 0; |
1942 | } | |
1943 | ||
1944 | static int | |
87cad5c3 | 1945 | fec_resume(struct device *dev) |
ead73183 | 1946 | { |
87cad5c3 | 1947 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1948 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1949 | |
f4d40de3 SH |
1950 | clk_prepare_enable(fep->clk_ahb); |
1951 | clk_prepare_enable(fep->clk_ipg); | |
04e5216d UKK |
1952 | if (netif_running(ndev)) { |
1953 | fec_restart(ndev, fep->full_duplex); | |
1954 | netif_device_attach(ndev); | |
ead73183 | 1955 | } |
04e5216d | 1956 | |
ead73183 SH |
1957 | return 0; |
1958 | } | |
1959 | ||
59d4289b DK |
1960 | static const struct dev_pm_ops fec_pm_ops = { |
1961 | .suspend = fec_suspend, | |
1962 | .resume = fec_resume, | |
1963 | .freeze = fec_suspend, | |
1964 | .thaw = fec_resume, | |
1965 | .poweroff = fec_suspend, | |
1966 | .restore = fec_resume, | |
1967 | }; | |
87cad5c3 | 1968 | #endif |
59d4289b | 1969 | |
ead73183 SH |
1970 | static struct platform_driver fec_driver = { |
1971 | .driver = { | |
b5680e0b | 1972 | .name = DRIVER_NAME, |
87cad5c3 EB |
1973 | .owner = THIS_MODULE, |
1974 | #ifdef CONFIG_PM | |
1975 | .pm = &fec_pm_ops, | |
1976 | #endif | |
ca2cc333 | 1977 | .of_match_table = fec_dt_ids, |
ead73183 | 1978 | }, |
b5680e0b | 1979 | .id_table = fec_devtype, |
87cad5c3 | 1980 | .probe = fec_probe, |
33897cc8 | 1981 | .remove = fec_drv_remove, |
ead73183 SH |
1982 | }; |
1983 | ||
aaca2377 | 1984 | module_platform_driver(fec_driver); |
1da177e4 LT |
1985 | |
1986 | MODULE_LICENSE("GPL"); |