Commit | Line | Data |
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d4fd0404 CM |
1 | /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ |
2 | /* Copyright 2017-2019 NXP */ | |
3 | ||
4 | #include <linux/bitops.h> | |
5 | ||
6 | /* ENETC device IDs */ | |
19971f5e YL |
7 | #define ENETC_DEV_ID_PF 0xe100 |
8 | #define ENETC_DEV_ID_VF 0xef00 | |
9 | #define ENETC_DEV_ID_PTP 0xee02 | |
d4fd0404 CM |
10 | |
11 | /* ENETC register block BAR */ | |
12 | #define ENETC_BAR_REGS 0 | |
13 | ||
14 | /** SI regs, offset: 0h */ | |
15 | #define ENETC_SIMR 0 | |
16 | #define ENETC_SIMR_EN BIT(31) | |
d382563f | 17 | #define ENETC_SIMR_RSSE BIT(0) |
d4fd0404 CM |
18 | #define ENETC_SICTR0 0x18 |
19 | #define ENETC_SICTR1 0x1c | |
20 | #define ENETC_SIPCAPR0 0x20 | |
34c6adf1 | 21 | #define ENETC_SIPCAPR0_QBV BIT(4) |
79e49982 | 22 | #define ENETC_SIPCAPR0_PSFP BIT(9) |
d382563f | 23 | #define ENETC_SIPCAPR0_RSS BIT(8) |
d4fd0404 CM |
24 | #define ENETC_SIPCAPR1 0x24 |
25 | #define ENETC_SITGTGR 0x30 | |
26 | #define ENETC_SIRBGCR 0x38 | |
27 | /* cache attribute registers for transactions initiated by ENETC */ | |
28 | #define ENETC_SICAR0 0x40 | |
29 | #define ENETC_SICAR1 0x44 | |
30 | #define ENETC_SICAR2 0x48 | |
31 | /* rd snoop, no alloc | |
32 | * wr snoop, no alloc, partial cache line update for BDs and full cache line | |
33 | * update for data | |
34 | */ | |
35 | #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 | |
36 | #define ENETC_SICAR_WR_COHERENT 0x00006727 | |
37 | #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ | |
38 | ||
39 | #define ENETC_SIPMAR0 0x80 | |
40 | #define ENETC_SIPMAR1 0x84 | |
41 | ||
beb74ac8 CM |
42 | /* VF-PF Message passing */ |
43 | #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ | |
44 | /* msg size encoding: default and max msg value of 1024B encoded as 0 */ | |
45 | static inline u32 enetc_vsi_set_msize(u32 size) | |
46 | { | |
47 | return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; | |
48 | } | |
49 | ||
50 | #define ENETC_PSIMSGRR 0x204 | |
51 | #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) | |
52 | #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ | |
53 | #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ | |
54 | #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) | |
55 | ||
56 | #define ENETC_VSIMSGSR 0x204 /* RO */ | |
57 | #define ENETC_VSIMSGSR_MB BIT(0) | |
58 | #define ENETC_VSIMSGSR_MS BIT(1) | |
59 | #define ENETC_VSIMSGSNDAR0 0x210 | |
60 | #define ENETC_VSIMSGSNDAR1 0x214 | |
61 | ||
62 | #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) | |
63 | #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) | |
64 | ||
16eb4c85 CM |
65 | /* SI statistics */ |
66 | #define ENETC_SIROCT 0x300 | |
67 | #define ENETC_SIRFRM 0x308 | |
68 | #define ENETC_SIRUCA 0x310 | |
69 | #define ENETC_SIRMCA 0x318 | |
70 | #define ENETC_SITOCT 0x320 | |
71 | #define ENETC_SITFRM 0x328 | |
72 | #define ENETC_SITUCA 0x330 | |
73 | #define ENETC_SITMCA 0x338 | |
74 | #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) | |
75 | ||
d4fd0404 CM |
76 | /* Control BDR regs */ |
77 | #define ENETC_SICBDRMR 0x800 | |
78 | #define ENETC_SICBDRSR 0x804 /* RO */ | |
79 | #define ENETC_SICBDRBAR0 0x810 | |
80 | #define ENETC_SICBDRBAR1 0x814 | |
81 | #define ENETC_SICBDRPIR 0x818 | |
82 | #define ENETC_SICBDRCIR 0x81c | |
83 | #define ENETC_SICBDRLENR 0x820 | |
84 | ||
85 | #define ENETC_SICAPR0 0x900 | |
86 | #define ENETC_SICAPR1 0x904 | |
87 | ||
88 | #define ENETC_PSIIER 0xa00 | |
89 | #define ENETC_PSIIER_MR_MASK GENMASK(2, 1) | |
90 | #define ENETC_PSIIDR 0xa08 | |
91 | #define ENETC_SITXIDR 0xa18 | |
92 | #define ENETC_SIRXIDR 0xa28 | |
93 | #define ENETC_SIMSIVR 0xa30 | |
94 | ||
95 | #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) | |
96 | #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) | |
97 | ||
98 | #define ENETC_SIUEFDCR 0xe28 | |
99 | ||
d382563f CM |
100 | #define ENETC_SIRFSCAPR 0x1200 |
101 | #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) | |
102 | #define ENETC_SIRSSCAPR 0x1600 | |
103 | #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) | |
104 | ||
d4fd0404 CM |
105 | /** SI BDR sub-blocks, n = 0..7 */ |
106 | enum enetc_bdr_type {TX, RX}; | |
107 | #define ENETC_BDR_OFF(i) ((i) * 0x200) | |
108 | #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) | |
109 | /* RX BDR reg offsets */ | |
110 | #define ENETC_RBMR 0 | |
111 | #define ENETC_RBMR_BDS BIT(2) | |
112 | #define ENETC_RBMR_VTE BIT(5) | |
113 | #define ENETC_RBMR_EN BIT(31) | |
114 | #define ENETC_RBSR 0x4 | |
115 | #define ENETC_RBBSR 0x8 | |
116 | #define ENETC_RBCIR 0xc | |
117 | #define ENETC_RBBAR0 0x10 | |
118 | #define ENETC_RBBAR1 0x14 | |
119 | #define ENETC_RBPIR 0x18 | |
120 | #define ENETC_RBLENR 0x20 | |
121 | #define ENETC_RBIER 0xa0 | |
122 | #define ENETC_RBIER_RXTIE BIT(0) | |
123 | #define ENETC_RBIDR 0xa4 | |
124 | #define ENETC_RBICIR0 0xa8 | |
125 | #define ENETC_RBICIR0_ICEN BIT(31) | |
126 | ||
127 | /* TX BDR reg offsets */ | |
128 | #define ENETC_TBMR 0 | |
129 | #define ENETC_TBSR_BUSY BIT(0) | |
130 | #define ENETC_TBMR_VIH BIT(9) | |
131 | #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) | |
cbe9e835 | 132 | #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) |
d4fd0404 CM |
133 | #define ENETC_TBMR_EN BIT(31) |
134 | #define ENETC_TBSR 0x4 | |
135 | #define ENETC_TBBAR0 0x10 | |
136 | #define ENETC_TBBAR1 0x14 | |
137 | #define ENETC_TBPIR 0x18 | |
138 | #define ENETC_TBCIR 0x1c | |
139 | #define ENETC_TBCIR_IDX_MASK 0xffff | |
140 | #define ENETC_TBLENR 0x20 | |
141 | #define ENETC_TBIER 0xa0 | |
142 | #define ENETC_TBIER_TXTIE BIT(0) | |
143 | #define ENETC_TBIDR 0xa4 | |
144 | #define ENETC_TBICIR0 0xa8 | |
145 | #define ENETC_TBICIR0_ICEN BIT(31) | |
146 | ||
147 | #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) | |
148 | ||
149 | /* Port regs, offset: 1_0000h */ | |
150 | #define ENETC_PORT_BASE 0x10000 | |
151 | #define ENETC_PMR 0x0000 | |
152 | #define ENETC_PMR_EN GENMASK(18, 16) | |
2e47cb41 PL |
153 | #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) |
154 | #define ENETC_PMR_PSPEED_10M 0 | |
155 | #define ENETC_PMR_PSPEED_100M BIT(8) | |
156 | #define ENETC_PMR_PSPEED_1000M BIT(9) | |
157 | #define ENETC_PMR_PSPEED_2500M BIT(10) | |
d4fd0404 CM |
158 | #define ENETC_PSR 0x0004 /* RO */ |
159 | #define ENETC_PSIPMR 0x0018 | |
160 | #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ | |
161 | #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) | |
162 | #define ENETC_PSIPVMR 0x001c | |
163 | #define ENETC_VLAN_PROMISC_MAP_ALL 0x7 | |
164 | #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) | |
165 | #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) | |
166 | #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ | |
167 | #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) | |
168 | #define ENETC_PVCLCTR 0x0208 | |
169 | #define ENETC_VLAN_TYPE_C BIT(0) | |
170 | #define ENETC_VLAN_TYPE_S BIT(1) | |
171 | #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ | |
172 | #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ | |
173 | #define ENETC_PSIVLAN_EN BIT(31) | |
174 | #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) | |
175 | #define ENETC_PTXMBAR 0x0608 | |
176 | #define ENETC_PCAPR0 0x0900 | |
177 | #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) | |
178 | #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) | |
179 | #define ENETC_PCAPR1 0x0904 | |
180 | #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ | |
181 | #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) | |
182 | #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) | |
183 | #define ENETC_PSICFGR0_VTE BIT(12) | |
184 | #define ENETC_PSICFGR0_SIVIE BIT(14) | |
185 | #define ENETC_PSICFGR0_ASE BIT(15) | |
186 | #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ | |
187 | ||
188 | #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ | |
c431047c PL |
189 | #define ENETC_CBSE BIT(31) |
190 | #define ENETC_CBS_BW_MASK GENMASK(6, 0) | |
d4fd0404 | 191 | #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ |
d382563f CM |
192 | #define ENETC_RSSHASH_KEY_SIZE 40 |
193 | #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ | |
d4fd0404 CM |
194 | #define ENETC_PSIVLANFMR 0x1700 |
195 | #define ENETC_PSIVLANFMR_VS BIT(0) | |
d382563f CM |
196 | #define ENETC_PRFSMR 0x1800 |
197 | #define ENETC_PRFSMR_RFSE BIT(31) | |
198 | #define ENETC_PRFSCAPR 0x1804 | |
199 | #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) | |
200 | #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ | |
d4fd0404 CM |
201 | #define ENETC_PFPMR 0x1900 |
202 | #define ENETC_PFPMR_PMACE BIT(1) | |
203 | #define ENETC_PFPMR_MWLM BIT(0) | |
6517798d | 204 | #define ENETC_EMDIO_BASE 0x1c00 |
d4fd0404 CM |
205 | #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) |
206 | #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) | |
207 | #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) | |
208 | #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) | |
209 | #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ | |
210 | #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ | |
211 | #define ENETC_MMCSR 0x1f00 | |
212 | #define ENETC_MMCSR_ME BIT(16) | |
213 | #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ | |
214 | ||
215 | #define ENETC_PM0_CMD_CFG 0x8008 | |
216 | #define ENETC_PM1_CMD_CFG 0x9008 | |
217 | #define ENETC_PM0_TX_EN BIT(0) | |
218 | #define ENETC_PM0_RX_EN BIT(1) | |
219 | #define ENETC_PM0_PROMISC BIT(4) | |
220 | #define ENETC_PM0_CMD_XGLP BIT(10) | |
221 | #define ENETC_PM0_CMD_TXP BIT(11) | |
222 | #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) | |
223 | #define ENETC_PM0_CMD_SFD BIT(21) | |
224 | #define ENETC_PM0_MAXFRM 0x8014 | |
225 | #define ENETC_SET_TX_MTU(val) ((val) << 16) | |
226 | #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) | |
975d183e MW |
227 | |
228 | #define ENETC_PM_IMDIO_BASE 0x8030 | |
229 | ||
d4fd0404 CM |
230 | #define ENETC_PM0_IF_MODE 0x8300 |
231 | #define ENETC_PMO_IFM_RG BIT(2) | |
232 | #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) | |
233 | #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1)) | |
234 | #define ENETC_PM0_IFM_XGMII BIT(12) | |
79e49982 PL |
235 | #define ENETC_PSIDCAPR 0x1b08 |
236 | #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) | |
237 | #define ENETC_PSFCAPR 0x1b18 | |
238 | #define ENETC_PSFCAPR_MSK GENMASK(15, 0) | |
239 | #define ENETC_PSGCAPR 0x1b28 | |
240 | #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) | |
241 | #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) | |
242 | #define ENETC_PFMCAPR 0x1b38 | |
243 | #define ENETC_PFMCAPR_MSK GENMASK(15, 0) | |
d4fd0404 | 244 | |
16eb4c85 CM |
245 | /* MAC counters */ |
246 | #define ENETC_PM0_REOCT 0x8100 | |
247 | #define ENETC_PM0_RALN 0x8110 | |
248 | #define ENETC_PM0_RXPF 0x8118 | |
249 | #define ENETC_PM0_RFRM 0x8120 | |
250 | #define ENETC_PM0_RFCS 0x8128 | |
251 | #define ENETC_PM0_RVLAN 0x8130 | |
252 | #define ENETC_PM0_RERR 0x8138 | |
253 | #define ENETC_PM0_RUCA 0x8140 | |
254 | #define ENETC_PM0_RMCA 0x8148 | |
255 | #define ENETC_PM0_RBCA 0x8150 | |
256 | #define ENETC_PM0_RDRP 0x8158 | |
257 | #define ENETC_PM0_RPKT 0x8160 | |
258 | #define ENETC_PM0_RUND 0x8168 | |
259 | #define ENETC_PM0_R64 0x8170 | |
260 | #define ENETC_PM0_R127 0x8178 | |
261 | #define ENETC_PM0_R255 0x8180 | |
262 | #define ENETC_PM0_R511 0x8188 | |
263 | #define ENETC_PM0_R1023 0x8190 | |
264 | #define ENETC_PM0_R1518 0x8198 | |
265 | #define ENETC_PM0_R1519X 0x81A0 | |
266 | #define ENETC_PM0_ROVR 0x81A8 | |
267 | #define ENETC_PM0_RJBR 0x81B0 | |
268 | #define ENETC_PM0_RFRG 0x81B8 | |
269 | #define ENETC_PM0_RCNP 0x81C0 | |
270 | #define ENETC_PM0_RDRNTP 0x81C8 | |
271 | #define ENETC_PM0_TEOCT 0x8200 | |
272 | #define ENETC_PM0_TOCT 0x8208 | |
273 | #define ENETC_PM0_TCRSE 0x8210 | |
274 | #define ENETC_PM0_TXPF 0x8218 | |
275 | #define ENETC_PM0_TFRM 0x8220 | |
276 | #define ENETC_PM0_TFCS 0x8228 | |
277 | #define ENETC_PM0_TVLAN 0x8230 | |
278 | #define ENETC_PM0_TERR 0x8238 | |
279 | #define ENETC_PM0_TUCA 0x8240 | |
280 | #define ENETC_PM0_TMCA 0x8248 | |
281 | #define ENETC_PM0_TBCA 0x8250 | |
282 | #define ENETC_PM0_TPKT 0x8260 | |
283 | #define ENETC_PM0_TUND 0x8268 | |
284 | #define ENETC_PM0_T127 0x8278 | |
285 | #define ENETC_PM0_T1023 0x8290 | |
286 | #define ENETC_PM0_T1518 0x8298 | |
287 | #define ENETC_PM0_TCNP 0x82C0 | |
288 | #define ENETC_PM0_TDFR 0x82D0 | |
289 | #define ENETC_PM0_TMCOL 0x82D8 | |
290 | #define ENETC_PM0_TSCOL 0x82E0 | |
291 | #define ENETC_PM0_TLCOL 0x82E8 | |
292 | #define ENETC_PM0_TECOL 0x82F0 | |
293 | ||
294 | /* Port counters */ | |
295 | #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ | |
296 | #define ENETC_PBFDSIR 0x0810 | |
297 | #define ENETC_PFDMSAPR 0x0814 | |
298 | #define ENETC_UFDMF 0x1680 | |
299 | #define ENETC_MFDMF 0x1684 | |
300 | #define ENETC_PUFDVFR 0x1780 | |
301 | #define ENETC_PMFDVFR 0x1784 | |
302 | #define ENETC_PBFDVFR 0x1788 | |
303 | ||
d4fd0404 CM |
304 | /** Global regs, offset: 2_0000h */ |
305 | #define ENETC_GLOBAL_BASE 0x20000 | |
306 | #define ENETC_G_EIPBRR0 0x0bf8 | |
307 | #define ENETC_G_EIPBRR1 0x0bfc | |
308 | #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) | |
309 | #define ENETC_G_EPFBLPR1_XGMII 0x80000000 | |
310 | ||
311 | /* PCI device info */ | |
312 | struct enetc_hw { | |
313 | /* SI registers, used by all PCI functions */ | |
314 | void __iomem *reg; | |
315 | /* Port registers, PF only */ | |
316 | void __iomem *port; | |
317 | /* IP global registers, PF only */ | |
318 | void __iomem *global; | |
319 | }; | |
320 | ||
321 | /* general register accessors */ | |
322 | #define enetc_rd_reg(reg) ioread32((reg)) | |
323 | #define enetc_wr_reg(reg, val) iowrite32((val), (reg)) | |
16eb4c85 CM |
324 | #ifdef ioread64 |
325 | #define enetc_rd_reg64(reg) ioread64((reg)) | |
326 | #else | |
327 | /* using this to read out stats on 32b systems */ | |
328 | static inline u64 enetc_rd_reg64(void __iomem *reg) | |
329 | { | |
330 | u32 low, high, tmp; | |
331 | ||
332 | do { | |
333 | high = ioread32(reg + 4); | |
334 | low = ioread32(reg); | |
335 | tmp = ioread32(reg + 4); | |
336 | } while (high != tmp); | |
337 | ||
338 | return le64_to_cpu((__le64)high << 32 | low); | |
339 | } | |
340 | #endif | |
d4fd0404 CM |
341 | |
342 | #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) | |
343 | #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) | |
16eb4c85 | 344 | #define enetc_rd64(hw, off) enetc_rd_reg64((hw)->reg + (off)) |
d4fd0404 CM |
345 | /* port register accessors - PF only */ |
346 | #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) | |
347 | #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) | |
348 | /* global register accessors - PF only */ | |
349 | #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) | |
350 | #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) | |
351 | /* BDR register accessors, see ENETC_BDR() */ | |
352 | #define enetc_bdr_rd(hw, t, n, off) \ | |
353 | enetc_rd(hw, ENETC_BDR(t, n, off)) | |
354 | #define enetc_bdr_wr(hw, t, n, off, val) \ | |
355 | enetc_wr(hw, ENETC_BDR(t, n, off), val) | |
356 | #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) | |
357 | #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) | |
358 | #define enetc_txbdr_wr(hw, n, off, val) \ | |
359 | enetc_bdr_wr(hw, TX, n, off, val) | |
360 | #define enetc_rxbdr_wr(hw, n, off, val) \ | |
361 | enetc_bdr_wr(hw, RX, n, off, val) | |
362 | ||
363 | /* Buffer Descriptors (BD) */ | |
364 | union enetc_tx_bd { | |
365 | struct { | |
366 | __le64 addr; | |
367 | __le16 buf_len; | |
368 | __le16 frm_len; | |
369 | union { | |
370 | struct { | |
371 | __le16 l3_csoff; | |
372 | u8 l4_csoff; | |
373 | u8 flags; | |
374 | }; /* default layout */ | |
0d08c9ec | 375 | __le32 txstart; |
d4fd0404 CM |
376 | __le32 lstatus; |
377 | }; | |
378 | }; | |
379 | struct { | |
380 | __le32 tstamp; | |
381 | __le16 tpid; | |
382 | __le16 vid; | |
383 | u8 reserved[6]; | |
384 | u8 e_flags; | |
385 | u8 flags; | |
386 | } ext; /* Tx BD extension */ | |
d3982312 L |
387 | struct { |
388 | __le32 tstamp; | |
389 | u8 reserved[10]; | |
390 | u8 status; | |
391 | u8 flags; | |
392 | } wb; /* writeback descriptor */ | |
d4fd0404 CM |
393 | }; |
394 | ||
395 | #define ENETC_TXBD_FLAGS_L4CS BIT(0) | |
0d08c9ec | 396 | #define ENETC_TXBD_FLAGS_TSE BIT(1) |
d4fd0404 CM |
397 | #define ENETC_TXBD_FLAGS_W BIT(2) |
398 | #define ENETC_TXBD_FLAGS_CSUM BIT(3) | |
0d08c9ec | 399 | #define ENETC_TXBD_FLAGS_TXSTART BIT(4) |
d4fd0404 CM |
400 | #define ENETC_TXBD_FLAGS_EX BIT(6) |
401 | #define ENETC_TXBD_FLAGS_F BIT(7) | |
0d08c9ec PL |
402 | #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) |
403 | #define ENETC_TXBD_FLAGS_OFFSET 24 | |
d4fd0404 CM |
404 | static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) |
405 | { | |
406 | memset(txbd, 0, sizeof(*txbd)); | |
407 | } | |
408 | ||
409 | /* L3 csum flags */ | |
410 | #define ENETC_TXBD_L3_IPCS BIT(7) | |
411 | #define ENETC_TXBD_L3_IPV6 BIT(15) | |
412 | ||
413 | #define ENETC_TXBD_L3_START_MASK GENMASK(6, 0) | |
414 | #define ENETC_TXBD_L3_SET_HSIZE(val) ((((val) >> 2) & 0x7f) << 8) | |
415 | ||
416 | /* Extension flags */ | |
417 | #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) | |
418 | #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) | |
419 | ||
420 | static inline __le16 enetc_txbd_l3_csoff(int start, int hdr_sz, u16 l3_flags) | |
421 | { | |
422 | return cpu_to_le16(l3_flags | ENETC_TXBD_L3_SET_HSIZE(hdr_sz) | | |
423 | (start & ENETC_TXBD_L3_START_MASK)); | |
424 | } | |
425 | ||
426 | /* L4 csum flags */ | |
427 | #define ENETC_TXBD_L4_UDP BIT(5) | |
428 | #define ENETC_TXBD_L4_TCP BIT(6) | |
429 | ||
430 | union enetc_rx_bd { | |
431 | struct { | |
432 | __le64 addr; | |
433 | u8 reserved[8]; | |
434 | } w; | |
435 | struct { | |
436 | __le16 inet_csum; | |
437 | __le16 parse_summary; | |
438 | __le32 rss_hash; | |
439 | __le16 buf_len; | |
440 | __le16 vlan_opt; | |
441 | union { | |
442 | struct { | |
443 | __le16 flags; | |
444 | __le16 error; | |
445 | }; | |
446 | __le32 lstatus; | |
447 | }; | |
434cebab CM |
448 | } r; |
449 | struct { | |
d3982312 L |
450 | __le32 tstamp; |
451 | u8 reserved[12]; | |
434cebab | 452 | } ext; |
d4fd0404 CM |
453 | }; |
454 | ||
455 | #define ENETC_RXBD_LSTATUS_R BIT(30) | |
456 | #define ENETC_RXBD_LSTATUS_F BIT(31) | |
457 | #define ENETC_RXBD_ERR_MASK 0xff | |
458 | #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) | |
459 | #define ENETC_RXBD_FLAG_VLAN BIT(9) | |
460 | #define ENETC_RXBD_FLAG_TSTMP BIT(10) | |
461 | ||
462 | #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ | |
463 | #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ | |
464 | #define ENETC_MAX_NUM_VFS 2 | |
465 | ||
d4fd0404 CM |
466 | #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ |
467 | #define ENETC_CBD_STATUS_MASK 0xf | |
468 | ||
d382563f CM |
469 | struct enetc_cmd_rfse { |
470 | u8 smac_h[6]; | |
471 | u8 smac_m[6]; | |
472 | u8 dmac_h[6]; | |
473 | u8 dmac_m[6]; | |
474 | u32 sip_h[4]; | |
475 | u32 sip_m[4]; | |
476 | u32 dip_h[4]; | |
477 | u32 dip_m[4]; | |
478 | u16 ethtype_h; | |
479 | u16 ethtype_m; | |
480 | u16 ethtype4_h; | |
481 | u16 ethtype4_m; | |
482 | u16 sport_h; | |
483 | u16 sport_m; | |
484 | u16 dport_h; | |
485 | u16 dport_m; | |
486 | u16 vlan_h; | |
487 | u16 vlan_m; | |
488 | u8 proto_h; | |
489 | u8 proto_m; | |
490 | u16 flags; | |
491 | u16 result; | |
492 | u16 mode; | |
493 | }; | |
494 | ||
495 | #define ENETC_RFSE_EN BIT(15) | |
496 | #define ENETC_RFSE_MODE_BD 2 | |
497 | ||
d4fd0404 CM |
498 | static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr) |
499 | { | |
500 | *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); | |
501 | *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); | |
502 | } | |
503 | ||
504 | #define ENETC_SI_INT_IDX 0 | |
505 | /* base index for Rx/Tx interrupts */ | |
506 | #define ENETC_BDR_INT_BASE_IDX 1 | |
507 | ||
beb74ac8 CM |
508 | /* Messaging */ |
509 | ||
510 | /* Command completion status */ | |
511 | enum enetc_msg_cmd_status { | |
512 | ENETC_MSG_CMD_STATUS_OK, | |
513 | ENETC_MSG_CMD_STATUS_FAIL | |
514 | }; | |
515 | ||
516 | /* VSI-PSI command message types */ | |
517 | enum enetc_msg_cmd_type { | |
518 | ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ | |
519 | ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ | |
520 | ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ | |
521 | }; | |
522 | ||
523 | /* VSI-PSI command action types */ | |
524 | enum enetc_msg_cmd_action_type { | |
525 | ENETC_MSG_CMD_MNG_ADD = 1, | |
526 | ENETC_MSG_CMD_MNG_REMOVE | |
527 | }; | |
528 | ||
529 | /* PSI-VSI command header format */ | |
530 | struct enetc_msg_cmd_header { | |
531 | u16 type; /* command class type */ | |
532 | u16 id; /* denotes the specific required action */ | |
533 | }; | |
534 | ||
d4fd0404 CM |
535 | /* Common H/W utility functions */ |
536 | ||
9deba33f CM |
537 | static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, |
538 | bool en) | |
d4fd0404 | 539 | { |
9deba33f | 540 | u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); |
d4fd0404 CM |
541 | |
542 | val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); | |
9deba33f | 543 | enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); |
d4fd0404 CM |
544 | } |
545 | ||
9deba33f CM |
546 | static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, |
547 | bool en) | |
d4fd0404 | 548 | { |
9deba33f | 549 | u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); |
d4fd0404 CM |
550 | |
551 | val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); | |
9deba33f | 552 | enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); |
d4fd0404 | 553 | } |
cbe9e835 CG |
554 | |
555 | static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, | |
556 | int prio) | |
557 | { | |
558 | u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); | |
559 | ||
560 | val &= ~ENETC_TBMR_PRIO_MASK; | |
561 | val |= ENETC_TBMR_SET_PRIO(prio); | |
562 | enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); | |
563 | } | |
34c6adf1 PL |
564 | |
565 | enum bdcr_cmd_class { | |
566 | BDCR_CMD_UNSPEC = 0, | |
567 | BDCR_CMD_MAC_FILTER, | |
568 | BDCR_CMD_VLAN_FILTER, | |
569 | BDCR_CMD_RSS, | |
570 | BDCR_CMD_RFS, | |
571 | BDCR_CMD_PORT_GCL, | |
572 | BDCR_CMD_RECV_CLASSIFIER, | |
888ae5a3 PL |
573 | BDCR_CMD_STREAM_IDENTIFY, |
574 | BDCR_CMD_STREAM_FILTER, | |
575 | BDCR_CMD_STREAM_GCL, | |
d621d770 | 576 | BDCR_CMD_FLOW_METER, |
34c6adf1 PL |
577 | __BDCR_CMD_MAX_LEN, |
578 | BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, | |
579 | }; | |
580 | ||
581 | /* class 5, command 0 */ | |
582 | struct tgs_gcl_conf { | |
583 | u8 atc; /* init gate value */ | |
584 | u8 res[7]; | |
585 | struct { | |
586 | u8 res1[4]; | |
587 | __le16 acl_len; | |
588 | u8 res2[2]; | |
589 | }; | |
590 | }; | |
591 | ||
592 | /* gate control list entry */ | |
593 | struct gce { | |
594 | __le32 period; | |
595 | u8 gate; | |
596 | u8 res[3]; | |
597 | }; | |
598 | ||
599 | /* tgs_gcl_conf address point to this data space */ | |
600 | struct tgs_gcl_data { | |
601 | __le32 btl; | |
602 | __le32 bth; | |
603 | __le32 ct; | |
604 | __le32 cte; | |
cc5b48b5 | 605 | struct gce entry[]; |
34c6adf1 PL |
606 | }; |
607 | ||
888ae5a3 PL |
608 | /* class 7, command 0, Stream Identity Entry Configuration */ |
609 | struct streamid_conf { | |
610 | __le32 stream_handle; /* init gate value */ | |
611 | __le32 iports; | |
612 | u8 id_type; | |
613 | u8 oui[3]; | |
614 | u8 res[3]; | |
615 | u8 en; | |
616 | }; | |
617 | ||
618 | #define ENETC_CBDR_SID_VID_MASK 0xfff | |
619 | #define ENETC_CBDR_SID_VIDM BIT(12) | |
620 | #define ENETC_CBDR_SID_TG_MASK 0xc000 | |
621 | /* streamid_conf address point to this data space */ | |
622 | struct streamid_data { | |
623 | union { | |
624 | u8 dmac[6]; | |
625 | u8 smac[6]; | |
626 | }; | |
627 | u16 vid_vidm_tg; | |
628 | }; | |
629 | ||
630 | #define ENETC_CBDR_SFI_PRI_MASK 0x7 | |
631 | #define ENETC_CBDR_SFI_PRIM BIT(3) | |
632 | #define ENETC_CBDR_SFI_BLOV BIT(4) | |
633 | #define ENETC_CBDR_SFI_BLEN BIT(5) | |
634 | #define ENETC_CBDR_SFI_MSDUEN BIT(6) | |
635 | #define ENETC_CBDR_SFI_FMITEN BIT(7) | |
636 | #define ENETC_CBDR_SFI_ENABLE BIT(7) | |
637 | /* class 8, command 0, Stream Filter Instance, Short Format */ | |
638 | struct sfi_conf { | |
639 | __le32 stream_handle; | |
640 | u8 multi; | |
641 | u8 res[2]; | |
642 | u8 sthm; | |
643 | /* Max Service Data Unit or Flow Meter Instance Table index. | |
644 | * Depending on the value of FLT this represents either Max | |
645 | * Service Data Unit (max frame size) allowed by the filter | |
646 | * entry or is an index into the Flow Meter Instance table | |
647 | * index identifying the policer which will be used to police | |
648 | * it. | |
649 | */ | |
650 | __le16 fm_inst_table_index; | |
651 | __le16 msdu; | |
652 | __le16 sg_inst_table_index; | |
653 | u8 res1[2]; | |
654 | __le32 input_ports; | |
655 | u8 res2[3]; | |
656 | u8 en; | |
657 | }; | |
658 | ||
659 | /* class 8, command 2 stream Filter Instance status query short format | |
660 | * command no need structure define | |
661 | * Stream Filter Instance Query Statistics Response data | |
662 | */ | |
663 | struct sfi_counter_data { | |
664 | u32 matchl; | |
665 | u32 matchh; | |
666 | u32 msdu_dropl; | |
667 | u32 msdu_droph; | |
668 | u32 stream_gate_dropl; | |
669 | u32 stream_gate_droph; | |
670 | u32 flow_meter_dropl; | |
671 | u32 flow_meter_droph; | |
672 | }; | |
673 | ||
674 | #define ENETC_CBDR_SGI_OIPV_MASK 0x7 | |
675 | #define ENETC_CBDR_SGI_OIPV_EN BIT(3) | |
676 | #define ENETC_CBDR_SGI_CGTST BIT(6) | |
677 | #define ENETC_CBDR_SGI_OGTST BIT(7) | |
678 | #define ENETC_CBDR_SGI_CFG_CHG BIT(1) | |
679 | #define ENETC_CBDR_SGI_CFG_PND BIT(2) | |
680 | #define ENETC_CBDR_SGI_OEX BIT(4) | |
681 | #define ENETC_CBDR_SGI_OEXEN BIT(5) | |
682 | #define ENETC_CBDR_SGI_IRX BIT(6) | |
683 | #define ENETC_CBDR_SGI_IRXEN BIT(7) | |
684 | #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 | |
685 | #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc | |
686 | #define ENETC_CBDR_SGI_EN BIT(7) | |
687 | /* class 9, command 0, Stream Gate Instance Table, Short Format | |
688 | * class 9, command 2, Stream Gate Instance Table entry query write back | |
689 | * Short Format | |
690 | */ | |
691 | struct sgi_table { | |
692 | u8 res[8]; | |
693 | u8 oipv; | |
694 | u8 res0[2]; | |
695 | u8 ocgtst; | |
696 | u8 res1[7]; | |
697 | u8 gset; | |
698 | u8 oacl_len; | |
699 | u8 res2[2]; | |
700 | u8 en; | |
701 | }; | |
702 | ||
703 | #define ENETC_CBDR_SGI_AIPV_MASK 0x7 | |
704 | #define ENETC_CBDR_SGI_AIPV_EN BIT(3) | |
705 | #define ENETC_CBDR_SGI_AGTST BIT(7) | |
706 | ||
707 | /* class 9, command 1, Stream Gate Control List, Long Format */ | |
708 | struct sgcl_conf { | |
709 | u8 aipv; | |
710 | u8 res[2]; | |
711 | u8 agtst; | |
712 | u8 res1[4]; | |
713 | union { | |
714 | struct { | |
715 | u8 res2[4]; | |
716 | u8 acl_len; | |
717 | u8 res3[3]; | |
718 | }; | |
719 | u8 cct[8]; /* Config change time */ | |
720 | }; | |
721 | }; | |
722 | ||
723 | #define ENETC_CBDR_SGL_IOMEN BIT(0) | |
724 | #define ENETC_CBDR_SGL_IPVEN BIT(3) | |
725 | #define ENETC_CBDR_SGL_GTST BIT(4) | |
726 | #define ENETC_CBDR_SGL_IPV_MASK 0xe | |
727 | /* Stream Gate Control List Entry */ | |
728 | struct sgce { | |
729 | u32 interval; | |
730 | u8 msdu[3]; | |
731 | u8 multi; | |
732 | }; | |
733 | ||
734 | /* stream control list class 9 , cmd 1 data buffer */ | |
735 | struct sgcl_data { | |
736 | u32 btl; | |
737 | u32 bth; | |
738 | u32 ct; | |
739 | u32 cte; | |
740 | struct sgce sgcl[0]; | |
741 | }; | |
742 | ||
d621d770 PL |
743 | #define ENETC_CBDR_FMI_MR BIT(0) |
744 | #define ENETC_CBDR_FMI_MREN BIT(1) | |
745 | #define ENETC_CBDR_FMI_DOY BIT(2) | |
746 | #define ENETC_CBDR_FMI_CM BIT(3) | |
747 | #define ENETC_CBDR_FMI_CF BIT(4) | |
748 | #define ENETC_CBDR_FMI_NDOR BIT(5) | |
749 | #define ENETC_CBDR_FMI_OALEN BIT(6) | |
750 | #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) | |
751 | ||
752 | /* class 10: command 0/1, Flow Meter Instance Set, short Format */ | |
753 | struct fmi_conf { | |
754 | __le32 cir; | |
755 | __le32 cbs; | |
756 | __le32 eir; | |
757 | __le32 ebs; | |
758 | u8 conf; | |
759 | u8 res1; | |
760 | u8 ir_fpp; | |
761 | u8 res2[4]; | |
762 | u8 en; | |
763 | }; | |
764 | ||
34c6adf1 PL |
765 | struct enetc_cbd { |
766 | union{ | |
888ae5a3 PL |
767 | struct sfi_conf sfi_conf; |
768 | struct sgi_table sgi_table; | |
d621d770 | 769 | struct fmi_conf fmi_conf; |
34c6adf1 PL |
770 | struct { |
771 | __le32 addr[2]; | |
772 | union { | |
773 | __le32 opt[4]; | |
774 | struct tgs_gcl_conf gcl_conf; | |
888ae5a3 PL |
775 | struct streamid_conf sid_set; |
776 | struct sgcl_conf sgcl_conf; | |
34c6adf1 PL |
777 | }; |
778 | }; /* Long format */ | |
779 | __le32 data[6]; | |
780 | }; | |
781 | __le16 index; | |
782 | __le16 length; | |
783 | u8 cmd; | |
784 | u8 cls; | |
785 | u8 _res; | |
786 | u8 status_flags; | |
787 | }; | |
788 | ||
c431047c PL |
789 | #define ENETC_CLK 400000000ULL |
790 | ||
34c6adf1 PL |
791 | /* port time gating control register */ |
792 | #define ENETC_QBV_PTGCR_OFFSET 0x11a00 | |
793 | #define ENETC_QBV_TGE BIT(31) | |
794 | #define ENETC_QBV_TGPE BIT(30) | |
795 | ||
796 | /* Port time gating capability register */ | |
797 | #define ENETC_QBV_PTGCAPR_OFFSET 0x11a08 | |
798 | #define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0) | |
0d08c9ec PL |
799 | |
800 | /* Port time specific departure */ | |
801 | #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) | |
802 | #define ENETC_TSDE BIT(31) | |
79e49982 PL |
803 | |
804 | /* PSFP setting */ | |
805 | #define ENETC_PPSFPMR 0x11b00 | |
806 | #define ENETC_PPSFPMR_PSFPEN BIT(0) | |
807 | #define ENETC_PPSFPMR_VS BIT(1) | |
808 | #define ENETC_PPSFPMR_PVC BIT(2) | |
809 | #define ENETC_PPSFPMR_PVZC BIT(3) |