[linux-block.git] / drivers / net / ethernet / freescale / enetc / enetc_hw.h

/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2017-2019 NXP */

#include <linux/bitops.h>

/* ENETC device IDs */
#define ENETC_DEV_ID_PF		0xe100
#define ENETC_DEV_ID_VF		0xef00
#define ENETC_DEV_ID_PTP	0xee02

/* ENETC register block BAR */
#define ENETC_BAR_REGS	0

/** SI regs, offset: 0h */
#define ENETC_SIMR	0
#define ENETC_SIMR_EN	BIT(31)
#define ENETC_SIMR_RSSE	BIT(0)
#define ENETC_SICTR0	0x18
#define ENETC_SICTR1	0x1c
#define ENETC_SIPCAPR0	0x20
#define ENETC_SIPCAPR0_QBV	BIT(4)
#define ENETC_SIPCAPR0_RSS	BIT(8)
#define ENETC_SIPCAPR1	0x24
#define ENETC_SITGTGR	0x30
#define ENETC_SIRBGCR	0x38
/* cache attribute registers for transactions initiated by ENETC */
#define ENETC_SICAR0	0x40
#define ENETC_SICAR1	0x44
#define ENETC_SICAR2	0x48
/* rd snoop, no alloc
 * wr snoop, no alloc, partial cache line update for BDs and full cache line
 * update for data
 */
#define ENETC_SICAR_RD_COHERENT	0x2b2b0000
#define ENETC_SICAR_WR_COHERENT	0x00006727
#define ENETC_SICAR_MSI	0x00300030 /* rd/wr device, no snoop, no alloc */

#define ENETC_SIPMAR0	0x80
#define ENETC_SIPMAR1	0x84

/* VF-PF Message passing */
#define ENETC_DEFAULT_MSG_SIZE	1024	/* and max size */
/* msg size encoding: default and max msg value of 1024B encoded as 0 */
static inline u32 enetc_vsi_set_msize(u32 size)
{
	return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0;
}

#define ENETC_PSIMSGRR	0x204
#define ENETC_PSIMSGRR_MR_MASK	GENMASK(2, 1)
#define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
#define ENETC_PSIVMSGRCVAR0(n)	(0x210 + (n) * 0x8) /* n = VSI index */
#define ENETC_PSIVMSGRCVAR1(n)	(0x214 + (n) * 0x8)

#define ENETC_VSIMSGSR	0x204	/* RO */
#define ENETC_VSIMSGSR_MB	BIT(0)
#define ENETC_VSIMSGSR_MS	BIT(1)
#define ENETC_VSIMSGSNDAR0	0x210
#define ENETC_VSIMSGSNDAR1	0x214

#define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
#define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)

/* SI statistics */
#define ENETC_SIROCT	0x300
#define ENETC_SIRFRM	0x308
#define ENETC_SIRUCA	0x310
#define ENETC_SIRMCA	0x318
#define ENETC_SITOCT	0x320
#define ENETC_SITFRM	0x328
#define ENETC_SITUCA	0x330
#define ENETC_SITMCA	0x338
#define ENETC_RBDCR(n)	(0x8180 + (n) * 0x200)

/* Control BDR regs */
#define ENETC_SICBDRMR		0x800
#define ENETC_SICBDRSR		0x804	/* RO */
#define ENETC_SICBDRBAR0	0x810
#define ENETC_SICBDRBAR1	0x814
#define ENETC_SICBDRPIR		0x818
#define ENETC_SICBDRCIR		0x81c
#define ENETC_SICBDRLENR	0x820

#define ENETC_SICAPR0	0x900
#define ENETC_SICAPR1	0x904

#define ENETC_PSIIER	0xa00
#define ENETC_PSIIER_MR_MASK	GENMASK(2, 1)
#define ENETC_PSIIDR	0xa08
#define ENETC_SITXIDR	0xa18
#define ENETC_SIRXIDR	0xa28
#define ENETC_SIMSIVR	0xa30

#define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
#define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)

#define ENETC_SIUEFDCR	0xe28

#define ENETC_SIRFSCAPR	0x1200
#define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
#define ENETC_SIRSSCAPR	0x1600
#define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)

/** SI BDR sub-blocks, n = 0..7 */
enum enetc_bdr_type {TX, RX};
#define ENETC_BDR_OFF(i)	((i) * 0x200)
#define ENETC_BDR(t, i, r)	(0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
/* RX BDR reg offsets */
#define ENETC_RBMR	0
#define ENETC_RBMR_BDS	BIT(2)
#define ENETC_RBMR_VTE	BIT(5)
#define ENETC_RBMR_EN	BIT(31)
#define ENETC_RBSR	0x4
#define ENETC_RBBSR	0x8
#define ENETC_RBCIR	0xc
#define ENETC_RBBAR0	0x10
#define ENETC_RBBAR1	0x14
#define ENETC_RBPIR	0x18
#define ENETC_RBLENR	0x20
#define ENETC_RBIER	0xa0
#define ENETC_RBIER_RXTIE	BIT(0)
#define ENETC_RBIDR	0xa4
#define ENETC_RBICIR0	0xa8
#define ENETC_RBICIR0_ICEN	BIT(31)

/* TX BDR reg offsets */
#define ENETC_TBMR	0
#define ENETC_TBSR_BUSY	BIT(0)
#define ENETC_TBMR_VIH	BIT(9)
#define ENETC_TBMR_PRIO_MASK		GENMASK(2, 0)
#define ENETC_TBMR_SET_PRIO(val)	((val) & ENETC_TBMR_PRIO_MASK)
#define ENETC_TBMR_EN	BIT(31)
#define ENETC_TBSR	0x4
#define ENETC_TBBAR0	0x10
#define ENETC_TBBAR1	0x14
#define ENETC_TBPIR	0x18
#define ENETC_TBCIR	0x1c
#define ENETC_TBCIR_IDX_MASK	0xffff
#define ENETC_TBLENR	0x20
#define ENETC_TBIER	0xa0
#define ENETC_TBIER_TXTIE	BIT(0)
#define ENETC_TBIDR	0xa4
#define ENETC_TBICIR0	0xa8
#define ENETC_TBICIR0_ICEN	BIT(31)

#define ENETC_RTBLENR_LEN(n)	((n) & ~0x7)

/* Port regs, offset: 1_0000h */
#define ENETC_PORT_BASE		0x10000
#define ENETC_PMR		0x0000
#define ENETC_PMR_EN	GENMASK(18, 16)
#define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)
#define ENETC_PMR_PSPEED_10M	0
#define ENETC_PMR_PSPEED_100M	BIT(8)
#define ENETC_PMR_PSPEED_1000M	BIT(9)
#define ENETC_PMR_PSPEED_2500M	BIT(10)
#define ENETC_PSR		0x0004 /* RO */
#define ENETC_PSIPMR		0x0018
#define ENETC_PSIPMR_SET_UP(n)	BIT(n) /* n = SI index */
#define ENETC_PSIPMR_SET_MP(n)	BIT((n) + 16)
#define ENETC_PSIPVMR		0x001c
#define ENETC_VLAN_PROMISC_MAP_ALL	0x7
#define ENETC_PSIPVMR_SET_VP(simap)	((simap) & 0x7)
#define ENETC_PSIPVMR_SET_VUTA(simap)	(((simap) & 0x7) << 16)
#define ENETC_PSIPMAR0(n)	(0x0100 + (n) * 0x8) /* n = SI index */
#define ENETC_PSIPMAR1(n)	(0x0104 + (n) * 0x8)
#define ENETC_PVCLCTR		0x0208
#define ENETC_VLAN_TYPE_C	BIT(0)
#define ENETC_VLAN_TYPE_S	BIT(1)
#define ENETC_PVCLCTR_OVTPIDL(bmp)	((bmp) & 0xff) /* VLAN_TYPE */
#define ENETC_PSIVLANR(n)	(0x0240 + (n) * 4) /* n = SI index */
#define ENETC_PSIVLAN_EN	BIT(31)
#define ENETC_PSIVLAN_SET_QOS(val)	((u32)(val) << 12)
#define ENETC_PTXMBAR		0x0608
#define ENETC_PCAPR0		0x0900
#define ENETC_PCAPR0_RXBDR(val)	((val) >> 24)
#define ENETC_PCAPR0_TXBDR(val)	(((val) >> 16) & 0xff)
#define ENETC_PCAPR1		0x0904
#define ENETC_PSICFGR0(n)	(0x0940 + (n) * 0xc)  /* n = SI index */
#define ENETC_PSICFGR0_SET_TXBDR(val)	((val) & 0xff)
#define ENETC_PSICFGR0_SET_RXBDR(val)	(((val) & 0xff) << 16)
#define ENETC_PSICFGR0_VTE	BIT(12)
#define ENETC_PSICFGR0_SIVIE	BIT(14)
#define ENETC_PSICFGR0_ASE	BIT(15)
#define ENETC_PSICFGR0_SIVC(bmp)	(((bmp) & 0xff) << 24) /* VLAN_TYPE */

#define ENETC_PTCCBSR0(n)	(0x1110 + (n) * 8) /* n = 0 to 7*/
#define ENETC_CBSE		BIT(31)
#define ENETC_CBS_BW_MASK	GENMASK(6, 0)
#define ENETC_PTCCBSR1(n)	(0x1114 + (n) * 8) /* n = 0 to 7*/
#define ENETC_RSSHASH_KEY_SIZE	40
#define ENETC_PRSSK(n)		(0x1410 + (n) * 4) /* n = [0..9] */
#define ENETC_PSIVLANFMR	0x1700
#define ENETC_PSIVLANFMR_VS	BIT(0)
#define ENETC_PRFSMR		0x1800
#define ENETC_PRFSMR_RFSE	BIT(31)
#define ENETC_PRFSCAPR		0x1804
#define ENETC_PRFSCAPR_GET_NUM_RFS(val)	((((val) & 0xf) + 1) * 16)
#define ENETC_PSIRFSCFGR(n)	(0x1814 + (n) * 4) /* n = SI index */
#define ENETC_PFPMR		0x1900
#define ENETC_PFPMR_PMACE	BIT(1)
#define ENETC_PFPMR_MWLM	BIT(0)
#define ENETC_EMDIO_BASE	0x1c00
#define ENETC_PSIUMHFR0(n, err)	(((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
#define ENETC_PSIUMHFR1(n)	(0x1d04 + (n) * 0x10)
#define ENETC_PSIMMHFR0(n, err)	(((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
#define ENETC_PSIMMHFR1(n)	(0x1d0c + (n) * 0x10)
#define ENETC_PSIVHFR0(n)	(0x1e00 + (n) * 8) /* n = SI index */
#define ENETC_PSIVHFR1(n)	(0x1e04 + (n) * 8) /* n = SI index */
#define ENETC_MMCSR		0x1f00
#define ENETC_MMCSR_ME		BIT(16)
#define ENETC_PTCMSDUR(n)	(0x2020 + (n) * 4) /* n = TC index [0..7] */

#define ENETC_PM0_CMD_CFG	0x8008
#define ENETC_PM1_CMD_CFG	0x9008
#define ENETC_PM0_TX_EN		BIT(0)
#define ENETC_PM0_RX_EN		BIT(1)
#define ENETC_PM0_PROMISC	BIT(4)
#define ENETC_PM0_CMD_XGLP	BIT(10)
#define ENETC_PM0_CMD_TXP	BIT(11)
#define ENETC_PM0_CMD_PHY_TX_EN	BIT(15)
#define ENETC_PM0_CMD_SFD	BIT(21)
#define ENETC_PM0_MAXFRM	0x8014
#define ENETC_SET_TX_MTU(val)	((val) << 16)
#define ENETC_SET_MAXFRM(val)	((val) & 0xffff)
#define ENETC_PM0_IF_MODE	0x8300
#define ENETC_PMO_IFM_RG	BIT(2)
#define ENETC_PM0_IFM_RLP	(BIT(5) | BIT(11))
#define ENETC_PM0_IFM_RGAUTO	(BIT(15) | ENETC_PMO_IFM_RG | BIT(1))
#define ENETC_PM0_IFM_XGMII	BIT(12)

/* MAC counters */
#define ENETC_PM0_REOCT		0x8100
#define ENETC_PM0_RALN		0x8110
#define ENETC_PM0_RXPF		0x8118
#define ENETC_PM0_RFRM		0x8120
#define ENETC_PM0_RFCS		0x8128
#define ENETC_PM0_RVLAN		0x8130
#define ENETC_PM0_RERR		0x8138
#define ENETC_PM0_RUCA		0x8140
#define ENETC_PM0_RMCA		0x8148
#define ENETC_PM0_RBCA		0x8150
#define ENETC_PM0_RDRP		0x8158
#define ENETC_PM0_RPKT		0x8160
#define ENETC_PM0_RUND		0x8168
#define ENETC_PM0_R64		0x8170
#define ENETC_PM0_R127		0x8178
#define ENETC_PM0_R255		0x8180
#define ENETC_PM0_R511		0x8188
#define ENETC_PM0_R1023		0x8190
#define ENETC_PM0_R1518		0x8198
#define ENETC_PM0_R1519X	0x81A0
#define ENETC_PM0_ROVR		0x81A8
#define ENETC_PM0_RJBR		0x81B0
#define ENETC_PM0_RFRG		0x81B8
#define ENETC_PM0_RCNP		0x81C0
#define ENETC_PM0_RDRNTP	0x81C8
#define ENETC_PM0_TEOCT		0x8200
#define ENETC_PM0_TOCT		0x8208
#define ENETC_PM0_TCRSE		0x8210
#define ENETC_PM0_TXPF		0x8218
#define ENETC_PM0_TFRM		0x8220
#define ENETC_PM0_TFCS		0x8228
#define ENETC_PM0_TVLAN		0x8230
#define ENETC_PM0_TERR		0x8238
#define ENETC_PM0_TUCA		0x8240
#define ENETC_PM0_TMCA		0x8248
#define ENETC_PM0_TBCA		0x8250
#define ENETC_PM0_TPKT		0x8260
#define ENETC_PM0_TUND		0x8268
#define ENETC_PM0_T127		0x8278
#define ENETC_PM0_T1023		0x8290
#define ENETC_PM0_T1518		0x8298
#define ENETC_PM0_TCNP		0x82C0
#define ENETC_PM0_TDFR		0x82D0
#define ENETC_PM0_TMCOL		0x82D8
#define ENETC_PM0_TSCOL		0x82E0
#define ENETC_PM0_TLCOL		0x82E8
#define ENETC_PM0_TECOL		0x82F0

/* Port counters */
#define ENETC_PICDR(n)		(0x0700 + (n) * 8) /* n = [0..3] */
#define ENETC_PBFDSIR		0x0810
#define ENETC_PFDMSAPR		0x0814
#define ENETC_UFDMF		0x1680
#define ENETC_MFDMF		0x1684
#define ENETC_PUFDVFR		0x1780
#define ENETC_PMFDVFR		0x1784
#define ENETC_PBFDVFR		0x1788

/** Global regs, offset: 2_0000h */
#define ENETC_GLOBAL_BASE	0x20000
#define ENETC_G_EIPBRR0		0x0bf8
#define ENETC_G_EIPBRR1		0x0bfc
#define ENETC_G_EPFBLPR(n)	(0xd00 + 4 * (n))
#define ENETC_G_EPFBLPR1_XGMII	0x80000000

/* PCI device info */
struct enetc_hw {
	/* SI registers, used by all PCI functions */
	void __iomem *reg;
	/* Port registers, PF only */
	void __iomem *port;
	/* IP global registers, PF only */
	void __iomem *global;
};

/* general register accessors */
#define enetc_rd_reg(reg)	ioread32((reg))
#define enetc_wr_reg(reg, val)	iowrite32((val), (reg))
#ifdef ioread64
#define enetc_rd_reg64(reg)	ioread64((reg))
#else
/* using this to read out stats on 32b systems */
static inline u64 enetc_rd_reg64(void __iomem *reg)
{
	u32 low, high, tmp;

	do {
		high = ioread32(reg + 4);
		low = ioread32(reg);
		tmp = ioread32(reg + 4);
	} while (high != tmp);

	return le64_to_cpu((__le64)high << 32 | low);
}
#endif

#define enetc_rd(hw, off)		enetc_rd_reg((hw)->reg + (off))
#define enetc_wr(hw, off, val)		enetc_wr_reg((hw)->reg + (off), val)
#define enetc_rd64(hw, off)		enetc_rd_reg64((hw)->reg + (off))
/* port register accessors - PF only */
#define enetc_port_rd(hw, off)		enetc_rd_reg((hw)->port + (off))
#define enetc_port_wr(hw, off, val)	enetc_wr_reg((hw)->port + (off), val)
/* global register accessors - PF only */
#define enetc_global_rd(hw, off)	enetc_rd_reg((hw)->global + (off))
#define enetc_global_wr(hw, off, val)	enetc_wr_reg((hw)->global + (off), val)
/* BDR register accessors, see ENETC_BDR() */
#define enetc_bdr_rd(hw, t, n, off) \
				enetc_rd(hw, ENETC_BDR(t, n, off))
#define enetc_bdr_wr(hw, t, n, off, val) \
				enetc_wr(hw, ENETC_BDR(t, n, off), val)
#define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
#define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
#define enetc_txbdr_wr(hw, n, off, val) \
				enetc_bdr_wr(hw, TX, n, off, val)
#define enetc_rxbdr_wr(hw, n, off, val) \
				enetc_bdr_wr(hw, RX, n, off, val)

/* Buffer Descriptors (BD) */
union enetc_tx_bd {
	struct {
		__le64 addr;
		__le16 buf_len;
		__le16 frm_len;
		union {
			struct {
				__le16 l3_csoff;
				u8 l4_csoff;
				u8 flags;
			}; /* default layout */
			__le32 txstart;
			__le32 lstatus;
		};
	};
	struct {
		__le32 tstamp;
		__le16 tpid;
		__le16 vid;
		u8 reserved[6];
		u8 e_flags;
		u8 flags;
	} ext; /* Tx BD extension */
	struct {
		__le32 tstamp;
		u8 reserved[10];
		u8 status;
		u8 flags;
	} wb; /* writeback descriptor */
};

#define ENETC_TXBD_FLAGS_L4CS	BIT(0)
#define ENETC_TXBD_FLAGS_TSE	BIT(1)
#define ENETC_TXBD_FLAGS_W	BIT(2)
#define ENETC_TXBD_FLAGS_CSUM	BIT(3)
#define ENETC_TXBD_FLAGS_TXSTART BIT(4)
#define ENETC_TXBD_FLAGS_EX	BIT(6)
#define ENETC_TXBD_FLAGS_F	BIT(7)
#define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
#define ENETC_TXBD_FLAGS_OFFSET 24
static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
{
	memset(txbd, 0, sizeof(*txbd));
}

/* L3 csum flags */
#define ENETC_TXBD_L3_IPCS	BIT(7)
#define ENETC_TXBD_L3_IPV6	BIT(15)

#define ENETC_TXBD_L3_START_MASK	GENMASK(6, 0)
#define ENETC_TXBD_L3_SET_HSIZE(val)	((((val) >> 2) & 0x7f) << 8)

/* Extension flags */
#define ENETC_TXBD_E_FLAGS_VLAN_INS	BIT(0)
#define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP	BIT(2)

static inline __le16 enetc_txbd_l3_csoff(int start, int hdr_sz, u16 l3_flags)
{
	return cpu_to_le16(l3_flags | ENETC_TXBD_L3_SET_HSIZE(hdr_sz) |
			   (start & ENETC_TXBD_L3_START_MASK));
}

/* L4 csum flags */
#define ENETC_TXBD_L4_UDP	BIT(5)
#define ENETC_TXBD_L4_TCP	BIT(6)

union enetc_rx_bd {
	struct {
		__le64 addr;
		u8 reserved[8];
#ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING
		u8 reserved1[16];
#endif
	} w;
	struct {
		__le16 inet_csum;
		__le16 parse_summary;
		__le32 rss_hash;
		__le16 buf_len;
		__le16 vlan_opt;
		union {
			struct {
				__le16 flags;
				__le16 error;
			};
			__le32 lstatus;
		};
#ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING
		__le32 tstamp;
		u8 reserved[12];
#endif
	} r;
};

#define ENETC_RXBD_LSTATUS_R	BIT(30)
#define ENETC_RXBD_LSTATUS_F	BIT(31)
#define ENETC_RXBD_ERR_MASK	0xff
#define ENETC_RXBD_LSTATUS(flags)	((flags) << 16)
#define ENETC_RXBD_FLAG_VLAN	BIT(9)
#define ENETC_RXBD_FLAG_TSTMP	BIT(10)

#define ENETC_MAC_ADDR_FILT_CNT	8 /* # of supported entries per port */
#define EMETC_MAC_ADDR_FILT_RES	3 /* # of reserved entries at the beginning */
#define ENETC_MAX_NUM_VFS	2

#define ENETC_CBD_FLAGS_SF	BIT(7) /* short format */
#define ENETC_CBD_STATUS_MASK	0xf

struct enetc_cmd_rfse {
	u8 smac_h[6];
	u8 smac_m[6];
	u8 dmac_h[6];
	u8 dmac_m[6];
	u32 sip_h[4];
	u32 sip_m[4];
	u32 dip_h[4];
	u32 dip_m[4];
	u16 ethtype_h;
	u16 ethtype_m;
	u16 ethtype4_h;
	u16 ethtype4_m;
	u16 sport_h;
	u16 sport_m;
	u16 dport_h;
	u16 dport_m;
	u16 vlan_h;
	u16 vlan_m;
	u8 proto_h;
	u8 proto_m;
	u16 flags;
	u16 result;
	u16 mode;
};

#define ENETC_RFSE_EN	BIT(15)
#define ENETC_RFSE_MODE_BD	2

static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr)
{
	*(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0);
	*(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1);
}

#define ENETC_SI_INT_IDX	0
/* base index for Rx/Tx interrupts */
#define ENETC_BDR_INT_BASE_IDX	1

/* Messaging */

/* Command completion status */
enum enetc_msg_cmd_status {
	ENETC_MSG_CMD_STATUS_OK,
	ENETC_MSG_CMD_STATUS_FAIL
};

/* VSI-PSI command message types */
enum enetc_msg_cmd_type {
	ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
	ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
	ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
};

/* VSI-PSI command action types */
enum enetc_msg_cmd_action_type {
	ENETC_MSG_CMD_MNG_ADD = 1,
	ENETC_MSG_CMD_MNG_REMOVE
};

/* PSI-VSI command header format */
struct enetc_msg_cmd_header {
	u16 type;	/* command class type */
	u16 id;		/* denotes the specific required action */
};

/* Common H/W utility functions */

static inline void enetc_enable_rxvlan(struct enetc_hw *hw, int si_idx,
				       bool en)
{
	u32 val = enetc_rxbdr_rd(hw, si_idx, ENETC_RBMR);

	val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0);
	enetc_rxbdr_wr(hw, si_idx, ENETC_RBMR, val);
}

static inline void enetc_enable_txvlan(struct enetc_hw *hw, int si_idx,
				       bool en)
{
	u32 val = enetc_txbdr_rd(hw, si_idx, ENETC_TBMR);

	val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0);
	enetc_txbdr_wr(hw, si_idx, ENETC_TBMR, val);
}

static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx,
				      int prio)
{
	u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR);

	val &= ~ENETC_TBMR_PRIO_MASK;
	val |= ENETC_TBMR_SET_PRIO(prio);
	enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val);
}

enum bdcr_cmd_class {
	BDCR_CMD_UNSPEC = 0,
	BDCR_CMD_MAC_FILTER,
	BDCR_CMD_VLAN_FILTER,
	BDCR_CMD_RSS,
	BDCR_CMD_RFS,
	BDCR_CMD_PORT_GCL,
	BDCR_CMD_RECV_CLASSIFIER,
	__BDCR_CMD_MAX_LEN,
	BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
};

/* class 5, command 0 */
struct tgs_gcl_conf {
	u8	atc;	/* init gate value */
	u8	res[7];
	struct {
		u8	res1[4];
		__le16	acl_len;
		u8	res2[2];
	};
};

/* gate control list entry */
struct gce {
	__le32	period;
	u8	gate;
	u8	res[3];
};

/* tgs_gcl_conf address point to this data space */
struct tgs_gcl_data {
	__le32		btl;
	__le32		bth;
	__le32		ct;
	__le32		cte;
	struct gce	entry[0];
};

struct enetc_cbd {
	union{
		struct {
			__le32	addr[2];
			union {
				__le32	opt[4];
				struct tgs_gcl_conf	gcl_conf;
			};
		};	/* Long format */
		__le32 data[6];
	};
	__le16 index;
	__le16 length;
	u8 cmd;
	u8 cls;
	u8 _res;
	u8 status_flags;
};

#define ENETC_CLK  400000000ULL

/* port time gating control register */
#define ENETC_QBV_PTGCR_OFFSET		0x11a00
#define ENETC_QBV_TGE			BIT(31)
#define ENETC_QBV_TGPE			BIT(30)

/* Port time gating capability register */
#define ENETC_QBV_PTGCAPR_OFFSET	0x11a08
#define ENETC_QBV_MAX_GCL_LEN_MASK	GENMASK(15, 0)

/* Port time specific departure */
#define ENETC_PTCTSDR(n)	(0x1210 + 4 * (n))
#define ENETC_TSDE		BIT(31)
Commit	Line	Data
d4fd0404 CM	1	/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
	2	/* Copyright 2017-2019 NXP */
	3
	4	#include <linux/bitops.h>
	5
	6	/* ENETC device IDs */
19971f5e YL	7	#define ENETC_DEV_ID_PF 0xe100
	8	#define ENETC_DEV_ID_VF 0xef00
	9	#define ENETC_DEV_ID_PTP 0xee02
d4fd0404 CM	10
	11	/* ENETC register block BAR */
	12	#define ENETC_BAR_REGS 0
	13
	14	/** SI regs, offset: 0h */
	15	#define ENETC_SIMR 0
	16	#define ENETC_SIMR_EN BIT(31)
d382563f	17	#define ENETC_SIMR_RSSE BIT(0)
d4fd0404 CM	18	#define ENETC_SICTR0 0x18
	19	#define ENETC_SICTR1 0x1c
	20	#define ENETC_SIPCAPR0 0x20
34c6adf1	21	#define ENETC_SIPCAPR0_QBV BIT(4)
d382563f	22	#define ENETC_SIPCAPR0_RSS BIT(8)
d4fd0404 CM	23	#define ENETC_SIPCAPR1 0x24
	24	#define ENETC_SITGTGR 0x30
	25	#define ENETC_SIRBGCR 0x38
	26	/* cache attribute registers for transactions initiated by ENETC */
	27	#define ENETC_SICAR0 0x40
	28	#define ENETC_SICAR1 0x44
	29	#define ENETC_SICAR2 0x48
	30	/* rd snoop, no alloc
	31	* wr snoop, no alloc, partial cache line update for BDs and full cache line
	32	* update for data
	33	*/
	34	#define ENETC_SICAR_RD_COHERENT 0x2b2b0000
	35	#define ENETC_SICAR_WR_COHERENT 0x00006727
	36	#define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
	37
	38	#define ENETC_SIPMAR0 0x80
	39	#define ENETC_SIPMAR1 0x84
	40
beb74ac8 CM	41	/* VF-PF Message passing */
	42	#define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */
	43	/* msg size encoding: default and max msg value of 1024B encoded as 0 */
	44	static inline u32 enetc_vsi_set_msize(u32 size)
	45	{
	46	return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0;
	47	}
	48
	49	#define ENETC_PSIMSGRR 0x204
	50	#define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1)
	51	#define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
	52	#define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
	53	#define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
	54
	55	#define ENETC_VSIMSGSR 0x204 /* RO */
	56	#define ENETC_VSIMSGSR_MB BIT(0)
	57	#define ENETC_VSIMSGSR_MS BIT(1)
	58	#define ENETC_VSIMSGSNDAR0 0x210
	59	#define ENETC_VSIMSGSNDAR1 0x214
	60
	61	#define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
	62	#define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)
	63
16eb4c85 CM	64	/* SI statistics */
	65	#define ENETC_SIROCT 0x300
	66	#define ENETC_SIRFRM 0x308
	67	#define ENETC_SIRUCA 0x310
	68	#define ENETC_SIRMCA 0x318
	69	#define ENETC_SITOCT 0x320
	70	#define ENETC_SITFRM 0x328
	71	#define ENETC_SITUCA 0x330
	72	#define ENETC_SITMCA 0x338
	73	#define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
	74
d4fd0404 CM	75	/* Control BDR regs */
	76	#define ENETC_SICBDRMR 0x800
	77	#define ENETC_SICBDRSR 0x804 /* RO */
	78	#define ENETC_SICBDRBAR0 0x810
	79	#define ENETC_SICBDRBAR1 0x814
	80	#define ENETC_SICBDRPIR 0x818
	81	#define ENETC_SICBDRCIR 0x81c
	82	#define ENETC_SICBDRLENR 0x820
	83
	84	#define ENETC_SICAPR0 0x900
	85	#define ENETC_SICAPR1 0x904
	86
	87	#define ENETC_PSIIER 0xa00
	88	#define ENETC_PSIIER_MR_MASK GENMASK(2, 1)
	89	#define ENETC_PSIIDR 0xa08
	90	#define ENETC_SITXIDR 0xa18
	91	#define ENETC_SIRXIDR 0xa28
	92	#define ENETC_SIMSIVR 0xa30
	93
	94	#define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
	95	#define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
	96
	97	#define ENETC_SIUEFDCR 0xe28
	98
d382563f CM	99	#define ENETC_SIRFSCAPR 0x1200
	100	#define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
	101	#define ENETC_SIRSSCAPR 0x1600
	102	#define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
	103
d4fd0404 CM	104	/** SI BDR sub-blocks, n = 0..7 */
	105	enum enetc_bdr_type {TX, RX};
	106	#define ENETC_BDR_OFF(i) ((i) * 0x200)
	107	#define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
	108	/* RX BDR reg offsets */
	109	#define ENETC_RBMR 0
	110	#define ENETC_RBMR_BDS BIT(2)
	111	#define ENETC_RBMR_VTE BIT(5)
	112	#define ENETC_RBMR_EN BIT(31)
	113	#define ENETC_RBSR 0x4
	114	#define ENETC_RBBSR 0x8
	115	#define ENETC_RBCIR 0xc
	116	#define ENETC_RBBAR0 0x10
	117	#define ENETC_RBBAR1 0x14
	118	#define ENETC_RBPIR 0x18
	119	#define ENETC_RBLENR 0x20
	120	#define ENETC_RBIER 0xa0
	121	#define ENETC_RBIER_RXTIE BIT(0)
	122	#define ENETC_RBIDR 0xa4
	123	#define ENETC_RBICIR0 0xa8
	124	#define ENETC_RBICIR0_ICEN BIT(31)
	125
	126	/* TX BDR reg offsets */
	127	#define ENETC_TBMR 0
	128	#define ENETC_TBSR_BUSY BIT(0)
	129	#define ENETC_TBMR_VIH BIT(9)
	130	#define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
cbe9e835	131	#define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK)
d4fd0404 CM	132	#define ENETC_TBMR_EN BIT(31)
	133	#define ENETC_TBSR 0x4
	134	#define ENETC_TBBAR0 0x10
	135	#define ENETC_TBBAR1 0x14
	136	#define ENETC_TBPIR 0x18
	137	#define ENETC_TBCIR 0x1c
	138	#define ENETC_TBCIR_IDX_MASK 0xffff
	139	#define ENETC_TBLENR 0x20
	140	#define ENETC_TBIER 0xa0
	141	#define ENETC_TBIER_TXTIE BIT(0)
	142	#define ENETC_TBIDR 0xa4
	143	#define ENETC_TBICIR0 0xa8
	144	#define ENETC_TBICIR0_ICEN BIT(31)
	145
	146	#define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
	147
	148	/* Port regs, offset: 1_0000h */
	149	#define ENETC_PORT_BASE 0x10000
	150	#define ENETC_PMR 0x0000
	151	#define ENETC_PMR_EN GENMASK(18, 16)
2e47cb41 PL	152	#define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)
	153	#define ENETC_PMR_PSPEED_10M 0
	154	#define ENETC_PMR_PSPEED_100M BIT(8)
	155	#define ENETC_PMR_PSPEED_1000M BIT(9)
	156	#define ENETC_PMR_PSPEED_2500M BIT(10)
d4fd0404 CM	157	#define ENETC_PSR 0x0004 /* RO */
	158	#define ENETC_PSIPMR 0x0018
	159	#define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */
	160	#define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16)
	161	#define ENETC_PSIPVMR 0x001c
	162	#define ENETC_VLAN_PROMISC_MAP_ALL 0x7
	163	#define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
	164	#define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
	165	#define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
	166	#define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
	167	#define ENETC_PVCLCTR 0x0208
	168	#define ENETC_VLAN_TYPE_C BIT(0)
	169	#define ENETC_VLAN_TYPE_S BIT(1)
	170	#define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
	171	#define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
	172	#define ENETC_PSIVLAN_EN BIT(31)
	173	#define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12)
	174	#define ENETC_PTXMBAR 0x0608
	175	#define ENETC_PCAPR0 0x0900
	176	#define ENETC_PCAPR0_RXBDR(val) ((val) >> 24)
	177	#define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
	178	#define ENETC_PCAPR1 0x0904
	179	#define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
	180	#define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
	181	#define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
	182	#define ENETC_PSICFGR0_VTE BIT(12)
	183	#define ENETC_PSICFGR0_SIVIE BIT(14)
	184	#define ENETC_PSICFGR0_ASE BIT(15)
	185	#define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
	186
	187	#define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
c431047c PL	188	#define ENETC_CBSE BIT(31)
c431047c PL	189	#define ENETC_CBS_BW_MASK GENMASK(6, 0)
d4fd0404	190	#define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
d382563f CM	191	#define ENETC_RSSHASH_KEY_SIZE 40
d382563f CM	192	#define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
d4fd0404 CM	193	#define ENETC_PSIVLANFMR 0x1700
d4fd0404 CM	194	#define ENETC_PSIVLANFMR_VS BIT(0)
d382563f CM	195	#define ENETC_PRFSMR 0x1800
	196	#define ENETC_PRFSMR_RFSE BIT(31)
	197	#define ENETC_PRFSCAPR 0x1804
	198	#define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
	199	#define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
d4fd0404 CM	200	#define ENETC_PFPMR 0x1900
	201	#define ENETC_PFPMR_PMACE BIT(1)
	202	#define ENETC_PFPMR_MWLM BIT(0)
6517798d	203	#define ENETC_EMDIO_BASE 0x1c00
d4fd0404 CM	204	#define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
	205	#define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
	206	#define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
	207	#define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
	208	#define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
	209	#define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
	210	#define ENETC_MMCSR 0x1f00
	211	#define ENETC_MMCSR_ME BIT(16)
	212	#define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
	213
	214	#define ENETC_PM0_CMD_CFG 0x8008
	215	#define ENETC_PM1_CMD_CFG 0x9008
	216	#define ENETC_PM0_TX_EN BIT(0)
	217	#define ENETC_PM0_RX_EN BIT(1)
	218	#define ENETC_PM0_PROMISC BIT(4)
	219	#define ENETC_PM0_CMD_XGLP BIT(10)
	220	#define ENETC_PM0_CMD_TXP BIT(11)
	221	#define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
	222	#define ENETC_PM0_CMD_SFD BIT(21)
	223	#define ENETC_PM0_MAXFRM 0x8014
	224	#define ENETC_SET_TX_MTU(val) ((val) << 16)
	225	#define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
	226	#define ENETC_PM0_IF_MODE 0x8300
	227	#define ENETC_PMO_IFM_RG BIT(2)
	228	#define ENETC_PM0_IFM_RLP (BIT(5) \| BIT(11))
	229	#define ENETC_PM0_IFM_RGAUTO (BIT(15) \| ENETC_PMO_IFM_RG \| BIT(1))
	230	#define ENETC_PM0_IFM_XGMII BIT(12)
	231
16eb4c85 CM	232	/* MAC counters */
	233	#define ENETC_PM0_REOCT 0x8100
	234	#define ENETC_PM0_RALN 0x8110
	235	#define ENETC_PM0_RXPF 0x8118
	236	#define ENETC_PM0_RFRM 0x8120
	237	#define ENETC_PM0_RFCS 0x8128
	238	#define ENETC_PM0_RVLAN 0x8130
	239	#define ENETC_PM0_RERR 0x8138
	240	#define ENETC_PM0_RUCA 0x8140
	241	#define ENETC_PM0_RMCA 0x8148
	242	#define ENETC_PM0_RBCA 0x8150
	243	#define ENETC_PM0_RDRP 0x8158
	244	#define ENETC_PM0_RPKT 0x8160
	245	#define ENETC_PM0_RUND 0x8168
	246	#define ENETC_PM0_R64 0x8170
	247	#define ENETC_PM0_R127 0x8178
	248	#define ENETC_PM0_R255 0x8180
	249	#define ENETC_PM0_R511 0x8188
	250	#define ENETC_PM0_R1023 0x8190
	251	#define ENETC_PM0_R1518 0x8198
	252	#define ENETC_PM0_R1519X 0x81A0
	253	#define ENETC_PM0_ROVR 0x81A8
	254	#define ENETC_PM0_RJBR 0x81B0
	255	#define ENETC_PM0_RFRG 0x81B8
	256	#define ENETC_PM0_RCNP 0x81C0
	257	#define ENETC_PM0_RDRNTP 0x81C8
	258	#define ENETC_PM0_TEOCT 0x8200
	259	#define ENETC_PM0_TOCT 0x8208
	260	#define ENETC_PM0_TCRSE 0x8210
	261	#define ENETC_PM0_TXPF 0x8218
	262	#define ENETC_PM0_TFRM 0x8220
	263	#define ENETC_PM0_TFCS 0x8228
	264	#define ENETC_PM0_TVLAN 0x8230
	265	#define ENETC_PM0_TERR 0x8238
	266	#define ENETC_PM0_TUCA 0x8240
	267	#define ENETC_PM0_TMCA 0x8248
	268	#define ENETC_PM0_TBCA 0x8250
	269	#define ENETC_PM0_TPKT 0x8260
	270	#define ENETC_PM0_TUND 0x8268
	271	#define ENETC_PM0_T127 0x8278
	272	#define ENETC_PM0_T1023 0x8290
	273	#define ENETC_PM0_T1518 0x8298
	274	#define ENETC_PM0_TCNP 0x82C0
	275	#define ENETC_PM0_TDFR 0x82D0
	276	#define ENETC_PM0_TMCOL 0x82D8
	277	#define ENETC_PM0_TSCOL 0x82E0
	278	#define ENETC_PM0_TLCOL 0x82E8
	279	#define ENETC_PM0_TECOL 0x82F0
	280
	281	/* Port counters */
	282	#define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
	283	#define ENETC_PBFDSIR 0x0810
	284	#define ENETC_PFDMSAPR 0x0814
	285	#define ENETC_UFDMF 0x1680
	286	#define ENETC_MFDMF 0x1684
	287	#define ENETC_PUFDVFR 0x1780
	288	#define ENETC_PMFDVFR 0x1784
	289	#define ENETC_PBFDVFR 0x1788
	290
d4fd0404 CM	291	/** Global regs, offset: 2_0000h */
	292	#define ENETC_GLOBAL_BASE 0x20000
	293	#define ENETC_G_EIPBRR0 0x0bf8
	294	#define ENETC_G_EIPBRR1 0x0bfc
	295	#define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
	296	#define ENETC_G_EPFBLPR1_XGMII 0x80000000
	297
	298	/* PCI device info */
	299	struct enetc_hw {
	300	/* SI registers, used by all PCI functions */
	301	void __iomem *reg;
	302	/* Port registers, PF only */
	303	void __iomem *port;
	304	/* IP global registers, PF only */
	305	void __iomem *global;
	306	};
	307
	308	/* general register accessors */
	309	#define enetc_rd_reg(reg) ioread32((reg))
	310	#define enetc_wr_reg(reg, val) iowrite32((val), (reg))
16eb4c85 CM	311	#ifdef ioread64
	312	#define enetc_rd_reg64(reg) ioread64((reg))
	313	#else
	314	/* using this to read out stats on 32b systems */
	315	static inline u64 enetc_rd_reg64(void __iomem *reg)
	316	{
	317	u32 low, high, tmp;
	318
	319	do {
	320	high = ioread32(reg + 4);
	321	low = ioread32(reg);
	322	tmp = ioread32(reg + 4);
	323	} while (high != tmp);
	324
	325	return le64_to_cpu((__le64)high << 32 \| low);
	326	}
	327	#endif
d4fd0404 CM	328
	329	#define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off))
	330	#define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val)
16eb4c85	331	#define enetc_rd64(hw, off) enetc_rd_reg64((hw)->reg + (off))
d4fd0404 CM	332	/* port register accessors - PF only */
	333	#define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off))
	334	#define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val)
	335	/* global register accessors - PF only */
	336	#define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off))
	337	#define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val)
	338	/* BDR register accessors, see ENETC_BDR() */
	339	#define enetc_bdr_rd(hw, t, n, off) \
	340	enetc_rd(hw, ENETC_BDR(t, n, off))
	341	#define enetc_bdr_wr(hw, t, n, off, val) \
	342	enetc_wr(hw, ENETC_BDR(t, n, off), val)
	343	#define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
	344	#define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
	345	#define enetc_txbdr_wr(hw, n, off, val) \
	346	enetc_bdr_wr(hw, TX, n, off, val)
	347	#define enetc_rxbdr_wr(hw, n, off, val) \
	348	enetc_bdr_wr(hw, RX, n, off, val)
	349
	350	/* Buffer Descriptors (BD) */
	351	union enetc_tx_bd {
	352	struct {
	353	__le64 addr;
	354	__le16 buf_len;
	355	__le16 frm_len;
	356	union {
	357	struct {
	358	__le16 l3_csoff;
	359	u8 l4_csoff;
	360	u8 flags;
	361	}; /* default layout */
0d08c9ec	362	__le32 txstart;
d4fd0404 CM	363	__le32 lstatus;
	364	};
	365	};
	366	struct {
	367	__le32 tstamp;
	368	__le16 tpid;
	369	__le16 vid;
	370	u8 reserved[6];
	371	u8 e_flags;
	372	u8 flags;
	373	} ext; /* Tx BD extension */
d3982312 L	374	struct {
	375	__le32 tstamp;
	376	u8 reserved[10];
	377	u8 status;
	378	u8 flags;
	379	} wb; /* writeback descriptor */
d4fd0404 CM	380	};
	381
	382	#define ENETC_TXBD_FLAGS_L4CS BIT(0)
0d08c9ec	383	#define ENETC_TXBD_FLAGS_TSE BIT(1)
d4fd0404 CM	384	#define ENETC_TXBD_FLAGS_W BIT(2)
d4fd0404 CM	385	#define ENETC_TXBD_FLAGS_CSUM BIT(3)
0d08c9ec	386	#define ENETC_TXBD_FLAGS_TXSTART BIT(4)
d4fd0404 CM	387	#define ENETC_TXBD_FLAGS_EX BIT(6)
d4fd0404 CM	388	#define ENETC_TXBD_FLAGS_F BIT(7)
0d08c9ec PL	389	#define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
0d08c9ec PL	390	#define ENETC_TXBD_FLAGS_OFFSET 24
d4fd0404 CM	391	static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
	392	{
	393	memset(txbd, 0, sizeof(*txbd));
	394	}
	395
	396	/* L3 csum flags */
	397	#define ENETC_TXBD_L3_IPCS BIT(7)
	398	#define ENETC_TXBD_L3_IPV6 BIT(15)
	399
	400	#define ENETC_TXBD_L3_START_MASK GENMASK(6, 0)
	401	#define ENETC_TXBD_L3_SET_HSIZE(val) ((((val) >> 2) & 0x7f) << 8)
	402
	403	/* Extension flags */
	404	#define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
	405	#define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
	406
	407	static inline __le16 enetc_txbd_l3_csoff(int start, int hdr_sz, u16 l3_flags)
	408	{
	409	return cpu_to_le16(l3_flags \| ENETC_TXBD_L3_SET_HSIZE(hdr_sz) \|
	410	(start & ENETC_TXBD_L3_START_MASK));
	411	}
	412
	413	/* L4 csum flags */
	414	#define ENETC_TXBD_L4_UDP BIT(5)
	415	#define ENETC_TXBD_L4_TCP BIT(6)
	416
	417	union enetc_rx_bd {
	418	struct {
	419	__le64 addr;
	420	u8 reserved[8];
d3982312 L	421	#ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING
	422	u8 reserved1[16];
	423	#endif
d4fd0404 CM	424	} w;
	425	struct {
	426	__le16 inet_csum;
	427	__le16 parse_summary;
	428	__le32 rss_hash;
	429	__le16 buf_len;
	430	__le16 vlan_opt;
	431	union {
	432	struct {
	433	__le16 flags;
	434	__le16 error;
	435	};
	436	__le32 lstatus;
	437	};
d3982312 L	438	#ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING
	439	__le32 tstamp;
	440	u8 reserved[12];
	441	#endif
d4fd0404 CM	442	} r;
	443	};
	444
	445	#define ENETC_RXBD_LSTATUS_R BIT(30)
	446	#define ENETC_RXBD_LSTATUS_F BIT(31)
	447	#define ENETC_RXBD_ERR_MASK 0xff
	448	#define ENETC_RXBD_LSTATUS(flags) ((flags) << 16)
	449	#define ENETC_RXBD_FLAG_VLAN BIT(9)
	450	#define ENETC_RXBD_FLAG_TSTMP BIT(10)
	451
	452	#define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */
	453	#define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */
	454	#define ENETC_MAX_NUM_VFS 2
	455
d4fd0404 CM	456	#define ENETC_CBD_FLAGS_SF BIT(7) /* short format */
	457	#define ENETC_CBD_STATUS_MASK 0xf
	458
d382563f CM	459	struct enetc_cmd_rfse {
	460	u8 smac_h[6];
	461	u8 smac_m[6];
	462	u8 dmac_h[6];
	463	u8 dmac_m[6];
	464	u32 sip_h[4];
	465	u32 sip_m[4];
	466	u32 dip_h[4];
	467	u32 dip_m[4];
	468	u16 ethtype_h;
	469	u16 ethtype_m;
	470	u16 ethtype4_h;
	471	u16 ethtype4_m;
	472	u16 sport_h;
	473	u16 sport_m;
	474	u16 dport_h;
	475	u16 dport_m;
	476	u16 vlan_h;
	477	u16 vlan_m;
	478	u8 proto_h;
	479	u8 proto_m;
	480	u16 flags;
	481	u16 result;
	482	u16 mode;
	483	};
	484
	485	#define ENETC_RFSE_EN BIT(15)
	486	#define ENETC_RFSE_MODE_BD 2
	487
d4fd0404 CM	488	static inline void enetc_get_primary_mac_addr(struct enetc_hw hw, u8 addr)
	489	{
	490	(u32 )addr = __raw_readl(hw->reg + ENETC_SIPMAR0);
	491	(u16 )(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1);
	492	}
	493
	494	#define ENETC_SI_INT_IDX 0
	495	/* base index for Rx/Tx interrupts */
	496	#define ENETC_BDR_INT_BASE_IDX 1
	497
beb74ac8 CM	498	/* Messaging */
	499
	500	/* Command completion status */
	501	enum enetc_msg_cmd_status {
	502	ENETC_MSG_CMD_STATUS_OK,
	503	ENETC_MSG_CMD_STATUS_FAIL
	504	};
	505
	506	/* VSI-PSI command message types */
	507	enum enetc_msg_cmd_type {
	508	ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
	509	ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
	510	ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
	511	};
	512
	513	/* VSI-PSI command action types */
	514	enum enetc_msg_cmd_action_type {
	515	ENETC_MSG_CMD_MNG_ADD = 1,
	516	ENETC_MSG_CMD_MNG_REMOVE
	517	};
	518
	519	/* PSI-VSI command header format */
	520	struct enetc_msg_cmd_header {
	521	u16 type; /* command class type */
	522	u16 id; /* denotes the specific required action */
	523	};
	524
d4fd0404 CM	525	/* Common H/W utility functions */
	526
	527	static inline void enetc_enable_rxvlan(struct enetc_hw *hw, int si_idx,
	528	bool en)
	529	{
	530	u32 val = enetc_rxbdr_rd(hw, si_idx, ENETC_RBMR);
	531
	532	val = (val & ~ENETC_RBMR_VTE) \| (en ? ENETC_RBMR_VTE : 0);
	533	enetc_rxbdr_wr(hw, si_idx, ENETC_RBMR, val);
	534	}
	535
	536	static inline void enetc_enable_txvlan(struct enetc_hw *hw, int si_idx,
	537	bool en)
	538	{
	539	u32 val = enetc_txbdr_rd(hw, si_idx, ENETC_TBMR);
	540
	541	val = (val & ~ENETC_TBMR_VIH) \| (en ? ENETC_TBMR_VIH : 0);
	542	enetc_txbdr_wr(hw, si_idx, ENETC_TBMR, val);
	543	}
cbe9e835 CG	544
	545	static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx,
	546	int prio)
	547	{
	548	u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR);
	549
	550	val &= ~ENETC_TBMR_PRIO_MASK;
	551	val \|= ENETC_TBMR_SET_PRIO(prio);
	552	enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val);
	553	}
34c6adf1 PL	554
	555	enum bdcr_cmd_class {
	556	BDCR_CMD_UNSPEC = 0,
	557	BDCR_CMD_MAC_FILTER,
	558	BDCR_CMD_VLAN_FILTER,
	559	BDCR_CMD_RSS,
	560	BDCR_CMD_RFS,
	561	BDCR_CMD_PORT_GCL,
	562	BDCR_CMD_RECV_CLASSIFIER,
	563	__BDCR_CMD_MAX_LEN,
	564	BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
	565	};
	566
	567	/* class 5, command 0 */
	568	struct tgs_gcl_conf {
	569	u8 atc; /* init gate value */
	570	u8 res[7];
	571	struct {
	572	u8 res1[4];
	573	__le16 acl_len;
	574	u8 res2[2];
	575	};
	576	};
	577
	578	/* gate control list entry */
	579	struct gce {
	580	__le32 period;
	581	u8 gate;
	582	u8 res[3];
	583	};
	584
	585	/* tgs_gcl_conf address point to this data space */
	586	struct tgs_gcl_data {
	587	__le32 btl;
	588	__le32 bth;
	589	__le32 ct;
	590	__le32 cte;
	591	struct gce entry[0];
	592	};
	593
	594	struct enetc_cbd {
	595	union{
	596	struct {
	597	__le32 addr[2];
	598	union {
	599	__le32 opt[4];
	600	struct tgs_gcl_conf gcl_conf;
	601	};
	602	}; /* Long format */
	603	__le32 data[6];
	604	};
	605	__le16 index;
	606	__le16 length;
	607	u8 cmd;
	608	u8 cls;
	609	u8 _res;
	610	u8 status_flags;
	611	};
	612
c431047c PL	613	#define ENETC_CLK 400000000ULL
c431047c PL	614
34c6adf1 PL	615	/* port time gating control register */
	616	#define ENETC_QBV_PTGCR_OFFSET 0x11a00
	617	#define ENETC_QBV_TGE BIT(31)
	618	#define ENETC_QBV_TGPE BIT(30)
	619
	620	/* Port time gating capability register */
	621	#define ENETC_QBV_PTGCAPR_OFFSET 0x11a08
	622	#define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0)
0d08c9ec PL	623
	624	/* Port time specific departure */
	625	#define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
	626	#define ENETC_TSDE BIT(31)