Commit | Line | Data |
---|---|---|
69785b79 PYC |
1 | /* |
2 | * Faraday FTGMAC100 Gigabit Ethernet | |
3 | * | |
4 | * (C) Copyright 2009-2011 Faraday Technology | |
5 | * Po-Yu Chuang <ratbert@faraday-tech.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
23 | ||
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/ethtool.h> | |
27 | #include <linux/init.h> | |
17f1bbca | 28 | #include <linux/interrupt.h> |
69785b79 PYC |
29 | #include <linux/io.h> |
30 | #include <linux/module.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/phy.h> | |
33 | #include <linux/platform_device.h> | |
34 | #include <net/ip.h> | |
35 | ||
36 | #include "ftgmac100.h" | |
37 | ||
38 | #define DRV_NAME "ftgmac100" | |
39 | #define DRV_VERSION "0.7" | |
40 | ||
41 | #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */ | |
42 | #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */ | |
43 | ||
44 | #define MAX_PKT_SIZE 1518 | |
45 | #define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */ | |
46 | ||
47 | /****************************************************************************** | |
48 | * private data | |
49 | *****************************************************************************/ | |
50 | struct ftgmac100_descs { | |
51 | struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES]; | |
52 | struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES]; | |
53 | }; | |
54 | ||
55 | struct ftgmac100 { | |
56 | struct resource *res; | |
57 | void __iomem *base; | |
58 | int irq; | |
59 | ||
60 | struct ftgmac100_descs *descs; | |
61 | dma_addr_t descs_dma_addr; | |
62 | ||
63 | unsigned int rx_pointer; | |
64 | unsigned int tx_clean_pointer; | |
65 | unsigned int tx_pointer; | |
66 | unsigned int tx_pending; | |
67 | ||
68 | spinlock_t tx_lock; | |
69 | ||
70 | struct net_device *netdev; | |
71 | struct device *dev; | |
72 | struct napi_struct napi; | |
73 | ||
74 | struct mii_bus *mii_bus; | |
75 | int phy_irq[PHY_MAX_ADDR]; | |
76 | struct phy_device *phydev; | |
77 | int old_speed; | |
78 | }; | |
79 | ||
80 | static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, | |
81 | struct ftgmac100_rxdes *rxdes, gfp_t gfp); | |
82 | ||
83 | /****************************************************************************** | |
84 | * internal functions (hardware register access) | |
85 | *****************************************************************************/ | |
86 | #define INT_MASK_ALL_ENABLED (FTGMAC100_INT_RPKT_LOST | \ | |
87 | FTGMAC100_INT_XPKT_ETH | \ | |
88 | FTGMAC100_INT_XPKT_LOST | \ | |
89 | FTGMAC100_INT_AHB_ERR | \ | |
90 | FTGMAC100_INT_PHYSTS_CHG | \ | |
91 | FTGMAC100_INT_RPKT_BUF | \ | |
92 | FTGMAC100_INT_NO_RXBUF) | |
93 | ||
94 | static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr) | |
95 | { | |
96 | iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR); | |
97 | } | |
98 | ||
99 | static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv, | |
100 | unsigned int size) | |
101 | { | |
102 | size = FTGMAC100_RBSR_SIZE(size); | |
103 | iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR); | |
104 | } | |
105 | ||
106 | static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv, | |
107 | dma_addr_t addr) | |
108 | { | |
109 | iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); | |
110 | } | |
111 | ||
112 | static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv) | |
113 | { | |
114 | iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); | |
115 | } | |
116 | ||
117 | static int ftgmac100_reset_hw(struct ftgmac100 *priv) | |
118 | { | |
119 | struct net_device *netdev = priv->netdev; | |
120 | int i; | |
121 | ||
122 | /* NOTE: reset clears all registers */ | |
123 | iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR); | |
124 | for (i = 0; i < 5; i++) { | |
125 | unsigned int maccr; | |
126 | ||
127 | maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); | |
128 | if (!(maccr & FTGMAC100_MACCR_SW_RST)) | |
129 | return 0; | |
130 | ||
131 | udelay(1000); | |
132 | } | |
133 | ||
134 | netdev_err(netdev, "software reset failed\n"); | |
135 | return -EIO; | |
136 | } | |
137 | ||
138 | static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac) | |
139 | { | |
140 | unsigned int maddr = mac[0] << 8 | mac[1]; | |
141 | unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; | |
142 | ||
143 | iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); | |
144 | iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); | |
145 | } | |
146 | ||
147 | static void ftgmac100_init_hw(struct ftgmac100 *priv) | |
148 | { | |
149 | /* setup ring buffer base registers */ | |
150 | ftgmac100_set_rx_ring_base(priv, | |
151 | priv->descs_dma_addr + | |
152 | offsetof(struct ftgmac100_descs, rxdes)); | |
153 | ftgmac100_set_normal_prio_tx_ring_base(priv, | |
154 | priv->descs_dma_addr + | |
155 | offsetof(struct ftgmac100_descs, txdes)); | |
156 | ||
157 | ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE); | |
158 | ||
159 | iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC); | |
160 | ||
161 | ftgmac100_set_mac(priv, priv->netdev->dev_addr); | |
162 | } | |
163 | ||
164 | #define MACCR_ENABLE_ALL (FTGMAC100_MACCR_TXDMA_EN | \ | |
165 | FTGMAC100_MACCR_RXDMA_EN | \ | |
166 | FTGMAC100_MACCR_TXMAC_EN | \ | |
167 | FTGMAC100_MACCR_RXMAC_EN | \ | |
168 | FTGMAC100_MACCR_FULLDUP | \ | |
169 | FTGMAC100_MACCR_CRC_APD | \ | |
170 | FTGMAC100_MACCR_RX_RUNT | \ | |
171 | FTGMAC100_MACCR_RX_BROADPKT) | |
172 | ||
173 | static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed) | |
174 | { | |
175 | int maccr = MACCR_ENABLE_ALL; | |
176 | ||
177 | switch (speed) { | |
178 | default: | |
179 | case 10: | |
180 | break; | |
181 | ||
182 | case 100: | |
183 | maccr |= FTGMAC100_MACCR_FAST_MODE; | |
184 | break; | |
185 | ||
186 | case 1000: | |
187 | maccr |= FTGMAC100_MACCR_GIGA_MODE; | |
188 | break; | |
189 | } | |
190 | ||
191 | iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); | |
192 | } | |
193 | ||
194 | static void ftgmac100_stop_hw(struct ftgmac100 *priv) | |
195 | { | |
196 | iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); | |
197 | } | |
198 | ||
199 | /****************************************************************************** | |
200 | * internal functions (receive descriptor) | |
201 | *****************************************************************************/ | |
202 | static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes) | |
203 | { | |
204 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS); | |
205 | } | |
206 | ||
207 | static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes) | |
208 | { | |
209 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS); | |
210 | } | |
211 | ||
212 | static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes) | |
213 | { | |
214 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY); | |
215 | } | |
216 | ||
217 | static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes) | |
218 | { | |
219 | /* clear status bits */ | |
220 | rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR); | |
221 | } | |
222 | ||
223 | static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes) | |
224 | { | |
225 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR); | |
226 | } | |
227 | ||
228 | static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes) | |
229 | { | |
230 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR); | |
231 | } | |
232 | ||
233 | static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes) | |
234 | { | |
235 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL); | |
236 | } | |
237 | ||
238 | static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes) | |
239 | { | |
240 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT); | |
241 | } | |
242 | ||
243 | static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes) | |
244 | { | |
245 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB); | |
246 | } | |
247 | ||
248 | static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes) | |
249 | { | |
250 | return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC; | |
251 | } | |
252 | ||
253 | static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes) | |
254 | { | |
255 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST); | |
256 | } | |
257 | ||
258 | static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes) | |
259 | { | |
260 | rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR); | |
261 | } | |
262 | ||
263 | static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes, | |
264 | dma_addr_t addr) | |
265 | { | |
266 | rxdes->rxdes3 = cpu_to_le32(addr); | |
267 | } | |
268 | ||
269 | static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes) | |
270 | { | |
271 | return le32_to_cpu(rxdes->rxdes3); | |
272 | } | |
273 | ||
274 | static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes) | |
275 | { | |
276 | return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == | |
277 | cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP); | |
278 | } | |
279 | ||
280 | static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes) | |
281 | { | |
282 | return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == | |
283 | cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP); | |
284 | } | |
285 | ||
286 | static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes) | |
287 | { | |
288 | return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR); | |
289 | } | |
290 | ||
291 | static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes) | |
292 | { | |
293 | return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR); | |
294 | } | |
295 | ||
296 | static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes) | |
297 | { | |
298 | return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR); | |
299 | } | |
300 | ||
301 | /* | |
302 | * rxdes2 is not used by hardware. We use it to keep track of page. | |
303 | * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). | |
304 | */ | |
305 | static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page) | |
306 | { | |
307 | rxdes->rxdes2 = (unsigned int)page; | |
308 | } | |
309 | ||
310 | static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes) | |
311 | { | |
312 | return (struct page *)rxdes->rxdes2; | |
313 | } | |
314 | ||
315 | /****************************************************************************** | |
316 | * internal functions (receive) | |
317 | *****************************************************************************/ | |
318 | static int ftgmac100_next_rx_pointer(int pointer) | |
319 | { | |
320 | return (pointer + 1) & (RX_QUEUE_ENTRIES - 1); | |
321 | } | |
322 | ||
323 | static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv) | |
324 | { | |
325 | priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer); | |
326 | } | |
327 | ||
328 | static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv) | |
329 | { | |
330 | return &priv->descs->rxdes[priv->rx_pointer]; | |
331 | } | |
332 | ||
333 | static struct ftgmac100_rxdes * | |
334 | ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv) | |
335 | { | |
336 | struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); | |
337 | ||
338 | while (ftgmac100_rxdes_packet_ready(rxdes)) { | |
339 | if (ftgmac100_rxdes_first_segment(rxdes)) | |
340 | return rxdes; | |
341 | ||
342 | ftgmac100_rxdes_set_dma_own(rxdes); | |
343 | ftgmac100_rx_pointer_advance(priv); | |
344 | rxdes = ftgmac100_current_rxdes(priv); | |
345 | } | |
346 | ||
347 | return NULL; | |
348 | } | |
349 | ||
350 | static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv, | |
351 | struct ftgmac100_rxdes *rxdes) | |
352 | { | |
353 | struct net_device *netdev = priv->netdev; | |
354 | bool error = false; | |
355 | ||
356 | if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) { | |
357 | if (net_ratelimit()) | |
358 | netdev_info(netdev, "rx err\n"); | |
359 | ||
360 | netdev->stats.rx_errors++; | |
361 | error = true; | |
362 | } | |
363 | ||
364 | if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) { | |
365 | if (net_ratelimit()) | |
366 | netdev_info(netdev, "rx crc err\n"); | |
367 | ||
368 | netdev->stats.rx_crc_errors++; | |
369 | error = true; | |
370 | } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) { | |
371 | if (net_ratelimit()) | |
372 | netdev_info(netdev, "rx IP checksum err\n"); | |
373 | ||
374 | error = true; | |
375 | } | |
376 | ||
377 | if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) { | |
378 | if (net_ratelimit()) | |
379 | netdev_info(netdev, "rx frame too long\n"); | |
380 | ||
381 | netdev->stats.rx_length_errors++; | |
382 | error = true; | |
383 | } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) { | |
384 | if (net_ratelimit()) | |
385 | netdev_info(netdev, "rx runt\n"); | |
386 | ||
387 | netdev->stats.rx_length_errors++; | |
388 | error = true; | |
389 | } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) { | |
390 | if (net_ratelimit()) | |
391 | netdev_info(netdev, "rx odd nibble\n"); | |
392 | ||
393 | netdev->stats.rx_length_errors++; | |
394 | error = true; | |
395 | } | |
396 | ||
397 | return error; | |
398 | } | |
399 | ||
400 | static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv) | |
401 | { | |
402 | struct net_device *netdev = priv->netdev; | |
403 | struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); | |
404 | bool done = false; | |
405 | ||
406 | if (net_ratelimit()) | |
407 | netdev_dbg(netdev, "drop packet %p\n", rxdes); | |
408 | ||
409 | do { | |
410 | if (ftgmac100_rxdes_last_segment(rxdes)) | |
411 | done = true; | |
412 | ||
413 | ftgmac100_rxdes_set_dma_own(rxdes); | |
414 | ftgmac100_rx_pointer_advance(priv); | |
415 | rxdes = ftgmac100_current_rxdes(priv); | |
416 | } while (!done && ftgmac100_rxdes_packet_ready(rxdes)); | |
417 | ||
418 | netdev->stats.rx_dropped++; | |
419 | } | |
420 | ||
421 | static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) | |
422 | { | |
423 | struct net_device *netdev = priv->netdev; | |
424 | struct ftgmac100_rxdes *rxdes; | |
425 | struct sk_buff *skb; | |
426 | bool done = false; | |
427 | ||
428 | rxdes = ftgmac100_rx_locate_first_segment(priv); | |
429 | if (!rxdes) | |
430 | return false; | |
431 | ||
432 | if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) { | |
433 | ftgmac100_rx_drop_packet(priv); | |
434 | return true; | |
435 | } | |
436 | ||
437 | /* start processing */ | |
438 | skb = netdev_alloc_skb_ip_align(netdev, 128); | |
439 | if (unlikely(!skb)) { | |
440 | if (net_ratelimit()) | |
441 | netdev_err(netdev, "rx skb alloc failed\n"); | |
442 | ||
443 | ftgmac100_rx_drop_packet(priv); | |
444 | return true; | |
445 | } | |
446 | ||
447 | if (unlikely(ftgmac100_rxdes_multicast(rxdes))) | |
448 | netdev->stats.multicast++; | |
449 | ||
450 | /* | |
451 | * It seems that HW does checksum incorrectly with fragmented packets, | |
452 | * so we are conservative here - if HW checksum error, let software do | |
453 | * the checksum again. | |
454 | */ | |
455 | if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) || | |
456 | (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes))) | |
457 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
458 | ||
459 | do { | |
460 | dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); | |
461 | struct page *page = ftgmac100_rxdes_get_page(rxdes); | |
462 | unsigned int size; | |
463 | ||
464 | dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); | |
465 | ||
466 | size = ftgmac100_rxdes_data_length(rxdes); | |
467 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size); | |
468 | ||
469 | skb->len += size; | |
470 | skb->data_len += size; | |
5935f81c | 471 | skb->truesize += PAGE_SIZE; |
69785b79 PYC |
472 | |
473 | if (ftgmac100_rxdes_last_segment(rxdes)) | |
474 | done = true; | |
475 | ||
476 | ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC); | |
477 | ||
478 | ftgmac100_rx_pointer_advance(priv); | |
479 | rxdes = ftgmac100_current_rxdes(priv); | |
480 | } while (!done); | |
481 | ||
6ecd09dd ED |
482 | /* Small frames are copied into linear part of skb to free one page */ |
483 | if (skb->len <= 128) { | |
5935f81c | 484 | skb->truesize -= PAGE_SIZE; |
6ecd09dd ED |
485 | __pskb_pull_tail(skb, skb->len); |
486 | } else { | |
487 | /* We pull the minimum amount into linear part */ | |
488 | __pskb_pull_tail(skb, ETH_HLEN); | |
489 | } | |
69785b79 PYC |
490 | skb->protocol = eth_type_trans(skb, netdev); |
491 | ||
492 | netdev->stats.rx_packets++; | |
493 | netdev->stats.rx_bytes += skb->len; | |
494 | ||
495 | /* push packet to protocol stack */ | |
496 | napi_gro_receive(&priv->napi, skb); | |
497 | ||
498 | (*processed)++; | |
499 | return true; | |
500 | } | |
501 | ||
502 | /****************************************************************************** | |
503 | * internal functions (transmit descriptor) | |
504 | *****************************************************************************/ | |
505 | static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes) | |
506 | { | |
507 | /* clear all except end of ring bit */ | |
508 | txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); | |
509 | txdes->txdes1 = 0; | |
510 | txdes->txdes2 = 0; | |
511 | txdes->txdes3 = 0; | |
512 | } | |
513 | ||
514 | static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes) | |
515 | { | |
516 | return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); | |
517 | } | |
518 | ||
519 | static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes) | |
520 | { | |
521 | /* | |
522 | * Make sure dma own bit will not be set before any other | |
523 | * descriptor fields. | |
524 | */ | |
525 | wmb(); | |
526 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); | |
527 | } | |
528 | ||
529 | static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes) | |
530 | { | |
531 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); | |
532 | } | |
533 | ||
534 | static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes) | |
535 | { | |
536 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS); | |
537 | } | |
538 | ||
539 | static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes) | |
540 | { | |
541 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS); | |
542 | } | |
543 | ||
544 | static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes, | |
545 | unsigned int len) | |
546 | { | |
547 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len)); | |
548 | } | |
549 | ||
550 | static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes) | |
551 | { | |
552 | txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC); | |
553 | } | |
554 | ||
555 | static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes) | |
556 | { | |
557 | txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM); | |
558 | } | |
559 | ||
560 | static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes) | |
561 | { | |
562 | txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM); | |
563 | } | |
564 | ||
565 | static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes) | |
566 | { | |
567 | txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM); | |
568 | } | |
569 | ||
570 | static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes, | |
571 | dma_addr_t addr) | |
572 | { | |
573 | txdes->txdes3 = cpu_to_le32(addr); | |
574 | } | |
575 | ||
576 | static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes) | |
577 | { | |
578 | return le32_to_cpu(txdes->txdes3); | |
579 | } | |
580 | ||
581 | /* | |
582 | * txdes2 is not used by hardware. We use it to keep track of socket buffer. | |
583 | * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). | |
584 | */ | |
585 | static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes, | |
586 | struct sk_buff *skb) | |
587 | { | |
588 | txdes->txdes2 = (unsigned int)skb; | |
589 | } | |
590 | ||
591 | static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes) | |
592 | { | |
593 | return (struct sk_buff *)txdes->txdes2; | |
594 | } | |
595 | ||
596 | /****************************************************************************** | |
597 | * internal functions (transmit) | |
598 | *****************************************************************************/ | |
599 | static int ftgmac100_next_tx_pointer(int pointer) | |
600 | { | |
601 | return (pointer + 1) & (TX_QUEUE_ENTRIES - 1); | |
602 | } | |
603 | ||
604 | static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv) | |
605 | { | |
606 | priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer); | |
607 | } | |
608 | ||
609 | static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv) | |
610 | { | |
611 | priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer); | |
612 | } | |
613 | ||
614 | static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv) | |
615 | { | |
616 | return &priv->descs->txdes[priv->tx_pointer]; | |
617 | } | |
618 | ||
619 | static struct ftgmac100_txdes * | |
620 | ftgmac100_current_clean_txdes(struct ftgmac100 *priv) | |
621 | { | |
622 | return &priv->descs->txdes[priv->tx_clean_pointer]; | |
623 | } | |
624 | ||
625 | static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) | |
626 | { | |
627 | struct net_device *netdev = priv->netdev; | |
628 | struct ftgmac100_txdes *txdes; | |
629 | struct sk_buff *skb; | |
630 | dma_addr_t map; | |
631 | ||
632 | if (priv->tx_pending == 0) | |
633 | return false; | |
634 | ||
635 | txdes = ftgmac100_current_clean_txdes(priv); | |
636 | ||
637 | if (ftgmac100_txdes_owned_by_dma(txdes)) | |
638 | return false; | |
639 | ||
640 | skb = ftgmac100_txdes_get_skb(txdes); | |
641 | map = ftgmac100_txdes_get_dma_addr(txdes); | |
642 | ||
643 | netdev->stats.tx_packets++; | |
644 | netdev->stats.tx_bytes += skb->len; | |
645 | ||
646 | dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); | |
647 | ||
648 | dev_kfree_skb(skb); | |
649 | ||
650 | ftgmac100_txdes_reset(txdes); | |
651 | ||
652 | ftgmac100_tx_clean_pointer_advance(priv); | |
653 | ||
654 | spin_lock(&priv->tx_lock); | |
655 | priv->tx_pending--; | |
656 | spin_unlock(&priv->tx_lock); | |
657 | netif_wake_queue(netdev); | |
658 | ||
659 | return true; | |
660 | } | |
661 | ||
662 | static void ftgmac100_tx_complete(struct ftgmac100 *priv) | |
663 | { | |
664 | while (ftgmac100_tx_complete_packet(priv)) | |
665 | ; | |
666 | } | |
667 | ||
668 | static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb, | |
669 | dma_addr_t map) | |
670 | { | |
671 | struct net_device *netdev = priv->netdev; | |
672 | struct ftgmac100_txdes *txdes; | |
673 | unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len; | |
674 | ||
675 | txdes = ftgmac100_current_txdes(priv); | |
676 | ftgmac100_tx_pointer_advance(priv); | |
677 | ||
678 | /* setup TX descriptor */ | |
679 | ftgmac100_txdes_set_skb(txdes, skb); | |
680 | ftgmac100_txdes_set_dma_addr(txdes, map); | |
681 | ftgmac100_txdes_set_buffer_size(txdes, len); | |
682 | ||
683 | ftgmac100_txdes_set_first_segment(txdes); | |
684 | ftgmac100_txdes_set_last_segment(txdes); | |
685 | ftgmac100_txdes_set_txint(txdes); | |
686 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
687 | __be16 protocol = skb->protocol; | |
688 | ||
689 | if (protocol == cpu_to_be16(ETH_P_IP)) { | |
690 | u8 ip_proto = ip_hdr(skb)->protocol; | |
691 | ||
692 | ftgmac100_txdes_set_ipcs(txdes); | |
693 | if (ip_proto == IPPROTO_TCP) | |
694 | ftgmac100_txdes_set_tcpcs(txdes); | |
695 | else if (ip_proto == IPPROTO_UDP) | |
696 | ftgmac100_txdes_set_udpcs(txdes); | |
697 | } | |
698 | } | |
699 | ||
700 | spin_lock(&priv->tx_lock); | |
701 | priv->tx_pending++; | |
702 | if (priv->tx_pending == TX_QUEUE_ENTRIES) | |
703 | netif_stop_queue(netdev); | |
704 | ||
705 | /* start transmit */ | |
706 | ftgmac100_txdes_set_dma_own(txdes); | |
707 | spin_unlock(&priv->tx_lock); | |
708 | ||
709 | ftgmac100_txdma_normal_prio_start_polling(priv); | |
710 | ||
711 | return NETDEV_TX_OK; | |
712 | } | |
713 | ||
714 | /****************************************************************************** | |
715 | * internal functions (buffer) | |
716 | *****************************************************************************/ | |
717 | static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, | |
718 | struct ftgmac100_rxdes *rxdes, gfp_t gfp) | |
719 | { | |
720 | struct net_device *netdev = priv->netdev; | |
721 | struct page *page; | |
722 | dma_addr_t map; | |
723 | ||
724 | page = alloc_page(gfp); | |
725 | if (!page) { | |
726 | if (net_ratelimit()) | |
727 | netdev_err(netdev, "failed to allocate rx page\n"); | |
728 | return -ENOMEM; | |
729 | } | |
730 | ||
731 | map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE); | |
732 | if (unlikely(dma_mapping_error(priv->dev, map))) { | |
733 | if (net_ratelimit()) | |
734 | netdev_err(netdev, "failed to map rx page\n"); | |
735 | __free_page(page); | |
736 | return -ENOMEM; | |
737 | } | |
738 | ||
739 | ftgmac100_rxdes_set_page(rxdes, page); | |
740 | ftgmac100_rxdes_set_dma_addr(rxdes, map); | |
741 | ftgmac100_rxdes_set_dma_own(rxdes); | |
742 | return 0; | |
743 | } | |
744 | ||
745 | static void ftgmac100_free_buffers(struct ftgmac100 *priv) | |
746 | { | |
747 | int i; | |
748 | ||
749 | for (i = 0; i < RX_QUEUE_ENTRIES; i++) { | |
750 | struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; | |
751 | struct page *page = ftgmac100_rxdes_get_page(rxdes); | |
752 | dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); | |
753 | ||
754 | if (!page) | |
755 | continue; | |
756 | ||
757 | dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); | |
758 | __free_page(page); | |
759 | } | |
760 | ||
761 | for (i = 0; i < TX_QUEUE_ENTRIES; i++) { | |
762 | struct ftgmac100_txdes *txdes = &priv->descs->txdes[i]; | |
763 | struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes); | |
764 | dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes); | |
765 | ||
766 | if (!skb) | |
767 | continue; | |
768 | ||
769 | dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); | |
770 | dev_kfree_skb(skb); | |
771 | } | |
772 | ||
773 | dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs), | |
774 | priv->descs, priv->descs_dma_addr); | |
775 | } | |
776 | ||
777 | static int ftgmac100_alloc_buffers(struct ftgmac100 *priv) | |
778 | { | |
779 | int i; | |
780 | ||
781 | priv->descs = dma_alloc_coherent(priv->dev, | |
782 | sizeof(struct ftgmac100_descs), | |
783 | &priv->descs_dma_addr, GFP_KERNEL); | |
784 | if (!priv->descs) | |
785 | return -ENOMEM; | |
786 | ||
787 | memset(priv->descs, 0, sizeof(struct ftgmac100_descs)); | |
788 | ||
789 | /* initialize RX ring */ | |
790 | ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); | |
791 | ||
792 | for (i = 0; i < RX_QUEUE_ENTRIES; i++) { | |
793 | struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; | |
794 | ||
795 | if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL)) | |
796 | goto err; | |
797 | } | |
798 | ||
799 | /* initialize TX ring */ | |
800 | ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]); | |
801 | return 0; | |
802 | ||
803 | err: | |
804 | ftgmac100_free_buffers(priv); | |
805 | return -ENOMEM; | |
806 | } | |
807 | ||
808 | /****************************************************************************** | |
809 | * internal functions (mdio) | |
810 | *****************************************************************************/ | |
811 | static void ftgmac100_adjust_link(struct net_device *netdev) | |
812 | { | |
813 | struct ftgmac100 *priv = netdev_priv(netdev); | |
814 | struct phy_device *phydev = priv->phydev; | |
815 | int ier; | |
816 | ||
817 | if (phydev->speed == priv->old_speed) | |
818 | return; | |
819 | ||
820 | priv->old_speed = phydev->speed; | |
821 | ||
822 | ier = ioread32(priv->base + FTGMAC100_OFFSET_IER); | |
823 | ||
824 | /* disable all interrupts */ | |
825 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
826 | ||
827 | netif_stop_queue(netdev); | |
828 | ftgmac100_stop_hw(priv); | |
829 | ||
830 | netif_start_queue(netdev); | |
831 | ftgmac100_init_hw(priv); | |
832 | ftgmac100_start_hw(priv, phydev->speed); | |
833 | ||
834 | /* re-enable interrupts */ | |
835 | iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER); | |
836 | } | |
837 | ||
838 | static int ftgmac100_mii_probe(struct ftgmac100 *priv) | |
839 | { | |
840 | struct net_device *netdev = priv->netdev; | |
841 | struct phy_device *phydev = NULL; | |
842 | int i; | |
843 | ||
844 | /* search for connect PHY device */ | |
845 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
846 | struct phy_device *tmp = priv->mii_bus->phy_map[i]; | |
847 | ||
848 | if (tmp) { | |
849 | phydev = tmp; | |
850 | break; | |
851 | } | |
852 | } | |
853 | ||
854 | /* now we are supposed to have a proper phydev, to attach to... */ | |
855 | if (!phydev) { | |
856 | netdev_info(netdev, "%s: no PHY found\n", netdev->name); | |
857 | return -ENODEV; | |
858 | } | |
859 | ||
860 | phydev = phy_connect(netdev, dev_name(&phydev->dev), | |
f9a8f83b | 861 | &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII); |
69785b79 PYC |
862 | |
863 | if (IS_ERR(phydev)) { | |
864 | netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); | |
865 | return PTR_ERR(phydev); | |
866 | } | |
867 | ||
868 | priv->phydev = phydev; | |
869 | return 0; | |
870 | } | |
871 | ||
872 | /****************************************************************************** | |
873 | * struct mii_bus functions | |
874 | *****************************************************************************/ | |
875 | static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) | |
876 | { | |
877 | struct net_device *netdev = bus->priv; | |
878 | struct ftgmac100 *priv = netdev_priv(netdev); | |
879 | unsigned int phycr; | |
880 | int i; | |
881 | ||
882 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
883 | ||
884 | /* preserve MDC cycle threshold */ | |
885 | phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; | |
886 | ||
887 | phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | | |
888 | FTGMAC100_PHYCR_REGAD(regnum) | | |
889 | FTGMAC100_PHYCR_MIIRD; | |
890 | ||
891 | iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); | |
892 | ||
893 | for (i = 0; i < 10; i++) { | |
894 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
895 | ||
896 | if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { | |
897 | int data; | |
898 | ||
899 | data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); | |
900 | return FTGMAC100_PHYDATA_MIIRDATA(data); | |
901 | } | |
902 | ||
903 | udelay(100); | |
904 | } | |
905 | ||
906 | netdev_err(netdev, "mdio read timed out\n"); | |
907 | return -EIO; | |
908 | } | |
909 | ||
910 | static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, | |
911 | int regnum, u16 value) | |
912 | { | |
913 | struct net_device *netdev = bus->priv; | |
914 | struct ftgmac100 *priv = netdev_priv(netdev); | |
915 | unsigned int phycr; | |
916 | int data; | |
917 | int i; | |
918 | ||
919 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
920 | ||
921 | /* preserve MDC cycle threshold */ | |
922 | phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; | |
923 | ||
924 | phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | | |
925 | FTGMAC100_PHYCR_REGAD(regnum) | | |
926 | FTGMAC100_PHYCR_MIIWR; | |
927 | ||
928 | data = FTGMAC100_PHYDATA_MIIWDATA(value); | |
929 | ||
930 | iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); | |
931 | iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); | |
932 | ||
933 | for (i = 0; i < 10; i++) { | |
934 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
935 | ||
936 | if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) | |
937 | return 0; | |
938 | ||
939 | udelay(100); | |
940 | } | |
941 | ||
942 | netdev_err(netdev, "mdio write timed out\n"); | |
943 | return -EIO; | |
944 | } | |
945 | ||
946 | static int ftgmac100_mdiobus_reset(struct mii_bus *bus) | |
947 | { | |
948 | return 0; | |
949 | } | |
950 | ||
951 | /****************************************************************************** | |
952 | * struct ethtool_ops functions | |
953 | *****************************************************************************/ | |
954 | static void ftgmac100_get_drvinfo(struct net_device *netdev, | |
955 | struct ethtool_drvinfo *info) | |
956 | { | |
7826d43f JP |
957 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
958 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
959 | strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); | |
69785b79 PYC |
960 | } |
961 | ||
962 | static int ftgmac100_get_settings(struct net_device *netdev, | |
963 | struct ethtool_cmd *cmd) | |
964 | { | |
965 | struct ftgmac100 *priv = netdev_priv(netdev); | |
966 | ||
967 | return phy_ethtool_gset(priv->phydev, cmd); | |
968 | } | |
969 | ||
970 | static int ftgmac100_set_settings(struct net_device *netdev, | |
971 | struct ethtool_cmd *cmd) | |
972 | { | |
973 | struct ftgmac100 *priv = netdev_priv(netdev); | |
974 | ||
975 | return phy_ethtool_sset(priv->phydev, cmd); | |
976 | } | |
977 | ||
978 | static const struct ethtool_ops ftgmac100_ethtool_ops = { | |
979 | .set_settings = ftgmac100_set_settings, | |
980 | .get_settings = ftgmac100_get_settings, | |
981 | .get_drvinfo = ftgmac100_get_drvinfo, | |
982 | .get_link = ethtool_op_get_link, | |
983 | }; | |
984 | ||
985 | /****************************************************************************** | |
986 | * interrupt handler | |
987 | *****************************************************************************/ | |
988 | static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) | |
989 | { | |
990 | struct net_device *netdev = dev_id; | |
991 | struct ftgmac100 *priv = netdev_priv(netdev); | |
992 | ||
993 | if (likely(netif_running(netdev))) { | |
994 | /* Disable interrupts for polling */ | |
995 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
996 | napi_schedule(&priv->napi); | |
997 | } | |
998 | ||
999 | return IRQ_HANDLED; | |
1000 | } | |
1001 | ||
1002 | /****************************************************************************** | |
1003 | * struct napi_struct functions | |
1004 | *****************************************************************************/ | |
1005 | static int ftgmac100_poll(struct napi_struct *napi, int budget) | |
1006 | { | |
1007 | struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); | |
1008 | struct net_device *netdev = priv->netdev; | |
1009 | unsigned int status; | |
1010 | bool completed = true; | |
1011 | int rx = 0; | |
1012 | ||
1013 | status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); | |
1014 | iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); | |
1015 | ||
1016 | if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) { | |
1017 | /* | |
1018 | * FTGMAC100_INT_RPKT_BUF: | |
1019 | * RX DMA has received packets into RX buffer successfully | |
1020 | * | |
1021 | * FTGMAC100_INT_NO_RXBUF: | |
1022 | * RX buffer unavailable | |
1023 | */ | |
1024 | bool retry; | |
1025 | ||
1026 | do { | |
1027 | retry = ftgmac100_rx_packet(priv, &rx); | |
1028 | } while (retry && rx < budget); | |
1029 | ||
1030 | if (retry && rx == budget) | |
1031 | completed = false; | |
1032 | } | |
1033 | ||
1034 | if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) { | |
1035 | /* | |
1036 | * FTGMAC100_INT_XPKT_ETH: | |
1037 | * packet transmitted to ethernet successfully | |
1038 | * | |
1039 | * FTGMAC100_INT_XPKT_LOST: | |
1040 | * packet transmitted to ethernet lost due to late | |
1041 | * collision or excessive collision | |
1042 | */ | |
1043 | ftgmac100_tx_complete(priv); | |
1044 | } | |
1045 | ||
1046 | if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST | | |
1047 | FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) { | |
1048 | if (net_ratelimit()) | |
1049 | netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status, | |
1050 | status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "", | |
1051 | status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "", | |
1052 | status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "", | |
1053 | status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : ""); | |
1054 | ||
1055 | if (status & FTGMAC100_INT_NO_RXBUF) { | |
1056 | /* RX buffer unavailable */ | |
1057 | netdev->stats.rx_over_errors++; | |
1058 | } | |
1059 | ||
1060 | if (status & FTGMAC100_INT_RPKT_LOST) { | |
1061 | /* received packet lost due to RX FIFO full */ | |
1062 | netdev->stats.rx_fifo_errors++; | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | if (completed) { | |
1067 | napi_complete(napi); | |
1068 | ||
1069 | /* enable all interrupts */ | |
1070 | iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); | |
1071 | } | |
1072 | ||
1073 | return rx; | |
1074 | } | |
1075 | ||
1076 | /****************************************************************************** | |
1077 | * struct net_device_ops functions | |
1078 | *****************************************************************************/ | |
1079 | static int ftgmac100_open(struct net_device *netdev) | |
1080 | { | |
1081 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1082 | int err; | |
1083 | ||
1084 | err = ftgmac100_alloc_buffers(priv); | |
1085 | if (err) { | |
1086 | netdev_err(netdev, "failed to allocate buffers\n"); | |
1087 | goto err_alloc; | |
1088 | } | |
1089 | ||
1090 | err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev); | |
1091 | if (err) { | |
1092 | netdev_err(netdev, "failed to request irq %d\n", priv->irq); | |
1093 | goto err_irq; | |
1094 | } | |
1095 | ||
1096 | priv->rx_pointer = 0; | |
1097 | priv->tx_clean_pointer = 0; | |
1098 | priv->tx_pointer = 0; | |
1099 | priv->tx_pending = 0; | |
1100 | ||
1101 | err = ftgmac100_reset_hw(priv); | |
1102 | if (err) | |
1103 | goto err_hw; | |
1104 | ||
1105 | ftgmac100_init_hw(priv); | |
1106 | ftgmac100_start_hw(priv, 10); | |
1107 | ||
1108 | phy_start(priv->phydev); | |
1109 | ||
1110 | napi_enable(&priv->napi); | |
1111 | netif_start_queue(netdev); | |
1112 | ||
1113 | /* enable all interrupts */ | |
1114 | iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); | |
1115 | return 0; | |
1116 | ||
1117 | err_hw: | |
1118 | free_irq(priv->irq, netdev); | |
1119 | err_irq: | |
1120 | ftgmac100_free_buffers(priv); | |
1121 | err_alloc: | |
1122 | return err; | |
1123 | } | |
1124 | ||
1125 | static int ftgmac100_stop(struct net_device *netdev) | |
1126 | { | |
1127 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1128 | ||
1129 | /* disable all interrupts */ | |
1130 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
1131 | ||
1132 | netif_stop_queue(netdev); | |
1133 | napi_disable(&priv->napi); | |
1134 | phy_stop(priv->phydev); | |
1135 | ||
1136 | ftgmac100_stop_hw(priv); | |
1137 | free_irq(priv->irq, netdev); | |
1138 | ftgmac100_free_buffers(priv); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static int ftgmac100_hard_start_xmit(struct sk_buff *skb, | |
1144 | struct net_device *netdev) | |
1145 | { | |
1146 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1147 | dma_addr_t map; | |
1148 | ||
1149 | if (unlikely(skb->len > MAX_PKT_SIZE)) { | |
1150 | if (net_ratelimit()) | |
1151 | netdev_dbg(netdev, "tx packet too big\n"); | |
1152 | ||
1153 | netdev->stats.tx_dropped++; | |
1154 | dev_kfree_skb(skb); | |
1155 | return NETDEV_TX_OK; | |
1156 | } | |
1157 | ||
1158 | map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); | |
1159 | if (unlikely(dma_mapping_error(priv->dev, map))) { | |
1160 | /* drop packet */ | |
1161 | if (net_ratelimit()) | |
1162 | netdev_err(netdev, "map socket buffer failed\n"); | |
1163 | ||
1164 | netdev->stats.tx_dropped++; | |
1165 | dev_kfree_skb(skb); | |
1166 | return NETDEV_TX_OK; | |
1167 | } | |
1168 | ||
1169 | return ftgmac100_xmit(priv, skb, map); | |
1170 | } | |
1171 | ||
1172 | /* optional */ | |
1173 | static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
1174 | { | |
1175 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1176 | ||
1177 | return phy_mii_ioctl(priv->phydev, ifr, cmd); | |
1178 | } | |
1179 | ||
1180 | static const struct net_device_ops ftgmac100_netdev_ops = { | |
1181 | .ndo_open = ftgmac100_open, | |
1182 | .ndo_stop = ftgmac100_stop, | |
1183 | .ndo_start_xmit = ftgmac100_hard_start_xmit, | |
1184 | .ndo_set_mac_address = eth_mac_addr, | |
1185 | .ndo_validate_addr = eth_validate_addr, | |
1186 | .ndo_do_ioctl = ftgmac100_do_ioctl, | |
1187 | }; | |
1188 | ||
1189 | /****************************************************************************** | |
1190 | * struct platform_driver functions | |
1191 | *****************************************************************************/ | |
1192 | static int ftgmac100_probe(struct platform_device *pdev) | |
1193 | { | |
1194 | struct resource *res; | |
1195 | int irq; | |
1196 | struct net_device *netdev; | |
1197 | struct ftgmac100 *priv; | |
1198 | int err; | |
1199 | int i; | |
1200 | ||
1201 | if (!pdev) | |
1202 | return -ENODEV; | |
1203 | ||
1204 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1205 | if (!res) | |
1206 | return -ENXIO; | |
1207 | ||
1208 | irq = platform_get_irq(pdev, 0); | |
1209 | if (irq < 0) | |
1210 | return irq; | |
1211 | ||
1212 | /* setup net_device */ | |
1213 | netdev = alloc_etherdev(sizeof(*priv)); | |
1214 | if (!netdev) { | |
1215 | err = -ENOMEM; | |
1216 | goto err_alloc_etherdev; | |
1217 | } | |
1218 | ||
1219 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1220 | ||
1221 | SET_ETHTOOL_OPS(netdev, &ftgmac100_ethtool_ops); | |
1222 | netdev->netdev_ops = &ftgmac100_netdev_ops; | |
1223 | netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO; | |
1224 | ||
1225 | platform_set_drvdata(pdev, netdev); | |
1226 | ||
1227 | /* setup private data */ | |
1228 | priv = netdev_priv(netdev); | |
1229 | priv->netdev = netdev; | |
1230 | priv->dev = &pdev->dev; | |
1231 | ||
1232 | spin_lock_init(&priv->tx_lock); | |
1233 | ||
1234 | /* initialize NAPI */ | |
1235 | netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); | |
1236 | ||
1237 | /* map io memory */ | |
1238 | priv->res = request_mem_region(res->start, resource_size(res), | |
1239 | dev_name(&pdev->dev)); | |
1240 | if (!priv->res) { | |
1241 | dev_err(&pdev->dev, "Could not reserve memory region\n"); | |
1242 | err = -ENOMEM; | |
1243 | goto err_req_mem; | |
1244 | } | |
1245 | ||
1246 | priv->base = ioremap(res->start, resource_size(res)); | |
1247 | if (!priv->base) { | |
1248 | dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); | |
1249 | err = -EIO; | |
1250 | goto err_ioremap; | |
1251 | } | |
1252 | ||
1253 | priv->irq = irq; | |
1254 | ||
1255 | /* initialize mdio bus */ | |
1256 | priv->mii_bus = mdiobus_alloc(); | |
1257 | if (!priv->mii_bus) { | |
1258 | err = -EIO; | |
1259 | goto err_alloc_mdiobus; | |
1260 | } | |
1261 | ||
1262 | priv->mii_bus->name = "ftgmac100_mdio"; | |
1263 | snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii"); | |
1264 | ||
1265 | priv->mii_bus->priv = netdev; | |
1266 | priv->mii_bus->read = ftgmac100_mdiobus_read; | |
1267 | priv->mii_bus->write = ftgmac100_mdiobus_write; | |
1268 | priv->mii_bus->reset = ftgmac100_mdiobus_reset; | |
1269 | priv->mii_bus->irq = priv->phy_irq; | |
1270 | ||
1271 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
1272 | priv->mii_bus->irq[i] = PHY_POLL; | |
1273 | ||
1274 | err = mdiobus_register(priv->mii_bus); | |
1275 | if (err) { | |
1276 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1277 | goto err_register_mdiobus; | |
1278 | } | |
1279 | ||
1280 | err = ftgmac100_mii_probe(priv); | |
1281 | if (err) { | |
1282 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1283 | goto err_mii_probe; | |
1284 | } | |
1285 | ||
1286 | /* register network device */ | |
1287 | err = register_netdev(netdev); | |
1288 | if (err) { | |
1289 | dev_err(&pdev->dev, "Failed to register netdev\n"); | |
1290 | goto err_register_netdev; | |
1291 | } | |
1292 | ||
1293 | netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base); | |
1294 | ||
1295 | if (!is_valid_ether_addr(netdev->dev_addr)) { | |
f2cedb63 | 1296 | eth_hw_addr_random(netdev); |
69785b79 PYC |
1297 | netdev_info(netdev, "generated random MAC address %pM\n", |
1298 | netdev->dev_addr); | |
1299 | } | |
1300 | ||
1301 | return 0; | |
1302 | ||
1303 | err_register_netdev: | |
1304 | phy_disconnect(priv->phydev); | |
1305 | err_mii_probe: | |
1306 | mdiobus_unregister(priv->mii_bus); | |
1307 | err_register_mdiobus: | |
1308 | mdiobus_free(priv->mii_bus); | |
1309 | err_alloc_mdiobus: | |
1310 | iounmap(priv->base); | |
1311 | err_ioremap: | |
1312 | release_resource(priv->res); | |
1313 | err_req_mem: | |
1314 | netif_napi_del(&priv->napi); | |
1315 | platform_set_drvdata(pdev, NULL); | |
1316 | free_netdev(netdev); | |
1317 | err_alloc_etherdev: | |
1318 | return err; | |
1319 | } | |
1320 | ||
1321 | static int __exit ftgmac100_remove(struct platform_device *pdev) | |
1322 | { | |
1323 | struct net_device *netdev; | |
1324 | struct ftgmac100 *priv; | |
1325 | ||
1326 | netdev = platform_get_drvdata(pdev); | |
1327 | priv = netdev_priv(netdev); | |
1328 | ||
1329 | unregister_netdev(netdev); | |
1330 | ||
1331 | phy_disconnect(priv->phydev); | |
1332 | mdiobus_unregister(priv->mii_bus); | |
1333 | mdiobus_free(priv->mii_bus); | |
1334 | ||
1335 | iounmap(priv->base); | |
1336 | release_resource(priv->res); | |
1337 | ||
1338 | netif_napi_del(&priv->napi); | |
1339 | platform_set_drvdata(pdev, NULL); | |
1340 | free_netdev(netdev); | |
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | static struct platform_driver ftgmac100_driver = { | |
1345 | .probe = ftgmac100_probe, | |
1346 | .remove = __exit_p(ftgmac100_remove), | |
1347 | .driver = { | |
1348 | .name = DRV_NAME, | |
1349 | .owner = THIS_MODULE, | |
1350 | }, | |
1351 | }; | |
1352 | ||
1353 | /****************************************************************************** | |
1354 | * initialization / finalization | |
1355 | *****************************************************************************/ | |
1356 | static int __init ftgmac100_init(void) | |
1357 | { | |
1358 | pr_info("Loading version " DRV_VERSION " ...\n"); | |
1359 | return platform_driver_register(&ftgmac100_driver); | |
1360 | } | |
1361 | ||
1362 | static void __exit ftgmac100_exit(void) | |
1363 | { | |
1364 | platform_driver_unregister(&ftgmac100_driver); | |
1365 | } | |
1366 | ||
1367 | module_init(ftgmac100_init); | |
1368 | module_exit(ftgmac100_exit); | |
1369 | ||
1370 | MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); | |
1371 | MODULE_DESCRIPTION("FTGMAC100 driver"); | |
1372 | MODULE_LICENSE("GPL"); |