projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
be2net: Don't log "Out of MCCQ wrbs" error
[linux-2.6-block.git] / drivers / net / ethernet / emulex / benet / be_cmds.h
CommitLineData
6b7c5b94 1/*
c7bb15a6 2 * Copyright (C) 2005 - 2013 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
2b3f291b
SP		 54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
49643848 60 MCC_STATUS_NOT_SUPPORTED = 66
6b7c5b94
SP		 61};
62
63#define CQE_STATUS_COMPL_MASK 0xFFFF
64#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
65#define CQE_STATUS_EXTD_MASK 0xFFFF
f5209b44 66#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
6b7c5b94 67
efd2e40a 68struct be_mcc_compl {
6b7c5b94
SP		 69 u32 status; /* dword 0 */
70 u32 tag0; /* dword 1 */
71 u32 tag1; /* dword 2 */
72 u32 flags; /* dword 3 */
73};
74
a8f447bd
SP		 75/* When the async bit of mcc_compl is set, the last 4 bytes of
76 * mcc_compl is interpreted as follows:
77 */
78#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
79#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
cc4ce020
SK		 80#define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
81#define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
a8f447bd 82#define ASYNC_EVENT_CODE_LINK_STATE 0x1
cc4ce020
SK		 83#define ASYNC_EVENT_CODE_GRP_5 0x5
84#define ASYNC_EVENT_QOS_SPEED 0x1
85#define ASYNC_EVENT_COS_PRIORITY 0x2
3968fa1e 86#define ASYNC_EVENT_PVID_STATE 0x3
a8f447bd
SP		 87struct be_async_event_trailer {
88 u32 code;
89};
90
91enum {
ea172a01
SP		 92 LINK_DOWN = 0x0,
93 LINK_UP = 0x1
a8f447bd 94};
ea172a01 95#define LINK_STATUS_MASK 0x1
2e177a5c 96#define LOGICAL_LINK_STATUS_MASK 0x2
a8f447bd
SP		 97
98/* When the event code of an async trailer is link-state, the mcc_compl
99 * must be interpreted as follows
100 */
101struct be_async_event_link_state {
102 u8 physical_port;
103 u8 port_link_status;
104 u8 port_duplex;
105 u8 port_speed;
106 u8 port_fault;
107 u8 rsvd0[7];
108 struct be_async_event_trailer trailer;
109} __packed;
110
cc4ce020
SK		 111/* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
112 * the mcc_compl must be interpreted as follows
113 */
114struct be_async_event_grp5_qos_link_speed {
115 u8 physical_port;
116 u8 rsvd[5];
117 u16 qos_link_speed;
118 u32 event_tag;
119 struct be_async_event_trailer trailer;
120} __packed;
121
122/* When the event code of an async trailer is GRP5 and event type is
123 * CoS-Priority, the mcc_compl must be interpreted as follows
124 */
125struct be_async_event_grp5_cos_priority {
126 u8 physical_port;
127 u8 available_priority_bmap;
128 u8 reco_default_priority;
129 u8 valid;
130 u8 rsvd0;
131 u8 event_tag;
132 struct be_async_event_trailer trailer;
133} __packed;
134
3968fa1e
AK		 135/* When the event code of an async trailer is GRP5 and event type is
136 * PVID state, the mcc_compl must be interpreted as follows
137 */
138struct be_async_event_grp5_pvid_state {
139 u8 enabled;
140 u8 rsvd0;
141 u16 tag;
142 u32 event_tag;
143 u32 rsvd1;
144 struct be_async_event_trailer trailer;
145} __packed;
146
6b7c5b94
SP		 147struct be_mcc_mailbox {
148 struct be_mcc_wrb wrb;
efd2e40a 149 struct be_mcc_compl compl;
6b7c5b94
SP		 150};
151
152#define CMD_SUBSYSTEM_COMMON 0x1
153#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 154#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 155
156#define OPCODE_COMMON_NTWK_MAC_QUERY 1
157#define OPCODE_COMMON_NTWK_MAC_SET 2
158#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
159#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
160#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 161#define OPCODE_COMMON_READ_FLASHROM 6
84517482 162#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 163#define OPCODE_COMMON_CQ_CREATE 12
164#define OPCODE_COMMON_EQ_CREATE 13
cc4ce020 165#define OPCODE_COMMON_MCC_CREATE 21
e1d18735 166#define OPCODE_COMMON_SET_QOS 28
cc4ce020 167#define OPCODE_COMMON_MCC_CREATE_EXT 90
368c0ca2 168#define OPCODE_COMMON_SEEPROM_READ 30
9e1453c5 169#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
6b7c5b94
SP		 170#define OPCODE_COMMON_NTWK_RX_FILTER 34
171#define OPCODE_COMMON_GET_FW_VERSION 35
172#define OPCODE_COMMON_SET_FLOW_CONTROL 36
173#define OPCODE_COMMON_GET_FLOW_CONTROL 37
174#define OPCODE_COMMON_SET_FRAME_SIZE 39
175#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
176#define OPCODE_COMMON_FIRMWARE_CONFIG 42
177#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
178#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 179#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 180#define OPCODE_COMMON_CQ_DESTROY 54
181#define OPCODE_COMMON_EQ_DESTROY 55
182#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
183#define OPCODE_COMMON_NTWK_PMAC_ADD 59
184#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 185#define OPCODE_COMMON_FUNCTION_RESET 61
311fddc7 186#define OPCODE_COMMON_MANAGE_FAT 68
fad9ab2c
SB		 187#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
188#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 189#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
b4e32a71 190#define OPCODE_COMMON_GET_PORT_NAME 77
68c45a2d 191#define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
ee3cb629 192#define OPCODE_COMMON_GET_PHY_DETAILS 102
2e588f84 193#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
609ff3bb 194#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
941a77d5
SK		 195#define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
196#define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
590c391d
PR		 197#define OPCODE_COMMON_GET_MAC_LIST 147
198#define OPCODE_COMMON_SET_MAC_LIST 148
f1f3ee1b 199#define OPCODE_COMMON_GET_HSW_CONFIG 152
abb93951
PR		 200#define OPCODE_COMMON_GET_FUNC_CONFIG 160
201#define OPCODE_COMMON_GET_PROFILE_CONFIG 164
d5c18473 202#define OPCODE_COMMON_SET_PROFILE_CONFIG 165
f1f3ee1b 203#define OPCODE_COMMON_SET_HSW_CONFIG 153
f25b119c 204#define OPCODE_COMMON_GET_FN_PRIVILEGES 170
de49bd5a 205#define OPCODE_COMMON_READ_OBJECT 171
485bf569 206#define OPCODE_COMMON_WRITE_OBJECT 172
4c876616 207#define OPCODE_COMMON_GET_IFACE_LIST 194
dcf7ebba 208#define OPCODE_COMMON_ENABLE_DISABLE_VF 196
6b7c5b94 209
3abcdeda 210#define OPCODE_ETH_RSS_CONFIG 1
6b7c5b94
SP		 211#define OPCODE_ETH_ACPI_CONFIG 2
212#define OPCODE_ETH_PROMISCUOUS 3
213#define OPCODE_ETH_GET_STATISTICS 4
214#define OPCODE_ETH_TX_CREATE 7
215#define OPCODE_ETH_RX_CREATE 8
216#define OPCODE_ETH_TX_DESTROY 9
217#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 218#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
005d5696 219#define OPCODE_ETH_GET_PPORT_STATS 18
6b7c5b94 220
ff33a6e2
S		 221#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
222#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
fced9999 223#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
ff33a6e2 224
6b7c5b94
SP		 225struct be_cmd_req_hdr {
226 u8 opcode; /* dword 0 */
227 u8 subsystem; /* dword 0 */
228 u8 port_number; /* dword 0 */
229 u8 domain; /* dword 0 */
230 u32 timeout; /* dword 1 */
231 u32 request_length; /* dword 2 */
7b139c83
AK		 232 u8 version; /* dword 3 */
233 u8 rsvd[3]; /* dword 3 */
6b7c5b94
SP		 234};
235
236#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
237#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
238struct be_cmd_resp_hdr {
652bf646
PR		 239 u8 opcode; /* dword 0 */
240 u8 subsystem; /* dword 0 */
241 u8 rsvd[2]; /* dword 0 */
242 u8 status; /* dword 1 */
243 u8 add_status; /* dword 1 */
244 u8 rsvd1[2]; /* dword 1 */
6b7c5b94
SP		 245 u32 response_length; /* dword 2 */
246 u32 actual_resp_len; /* dword 3 */
247};
248
249struct phys_addr {
250 u32 lo;
251 u32 hi;
252};
253
254/**************************
255 * BE Command definitions *
256 **************************/
257
258/* Pseudo amap definition in which each bit of the actual structure is defined
259 * as a byte: used to calculate offset/shift/mask of each field */
260struct amap_eq_context {
261 u8 cidx[13]; /* dword 0*/
262 u8 rsvd0[3]; /* dword 0*/
263 u8 epidx[13]; /* dword 0*/
264 u8 valid; /* dword 0*/
265 u8 rsvd1; /* dword 0*/
266 u8 size; /* dword 0*/
267 u8 pidx[13]; /* dword 1*/
268 u8 rsvd2[3]; /* dword 1*/
269 u8 pd[10]; /* dword 1*/
270 u8 count[3]; /* dword 1*/
271 u8 solevent; /* dword 1*/
272 u8 stalled; /* dword 1*/
273 u8 armed; /* dword 1*/
274 u8 rsvd3[4]; /* dword 2*/
275 u8 func[8]; /* dword 2*/
276 u8 rsvd4; /* dword 2*/
277 u8 delaymult[10]; /* dword 2*/
278 u8 rsvd5[2]; /* dword 2*/
279 u8 phase[2]; /* dword 2*/
280 u8 nodelay; /* dword 2*/
281 u8 rsvd6[4]; /* dword 2*/
282 u8 rsvd7[32]; /* dword 3*/
283} __packed;
284
285struct be_cmd_req_eq_create {
286 struct be_cmd_req_hdr hdr;
287 u16 num_pages; /* sword */
288 u16 rsvd0; /* sword */
289 u8 context[sizeof(struct amap_eq_context) / 8];
290 struct phys_addr pages[8];
291} __packed;
292
293struct be_cmd_resp_eq_create {
294 struct be_cmd_resp_hdr resp_hdr;
295 u16 eq_id; /* sword */
296 u16 rsvd0; /* sword */
297} __packed;
298
299/******************** Mac query ***************************/
300enum {
301 MAC_ADDRESS_TYPE_STORAGE = 0x0,
302 MAC_ADDRESS_TYPE_NETWORK = 0x1,
303 MAC_ADDRESS_TYPE_PD = 0x2,
304 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
305};
306
307struct mac_addr {
308 u16 size_of_struct;
309 u8 addr[ETH_ALEN];
310} __packed;
311
312struct be_cmd_req_mac_query {
313 struct be_cmd_req_hdr hdr;
314 u8 type;
315 u8 permanent;
316 u16 if_id;
590c391d 317 u32 pmac_id;
6b7c5b94
SP		 318} __packed;
319
320struct be_cmd_resp_mac_query {
321 struct be_cmd_resp_hdr hdr;
322 struct mac_addr mac;
323};
324
325/******************** PMac Add ***************************/
326struct be_cmd_req_pmac_add {
327 struct be_cmd_req_hdr hdr;
328 u32 if_id;
329 u8 mac_address[ETH_ALEN];
330 u8 rsvd0[2];
331} __packed;
332
333struct be_cmd_resp_pmac_add {
334 struct be_cmd_resp_hdr hdr;
335 u32 pmac_id;
336};
337
338/******************** PMac Del ***************************/
339struct be_cmd_req_pmac_del {
340 struct be_cmd_req_hdr hdr;
341 u32 if_id;
342 u32 pmac_id;
343};
344
345/******************** Create CQ ***************************/
346/* Pseudo amap definition in which each bit of the actual structure is defined
347 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 348struct amap_cq_context_be {
6b7c5b94
SP		 349 u8 cidx[11]; /* dword 0*/
350 u8 rsvd0; /* dword 0*/
351 u8 coalescwm[2]; /* dword 0*/
352 u8 nodelay; /* dword 0*/
353 u8 epidx[11]; /* dword 0*/
354 u8 rsvd1; /* dword 0*/
355 u8 count[2]; /* dword 0*/
356 u8 valid; /* dword 0*/
357 u8 solevent; /* dword 0*/
358 u8 eventable; /* dword 0*/
359 u8 pidx[11]; /* dword 1*/
360 u8 rsvd2; /* dword 1*/
361 u8 pd[10]; /* dword 1*/
362 u8 eqid[8]; /* dword 1*/
363 u8 stalled; /* dword 1*/
364 u8 armed; /* dword 1*/
365 u8 rsvd3[4]; /* dword 2*/
366 u8 func[8]; /* dword 2*/
367 u8 rsvd4[20]; /* dword 2*/
368 u8 rsvd5[32]; /* dword 3*/
369} __packed;
370
fe6d2a38
SP		 371struct amap_cq_context_lancer {
372 u8 rsvd0[12]; /* dword 0*/
373 u8 coalescwm[2]; /* dword 0*/
374 u8 nodelay; /* dword 0*/
375 u8 rsvd1[12]; /* dword 0*/
376 u8 count[2]; /* dword 0*/
377 u8 valid; /* dword 0*/
378 u8 rsvd2; /* dword 0*/
379 u8 eventable; /* dword 0*/
380 u8 eqid[16]; /* dword 1*/
381 u8 rsvd3[15]; /* dword 1*/
382 u8 armed; /* dword 1*/
383 u8 rsvd4[32]; /* dword 2*/
384 u8 rsvd5[32]; /* dword 3*/
385} __packed;
386
6b7c5b94
SP		 387struct be_cmd_req_cq_create {
388 struct be_cmd_req_hdr hdr;
389 u16 num_pages;
fe6d2a38
SP		 390 u8 page_size;
391 u8 rsvd0;
392 u8 context[sizeof(struct amap_cq_context_be) / 8];
6b7c5b94
SP		 393 struct phys_addr pages[8];
394} __packed;
395
fe6d2a38 396
6b7c5b94
SP		 397struct be_cmd_resp_cq_create {
398 struct be_cmd_resp_hdr hdr;
399 u16 cq_id;
400 u16 rsvd0;
401} __packed;
402
311fddc7
SK		 403struct be_cmd_req_get_fat {
404 struct be_cmd_req_hdr hdr;
405 u32 fat_operation;
406 u32 read_log_offset;
407 u32 read_log_length;
408 u32 data_buffer_size;
409 u32 data_buffer[1];
410} __packed;
411
412struct be_cmd_resp_get_fat {
413 struct be_cmd_resp_hdr hdr;
414 u32 log_size;
415 u32 read_log_length;
416 u32 rsvd[2];
417 u32 data_buffer[1];
418} __packed;
419
420
5fb379ee
SP		 421/******************** Create MCCQ ***************************/
422/* Pseudo amap definition in which each bit of the actual structure is defined
423 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 424struct amap_mcc_context_be {
5fb379ee
SP		 425 u8 con_index[14];
426 u8 rsvd0[2];
427 u8 ring_size[4];
428 u8 fetch_wrb;
429 u8 fetch_r2t;
430 u8 cq_id[10];
431 u8 prod_index[14];
432 u8 fid[8];
433 u8 pdid[9];
434 u8 valid;
435 u8 rsvd1[32];
436 u8 rsvd2[32];
437} __packed;
438
fe6d2a38
SP		 439struct amap_mcc_context_lancer {
440 u8 async_cq_id[16];
441 u8 ring_size[4];
442 u8 rsvd0[12];
443 u8 rsvd1[31];
444 u8 valid;
445 u8 async_cq_valid[1];
446 u8 rsvd2[31];
447 u8 rsvd3[32];
448} __packed;
449
5fb379ee 450struct be_cmd_req_mcc_create {
34b1ef04
SK		 451 struct be_cmd_req_hdr hdr;
452 u16 num_pages;
453 u16 cq_id;
454 u8 context[sizeof(struct amap_mcc_context_be) / 8];
455 struct phys_addr pages[8];
456} __packed;
457
458struct be_cmd_req_mcc_ext_create {
5fb379ee
SP		 459 struct be_cmd_req_hdr hdr;
460 u16 num_pages;
fe6d2a38 461 u16 cq_id;
cc4ce020 462 u32 async_event_bitmap[1];
fe6d2a38 463 u8 context[sizeof(struct amap_mcc_context_be) / 8];
5fb379ee
SP		 464 struct phys_addr pages[8];
465} __packed;
466
467struct be_cmd_resp_mcc_create {
468 struct be_cmd_resp_hdr hdr;
469 u16 id;
470 u16 rsvd0;
471} __packed;
472
6b7c5b94
SP		 473/******************** Create TxQ ***************************/
474#define BE_ETH_TX_RING_TYPE_STANDARD 2
475#define BE_ULP1_NUM 1
476
6b7c5b94
SP		 477struct be_cmd_req_eth_tx_create {
478 struct be_cmd_req_hdr hdr;
479 u8 num_pages;
480 u8 ulp_num;
94d73aaa
VV		 481 u16 type;
482 u16 if_id;
483 u8 queue_size;
484 u8 rsvd0;
485 u32 rsvd1;
486 u16 cq_id;
487 u16 rsvd2;
488 u32 rsvd3[13];
6b7c5b94
SP		 489 struct phys_addr pages[8];
490} __packed;
491
492struct be_cmd_resp_eth_tx_create {
493 struct be_cmd_resp_hdr hdr;
494 u16 cid;
94d73aaa
VV		 495 u16 rid;
496 u32 db_offset;
497 u32 rsvd0[4];
6b7c5b94
SP		 498} __packed;
499
500/******************** Create RxQ ***************************/
501struct be_cmd_req_eth_rx_create {
502 struct be_cmd_req_hdr hdr;
503 u16 cq_id;
504 u8 frag_size;
505 u8 num_pages;
506 struct phys_addr pages[2];
507 u32 interface_id;
508 u16 max_frame_size;
509 u16 rsvd0;
510 u32 rss_queue;
511} __packed;
512
513struct be_cmd_resp_eth_rx_create {
514 struct be_cmd_resp_hdr hdr;
515 u16 id;
3abcdeda 516 u8 rss_id;
6b7c5b94
SP		 517 u8 rsvd0;
518} __packed;
519
520/******************** Q Destroy ***************************/
521/* Type of Queue to be destroyed */
522enum {
523 QTYPE_EQ = 1,
524 QTYPE_CQ,
525 QTYPE_TXQ,
5fb379ee
SP		 526 QTYPE_RXQ,
527 QTYPE_MCCQ
6b7c5b94
SP		 528};
529
530struct be_cmd_req_q_destroy {
531 struct be_cmd_req_hdr hdr;
532 u16 id;
533 u16 bypass_flush; /* valid only for rx q destroy */
534} __packed;
535
536/************ I/f Create (it's actually I/f Config Create)**********/
537
538/* Capability flags for the i/f */
539enum be_if_flags {
540 BE_IF_FLAGS_RSS = 0x4,
541 BE_IF_FLAGS_PROMISCUOUS = 0x8,
542 BE_IF_FLAGS_BROADCAST = 0x10,
543 BE_IF_FLAGS_UNTAGGED = 0x20,
544 BE_IF_FLAGS_ULP = 0x40,
545 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
546 BE_IF_FLAGS_VLAN = 0x100,
547 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
548 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
f21b538c
PR		 549 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
550 BE_IF_FLAGS_MULTICAST = 0x1000
6b7c5b94
SP		 551};
552
553/* An RX interface is an object with one or more MAC addresses and
554 * filtering capabilities. */
555struct be_cmd_req_if_create {
556 struct be_cmd_req_hdr hdr;
af901ca1 557 u32 version; /* ignore currently */
6b7c5b94
SP		 558 u32 capability_flags;
559 u32 enable_flags;
560 u8 mac_addr[ETH_ALEN];
561 u8 rsvd0;
562 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
563 u32 vlan_tag; /* not used currently */
564} __packed;
565
566struct be_cmd_resp_if_create {
567 struct be_cmd_resp_hdr hdr;
568 u32 interface_id;
569 u32 pmac_id;
570};
571
572/****** I/f Destroy(it's actually I/f Config Destroy )**********/
573struct be_cmd_req_if_destroy {
574 struct be_cmd_req_hdr hdr;
575 u32 interface_id;
576};
577
578/*************** HW Stats Get **********************************/
89a88ab8 579struct be_port_rxf_stats_v0 {
6b7c5b94
SP		 580 u32 rx_bytes_lsd; /* dword 0*/
581 u32 rx_bytes_msd; /* dword 1*/
582 u32 rx_total_frames; /* dword 2*/
583 u32 rx_unicast_frames; /* dword 3*/
584 u32 rx_multicast_frames; /* dword 4*/
585 u32 rx_broadcast_frames; /* dword 5*/
586 u32 rx_crc_errors; /* dword 6*/
587 u32 rx_alignment_symbol_errors; /* dword 7*/
588 u32 rx_pause_frames; /* dword 8*/
589 u32 rx_control_frames; /* dword 9*/
590 u32 rx_in_range_errors; /* dword 10*/
591 u32 rx_out_range_errors; /* dword 11*/
592 u32 rx_frame_too_long; /* dword 12*/
d45b9d39
SP		 593 u32 rx_address_mismatch_drops; /* dword 13*/
594 u32 rx_vlan_mismatch_drops; /* dword 14*/
6b7c5b94
SP		 595 u32 rx_dropped_too_small; /* dword 15*/
596 u32 rx_dropped_too_short; /* dword 16*/
597 u32 rx_dropped_header_too_small; /* dword 17*/
598 u32 rx_dropped_tcp_length; /* dword 18*/
599 u32 rx_dropped_runt; /* dword 19*/
600 u32 rx_64_byte_packets; /* dword 20*/
601 u32 rx_65_127_byte_packets; /* dword 21*/
602 u32 rx_128_256_byte_packets; /* dword 22*/
603 u32 rx_256_511_byte_packets; /* dword 23*/
604 u32 rx_512_1023_byte_packets; /* dword 24*/
605 u32 rx_1024_1518_byte_packets; /* dword 25*/
606 u32 rx_1519_2047_byte_packets; /* dword 26*/
607 u32 rx_2048_4095_byte_packets; /* dword 27*/
608 u32 rx_4096_8191_byte_packets; /* dword 28*/
609 u32 rx_8192_9216_byte_packets; /* dword 29*/
610 u32 rx_ip_checksum_errs; /* dword 30*/
611 u32 rx_tcp_checksum_errs; /* dword 31*/
612 u32 rx_udp_checksum_errs; /* dword 32*/
613 u32 rx_non_rss_packets; /* dword 33*/
614 u32 rx_ipv4_packets; /* dword 34*/
615 u32 rx_ipv6_packets; /* dword 35*/
616 u32 rx_ipv4_bytes_lsd; /* dword 36*/
617 u32 rx_ipv4_bytes_msd; /* dword 37*/
618 u32 rx_ipv6_bytes_lsd; /* dword 38*/
619 u32 rx_ipv6_bytes_msd; /* dword 39*/
620 u32 rx_chute1_packets; /* dword 40*/
621 u32 rx_chute2_packets; /* dword 41*/
622 u32 rx_chute3_packets; /* dword 42*/
623 u32 rx_management_packets; /* dword 43*/
624 u32 rx_switched_unicast_packets; /* dword 44*/
625 u32 rx_switched_multicast_packets; /* dword 45*/
626 u32 rx_switched_broadcast_packets; /* dword 46*/
627 u32 tx_bytes_lsd; /* dword 47*/
628 u32 tx_bytes_msd; /* dword 48*/
629 u32 tx_unicastframes; /* dword 49*/
630 u32 tx_multicastframes; /* dword 50*/
631 u32 tx_broadcastframes; /* dword 51*/
632 u32 tx_pauseframes; /* dword 52*/
633 u32 tx_controlframes; /* dword 53*/
634 u32 tx_64_byte_packets; /* dword 54*/
635 u32 tx_65_127_byte_packets; /* dword 55*/
636 u32 tx_128_256_byte_packets; /* dword 56*/
637 u32 tx_256_511_byte_packets; /* dword 57*/
638 u32 tx_512_1023_byte_packets; /* dword 58*/
639 u32 tx_1024_1518_byte_packets; /* dword 59*/
640 u32 tx_1519_2047_byte_packets; /* dword 60*/
641 u32 tx_2048_4095_byte_packets; /* dword 61*/
642 u32 tx_4096_8191_byte_packets; /* dword 62*/
643 u32 tx_8192_9216_byte_packets; /* dword 63*/
644 u32 rx_fifo_overflow; /* dword 64*/
645 u32 rx_input_fifo_overflow; /* dword 65*/
646};
647
89a88ab8
AK		 648struct be_rxf_stats_v0 {
649 struct be_port_rxf_stats_v0 port[2];
6b7c5b94
SP		 650 u32 rx_drops_no_pbuf; /* dword 132*/
651 u32 rx_drops_no_txpb; /* dword 133*/
652 u32 rx_drops_no_erx_descr; /* dword 134*/
653 u32 rx_drops_no_tpre_descr; /* dword 135*/
654 u32 management_rx_port_packets; /* dword 136*/
655 u32 management_rx_port_bytes; /* dword 137*/
656 u32 management_rx_port_pause_frames; /* dword 138*/
657 u32 management_rx_port_errors; /* dword 139*/
658 u32 management_tx_port_packets; /* dword 140*/
659 u32 management_tx_port_bytes; /* dword 141*/
660 u32 management_tx_port_pause; /* dword 142*/
661 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
662 u32 rx_drops_too_many_frags; /* dword 144*/
663 u32 rx_drops_invalid_ring; /* dword 145*/
664 u32 forwarded_packets; /* dword 146*/
665 u32 rx_drops_mtu; /* dword 147*/
f6c4bf3e
AK		 666 u32 rsvd0[7];
667 u32 port0_jabber_events;
668 u32 port1_jabber_events;
669 u32 rsvd1[6];
6b7c5b94
SP		 670};
671
89a88ab8 672struct be_erx_stats_v0 {
6b7c5b94 673 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
89a88ab8 674 u32 rsvd[4];
6b7c5b94
SP		 675};
676
f6c4bf3e
AK		 677struct be_pmem_stats {
678 u32 eth_red_drops;
89a88ab8 679 u32 rsvd[5];
f6c4bf3e
AK		 680};
681
89a88ab8
AK		 682struct be_hw_stats_v0 {
683 struct be_rxf_stats_v0 rxf;
6b7c5b94 684 u32 rsvd[48];
89a88ab8 685 struct be_erx_stats_v0 erx;
f6c4bf3e 686 struct be_pmem_stats pmem;
6b7c5b94
SP		 687};
688
89a88ab8 689struct be_cmd_req_get_stats_v0 {
6b7c5b94 690 struct be_cmd_req_hdr hdr;
89a88ab8 691 u8 rsvd[sizeof(struct be_hw_stats_v0)];
6b7c5b94
SP		 692};
693
89a88ab8 694struct be_cmd_resp_get_stats_v0 {
6b7c5b94 695 struct be_cmd_resp_hdr hdr;
89a88ab8 696 struct be_hw_stats_v0 hw_stats;
6b7c5b94
SP		 697};
698
ac124ff9 699struct lancer_pport_stats {
005d5696
SX		 700 u32 tx_packets_lo;
701 u32 tx_packets_hi;
702 u32 tx_unicast_packets_lo;
703 u32 tx_unicast_packets_hi;
704 u32 tx_multicast_packets_lo;
705 u32 tx_multicast_packets_hi;
706 u32 tx_broadcast_packets_lo;
707 u32 tx_broadcast_packets_hi;
708 u32 tx_bytes_lo;
709 u32 tx_bytes_hi;
710 u32 tx_unicast_bytes_lo;
711 u32 tx_unicast_bytes_hi;
712 u32 tx_multicast_bytes_lo;
713 u32 tx_multicast_bytes_hi;
714 u32 tx_broadcast_bytes_lo;
715 u32 tx_broadcast_bytes_hi;
716 u32 tx_discards_lo;
717 u32 tx_discards_hi;
718 u32 tx_errors_lo;
719 u32 tx_errors_hi;
720 u32 tx_pause_frames_lo;
721 u32 tx_pause_frames_hi;
722 u32 tx_pause_on_frames_lo;
723 u32 tx_pause_on_frames_hi;
724 u32 tx_pause_off_frames_lo;
725 u32 tx_pause_off_frames_hi;
726 u32 tx_internal_mac_errors_lo;
727 u32 tx_internal_mac_errors_hi;
728 u32 tx_control_frames_lo;
729 u32 tx_control_frames_hi;
730 u32 tx_packets_64_bytes_lo;
731 u32 tx_packets_64_bytes_hi;
732 u32 tx_packets_65_to_127_bytes_lo;
733 u32 tx_packets_65_to_127_bytes_hi;
734 u32 tx_packets_128_to_255_bytes_lo;
735 u32 tx_packets_128_to_255_bytes_hi;
736 u32 tx_packets_256_to_511_bytes_lo;
737 u32 tx_packets_256_to_511_bytes_hi;
738 u32 tx_packets_512_to_1023_bytes_lo;
739 u32 tx_packets_512_to_1023_bytes_hi;
740 u32 tx_packets_1024_to_1518_bytes_lo;
741 u32 tx_packets_1024_to_1518_bytes_hi;
742 u32 tx_packets_1519_to_2047_bytes_lo;
743 u32 tx_packets_1519_to_2047_bytes_hi;
744 u32 tx_packets_2048_to_4095_bytes_lo;
745 u32 tx_packets_2048_to_4095_bytes_hi;
746 u32 tx_packets_4096_to_8191_bytes_lo;
747 u32 tx_packets_4096_to_8191_bytes_hi;
748 u32 tx_packets_8192_to_9216_bytes_lo;
749 u32 tx_packets_8192_to_9216_bytes_hi;
750 u32 tx_lso_packets_lo;
751 u32 tx_lso_packets_hi;
752 u32 rx_packets_lo;
753 u32 rx_packets_hi;
754 u32 rx_unicast_packets_lo;
755 u32 rx_unicast_packets_hi;
756 u32 rx_multicast_packets_lo;
757 u32 rx_multicast_packets_hi;
758 u32 rx_broadcast_packets_lo;
759 u32 rx_broadcast_packets_hi;
760 u32 rx_bytes_lo;
761 u32 rx_bytes_hi;
762 u32 rx_unicast_bytes_lo;
763 u32 rx_unicast_bytes_hi;
764 u32 rx_multicast_bytes_lo;
765 u32 rx_multicast_bytes_hi;
766 u32 rx_broadcast_bytes_lo;
767 u32 rx_broadcast_bytes_hi;
768 u32 rx_unknown_protos;
769 u32 rsvd_69; /* Word 69 is reserved */
770 u32 rx_discards_lo;
771 u32 rx_discards_hi;
772 u32 rx_errors_lo;
773 u32 rx_errors_hi;
774 u32 rx_crc_errors_lo;
775 u32 rx_crc_errors_hi;
776 u32 rx_alignment_errors_lo;
777 u32 rx_alignment_errors_hi;
778 u32 rx_symbol_errors_lo;
779 u32 rx_symbol_errors_hi;
780 u32 rx_pause_frames_lo;
781 u32 rx_pause_frames_hi;
782 u32 rx_pause_on_frames_lo;
783 u32 rx_pause_on_frames_hi;
784 u32 rx_pause_off_frames_lo;
785 u32 rx_pause_off_frames_hi;
786 u32 rx_frames_too_long_lo;
787 u32 rx_frames_too_long_hi;
788 u32 rx_internal_mac_errors_lo;
789 u32 rx_internal_mac_errors_hi;
790 u32 rx_undersize_packets;
791 u32 rx_oversize_packets;
792 u32 rx_fragment_packets;
793 u32 rx_jabbers;
794 u32 rx_control_frames_lo;
795 u32 rx_control_frames_hi;
796 u32 rx_control_frames_unknown_opcode_lo;
797 u32 rx_control_frames_unknown_opcode_hi;
798 u32 rx_in_range_errors;
799 u32 rx_out_of_range_errors;
d45b9d39
SP		 800 u32 rx_address_mismatch_drops;
801 u32 rx_vlan_mismatch_drops;
005d5696
SX		 802 u32 rx_dropped_too_small;
803 u32 rx_dropped_too_short;
804 u32 rx_dropped_header_too_small;
805 u32 rx_dropped_invalid_tcp_length;
806 u32 rx_dropped_runt;
807 u32 rx_ip_checksum_errors;
808 u32 rx_tcp_checksum_errors;
809 u32 rx_udp_checksum_errors;
810 u32 rx_non_rss_packets;
811 u32 rsvd_111;
812 u32 rx_ipv4_packets_lo;
813 u32 rx_ipv4_packets_hi;
814 u32 rx_ipv6_packets_lo;
815 u32 rx_ipv6_packets_hi;
816 u32 rx_ipv4_bytes_lo;
817 u32 rx_ipv4_bytes_hi;
818 u32 rx_ipv6_bytes_lo;
819 u32 rx_ipv6_bytes_hi;
820 u32 rx_nic_packets_lo;
821 u32 rx_nic_packets_hi;
822 u32 rx_tcp_packets_lo;
823 u32 rx_tcp_packets_hi;
824 u32 rx_iscsi_packets_lo;
825 u32 rx_iscsi_packets_hi;
826 u32 rx_management_packets_lo;
827 u32 rx_management_packets_hi;
828 u32 rx_switched_unicast_packets_lo;
829 u32 rx_switched_unicast_packets_hi;
830 u32 rx_switched_multicast_packets_lo;
831 u32 rx_switched_multicast_packets_hi;
832 u32 rx_switched_broadcast_packets_lo;
833 u32 rx_switched_broadcast_packets_hi;
834 u32 num_forwards_lo;
835 u32 num_forwards_hi;
836 u32 rx_fifo_overflow;
837 u32 rx_input_fifo_overflow;
838 u32 rx_drops_too_many_frags_lo;
839 u32 rx_drops_too_many_frags_hi;
840 u32 rx_drops_invalid_queue;
841 u32 rsvd_141;
842 u32 rx_drops_mtu_lo;
843 u32 rx_drops_mtu_hi;
844 u32 rx_packets_64_bytes_lo;
845 u32 rx_packets_64_bytes_hi;
846 u32 rx_packets_65_to_127_bytes_lo;
847 u32 rx_packets_65_to_127_bytes_hi;
848 u32 rx_packets_128_to_255_bytes_lo;
849 u32 rx_packets_128_to_255_bytes_hi;
850 u32 rx_packets_256_to_511_bytes_lo;
851 u32 rx_packets_256_to_511_bytes_hi;
852 u32 rx_packets_512_to_1023_bytes_lo;
853 u32 rx_packets_512_to_1023_bytes_hi;
854 u32 rx_packets_1024_to_1518_bytes_lo;
855 u32 rx_packets_1024_to_1518_bytes_hi;
856 u32 rx_packets_1519_to_2047_bytes_lo;
857 u32 rx_packets_1519_to_2047_bytes_hi;
858 u32 rx_packets_2048_to_4095_bytes_lo;
859 u32 rx_packets_2048_to_4095_bytes_hi;
860 u32 rx_packets_4096_to_8191_bytes_lo;
861 u32 rx_packets_4096_to_8191_bytes_hi;
862 u32 rx_packets_8192_to_9216_bytes_lo;
863 u32 rx_packets_8192_to_9216_bytes_hi;
864};
865
866struct pport_stats_params {
867 u16 pport_num;
868 u8 rsvd;
869 u8 reset_stats;
870};
871
872struct lancer_cmd_req_pport_stats {
873 struct be_cmd_req_hdr hdr;
874 union {
875 struct pport_stats_params params;
ac124ff9 876 u8 rsvd[sizeof(struct lancer_pport_stats)];
005d5696
SX		 877 } cmd_params;
878};
879
880struct lancer_cmd_resp_pport_stats {
881 struct be_cmd_resp_hdr hdr;
ac124ff9 882 struct lancer_pport_stats pport_stats;
005d5696
SX		 883};
884
ac124ff9 885static inline struct lancer_pport_stats*
005d5696
SX		 886 pport_stats_from_cmd(struct be_adapter *adapter)
887{
888 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
889 return &cmd->pport_stats;
890}
891
609ff3bb
AK		 892struct be_cmd_req_get_cntl_addnl_attribs {
893 struct be_cmd_req_hdr hdr;
894 u8 rsvd[8];
895};
896
897struct be_cmd_resp_get_cntl_addnl_attribs {
898 struct be_cmd_resp_hdr hdr;
899 u16 ipl_file_number;
900 u8 ipl_file_version;
901 u8 rsvd0;
902 u8 on_die_temperature; /* in degrees centigrade*/
903 u8 rsvd1[3];
904};
905
6b7c5b94
SP		 906struct be_cmd_req_vlan_config {
907 struct be_cmd_req_hdr hdr;
908 u8 interface_id;
909 u8 promiscuous;
910 u8 untagged;
911 u8 num_vlan;
912 u16 normal_vlan[64];
913} __packed;
914
5b8821b7 915/******************* RX FILTER ******************************/
e7b909a6 916#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 917struct macaddr {
918 u8 byte[ETH_ALEN];
919};
920
ecd0bf0f
PR		 921struct be_cmd_req_rx_filter {
922 struct be_cmd_req_hdr hdr;
923 u32 global_flags_mask;
924 u32 global_flags;
925 u32 if_flags_mask;
926 u32 if_flags;
927 u32 if_id;
5b8821b7
SP		 928 u32 mcast_num;
929 struct macaddr mcast_mac[BE_MAX_MC];
ecd0bf0f
PR		 930};
931
6b7c5b94
SP		 932/******************** Link Status Query *******************/
933struct be_cmd_req_link_status {
934 struct be_cmd_req_hdr hdr;
935 u32 rsvd;
936};
937
6b7c5b94
SP		 938enum {
939 PHY_LINK_DUPLEX_NONE = 0x0,
940 PHY_LINK_DUPLEX_HALF = 0x1,
941 PHY_LINK_DUPLEX_FULL = 0x2
942};
943
944enum {
945 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
946 PHY_LINK_SPEED_10MBPS = 0x1,
947 PHY_LINK_SPEED_100MBPS = 0x2,
948 PHY_LINK_SPEED_1GBPS = 0x3,
949 PHY_LINK_SPEED_10GBPS = 0x4
950};
951
952struct be_cmd_resp_link_status {
953 struct be_cmd_resp_hdr hdr;
954 u8 physical_port;
955 u8 mac_duplex;
956 u8 mac_speed;
957 u8 mac_fault;
958 u8 mgmt_mac_duplex;
959 u8 mgmt_mac_speed;
0388f251 960 u16 link_speed;
b236916a
AK		 961 u8 logical_link_status;
962 u8 rsvd1[3];
6b7c5b94
SP		 963} __packed;
964
0388f251
SB		 965/******************** Port Identification ***************************/
966/* Identifies the type of port attached to NIC */
967struct be_cmd_req_port_type {
968 struct be_cmd_req_hdr hdr;
969 u32 page_num;
970 u32 port;
971};
972
973enum {
974 TR_PAGE_A0 = 0xa0,
975 TR_PAGE_A2 = 0xa2
976};
977
978struct be_cmd_resp_port_type {
979 struct be_cmd_resp_hdr hdr;
980 u32 page_num;
981 u32 port;
982 struct data {
983 u8 identifier;
984 u8 identifier_ext;
985 u8 connector;
986 u8 transceiver[8];
987 u8 rsvd0[3];
988 u8 length_km;
989 u8 length_hm;
990 u8 length_om1;
991 u8 length_om2;
992 u8 length_cu;
993 u8 length_cu_m;
994 u8 vendor_name[16];
995 u8 rsvd;
996 u8 vendor_oui[3];
997 u8 vendor_pn[16];
998 u8 vendor_rev[4];
999 } data;
1000};
1001
6b7c5b94 1002/******************** Get FW Version *******************/
6b7c5b94
SP		 1003struct be_cmd_req_get_fw_version {
1004 struct be_cmd_req_hdr hdr;
1005 u8 rsvd0[FW_VER_LEN];
1006 u8 rsvd1[FW_VER_LEN];
1007} __packed;
1008
1009struct be_cmd_resp_get_fw_version {
1010 struct be_cmd_resp_hdr hdr;
1011 u8 firmware_version_string[FW_VER_LEN];
1012 u8 fw_on_flash_version_string[FW_VER_LEN];
1013} __packed;
1014
1015/******************** Set Flow Contrl *******************/
1016struct be_cmd_req_set_flow_control {
1017 struct be_cmd_req_hdr hdr;
1018 u16 tx_flow_control;
1019 u16 rx_flow_control;
1020} __packed;
1021
1022/******************** Get Flow Contrl *******************/
1023struct be_cmd_req_get_flow_control {
1024 struct be_cmd_req_hdr hdr;
1025 u32 rsvd;
1026};
1027
1028struct be_cmd_resp_get_flow_control {
1029 struct be_cmd_resp_hdr hdr;
1030 u16 tx_flow_control;
1031 u16 rx_flow_control;
1032} __packed;
1033
1034/******************** Modify EQ Delay *******************/
1035struct be_cmd_req_modify_eq_delay {
1036 struct be_cmd_req_hdr hdr;
1037 u32 num_eq;
1038 struct {
1039 u32 eq_id;
1040 u32 phase;
1041 u32 delay_multiplier;
1042 } delay[8];
1043} __packed;
1044
1045struct be_cmd_resp_modify_eq_delay {
1046 struct be_cmd_resp_hdr hdr;
1047 u32 rsvd0;
1048} __packed;
1049
1050/******************** Get FW Config *******************/
752961a1
SP		 1051/* The HW can come up in either of the following multi-channel modes
1052 * based on the skew/IPL.
1053 */
045508a8 1054#define RDMA_ENABLED 0x4
752961a1
SP		 1055#define FLEX10_MODE 0x400
1056#define VNIC_MODE 0x20000
1057#define UMC_ENABLED 0x1000000
6b7c5b94
SP		 1058struct be_cmd_req_query_fw_cfg {
1059 struct be_cmd_req_hdr hdr;
3abcdeda 1060 u32 rsvd[31];
6b7c5b94
SP		 1061};
1062
1063struct be_cmd_resp_query_fw_cfg {
1064 struct be_cmd_resp_hdr hdr;
1065 u32 be_config_number;
1066 u32 asic_revision;
1067 u32 phys_port;
3486be29 1068 u32 function_mode;
6b7c5b94 1069 u32 rsvd[26];
3abcdeda
SP		 1070 u32 function_caps;
1071};
1072
73dea398
PR		 1073/******************** RSS Config ****************************************/
1074/* RSS type Input parameters used to compute RX hash
1075 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1076 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1077 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1078 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1079 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1080 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1081 *
1082 * When multiple RSS types are enabled, HW picks the best hash policy
1083 * based on the type of the received packet.
1084 */
3abcdeda
SP		 1085#define RSS_ENABLE_NONE 0x0
1086#define RSS_ENABLE_IPV4 0x1
1087#define RSS_ENABLE_TCP_IPV4 0x2
1088#define RSS_ENABLE_IPV6 0x4
1089#define RSS_ENABLE_TCP_IPV6 0x8
d3bd3a5e
PR		 1090#define RSS_ENABLE_UDP_IPV4 0x10
1091#define RSS_ENABLE_UDP_IPV6 0x20
3abcdeda
SP		 1092
1093struct be_cmd_req_rss_config {
1094 struct be_cmd_req_hdr hdr;
1095 u32 if_id;
1096 u16 enable_rss;
1097 u16 cpu_table_size_log2;
1098 u32 hash[10];
1099 u8 cpu_table[128];
1100 u8 flush;
1101 u8 rsvd0[3];
6b7c5b94
SP		 1102};
1103
fad9ab2c
SB		 1104/******************** Port Beacon ***************************/
1105
1106#define BEACON_STATE_ENABLED 0x1
1107#define BEACON_STATE_DISABLED 0x0
1108
1109struct be_cmd_req_enable_disable_beacon {
1110 struct be_cmd_req_hdr hdr;
1111 u8 port_num;
1112 u8 beacon_state;
1113 u8 beacon_duration;
1114 u8 status_duration;
1115} __packed;
1116
1117struct be_cmd_resp_enable_disable_beacon {
1118 struct be_cmd_resp_hdr resp_hdr;
1119 u32 rsvd0;
1120} __packed;
1121
1122struct be_cmd_req_get_beacon_state {
1123 struct be_cmd_req_hdr hdr;
1124 u8 port_num;
1125 u8 rsvd0;
1126 u16 rsvd1;
1127} __packed;
1128
1129struct be_cmd_resp_get_beacon_state {
1130 struct be_cmd_resp_hdr resp_hdr;
1131 u8 beacon_state;
1132 u8 rsvd0[3];
1133} __packed;
1134
84517482
AK		 1135/****************** Firmware Flash ******************/
1136struct flashrom_params {
1137 u32 op_code;
1138 u32 op_type;
1139 u32 data_buf_size;
1140 u32 offset;
84517482
AK		 1141};
1142
1143struct be_cmd_write_flashrom {
1144 struct be_cmd_req_hdr hdr;
1145 struct flashrom_params params;
be716446
PR		 1146 u8 data_buf[32768];
1147 u8 rsvd[4];
1148} __packed;
84517482 1149
be716446
PR		 1150/* cmd to read flash crc */
1151struct be_cmd_read_flash_crc {
1152 struct be_cmd_req_hdr hdr;
1153 struct flashrom_params params;
1154 u8 crc[4];
1155 u8 rsvd[4];
1156};
485bf569
SN		 1157/**************** Lancer Firmware Flash ************/
1158struct amap_lancer_write_obj_context {
1159 u8 write_length[24];
1160 u8 reserved1[7];
1161 u8 eof;
1162} __packed;
1163
1164struct lancer_cmd_req_write_object {
1165 struct be_cmd_req_hdr hdr;
1166 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1167 u32 write_offset;
1168 u8 object_name[104];
1169 u32 descriptor_count;
1170 u32 buf_len;
1171 u32 addr_low;
1172 u32 addr_high;
1173};
1174
f67ef7ba
PR		 1175#define LANCER_NO_RESET_NEEDED 0x00
1176#define LANCER_FW_RESET_NEEDED 0x02
485bf569
SN		 1177struct lancer_cmd_resp_write_object {
1178 u8 opcode;
1179 u8 subsystem;
1180 u8 rsvd1[2];
1181 u8 status;
1182 u8 additional_status;
1183 u8 rsvd2[2];
1184 u32 resp_len;
1185 u32 actual_resp_len;
1186 u32 actual_write_len;
f67ef7ba
PR		 1187 u8 change_status;
1188 u8 rsvd3[3];
485bf569
SN		 1189};
1190
de49bd5a
PR		 1191/************************ Lancer Read FW info **************/
1192#define LANCER_READ_FILE_CHUNK (32*1024)
1193#define LANCER_READ_FILE_EOF_MASK 0x80000000
1194
1195#define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
af5875bd
PR		 1196#define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1197#define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
de49bd5a
PR		 1198
1199struct lancer_cmd_req_read_object {
1200 struct be_cmd_req_hdr hdr;
1201 u32 desired_read_len;
1202 u32 read_offset;
1203 u8 object_name[104];
1204 u32 descriptor_count;
1205 u32 buf_len;
1206 u32 addr_low;
1207 u32 addr_high;
1208};
1209
1210struct lancer_cmd_resp_read_object {
1211 u8 opcode;
1212 u8 subsystem;
1213 u8 rsvd1[2];
1214 u8 status;
1215 u8 additional_status;
1216 u8 rsvd2[2];
1217 u32 resp_len;
1218 u32 actual_resp_len;
1219 u32 actual_read_len;
1220 u32 eof;
1221};
1222
71d8d1b5
AK		 1223/************************ WOL *******************************/
1224struct be_cmd_req_acpi_wol_magic_config{
1225 struct be_cmd_req_hdr hdr;
1226 u32 rsvd0[145];
1227 u8 magic_mac[6];
1228 u8 rsvd2[2];
1229} __packed;
1230
4762f6ce
AK		 1231struct be_cmd_req_acpi_wol_magic_config_v1 {
1232 struct be_cmd_req_hdr hdr;
1233 u8 rsvd0[2];
1234 u8 query_options;
1235 u8 rsvd1[5];
1236 u32 rsvd2[288];
1237 u8 magic_mac[6];
1238 u8 rsvd3[22];
1239} __packed;
1240
1241struct be_cmd_resp_acpi_wol_magic_config_v1 {
1242 struct be_cmd_resp_hdr hdr;
1243 u8 rsvd0[2];
1244 u8 wol_settings;
1245 u8 rsvd1[5];
1246 u32 rsvd2[295];
1247} __packed;
1248
1249#define BE_GET_WOL_CAP 2
1250
1251#define BE_WOL_CAP 0x1
1252#define BE_PME_D0_CAP 0x8
1253#define BE_PME_D1_CAP 0x10
1254#define BE_PME_D2_CAP 0x20
1255#define BE_PME_D3HOT_CAP 0x40
1256#define BE_PME_D3COLD_CAP 0x80
1257
ff33a6e2
S		 1258/********************** LoopBack test *********************/
1259struct be_cmd_req_loopback_test {
1260 struct be_cmd_req_hdr hdr;
1261 u32 loopback_type;
1262 u32 num_pkts;
1263 u64 pattern;
1264 u32 src_port;
1265 u32 dest_port;
1266 u32 pkt_size;
1267};
1268
1269struct be_cmd_resp_loopback_test {
1270 struct be_cmd_resp_hdr resp_hdr;
1271 u32 status;
1272 u32 num_txfer;
1273 u32 num_rx;
1274 u32 miscomp_off;
1275 u32 ticks_compl;
1276};
1277
fced9999
SB		 1278struct be_cmd_req_set_lmode {
1279 struct be_cmd_req_hdr hdr;
1280 u8 src_port;
1281 u8 dest_port;
1282 u8 loopback_type;
1283 u8 loopback_state;
1284};
1285
1286struct be_cmd_resp_set_lmode {
1287 struct be_cmd_resp_hdr resp_hdr;
1288 u8 rsvd0[4];
1289};
1290
ff33a6e2
S		 1291/********************** DDR DMA test *********************/
1292struct be_cmd_req_ddrdma_test {
1293 struct be_cmd_req_hdr hdr;
1294 u64 pattern;
1295 u32 byte_count;
1296 u32 rsvd0;
1297 u8 snd_buff[4096];
1298 u8 rsvd1[4096];
1299};
1300
1301struct be_cmd_resp_ddrdma_test {
1302 struct be_cmd_resp_hdr hdr;
1303 u64 pattern;
1304 u32 byte_cnt;
1305 u32 snd_err;
1306 u8 rsvd0[4096];
1307 u8 rcv_buff[4096];
1308};
1309
368c0ca2
SB		 1310/*********************** SEEPROM Read ***********************/
1311
1312#define BE_READ_SEEPROM_LEN 1024
1313struct be_cmd_req_seeprom_read {
1314 struct be_cmd_req_hdr hdr;
1315 u8 rsvd0[BE_READ_SEEPROM_LEN];
1316};
1317
1318struct be_cmd_resp_seeprom_read {
1319 struct be_cmd_req_hdr hdr;
1320 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1321};
1322
ee3cb629
AK		 1323enum {
1324 PHY_TYPE_CX4_10GB = 0,
1325 PHY_TYPE_XFP_10GB,
1326 PHY_TYPE_SFP_1GB,
1327 PHY_TYPE_SFP_PLUS_10GB,
1328 PHY_TYPE_KR_10GB,
1329 PHY_TYPE_KX4_10GB,
1330 PHY_TYPE_BASET_10GB,
1331 PHY_TYPE_BASET_1GB,
42f11cf2
AK		 1332 PHY_TYPE_BASEX_1GB,
1333 PHY_TYPE_SGMII,
ee3cb629
AK		 1334 PHY_TYPE_DISABLED = 255
1335};
1336
42f11cf2
AK		 1337#define BE_SUPPORTED_SPEED_NONE 0
1338#define BE_SUPPORTED_SPEED_10MBPS 1
1339#define BE_SUPPORTED_SPEED_100MBPS 2
1340#define BE_SUPPORTED_SPEED_1GBPS 4
1341#define BE_SUPPORTED_SPEED_10GBPS 8
1342
1343#define BE_AN_EN 0x2
1344#define BE_PAUSE_SYM_EN 0x80
1345
1346/* MAC speed valid values */
1347#define SPEED_DEFAULT 0x0
1348#define SPEED_FORCED_10GB 0x1
1349#define SPEED_FORCED_1GB 0x2
1350#define SPEED_AUTONEG_10GB 0x3
1351#define SPEED_AUTONEG_1GB 0x4
1352#define SPEED_AUTONEG_100MB 0x5
1353#define SPEED_AUTONEG_10GB_1GB 0x6
1354#define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1355#define SPEED_AUTONEG_1GB_100MB 0x8
1356#define SPEED_AUTONEG_10MB 0x9
1357#define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1358#define SPEED_AUTONEG_100MB_10MB 0xb
1359#define SPEED_FORCED_100MB 0xc
1360#define SPEED_FORCED_10MB 0xd
1361
ee3cb629
AK		 1362struct be_cmd_req_get_phy_info {
1363 struct be_cmd_req_hdr hdr;
1364 u8 rsvd0[24];
1365};
306f1348
SP		 1366
1367struct be_phy_info {
ee3cb629
AK		 1368 u16 phy_type;
1369 u16 interface_type;
1370 u32 misc_params;
42f11cf2
AK		 1371 u16 ext_phy_details;
1372 u16 rsvd;
1373 u16 auto_speeds_supported;
1374 u16 fixed_speeds_supported;
1375 u32 future_use[2];
ee3cb629
AK		 1376};
1377
306f1348
SP		 1378struct be_cmd_resp_get_phy_info {
1379 struct be_cmd_req_hdr hdr;
1380 struct be_phy_info phy_info;
1381};
1382
e1d18735
AK		 1383/*********************** Set QOS ***********************/
1384
1385#define BE_QOS_BITS_NIC 1
1386
1387struct be_cmd_req_set_qos {
1388 struct be_cmd_req_hdr hdr;
1389 u32 valid_bits;
1390 u32 max_bps_nic;
1391 u32 rsvd[7];
1392};
1393
1394struct be_cmd_resp_set_qos {
1395 struct be_cmd_resp_hdr hdr;
1396 u32 rsvd;
1397};
1398
9e1453c5
AK		 1399/*********************** Controller Attributes ***********************/
1400struct be_cmd_req_cntl_attribs {
1401 struct be_cmd_req_hdr hdr;
1402};
1403
1404struct be_cmd_resp_cntl_attribs {
1405 struct be_cmd_resp_hdr hdr;
1406 struct mgmt_controller_attrib attribs;
1407};
1408
2e588f84
SP		 1409/*********************** Set driver function ***********************/
1410#define CAPABILITY_SW_TIMESTAMPS 2
1411#define CAPABILITY_BE3_NATIVE_ERX_API 4
1412
1413struct be_cmd_req_set_func_cap {
1414 struct be_cmd_req_hdr hdr;
1415 u32 valid_cap_flags;
1416 u32 cap_flags;
1417 u8 rsvd[212];
1418};
1419
1420struct be_cmd_resp_set_func_cap {
1421 struct be_cmd_resp_hdr hdr;
1422 u32 valid_cap_flags;
1423 u32 cap_flags;
1424 u8 rsvd[212];
1425};
1426
f25b119c
PR		 1427/*********************** Function Privileges ***********************/
1428enum {
1429 BE_PRIV_DEFAULT = 0x1,
1430 BE_PRIV_LNKQUERY = 0x2,
1431 BE_PRIV_LNKSTATS = 0x4,
1432 BE_PRIV_LNKMGMT = 0x8,
1433 BE_PRIV_LNKDIAG = 0x10,
1434 BE_PRIV_UTILQUERY = 0x20,
1435 BE_PRIV_FILTMGMT = 0x40,
1436 BE_PRIV_IFACEMGMT = 0x80,
1437 BE_PRIV_VHADM = 0x100,
1438 BE_PRIV_DEVCFG = 0x200,
1439 BE_PRIV_DEVSEC = 0x400
1440};
1441#define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1442 BE_PRIV_DEVSEC)
1443#define MIN_PRIVILEGES BE_PRIV_DEFAULT
1444
1445struct be_cmd_priv_map {
1446 u8 opcode;
1447 u8 subsystem;
1448 u32 priv_mask;
1449};
1450
1451struct be_cmd_req_get_fn_privileges {
1452 struct be_cmd_req_hdr hdr;
1453 u32 rsvd;
1454};
1455
1456struct be_cmd_resp_get_fn_privileges {
1457 struct be_cmd_resp_hdr hdr;
1458 u32 privilege_mask;
1459};
1460
1461
590c391d
PR		 1462/******************** GET/SET_MACLIST **************************/
1463#define BE_MAX_MAC 64
590c391d
PR		 1464struct be_cmd_req_get_mac_list {
1465 struct be_cmd_req_hdr hdr;
e5e1ee89
PR		 1466 u8 mac_type;
1467 u8 perm_override;
1468 u16 iface_id;
1469 u32 mac_id;
1470 u32 rsvd[3];
1471} __packed;
1472
1473struct get_list_macaddr {
1474 u16 mac_addr_size;
1475 union {
1476 u8 macaddr[6];
1477 struct {
1478 u8 rsvd[2];
1479 u32 mac_id;
1480 } __packed s_mac_id;
1481 } __packed mac_addr_id;
590c391d
PR		 1482} __packed;
1483
1484struct be_cmd_resp_get_mac_list {
1485 struct be_cmd_resp_hdr hdr;
e5e1ee89
PR		 1486 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1487 struct get_list_macaddr macid_macaddr; /* soft mac */
1488 u8 true_mac_count;
1489 u8 pseudo_mac_count;
1490 u8 mac_list_size;
1491 u8 rsvd;
1492 /* perm override mac */
1493 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
590c391d
PR		 1494} __packed;
1495
1496struct be_cmd_req_set_mac_list {
1497 struct be_cmd_req_hdr hdr;
1498 u8 mac_count;
1499 u8 rsvd1;
1500 u16 rsvd2;
1501 struct macaddr mac[BE_MAX_MAC];
1502} __packed;
1503
f1f3ee1b
AK		 1504/*********************** HSW Config ***********************/
1505struct amap_set_hsw_context {
1506 u8 interface_id[16];
1507 u8 rsvd0[14];
1508 u8 pvid_valid;
1509 u8 rsvd1;
1510 u8 rsvd2[16];
1511 u8 pvid[16];
1512 u8 rsvd3[32];
1513 u8 rsvd4[32];
1514 u8 rsvd5[32];
1515} __packed;
1516
1517struct be_cmd_req_set_hsw_config {
1518 struct be_cmd_req_hdr hdr;
1519 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1520} __packed;
1521
1522struct be_cmd_resp_set_hsw_config {
1523 struct be_cmd_resp_hdr hdr;
1524 u32 rsvd;
1525};
1526
1527struct amap_get_hsw_req_context {
1528 u8 interface_id[16];
1529 u8 rsvd0[14];
1530 u8 pvid_valid;
1531 u8 pport;
1532} __packed;
1533
1534struct amap_get_hsw_resp_context {
1535 u8 rsvd1[16];
1536 u8 pvid[16];
1537 u8 rsvd2[32];
1538 u8 rsvd3[32];
1539 u8 rsvd4[32];
1540} __packed;
1541
1542struct be_cmd_req_get_hsw_config {
1543 struct be_cmd_req_hdr hdr;
1544 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1545} __packed;
1546
1547struct be_cmd_resp_get_hsw_config {
1548 struct be_cmd_resp_hdr hdr;
1549 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1550 u32 rsvd;
1551};
1552
b4e32a71
PR		 1553/******************* get port names ***************/
1554struct be_cmd_req_get_port_name {
1555 struct be_cmd_req_hdr hdr;
1556 u32 rsvd0;
1557};
1558
1559struct be_cmd_resp_get_port_name {
1560 struct be_cmd_req_hdr hdr;
1561 u8 port_name[4];
1562};
1563
89a88ab8
AK		 1564/*************** HW Stats Get v1 **********************************/
1565#define BE_TXP_SW_SZ 48
1566struct be_port_rxf_stats_v1 {
1567 u32 rsvd0[12];
1568 u32 rx_crc_errors;
1569 u32 rx_alignment_symbol_errors;
1570 u32 rx_pause_frames;
1571 u32 rx_priority_pause_frames;
1572 u32 rx_control_frames;
1573 u32 rx_in_range_errors;
1574 u32 rx_out_range_errors;
1575 u32 rx_frame_too_long;
d45b9d39 1576 u32 rx_address_mismatch_drops;
89a88ab8
AK		 1577 u32 rx_dropped_too_small;
1578 u32 rx_dropped_too_short;
1579 u32 rx_dropped_header_too_small;
1580 u32 rx_dropped_tcp_length;
1581 u32 rx_dropped_runt;
1582 u32 rsvd1[10];
1583 u32 rx_ip_checksum_errs;
1584 u32 rx_tcp_checksum_errs;
1585 u32 rx_udp_checksum_errs;
1586 u32 rsvd2[7];
1587 u32 rx_switched_unicast_packets;
1588 u32 rx_switched_multicast_packets;
1589 u32 rx_switched_broadcast_packets;
1590 u32 rsvd3[3];
1591 u32 tx_pauseframes;
1592 u32 tx_priority_pauseframes;
1593 u32 tx_controlframes;
1594 u32 rsvd4[10];
1595 u32 rxpp_fifo_overflow_drop;
1596 u32 rx_input_fifo_overflow_drop;
1597 u32 pmem_fifo_overflow_drop;
1598 u32 jabber_events;
1599 u32 rsvd5[3];
1600};
1601
1602
1603struct be_rxf_stats_v1 {
1604 struct be_port_rxf_stats_v1 port[4];
1605 u32 rsvd0[2];
1606 u32 rx_drops_no_pbuf;
1607 u32 rx_drops_no_txpb;
1608 u32 rx_drops_no_erx_descr;
1609 u32 rx_drops_no_tpre_descr;
1610 u32 rsvd1[6];
1611 u32 rx_drops_too_many_frags;
1612 u32 rx_drops_invalid_ring;
1613 u32 forwarded_packets;
1614 u32 rx_drops_mtu;
1615 u32 rsvd2[14];
1616};
1617
1618struct be_erx_stats_v1 {
1619 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1620 u32 rsvd[4];
1621};
1622
1623struct be_hw_stats_v1 {
1624 struct be_rxf_stats_v1 rxf;
1625 u32 rsvd0[BE_TXP_SW_SZ];
1626 struct be_erx_stats_v1 erx;
1627 struct be_pmem_stats pmem;
0b3f0e7a 1628 u32 rsvd1[18];
89a88ab8
AK		 1629};
1630
1631struct be_cmd_req_get_stats_v1 {
1632 struct be_cmd_req_hdr hdr;
1633 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1634};
1635
1636struct be_cmd_resp_get_stats_v1 {
1637 struct be_cmd_resp_hdr hdr;
1638 struct be_hw_stats_v1 hw_stats;
1639};
1640
941a77d5
SK		 1641/************** get fat capabilites *******************/
1642#define MAX_MODULES 27
1643#define MAX_MODES 4
1644#define MODE_UART 0
1645#define FW_LOG_LEVEL_DEFAULT 48
1646#define FW_LOG_LEVEL_FATAL 64
1647
1648struct ext_fat_mode {
1649 u8 mode;
1650 u8 rsvd0;
1651 u16 port_mask;
1652 u32 dbg_lvl;
1653 u64 fun_mask;
1654} __packed;
1655
1656struct ext_fat_modules {
1657 u8 modules_str[32];
1658 u32 modules_id;
1659 u32 num_modes;
1660 struct ext_fat_mode trace_lvl[MAX_MODES];
1661} __packed;
1662
1663struct be_fat_conf_params {
1664 u32 max_log_entries;
1665 u32 log_entry_size;
1666 u8 log_type;
1667 u8 max_log_funs;
1668 u8 max_log_ports;
1669 u8 rsvd0;
1670 u32 supp_modes;
1671 u32 num_modules;
1672 struct ext_fat_modules module[MAX_MODULES];
1673} __packed;
1674
1675struct be_cmd_req_get_ext_fat_caps {
1676 struct be_cmd_req_hdr hdr;
1677 u32 parameter_type;
1678};
1679
1680struct be_cmd_resp_get_ext_fat_caps {
1681 struct be_cmd_resp_hdr hdr;
1682 struct be_fat_conf_params get_params;
1683};
1684
1685struct be_cmd_req_set_ext_fat_caps {
1686 struct be_cmd_req_hdr hdr;
1687 struct be_fat_conf_params set_params;
1688};
1689
abb93951
PR		 1690#define RESOURCE_DESC_SIZE 72
1691#define NIC_RESOURCE_DESC_TYPE_ID 0x41
1692#define MAX_RESOURCE_DESC 4
d5c18473
PR		 1693
1694/* QOS unit number */
1695#define QUN 4
1696/* Immediate */
1697#define IMM 6
1698/* No save */
1699#define NOSV 7
1700
abb93951
PR		 1701struct be_nic_resource_desc {
1702 u8 desc_type;
1703 u8 desc_len;
1704 u8 rsvd1;
1705 u8 flags;
1706 u8 vf_num;
1707 u8 rsvd2;
1708 u8 pf_num;
1709 u8 rsvd3;
1710 u16 unicast_mac_count;
1711 u8 rsvd4[6];
1712 u16 mcc_count;
1713 u16 vlan_count;
1714 u16 mcast_mac_count;
1715 u16 txq_count;
1716 u16 rq_count;
1717 u16 rssq_count;
1718 u16 lro_count;
1719 u16 cq_count;
1720 u16 toe_conn_count;
1721 u16 eq_count;
1722 u32 rsvd5;
1723 u32 cap_flags;
1724 u8 link_param;
1725 u8 rsvd6[3];
1726 u32 bw_min;
1727 u32 bw_max;
1728 u8 acpi_params;
1729 u8 wol_param;
1730 u16 rsvd7;
1731 u32 rsvd8[3];
1732};
1733
1734struct be_cmd_req_get_func_config {
1735 struct be_cmd_req_hdr hdr;
1736};
1737
1738struct be_cmd_resp_get_func_config {
1739 struct be_cmd_req_hdr hdr;
1740 u32 desc_count;
1741 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE];
1742};
1743
1744#define ACTIVE_PROFILE_TYPE 0x2
1745struct be_cmd_req_get_profile_config {
1746 struct be_cmd_req_hdr hdr;
1747 u8 rsvd;
1748 u8 type;
1749 u16 rsvd1;
1750};
1751
1752struct be_cmd_resp_get_profile_config {
1753 struct be_cmd_req_hdr hdr;
1754 u32 desc_count;
1755 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE];
1756};
1757
d5c18473
PR		 1758struct be_cmd_req_set_profile_config {
1759 struct be_cmd_req_hdr hdr;
1760 u32 rsvd;
1761 u32 desc_count;
1762 struct be_nic_resource_desc nic_desc;
1763};
1764
1765struct be_cmd_resp_set_profile_config {
1766 struct be_cmd_req_hdr hdr;
1767};
1768
dcf7ebba
PR		 1769struct be_cmd_enable_disable_vf {
1770 struct be_cmd_req_hdr hdr;
1771 u8 enable;
1772 u8 rsvd[3];
1773};
1774
68c45a2d
SK		 1775struct be_cmd_req_intr_set {
1776 struct be_cmd_req_hdr hdr;
1777 u8 intr_enabled;
1778 u8 rsvd[3];
1779};
1780
f25b119c
PR		 1781static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
1782{
1783 return flags & adapter->cmd_privileges ? true : false;
1784}
1785
4c876616
SP		 1786/************** Get IFACE LIST *******************/
1787struct be_if_desc {
1788 u32 if_id;
1789 u32 cap_flags;
1790 u32 en_flags;
1791};
1792
1793struct be_cmd_req_get_iface_list {
1794 struct be_cmd_req_hdr hdr;
1795};
1796
1797struct be_cmd_resp_get_iface_list {
1798 struct be_cmd_req_hdr hdr;
1799 u32 if_cnt;
1800 struct be_if_desc if_desc;
1801};
1802
8788fdc2 1803extern int be_pci_fnum_get(struct be_adapter *adapter);
bf99e50d 1804extern int be_fw_wait_ready(struct be_adapter *adapter);
8788fdc2 1805extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 1806 bool permanent, u32 if_handle, u32 pmac_id);
8788fdc2 1807extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08
AK		 1808 u32 if_id, u32 *pmac_id, u32 domain);
1809extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
30128031 1810 int pmac_id, u32 domain);
73d540f2 1811extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1578e777 1812 u32 en_flags, u32 *if_handle, u32 domain);
30128031 1813extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle,
658681f7 1814 u32 domain);
8788fdc2 1815extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 1816 struct be_queue_info *eq, int eq_delay);
8788fdc2 1817extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94 1818 struct be_queue_info *cq, struct be_queue_info *eq,
10ef9ab4 1819 bool no_delay, int num_cqe_dma_coalesce);
8788fdc2 1820extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 1821 struct be_queue_info *mccq,
1822 struct be_queue_info *cq);
8788fdc2 1823extern int be_cmd_txq_create(struct be_adapter *adapter,
94d73aaa 1824 struct be_tx_obj *txo);
8788fdc2 1825extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94 1826 struct be_queue_info *rxq, u16 cq_id,
10ef9ab4 1827 u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
8788fdc2 1828extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 1829 int type);
482c9e79
SP		 1830extern int be_cmd_rxq_destroy(struct be_adapter *adapter,
1831 struct be_queue_info *q);
323ff71e
SP		 1832extern int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1833 u8 *link_status, u32 dom);
8788fdc2
SP		 1834extern int be_cmd_reset(struct be_adapter *adapter);
1835extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 1836 struct be_dma_mem *nonemb_cmd);
005d5696
SX		 1837extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1838 struct be_dma_mem *nonemb_cmd);
04b71175
SP		 1839extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1840 char *fw_on_flash);
6b7c5b94 1841
8788fdc2
SP		 1842extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1843extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 1844 u16 *vtag_array, u32 num, bool untagged,
1845 bool promiscuous);
5b8821b7 1846extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
8788fdc2 1847extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 1848 u32 tx_fc, u32 rx_fc);
8788fdc2 1849extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 1850 u32 *tx_fc, u32 *rx_fc);
dcb9b564 1851extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
3abcdeda 1852 u32 *port_num, u32 *function_mode, u32 *function_caps);
14074eab 1853extern int be_cmd_reset_function(struct be_adapter *adapter);
3abcdeda
SP		 1854extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1855 u16 table_size);
10ef9ab4 1856extern int be_process_mcc(struct be_adapter *adapter);
fad9ab2c
SB		 1857extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1858 u8 port_num, u8 beacon, u8 status, u8 state);
1859extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1860 u8 port_num, u32 *state);
84517482
AK		 1861extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1862 struct be_dma_mem *cmd, u32 flash_oper,
1863 u32 flash_opcode, u32 buf_size);
485bf569 1864extern int lancer_cmd_write_object(struct be_adapter *adapter,
f67ef7ba
PR		 1865 struct be_dma_mem *cmd,
1866 u32 data_size, u32 data_offset,
1867 const char *obj_name,
1868 u32 *data_written, u8 *change_status,
1869 u8 *addn_status);
de49bd5a
PR		 1870int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1871 u32 data_size, u32 data_offset, const char *obj_name,
1872 u32 *data_read, u32 *eof, u8 *addn_status);
3f0d4560
AK		 1873int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1874 int offset);
71d8d1b5
AK		 1875extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1876 struct be_dma_mem *nonemb_cmd);
2243e2e9
SP		 1877extern int be_cmd_fw_init(struct be_adapter *adapter);
1878extern int be_cmd_fw_clean(struct be_adapter *adapter);
7a1e9b20
SP		 1879extern void be_async_mcc_enable(struct be_adapter *adapter);
1880extern void be_async_mcc_disable(struct be_adapter *adapter);
ff33a6e2
S		 1881extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1882 u32 loopback_type, u32 pkt_size,
1883 u32 num_pkts, u64 pattern);
1884extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1885 u32 byte_cnt, struct be_dma_mem *cmd);
368c0ca2
SB		 1886extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1887 struct be_dma_mem *nonemb_cmd);
fced9999
SB		 1888extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1889 u8 loopback_type, u8 enable);
42f11cf2 1890extern int be_cmd_get_phy_info(struct be_adapter *adapter);
e1d18735 1891extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
f67ef7ba 1892extern void be_detect_error(struct be_adapter *adapter);
609ff3bb 1893extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
9e1453c5 1894extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
2dc1deb6 1895extern int be_cmd_req_native_mode(struct be_adapter *adapter);
311fddc7
SK		 1896extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1897extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
f25b119c
PR		 1898extern int be_cmd_get_fn_privileges(struct be_adapter *adapter,
1899 u32 *privilege, u32 domain);
1578e777
PR		 1900extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
1901 bool *pmac_id_active, u32 *pmac_id,
1902 u8 domain);
590c391d
PR		 1903extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
1904 u8 mac_count, u32 domain);
f1f3ee1b
AK		 1905extern int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
1906 u32 domain, u16 intf_id);
1907extern int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
1908 u32 domain, u16 intf_id);
4762f6ce 1909extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
941a77d5
SK		 1910extern int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
1911 struct be_dma_mem *cmd);
1912extern int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
1913 struct be_dma_mem *cmd,
1914 struct be_fat_conf_params *cfgs);
bf99e50d
PR		 1915extern int lancer_wait_ready(struct be_adapter *adapter);
1916extern int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
b4e32a71 1917extern int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name);
abb93951
PR		 1918extern int be_cmd_get_func_config(struct be_adapter *adapter);
1919extern int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
1920 u8 domain);
d5c18473
PR		 1921
1922extern int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
1923 u8 domain);
4c876616
SP		 1924extern int be_cmd_get_if_id(struct be_adapter *adapter,
1925 struct be_vf_cfg *vf_cfg, int vf_num);
dcf7ebba 1926extern int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
68c45a2d 1927extern int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
Linux 6.x block layer and io_uring tree(s)