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Merge tag 'for-linus-20160311' of git://git.infradead.org/linux-mtd
[linux-2.6-block.git] / drivers / net / ethernet / emulex / benet / be_cmds.h
CommitLineData
6b7c5b94 1/*
d19261b8 2 * Copyright (C) 2005 - 2015 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
83b06116
VV		 47#define CQE_FLAGS_VALID_MASK BIT(31)
48#define CQE_FLAGS_ASYNC_MASK BIT(30)
49#define CQE_FLAGS_COMPLETED_MASK BIT(28)
50#define CQE_FLAGS_CONSUMED_MASK BIT(27)
6b7c5b94
SP		 51
52/* Completion Status */
4c60005f 53enum mcc_base_status {
2b3f291b
SP		 54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
b29812c1
SR		 60 MCC_STATUS_NOT_SUPPORTED = 66,
61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68
6b7c5b94
SP		 62};
63
4c60005f
KA		 64/* Additional status */
65enum mcc_addl_status {
66 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16,
67 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d,
77be8c1c 68 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a,
6b525782
SR		 69 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab,
70 MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56,
71 MCC_ADDL_STATUS_MISSING_SIGNATURE = 0x57
4c60005f
KA		 72};
73
74#define CQE_BASE_STATUS_MASK 0xFFFF
75#define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */
76#define CQE_ADDL_STATUS_MASK 0xFF
77#define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */
d9d604f8 78
4c60005f
KA		 79#define base_status(status) \
80 ((enum mcc_base_status) \
81 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0))
82#define addl_status(status) \
83 ((enum mcc_addl_status) \
84 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \
85 CQE_ADDL_STATUS_MASK : 0))
6b7c5b94 86
efd2e40a 87struct be_mcc_compl {
6b7c5b94
SP		 88 u32 status; /* dword 0 */
89 u32 tag0; /* dword 1 */
90 u32 tag1; /* dword 2 */
91 u32 flags; /* dword 3 */
92};
93
3acf19d9
SP		 94/* When the async bit of mcc_compl flags is set, flags
95 * is interpreted as follows:
a8f447bd 96 */
3acf19d9
SP		 97#define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
98#define ASYNC_EVENT_CODE_MASK 0xFF
99#define ASYNC_EVENT_TYPE_SHIFT 16
100#define ASYNC_EVENT_TYPE_MASK 0xFF
a8f447bd 101#define ASYNC_EVENT_CODE_LINK_STATE 0x1
cc4ce020
SK		 102#define ASYNC_EVENT_CODE_GRP_5 0x5
103#define ASYNC_EVENT_QOS_SPEED 0x1
104#define ASYNC_EVENT_COS_PRIORITY 0x2
3968fa1e 105#define ASYNC_EVENT_PVID_STATE 0x3
bc0c3405
AK		 106#define ASYNC_EVENT_CODE_QNQ 0x6
107#define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
21252377
VV		 108#define ASYNC_EVENT_CODE_SLIPORT 0x11
109#define ASYNC_EVENT_PORT_MISCONFIG 0x9
760c295e 110#define ASYNC_EVENT_FW_CONTROL 0x5
bc0c3405 111
a8f447bd 112enum {
ea172a01
SP		 113 LINK_DOWN = 0x0,
114 LINK_UP = 0x1
a8f447bd 115};
ea172a01 116#define LINK_STATUS_MASK 0x1
2e177a5c 117#define LOGICAL_LINK_STATUS_MASK 0x2
a8f447bd 118
3acf19d9 119/* When the event code of compl->flags is link-state, the mcc_compl
a8f447bd
SP		 120 * must be interpreted as follows
121 */
122struct be_async_event_link_state {
123 u8 physical_port;
124 u8 port_link_status;
125 u8 port_duplex;
126 u8 port_speed;
127 u8 port_fault;
128 u8 rsvd0[7];
3acf19d9 129 u32 flags;
a8f447bd
SP		 130} __packed;
131
3acf19d9 132/* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED
cc4ce020
SK		 133 * the mcc_compl must be interpreted as follows
134 */
135struct be_async_event_grp5_qos_link_speed {
136 u8 physical_port;
137 u8 rsvd[5];
138 u16 qos_link_speed;
139 u32 event_tag;
3acf19d9 140 u32 flags;
cc4ce020
SK		 141} __packed;
142
3acf19d9 143/* When the event code of compl->flags is GRP5 and event type is
cc4ce020
SK		 144 * CoS-Priority, the mcc_compl must be interpreted as follows
145 */
146struct be_async_event_grp5_cos_priority {
147 u8 physical_port;
148 u8 available_priority_bmap;
149 u8 reco_default_priority;
150 u8 valid;
151 u8 rsvd0;
152 u8 event_tag;
3acf19d9 153 u32 flags;
cc4ce020
SK		 154} __packed;
155
3acf19d9 156/* When the event code of compl->flags is GRP5 and event type is
3968fa1e
AK		 157 * PVID state, the mcc_compl must be interpreted as follows
158 */
159struct be_async_event_grp5_pvid_state {
160 u8 enabled;
161 u8 rsvd0;
162 u16 tag;
163 u32 event_tag;
164 u32 rsvd1;
3acf19d9 165 u32 flags;
3968fa1e
AK		 166} __packed;
167
bc0c3405
AK		 168/* async event indicating outer VLAN tag in QnQ */
169struct be_async_event_qnq {
170 u8 valid; /* Indicates if outer VLAN is valid */
171 u8 rsvd0;
172 u16 vlan_tag;
173 u32 event_tag;
174 u8 rsvd1[4];
3acf19d9 175 u32 flags;
bc0c3405
AK		 176} __packed;
177
21252377
VV		 178#define INCOMPATIBLE_SFP 0x3
179/* async event indicating misconfigured port */
180struct be_async_event_misconfig_port {
181 u32 event_data_word1;
182 u32 event_data_word2;
183 u32 rsvd0;
184 u32 flags;
185} __packed;
186
760c295e
VD		 187#define BMC_FILT_BROADCAST_ARP BIT(0)
188#define BMC_FILT_BROADCAST_DHCP_CLIENT BIT(1)
189#define BMC_FILT_BROADCAST_DHCP_SERVER BIT(2)
190#define BMC_FILT_BROADCAST_NET_BIOS BIT(3)
191#define BMC_FILT_BROADCAST BIT(7)
192#define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER BIT(8)
193#define BMC_FILT_MULTICAST_IPV6_RA BIT(9)
194#define BMC_FILT_MULTICAST_IPV6_RAS BIT(10)
195#define BMC_FILT_MULTICAST BIT(15)
196struct be_async_fw_control {
197 u32 event_data_word1;
198 u32 event_data_word2;
199 u32 evt_tag;
200 u32 event_data_word4;
201} __packed;
202
6b7c5b94
SP		 203struct be_mcc_mailbox {
204 struct be_mcc_wrb wrb;
efd2e40a 205 struct be_mcc_compl compl;
6b7c5b94
SP		 206};
207
208#define CMD_SUBSYSTEM_COMMON 0x1
209#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 210#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 211
212#define OPCODE_COMMON_NTWK_MAC_QUERY 1
213#define OPCODE_COMMON_NTWK_MAC_SET 2
214#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
215#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
216#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 217#define OPCODE_COMMON_READ_FLASHROM 6
84517482 218#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 219#define OPCODE_COMMON_CQ_CREATE 12
220#define OPCODE_COMMON_EQ_CREATE 13
cc4ce020 221#define OPCODE_COMMON_MCC_CREATE 21
e1d18735 222#define OPCODE_COMMON_SET_QOS 28
cc4ce020 223#define OPCODE_COMMON_MCC_CREATE_EXT 90
368c0ca2 224#define OPCODE_COMMON_SEEPROM_READ 30
9e1453c5 225#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
6b7c5b94
SP		 226#define OPCODE_COMMON_NTWK_RX_FILTER 34
227#define OPCODE_COMMON_GET_FW_VERSION 35
228#define OPCODE_COMMON_SET_FLOW_CONTROL 36
229#define OPCODE_COMMON_GET_FLOW_CONTROL 37
230#define OPCODE_COMMON_SET_FRAME_SIZE 39
231#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
232#define OPCODE_COMMON_FIRMWARE_CONFIG 42
233#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
234#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 235#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 236#define OPCODE_COMMON_CQ_DESTROY 54
237#define OPCODE_COMMON_EQ_DESTROY 55
238#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
239#define OPCODE_COMMON_NTWK_PMAC_ADD 59
240#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 241#define OPCODE_COMMON_FUNCTION_RESET 61
311fddc7 242#define OPCODE_COMMON_MANAGE_FAT 68
fad9ab2c
SB		 243#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
244#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 245#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
b4e32a71 246#define OPCODE_COMMON_GET_PORT_NAME 77
bdce2ad7 247#define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80
68c45a2d 248#define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
04a06028 249#define OPCODE_COMMON_SET_FN_PRIVILEGES 100
ee3cb629 250#define OPCODE_COMMON_GET_PHY_DETAILS 102
2e588f84 251#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
609ff3bb 252#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
941a77d5
SK		 253#define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
254#define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
590c391d
PR		 255#define OPCODE_COMMON_GET_MAC_LIST 147
256#define OPCODE_COMMON_SET_MAC_LIST 148
f1f3ee1b 257#define OPCODE_COMMON_GET_HSW_CONFIG 152
abb93951
PR		 258#define OPCODE_COMMON_GET_FUNC_CONFIG 160
259#define OPCODE_COMMON_GET_PROFILE_CONFIG 164
d5c18473 260#define OPCODE_COMMON_SET_PROFILE_CONFIG 165
542963b7 261#define OPCODE_COMMON_GET_ACTIVE_PROFILE 167
f1f3ee1b 262#define OPCODE_COMMON_SET_HSW_CONFIG 153
f25b119c 263#define OPCODE_COMMON_GET_FN_PRIVILEGES 170
de49bd5a 264#define OPCODE_COMMON_READ_OBJECT 171
485bf569 265#define OPCODE_COMMON_WRITE_OBJECT 172
f0613380 266#define OPCODE_COMMON_DELETE_OBJECT 174
a401801c 267#define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193
4c876616 268#define OPCODE_COMMON_GET_IFACE_LIST 194
dcf7ebba 269#define OPCODE_COMMON_ENABLE_DISABLE_VF 196
6b7c5b94 270
3abcdeda 271#define OPCODE_ETH_RSS_CONFIG 1
6b7c5b94
SP		 272#define OPCODE_ETH_ACPI_CONFIG 2
273#define OPCODE_ETH_PROMISCUOUS 3
274#define OPCODE_ETH_GET_STATISTICS 4
275#define OPCODE_ETH_TX_CREATE 7
276#define OPCODE_ETH_RX_CREATE 8
277#define OPCODE_ETH_TX_DESTROY 9
278#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 279#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
005d5696 280#define OPCODE_ETH_GET_PPORT_STATS 18
6b7c5b94 281
ff33a6e2
S		 282#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
283#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
fced9999 284#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
ff33a6e2 285
6b7c5b94
SP		 286struct be_cmd_req_hdr {
287 u8 opcode; /* dword 0 */
288 u8 subsystem; /* dword 0 */
289 u8 port_number; /* dword 0 */
290 u8 domain; /* dword 0 */
291 u32 timeout; /* dword 1 */
292 u32 request_length; /* dword 2 */
7b139c83 293 u8 version; /* dword 3 */
980df249 294 u8 rsvd[3]; /* dword 3 */
6b7c5b94
SP		 295};
296
297#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
298#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
299struct be_cmd_resp_hdr {
652bf646
PR		 300 u8 opcode; /* dword 0 */
301 u8 subsystem; /* dword 0 */
302 u8 rsvd[2]; /* dword 0 */
4c60005f
KA		 303 u8 base_status; /* dword 1 */
304 u8 addl_status; /* dword 1 */
652bf646 305 u8 rsvd1[2]; /* dword 1 */
6b7c5b94
SP		 306 u32 response_length; /* dword 2 */
307 u32 actual_resp_len; /* dword 3 */
308};
309
310struct phys_addr {
311 u32 lo;
312 u32 hi;
313};
314
315/**************************
316 * BE Command definitions *
317 **************************/
318
319/* Pseudo amap definition in which each bit of the actual structure is defined
320 * as a byte: used to calculate offset/shift/mask of each field */
321struct amap_eq_context {
322 u8 cidx[13]; /* dword 0*/
323 u8 rsvd0[3]; /* dword 0*/
324 u8 epidx[13]; /* dword 0*/
325 u8 valid; /* dword 0*/
326 u8 rsvd1; /* dword 0*/
327 u8 size; /* dword 0*/
328 u8 pidx[13]; /* dword 1*/
329 u8 rsvd2[3]; /* dword 1*/
330 u8 pd[10]; /* dword 1*/
331 u8 count[3]; /* dword 1*/
332 u8 solevent; /* dword 1*/
333 u8 stalled; /* dword 1*/
334 u8 armed; /* dword 1*/
335 u8 rsvd3[4]; /* dword 2*/
336 u8 func[8]; /* dword 2*/
337 u8 rsvd4; /* dword 2*/
338 u8 delaymult[10]; /* dword 2*/
339 u8 rsvd5[2]; /* dword 2*/
340 u8 phase[2]; /* dword 2*/
341 u8 nodelay; /* dword 2*/
342 u8 rsvd6[4]; /* dword 2*/
343 u8 rsvd7[32]; /* dword 3*/
344} __packed;
345
346struct be_cmd_req_eq_create {
347 struct be_cmd_req_hdr hdr;
348 u16 num_pages; /* sword */
349 u16 rsvd0; /* sword */
350 u8 context[sizeof(struct amap_eq_context) / 8];
351 struct phys_addr pages[8];
352} __packed;
353
354struct be_cmd_resp_eq_create {
355 struct be_cmd_resp_hdr resp_hdr;
356 u16 eq_id; /* sword */
f2f781a7 357 u16 msix_idx; /* available only in v2 */
6b7c5b94
SP		 358} __packed;
359
360/******************** Mac query ***************************/
361enum {
362 MAC_ADDRESS_TYPE_STORAGE = 0x0,
363 MAC_ADDRESS_TYPE_NETWORK = 0x1,
364 MAC_ADDRESS_TYPE_PD = 0x2,
365 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
366};
367
368struct mac_addr {
369 u16 size_of_struct;
370 u8 addr[ETH_ALEN];
371} __packed;
372
373struct be_cmd_req_mac_query {
374 struct be_cmd_req_hdr hdr;
375 u8 type;
376 u8 permanent;
377 u16 if_id;
590c391d 378 u32 pmac_id;
6b7c5b94
SP		 379} __packed;
380
381struct be_cmd_resp_mac_query {
382 struct be_cmd_resp_hdr hdr;
383 struct mac_addr mac;
384};
385
386/******************** PMac Add ***************************/
387struct be_cmd_req_pmac_add {
388 struct be_cmd_req_hdr hdr;
389 u32 if_id;
390 u8 mac_address[ETH_ALEN];
391 u8 rsvd0[2];
392} __packed;
393
394struct be_cmd_resp_pmac_add {
395 struct be_cmd_resp_hdr hdr;
396 u32 pmac_id;
397};
398
399/******************** PMac Del ***************************/
400struct be_cmd_req_pmac_del {
401 struct be_cmd_req_hdr hdr;
402 u32 if_id;
403 u32 pmac_id;
404};
405
406/******************** Create CQ ***************************/
407/* Pseudo amap definition in which each bit of the actual structure is defined
408 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 409struct amap_cq_context_be {
6b7c5b94
SP		 410 u8 cidx[11]; /* dword 0*/
411 u8 rsvd0; /* dword 0*/
412 u8 coalescwm[2]; /* dword 0*/
413 u8 nodelay; /* dword 0*/
414 u8 epidx[11]; /* dword 0*/
415 u8 rsvd1; /* dword 0*/
416 u8 count[2]; /* dword 0*/
417 u8 valid; /* dword 0*/
418 u8 solevent; /* dword 0*/
419 u8 eventable; /* dword 0*/
420 u8 pidx[11]; /* dword 1*/
421 u8 rsvd2; /* dword 1*/
422 u8 pd[10]; /* dword 1*/
423 u8 eqid[8]; /* dword 1*/
424 u8 stalled; /* dword 1*/
425 u8 armed; /* dword 1*/
426 u8 rsvd3[4]; /* dword 2*/
427 u8 func[8]; /* dword 2*/
428 u8 rsvd4[20]; /* dword 2*/
429 u8 rsvd5[32]; /* dword 3*/
430} __packed;
431
bbdc42f8 432struct amap_cq_context_v2 {
fe6d2a38
SP		 433 u8 rsvd0[12]; /* dword 0*/
434 u8 coalescwm[2]; /* dword 0*/
435 u8 nodelay; /* dword 0*/
436 u8 rsvd1[12]; /* dword 0*/
437 u8 count[2]; /* dword 0*/
438 u8 valid; /* dword 0*/
439 u8 rsvd2; /* dword 0*/
440 u8 eventable; /* dword 0*/
441 u8 eqid[16]; /* dword 1*/
442 u8 rsvd3[15]; /* dword 1*/
443 u8 armed; /* dword 1*/
444 u8 rsvd4[32]; /* dword 2*/
445 u8 rsvd5[32]; /* dword 3*/
446} __packed;
447
6b7c5b94
SP		 448struct be_cmd_req_cq_create {
449 struct be_cmd_req_hdr hdr;
450 u16 num_pages;
fe6d2a38
SP		 451 u8 page_size;
452 u8 rsvd0;
453 u8 context[sizeof(struct amap_cq_context_be) / 8];
6b7c5b94
SP		 454 struct phys_addr pages[8];
455} __packed;
456
fe6d2a38 457
6b7c5b94
SP		 458struct be_cmd_resp_cq_create {
459 struct be_cmd_resp_hdr hdr;
460 u16 cq_id;
461 u16 rsvd0;
462} __packed;
463
311fddc7
SK		 464struct be_cmd_req_get_fat {
465 struct be_cmd_req_hdr hdr;
466 u32 fat_operation;
467 u32 read_log_offset;
468 u32 read_log_length;
469 u32 data_buffer_size;
470 u32 data_buffer[1];
471} __packed;
472
473struct be_cmd_resp_get_fat {
474 struct be_cmd_resp_hdr hdr;
475 u32 log_size;
476 u32 read_log_length;
477 u32 rsvd[2];
478 u32 data_buffer[1];
479} __packed;
480
481
5fb379ee
SP		 482/******************** Create MCCQ ***************************/
483/* Pseudo amap definition in which each bit of the actual structure is defined
484 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 485struct amap_mcc_context_be {
5fb379ee
SP		 486 u8 con_index[14];
487 u8 rsvd0[2];
488 u8 ring_size[4];
489 u8 fetch_wrb;
490 u8 fetch_r2t;
491 u8 cq_id[10];
492 u8 prod_index[14];
493 u8 fid[8];
494 u8 pdid[9];
495 u8 valid;
496 u8 rsvd1[32];
497 u8 rsvd2[32];
498} __packed;
499
666d39c7 500struct amap_mcc_context_v1 {
fe6d2a38
SP		 501 u8 async_cq_id[16];
502 u8 ring_size[4];
503 u8 rsvd0[12];
504 u8 rsvd1[31];
505 u8 valid;
506 u8 async_cq_valid[1];
507 u8 rsvd2[31];
508 u8 rsvd3[32];
509} __packed;
510
5fb379ee 511struct be_cmd_req_mcc_create {
34b1ef04
SK		 512 struct be_cmd_req_hdr hdr;
513 u16 num_pages;
514 u16 cq_id;
515 u8 context[sizeof(struct amap_mcc_context_be) / 8];
516 struct phys_addr pages[8];
517} __packed;
518
519struct be_cmd_req_mcc_ext_create {
5fb379ee
SP		 520 struct be_cmd_req_hdr hdr;
521 u16 num_pages;
fe6d2a38 522 u16 cq_id;
cc4ce020 523 u32 async_event_bitmap[1];
666d39c7 524 u8 context[sizeof(struct amap_mcc_context_v1) / 8];
5fb379ee
SP		 525 struct phys_addr pages[8];
526} __packed;
527
528struct be_cmd_resp_mcc_create {
529 struct be_cmd_resp_hdr hdr;
530 u16 id;
531 u16 rsvd0;
532} __packed;
533
6b7c5b94
SP		 534/******************** Create TxQ ***************************/
535#define BE_ETH_TX_RING_TYPE_STANDARD 2
536#define BE_ULP1_NUM 1
537
6b7c5b94
SP		 538struct be_cmd_req_eth_tx_create {
539 struct be_cmd_req_hdr hdr;
540 u8 num_pages;
541 u8 ulp_num;
94d73aaa
VV		 542 u16 type;
543 u16 if_id;
544 u8 queue_size;
545 u8 rsvd0;
546 u32 rsvd1;
547 u16 cq_id;
548 u16 rsvd2;
549 u32 rsvd3[13];
6b7c5b94
SP		 550 struct phys_addr pages[8];
551} __packed;
552
553struct be_cmd_resp_eth_tx_create {
554 struct be_cmd_resp_hdr hdr;
555 u16 cid;
94d73aaa
VV		 556 u16 rid;
557 u32 db_offset;
558 u32 rsvd0[4];
6b7c5b94
SP		 559} __packed;
560
561/******************** Create RxQ ***************************/
562struct be_cmd_req_eth_rx_create {
563 struct be_cmd_req_hdr hdr;
564 u16 cq_id;
565 u8 frag_size;
566 u8 num_pages;
567 struct phys_addr pages[2];
568 u32 interface_id;
569 u16 max_frame_size;
570 u16 rsvd0;
571 u32 rss_queue;
572} __packed;
573
574struct be_cmd_resp_eth_rx_create {
575 struct be_cmd_resp_hdr hdr;
576 u16 id;
3abcdeda 577 u8 rss_id;
6b7c5b94
SP		 578 u8 rsvd0;
579} __packed;
580
581/******************** Q Destroy ***************************/
582/* Type of Queue to be destroyed */
583enum {
584 QTYPE_EQ = 1,
585 QTYPE_CQ,
586 QTYPE_TXQ,
5fb379ee
SP		 587 QTYPE_RXQ,
588 QTYPE_MCCQ
6b7c5b94
SP		 589};
590
591struct be_cmd_req_q_destroy {
592 struct be_cmd_req_hdr hdr;
593 u16 id;
594 u16 bypass_flush; /* valid only for rx q destroy */
595} __packed;
596
597/************ I/f Create (it's actually I/f Config Create)**********/
598
599/* Capability flags for the i/f */
600enum be_if_flags {
601 BE_IF_FLAGS_RSS = 0x4,
602 BE_IF_FLAGS_PROMISCUOUS = 0x8,
603 BE_IF_FLAGS_BROADCAST = 0x10,
604 BE_IF_FLAGS_UNTAGGED = 0x20,
605 BE_IF_FLAGS_ULP = 0x40,
606 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
607 BE_IF_FLAGS_VLAN = 0x100,
608 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
609 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
f21b538c 610 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
71bb8bd0
VV		 611 BE_IF_FLAGS_MULTICAST = 0x1000,
612 BE_IF_FLAGS_DEFQ_RSS = 0x1000000
6b7c5b94
SP		 613};
614
3da988c9
SB		 615#define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\
616 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\
617 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\
618 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\
71bb8bd0 619 BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_DEFQ_RSS)
3da988c9 620
ac34b743
SP		 621#define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \
622 BE_IF_FLAGS_VLAN_PROMISCUOUS |\
623 BE_IF_FLAGS_MCAST_PROMISCUOUS)
624
c1bb0a55
VD		 625#define BE_IF_FILT_FLAGS_BASIC (BE_IF_FLAGS_BROADCAST | \
626 BE_IF_FLAGS_PASS_L3L4_ERRORS | \
627 BE_IF_FLAGS_UNTAGGED)
bcc84140 628
c1bb0a55
VD		 629#define BE_IF_ALL_FILT_FLAGS (BE_IF_FILT_FLAGS_BASIC | \
630 BE_IF_FLAGS_MULTICAST | \
631 BE_IF_FLAGS_ALL_PROMISCUOUS)
bcc84140 632
6b7c5b94
SP		 633/* An RX interface is an object with one or more MAC addresses and
634 * filtering capabilities. */
635struct be_cmd_req_if_create {
636 struct be_cmd_req_hdr hdr;
af901ca1 637 u32 version; /* ignore currently */
6b7c5b94
SP		 638 u32 capability_flags;
639 u32 enable_flags;
640 u8 mac_addr[ETH_ALEN];
641 u8 rsvd0;
642 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
643 u32 vlan_tag; /* not used currently */
644} __packed;
645
646struct be_cmd_resp_if_create {
647 struct be_cmd_resp_hdr hdr;
648 u32 interface_id;
649 u32 pmac_id;
650};
651
652/****** I/f Destroy(it's actually I/f Config Destroy )**********/
653struct be_cmd_req_if_destroy {
654 struct be_cmd_req_hdr hdr;
655 u32 interface_id;
656};
657
658/*************** HW Stats Get **********************************/
89a88ab8 659struct be_port_rxf_stats_v0 {
6b7c5b94
SP		 660 u32 rx_bytes_lsd; /* dword 0*/
661 u32 rx_bytes_msd; /* dword 1*/
662 u32 rx_total_frames; /* dword 2*/
663 u32 rx_unicast_frames; /* dword 3*/
664 u32 rx_multicast_frames; /* dword 4*/
665 u32 rx_broadcast_frames; /* dword 5*/
666 u32 rx_crc_errors; /* dword 6*/
667 u32 rx_alignment_symbol_errors; /* dword 7*/
668 u32 rx_pause_frames; /* dword 8*/
669 u32 rx_control_frames; /* dword 9*/
670 u32 rx_in_range_errors; /* dword 10*/
671 u32 rx_out_range_errors; /* dword 11*/
672 u32 rx_frame_too_long; /* dword 12*/
18fb06a1
SR		 673 u32 rx_address_filtered; /* dword 13*/
674 u32 rx_vlan_filtered; /* dword 14*/
6b7c5b94
SP		 675 u32 rx_dropped_too_small; /* dword 15*/
676 u32 rx_dropped_too_short; /* dword 16*/
677 u32 rx_dropped_header_too_small; /* dword 17*/
678 u32 rx_dropped_tcp_length; /* dword 18*/
679 u32 rx_dropped_runt; /* dword 19*/
680 u32 rx_64_byte_packets; /* dword 20*/
681 u32 rx_65_127_byte_packets; /* dword 21*/
682 u32 rx_128_256_byte_packets; /* dword 22*/
683 u32 rx_256_511_byte_packets; /* dword 23*/
684 u32 rx_512_1023_byte_packets; /* dword 24*/
685 u32 rx_1024_1518_byte_packets; /* dword 25*/
686 u32 rx_1519_2047_byte_packets; /* dword 26*/
687 u32 rx_2048_4095_byte_packets; /* dword 27*/
688 u32 rx_4096_8191_byte_packets; /* dword 28*/
689 u32 rx_8192_9216_byte_packets; /* dword 29*/
690 u32 rx_ip_checksum_errs; /* dword 30*/
691 u32 rx_tcp_checksum_errs; /* dword 31*/
692 u32 rx_udp_checksum_errs; /* dword 32*/
693 u32 rx_non_rss_packets; /* dword 33*/
694 u32 rx_ipv4_packets; /* dword 34*/
695 u32 rx_ipv6_packets; /* dword 35*/
696 u32 rx_ipv4_bytes_lsd; /* dword 36*/
697 u32 rx_ipv4_bytes_msd; /* dword 37*/
698 u32 rx_ipv6_bytes_lsd; /* dword 38*/
699 u32 rx_ipv6_bytes_msd; /* dword 39*/
700 u32 rx_chute1_packets; /* dword 40*/
701 u32 rx_chute2_packets; /* dword 41*/
702 u32 rx_chute3_packets; /* dword 42*/
703 u32 rx_management_packets; /* dword 43*/
704 u32 rx_switched_unicast_packets; /* dword 44*/
705 u32 rx_switched_multicast_packets; /* dword 45*/
706 u32 rx_switched_broadcast_packets; /* dword 46*/
707 u32 tx_bytes_lsd; /* dword 47*/
708 u32 tx_bytes_msd; /* dword 48*/
709 u32 tx_unicastframes; /* dword 49*/
710 u32 tx_multicastframes; /* dword 50*/
711 u32 tx_broadcastframes; /* dword 51*/
712 u32 tx_pauseframes; /* dword 52*/
713 u32 tx_controlframes; /* dword 53*/
714 u32 tx_64_byte_packets; /* dword 54*/
715 u32 tx_65_127_byte_packets; /* dword 55*/
716 u32 tx_128_256_byte_packets; /* dword 56*/
717 u32 tx_256_511_byte_packets; /* dword 57*/
718 u32 tx_512_1023_byte_packets; /* dword 58*/
719 u32 tx_1024_1518_byte_packets; /* dword 59*/
720 u32 tx_1519_2047_byte_packets; /* dword 60*/
721 u32 tx_2048_4095_byte_packets; /* dword 61*/
722 u32 tx_4096_8191_byte_packets; /* dword 62*/
723 u32 tx_8192_9216_byte_packets; /* dword 63*/
724 u32 rx_fifo_overflow; /* dword 64*/
725 u32 rx_input_fifo_overflow; /* dword 65*/
726};
727
89a88ab8
AK		 728struct be_rxf_stats_v0 {
729 struct be_port_rxf_stats_v0 port[2];
6b7c5b94
SP		 730 u32 rx_drops_no_pbuf; /* dword 132*/
731 u32 rx_drops_no_txpb; /* dword 133*/
732 u32 rx_drops_no_erx_descr; /* dword 134*/
733 u32 rx_drops_no_tpre_descr; /* dword 135*/
734 u32 management_rx_port_packets; /* dword 136*/
735 u32 management_rx_port_bytes; /* dword 137*/
736 u32 management_rx_port_pause_frames; /* dword 138*/
737 u32 management_rx_port_errors; /* dword 139*/
738 u32 management_tx_port_packets; /* dword 140*/
739 u32 management_tx_port_bytes; /* dword 141*/
740 u32 management_tx_port_pause; /* dword 142*/
741 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
742 u32 rx_drops_too_many_frags; /* dword 144*/
743 u32 rx_drops_invalid_ring; /* dword 145*/
744 u32 forwarded_packets; /* dword 146*/
745 u32 rx_drops_mtu; /* dword 147*/
f6c4bf3e
AK		 746 u32 rsvd0[7];
747 u32 port0_jabber_events;
748 u32 port1_jabber_events;
749 u32 rsvd1[6];
6b7c5b94
SP		 750};
751
89a88ab8 752struct be_erx_stats_v0 {
6b7c5b94 753 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
89a88ab8 754 u32 rsvd[4];
6b7c5b94
SP		 755};
756
f6c4bf3e
AK		 757struct be_pmem_stats {
758 u32 eth_red_drops;
89a88ab8 759 u32 rsvd[5];
f6c4bf3e
AK		 760};
761
89a88ab8
AK		 762struct be_hw_stats_v0 {
763 struct be_rxf_stats_v0 rxf;
6b7c5b94 764 u32 rsvd[48];
89a88ab8 765 struct be_erx_stats_v0 erx;
f6c4bf3e 766 struct be_pmem_stats pmem;
6b7c5b94
SP		 767};
768
89a88ab8 769struct be_cmd_req_get_stats_v0 {
6b7c5b94 770 struct be_cmd_req_hdr hdr;
89a88ab8 771 u8 rsvd[sizeof(struct be_hw_stats_v0)];
6b7c5b94
SP		 772};
773
89a88ab8 774struct be_cmd_resp_get_stats_v0 {
6b7c5b94 775 struct be_cmd_resp_hdr hdr;
89a88ab8 776 struct be_hw_stats_v0 hw_stats;
6b7c5b94
SP		 777};
778
ac124ff9 779struct lancer_pport_stats {
005d5696
SX		 780 u32 tx_packets_lo;
781 u32 tx_packets_hi;
782 u32 tx_unicast_packets_lo;
783 u32 tx_unicast_packets_hi;
784 u32 tx_multicast_packets_lo;
785 u32 tx_multicast_packets_hi;
786 u32 tx_broadcast_packets_lo;
787 u32 tx_broadcast_packets_hi;
788 u32 tx_bytes_lo;
789 u32 tx_bytes_hi;
790 u32 tx_unicast_bytes_lo;
791 u32 tx_unicast_bytes_hi;
792 u32 tx_multicast_bytes_lo;
793 u32 tx_multicast_bytes_hi;
794 u32 tx_broadcast_bytes_lo;
795 u32 tx_broadcast_bytes_hi;
796 u32 tx_discards_lo;
797 u32 tx_discards_hi;
798 u32 tx_errors_lo;
799 u32 tx_errors_hi;
800 u32 tx_pause_frames_lo;
801 u32 tx_pause_frames_hi;
802 u32 tx_pause_on_frames_lo;
803 u32 tx_pause_on_frames_hi;
804 u32 tx_pause_off_frames_lo;
805 u32 tx_pause_off_frames_hi;
806 u32 tx_internal_mac_errors_lo;
807 u32 tx_internal_mac_errors_hi;
808 u32 tx_control_frames_lo;
809 u32 tx_control_frames_hi;
810 u32 tx_packets_64_bytes_lo;
811 u32 tx_packets_64_bytes_hi;
812 u32 tx_packets_65_to_127_bytes_lo;
813 u32 tx_packets_65_to_127_bytes_hi;
814 u32 tx_packets_128_to_255_bytes_lo;
815 u32 tx_packets_128_to_255_bytes_hi;
816 u32 tx_packets_256_to_511_bytes_lo;
817 u32 tx_packets_256_to_511_bytes_hi;
818 u32 tx_packets_512_to_1023_bytes_lo;
819 u32 tx_packets_512_to_1023_bytes_hi;
820 u32 tx_packets_1024_to_1518_bytes_lo;
821 u32 tx_packets_1024_to_1518_bytes_hi;
822 u32 tx_packets_1519_to_2047_bytes_lo;
823 u32 tx_packets_1519_to_2047_bytes_hi;
824 u32 tx_packets_2048_to_4095_bytes_lo;
825 u32 tx_packets_2048_to_4095_bytes_hi;
826 u32 tx_packets_4096_to_8191_bytes_lo;
827 u32 tx_packets_4096_to_8191_bytes_hi;
828 u32 tx_packets_8192_to_9216_bytes_lo;
829 u32 tx_packets_8192_to_9216_bytes_hi;
830 u32 tx_lso_packets_lo;
831 u32 tx_lso_packets_hi;
832 u32 rx_packets_lo;
833 u32 rx_packets_hi;
834 u32 rx_unicast_packets_lo;
835 u32 rx_unicast_packets_hi;
836 u32 rx_multicast_packets_lo;
837 u32 rx_multicast_packets_hi;
838 u32 rx_broadcast_packets_lo;
839 u32 rx_broadcast_packets_hi;
840 u32 rx_bytes_lo;
841 u32 rx_bytes_hi;
842 u32 rx_unicast_bytes_lo;
843 u32 rx_unicast_bytes_hi;
844 u32 rx_multicast_bytes_lo;
845 u32 rx_multicast_bytes_hi;
846 u32 rx_broadcast_bytes_lo;
847 u32 rx_broadcast_bytes_hi;
848 u32 rx_unknown_protos;
849 u32 rsvd_69; /* Word 69 is reserved */
850 u32 rx_discards_lo;
851 u32 rx_discards_hi;
852 u32 rx_errors_lo;
853 u32 rx_errors_hi;
854 u32 rx_crc_errors_lo;
855 u32 rx_crc_errors_hi;
856 u32 rx_alignment_errors_lo;
857 u32 rx_alignment_errors_hi;
858 u32 rx_symbol_errors_lo;
859 u32 rx_symbol_errors_hi;
860 u32 rx_pause_frames_lo;
861 u32 rx_pause_frames_hi;
862 u32 rx_pause_on_frames_lo;
863 u32 rx_pause_on_frames_hi;
864 u32 rx_pause_off_frames_lo;
865 u32 rx_pause_off_frames_hi;
866 u32 rx_frames_too_long_lo;
867 u32 rx_frames_too_long_hi;
868 u32 rx_internal_mac_errors_lo;
869 u32 rx_internal_mac_errors_hi;
870 u32 rx_undersize_packets;
871 u32 rx_oversize_packets;
872 u32 rx_fragment_packets;
873 u32 rx_jabbers;
874 u32 rx_control_frames_lo;
875 u32 rx_control_frames_hi;
876 u32 rx_control_frames_unknown_opcode_lo;
877 u32 rx_control_frames_unknown_opcode_hi;
878 u32 rx_in_range_errors;
879 u32 rx_out_of_range_errors;
18fb06a1
SR		 880 u32 rx_address_filtered;
881 u32 rx_vlan_filtered;
005d5696
SX		 882 u32 rx_dropped_too_small;
883 u32 rx_dropped_too_short;
884 u32 rx_dropped_header_too_small;
885 u32 rx_dropped_invalid_tcp_length;
886 u32 rx_dropped_runt;
887 u32 rx_ip_checksum_errors;
888 u32 rx_tcp_checksum_errors;
889 u32 rx_udp_checksum_errors;
890 u32 rx_non_rss_packets;
891 u32 rsvd_111;
892 u32 rx_ipv4_packets_lo;
893 u32 rx_ipv4_packets_hi;
894 u32 rx_ipv6_packets_lo;
895 u32 rx_ipv6_packets_hi;
896 u32 rx_ipv4_bytes_lo;
897 u32 rx_ipv4_bytes_hi;
898 u32 rx_ipv6_bytes_lo;
899 u32 rx_ipv6_bytes_hi;
900 u32 rx_nic_packets_lo;
901 u32 rx_nic_packets_hi;
902 u32 rx_tcp_packets_lo;
903 u32 rx_tcp_packets_hi;
904 u32 rx_iscsi_packets_lo;
905 u32 rx_iscsi_packets_hi;
906 u32 rx_management_packets_lo;
907 u32 rx_management_packets_hi;
908 u32 rx_switched_unicast_packets_lo;
909 u32 rx_switched_unicast_packets_hi;
910 u32 rx_switched_multicast_packets_lo;
911 u32 rx_switched_multicast_packets_hi;
912 u32 rx_switched_broadcast_packets_lo;
913 u32 rx_switched_broadcast_packets_hi;
914 u32 num_forwards_lo;
915 u32 num_forwards_hi;
916 u32 rx_fifo_overflow;
917 u32 rx_input_fifo_overflow;
918 u32 rx_drops_too_many_frags_lo;
919 u32 rx_drops_too_many_frags_hi;
920 u32 rx_drops_invalid_queue;
921 u32 rsvd_141;
922 u32 rx_drops_mtu_lo;
923 u32 rx_drops_mtu_hi;
924 u32 rx_packets_64_bytes_lo;
925 u32 rx_packets_64_bytes_hi;
926 u32 rx_packets_65_to_127_bytes_lo;
927 u32 rx_packets_65_to_127_bytes_hi;
928 u32 rx_packets_128_to_255_bytes_lo;
929 u32 rx_packets_128_to_255_bytes_hi;
930 u32 rx_packets_256_to_511_bytes_lo;
931 u32 rx_packets_256_to_511_bytes_hi;
932 u32 rx_packets_512_to_1023_bytes_lo;
933 u32 rx_packets_512_to_1023_bytes_hi;
934 u32 rx_packets_1024_to_1518_bytes_lo;
935 u32 rx_packets_1024_to_1518_bytes_hi;
936 u32 rx_packets_1519_to_2047_bytes_lo;
937 u32 rx_packets_1519_to_2047_bytes_hi;
938 u32 rx_packets_2048_to_4095_bytes_lo;
939 u32 rx_packets_2048_to_4095_bytes_hi;
940 u32 rx_packets_4096_to_8191_bytes_lo;
941 u32 rx_packets_4096_to_8191_bytes_hi;
942 u32 rx_packets_8192_to_9216_bytes_lo;
943 u32 rx_packets_8192_to_9216_bytes_hi;
944};
945
946struct pport_stats_params {
947 u16 pport_num;
948 u8 rsvd;
949 u8 reset_stats;
950};
951
952struct lancer_cmd_req_pport_stats {
953 struct be_cmd_req_hdr hdr;
954 union {
955 struct pport_stats_params params;
ac124ff9 956 u8 rsvd[sizeof(struct lancer_pport_stats)];
005d5696
SX		 957 } cmd_params;
958};
959
960struct lancer_cmd_resp_pport_stats {
961 struct be_cmd_resp_hdr hdr;
ac124ff9 962 struct lancer_pport_stats pport_stats;
005d5696
SX		 963};
964
ac124ff9 965static inline struct lancer_pport_stats*
005d5696
SX		 966 pport_stats_from_cmd(struct be_adapter *adapter)
967{
968 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
969 return &cmd->pport_stats;
970}
971
609ff3bb
AK		 972struct be_cmd_req_get_cntl_addnl_attribs {
973 struct be_cmd_req_hdr hdr;
974 u8 rsvd[8];
975};
976
977struct be_cmd_resp_get_cntl_addnl_attribs {
978 struct be_cmd_resp_hdr hdr;
979 u16 ipl_file_number;
980 u8 ipl_file_version;
981 u8 rsvd0;
982 u8 on_die_temperature; /* in degrees centigrade*/
983 u8 rsvd1[3];
984};
985
6b7c5b94
SP		 986struct be_cmd_req_vlan_config {
987 struct be_cmd_req_hdr hdr;
988 u8 interface_id;
989 u8 promiscuous;
990 u8 untagged;
991 u8 num_vlan;
992 u16 normal_vlan[64];
993} __packed;
994
5b8821b7 995/******************* RX FILTER ******************************/
e7b909a6 996#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 997struct macaddr {
998 u8 byte[ETH_ALEN];
999};
1000
ecd0bf0f
PR		 1001struct be_cmd_req_rx_filter {
1002 struct be_cmd_req_hdr hdr;
1003 u32 global_flags_mask;
1004 u32 global_flags;
1005 u32 if_flags_mask;
1006 u32 if_flags;
1007 u32 if_id;
5b8821b7
SP		 1008 u32 mcast_num;
1009 struct macaddr mcast_mac[BE_MAX_MC];
ecd0bf0f
PR		 1010};
1011
6b7c5b94
SP		 1012/******************** Link Status Query *******************/
1013struct be_cmd_req_link_status {
1014 struct be_cmd_req_hdr hdr;
1015 u32 rsvd;
1016};
1017
6b7c5b94
SP		 1018enum {
1019 PHY_LINK_DUPLEX_NONE = 0x0,
1020 PHY_LINK_DUPLEX_HALF = 0x1,
1021 PHY_LINK_DUPLEX_FULL = 0x2
1022};
1023
1024enum {
1025 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
1026 PHY_LINK_SPEED_10MBPS = 0x1,
1027 PHY_LINK_SPEED_100MBPS = 0x2,
1028 PHY_LINK_SPEED_1GBPS = 0x3,
b971f847
VV		 1029 PHY_LINK_SPEED_10GBPS = 0x4,
1030 PHY_LINK_SPEED_20GBPS = 0x5,
1031 PHY_LINK_SPEED_25GBPS = 0x6,
1032 PHY_LINK_SPEED_40GBPS = 0x7
6b7c5b94
SP		 1033};
1034
1035struct be_cmd_resp_link_status {
1036 struct be_cmd_resp_hdr hdr;
1037 u8 physical_port;
1038 u8 mac_duplex;
1039 u8 mac_speed;
1040 u8 mac_fault;
1041 u8 mgmt_mac_duplex;
1042 u8 mgmt_mac_speed;
0388f251 1043 u16 link_speed;
b236916a
AK		 1044 u8 logical_link_status;
1045 u8 rsvd1[3];
6b7c5b94
SP		 1046} __packed;
1047
0388f251
SB		 1048/******************** Port Identification ***************************/
1049/* Identifies the type of port attached to NIC */
1050struct be_cmd_req_port_type {
1051 struct be_cmd_req_hdr hdr;
72d7e2bf
SR		 1052 __le32 page_num;
1053 __le32 port;
0388f251
SB		 1054};
1055
1056enum {
1057 TR_PAGE_A0 = 0xa0,
1058 TR_PAGE_A2 = 0xa2
1059};
1060
6809cee0
RN		 1061/* From SFF-8436 QSFP+ spec */
1062#define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83
1063#define QSFP_PLUS_CR4_CABLE 0x8
1064#define QSFP_PLUS_SR4_CABLE 0x4
1065#define QSFP_PLUS_LR4_CABLE 0x2
1066
e36edd9d 1067/* From SFF-8472 spec */
6809cee0
RN		 1068#define SFP_PLUS_SFF_8472_COMP 0x5E
1069#define SFP_PLUS_CABLE_TYPE_OFFSET 0x8
1070#define SFP_PLUS_COPPER_CABLE 0x4
21252377
VV		 1071#define SFP_VENDOR_NAME_OFFSET 0x14
1072#define SFP_VENDOR_PN_OFFSET 0x28
e36edd9d
ML		 1073
1074#define PAGE_DATA_LEN 256
0388f251
SB		 1075struct be_cmd_resp_port_type {
1076 struct be_cmd_resp_hdr hdr;
1077 u32 page_num;
1078 u32 port;
e36edd9d 1079 u8 page_data[PAGE_DATA_LEN];
0388f251
SB		 1080};
1081
6b7c5b94 1082/******************** Get FW Version *******************/
6b7c5b94
SP		 1083struct be_cmd_req_get_fw_version {
1084 struct be_cmd_req_hdr hdr;
1085 u8 rsvd0[FW_VER_LEN];
1086 u8 rsvd1[FW_VER_LEN];
1087} __packed;
1088
1089struct be_cmd_resp_get_fw_version {
1090 struct be_cmd_resp_hdr hdr;
1091 u8 firmware_version_string[FW_VER_LEN];
1092 u8 fw_on_flash_version_string[FW_VER_LEN];
1093} __packed;
1094
1095/******************** Set Flow Contrl *******************/
1096struct be_cmd_req_set_flow_control {
1097 struct be_cmd_req_hdr hdr;
1098 u16 tx_flow_control;
1099 u16 rx_flow_control;
1100} __packed;
1101
1102/******************** Get Flow Contrl *******************/
1103struct be_cmd_req_get_flow_control {
1104 struct be_cmd_req_hdr hdr;
1105 u32 rsvd;
1106};
1107
1108struct be_cmd_resp_get_flow_control {
1109 struct be_cmd_resp_hdr hdr;
1110 u16 tx_flow_control;
1111 u16 rx_flow_control;
1112} __packed;
1113
1114/******************** Modify EQ Delay *******************/
2632bafd
SP		 1115struct be_set_eqd {
1116 u32 eq_id;
1117 u32 phase;
1118 u32 delay_multiplier;
1119};
1120
6b7c5b94
SP		 1121struct be_cmd_req_modify_eq_delay {
1122 struct be_cmd_req_hdr hdr;
1123 u32 num_eq;
2632bafd 1124 struct be_set_eqd set_eqd[MAX_EVT_QS];
6b7c5b94
SP		 1125} __packed;
1126
6b7c5b94 1127/******************** Get FW Config *******************/
752961a1
SP		 1128/* The HW can come up in either of the following multi-channel modes
1129 * based on the skew/IPL.
1130 */
045508a8 1131#define RDMA_ENABLED 0x4
66064dbc 1132#define QNQ_MODE 0x400
752961a1
SP		 1133#define VNIC_MODE 0x20000
1134#define UMC_ENABLED 0x1000000
6b7c5b94
SP		 1135struct be_cmd_req_query_fw_cfg {
1136 struct be_cmd_req_hdr hdr;
3abcdeda 1137 u32 rsvd[31];
6b7c5b94
SP		 1138};
1139
1140struct be_cmd_resp_query_fw_cfg {
1141 struct be_cmd_resp_hdr hdr;
1142 u32 be_config_number;
1143 u32 asic_revision;
1144 u32 phys_port;
3486be29 1145 u32 function_mode;
6b7c5b94 1146 u32 rsvd[26];
3abcdeda
SP		 1147 u32 function_caps;
1148};
1149
73dea398
PR		 1150/******************** RSS Config ****************************************/
1151/* RSS type Input parameters used to compute RX hash
1152 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1153 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1154 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1155 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1156 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1157 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1158 *
1159 * When multiple RSS types are enabled, HW picks the best hash policy
1160 * based on the type of the received packet.
1161 */
3abcdeda
SP		 1162#define RSS_ENABLE_NONE 0x0
1163#define RSS_ENABLE_IPV4 0x1
1164#define RSS_ENABLE_TCP_IPV4 0x2
1165#define RSS_ENABLE_IPV6 0x4
1166#define RSS_ENABLE_TCP_IPV6 0x8
d3bd3a5e
PR		 1167#define RSS_ENABLE_UDP_IPV4 0x10
1168#define RSS_ENABLE_UDP_IPV6 0x20
3abcdeda 1169
594ad54a
SR		 1170#define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1171#define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1172
3abcdeda
SP		 1173struct be_cmd_req_rss_config {
1174 struct be_cmd_req_hdr hdr;
1175 u32 if_id;
1176 u16 enable_rss;
1177 u16 cpu_table_size_log2;
1178 u32 hash[10];
1179 u8 cpu_table[128];
1180 u8 flush;
1181 u8 rsvd0[3];
6b7c5b94
SP		 1182};
1183
fad9ab2c
SB		 1184/******************** Port Beacon ***************************/
1185
1186#define BEACON_STATE_ENABLED 0x1
1187#define BEACON_STATE_DISABLED 0x0
1188
1189struct be_cmd_req_enable_disable_beacon {
1190 struct be_cmd_req_hdr hdr;
1191 u8 port_num;
1192 u8 beacon_state;
1193 u8 beacon_duration;
1194 u8 status_duration;
1195} __packed;
1196
fad9ab2c
SB		 1197struct be_cmd_req_get_beacon_state {
1198 struct be_cmd_req_hdr hdr;
1199 u8 port_num;
1200 u8 rsvd0;
1201 u16 rsvd1;
1202} __packed;
1203
1204struct be_cmd_resp_get_beacon_state {
1205 struct be_cmd_resp_hdr resp_hdr;
1206 u8 beacon_state;
1207 u8 rsvd0[3];
1208} __packed;
1209
e02cfd96
VV		 1210/* Flashrom related descriptors */
1211#define MAX_FLASH_COMP 32
1212
8836ff48
SR		 1213/* Optypes of each component in the UFI */
1214enum {
1215 OPTYPE_ISCSI_ACTIVE = 0,
1216 OPTYPE_REDBOOT = 1,
1217 OPTYPE_BIOS = 2,
1218 OPTYPE_PXE_BIOS = 3,
1219 OPTYPE_OFFSET_SPECIFIED = 7,
1220 OPTYPE_FCOE_BIOS = 8,
1221 OPTYPE_ISCSI_BACKUP = 9,
1222 OPTYPE_FCOE_FW_ACTIVE = 10,
1223 OPTYPE_FCOE_FW_BACKUP = 11,
1224 OPTYPE_NCSI_FW = 13,
1225 OPTYPE_REDBOOT_DIR = 18,
1226 OPTYPE_REDBOOT_CONFIG = 19,
1227 OPTYPE_SH_PHY_FW = 21,
1228 OPTYPE_FLASHISM_JUMPVECTOR = 22,
1229 OPTYPE_UFI_DIR = 23,
1230 OPTYPE_PHY_FW = 99
1231};
1232
1233/* Maximum sizes of components in BE2 FW UFI */
1234enum {
1235 BE2_BIOS_COMP_MAX_SIZE = 0x40000,
1236 BE2_REDBOOT_COMP_MAX_SIZE = 0x40000,
1237 BE2_COMP_MAX_SIZE = 0x140000
1238};
1239
1240/* Maximum sizes of components in BE3 FW UFI */
1241enum {
1242 BE3_NCSI_COMP_MAX_SIZE = 0x40000,
1243 BE3_PHY_FW_COMP_MAX_SIZE = 0x40000,
1244 BE3_BIOS_COMP_MAX_SIZE = 0x80000,
1245 BE3_REDBOOT_COMP_MAX_SIZE = 0x100000,
1246 BE3_COMP_MAX_SIZE = 0x200000
1247};
1248
1249/* Offsets for components in BE2 FW UFI */
1250enum {
1251 BE2_REDBOOT_START = 0x8000,
1252 BE2_FCOE_BIOS_START = 0x80000,
1253 BE2_ISCSI_PRIMARY_IMAGE_START = 0x100000,
1254 BE2_ISCSI_BACKUP_IMAGE_START = 0x240000,
1255 BE2_FCOE_PRIMARY_IMAGE_START = 0x380000,
1256 BE2_FCOE_BACKUP_IMAGE_START = 0x4c0000,
1257 BE2_ISCSI_BIOS_START = 0x700000,
1258 BE2_PXE_BIOS_START = 0x780000
1259};
1260
1261/* Offsets for components in BE3 FW UFI */
1262enum {
1263 BE3_REDBOOT_START = 0x40000,
1264 BE3_PHY_FW_START = 0x140000,
1265 BE3_ISCSI_PRIMARY_IMAGE_START = 0x200000,
1266 BE3_ISCSI_BACKUP_IMAGE_START = 0x400000,
1267 BE3_FCOE_PRIMARY_IMAGE_START = 0x600000,
1268 BE3_FCOE_BACKUP_IMAGE_START = 0x800000,
1269 BE3_ISCSI_BIOS_START = 0xc00000,
1270 BE3_PXE_BIOS_START = 0xc80000,
1271 BE3_FCOE_BIOS_START = 0xd00000,
1272 BE3_NCSI_START = 0xf40000
1273};
1274
1275/* Component entry types */
1276enum {
1277 IMAGE_NCSI = 0x10,
1278 IMAGE_OPTION_ROM_PXE = 0x20,
1279 IMAGE_OPTION_ROM_FCOE = 0x21,
1280 IMAGE_OPTION_ROM_ISCSI = 0x22,
1281 IMAGE_FLASHISM_JUMPVECTOR = 0x30,
1282 IMAGE_FIRMWARE_ISCSI = 0xa0,
1283 IMAGE_FIRMWARE_FCOE = 0xa2,
1284 IMAGE_FIRMWARE_BACKUP_ISCSI = 0xb0,
1285 IMAGE_FIRMWARE_BACKUP_FCOE = 0xb2,
1286 IMAGE_FIRMWARE_PHY = 0xc0,
1287 IMAGE_REDBOOT_DIR = 0xd0,
1288 IMAGE_REDBOOT_CONFIG = 0xd1,
1289 IMAGE_UFI_DIR = 0xd2,
1290 IMAGE_BOOT_CODE = 0xe2
1291};
e02cfd96
VV		 1292
1293struct controller_id {
1294 u32 vendor;
1295 u32 device;
1296 u32 subvendor;
1297 u32 subdevice;
1298};
1299
1300struct flash_comp {
1301 unsigned long offset;
1302 int optype;
1303 int size;
1304 int img_type;
1305};
1306
1307struct image_hdr {
1308 u32 imageid;
1309 u32 imageoffset;
1310 u32 imagelength;
1311 u32 image_checksum;
1312 u8 image_version[32];
1313};
1314
1315struct flash_file_hdr_g2 {
1316 u8 sign[32];
1317 u32 cksum;
1318 u32 antidote;
1319 struct controller_id cont_id;
1320 u32 file_len;
1321 u32 chunk_num;
1322 u32 total_chunks;
1323 u32 num_imgs;
1324 u8 build[24];
1325};
1326
5d3acd0d
VV		 1327/* First letter of the build version of the image */
1328#define BLD_STR_UFI_TYPE_BE2 '2'
1329#define BLD_STR_UFI_TYPE_BE3 '3'
1330#define BLD_STR_UFI_TYPE_SH '4'
1331
e02cfd96
VV		 1332struct flash_file_hdr_g3 {
1333 u8 sign[52];
1334 u8 ufi_version[4];
1335 u32 file_len;
1336 u32 cksum;
1337 u32 antidote;
1338 u32 num_imgs;
1339 u8 build[24];
1340 u8 asic_type_rev;
1341 u8 rsvd[31];
1342};
1343
1344struct flash_section_hdr {
1345 u32 format_rev;
1346 u32 cksum;
1347 u32 antidote;
1348 u32 num_images;
1349 u8 id_string[128];
1350 u32 rsvd[4];
1351} __packed;
1352
1353struct flash_section_hdr_g2 {
1354 u32 format_rev;
1355 u32 cksum;
1356 u32 antidote;
1357 u32 build_num;
1358 u8 id_string[128];
1359 u32 rsvd[8];
1360} __packed;
1361
1362struct flash_section_entry {
1363 u32 type;
1364 u32 offset;
1365 u32 pad_size;
1366 u32 image_size;
1367 u32 cksum;
1368 u32 entry_point;
1369 u16 optype;
1370 u16 rsvd0;
1371 u32 rsvd1;
1372 u8 ver_data[32];
1373} __packed;
1374
1375struct flash_section_info {
1376 u8 cookie[32];
1377 struct flash_section_hdr fsec_hdr;
1378 struct flash_section_entry fsec_entry[32];
1379} __packed;
1380
1381struct flash_section_info_g2 {
1382 u8 cookie[32];
1383 struct flash_section_hdr_g2 fsec_hdr;
1384 struct flash_section_entry fsec_entry[32];
1385} __packed;
1386
84517482 1387/****************** Firmware Flash ******************/
e02cfd96
VV		 1388#define FLASHROM_OPER_FLASH 1
1389#define FLASHROM_OPER_SAVE 2
1390#define FLASHROM_OPER_REPORT 4
1391#define FLASHROM_OPER_PHY_FLASH 9
1392#define FLASHROM_OPER_PHY_SAVE 10
1393
84517482
AK		 1394struct flashrom_params {
1395 u32 op_code;
1396 u32 op_type;
1397 u32 data_buf_size;
1398 u32 offset;
84517482
AK		 1399};
1400
1401struct be_cmd_write_flashrom {
1402 struct be_cmd_req_hdr hdr;
1403 struct flashrom_params params;
be716446
PR		 1404 u8 data_buf[32768];
1405 u8 rsvd[4];
1406} __packed;
84517482 1407
be716446
PR		 1408/* cmd to read flash crc */
1409struct be_cmd_read_flash_crc {
1410 struct be_cmd_req_hdr hdr;
1411 struct flashrom_params params;
1412 u8 crc[4];
1413 u8 rsvd[4];
96c9b2e4
VV		 1414} __packed;
1415
485bf569 1416/**************** Lancer Firmware Flash ************/
a23113b5
SR		 1417#define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024)
1418#define LANCER_FW_DOWNLOAD_LOCATION "/prg"
1419
485bf569
SN		 1420struct amap_lancer_write_obj_context {
1421 u8 write_length[24];
1422 u8 reserved1[7];
1423 u8 eof;
1424} __packed;
1425
1426struct lancer_cmd_req_write_object {
1427 struct be_cmd_req_hdr hdr;
1428 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1429 u32 write_offset;
1430 u8 object_name[104];
1431 u32 descriptor_count;
1432 u32 buf_len;
1433 u32 addr_low;
1434 u32 addr_high;
1435};
1436
f67ef7ba
PR		 1437#define LANCER_NO_RESET_NEEDED 0x00
1438#define LANCER_FW_RESET_NEEDED 0x02
485bf569
SN		 1439struct lancer_cmd_resp_write_object {
1440 u8 opcode;
1441 u8 subsystem;
1442 u8 rsvd1[2];
1443 u8 status;
1444 u8 additional_status;
1445 u8 rsvd2[2];
1446 u32 resp_len;
1447 u32 actual_resp_len;
1448 u32 actual_write_len;
f67ef7ba
PR		 1449 u8 change_status;
1450 u8 rsvd3[3];
485bf569
SN		 1451};
1452
de49bd5a
PR		 1453/************************ Lancer Read FW info **************/
1454#define LANCER_READ_FILE_CHUNK (32*1024)
1455#define LANCER_READ_FILE_EOF_MASK 0x80000000
1456
1457#define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
af5875bd
PR		 1458#define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1459#define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
de49bd5a
PR		 1460
1461struct lancer_cmd_req_read_object {
1462 struct be_cmd_req_hdr hdr;
1463 u32 desired_read_len;
1464 u32 read_offset;
1465 u8 object_name[104];
1466 u32 descriptor_count;
1467 u32 buf_len;
1468 u32 addr_low;
1469 u32 addr_high;
1470};
1471
1472struct lancer_cmd_resp_read_object {
1473 u8 opcode;
1474 u8 subsystem;
1475 u8 rsvd1[2];
1476 u8 status;
1477 u8 additional_status;
1478 u8 rsvd2[2];
1479 u32 resp_len;
1480 u32 actual_resp_len;
1481 u32 actual_read_len;
1482 u32 eof;
1483};
1484
f0613380
KA		 1485struct lancer_cmd_req_delete_object {
1486 struct be_cmd_req_hdr hdr;
1487 u32 rsvd1;
1488 u32 rsvd2;
1489 u8 object_name[104];
1490};
1491
71d8d1b5
AK		 1492/************************ WOL *******************************/
1493struct be_cmd_req_acpi_wol_magic_config{
1494 struct be_cmd_req_hdr hdr;
1495 u32 rsvd0[145];
1496 u8 magic_mac[6];
1497 u8 rsvd2[2];
1498} __packed;
1499
4762f6ce
AK		 1500struct be_cmd_req_acpi_wol_magic_config_v1 {
1501 struct be_cmd_req_hdr hdr;
1502 u8 rsvd0[2];
1503 u8 query_options;
1504 u8 rsvd1[5];
1505 u32 rsvd2[288];
1506 u8 magic_mac[6];
1507 u8 rsvd3[22];
1508} __packed;
1509
1510struct be_cmd_resp_acpi_wol_magic_config_v1 {
1511 struct be_cmd_resp_hdr hdr;
1512 u8 rsvd0[2];
1513 u8 wol_settings;
1514 u8 rsvd1[5];
1515 u32 rsvd2[295];
1516} __packed;
1517
1518#define BE_GET_WOL_CAP 2
1519
1520#define BE_WOL_CAP 0x1
1521#define BE_PME_D0_CAP 0x8
1522#define BE_PME_D1_CAP 0x10
1523#define BE_PME_D2_CAP 0x20
1524#define BE_PME_D3HOT_CAP 0x40
1525#define BE_PME_D3COLD_CAP 0x80
1526
ff33a6e2 1527/********************** LoopBack test *********************/
9c855975
SR		 1528#define SET_LB_MODE_TIMEOUT 12000
1529
ff33a6e2
S		 1530struct be_cmd_req_loopback_test {
1531 struct be_cmd_req_hdr hdr;
1532 u32 loopback_type;
1533 u32 num_pkts;
1534 u64 pattern;
1535 u32 src_port;
1536 u32 dest_port;
1537 u32 pkt_size;
1538};
1539
1540struct be_cmd_resp_loopback_test {
1541 struct be_cmd_resp_hdr resp_hdr;
1542 u32 status;
1543 u32 num_txfer;
1544 u32 num_rx;
1545 u32 miscomp_off;
1546 u32 ticks_compl;
1547};
1548
fced9999
SB		 1549struct be_cmd_req_set_lmode {
1550 struct be_cmd_req_hdr hdr;
1551 u8 src_port;
1552 u8 dest_port;
1553 u8 loopback_type;
1554 u8 loopback_state;
1555};
1556
ff33a6e2
S		 1557/********************** DDR DMA test *********************/
1558struct be_cmd_req_ddrdma_test {
1559 struct be_cmd_req_hdr hdr;
1560 u64 pattern;
1561 u32 byte_count;
1562 u32 rsvd0;
1563 u8 snd_buff[4096];
1564 u8 rsvd1[4096];
1565};
1566
1567struct be_cmd_resp_ddrdma_test {
1568 struct be_cmd_resp_hdr hdr;
1569 u64 pattern;
1570 u32 byte_cnt;
1571 u32 snd_err;
1572 u8 rsvd0[4096];
1573 u8 rcv_buff[4096];
1574};
1575
368c0ca2
SB		 1576/*********************** SEEPROM Read ***********************/
1577
1578#define BE_READ_SEEPROM_LEN 1024
1579struct be_cmd_req_seeprom_read {
1580 struct be_cmd_req_hdr hdr;
1581 u8 rsvd0[BE_READ_SEEPROM_LEN];
1582};
1583
1584struct be_cmd_resp_seeprom_read {
1585 struct be_cmd_req_hdr hdr;
1586 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1587};
1588
ee3cb629
AK		 1589enum {
1590 PHY_TYPE_CX4_10GB = 0,
1591 PHY_TYPE_XFP_10GB,
1592 PHY_TYPE_SFP_1GB,
1593 PHY_TYPE_SFP_PLUS_10GB,
1594 PHY_TYPE_KR_10GB,
1595 PHY_TYPE_KX4_10GB,
1596 PHY_TYPE_BASET_10GB,
1597 PHY_TYPE_BASET_1GB,
42f11cf2
AK		 1598 PHY_TYPE_BASEX_1GB,
1599 PHY_TYPE_SGMII,
6809cee0
RN		 1600 PHY_TYPE_QSFP,
1601 PHY_TYPE_KR4_40GB,
1602 PHY_TYPE_KR2_20GB,
e02cfd96 1603 PHY_TYPE_TN_8022,
ee3cb629
AK		 1604 PHY_TYPE_DISABLED = 255
1605};
1606
42f11cf2
AK		 1607#define BE_SUPPORTED_SPEED_NONE 0
1608#define BE_SUPPORTED_SPEED_10MBPS 1
1609#define BE_SUPPORTED_SPEED_100MBPS 2
1610#define BE_SUPPORTED_SPEED_1GBPS 4
1611#define BE_SUPPORTED_SPEED_10GBPS 8
d6b7a9b7 1612#define BE_SUPPORTED_SPEED_20GBPS 0x10
6809cee0 1613#define BE_SUPPORTED_SPEED_40GBPS 0x20
42f11cf2
AK		 1614
1615#define BE_AN_EN 0x2
1616#define BE_PAUSE_SYM_EN 0x80
1617
1618/* MAC speed valid values */
1619#define SPEED_DEFAULT 0x0
1620#define SPEED_FORCED_10GB 0x1
1621#define SPEED_FORCED_1GB 0x2
1622#define SPEED_AUTONEG_10GB 0x3
1623#define SPEED_AUTONEG_1GB 0x4
1624#define SPEED_AUTONEG_100MB 0x5
1625#define SPEED_AUTONEG_10GB_1GB 0x6
1626#define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1627#define SPEED_AUTONEG_1GB_100MB 0x8
1628#define SPEED_AUTONEG_10MB 0x9
1629#define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1630#define SPEED_AUTONEG_100MB_10MB 0xb
1631#define SPEED_FORCED_100MB 0xc
1632#define SPEED_FORCED_10MB 0xd
1633
ee3cb629
AK		 1634struct be_cmd_req_get_phy_info {
1635 struct be_cmd_req_hdr hdr;
1636 u8 rsvd0[24];
1637};
306f1348
SP		 1638
1639struct be_phy_info {
ee3cb629
AK		 1640 u16 phy_type;
1641 u16 interface_type;
1642 u32 misc_params;
42f11cf2
AK		 1643 u16 ext_phy_details;
1644 u16 rsvd;
1645 u16 auto_speeds_supported;
1646 u16 fixed_speeds_supported;
1647 u32 future_use[2];
ee3cb629
AK		 1648};
1649
306f1348
SP		 1650struct be_cmd_resp_get_phy_info {
1651 struct be_cmd_req_hdr hdr;
1652 struct be_phy_info phy_info;
1653};
1654
e1d18735
AK		 1655/*********************** Set QOS ***********************/
1656
1657#define BE_QOS_BITS_NIC 1
1658
1659struct be_cmd_req_set_qos {
1660 struct be_cmd_req_hdr hdr;
1661 u32 valid_bits;
1662 u32 max_bps_nic;
1663 u32 rsvd[7];
1664};
1665
9e1453c5 1666/*********************** Controller Attributes ***********************/
e02cfd96
VV		 1667struct mgmt_hba_attribs {
1668 u32 rsvd0[24];
1669 u8 controller_model_number[32];
a155a5db
SB		 1670 u32 rsvd1[16];
1671 u32 controller_serial_number[8];
1672 u32 rsvd2[55];
1673 u8 rsvd3[3];
e02cfd96 1674 u8 phy_port;
a155a5db 1675 u32 rsvd4[13];
e02cfd96
VV		 1676} __packed;
1677
1678struct mgmt_controller_attrib {
1679 struct mgmt_hba_attribs hba_attribs;
980df249 1680 u32 rsvd0[10];
e02cfd96
VV		 1681} __packed;
1682
9e1453c5
AK		 1683struct be_cmd_req_cntl_attribs {
1684 struct be_cmd_req_hdr hdr;
1685};
1686
1687struct be_cmd_resp_cntl_attribs {
1688 struct be_cmd_resp_hdr hdr;
1689 struct mgmt_controller_attrib attribs;
1690};
1691
2e588f84
SP		 1692/*********************** Set driver function ***********************/
1693#define CAPABILITY_SW_TIMESTAMPS 2
1694#define CAPABILITY_BE3_NATIVE_ERX_API 4
1695
1696struct be_cmd_req_set_func_cap {
1697 struct be_cmd_req_hdr hdr;
1698 u32 valid_cap_flags;
1699 u32 cap_flags;
1700 u8 rsvd[212];
1701};
1702
1703struct be_cmd_resp_set_func_cap {
1704 struct be_cmd_resp_hdr hdr;
1705 u32 valid_cap_flags;
1706 u32 cap_flags;
1707 u8 rsvd[212];
1708};
1709
f25b119c
PR		 1710/*********************** Function Privileges ***********************/
1711enum {
1712 BE_PRIV_DEFAULT = 0x1,
1713 BE_PRIV_LNKQUERY = 0x2,
1714 BE_PRIV_LNKSTATS = 0x4,
1715 BE_PRIV_LNKMGMT = 0x8,
1716 BE_PRIV_LNKDIAG = 0x10,
1717 BE_PRIV_UTILQUERY = 0x20,
1718 BE_PRIV_FILTMGMT = 0x40,
1719 BE_PRIV_IFACEMGMT = 0x80,
1720 BE_PRIV_VHADM = 0x100,
1721 BE_PRIV_DEVCFG = 0x200,
1722 BE_PRIV_DEVSEC = 0x400
1723};
1724#define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1725 BE_PRIV_DEVSEC)
1726#define MIN_PRIVILEGES BE_PRIV_DEFAULT
1727
1728struct be_cmd_priv_map {
1729 u8 opcode;
1730 u8 subsystem;
1731 u32 priv_mask;
1732};
1733
1734struct be_cmd_req_get_fn_privileges {
1735 struct be_cmd_req_hdr hdr;
1736 u32 rsvd;
1737};
1738
1739struct be_cmd_resp_get_fn_privileges {
1740 struct be_cmd_resp_hdr hdr;
1741 u32 privilege_mask;
1742};
1743
04a06028
SP		 1744struct be_cmd_req_set_fn_privileges {
1745 struct be_cmd_req_hdr hdr;
1746 u32 privileges; /* Used by BE3, SH-R */
1747 u32 privileges_lancer; /* Used by Lancer */
1748};
f25b119c 1749
590c391d
PR		 1750/******************** GET/SET_MACLIST **************************/
1751#define BE_MAX_MAC 64
590c391d
PR		 1752struct be_cmd_req_get_mac_list {
1753 struct be_cmd_req_hdr hdr;
e5e1ee89
PR		 1754 u8 mac_type;
1755 u8 perm_override;
1756 u16 iface_id;
1757 u32 mac_id;
1758 u32 rsvd[3];
1759} __packed;
1760
1761struct get_list_macaddr {
1762 u16 mac_addr_size;
1763 union {
1764 u8 macaddr[6];
1765 struct {
1766 u8 rsvd[2];
1767 u32 mac_id;
1768 } __packed s_mac_id;
1769 } __packed mac_addr_id;
590c391d
PR		 1770} __packed;
1771
1772struct be_cmd_resp_get_mac_list {
1773 struct be_cmd_resp_hdr hdr;
e5e1ee89
PR		 1774 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1775 struct get_list_macaddr macid_macaddr; /* soft mac */
1776 u8 true_mac_count;
1777 u8 pseudo_mac_count;
1778 u8 mac_list_size;
1779 u8 rsvd;
1780 /* perm override mac */
1781 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
590c391d
PR		 1782} __packed;
1783
1784struct be_cmd_req_set_mac_list {
1785 struct be_cmd_req_hdr hdr;
1786 u8 mac_count;
1787 u8 rsvd1;
1788 u16 rsvd2;
1789 struct macaddr mac[BE_MAX_MAC];
1790} __packed;
1791
f1f3ee1b 1792/*********************** HSW Config ***********************/
a77dcb8c
AK		 1793#define PORT_FWD_TYPE_VEPA 0x3
1794#define PORT_FWD_TYPE_VEB 0x2
ff9ed19d 1795#define PORT_FWD_TYPE_PASSTHRU 0x1
a77dcb8c 1796
e7bcbd7b
KA		 1797#define ENABLE_MAC_SPOOFCHK 0x2
1798#define DISABLE_MAC_SPOOFCHK 0x3
1799
f1f3ee1b
AK		 1800struct amap_set_hsw_context {
1801 u8 interface_id[16];
e7bcbd7b
KA		 1802 u8 rsvd0[8];
1803 u8 mac_spoofchk[2];
1804 u8 rsvd1[4];
f1f3ee1b 1805 u8 pvid_valid;
a77dcb8c 1806 u8 pport;
e7bcbd7b 1807 u8 rsvd2[6];
a77dcb8c 1808 u8 port_fwd_type[3];
e7bcbd7b
KA		 1809 u8 rsvd3[5];
1810 u8 vlan_spoofchk[2];
f1f3ee1b 1811 u8 pvid[16];
f1f3ee1b
AK		 1812 u8 rsvd4[32];
1813 u8 rsvd5[32];
e7bcbd7b 1814 u8 rsvd6[32];
f1f3ee1b
AK		 1815} __packed;
1816
1817struct be_cmd_req_set_hsw_config {
1818 struct be_cmd_req_hdr hdr;
1819 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1820} __packed;
1821
f1f3ee1b
AK		 1822struct amap_get_hsw_req_context {
1823 u8 interface_id[16];
1824 u8 rsvd0[14];
1825 u8 pvid_valid;
1826 u8 pport;
1827} __packed;
1828
1829struct amap_get_hsw_resp_context {
a77dcb8c
AK		 1830 u8 rsvd0[6];
1831 u8 port_fwd_type[3];
e7bcbd7b
KA		 1832 u8 rsvd1[5];
1833 u8 spoofchk;
1834 u8 rsvd2;
f1f3ee1b 1835 u8 pvid[16];
f1f3ee1b
AK		 1836 u8 rsvd3[32];
1837 u8 rsvd4[32];
e7bcbd7b 1838 u8 rsvd5[32];
f1f3ee1b
AK		 1839} __packed;
1840
1841struct be_cmd_req_get_hsw_config {
1842 struct be_cmd_req_hdr hdr;
1843 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1844} __packed;
1845
1846struct be_cmd_resp_get_hsw_config {
1847 struct be_cmd_resp_hdr hdr;
1848 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1849 u32 rsvd;
1850};
1851
b4e32a71
PR		 1852/******************* get port names ***************/
1853struct be_cmd_req_get_port_name {
1854 struct be_cmd_req_hdr hdr;
1855 u32 rsvd0;
1856};
1857
1858struct be_cmd_resp_get_port_name {
1859 struct be_cmd_req_hdr hdr;
1860 u8 port_name[4];
1861};
1862
89a88ab8
AK		 1863/*************** HW Stats Get v1 **********************************/
1864#define BE_TXP_SW_SZ 48
1865struct be_port_rxf_stats_v1 {
1866 u32 rsvd0[12];
1867 u32 rx_crc_errors;
1868 u32 rx_alignment_symbol_errors;
1869 u32 rx_pause_frames;
1870 u32 rx_priority_pause_frames;
1871 u32 rx_control_frames;
1872 u32 rx_in_range_errors;
1873 u32 rx_out_range_errors;
1874 u32 rx_frame_too_long;
18fb06a1 1875 u32 rx_address_filtered;
89a88ab8
AK		 1876 u32 rx_dropped_too_small;
1877 u32 rx_dropped_too_short;
1878 u32 rx_dropped_header_too_small;
1879 u32 rx_dropped_tcp_length;
1880 u32 rx_dropped_runt;
1881 u32 rsvd1[10];
1882 u32 rx_ip_checksum_errs;
1883 u32 rx_tcp_checksum_errs;
1884 u32 rx_udp_checksum_errs;
1885 u32 rsvd2[7];
1886 u32 rx_switched_unicast_packets;
1887 u32 rx_switched_multicast_packets;
1888 u32 rx_switched_broadcast_packets;
1889 u32 rsvd3[3];
1890 u32 tx_pauseframes;
1891 u32 tx_priority_pauseframes;
1892 u32 tx_controlframes;
1893 u32 rsvd4[10];
1894 u32 rxpp_fifo_overflow_drop;
1895 u32 rx_input_fifo_overflow_drop;
1896 u32 pmem_fifo_overflow_drop;
1897 u32 jabber_events;
1898 u32 rsvd5[3];
1899};
1900
1901
1902struct be_rxf_stats_v1 {
1903 struct be_port_rxf_stats_v1 port[4];
1904 u32 rsvd0[2];
1905 u32 rx_drops_no_pbuf;
1906 u32 rx_drops_no_txpb;
1907 u32 rx_drops_no_erx_descr;
1908 u32 rx_drops_no_tpre_descr;
1909 u32 rsvd1[6];
1910 u32 rx_drops_too_many_frags;
1911 u32 rx_drops_invalid_ring;
1912 u32 forwarded_packets;
1913 u32 rx_drops_mtu;
1914 u32 rsvd2[14];
1915};
1916
1917struct be_erx_stats_v1 {
1918 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1919 u32 rsvd[4];
1920};
1921
61000861
AK		 1922struct be_port_rxf_stats_v2 {
1923 u32 rsvd0[10];
1924 u32 roce_bytes_received_lsd;
1925 u32 roce_bytes_received_msd;
1926 u32 rsvd1[5];
1927 u32 roce_frames_received;
1928 u32 rx_crc_errors;
1929 u32 rx_alignment_symbol_errors;
1930 u32 rx_pause_frames;
1931 u32 rx_priority_pause_frames;
1932 u32 rx_control_frames;
1933 u32 rx_in_range_errors;
1934 u32 rx_out_range_errors;
1935 u32 rx_frame_too_long;
1936 u32 rx_address_filtered;
1937 u32 rx_dropped_too_small;
1938 u32 rx_dropped_too_short;
1939 u32 rx_dropped_header_too_small;
1940 u32 rx_dropped_tcp_length;
1941 u32 rx_dropped_runt;
1942 u32 rsvd2[10];
1943 u32 rx_ip_checksum_errs;
1944 u32 rx_tcp_checksum_errs;
1945 u32 rx_udp_checksum_errs;
1946 u32 rsvd3[7];
1947 u32 rx_switched_unicast_packets;
1948 u32 rx_switched_multicast_packets;
1949 u32 rx_switched_broadcast_packets;
1950 u32 rsvd4[3];
1951 u32 tx_pauseframes;
1952 u32 tx_priority_pauseframes;
1953 u32 tx_controlframes;
1954 u32 rsvd5[10];
1955 u32 rxpp_fifo_overflow_drop;
1956 u32 rx_input_fifo_overflow_drop;
1957 u32 pmem_fifo_overflow_drop;
1958 u32 jabber_events;
1959 u32 rsvd6[3];
1960 u32 rx_drops_payload_size;
1961 u32 rx_drops_clipped_header;
1962 u32 rx_drops_crc;
1963 u32 roce_drops_payload_len;
1964 u32 roce_drops_crc;
1965 u32 rsvd7[19];
1966};
1967
1968struct be_rxf_stats_v2 {
1969 struct be_port_rxf_stats_v2 port[4];
1970 u32 rsvd0[2];
1971 u32 rx_drops_no_pbuf;
1972 u32 rx_drops_no_txpb;
1973 u32 rx_drops_no_erx_descr;
1974 u32 rx_drops_no_tpre_descr;
1975 u32 rsvd1[6];
1976 u32 rx_drops_too_many_frags;
1977 u32 rx_drops_invalid_ring;
1978 u32 forwarded_packets;
1979 u32 rx_drops_mtu;
1980 u32 rsvd2[35];
1981};
1982
89a88ab8
AK		 1983struct be_hw_stats_v1 {
1984 struct be_rxf_stats_v1 rxf;
1985 u32 rsvd0[BE_TXP_SW_SZ];
1986 struct be_erx_stats_v1 erx;
1987 struct be_pmem_stats pmem;
0b3f0e7a 1988 u32 rsvd1[18];
89a88ab8
AK		 1989};
1990
1991struct be_cmd_req_get_stats_v1 {
1992 struct be_cmd_req_hdr hdr;
1993 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1994};
1995
1996struct be_cmd_resp_get_stats_v1 {
1997 struct be_cmd_resp_hdr hdr;
1998 struct be_hw_stats_v1 hw_stats;
1999};
2000
61000861
AK		 2001struct be_erx_stats_v2 {
2002 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/
2003 u32 rsvd[3];
2004};
2005
2006struct be_hw_stats_v2 {
2007 struct be_rxf_stats_v2 rxf;
2008 u32 rsvd0[BE_TXP_SW_SZ];
2009 struct be_erx_stats_v2 erx;
2010 struct be_pmem_stats pmem;
2011 u32 rsvd1[18];
2012};
2013
2014struct be_cmd_req_get_stats_v2 {
2015 struct be_cmd_req_hdr hdr;
2016 u8 rsvd[sizeof(struct be_hw_stats_v2)];
2017};
2018
2019struct be_cmd_resp_get_stats_v2 {
2020 struct be_cmd_resp_hdr hdr;
2021 struct be_hw_stats_v2 hw_stats;
2022};
2023
941a77d5
SK		 2024/************** get fat capabilites *******************/
2025#define MAX_MODULES 27
2026#define MAX_MODES 4
2027#define MODE_UART 0
2028#define FW_LOG_LEVEL_DEFAULT 48
2029#define FW_LOG_LEVEL_FATAL 64
2030
2031struct ext_fat_mode {
2032 u8 mode;
2033 u8 rsvd0;
2034 u16 port_mask;
2035 u32 dbg_lvl;
2036 u64 fun_mask;
2037} __packed;
2038
2039struct ext_fat_modules {
2040 u8 modules_str[32];
2041 u32 modules_id;
2042 u32 num_modes;
2043 struct ext_fat_mode trace_lvl[MAX_MODES];
2044} __packed;
2045
2046struct be_fat_conf_params {
2047 u32 max_log_entries;
2048 u32 log_entry_size;
2049 u8 log_type;
2050 u8 max_log_funs;
2051 u8 max_log_ports;
2052 u8 rsvd0;
2053 u32 supp_modes;
2054 u32 num_modules;
2055 struct ext_fat_modules module[MAX_MODULES];
2056} __packed;
2057
2058struct be_cmd_req_get_ext_fat_caps {
2059 struct be_cmd_req_hdr hdr;
2060 u32 parameter_type;
2061};
2062
2063struct be_cmd_resp_get_ext_fat_caps {
2064 struct be_cmd_resp_hdr hdr;
2065 struct be_fat_conf_params get_params;
2066};
2067
2068struct be_cmd_req_set_ext_fat_caps {
2069 struct be_cmd_req_hdr hdr;
2070 struct be_fat_conf_params set_params;
2071};
2072
150d58c7
VV		 2073#define RESOURCE_DESC_SIZE_V0 72
2074#define RESOURCE_DESC_SIZE_V1 88
2075#define PCIE_RESOURCE_DESC_TYPE_V0 0x40
a05f99db 2076#define NIC_RESOURCE_DESC_TYPE_V0 0x41
150d58c7 2077#define PCIE_RESOURCE_DESC_TYPE_V1 0x50
a05f99db 2078#define NIC_RESOURCE_DESC_TYPE_V1 0x51
f93f160b 2079#define PORT_RESOURCE_DESC_TYPE_V1 0x55
150d58c7 2080#define MAX_RESOURCE_DESC 264
d5c18473 2081
f2858738 2082#define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */
10cccf60 2083#define VFT_SHIFT 3 /* VF template */
a401801c
SP		 2084#define IMM_SHIFT 6 /* Immediate */
2085#define NOSV_SHIFT 7 /* No save */
d5c18473 2086
150d58c7 2087struct be_res_desc_hdr {
abb93951
PR		 2088 u8 desc_type;
2089 u8 desc_len;
150d58c7
VV		 2090} __packed;
2091
a401801c
SP		 2092struct be_port_res_desc {
2093 struct be_res_desc_hdr hdr;
2094 u8 rsvd0;
2095 u8 flags;
2096 u8 link_num;
2097 u8 mc_type;
2098 u16 rsvd1;
2099
2100#define NV_TYPE_MASK 0x3 /* bits 0-1 */
2101#define NV_TYPE_DISABLED 1
2102#define NV_TYPE_VXLAN 3
2103#define SOCVID_SHIFT 2 /* Strip outer vlan */
2104#define RCVID_SHIFT 4 /* Report vlan */
980df249 2105#define PF_NUM_IGNORE 255
a401801c
SP		 2106 u8 nv_flags;
2107 u8 rsvd2;
2108 __le16 nv_port; /* vxlan/gre port */
2109 u32 rsvd3[19];
2110} __packed;
2111
150d58c7
VV		 2112struct be_pcie_res_desc {
2113 struct be_res_desc_hdr hdr;
2114 u8 rsvd0;
2115 u8 flags;
2116 u16 rsvd1;
2117 u8 pf_num;
2118 u8 rsvd2;
2119 u32 rsvd3;
2120 u8 sriov_state;
2121 u8 pf_state;
2122 u8 pf_type;
2123 u8 rsvd4;
2124 u16 num_vfs;
2125 u16 rsvd5;
2126 u32 rsvd6[17];
2127} __packed;
2128
2129struct be_nic_res_desc {
2130 struct be_res_desc_hdr hdr;
abb93951 2131 u8 rsvd1;
a401801c
SP		 2132
2133#define QUN_SHIFT 4 /* QoS is in absolute units */
abb93951
PR		 2134 u8 flags;
2135 u8 vf_num;
2136 u8 rsvd2;
2137 u8 pf_num;
2138 u8 rsvd3;
2139 u16 unicast_mac_count;
2140 u8 rsvd4[6];
2141 u16 mcc_count;
2142 u16 vlan_count;
2143 u16 mcast_mac_count;
2144 u16 txq_count;
2145 u16 rq_count;
2146 u16 rssq_count;
2147 u16 lro_count;
2148 u16 cq_count;
2149 u16 toe_conn_count;
2150 u16 eq_count;
0f77ba73
RN		 2151 u16 vlan_id;
2152 u16 iface_count;
abb93951
PR		 2153 u32 cap_flags;
2154 u8 link_param;
0f77ba73
RN		 2155 u8 rsvd6;
2156 u16 channel_id_param;
abb93951
PR		 2157 u32 bw_min;
2158 u32 bw_max;
2159 u8 acpi_params;
2160 u8 wol_param;
2161 u16 rsvd7;
0f77ba73
RN		 2162 u16 tunnel_iface_count;
2163 u16 direct_tenant_iface_count;
2164 u32 rsvd8[6];
150d58c7 2165} __packed;
abb93951 2166
f93f160b
VV		 2167/************ Multi-Channel type ***********/
2168enum mc_type {
2169 MC_NONE = 0x01,
2170 UMC = 0x02,
2171 FLEX10 = 0x03,
2172 vNIC1 = 0x04,
2173 nPAR = 0x05,
2174 UFP = 0x06,
2175 vNIC2 = 0x07
2176};
2177
f93f160b
VV		 2178/* Is BE in a multi-channel mode */
2179static inline bool be_is_mc(struct be_adapter *adapter)
2180{
2181 return adapter->mc_type > MC_NONE;
2182}
2183
abb93951
PR		 2184struct be_cmd_req_get_func_config {
2185 struct be_cmd_req_hdr hdr;
2186};
2187
2188struct be_cmd_resp_get_func_config {
28710c55 2189 struct be_cmd_resp_hdr hdr;
abb93951 2190 u32 desc_count;
150d58c7 2191 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
abb93951
PR		 2192};
2193
f2858738
VV		 2194enum {
2195 RESOURCE_LIMITS,
2196 RESOURCE_MODIFIABLE
2197};
2198
abb93951
PR		 2199struct be_cmd_req_get_profile_config {
2200 struct be_cmd_req_hdr hdr;
2201 u8 rsvd;
f2858738
VV		 2202#define ACTIVE_PROFILE_TYPE 0x2
2203#define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3)
abb93951
PR		 2204 u8 type;
2205 u16 rsvd1;
2206};
2207
2208struct be_cmd_resp_get_profile_config {
150d58c7 2209 struct be_cmd_resp_hdr hdr;
f2858738
VV		 2210 __le16 desc_count;
2211 u16 rsvd;
150d58c7 2212 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
a05f99db
VV		 2213};
2214
f2858738 2215#define FIELD_MODIFIABLE 0xFFFF
d5c18473
PR		 2216struct be_cmd_req_set_profile_config {
2217 struct be_cmd_req_hdr hdr;
2218 u32 rsvd;
2219 u32 desc_count;
bec84e6b
VV		 2220 u8 desc[2 * RESOURCE_DESC_SIZE_V1];
2221} __packed;
d5c18473 2222
542963b7
VV		 2223struct be_cmd_req_get_active_profile {
2224 struct be_cmd_req_hdr hdr;
2225 u32 rsvd;
2226} __packed;
2227
2228struct be_cmd_resp_get_active_profile {
2229 struct be_cmd_resp_hdr hdr;
2230 u16 active_profile_id;
2231 u16 next_profile_id;
2232} __packed;
2233
dcf7ebba
PR		 2234struct be_cmd_enable_disable_vf {
2235 struct be_cmd_req_hdr hdr;
2236 u8 enable;
2237 u8 rsvd[3];
2238};
2239
68c45a2d
SK		 2240struct be_cmd_req_intr_set {
2241 struct be_cmd_req_hdr hdr;
2242 u8 intr_enabled;
2243 u8 rsvd[3];
2244};
2245
f25b119c
PR		 2246static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
2247{
2248 return flags & adapter->cmd_privileges ? true : false;
2249}
2250
4c876616
SP		 2251/************** Get IFACE LIST *******************/
2252struct be_if_desc {
2253 u32 if_id;
2254 u32 cap_flags;
2255 u32 en_flags;
2256};
2257
2258struct be_cmd_req_get_iface_list {
2259 struct be_cmd_req_hdr hdr;
2260};
2261
2262struct be_cmd_resp_get_iface_list {
2263 struct be_cmd_req_hdr hdr;
2264 u32 if_cnt;
2265 struct be_if_desc if_desc;
2266};
2267
bdce2ad7 2268/*************** Set logical link ********************/
d9d426af
SR		 2269#define PLINK_ENABLE BIT(0)
2270#define PLINK_TRACK BIT(8)
bdce2ad7
SR		 2271struct be_cmd_req_set_ll_link {
2272 struct be_cmd_req_hdr hdr;
2273 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */
2274};
2275
a401801c
SP		 2276/************** Manage IFACE Filters *******************/
2277#define OP_CONVERT_NORMAL_TO_TUNNEL 0
2278#define OP_CONVERT_TUNNEL_TO_NORMAL 1
2279
2280struct be_cmd_req_manage_iface_filters {
2281 struct be_cmd_req_hdr hdr;
2282 u8 op;
2283 u8 rsvd0;
2284 u8 flags;
2285 u8 rsvd1;
2286 u32 tunnel_iface_id;
2287 u32 target_iface_id;
2288 u8 mac[6];
2289 u16 vlan_tag;
2290 u32 tenant_id;
2291 u32 filter_id;
2292 u32 cap_flags;
2293 u32 cap_control_flags;
2294} __packed;
2295
31886e87
JP		 2296int be_pci_fnum_get(struct be_adapter *adapter);
2297int be_fw_wait_ready(struct be_adapter *adapter);
2298int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
2299 bool permanent, u32 if_handle, u32 pmac_id);
2300int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id,
2301 u32 *pmac_id, u32 domain);
2302int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id,
2303 u32 domain);
2304int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
2305 u32 *if_handle, u32 domain);
2306int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain);
2307int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo);
2308int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
2309 struct be_queue_info *eq, bool no_delay,
2310 int num_cqe_dma_coalesce);
2311int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq,
2312 struct be_queue_info *cq);
2313int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo);
2314int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq,
2315 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
2316int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
2317 int type);
2318int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q);
2319int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
2320 u8 *link_status, u32 dom);
2321int be_cmd_reset(struct be_adapter *adapter);
2322int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd);
2323int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
2324 struct be_dma_mem *nonemb_cmd);
e97e3cda 2325int be_cmd_get_fw_ver(struct be_adapter *adapter);
2632bafd 2326int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num);
31886e87 2327int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 2328 u32 num, u32 domain);
31886e87
JP		 2329int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
2330int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc);
2331int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc);
e97e3cda 2332int be_cmd_query_fw_cfg(struct be_adapter *adapter);
31886e87
JP		 2333int be_cmd_reset_function(struct be_adapter *adapter);
2334int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2335 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey);
31886e87
JP		 2336int be_process_mcc(struct be_adapter *adapter);
2337int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon,
2338 u8 status, u8 state);
2339int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num,
2340 u32 *state);
e36edd9d
ML		 2341int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2342 u8 page_num, u8 *data);
6809cee0 2343int be_cmd_query_cable_type(struct be_adapter *adapter);
21252377 2344int be_cmd_query_sfp_info(struct be_adapter *adapter);
de49bd5a 2345int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
31886e87
JP		 2346 u32 data_size, u32 data_offset, const char *obj_name,
2347 u32 *data_read, u32 *eof, u8 *addn_status);
a23113b5
SR		 2348int lancer_fw_download(struct be_adapter *adapter, const struct firmware *fw);
2349int be_fw_download(struct be_adapter *adapter, const struct firmware *fw);
31886e87
JP		 2350int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2351 struct be_dma_mem *nonemb_cmd);
2352int be_cmd_fw_init(struct be_adapter *adapter);
2353int be_cmd_fw_clean(struct be_adapter *adapter);
2354void be_async_mcc_enable(struct be_adapter *adapter);
2355void be_async_mcc_disable(struct be_adapter *adapter);
2356int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2357 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2358 u64 pattern);
2359int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt,
2360 struct be_dma_mem *cmd);
2361int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2362 struct be_dma_mem *nonemb_cmd);
2363int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2364 u8 loopback_type, u8 enable);
2365int be_cmd_get_phy_info(struct be_adapter *adapter);
0f77ba73
RN		 2366int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate,
2367 u16 link_speed, u8 domain);
31886e87
JP		 2368void be_detect_error(struct be_adapter *adapter);
2369int be_cmd_get_die_temperature(struct be_adapter *adapter);
2370int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
fd7ff6f0
VD		 2371int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size);
2372int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf);
31886e87 2373int be_cmd_req_native_mode(struct be_adapter *adapter);
31886e87
JP		 2374int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2375 u32 domain);
2376int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2377 u32 vf_num);
2378int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 2379 bool *pmac_id_active, u32 *pmac_id,
2380 u32 if_handle, u8 domain);
2381int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac,
2382 u32 if_handle, bool active, u32 domain);
31886e87
JP		 2383int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac);
2384int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count,
2385 u32 domain);
2386int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom);
2387int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain,
e7bcbd7b 2388 u16 intf_id, u16 hsw_mode, u8 spoofchk);
31886e87 2389int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain,
e7bcbd7b 2390 u16 intf_id, u8 *mode, bool *spoofchk);
31886e87 2391int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
baaa08d1
VV		 2392int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level);
2393int be_cmd_get_fw_log_level(struct be_adapter *adapter);
31886e87
JP		 2394int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2395 struct be_dma_mem *cmd);
2396int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2397 struct be_dma_mem *cmd,
2398 struct be_fat_conf_params *cfgs);
31886e87
JP		 2399int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
2400int lancer_initiate_dump(struct be_adapter *adapter);
f0613380 2401int lancer_delete_dump(struct be_adapter *adapter);
31886e87
JP		 2402bool dump_present(struct be_adapter *adapter);
2403int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
21252377 2404int be_cmd_query_port_name(struct be_adapter *adapter);
92bf14ab
SP		 2405int be_cmd_get_func_config(struct be_adapter *adapter,
2406 struct be_resources *res);
2407int be_cmd_get_profile_config(struct be_adapter *adapter,
f2858738 2408 struct be_resources *res, u8 query, u8 domain);
542963b7 2409int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile);
31886e87
JP		 2410int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
2411 int vf_num);
2412int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
2413int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
bdce2ad7
SR		 2414int be_cmd_set_logical_link_config(struct be_adapter *adapter,
2415 int link_state, u8 domain);
a401801c
SP		 2416int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port);
2417int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op);
bec84e6b 2418int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738
VV		 2419 struct be_resources res, u16 num_vfs,
2420 u16 num_vf_qs);
Linux 6.x block layer and io_uring tree(s)