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be2net: Activate new FW after FW download for Lancer
[linux-2.6-block.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
3de09455
SK		 22static inline void *embedded_payload(struct be_mcc_wrb *wrb)
23{
24 return wrb->payload.embedded_payload;
25}
609ff3bb 26
8788fdc2 27static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 28{
8788fdc2 29 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 30 u32 val = 0;
31
6589ade0 32 if (be_error(adapter))
7acc2087 33 return;
7acc2087 34
5fb379ee
SP		 35 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
36 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 37
38 wmb();
8788fdc2 39 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 40}
41
42/* To check if valid bit is set, check the entire word as we don't know
43 * the endianness of the data (old entry is host endian while a new entry is
44 * little endian) */
efd2e40a 45static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee
SP		 46{
47 if (compl->flags != 0) {
48 compl->flags = le32_to_cpu(compl->flags);
49 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
50 return true;
51 } else {
52 return false;
53 }
54}
55
56/* Need to reset the entire word that houses the valid bit */
efd2e40a 57static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 58{
59 compl->flags = 0;
60}
61
652bf646
PR		 62static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
63{
64 unsigned long addr;
65
66 addr = tag1;
67 addr = ((addr << 16) << 16) | tag0;
68 return (void *)addr;
69}
70
8788fdc2 71static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 72 struct be_mcc_compl *compl)
5fb379ee
SP		 73{
74 u16 compl_status, extd_status;
652bf646
PR		 75 struct be_cmd_resp_hdr *resp_hdr;
76 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 77
78 /* Just swap the status to host endian; mcc tag is opaquely copied
79 * from mcc_wrb */
80 be_dws_le_to_cpu(compl, 4);
81
82 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
83 CQE_STATUS_COMPL_MASK;
dd131e76 84
652bf646
PR		 85 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
86
87 if (resp_hdr) {
88 opcode = resp_hdr->opcode;
89 subsystem = resp_hdr->subsystem;
90 }
91
92 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
93 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
94 (subsystem == CMD_SUBSYSTEM_COMMON)) {
dd131e76
SB		 95 adapter->flash_status = compl_status;
96 complete(&adapter->flash_compl);
97 }
98
b31c50a7 99 if (compl_status == MCC_STATUS_SUCCESS) {
652bf646
PR		 100 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
101 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
102 (subsystem == CMD_SUBSYSTEM_ETH)) {
89a88ab8 103 be_parse_stats(adapter);
b2aebe6d 104 adapter->stats_cmd_sent = false;
b31c50a7 105 }
652bf646
PR		 106 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
107 subsystem == CMD_SUBSYSTEM_COMMON) {
3de09455 108 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
652bf646 109 (void *)resp_hdr;
3de09455
SK		 110 adapter->drv_stats.be_on_die_temperature =
111 resp->on_die_temperature;
112 }
2b3f291b 113 } else {
652bf646 114 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
7aeb2156 115 adapter->be_get_temp_freq = 0;
3de09455 116
2b3f291b
SP		 117 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
118 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
119 goto done;
120
121 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd
VV		 122 dev_warn(&adapter->pdev->dev,
123 "opcode %d-%d is not permitted\n",
124 opcode, subsystem);
2b3f291b
SP		 125 } else {
126 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
127 CQE_STATUS_EXTD_MASK;
97f1d8cd
VV		 128 dev_err(&adapter->pdev->dev,
129 "opcode %d-%d failed:status %d-%d\n",
130 opcode, subsystem, compl_status, extd_status);
2b3f291b 131 }
5fb379ee 132 }
2b3f291b 133done:
b31c50a7 134 return compl_status;
5fb379ee
SP		 135}
136
a8f447bd 137/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 138static void be_async_link_state_process(struct be_adapter *adapter,
a8f447bd
SP		 139 struct be_async_event_link_state *evt)
140{
b236916a 141 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 142 adapter->phy.link_speed = -1;
b236916a
AK		 143
144 /* For the initial link status do not rely on the ASYNC event as
145 * it may not be received in some cases.
146 */
147 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
148 be_link_status_update(adapter, evt->port_link_status);
a8f447bd
SP		 149}
150
cc4ce020
SK		 151/* Grp5 CoS Priority evt */
152static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
153 struct be_async_event_grp5_cos_priority *evt)
154{
155 if (evt->valid) {
156 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 157 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 158 adapter->recommended_prio =
159 evt->reco_default_priority << VLAN_PRIO_SHIFT;
160 }
161}
162
163/* Grp5 QOS Speed evt */
164static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
165 struct be_async_event_grp5_qos_link_speed *evt)
166{
167 if (evt->physical_port == adapter->port_num) {
168 /* qos_link_speed is in units of 10 Mbps */
42f11cf2 169 adapter->phy.link_speed = evt->qos_link_speed * 10;
cc4ce020
SK		 170 }
171}
172
3968fa1e
AK		 173/*Grp5 PVID evt*/
174static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
175 struct be_async_event_grp5_pvid_state *evt)
176{
177 if (evt->enabled)
939cf306 178 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
3968fa1e
AK		 179 else
180 adapter->pvid = 0;
181}
182
cc4ce020
SK		 183static void be_async_grp5_evt_process(struct be_adapter *adapter,
184 u32 trailer, struct be_mcc_compl *evt)
185{
186 u8 event_type = 0;
187
188 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
189 ASYNC_TRAILER_EVENT_TYPE_MASK;
190
191 switch (event_type) {
192 case ASYNC_EVENT_COS_PRIORITY:
193 be_async_grp5_cos_priority_process(adapter,
194 (struct be_async_event_grp5_cos_priority *)evt);
195 break;
196 case ASYNC_EVENT_QOS_SPEED:
197 be_async_grp5_qos_speed_process(adapter,
198 (struct be_async_event_grp5_qos_link_speed *)evt);
199 break;
3968fa1e
AK		 200 case ASYNC_EVENT_PVID_STATE:
201 be_async_grp5_pvid_state_process(adapter,
202 (struct be_async_event_grp5_pvid_state *)evt);
203 break;
cc4ce020
SK		 204 default:
205 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
206 break;
207 }
208}
209
a8f447bd
SP		 210static inline bool is_link_state_evt(u32 trailer)
211{
807540ba 212 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
a8f447bd 213 ASYNC_TRAILER_EVENT_CODE_MASK) ==
807540ba 214 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 215}
5fb379ee 216
cc4ce020
SK		 217static inline bool is_grp5_evt(u32 trailer)
218{
219 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
220 ASYNC_TRAILER_EVENT_CODE_MASK) ==
221 ASYNC_EVENT_CODE_GRP_5);
222}
223
efd2e40a 224static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 225{
8788fdc2 226 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 227 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 228
229 if (be_mcc_compl_is_new(compl)) {
230 queue_tail_inc(mcc_cq);
231 return compl;
232 }
233 return NULL;
234}
235
7a1e9b20
SP		 236void be_async_mcc_enable(struct be_adapter *adapter)
237{
238 spin_lock_bh(&adapter->mcc_cq_lock);
239
240 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
241 adapter->mcc_obj.rearm_cq = true;
242
243 spin_unlock_bh(&adapter->mcc_cq_lock);
244}
245
246void be_async_mcc_disable(struct be_adapter *adapter)
247{
248 adapter->mcc_obj.rearm_cq = false;
249}
250
10ef9ab4 251int be_process_mcc(struct be_adapter *adapter)
5fb379ee 252{
efd2e40a 253 struct be_mcc_compl *compl;
10ef9ab4 254 int num = 0, status = 0;
7a1e9b20 255 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 256
8788fdc2
SP		 257 spin_lock_bh(&adapter->mcc_cq_lock);
258 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd
SP		 259 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
260 /* Interpret flags as an async trailer */
323f30b3
AK		 261 if (is_link_state_evt(compl->flags))
262 be_async_link_state_process(adapter,
a8f447bd 263 (struct be_async_event_link_state *) compl);
cc4ce020
SK		 264 else if (is_grp5_evt(compl->flags))
265 be_async_grp5_evt_process(adapter,
266 compl->flags, compl);
b31c50a7 267 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
10ef9ab4 268 status = be_mcc_compl_process(adapter, compl);
7a1e9b20 269 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 270 }
271 be_mcc_compl_use(compl);
272 num++;
273 }
b31c50a7 274
10ef9ab4
SP		 275 if (num)
276 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
277
8788fdc2 278 spin_unlock_bh(&adapter->mcc_cq_lock);
10ef9ab4 279 return status;
5fb379ee
SP		 280}
281
6ac7b687 282/* Wait till no more pending mcc requests are present */
b31c50a7 283static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 284{
b31c50a7 285#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 286 int i, status = 0;
f31e50a8
SP		 287 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
288
6ac7b687 289 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 290 if (be_error(adapter))
291 return -EIO;
292
10ef9ab4 293 status = be_process_mcc(adapter);
b31c50a7 294
f31e50a8 295 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 296 break;
297 udelay(100);
298 }
b31c50a7 299 if (i == mcc_timeout) {
6589ade0
SP		 300 dev_err(&adapter->pdev->dev, "FW not responding\n");
301 adapter->fw_timeout = true;
652bf646 302 return -EIO;
b31c50a7 303 }
f31e50a8 304 return status;
6ac7b687
SP		 305}
306
307/* Notify MCC requests and wait for completion */
b31c50a7 308static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 309{
652bf646
PR		 310 int status;
311 struct be_mcc_wrb *wrb;
312 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
313 u16 index = mcc_obj->q.head;
314 struct be_cmd_resp_hdr *resp;
315
316 index_dec(&index, mcc_obj->q.len);
317 wrb = queue_index_node(&mcc_obj->q, index);
318
319 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
320
8788fdc2 321 be_mcc_notify(adapter);
652bf646
PR		 322
323 status = be_mcc_wait_compl(adapter);
324 if (status == -EIO)
325 goto out;
326
327 status = resp->status;
328out:
329 return status;
6ac7b687
SP		 330}
331
5f0b849e 332static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 333{
f25b03a7 334 int msecs = 0;
6b7c5b94
SP		 335 u32 ready;
336
337 do {
6589ade0
SP		 338 if (be_error(adapter))
339 return -EIO;
340
cf588477 341 ready = ioread32(db);
434b3648 342 if (ready == 0xffffffff)
cf588477 343 return -1;
cf588477
SP		 344
345 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 346 if (ready)
347 break;
348
f25b03a7 349 if (msecs > 4000) {
6589ade0
SP		 350 dev_err(&adapter->pdev->dev, "FW not responding\n");
351 adapter->fw_timeout = true;
f67ef7ba 352 be_detect_error(adapter);
6b7c5b94
SP		 353 return -1;
354 }
355
1dbf53a2 356 msleep(1);
f25b03a7 357 msecs++;
6b7c5b94
SP		 358 } while (true);
359
360 return 0;
361}
362
363/*
364 * Insert the mailbox address into the doorbell in two steps
5fb379ee 365 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 366 */
b31c50a7 367static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 368{
369 int status;
6b7c5b94 370 u32 val = 0;
8788fdc2
SP		 371 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
372 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 373 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 374 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 375
cf588477
SP		 376 /* wait for ready to be set */
377 status = be_mbox_db_ready_wait(adapter, db);
378 if (status != 0)
379 return status;
380
6b7c5b94
SP		 381 val |= MPU_MAILBOX_DB_HI_MASK;
382 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
383 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
384 iowrite32(val, db);
385
386 /* wait for ready to be set */
5f0b849e 387 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 388 if (status != 0)
389 return status;
390
391 val = 0;
6b7c5b94
SP		 392 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
393 val |= (u32)(mbox_mem->dma >> 4) << 2;
394 iowrite32(val, db);
395
5f0b849e 396 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 397 if (status != 0)
398 return status;
399
5fb379ee 400 /* A cq entry has been made now */
efd2e40a
SP		 401 if (be_mcc_compl_is_new(compl)) {
402 status = be_mcc_compl_process(adapter, &mbox->compl);
403 be_mcc_compl_use(compl);
5fb379ee
SP		 404 if (status)
405 return status;
406 } else {
5f0b849e 407 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 408 return -1;
409 }
5fb379ee 410 return 0;
6b7c5b94
SP		 411}
412
8788fdc2 413static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
6b7c5b94 414{
fe6d2a38
SP		 415 u32 sem;
416
417 if (lancer_chip(adapter))
418 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
419 else
420 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
6b7c5b94
SP		 421
422 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
423 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
424 return -1;
425 else
426 return 0;
427}
428
bf99e50d
PR		 429int lancer_wait_ready(struct be_adapter *adapter)
430{
431#define SLIPORT_READY_TIMEOUT 30
432 u32 sliport_status;
433 int status = 0, i;
434
435 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
436 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
437 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
438 break;
439
440 msleep(1000);
441 }
442
443 if (i == SLIPORT_READY_TIMEOUT)
444 status = -1;
445
446 return status;
447}
448
449int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
450{
451 int status;
452 u32 sliport_status, err, reset_needed;
453 status = lancer_wait_ready(adapter);
454 if (!status) {
455 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
456 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
457 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
458 if (err && reset_needed) {
459 iowrite32(SLI_PORT_CONTROL_IP_MASK,
460 adapter->db + SLIPORT_CONTROL_OFFSET);
461
462 /* check adapter has corrected the error */
463 status = lancer_wait_ready(adapter);
464 sliport_status = ioread32(adapter->db +
465 SLIPORT_STATUS_OFFSET);
466 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
467 SLIPORT_STATUS_RN_MASK);
468 if (status || sliport_status)
469 status = -1;
470 } else if (err || reset_needed) {
471 status = -1;
472 }
473 }
474 return status;
475}
476
477int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 478{
43a04fdc
SP		 479 u16 stage;
480 int status, timeout = 0;
6ed35eea 481 struct device *dev = &adapter->pdev->dev;
6b7c5b94 482
bf99e50d
PR		 483 if (lancer_chip(adapter)) {
484 status = lancer_wait_ready(adapter);
485 return status;
486 }
487
43a04fdc
SP		 488 do {
489 status = be_POST_stage_get(adapter, &stage);
490 if (status) {
6ed35eea 491 dev_err(dev, "POST error; stage=0x%x\n", stage);
43a04fdc
SP		 492 return -1;
493 } else if (stage != POST_STAGE_ARMFW_RDY) {
6ed35eea
SP		 494 if (msleep_interruptible(2000)) {
495 dev_err(dev, "Waiting for POST aborted\n");
496 return -EINTR;
497 }
43a04fdc
SP		 498 timeout += 2;
499 } else {
500 return 0;
501 }
3ab81b5f 502 } while (timeout < 60);
6b7c5b94 503
6ed35eea 504 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
43a04fdc 505 return -1;
6b7c5b94
SP		 506}
507
6b7c5b94
SP		 508
509static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
510{
511 return &wrb->payload.sgl[0];
512}
513
6b7c5b94
SP		 514
515/* Don't touch the hdr after it's prepared */
106df1e3
SK		 516/* mem will be NULL for embedded commands */
517static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
518 u8 subsystem, u8 opcode, int cmd_len,
519 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
6b7c5b94 520{
106df1e3 521 struct be_sge *sge;
652bf646
PR		 522 unsigned long addr = (unsigned long)req_hdr;
523 u64 req_addr = addr;
106df1e3 524
6b7c5b94
SP		 525 req_hdr->opcode = opcode;
526 req_hdr->subsystem = subsystem;
527 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 528 req_hdr->version = 0;
106df1e3 529
652bf646
PR		 530 wrb->tag0 = req_addr & 0xFFFFFFFF;
531 wrb->tag1 = upper_32_bits(req_addr);
532
106df1e3
SK		 533 wrb->payload_length = cmd_len;
534 if (mem) {
535 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
536 MCC_WRB_SGE_CNT_SHIFT;
537 sge = nonembedded_sgl(wrb);
538 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
539 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
540 sge->len = cpu_to_le32(mem->size);
541 } else
542 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
543 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 544}
545
546static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
547 struct be_dma_mem *mem)
548{
549 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
550 u64 dma = (u64)mem->dma;
551
552 for (i = 0; i < buf_pages; i++) {
553 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
554 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
555 dma += PAGE_SIZE_4K;
556 }
557}
558
559/* Converts interrupt delay in microseconds to multiplier value */
560static u32 eq_delay_to_mult(u32 usec_delay)
561{
562#define MAX_INTR_RATE 651042
563 const u32 round = 10;
564 u32 multiplier;
565
566 if (usec_delay == 0)
567 multiplier = 0;
568 else {
569 u32 interrupt_rate = 1000000 / usec_delay;
570 /* Max delay, corresponding to the lowest interrupt rate */
571 if (interrupt_rate == 0)
572 multiplier = 1023;
573 else {
574 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
575 multiplier /= interrupt_rate;
576 /* Round the multiplier to the closest value.*/
577 multiplier = (multiplier + round/2) / round;
578 multiplier = min(multiplier, (u32)1023);
579 }
580 }
581 return multiplier;
582}
583
b31c50a7 584static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 585{
b31c50a7
SP		 586 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
587 struct be_mcc_wrb *wrb
588 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
589 memset(wrb, 0, sizeof(*wrb));
590 return wrb;
6b7c5b94
SP		 591}
592
b31c50a7 593static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 594{
b31c50a7
SP		 595 struct be_queue_info *mccq = &adapter->mcc_obj.q;
596 struct be_mcc_wrb *wrb;
597
713d0394
SP		 598 if (atomic_read(&mccq->used) >= mccq->len) {
599 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
600 return NULL;
601 }
602
b31c50a7
SP		 603 wrb = queue_head_node(mccq);
604 queue_head_inc(mccq);
605 atomic_inc(&mccq->used);
606 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 607 return wrb;
608}
609
2243e2e9
SP		 610/* Tell fw we're about to start firing cmds by writing a
611 * special pattern across the wrb hdr; uses mbox
612 */
613int be_cmd_fw_init(struct be_adapter *adapter)
614{
615 u8 *wrb;
616 int status;
617
bf99e50d
PR		 618 if (lancer_chip(adapter))
619 return 0;
620
2984961c
IV		 621 if (mutex_lock_interruptible(&adapter->mbox_lock))
622 return -1;
2243e2e9
SP		 623
624 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 625 *wrb++ = 0xFF;
626 *wrb++ = 0x12;
627 *wrb++ = 0x34;
628 *wrb++ = 0xFF;
629 *wrb++ = 0xFF;
630 *wrb++ = 0x56;
631 *wrb++ = 0x78;
632 *wrb = 0xFF;
2243e2e9
SP		 633
634 status = be_mbox_notify_wait(adapter);
635
2984961c 636 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 637 return status;
638}
639
640/* Tell fw we're done with firing cmds by writing a
641 * special pattern across the wrb hdr; uses mbox
642 */
643int be_cmd_fw_clean(struct be_adapter *adapter)
644{
645 u8 *wrb;
646 int status;
647
bf99e50d
PR		 648 if (lancer_chip(adapter))
649 return 0;
650
2984961c
IV		 651 if (mutex_lock_interruptible(&adapter->mbox_lock))
652 return -1;
2243e2e9
SP		 653
654 wrb = (u8 *)wrb_from_mbox(adapter);
655 *wrb++ = 0xFF;
656 *wrb++ = 0xAA;
657 *wrb++ = 0xBB;
658 *wrb++ = 0xFF;
659 *wrb++ = 0xFF;
660 *wrb++ = 0xCC;
661 *wrb++ = 0xDD;
662 *wrb = 0xFF;
663
664 status = be_mbox_notify_wait(adapter);
665
2984961c 666 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 667 return status;
668}
bf99e50d 669
8788fdc2 670int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94
SP		 671 struct be_queue_info *eq, int eq_delay)
672{
b31c50a7
SP		 673 struct be_mcc_wrb *wrb;
674 struct be_cmd_req_eq_create *req;
6b7c5b94
SP		 675 struct be_dma_mem *q_mem = &eq->dma_mem;
676 int status;
677
2984961c
IV		 678 if (mutex_lock_interruptible(&adapter->mbox_lock))
679 return -1;
b31c50a7
SP		 680
681 wrb = wrb_from_mbox(adapter);
682 req = embedded_payload(wrb);
6b7c5b94 683
106df1e3
SK		 684 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
685 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 686
687 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
688
6b7c5b94
SP		 689 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
690 /* 4byte eqe*/
691 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
692 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
693 __ilog2_u32(eq->len/256));
694 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
695 eq_delay_to_mult(eq_delay));
696 be_dws_cpu_to_le(req->context, sizeof(req->context));
697
698 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
699
b31c50a7 700 status = be_mbox_notify_wait(adapter);
6b7c5b94 701 if (!status) {
b31c50a7 702 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 703 eq->id = le16_to_cpu(resp->eq_id);
704 eq->created = true;
705 }
b31c50a7 706
2984961c 707 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 708 return status;
709}
710
f9449ab7 711/* Use MCC */
8788fdc2 712int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
590c391d 713 u8 type, bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 714{
b31c50a7
SP		 715 struct be_mcc_wrb *wrb;
716 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 717 int status;
718
f9449ab7 719 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 720
f9449ab7
SP		 721 wrb = wrb_from_mccq(adapter);
722 if (!wrb) {
723 status = -EBUSY;
724 goto err;
725 }
b31c50a7 726 req = embedded_payload(wrb);
6b7c5b94 727
106df1e3
SK		 728 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
729 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 730 req->type = type;
731 if (permanent) {
732 req->permanent = 1;
733 } else {
b31c50a7 734 req->if_id = cpu_to_le16((u16) if_handle);
590c391d 735 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 736 req->permanent = 0;
737 }
738
f9449ab7 739 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 740 if (!status) {
741 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
6b7c5b94 742 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 743 }
6b7c5b94 744
f9449ab7
SP		 745err:
746 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 747 return status;
748}
749
b31c50a7 750/* Uses synchronous MCCQ */
8788fdc2 751int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08 752 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 753{
b31c50a7
SP		 754 struct be_mcc_wrb *wrb;
755 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 756 int status;
757
b31c50a7
SP		 758 spin_lock_bh(&adapter->mcc_lock);
759
760 wrb = wrb_from_mccq(adapter);
713d0394
SP		 761 if (!wrb) {
762 status = -EBUSY;
763 goto err;
764 }
b31c50a7 765 req = embedded_payload(wrb);
6b7c5b94 766
106df1e3
SK		 767 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
768 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
6b7c5b94 769
f8617e08 770 req->hdr.domain = domain;
6b7c5b94
SP		 771 req->if_id = cpu_to_le32(if_id);
772 memcpy(req->mac_address, mac_addr, ETH_ALEN);
773
b31c50a7 774 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 775 if (!status) {
776 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
777 *pmac_id = le32_to_cpu(resp->pmac_id);
778 }
779
713d0394 780err:
b31c50a7 781 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 782
783 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
784 status = -EPERM;
785
6b7c5b94
SP		 786 return status;
787}
788
b31c50a7 789/* Uses synchronous MCCQ */
30128031 790int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 791{
b31c50a7
SP		 792 struct be_mcc_wrb *wrb;
793 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 794 int status;
795
30128031
SP		 796 if (pmac_id == -1)
797 return 0;
798
b31c50a7
SP		 799 spin_lock_bh(&adapter->mcc_lock);
800
801 wrb = wrb_from_mccq(adapter);
713d0394
SP		 802 if (!wrb) {
803 status = -EBUSY;
804 goto err;
805 }
b31c50a7 806 req = embedded_payload(wrb);
6b7c5b94 807
106df1e3
SK		 808 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
809 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
6b7c5b94 810
f8617e08 811 req->hdr.domain = dom;
6b7c5b94
SP		 812 req->if_id = cpu_to_le32(if_id);
813 req->pmac_id = cpu_to_le32(pmac_id);
814
b31c50a7
SP		 815 status = be_mcc_notify_wait(adapter);
816
713d0394 817err:
b31c50a7 818 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 819 return status;
820}
821
b31c50a7 822/* Uses Mbox */
10ef9ab4
SP		 823int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
824 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 825{
b31c50a7
SP		 826 struct be_mcc_wrb *wrb;
827 struct be_cmd_req_cq_create *req;
6b7c5b94 828 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 829 void *ctxt;
6b7c5b94
SP		 830 int status;
831
2984961c
IV		 832 if (mutex_lock_interruptible(&adapter->mbox_lock))
833 return -1;
b31c50a7
SP		 834
835 wrb = wrb_from_mbox(adapter);
836 req = embedded_payload(wrb);
837 ctxt = &req->context;
6b7c5b94 838
106df1e3
SK		 839 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
840 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 841
842 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38 843 if (lancer_chip(adapter)) {
8b7756ca 844 req->hdr.version = 2;
fe6d2a38 845 req->page_size = 1; /* 1 for 4K */
fe6d2a38
SP		 846 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
847 no_delay);
848 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
849 __ilog2_u32(cq->len/256));
850 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
851 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
852 ctxt, 1);
853 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
854 ctxt, eq->id);
fe6d2a38
SP		 855 } else {
856 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
857 coalesce_wm);
858 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
859 ctxt, no_delay);
860 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
861 __ilog2_u32(cq->len/256));
862 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 863 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
864 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
fe6d2a38 865 }
6b7c5b94 866
6b7c5b94
SP		 867 be_dws_cpu_to_le(ctxt, sizeof(req->context));
868
869 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
870
b31c50a7 871 status = be_mbox_notify_wait(adapter);
6b7c5b94 872 if (!status) {
b31c50a7 873 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 874 cq->id = le16_to_cpu(resp->cq_id);
875 cq->created = true;
876 }
b31c50a7 877
2984961c 878 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 879
880 return status;
881}
882
883static u32 be_encoded_q_len(int q_len)
884{
885 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
886 if (len_encoded == 16)
887 len_encoded = 0;
888 return len_encoded;
889}
890
34b1ef04 891int be_cmd_mccq_ext_create(struct be_adapter *adapter,
5fb379ee
SP		 892 struct be_queue_info *mccq,
893 struct be_queue_info *cq)
894{
b31c50a7 895 struct be_mcc_wrb *wrb;
34b1ef04 896 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 897 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 898 void *ctxt;
5fb379ee
SP		 899 int status;
900
2984961c
IV		 901 if (mutex_lock_interruptible(&adapter->mbox_lock))
902 return -1;
b31c50a7
SP		 903
904 wrb = wrb_from_mbox(adapter);
905 req = embedded_payload(wrb);
906 ctxt = &req->context;
5fb379ee 907
106df1e3
SK		 908 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
909 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
5fb379ee 910
d4a2ac3e 911 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38
SP		 912 if (lancer_chip(adapter)) {
913 req->hdr.version = 1;
914 req->cq_id = cpu_to_le16(cq->id);
915
916 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
917 be_encoded_q_len(mccq->len));
918 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
919 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
920 ctxt, cq->id);
921 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
922 ctxt, 1);
923
924 } else {
925 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
926 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
927 be_encoded_q_len(mccq->len));
928 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
929 }
5fb379ee 930
cc4ce020 931 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 932 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
5fb379ee
SP		 933 be_dws_cpu_to_le(ctxt, sizeof(req->context));
934
935 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
936
b31c50a7 937 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 938 if (!status) {
939 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
940 mccq->id = le16_to_cpu(resp->id);
941 mccq->created = true;
942 }
2984961c 943 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 944
945 return status;
946}
947
34b1ef04
SK		 948int be_cmd_mccq_org_create(struct be_adapter *adapter,
949 struct be_queue_info *mccq,
950 struct be_queue_info *cq)
951{
952 struct be_mcc_wrb *wrb;
953 struct be_cmd_req_mcc_create *req;
954 struct be_dma_mem *q_mem = &mccq->dma_mem;
955 void *ctxt;
956 int status;
957
958 if (mutex_lock_interruptible(&adapter->mbox_lock))
959 return -1;
960
961 wrb = wrb_from_mbox(adapter);
962 req = embedded_payload(wrb);
963 ctxt = &req->context;
964
106df1e3
SK		 965 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
966 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
34b1ef04
SK		 967
968 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
969
970 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
971 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
972 be_encoded_q_len(mccq->len));
973 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
974
975 be_dws_cpu_to_le(ctxt, sizeof(req->context));
976
977 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
978
979 status = be_mbox_notify_wait(adapter);
980 if (!status) {
981 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
982 mccq->id = le16_to_cpu(resp->id);
983 mccq->created = true;
984 }
985
986 mutex_unlock(&adapter->mbox_lock);
987 return status;
988}
989
990int be_cmd_mccq_create(struct be_adapter *adapter,
991 struct be_queue_info *mccq,
992 struct be_queue_info *cq)
993{
994 int status;
995
996 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
997 if (status && !lancer_chip(adapter)) {
998 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
999 "or newer to avoid conflicting priorities between NIC "
1000 "and FCoE traffic");
1001 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1002 }
1003 return status;
1004}
1005
8788fdc2 1006int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 1007 struct be_queue_info *txq,
1008 struct be_queue_info *cq)
1009{
b31c50a7
SP		 1010 struct be_mcc_wrb *wrb;
1011 struct be_cmd_req_eth_tx_create *req;
6b7c5b94 1012 struct be_dma_mem *q_mem = &txq->dma_mem;
b31c50a7 1013 void *ctxt;
6b7c5b94 1014 int status;
6b7c5b94 1015
293c4a7d
PR		 1016 spin_lock_bh(&adapter->mcc_lock);
1017
1018 wrb = wrb_from_mccq(adapter);
1019 if (!wrb) {
1020 status = -EBUSY;
1021 goto err;
1022 }
b31c50a7 1023
b31c50a7
SP		 1024 req = embedded_payload(wrb);
1025 ctxt = &req->context;
6b7c5b94 1026
106df1e3
SK		 1027 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1028 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94 1029
8b7756ca
PR		 1030 if (lancer_chip(adapter)) {
1031 req->hdr.version = 1;
1032 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1033 adapter->if_handle);
1034 }
1035
6b7c5b94
SP		 1036 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1037 req->ulp_num = BE_ULP1_NUM;
1038 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1039
b31c50a7
SP		 1040 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1041 be_encoded_q_len(txq->len));
6b7c5b94
SP		 1042 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1043 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1044
1045 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1046
1047 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1048
293c4a7d 1049 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1050 if (!status) {
1051 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1052 txq->id = le16_to_cpu(resp->cid);
1053 txq->created = true;
1054 }
b31c50a7 1055
293c4a7d
PR		 1056err:
1057 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1058
1059 return status;
1060}
1061
482c9e79 1062/* Uses MCC */
8788fdc2 1063int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94 1064 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
10ef9ab4 1065 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1066{
b31c50a7
SP		 1067 struct be_mcc_wrb *wrb;
1068 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1069 struct be_dma_mem *q_mem = &rxq->dma_mem;
1070 int status;
1071
482c9e79 1072 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1073
482c9e79
SP		 1074 wrb = wrb_from_mccq(adapter);
1075 if (!wrb) {
1076 status = -EBUSY;
1077 goto err;
1078 }
b31c50a7 1079 req = embedded_payload(wrb);
6b7c5b94 1080
106df1e3
SK		 1081 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1082 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1083
1084 req->cq_id = cpu_to_le16(cq_id);
1085 req->frag_size = fls(frag_size) - 1;
1086 req->num_pages = 2;
1087 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1088 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1089 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1090 req->rss_queue = cpu_to_le32(rss);
1091
482c9e79 1092 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1093 if (!status) {
1094 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1095 rxq->id = le16_to_cpu(resp->id);
1096 rxq->created = true;
3abcdeda 1097 *rss_id = resp->rss_id;
6b7c5b94 1098 }
b31c50a7 1099
482c9e79
SP		 1100err:
1101 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1102 return status;
1103}
1104
b31c50a7
SP		 1105/* Generic destroyer function for all types of queues
1106 * Uses Mbox
1107 */
8788fdc2 1108int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94
SP		 1109 int queue_type)
1110{
b31c50a7
SP		 1111 struct be_mcc_wrb *wrb;
1112 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1113 u8 subsys = 0, opcode = 0;
1114 int status;
1115
2984961c
IV		 1116 if (mutex_lock_interruptible(&adapter->mbox_lock))
1117 return -1;
6b7c5b94 1118
b31c50a7
SP		 1119 wrb = wrb_from_mbox(adapter);
1120 req = embedded_payload(wrb);
1121
6b7c5b94
SP		 1122 switch (queue_type) {
1123 case QTYPE_EQ:
1124 subsys = CMD_SUBSYSTEM_COMMON;
1125 opcode = OPCODE_COMMON_EQ_DESTROY;
1126 break;
1127 case QTYPE_CQ:
1128 subsys = CMD_SUBSYSTEM_COMMON;
1129 opcode = OPCODE_COMMON_CQ_DESTROY;
1130 break;
1131 case QTYPE_TXQ:
1132 subsys = CMD_SUBSYSTEM_ETH;
1133 opcode = OPCODE_ETH_TX_DESTROY;
1134 break;
1135 case QTYPE_RXQ:
1136 subsys = CMD_SUBSYSTEM_ETH;
1137 opcode = OPCODE_ETH_RX_DESTROY;
1138 break;
5fb379ee
SP		 1139 case QTYPE_MCCQ:
1140 subsys = CMD_SUBSYSTEM_COMMON;
1141 opcode = OPCODE_COMMON_MCC_DESTROY;
1142 break;
6b7c5b94 1143 default:
5f0b849e 1144 BUG();
6b7c5b94 1145 }
d744b44e 1146
106df1e3
SK		 1147 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1148 NULL);
6b7c5b94
SP		 1149 req->id = cpu_to_le16(q->id);
1150
b31c50a7 1151 status = be_mbox_notify_wait(adapter);
482c9e79
SP		 1152 if (!status)
1153 q->created = false;
5f0b849e 1154
2984961c 1155 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1156 return status;
1157}
6b7c5b94 1158
482c9e79
SP		 1159/* Uses MCC */
1160int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1161{
1162 struct be_mcc_wrb *wrb;
1163 struct be_cmd_req_q_destroy *req;
1164 int status;
1165
1166 spin_lock_bh(&adapter->mcc_lock);
1167
1168 wrb = wrb_from_mccq(adapter);
1169 if (!wrb) {
1170 status = -EBUSY;
1171 goto err;
1172 }
1173 req = embedded_payload(wrb);
1174
106df1e3
SK		 1175 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1176 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1177 req->id = cpu_to_le16(q->id);
1178
1179 status = be_mcc_notify_wait(adapter);
1180 if (!status)
1181 q->created = false;
1182
1183err:
1184 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1185 return status;
1186}
1187
b31c50a7 1188/* Create an rx filtering policy configuration on an i/f
f9449ab7 1189 * Uses MCCQ
b31c50a7 1190 */
73d540f2 1191int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1192 u32 *if_handle, u32 domain)
6b7c5b94 1193{
b31c50a7
SP		 1194 struct be_mcc_wrb *wrb;
1195 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1196 int status;
1197
f9449ab7 1198 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1199
f9449ab7
SP		 1200 wrb = wrb_from_mccq(adapter);
1201 if (!wrb) {
1202 status = -EBUSY;
1203 goto err;
1204 }
b31c50a7 1205 req = embedded_payload(wrb);
6b7c5b94 1206
106df1e3
SK		 1207 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1208 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
ba343c77 1209 req->hdr.domain = domain;
73d540f2
SP		 1210 req->capability_flags = cpu_to_le32(cap_flags);
1211 req->enable_flags = cpu_to_le32(en_flags);
1578e777
PR		 1212
1213 req->pmac_invalid = true;
6b7c5b94 1214
f9449ab7 1215 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1216 if (!status) {
1217 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1218 *if_handle = le32_to_cpu(resp->interface_id);
6b7c5b94
SP		 1219 }
1220
f9449ab7
SP		 1221err:
1222 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1223 return status;
1224}
1225
f9449ab7 1226/* Uses MCCQ */
30128031 1227int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1228{
b31c50a7
SP		 1229 struct be_mcc_wrb *wrb;
1230 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1231 int status;
1232
30128031 1233 if (interface_id == -1)
f9449ab7 1234 return 0;
b31c50a7 1235
f9449ab7
SP		 1236 spin_lock_bh(&adapter->mcc_lock);
1237
1238 wrb = wrb_from_mccq(adapter);
1239 if (!wrb) {
1240 status = -EBUSY;
1241 goto err;
1242 }
b31c50a7 1243 req = embedded_payload(wrb);
6b7c5b94 1244
106df1e3
SK		 1245 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1246 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
658681f7 1247 req->hdr.domain = domain;
6b7c5b94 1248 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1249
f9449ab7
SP		 1250 status = be_mcc_notify_wait(adapter);
1251err:
1252 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1253 return status;
1254}
1255
1256/* Get stats is a non embedded command: the request is not embedded inside
1257 * WRB but is a separate dma memory block
b31c50a7 1258 * Uses asynchronous MCC
6b7c5b94 1259 */
8788fdc2 1260int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1261{
b31c50a7 1262 struct be_mcc_wrb *wrb;
89a88ab8 1263 struct be_cmd_req_hdr *hdr;
713d0394 1264 int status = 0;
6b7c5b94 1265
b31c50a7 1266 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1267
b31c50a7 1268 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1269 if (!wrb) {
1270 status = -EBUSY;
1271 goto err;
1272 }
89a88ab8 1273 hdr = nonemb_cmd->va;
6b7c5b94 1274
106df1e3
SK		 1275 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1276 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
89a88ab8
AK		 1277
1278 if (adapter->generation == BE_GEN3)
1279 hdr->version = 1;
1280
b31c50a7 1281 be_mcc_notify(adapter);
b2aebe6d 1282 adapter->stats_cmd_sent = true;
6b7c5b94 1283
713d0394 1284err:
b31c50a7 1285 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1286 return status;
6b7c5b94
SP		 1287}
1288
005d5696
SX		 1289/* Lancer Stats */
1290int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1291 struct be_dma_mem *nonemb_cmd)
1292{
1293
1294 struct be_mcc_wrb *wrb;
1295 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1296 int status = 0;
1297
1298 spin_lock_bh(&adapter->mcc_lock);
1299
1300 wrb = wrb_from_mccq(adapter);
1301 if (!wrb) {
1302 status = -EBUSY;
1303 goto err;
1304 }
1305 req = nonemb_cmd->va;
005d5696 1306
106df1e3
SK		 1307 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1308 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1309 nonemb_cmd);
005d5696 1310
d51ebd33 1311 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1312 req->cmd_params.params.reset_stats = 0;
1313
005d5696
SX		 1314 be_mcc_notify(adapter);
1315 adapter->stats_cmd_sent = true;
1316
1317err:
1318 spin_unlock_bh(&adapter->mcc_lock);
1319 return status;
1320}
1321
b31c50a7 1322/* Uses synchronous mcc */
ea172a01 1323int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
b236916a 1324 u16 *link_speed, u8 *link_status, u32 dom)
6b7c5b94 1325{
b31c50a7
SP		 1326 struct be_mcc_wrb *wrb;
1327 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1328 int status;
1329
b31c50a7
SP		 1330 spin_lock_bh(&adapter->mcc_lock);
1331
b236916a
AK		 1332 if (link_status)
1333 *link_status = LINK_DOWN;
1334
b31c50a7 1335 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1336 if (!wrb) {
1337 status = -EBUSY;
1338 goto err;
1339 }
b31c50a7 1340 req = embedded_payload(wrb);
a8f447bd 1341
57cd80d4
PR		 1342 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1343 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1344
b236916a 1345 if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
daad6167
PR		 1346 req->hdr.version = 1;
1347
57cd80d4 1348 req->hdr.domain = dom;
6b7c5b94 1349
b31c50a7 1350 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1351 if (!status) {
1352 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
0388f251 1353 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
b236916a
AK		 1354 if (link_speed)
1355 *link_speed = le16_to_cpu(resp->link_speed);
f9449ab7
SP		 1356 if (mac_speed)
1357 *mac_speed = resp->mac_speed;
0388f251 1358 }
b236916a
AK		 1359 if (link_status)
1360 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1361 }
1362
713d0394 1363err:
b31c50a7 1364 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1365 return status;
1366}
1367
609ff3bb
AK		 1368/* Uses synchronous mcc */
1369int be_cmd_get_die_temperature(struct be_adapter *adapter)
1370{
1371 struct be_mcc_wrb *wrb;
1372 struct be_cmd_req_get_cntl_addnl_attribs *req;
1373 int status;
1374
1375 spin_lock_bh(&adapter->mcc_lock);
1376
1377 wrb = wrb_from_mccq(adapter);
1378 if (!wrb) {
1379 status = -EBUSY;
1380 goto err;
1381 }
1382 req = embedded_payload(wrb);
1383
106df1e3
SK		 1384 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1385 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1386 wrb, NULL);
609ff3bb 1387
3de09455 1388 be_mcc_notify(adapter);
609ff3bb
AK		 1389
1390err:
1391 spin_unlock_bh(&adapter->mcc_lock);
1392 return status;
1393}
1394
311fddc7
SK		 1395/* Uses synchronous mcc */
1396int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1397{
1398 struct be_mcc_wrb *wrb;
1399 struct be_cmd_req_get_fat *req;
1400 int status;
1401
1402 spin_lock_bh(&adapter->mcc_lock);
1403
1404 wrb = wrb_from_mccq(adapter);
1405 if (!wrb) {
1406 status = -EBUSY;
1407 goto err;
1408 }
1409 req = embedded_payload(wrb);
1410
106df1e3
SK		 1411 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1412 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
311fddc7
SK		 1413 req->fat_operation = cpu_to_le32(QUERY_FAT);
1414 status = be_mcc_notify_wait(adapter);
1415 if (!status) {
1416 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1417 if (log_size && resp->log_size)
fe2a70ee
SK		 1418 *log_size = le32_to_cpu(resp->log_size) -
1419 sizeof(u32);
311fddc7
SK		 1420 }
1421err:
1422 spin_unlock_bh(&adapter->mcc_lock);
1423 return status;
1424}
1425
1426void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1427{
1428 struct be_dma_mem get_fat_cmd;
1429 struct be_mcc_wrb *wrb;
1430 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1431 u32 offset = 0, total_size, buf_size,
1432 log_offset = sizeof(u32), payload_len;
311fddc7
SK		 1433 int status;
1434
1435 if (buf_len == 0)
1436 return;
1437
1438 total_size = buf_len;
1439
fe2a70ee
SK		 1440 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1441 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1442 get_fat_cmd.size,
1443 &get_fat_cmd.dma);
1444 if (!get_fat_cmd.va) {
1445 status = -ENOMEM;
1446 dev_err(&adapter->pdev->dev,
1447 "Memory allocation failure while retrieving FAT data\n");
1448 return;
1449 }
1450
311fddc7
SK		 1451 spin_lock_bh(&adapter->mcc_lock);
1452
311fddc7
SK		 1453 while (total_size) {
1454 buf_size = min(total_size, (u32)60*1024);
1455 total_size -= buf_size;
1456
fe2a70ee
SK		 1457 wrb = wrb_from_mccq(adapter);
1458 if (!wrb) {
1459 status = -EBUSY;
311fddc7
SK		 1460 goto err;
1461 }
1462 req = get_fat_cmd.va;
311fddc7 1463
fe2a70ee 1464 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3
SK		 1465 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1466 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1467 &get_fat_cmd);
311fddc7
SK		 1468
1469 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1470 req->read_log_offset = cpu_to_le32(log_offset);
1471 req->read_log_length = cpu_to_le32(buf_size);
1472 req->data_buffer_size = cpu_to_le32(buf_size);
1473
1474 status = be_mcc_notify_wait(adapter);
1475 if (!status) {
1476 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1477 memcpy(buf + offset,
1478 resp->data_buffer,
92aa9214 1479 le32_to_cpu(resp->read_log_length));
fe2a70ee 1480 } else {
311fddc7 1481 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1482 goto err;
1483 }
311fddc7
SK		 1484 offset += buf_size;
1485 log_offset += buf_size;
1486 }
1487err:
fe2a70ee
SK		 1488 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1489 get_fat_cmd.va,
1490 get_fat_cmd.dma);
311fddc7
SK		 1491 spin_unlock_bh(&adapter->mcc_lock);
1492}
1493
04b71175
SP		 1494/* Uses synchronous mcc */
1495int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1496 char *fw_on_flash)
6b7c5b94 1497{
b31c50a7
SP		 1498 struct be_mcc_wrb *wrb;
1499 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1500 int status;
1501
04b71175 1502 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1503
04b71175
SP		 1504 wrb = wrb_from_mccq(adapter);
1505 if (!wrb) {
1506 status = -EBUSY;
1507 goto err;
1508 }
6b7c5b94 1509
04b71175 1510 req = embedded_payload(wrb);
6b7c5b94 1511
106df1e3
SK		 1512 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1513 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
04b71175 1514 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1515 if (!status) {
1516 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
04b71175
SP		 1517 strcpy(fw_ver, resp->firmware_version_string);
1518 if (fw_on_flash)
1519 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
6b7c5b94 1520 }
04b71175
SP		 1521err:
1522 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1523 return status;
1524}
1525
b31c50a7
SP		 1526/* set the EQ delay interval of an EQ to specified value
1527 * Uses async mcc
1528 */
8788fdc2 1529int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
6b7c5b94 1530{
b31c50a7
SP		 1531 struct be_mcc_wrb *wrb;
1532 struct be_cmd_req_modify_eq_delay *req;
713d0394 1533 int status = 0;
6b7c5b94 1534
b31c50a7
SP		 1535 spin_lock_bh(&adapter->mcc_lock);
1536
1537 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1538 if (!wrb) {
1539 status = -EBUSY;
1540 goto err;
1541 }
b31c50a7 1542 req = embedded_payload(wrb);
6b7c5b94 1543
106df1e3
SK		 1544 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1545 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1546
1547 req->num_eq = cpu_to_le32(1);
1548 req->delay[0].eq_id = cpu_to_le32(eq_id);
1549 req->delay[0].phase = 0;
1550 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1551
b31c50a7 1552 be_mcc_notify(adapter);
6b7c5b94 1553
713d0394 1554err:
b31c50a7 1555 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1556 return status;
6b7c5b94
SP		 1557}
1558
b31c50a7 1559/* Uses sycnhronous mcc */
8788fdc2 1560int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
6b7c5b94
SP		 1561 u32 num, bool untagged, bool promiscuous)
1562{
b31c50a7
SP		 1563 struct be_mcc_wrb *wrb;
1564 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1565 int status;
1566
b31c50a7
SP		 1567 spin_lock_bh(&adapter->mcc_lock);
1568
1569 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1570 if (!wrb) {
1571 status = -EBUSY;
1572 goto err;
1573 }
b31c50a7 1574 req = embedded_payload(wrb);
6b7c5b94 1575
106df1e3
SK		 1576 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1577 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1578
1579 req->interface_id = if_id;
1580 req->promiscuous = promiscuous;
1581 req->untagged = untagged;
1582 req->num_vlan = num;
1583 if (!promiscuous) {
1584 memcpy(req->normal_vlan, vtag_array,
1585 req->num_vlan * sizeof(vtag_array[0]));
1586 }
1587
b31c50a7 1588 status = be_mcc_notify_wait(adapter);
6b7c5b94 1589
713d0394 1590err:
b31c50a7 1591 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1592 return status;
1593}
1594
5b8821b7 1595int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1596{
6ac7b687 1597 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1598 struct be_dma_mem *mem = &adapter->rx_filter;
1599 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1600 int status;
6b7c5b94 1601
8788fdc2 1602 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1603
b31c50a7 1604 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1605 if (!wrb) {
1606 status = -EBUSY;
1607 goto err;
1608 }
5b8821b7 1609 memset(req, 0, sizeof(*req));
106df1e3
SK		 1610 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1611 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1612 wrb, mem);
6b7c5b94 1613
5b8821b7
SP		 1614 req->if_id = cpu_to_le32(adapter->if_handle);
1615 if (flags & IFF_PROMISC) {
1616 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1617 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1618 if (value == ON)
1619 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
8e7d3f68 1620 BE_IF_FLAGS_VLAN_PROMISCUOUS);
5b8821b7
SP		 1621 } else if (flags & IFF_ALLMULTI) {
1622 req->if_flags_mask = req->if_flags =
8e7d3f68 1623 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7 1624 } else {
22bedad3 1625 struct netdev_hw_addr *ha;
5b8821b7 1626 int i = 0;
24307eef 1627
8e7d3f68
SP		 1628 req->if_flags_mask = req->if_flags =
1629 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1610c79f
PR		 1630
1631 /* Reset mcast promisc mode if already set by setting mask
1632 * and not setting flags field
1633 */
1634 req->if_flags_mask |=
1635 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1636
016f97b1 1637 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1638 netdev_for_each_mc_addr(ha, adapter->netdev)
1639 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1640 }
1641
0d1d5875 1642 status = be_mcc_notify_wait(adapter);
713d0394 1643err:
8788fdc2 1644 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1645 return status;
6b7c5b94
SP		 1646}
1647
b31c50a7 1648/* Uses synchrounous mcc */
8788fdc2 1649int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1650{
b31c50a7
SP		 1651 struct be_mcc_wrb *wrb;
1652 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1653 int status;
1654
b31c50a7 1655 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1656
b31c50a7 1657 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1658 if (!wrb) {
1659 status = -EBUSY;
1660 goto err;
1661 }
b31c50a7 1662 req = embedded_payload(wrb);
6b7c5b94 1663
106df1e3
SK		 1664 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1665 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1666
1667 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1668 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1669
b31c50a7 1670 status = be_mcc_notify_wait(adapter);
6b7c5b94 1671
713d0394 1672err:
b31c50a7 1673 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1674 return status;
1675}
1676
b31c50a7 1677/* Uses sycn mcc */
8788fdc2 1678int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1679{
b31c50a7
SP		 1680 struct be_mcc_wrb *wrb;
1681 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1682 int status;
1683
b31c50a7 1684 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1685
b31c50a7 1686 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1687 if (!wrb) {
1688 status = -EBUSY;
1689 goto err;
1690 }
b31c50a7 1691 req = embedded_payload(wrb);
6b7c5b94 1692
106df1e3
SK		 1693 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1694 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94 1695
b31c50a7 1696 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1697 if (!status) {
1698 struct be_cmd_resp_get_flow_control *resp =
1699 embedded_payload(wrb);
1700 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1701 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1702 }
1703
713d0394 1704err:
b31c50a7 1705 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1706 return status;
1707}
1708
b31c50a7 1709/* Uses mbox */
3abcdeda
SP		 1710int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1711 u32 *mode, u32 *caps)
6b7c5b94 1712{
b31c50a7
SP		 1713 struct be_mcc_wrb *wrb;
1714 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 1715 int status;
1716
2984961c
IV		 1717 if (mutex_lock_interruptible(&adapter->mbox_lock))
1718 return -1;
6b7c5b94 1719
b31c50a7
SP		 1720 wrb = wrb_from_mbox(adapter);
1721 req = embedded_payload(wrb);
6b7c5b94 1722
106df1e3
SK		 1723 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1724 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94 1725
b31c50a7 1726 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 1727 if (!status) {
1728 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1729 *port_num = le32_to_cpu(resp->phys_port);
3486be29 1730 *mode = le32_to_cpu(resp->function_mode);
3abcdeda 1731 *caps = le32_to_cpu(resp->function_caps);
6b7c5b94
SP		 1732 }
1733
2984961c 1734 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1735 return status;
1736}
14074eab 1737
b31c50a7 1738/* Uses mbox */
14074eab 1739int be_cmd_reset_function(struct be_adapter *adapter)
1740{
b31c50a7
SP		 1741 struct be_mcc_wrb *wrb;
1742 struct be_cmd_req_hdr *req;
14074eab 1743 int status;
1744
bf99e50d
PR		 1745 if (lancer_chip(adapter)) {
1746 status = lancer_wait_ready(adapter);
1747 if (!status) {
1748 iowrite32(SLI_PORT_CONTROL_IP_MASK,
1749 adapter->db + SLIPORT_CONTROL_OFFSET);
1750 status = lancer_test_and_set_rdy_state(adapter);
1751 }
1752 if (status) {
1753 dev_err(&adapter->pdev->dev,
1754 "Adapter in non recoverable error\n");
1755 }
1756 return status;
1757 }
1758
2984961c
IV		 1759 if (mutex_lock_interruptible(&adapter->mbox_lock))
1760 return -1;
14074eab 1761
b31c50a7
SP		 1762 wrb = wrb_from_mbox(adapter);
1763 req = embedded_payload(wrb);
14074eab 1764
106df1e3
SK		 1765 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1766 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
14074eab 1767
b31c50a7 1768 status = be_mbox_notify_wait(adapter);
14074eab 1769
2984961c 1770 mutex_unlock(&adapter->mbox_lock);
14074eab 1771 return status;
1772}
84517482 1773
3abcdeda
SP		 1774int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1775{
1776 struct be_mcc_wrb *wrb;
1777 struct be_cmd_req_rss_config *req;
65f8584e
PR		 1778 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1779 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1780 0x3ea83c02, 0x4a110304};
3abcdeda
SP		 1781 int status;
1782
2984961c
IV		 1783 if (mutex_lock_interruptible(&adapter->mbox_lock))
1784 return -1;
3abcdeda
SP		 1785
1786 wrb = wrb_from_mbox(adapter);
1787 req = embedded_payload(wrb);
1788
106df1e3
SK		 1789 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1790 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 1791
1792 req->if_id = cpu_to_le32(adapter->if_handle);
1ca7ba92
SP		 1793 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1794 RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
3abcdeda
SP		 1795 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1796 memcpy(req->cpu_table, rsstable, table_size);
1797 memcpy(req->hash, myhash, sizeof(myhash));
1798 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1799
1800 status = be_mbox_notify_wait(adapter);
1801
2984961c 1802 mutex_unlock(&adapter->mbox_lock);
3abcdeda
SP		 1803 return status;
1804}
1805
fad9ab2c
SB		 1806/* Uses sync mcc */
1807int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1808 u8 bcn, u8 sts, u8 state)
1809{
1810 struct be_mcc_wrb *wrb;
1811 struct be_cmd_req_enable_disable_beacon *req;
1812 int status;
1813
1814 spin_lock_bh(&adapter->mcc_lock);
1815
1816 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1817 if (!wrb) {
1818 status = -EBUSY;
1819 goto err;
1820 }
fad9ab2c
SB		 1821 req = embedded_payload(wrb);
1822
106df1e3
SK		 1823 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1824 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1825
1826 req->port_num = port_num;
1827 req->beacon_state = state;
1828 req->beacon_duration = bcn;
1829 req->status_duration = sts;
1830
1831 status = be_mcc_notify_wait(adapter);
1832
713d0394 1833err:
fad9ab2c
SB		 1834 spin_unlock_bh(&adapter->mcc_lock);
1835 return status;
1836}
1837
1838/* Uses sync mcc */
1839int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1840{
1841 struct be_mcc_wrb *wrb;
1842 struct be_cmd_req_get_beacon_state *req;
1843 int status;
1844
1845 spin_lock_bh(&adapter->mcc_lock);
1846
1847 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1848 if (!wrb) {
1849 status = -EBUSY;
1850 goto err;
1851 }
fad9ab2c
SB		 1852 req = embedded_payload(wrb);
1853
106df1e3
SK		 1854 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1855 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1856
1857 req->port_num = port_num;
1858
1859 status = be_mcc_notify_wait(adapter);
1860 if (!status) {
1861 struct be_cmd_resp_get_beacon_state *resp =
1862 embedded_payload(wrb);
1863 *state = resp->beacon_state;
1864 }
1865
713d0394 1866err:
fad9ab2c
SB		 1867 spin_unlock_bh(&adapter->mcc_lock);
1868 return status;
1869}
1870
485bf569 1871int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 1872 u32 data_size, u32 data_offset,
1873 const char *obj_name, u32 *data_written,
1874 u8 *change_status, u8 *addn_status)
485bf569
SN		 1875{
1876 struct be_mcc_wrb *wrb;
1877 struct lancer_cmd_req_write_object *req;
1878 struct lancer_cmd_resp_write_object *resp;
1879 void *ctxt = NULL;
1880 int status;
1881
1882 spin_lock_bh(&adapter->mcc_lock);
1883 adapter->flash_status = 0;
1884
1885 wrb = wrb_from_mccq(adapter);
1886 if (!wrb) {
1887 status = -EBUSY;
1888 goto err_unlock;
1889 }
1890
1891 req = embedded_payload(wrb);
1892
106df1e3 1893 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
485bf569 1894 OPCODE_COMMON_WRITE_OBJECT,
106df1e3
SK		 1895 sizeof(struct lancer_cmd_req_write_object), wrb,
1896 NULL);
485bf569
SN		 1897
1898 ctxt = &req->context;
1899 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1900 write_length, ctxt, data_size);
1901
1902 if (data_size == 0)
1903 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1904 eof, ctxt, 1);
1905 else
1906 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1907 eof, ctxt, 0);
1908
1909 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1910 req->write_offset = cpu_to_le32(data_offset);
1911 strcpy(req->object_name, obj_name);
1912 req->descriptor_count = cpu_to_le32(1);
1913 req->buf_len = cpu_to_le32(data_size);
1914 req->addr_low = cpu_to_le32((cmd->dma +
1915 sizeof(struct lancer_cmd_req_write_object))
1916 & 0xFFFFFFFF);
1917 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1918 sizeof(struct lancer_cmd_req_write_object)));
1919
1920 be_mcc_notify(adapter);
1921 spin_unlock_bh(&adapter->mcc_lock);
1922
1923 if (!wait_for_completion_timeout(&adapter->flash_compl,
804c7515 1924 msecs_to_jiffies(30000)))
485bf569
SN		 1925 status = -1;
1926 else
1927 status = adapter->flash_status;
1928
1929 resp = embedded_payload(wrb);
f67ef7ba 1930 if (!status) {
485bf569 1931 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 1932 *change_status = resp->change_status;
1933 } else {
485bf569 1934 *addn_status = resp->additional_status;
f67ef7ba 1935 }
485bf569
SN		 1936
1937 return status;
1938
1939err_unlock:
1940 spin_unlock_bh(&adapter->mcc_lock);
1941 return status;
1942}
1943
de49bd5a
PR		 1944int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1945 u32 data_size, u32 data_offset, const char *obj_name,
1946 u32 *data_read, u32 *eof, u8 *addn_status)
1947{
1948 struct be_mcc_wrb *wrb;
1949 struct lancer_cmd_req_read_object *req;
1950 struct lancer_cmd_resp_read_object *resp;
1951 int status;
1952
1953 spin_lock_bh(&adapter->mcc_lock);
1954
1955 wrb = wrb_from_mccq(adapter);
1956 if (!wrb) {
1957 status = -EBUSY;
1958 goto err_unlock;
1959 }
1960
1961 req = embedded_payload(wrb);
1962
1963 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1964 OPCODE_COMMON_READ_OBJECT,
1965 sizeof(struct lancer_cmd_req_read_object), wrb,
1966 NULL);
1967
1968 req->desired_read_len = cpu_to_le32(data_size);
1969 req->read_offset = cpu_to_le32(data_offset);
1970 strcpy(req->object_name, obj_name);
1971 req->descriptor_count = cpu_to_le32(1);
1972 req->buf_len = cpu_to_le32(data_size);
1973 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1974 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1975
1976 status = be_mcc_notify_wait(adapter);
1977
1978 resp = embedded_payload(wrb);
1979 if (!status) {
1980 *data_read = le32_to_cpu(resp->actual_read_len);
1981 *eof = le32_to_cpu(resp->eof);
1982 } else {
1983 *addn_status = resp->additional_status;
1984 }
1985
1986err_unlock:
1987 spin_unlock_bh(&adapter->mcc_lock);
1988 return status;
1989}
1990
84517482
AK		 1991int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1992 u32 flash_type, u32 flash_opcode, u32 buf_size)
1993{
b31c50a7 1994 struct be_mcc_wrb *wrb;
3f0d4560 1995 struct be_cmd_write_flashrom *req;
84517482
AK		 1996 int status;
1997
b31c50a7 1998 spin_lock_bh(&adapter->mcc_lock);
dd131e76 1999 adapter->flash_status = 0;
b31c50a7
SP		 2000
2001 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2002 if (!wrb) {
2003 status = -EBUSY;
2892d9c2 2004 goto err_unlock;
713d0394
SP		 2005 }
2006 req = cmd->va;
84517482 2007
106df1e3
SK		 2008 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2009 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
84517482
AK		 2010
2011 req->params.op_type = cpu_to_le32(flash_type);
2012 req->params.op_code = cpu_to_le32(flash_opcode);
2013 req->params.data_buf_size = cpu_to_le32(buf_size);
2014
dd131e76
SB		 2015 be_mcc_notify(adapter);
2016 spin_unlock_bh(&adapter->mcc_lock);
2017
2018 if (!wait_for_completion_timeout(&adapter->flash_compl,
e2edb7d5 2019 msecs_to_jiffies(40000)))
dd131e76
SB		 2020 status = -1;
2021 else
2022 status = adapter->flash_status;
84517482 2023
2892d9c2
DC		 2024 return status;
2025
2026err_unlock:
2027 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2028 return status;
2029}
fa9a6fed 2030
3f0d4560
AK		 2031int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2032 int offset)
fa9a6fed
SB		 2033{
2034 struct be_mcc_wrb *wrb;
2035 struct be_cmd_write_flashrom *req;
2036 int status;
2037
2038 spin_lock_bh(&adapter->mcc_lock);
2039
2040 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2041 if (!wrb) {
2042 status = -EBUSY;
2043 goto err;
2044 }
fa9a6fed
SB		 2045 req = embedded_payload(wrb);
2046
106df1e3
SK		 2047 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2048 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
fa9a6fed 2049
c165541e 2050 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
fa9a6fed 2051 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710
AK		 2052 req->params.offset = cpu_to_le32(offset);
2053 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2054
2055 status = be_mcc_notify_wait(adapter);
2056 if (!status)
2057 memcpy(flashed_crc, req->params.data_buf, 4);
2058
713d0394 2059err:
fa9a6fed
SB		 2060 spin_unlock_bh(&adapter->mcc_lock);
2061 return status;
2062}
71d8d1b5 2063
c196b02c 2064int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
71d8d1b5
AK		 2065 struct be_dma_mem *nonemb_cmd)
2066{
2067 struct be_mcc_wrb *wrb;
2068 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2069 int status;
2070
2071 spin_lock_bh(&adapter->mcc_lock);
2072
2073 wrb = wrb_from_mccq(adapter);
2074 if (!wrb) {
2075 status = -EBUSY;
2076 goto err;
2077 }
2078 req = nonemb_cmd->va;
71d8d1b5 2079
106df1e3
SK		 2080 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2081 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2082 nonemb_cmd);
71d8d1b5
AK		 2083 memcpy(req->magic_mac, mac, ETH_ALEN);
2084
71d8d1b5
AK		 2085 status = be_mcc_notify_wait(adapter);
2086
2087err:
2088 spin_unlock_bh(&adapter->mcc_lock);
2089 return status;
2090}
ff33a6e2 2091
fced9999
SB		 2092int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2093 u8 loopback_type, u8 enable)
2094{
2095 struct be_mcc_wrb *wrb;
2096 struct be_cmd_req_set_lmode *req;
2097 int status;
2098
2099 spin_lock_bh(&adapter->mcc_lock);
2100
2101 wrb = wrb_from_mccq(adapter);
2102 if (!wrb) {
2103 status = -EBUSY;
2104 goto err;
2105 }
2106
2107 req = embedded_payload(wrb);
2108
106df1e3
SK		 2109 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2110 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2111 NULL);
fced9999
SB		 2112
2113 req->src_port = port_num;
2114 req->dest_port = port_num;
2115 req->loopback_type = loopback_type;
2116 req->loopback_state = enable;
2117
2118 status = be_mcc_notify_wait(adapter);
2119err:
2120 spin_unlock_bh(&adapter->mcc_lock);
2121 return status;
2122}
2123
ff33a6e2
S		 2124int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2125 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2126{
2127 struct be_mcc_wrb *wrb;
2128 struct be_cmd_req_loopback_test *req;
2129 int status;
2130
2131 spin_lock_bh(&adapter->mcc_lock);
2132
2133 wrb = wrb_from_mccq(adapter);
2134 if (!wrb) {
2135 status = -EBUSY;
2136 goto err;
2137 }
2138
2139 req = embedded_payload(wrb);
2140
106df1e3
SK		 2141 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2142 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
3ffd0515 2143 req->hdr.timeout = cpu_to_le32(4);
ff33a6e2
S		 2144
2145 req->pattern = cpu_to_le64(pattern);
2146 req->src_port = cpu_to_le32(port_num);
2147 req->dest_port = cpu_to_le32(port_num);
2148 req->pkt_size = cpu_to_le32(pkt_size);
2149 req->num_pkts = cpu_to_le32(num_pkts);
2150 req->loopback_type = cpu_to_le32(loopback_type);
2151
2152 status = be_mcc_notify_wait(adapter);
2153 if (!status) {
2154 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2155 status = le32_to_cpu(resp->status);
2156 }
2157
2158err:
2159 spin_unlock_bh(&adapter->mcc_lock);
2160 return status;
2161}
2162
2163int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2164 u32 byte_cnt, struct be_dma_mem *cmd)
2165{
2166 struct be_mcc_wrb *wrb;
2167 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2168 int status;
2169 int i, j = 0;
2170
2171 spin_lock_bh(&adapter->mcc_lock);
2172
2173 wrb = wrb_from_mccq(adapter);
2174 if (!wrb) {
2175 status = -EBUSY;
2176 goto err;
2177 }
2178 req = cmd->va;
106df1e3
SK		 2179 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2180 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
ff33a6e2
S		 2181
2182 req->pattern = cpu_to_le64(pattern);
2183 req->byte_count = cpu_to_le32(byte_cnt);
2184 for (i = 0; i < byte_cnt; i++) {
2185 req->snd_buff[i] = (u8)(pattern >> (j*8));
2186 j++;
2187 if (j > 7)
2188 j = 0;
2189 }
2190
2191 status = be_mcc_notify_wait(adapter);
2192
2193 if (!status) {
2194 struct be_cmd_resp_ddrdma_test *resp;
2195 resp = cmd->va;
2196 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2197 resp->snd_err) {
2198 status = -1;
2199 }
2200 }
2201
2202err:
2203 spin_unlock_bh(&adapter->mcc_lock);
2204 return status;
2205}
368c0ca2 2206
c196b02c 2207int be_cmd_get_seeprom_data(struct be_adapter *adapter,
368c0ca2
SB		 2208 struct be_dma_mem *nonemb_cmd)
2209{
2210 struct be_mcc_wrb *wrb;
2211 struct be_cmd_req_seeprom_read *req;
2212 struct be_sge *sge;
2213 int status;
2214
2215 spin_lock_bh(&adapter->mcc_lock);
2216
2217 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2218 if (!wrb) {
2219 status = -EBUSY;
2220 goto err;
2221 }
368c0ca2
SB		 2222 req = nonemb_cmd->va;
2223 sge = nonembedded_sgl(wrb);
2224
106df1e3
SK		 2225 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2226 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2227 nonemb_cmd);
368c0ca2
SB		 2228
2229 status = be_mcc_notify_wait(adapter);
2230
e45ff01d 2231err:
368c0ca2
SB		 2232 spin_unlock_bh(&adapter->mcc_lock);
2233 return status;
2234}
ee3cb629 2235
42f11cf2 2236int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2237{
2238 struct be_mcc_wrb *wrb;
2239 struct be_cmd_req_get_phy_info *req;
306f1348 2240 struct be_dma_mem cmd;
ee3cb629
AK		 2241 int status;
2242
2243 spin_lock_bh(&adapter->mcc_lock);
2244
2245 wrb = wrb_from_mccq(adapter);
2246 if (!wrb) {
2247 status = -EBUSY;
2248 goto err;
2249 }
306f1348
SP		 2250 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2251 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2252 &cmd.dma);
2253 if (!cmd.va) {
2254 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2255 status = -ENOMEM;
2256 goto err;
2257 }
ee3cb629 2258
306f1348 2259 req = cmd.va;
ee3cb629 2260
106df1e3
SK		 2261 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2262 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2263 wrb, &cmd);
ee3cb629
AK		 2264
2265 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2266 if (!status) {
2267 struct be_phy_info *resp_phy_info =
2268 cmd.va + sizeof(struct be_cmd_req_hdr);
42f11cf2
AK		 2269 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2270 adapter->phy.interface_type =
306f1348 2271 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2272 adapter->phy.auto_speeds_supported =
2273 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2274 adapter->phy.fixed_speeds_supported =
2275 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2276 adapter->phy.misc_params =
2277 le32_to_cpu(resp_phy_info->misc_params);
306f1348
SP		 2278 }
2279 pci_free_consistent(adapter->pdev, cmd.size,
2280 cmd.va, cmd.dma);
ee3cb629
AK		 2281err:
2282 spin_unlock_bh(&adapter->mcc_lock);
2283 return status;
2284}
e1d18735
AK		 2285
2286int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2287{
2288 struct be_mcc_wrb *wrb;
2289 struct be_cmd_req_set_qos *req;
2290 int status;
2291
2292 spin_lock_bh(&adapter->mcc_lock);
2293
2294 wrb = wrb_from_mccq(adapter);
2295 if (!wrb) {
2296 status = -EBUSY;
2297 goto err;
2298 }
2299
2300 req = embedded_payload(wrb);
2301
106df1e3
SK		 2302 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2303 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2304
2305 req->hdr.domain = domain;
6bff57a7
AK		 2306 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2307 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2308
2309 status = be_mcc_notify_wait(adapter);
2310
2311err:
2312 spin_unlock_bh(&adapter->mcc_lock);
2313 return status;
2314}
9e1453c5
AK		 2315
2316int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2317{
2318 struct be_mcc_wrb *wrb;
2319 struct be_cmd_req_cntl_attribs *req;
2320 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2321 int status;
2322 int payload_len = max(sizeof(*req), sizeof(*resp));
2323 struct mgmt_controller_attrib *attribs;
2324 struct be_dma_mem attribs_cmd;
2325
2326 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2327 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2328 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2329 &attribs_cmd.dma);
2330 if (!attribs_cmd.va) {
2331 dev_err(&adapter->pdev->dev,
2332 "Memory allocation failure\n");
2333 return -ENOMEM;
2334 }
2335
2336 if (mutex_lock_interruptible(&adapter->mbox_lock))
2337 return -1;
2338
2339 wrb = wrb_from_mbox(adapter);
2340 if (!wrb) {
2341 status = -EBUSY;
2342 goto err;
2343 }
2344 req = attribs_cmd.va;
9e1453c5 2345
106df1e3
SK		 2346 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2347 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2348 &attribs_cmd);
9e1453c5
AK		 2349
2350 status = be_mbox_notify_wait(adapter);
2351 if (!status) {
43d620c8 2352 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2353 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2354 }
2355
2356err:
2357 mutex_unlock(&adapter->mbox_lock);
2358 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2359 attribs_cmd.dma);
2360 return status;
2361}
2e588f84
SP		 2362
2363/* Uses mbox */
2dc1deb6 2364int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2365{
2366 struct be_mcc_wrb *wrb;
2367 struct be_cmd_req_set_func_cap *req;
2368 int status;
2369
2370 if (mutex_lock_interruptible(&adapter->mbox_lock))
2371 return -1;
2372
2373 wrb = wrb_from_mbox(adapter);
2374 if (!wrb) {
2375 status = -EBUSY;
2376 goto err;
2377 }
2378
2379 req = embedded_payload(wrb);
2380
106df1e3
SK		 2381 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2382 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2e588f84
SP		 2383
2384 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2385 CAPABILITY_BE3_NATIVE_ERX_API);
2386 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2387
2388 status = be_mbox_notify_wait(adapter);
2389 if (!status) {
2390 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2391 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2392 CAPABILITY_BE3_NATIVE_ERX_API;
2393 }
2394err:
2395 mutex_unlock(&adapter->mbox_lock);
2396 return status;
2397}
590c391d
PR		 2398
2399/* Uses synchronous MCCQ */
1578e777
PR		 2400int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2401 bool *pmac_id_active, u32 *pmac_id, u8 domain)
590c391d
PR		 2402{
2403 struct be_mcc_wrb *wrb;
2404 struct be_cmd_req_get_mac_list *req;
2405 int status;
2406 int mac_count;
e5e1ee89
PR		 2407 struct be_dma_mem get_mac_list_cmd;
2408 int i;
2409
2410 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2411 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2412 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2413 get_mac_list_cmd.size,
2414 &get_mac_list_cmd.dma);
2415
2416 if (!get_mac_list_cmd.va) {
2417 dev_err(&adapter->pdev->dev,
2418 "Memory allocation failure during GET_MAC_LIST\n");
2419 return -ENOMEM;
2420 }
590c391d
PR		 2421
2422 spin_lock_bh(&adapter->mcc_lock);
2423
2424 wrb = wrb_from_mccq(adapter);
2425 if (!wrb) {
2426 status = -EBUSY;
e5e1ee89 2427 goto out;
590c391d 2428 }
e5e1ee89
PR		 2429
2430 req = get_mac_list_cmd.va;
590c391d
PR		 2431
2432 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2433 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
e5e1ee89 2434 wrb, &get_mac_list_cmd);
590c391d
PR		 2435
2436 req->hdr.domain = domain;
e5e1ee89
PR		 2437 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2438 req->perm_override = 1;
590c391d
PR		 2439
2440 status = be_mcc_notify_wait(adapter);
2441 if (!status) {
2442 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89
PR		 2443 get_mac_list_cmd.va;
2444 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2445 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 2446 * or one or more true or pseudo permanant mac addresses.
2447 * If an active mac_id is present, return first active mac_id
2448 * found.
e5e1ee89 2449 */
590c391d 2450 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 2451 struct get_list_macaddr *mac_entry;
2452 u16 mac_addr_size;
2453 u32 mac_id;
2454
2455 mac_entry = &resp->macaddr_list[i];
2456 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2457 /* mac_id is a 32 bit value and mac_addr size
2458 * is 6 bytes
2459 */
2460 if (mac_addr_size == sizeof(u32)) {
2461 *pmac_id_active = true;
2462 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2463 *pmac_id = le32_to_cpu(mac_id);
2464 goto out;
590c391d 2465 }
590c391d 2466 }
1578e777 2467 /* If no active mac_id found, return first mac addr */
e5e1ee89
PR		 2468 *pmac_id_active = false;
2469 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2470 ETH_ALEN);
590c391d
PR		 2471 }
2472
e5e1ee89 2473out:
590c391d 2474 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89
PR		 2475 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2476 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 2477 return status;
2478}
2479
2480/* Uses synchronous MCCQ */
2481int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2482 u8 mac_count, u32 domain)
2483{
2484 struct be_mcc_wrb *wrb;
2485 struct be_cmd_req_set_mac_list *req;
2486 int status;
2487 struct be_dma_mem cmd;
2488
2489 memset(&cmd, 0, sizeof(struct be_dma_mem));
2490 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2491 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2492 &cmd.dma, GFP_KERNEL);
2493 if (!cmd.va) {
2494 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2495 return -ENOMEM;
2496 }
2497
2498 spin_lock_bh(&adapter->mcc_lock);
2499
2500 wrb = wrb_from_mccq(adapter);
2501 if (!wrb) {
2502 status = -EBUSY;
2503 goto err;
2504 }
2505
2506 req = cmd.va;
2507 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2508 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2509 wrb, &cmd);
2510
2511 req->hdr.domain = domain;
2512 req->mac_count = mac_count;
2513 if (mac_count)
2514 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2515
2516 status = be_mcc_notify_wait(adapter);
2517
2518err:
2519 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2520 cmd.va, cmd.dma);
2521 spin_unlock_bh(&adapter->mcc_lock);
2522 return status;
2523}
4762f6ce 2524
f1f3ee1b
AK		 2525int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2526 u32 domain, u16 intf_id)
2527{
2528 struct be_mcc_wrb *wrb;
2529 struct be_cmd_req_set_hsw_config *req;
2530 void *ctxt;
2531 int status;
2532
2533 spin_lock_bh(&adapter->mcc_lock);
2534
2535 wrb = wrb_from_mccq(adapter);
2536 if (!wrb) {
2537 status = -EBUSY;
2538 goto err;
2539 }
2540
2541 req = embedded_payload(wrb);
2542 ctxt = &req->context;
2543
2544 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2545 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2546
2547 req->hdr.domain = domain;
2548 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2549 if (pvid) {
2550 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2551 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2552 }
2553
2554 be_dws_cpu_to_le(req->context, sizeof(req->context));
2555 status = be_mcc_notify_wait(adapter);
2556
2557err:
2558 spin_unlock_bh(&adapter->mcc_lock);
2559 return status;
2560}
2561
2562/* Get Hyper switch config */
2563int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2564 u32 domain, u16 intf_id)
2565{
2566 struct be_mcc_wrb *wrb;
2567 struct be_cmd_req_get_hsw_config *req;
2568 void *ctxt;
2569 int status;
2570 u16 vid;
2571
2572 spin_lock_bh(&adapter->mcc_lock);
2573
2574 wrb = wrb_from_mccq(adapter);
2575 if (!wrb) {
2576 status = -EBUSY;
2577 goto err;
2578 }
2579
2580 req = embedded_payload(wrb);
2581 ctxt = &req->context;
2582
2583 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2584 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2585
2586 req->hdr.domain = domain;
2587 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2588 intf_id);
2589 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2590 be_dws_cpu_to_le(req->context, sizeof(req->context));
2591
2592 status = be_mcc_notify_wait(adapter);
2593 if (!status) {
2594 struct be_cmd_resp_get_hsw_config *resp =
2595 embedded_payload(wrb);
2596 be_dws_le_to_cpu(&resp->context,
2597 sizeof(resp->context));
2598 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2599 pvid, &resp->context);
2600 *pvid = le16_to_cpu(vid);
2601 }
2602
2603err:
2604 spin_unlock_bh(&adapter->mcc_lock);
2605 return status;
2606}
2607
4762f6ce
AK		 2608int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2609{
2610 struct be_mcc_wrb *wrb;
2611 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2612 int status;
2613 int payload_len = sizeof(*req);
2614 struct be_dma_mem cmd;
2615
2616 memset(&cmd, 0, sizeof(struct be_dma_mem));
2617 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2618 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2619 &cmd.dma);
2620 if (!cmd.va) {
2621 dev_err(&adapter->pdev->dev,
2622 "Memory allocation failure\n");
2623 return -ENOMEM;
2624 }
2625
2626 if (mutex_lock_interruptible(&adapter->mbox_lock))
2627 return -1;
2628
2629 wrb = wrb_from_mbox(adapter);
2630 if (!wrb) {
2631 status = -EBUSY;
2632 goto err;
2633 }
2634
2635 req = cmd.va;
2636
2637 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2638 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2639 payload_len, wrb, &cmd);
2640
2641 req->hdr.version = 1;
2642 req->query_options = BE_GET_WOL_CAP;
2643
2644 status = be_mbox_notify_wait(adapter);
2645 if (!status) {
2646 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2647 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2648
2649 /* the command could succeed misleadingly on old f/w
2650 * which is not aware of the V1 version. fake an error. */
2651 if (resp->hdr.response_length < payload_len) {
2652 status = -1;
2653 goto err;
2654 }
2655 adapter->wol_cap = resp->wol_settings;
2656 }
2657err:
2658 mutex_unlock(&adapter->mbox_lock);
2659 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2660 return status;
941a77d5
SK		 2661
2662}
2663int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2664 struct be_dma_mem *cmd)
2665{
2666 struct be_mcc_wrb *wrb;
2667 struct be_cmd_req_get_ext_fat_caps *req;
2668 int status;
2669
2670 if (mutex_lock_interruptible(&adapter->mbox_lock))
2671 return -1;
2672
2673 wrb = wrb_from_mbox(adapter);
2674 if (!wrb) {
2675 status = -EBUSY;
2676 goto err;
2677 }
2678
2679 req = cmd->va;
2680 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2681 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2682 cmd->size, wrb, cmd);
2683 req->parameter_type = cpu_to_le32(1);
2684
2685 status = be_mbox_notify_wait(adapter);
2686err:
2687 mutex_unlock(&adapter->mbox_lock);
2688 return status;
2689}
2690
2691int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2692 struct be_dma_mem *cmd,
2693 struct be_fat_conf_params *configs)
2694{
2695 struct be_mcc_wrb *wrb;
2696 struct be_cmd_req_set_ext_fat_caps *req;
2697 int status;
2698
2699 spin_lock_bh(&adapter->mcc_lock);
2700
2701 wrb = wrb_from_mccq(adapter);
2702 if (!wrb) {
2703 status = -EBUSY;
2704 goto err;
2705 }
2706
2707 req = cmd->va;
2708 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2709 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2710 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2711 cmd->size, wrb, cmd);
2712
2713 status = be_mcc_notify_wait(adapter);
2714err:
2715 spin_unlock_bh(&adapter->mcc_lock);
2716 return status;
4762f6ce 2717}
6a4ab669
PP		 2718
2719int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
2720 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
2721{
2722 struct be_adapter *adapter = netdev_priv(netdev_handle);
2723 struct be_mcc_wrb *wrb;
2724 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
2725 struct be_cmd_req_hdr *req;
2726 struct be_cmd_resp_hdr *resp;
2727 int status;
2728
2729 spin_lock_bh(&adapter->mcc_lock);
2730
2731 wrb = wrb_from_mccq(adapter);
2732 if (!wrb) {
2733 status = -EBUSY;
2734 goto err;
2735 }
2736 req = embedded_payload(wrb);
2737 resp = embedded_payload(wrb);
2738
2739 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
2740 hdr->opcode, wrb_payload_size, wrb, NULL);
2741 memcpy(req, wrb_payload, wrb_payload_size);
2742 be_dws_cpu_to_le(req, wrb_payload_size);
2743
2744 status = be_mcc_notify_wait(adapter);
2745 if (cmd_status)
2746 *cmd_status = (status & 0xffff);
2747 if (ext_status)
2748 *ext_status = 0;
2749 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
2750 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
2751err:
2752 spin_unlock_bh(&adapter->mcc_lock);
2753 return status;
2754}
2755EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux 6.x block layer and io_uring tree(s)