Commit | Line | Data |
---|---|---|
6b7c5b94 | 1 | /* |
d2145cde | 2 | * Copyright (C) 2005 - 2011 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
6b7c5b94 SP |
23 | #include <linux/delay.h> |
24 | #include <net/tcp.h> | |
25 | #include <net/ip.h> | |
26 | #include <net/ipv6.h> | |
27 | #include <linux/if_vlan.h> | |
28 | #include <linux/workqueue.h> | |
29 | #include <linux/interrupt.h> | |
84517482 | 30 | #include <linux/firmware.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ab1594e9 | 32 | #include <linux/u64_stats_sync.h> |
6b7c5b94 SP |
33 | |
34 | #include "be_hw.h" | |
045508a8 | 35 | #include "be_roce.h" |
6b7c5b94 | 36 | |
20d5ec43 | 37 | #define DRV_VER "4.2.248.0u" |
6b7c5b94 SP |
38 | #define DRV_NAME "be2net" |
39 | #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" | |
12d7ea2c | 40 | #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC" |
c4ca2374 | 41 | #define OC_NAME "Emulex OneConnect 10Gbps NIC" |
fe6d2a38 SP |
42 | #define OC_NAME_BE OC_NAME "(be3)" |
43 | #define OC_NAME_LANCER OC_NAME "(Lancer)" | |
ecedb6ae | 44 | #define OC_NAME_SH OC_NAME "(Skyhawk)" |
35ecf03c | 45 | #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver" |
6b7c5b94 | 46 | |
c4ca2374 | 47 | #define BE_VENDOR_ID 0x19a2 |
fe6d2a38 | 48 | #define EMULEX_VENDOR_ID 0x10df |
c4ca2374 | 49 | #define BE_DEVICE_ID1 0x211 |
12d7ea2c | 50 | #define BE_DEVICE_ID2 0x221 |
fe6d2a38 SP |
51 | #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ |
52 | #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ | |
53 | #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ | |
12f4d0a8 | 54 | #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ |
ecedb6ae | 55 | #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ |
4762f6ce AK |
56 | #define OC_SUBSYS_DEVICE_ID1 0xE602 |
57 | #define OC_SUBSYS_DEVICE_ID2 0xE642 | |
58 | #define OC_SUBSYS_DEVICE_ID3 0xE612 | |
59 | #define OC_SUBSYS_DEVICE_ID4 0xE652 | |
c4ca2374 AK |
60 | |
61 | static inline char *nic_name(struct pci_dev *pdev) | |
62 | { | |
12d7ea2c AK |
63 | switch (pdev->device) { |
64 | case OC_DEVICE_ID1: | |
c4ca2374 | 65 | return OC_NAME; |
e254f6ec | 66 | case OC_DEVICE_ID2: |
fe6d2a38 SP |
67 | return OC_NAME_BE; |
68 | case OC_DEVICE_ID3: | |
12f4d0a8 | 69 | case OC_DEVICE_ID4: |
fe6d2a38 | 70 | return OC_NAME_LANCER; |
12d7ea2c AK |
71 | case BE_DEVICE_ID2: |
72 | return BE3_NAME; | |
ecedb6ae AK |
73 | case OC_DEVICE_ID5: |
74 | return OC_NAME_SH; | |
12d7ea2c | 75 | default: |
c4ca2374 | 76 | return BE_NAME; |
12d7ea2c | 77 | } |
c4ca2374 AK |
78 | } |
79 | ||
6b7c5b94 | 80 | /* Number of bytes of an RX frame that are copied to skb->data */ |
2e588f84 | 81 | #define BE_HDR_LEN ((u16) 64) |
bb349bb4 ED |
82 | /* allocate extra space to allow tunneling decapsulation without head reallocation */ |
83 | #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) | |
84 | ||
6b7c5b94 SP |
85 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 |
86 | #define BE_MIN_MTU 256 | |
87 | ||
88 | #define BE_NUM_VLANS_SUPPORTED 64 | |
10ef9ab4 | 89 | #define BE_MAX_EQD 96u |
6b7c5b94 SP |
90 | #define BE_MAX_TX_FRAG_COUNT 30 |
91 | ||
92 | #define EVNT_Q_LEN 1024 | |
93 | #define TX_Q_LEN 2048 | |
94 | #define TX_CQ_LEN 1024 | |
95 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
96 | #define RX_CQ_LEN 1024 | |
5fb379ee | 97 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
98 | #define MCC_CQ_LEN 256 |
99 | ||
10ef9ab4 SP |
100 | #define BE3_MAX_RSS_QS 8 |
101 | #define BE2_MAX_RSS_QS 4 | |
102 | #define MAX_RSS_QS BE3_MAX_RSS_QS | |
ac6a0c4a | 103 | #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */ |
10ef9ab4 | 104 | |
3c8def97 | 105 | #define MAX_TX_QS 8 |
045508a8 PP |
106 | #define MAX_ROCE_EQS 5 |
107 | #define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS) /* RSS qs + RoCE */ | |
10ef9ab4 | 108 | #define BE_TX_BUDGET 256 |
6b7c5b94 | 109 | #define BE_NAPI_WEIGHT 64 |
10ef9ab4 | 110 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ |
6b7c5b94 SP |
111 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) |
112 | ||
8788fdc2 SP |
113 | #define FW_VER_LEN 32 |
114 | ||
6b7c5b94 SP |
115 | struct be_dma_mem { |
116 | void *va; | |
117 | dma_addr_t dma; | |
118 | u32 size; | |
119 | }; | |
120 | ||
121 | struct be_queue_info { | |
122 | struct be_dma_mem dma_mem; | |
123 | u16 len; | |
124 | u16 entry_size; /* Size of an element in the queue */ | |
125 | u16 id; | |
126 | u16 tail, head; | |
127 | bool created; | |
128 | atomic_t used; /* Number of valid elements in the queue */ | |
129 | }; | |
130 | ||
5fb379ee SP |
131 | static inline u32 MODULO(u16 val, u16 limit) |
132 | { | |
133 | BUG_ON(limit & (limit - 1)); | |
134 | return val & (limit - 1); | |
135 | } | |
136 | ||
137 | static inline void index_adv(u16 *index, u16 val, u16 limit) | |
138 | { | |
139 | *index = MODULO((*index + val), limit); | |
140 | } | |
141 | ||
142 | static inline void index_inc(u16 *index, u16 limit) | |
143 | { | |
144 | *index = MODULO((*index + 1), limit); | |
145 | } | |
146 | ||
147 | static inline void *queue_head_node(struct be_queue_info *q) | |
148 | { | |
149 | return q->dma_mem.va + q->head * q->entry_size; | |
150 | } | |
151 | ||
152 | static inline void *queue_tail_node(struct be_queue_info *q) | |
153 | { | |
154 | return q->dma_mem.va + q->tail * q->entry_size; | |
155 | } | |
156 | ||
3de09455 SK |
157 | static inline void *queue_index_node(struct be_queue_info *q, u16 index) |
158 | { | |
159 | return q->dma_mem.va + index * q->entry_size; | |
160 | } | |
161 | ||
5fb379ee SP |
162 | static inline void queue_head_inc(struct be_queue_info *q) |
163 | { | |
164 | index_inc(&q->head, q->len); | |
165 | } | |
166 | ||
652bf646 PR |
167 | static inline void index_dec(u16 *index, u16 limit) |
168 | { | |
169 | *index = MODULO((*index - 1), limit); | |
170 | } | |
171 | ||
5fb379ee SP |
172 | static inline void queue_tail_inc(struct be_queue_info *q) |
173 | { | |
174 | index_inc(&q->tail, q->len); | |
175 | } | |
176 | ||
5fb379ee SP |
177 | struct be_eq_obj { |
178 | struct be_queue_info q; | |
179 | char desc[32]; | |
180 | ||
181 | /* Adaptive interrupt coalescing (AIC) info */ | |
182 | bool enable_aic; | |
10ef9ab4 SP |
183 | u32 min_eqd; /* in usecs */ |
184 | u32 max_eqd; /* in usecs */ | |
185 | u32 eqd; /* configured val when aic is off */ | |
186 | u32 cur_eqd; /* in usecs */ | |
5fb379ee | 187 | |
10ef9ab4 SP |
188 | u8 idx; /* array index */ |
189 | u16 tx_budget; | |
5fb379ee | 190 | struct napi_struct napi; |
10ef9ab4 SP |
191 | struct be_adapter *adapter; |
192 | } ____cacheline_aligned_in_smp; | |
5fb379ee SP |
193 | |
194 | struct be_mcc_obj { | |
195 | struct be_queue_info q; | |
196 | struct be_queue_info cq; | |
7a1e9b20 | 197 | bool rearm_cq; |
5fb379ee SP |
198 | }; |
199 | ||
3abcdeda | 200 | struct be_tx_stats { |
ac124ff9 SP |
201 | u64 tx_bytes; |
202 | u64 tx_pkts; | |
203 | u64 tx_reqs; | |
204 | u64 tx_wrbs; | |
205 | u64 tx_compl; | |
206 | ulong tx_jiffies; | |
207 | u32 tx_stops; | |
ab1594e9 SP |
208 | struct u64_stats_sync sync; |
209 | struct u64_stats_sync sync_compl; | |
6b7c5b94 SP |
210 | }; |
211 | ||
6b7c5b94 SP |
212 | struct be_tx_obj { |
213 | struct be_queue_info q; | |
214 | struct be_queue_info cq; | |
215 | /* Remember the skbs that were transmitted */ | |
216 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
3c8def97 | 217 | struct be_tx_stats stats; |
10ef9ab4 | 218 | } ____cacheline_aligned_in_smp; |
6b7c5b94 SP |
219 | |
220 | /* Struct to remember the pages posted for rx frags */ | |
221 | struct be_rx_page_info { | |
222 | struct page *page; | |
fac6da5b | 223 | DEFINE_DMA_UNMAP_ADDR(bus); |
6b7c5b94 SP |
224 | u16 page_offset; |
225 | bool last_page_user; | |
226 | }; | |
227 | ||
3abcdeda | 228 | struct be_rx_stats { |
3abcdeda | 229 | u64 rx_bytes; |
3abcdeda | 230 | u64 rx_pkts; |
ac124ff9 SP |
231 | u64 rx_pkts_prev; |
232 | ulong rx_jiffies; | |
233 | u32 rx_drops_no_skbs; /* skb allocation errors */ | |
234 | u32 rx_drops_no_frags; /* HW has no fetched frags */ | |
235 | u32 rx_post_fail; /* page post alloc failures */ | |
ac124ff9 | 236 | u32 rx_compl; |
3abcdeda | 237 | u32 rx_mcast_pkts; |
ac124ff9 SP |
238 | u32 rx_compl_err; /* completions with err set */ |
239 | u32 rx_pps; /* pkts per second */ | |
ab1594e9 | 240 | struct u64_stats_sync sync; |
3abcdeda SP |
241 | }; |
242 | ||
2e588f84 SP |
243 | struct be_rx_compl_info { |
244 | u32 rss_hash; | |
6709d952 | 245 | u16 vlan_tag; |
2e588f84 SP |
246 | u16 pkt_size; |
247 | u16 rxq_idx; | |
12004ae9 | 248 | u16 port; |
2e588f84 SP |
249 | u8 vlanf; |
250 | u8 num_rcvd; | |
251 | u8 err; | |
252 | u8 ipf; | |
253 | u8 tcpf; | |
254 | u8 udpf; | |
255 | u8 ip_csum; | |
256 | u8 l4_csum; | |
257 | u8 ipv6; | |
258 | u8 vtm; | |
259 | u8 pkt_type; | |
260 | }; | |
261 | ||
6b7c5b94 | 262 | struct be_rx_obj { |
3abcdeda | 263 | struct be_adapter *adapter; |
6b7c5b94 SP |
264 | struct be_queue_info q; |
265 | struct be_queue_info cq; | |
2e588f84 | 266 | struct be_rx_compl_info rxcp; |
6b7c5b94 | 267 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; |
3abcdeda SP |
268 | struct be_rx_stats stats; |
269 | u8 rss_id; | |
270 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | |
10ef9ab4 | 271 | } ____cacheline_aligned_in_smp; |
6b7c5b94 | 272 | |
609ff3bb | 273 | struct be_drv_stats { |
9ae081c6 | 274 | u32 be_on_die_temperature; |
ac124ff9 SP |
275 | u32 eth_red_drops; |
276 | u32 rx_drops_no_pbuf; | |
277 | u32 rx_drops_no_txpb; | |
278 | u32 rx_drops_no_erx_descr; | |
279 | u32 rx_drops_no_tpre_descr; | |
280 | u32 rx_drops_too_many_frags; | |
ac124ff9 SP |
281 | u32 forwarded_packets; |
282 | u32 rx_drops_mtu; | |
283 | u32 rx_crc_errors; | |
284 | u32 rx_alignment_symbol_errors; | |
285 | u32 rx_pause_frames; | |
286 | u32 rx_priority_pause_frames; | |
287 | u32 rx_control_frames; | |
288 | u32 rx_in_range_errors; | |
289 | u32 rx_out_range_errors; | |
290 | u32 rx_frame_too_long; | |
d45b9d39 | 291 | u32 rx_address_mismatch_drops; |
ac124ff9 SP |
292 | u32 rx_dropped_too_small; |
293 | u32 rx_dropped_too_short; | |
294 | u32 rx_dropped_header_too_small; | |
295 | u32 rx_dropped_tcp_length; | |
296 | u32 rx_dropped_runt; | |
297 | u32 rx_ip_checksum_errs; | |
298 | u32 rx_tcp_checksum_errs; | |
299 | u32 rx_udp_checksum_errs; | |
300 | u32 tx_pauseframes; | |
301 | u32 tx_priority_pauseframes; | |
302 | u32 tx_controlframes; | |
303 | u32 rxpp_fifo_overflow_drop; | |
304 | u32 rx_input_fifo_overflow_drop; | |
305 | u32 pmem_fifo_overflow_drop; | |
306 | u32 jabber_events; | |
609ff3bb AK |
307 | }; |
308 | ||
64600ea5 | 309 | struct be_vf_cfg { |
11ac75ed SP |
310 | unsigned char mac_addr[ETH_ALEN]; |
311 | int if_handle; | |
312 | int pmac_id; | |
f1f3ee1b | 313 | u16 def_vid; |
11ac75ed SP |
314 | u16 vlan_tag; |
315 | u32 tx_rate; | |
64600ea5 AK |
316 | }; |
317 | ||
39f1d94d SP |
318 | enum vf_state { |
319 | ENABLED = 0, | |
320 | ASSIGNED = 1 | |
321 | }; | |
322 | ||
b236916a | 323 | #define BE_FLAGS_LINK_STATUS_INIT 1 |
191eb756 | 324 | #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) |
fbc13f01 AK |
325 | #define BE_UC_PMAC_COUNT 30 |
326 | #define BE_VF_UC_PMAC_COUNT 2 | |
b236916a | 327 | |
42f11cf2 AK |
328 | struct phy_info { |
329 | u8 transceiver; | |
330 | u8 autoneg; | |
331 | u8 fc_autoneg; | |
332 | u8 port_type; | |
333 | u16 phy_type; | |
334 | u16 interface_type; | |
335 | u32 misc_params; | |
336 | u16 auto_speeds_supported; | |
337 | u16 fixed_speeds_supported; | |
338 | int link_speed; | |
339 | int forced_port_speed; | |
340 | u32 dac_cable_len; | |
341 | u32 advertising; | |
342 | u32 supported; | |
343 | }; | |
344 | ||
6b7c5b94 SP |
345 | struct be_adapter { |
346 | struct pci_dev *pdev; | |
347 | struct net_device *netdev; | |
348 | ||
8788fdc2 SP |
349 | u8 __iomem *csr; |
350 | u8 __iomem *db; /* Door Bell */ | |
8788fdc2 | 351 | |
2984961c | 352 | struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ |
8788fdc2 SP |
353 | struct be_dma_mem mbox_mem; |
354 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
355 | * is stored for freeing purpose */ | |
356 | struct be_dma_mem mbox_mem_alloced; | |
357 | ||
358 | struct be_mcc_obj mcc_obj; | |
359 | spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ | |
360 | spinlock_t mcc_cq_lock; | |
6b7c5b94 | 361 | |
ac6a0c4a | 362 | u32 num_msix_vec; |
10ef9ab4 SP |
363 | u32 num_evt_qs; |
364 | struct be_eq_obj eq_obj[MAX_MSIX_VECTORS]; | |
365 | struct msix_entry msix_entries[MAX_MSIX_VECTORS]; | |
6b7c5b94 SP |
366 | bool isr_registered; |
367 | ||
368 | /* TX Rings */ | |
10ef9ab4 | 369 | u32 num_tx_qs; |
3c8def97 | 370 | struct be_tx_obj tx_obj[MAX_TX_QS]; |
6b7c5b94 SP |
371 | |
372 | /* Rx rings */ | |
3abcdeda | 373 | u32 num_rx_qs; |
10ef9ab4 | 374 | struct be_rx_obj rx_obj[MAX_RX_QS]; |
6b7c5b94 SP |
375 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ |
376 | ||
ecd62107 | 377 | u8 eq_next_idx; |
609ff3bb | 378 | struct be_drv_stats drv_stats; |
fe6d2a38 | 379 | |
82903e4b AK |
380 | u16 vlans_added; |
381 | u16 max_vlans; /* Number of vlans supported */ | |
b738127d | 382 | u8 vlan_tag[VLAN_N_VID]; |
cc4ce020 SK |
383 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
384 | u16 recommended_prio; /* Recommended Priority */ | |
5b8821b7 | 385 | struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ |
6b7c5b94 | 386 | |
3abcdeda | 387 | struct be_dma_mem stats_cmd; |
6b7c5b94 SP |
388 | /* Work queue used to perform periodic tasks like getting statistics */ |
389 | struct delayed_work work; | |
609ff3bb | 390 | u16 work_counter; |
6b7c5b94 | 391 | |
f67ef7ba | 392 | struct delayed_work func_recovery_work; |
b236916a | 393 | u32 flags; |
6b7c5b94 | 394 | /* Ethtool knobs and info */ |
6b7c5b94 | 395 | char fw_ver[FW_VER_LEN]; |
30128031 | 396 | int if_handle; /* Used to configure filtering */ |
fbc13f01 | 397 | u32 *pmac_id; /* MAC addr handle used by BE card */ |
1a642469 | 398 | u32 beacon_state; /* for set_phys_id */ |
6b7c5b94 | 399 | |
f67ef7ba | 400 | bool eeh_error; |
6589ade0 | 401 | bool fw_timeout; |
f67ef7ba PR |
402 | bool hw_error; |
403 | ||
6b7c5b94 | 404 | u32 port_num; |
24307eef | 405 | bool promiscuous; |
3486be29 | 406 | u32 function_mode; |
3abcdeda | 407 | u32 function_caps; |
9e90c961 AK |
408 | u32 rx_fc; /* Rx flow control */ |
409 | u32 tx_fc; /* Tx flow control */ | |
b2aebe6d | 410 | bool stats_cmd_sent; |
7b139c83 | 411 | u8 generation; /* BladeEngine ASIC generation */ |
045508a8 PP |
412 | u32 if_type; |
413 | struct { | |
414 | u8 __iomem *base; /* Door Bell */ | |
415 | u32 size; | |
416 | u32 total_size; | |
417 | u64 io_addr; | |
418 | } roce_db; | |
419 | u32 num_msix_roce_vec; | |
420 | struct ocrdma_dev *ocrdma_dev; | |
421 | struct list_head entry; | |
422 | ||
dd131e76 SB |
423 | u32 flash_status; |
424 | struct completion flash_compl; | |
ba343c77 | 425 | |
39f1d94d SP |
426 | u32 num_vfs; /* Number of VFs provisioned by PF driver */ |
427 | u32 dev_num_vfs; /* Number of VFs supported by HW */ | |
428 | u8 virtfn; | |
11ac75ed SP |
429 | struct be_vf_cfg *vf_cfg; |
430 | bool be3_native; | |
fe6d2a38 | 431 | u32 sli_family; |
9e1453c5 | 432 | u8 hba_port_num; |
3968fa1e | 433 | u16 pvid; |
42f11cf2 | 434 | struct phy_info phy; |
4762f6ce AK |
435 | u8 wol_cap; |
436 | bool wol; | |
fbc13f01 AK |
437 | u32 max_pmac_cnt; /* Max secondary UC MACs programmable */ |
438 | u32 uc_macs; /* Count of secondary UC MAC programmed */ | |
941a77d5 | 439 | u32 msg_enable; |
7aeb2156 | 440 | int be_get_temp_freq; |
6b7c5b94 SP |
441 | }; |
442 | ||
39f1d94d | 443 | #define be_physfn(adapter) (!adapter->virtfn) |
11ac75ed | 444 | #define sriov_enabled(adapter) (adapter->num_vfs > 0) |
39f1d94d SP |
445 | #define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \ |
446 | be_physfn(adapter)) | |
11ac75ed SP |
447 | #define for_all_vfs(adapter, vf_cfg, i) \ |
448 | for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ | |
449 | i++, vf_cfg++) | |
ba343c77 | 450 | |
7b139c83 AK |
451 | /* BladeEngine Generation numbers */ |
452 | #define BE_GEN2 2 | |
453 | #define BE_GEN3 3 | |
454 | ||
5b8821b7 SP |
455 | #define ON 1 |
456 | #define OFF 0 | |
12f4d0a8 ME |
457 | #define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \ |
458 | (adapter->pdev->device == OC_DEVICE_ID4)) | |
fe6d2a38 | 459 | |
045508a8 PP |
460 | #define be_roce_supported(adapter) ((adapter->if_type == SLI_INTF_TYPE_3 || \ |
461 | adapter->sli_family == SKYHAWK_SLI_FAMILY) && \ | |
462 | (adapter->function_mode & RDMA_ENABLED)) | |
463 | ||
0fc0b732 | 464 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 | 465 | |
ac6a0c4a | 466 | #define msix_enabled(adapter) (adapter->num_msix_vec > 0) |
10ef9ab4 SP |
467 | #define num_irqs(adapter) (msix_enabled(adapter) ? \ |
468 | adapter->num_msix_vec : 1) | |
469 | #define tx_stats(txo) (&(txo)->stats) | |
470 | #define rx_stats(rxo) (&(rxo)->stats) | |
6b7c5b94 | 471 | |
10ef9ab4 SP |
472 | /* The default RXQ is the last RXQ */ |
473 | #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) | |
6b7c5b94 | 474 | |
3abcdeda SP |
475 | #define for_all_rx_queues(adapter, rxo, i) \ |
476 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ | |
477 | i++, rxo++) | |
478 | ||
10ef9ab4 | 479 | /* Skip the default non-rss queue (last one)*/ |
3abcdeda | 480 | #define for_all_rss_queues(adapter, rxo, i) \ |
10ef9ab4 | 481 | for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\ |
3abcdeda SP |
482 | i++, rxo++) |
483 | ||
3c8def97 SP |
484 | #define for_all_tx_queues(adapter, txo, i) \ |
485 | for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ | |
486 | i++, txo++) | |
487 | ||
10ef9ab4 SP |
488 | #define for_all_evt_queues(adapter, eqo, i) \ |
489 | for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ | |
490 | i++, eqo++) | |
491 | ||
492 | #define is_mcc_eqo(eqo) (eqo->idx == 0) | |
493 | #define mcc_eqo(adapter) (&adapter->eq_obj[0]) | |
494 | ||
6b7c5b94 SP |
495 | #define PAGE_SHIFT_4K 12 |
496 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
497 | ||
498 | /* Returns number of pages spanned by the data starting at the given addr */ | |
499 | #define PAGES_4K_SPANNED(_address, size) \ | |
500 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
501 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
502 | ||
6b7c5b94 SP |
503 | /* Returns bit offset within a DWORD of a bitfield */ |
504 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
505 | (((size_t)&(((_struct *)0)->field))%32) | |
506 | ||
507 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
508 | static inline u32 amap_mask(u32 bitsize) | |
509 | { | |
510 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
511 | } | |
512 | ||
513 | static inline void | |
514 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
515 | { | |
516 | u32 *dw = (u32 *) ptr + dw_offset; | |
517 | *dw &= ~(mask << offset); | |
518 | *dw |= (mask & value) << offset; | |
519 | } | |
520 | ||
521 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
522 | amap_set(ptr, \ | |
523 | offsetof(_struct, field)/32, \ | |
524 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
525 | AMAP_BIT_OFFSET(_struct, field), \ | |
526 | val) | |
527 | ||
528 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
529 | { | |
530 | u32 *dw = (u32 *) ptr; | |
531 | return mask & (*(dw + dw_offset) >> offset); | |
532 | } | |
533 | ||
534 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
535 | amap_get(ptr, \ | |
536 | offsetof(_struct, field)/32, \ | |
537 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
538 | AMAP_BIT_OFFSET(_struct, field)) | |
539 | ||
540 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) | |
541 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
542 | static inline void swap_dws(void *wrb, int len) | |
543 | { | |
544 | #ifdef __BIG_ENDIAN | |
545 | u32 *dw = wrb; | |
546 | BUG_ON(len % 4); | |
547 | do { | |
548 | *dw = cpu_to_le32(*dw); | |
549 | dw++; | |
550 | len -= 4; | |
551 | } while (len); | |
552 | #endif /* __BIG_ENDIAN */ | |
553 | } | |
554 | ||
555 | static inline u8 is_tcp_pkt(struct sk_buff *skb) | |
556 | { | |
557 | u8 val = 0; | |
558 | ||
559 | if (ip_hdr(skb)->version == 4) | |
560 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
561 | else if (ip_hdr(skb)->version == 6) | |
562 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
563 | ||
564 | return val; | |
565 | } | |
566 | ||
567 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
568 | { | |
569 | u8 val = 0; | |
570 | ||
571 | if (ip_hdr(skb)->version == 4) | |
572 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
573 | else if (ip_hdr(skb)->version == 6) | |
574 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
575 | ||
576 | return val; | |
577 | } | |
578 | ||
93040ae5 SK |
579 | static inline bool is_ipv4_pkt(struct sk_buff *skb) |
580 | { | |
e8efcec5 | 581 | return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; |
93040ae5 SK |
582 | } |
583 | ||
6d87f5c3 AK |
584 | static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) |
585 | { | |
586 | u32 addr; | |
587 | ||
588 | addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); | |
589 | ||
590 | mac[5] = (u8)(addr & 0xFF); | |
591 | mac[4] = (u8)((addr >> 8) & 0xFF); | |
592 | mac[3] = (u8)((addr >> 16) & 0xFF); | |
7a2414a5 AK |
593 | /* Use the OUI from the current MAC address */ |
594 | memcpy(mac, adapter->netdev->dev_addr, 3); | |
6d87f5c3 AK |
595 | } |
596 | ||
4b972914 AK |
597 | static inline bool be_multi_rxq(const struct be_adapter *adapter) |
598 | { | |
599 | return adapter->num_rx_qs > 1; | |
600 | } | |
601 | ||
6589ade0 SP |
602 | static inline bool be_error(struct be_adapter *adapter) |
603 | { | |
f67ef7ba PR |
604 | return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; |
605 | } | |
606 | ||
607 | static inline bool be_crit_error(struct be_adapter *adapter) | |
608 | { | |
609 | return adapter->eeh_error || adapter->hw_error; | |
610 | } | |
611 | ||
612 | static inline void be_clear_all_error(struct be_adapter *adapter) | |
613 | { | |
614 | adapter->eeh_error = false; | |
615 | adapter->hw_error = false; | |
616 | adapter->fw_timeout = false; | |
6589ade0 SP |
617 | } |
618 | ||
4762f6ce AK |
619 | static inline bool be_is_wol_excluded(struct be_adapter *adapter) |
620 | { | |
621 | struct pci_dev *pdev = adapter->pdev; | |
622 | ||
623 | if (!be_physfn(adapter)) | |
624 | return true; | |
625 | ||
626 | switch (pdev->subsystem_device) { | |
627 | case OC_SUBSYS_DEVICE_ID1: | |
628 | case OC_SUBSYS_DEVICE_ID2: | |
629 | case OC_SUBSYS_DEVICE_ID3: | |
630 | case OC_SUBSYS_DEVICE_ID4: | |
631 | return true; | |
632 | default: | |
633 | return false; | |
634 | } | |
635 | } | |
636 | ||
045508a8 PP |
637 | static inline bool be_type_2_3(struct be_adapter *adapter) |
638 | { | |
639 | return (adapter->if_type == SLI_INTF_TYPE_2 || | |
640 | adapter->if_type == SLI_INTF_TYPE_3) ? true : false; | |
641 | } | |
642 | ||
8788fdc2 | 643 | extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
5fb379ee | 644 | u16 num_popped); |
b236916a | 645 | extern void be_link_status_update(struct be_adapter *adapter, u8 link_status); |
89a88ab8 | 646 | extern void be_parse_stats(struct be_adapter *adapter); |
84517482 | 647 | extern int be_load_fw(struct be_adapter *adapter, u8 *func); |
4762f6ce | 648 | extern bool be_is_wol_supported(struct be_adapter *adapter); |
42f11cf2 | 649 | extern bool be_pause_supported(struct be_adapter *adapter); |
941a77d5 SK |
650 | extern u32 be_get_fw_log_level(struct be_adapter *adapter); |
651 | ||
045508a8 PP |
652 | /* |
653 | * internal function to initialize-cleanup roce device. | |
654 | */ | |
655 | extern void be_roce_dev_add(struct be_adapter *); | |
656 | extern void be_roce_dev_remove(struct be_adapter *); | |
657 | ||
658 | /* | |
659 | * internal function to open-close roce device during ifup-ifdown. | |
660 | */ | |
661 | extern void be_roce_dev_open(struct be_adapter *); | |
662 | extern void be_roce_dev_close(struct be_adapter *); | |
663 | ||
6b7c5b94 | 664 | #endif /* BE_H */ |