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[linux-block.git] / drivers / net / ethernet / cisco / enic / enic_main.c
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01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF		 27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF		 32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF		 34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
7c2ce6e6 41#include <linux/ktime.h>
322cf7e3 42#include <linux/numa.h>
b6e97c13
GV		 43#ifdef CONFIG_RFS_ACCEL
44#include <linux/cpu_rmap.h>
45#endif
3f255dcc 46#include <linux/crash_dump.h>
7a655c63 47#include <net/busy_poll.h>
257e7382 48#include <net/vxlan.h>
01f2e4ea
SF		 49
50#include "cq_enet_desc.h"
51#include "vnic_dev.h"
52#include "vnic_intr.h"
53#include "vnic_stats.h"
f8bd9091 54#include "vnic_vic.h"
01f2e4ea
SF		 55#include "enic_res.h"
56#include "enic.h"
51987461 57#include "enic_dev.h"
b3abfbd2 58#include "enic_pp.h"
a145df23 59#include "enic_clsf.h"
01f2e4ea
SF		 60
61#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
SF		 62#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
63#define MAX_TSO (1 << 16)
64#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
65
66#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 67#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 68#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea 69
a03bb56e
GV		 70#define RX_COPYBREAK_DEFAULT 256
71
01f2e4ea 72/* Supported devices */
9baa3c34 73static const struct pci_device_id enic_id_table[] = {
ea0d7d91 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 76 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF		 77 { 0, } /* end of table */
78};
79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
82MODULE_LICENSE("GPL");
01f2e4ea
SF		 83MODULE_DEVICE_TABLE(pci, enic_id_table);
84
7c2ce6e6
SS		 85#define ENIC_LARGE_PKT_THRESHOLD 1000
86#define ENIC_MAX_COALESCE_TIMERS 10
87/* Interrupt moderation table, which will be used to decide the
88 * coalescing timer values
89 * {rx_rate in Mbps, mapping percentage of the range}
90 */
57ae84a0 91static struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
7c2ce6e6
SS		 92 {4000, 0},
93 {4400, 10},
94 {5060, 20},
95 {5230, 30},
96 {5540, 40},
97 {5820, 50},
98 {6120, 60},
99 {6435, 70},
100 {6745, 80},
101 {7000, 90},
102 {0xFFFFFFFF, 100}
103};
104
105/* This table helps the driver to pick different ranges for rx coalescing
106 * timer depending on the link speed.
107 */
57ae84a0 108static struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
7c2ce6e6
SS		 109 {0, 0}, /* 0 - 4 Gbps */
110 {0, 3}, /* 4 - 10 Gbps */
111 {3, 6}, /* 10 - 40 Gbps */
112};
113
322cf7e3
GV		 114static void enic_init_affinity_hint(struct enic *enic)
115{
116 int numa_node = dev_to_node(&enic->pdev->dev);
117 int i;
118
119 for (i = 0; i < enic->intr_count; i++) {
120 if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i) ||
43d28166 121 (cpumask_available(enic->msix[i].affinity_mask) &&
322cf7e3
GV		 122 !cpumask_empty(enic->msix[i].affinity_mask)))
123 continue;
124 if (zalloc_cpumask_var(&enic->msix[i].affinity_mask,
125 GFP_KERNEL))
126 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
127 enic->msix[i].affinity_mask);
128 }
129}
130
131static void enic_free_affinity_hint(struct enic *enic)
132{
133 int i;
134
135 for (i = 0; i < enic->intr_count; i++) {
136 if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i))
137 continue;
138 free_cpumask_var(enic->msix[i].affinity_mask);
139 }
140}
141
142static void enic_set_affinity_hint(struct enic *enic)
143{
144 int i;
145 int err;
146
147 for (i = 0; i < enic->intr_count; i++) {
148 if (enic_is_err_intr(enic, i) ||
149 enic_is_notify_intr(enic, i) ||
43d28166 150 !cpumask_available(enic->msix[i].affinity_mask) ||
322cf7e3
GV		 151 cpumask_empty(enic->msix[i].affinity_mask))
152 continue;
153 err = irq_set_affinity_hint(enic->msix_entry[i].vector,
154 enic->msix[i].affinity_mask);
155 if (err)
156 netdev_warn(enic->netdev, "irq_set_affinity_hint failed, err %d\n",
157 err);
158 }
159
160 for (i = 0; i < enic->wq_count; i++) {
161 int wq_intr = enic_msix_wq_intr(enic, i);
162
43d28166 163 if (cpumask_available(enic->msix[wq_intr].affinity_mask) &&
322cf7e3
GV		 164 !cpumask_empty(enic->msix[wq_intr].affinity_mask))
165 netif_set_xps_queue(enic->netdev,
166 enic->msix[wq_intr].affinity_mask,
167 i);
168 }
169}
170
171static void enic_unset_affinity_hint(struct enic *enic)
172{
173 int i;
174
175 for (i = 0; i < enic->intr_count; i++)
176 irq_set_affinity_hint(enic->msix_entry[i].vector, NULL);
177}
178
fc9a7def
JK		 179static int enic_udp_tunnel_set_port(struct net_device *netdev,
180 unsigned int table, unsigned int entry,
181 struct udp_tunnel_info *ti)
257e7382
GV		 182{
183 struct enic *enic = netdev_priv(netdev);
257e7382
GV		 184 int err;
185
186 spin_lock_bh(&enic->devcmd_lock);
187
257e7382
GV		 188 err = vnic_dev_overlay_offload_cfg(enic->vdev,
189 OVERLAY_CFG_VXLAN_PORT_UPDATE,
fc9a7def 190 ntohs(ti->port));
257e7382
GV		 191 if (err)
192 goto error;
193
194 err = vnic_dev_overlay_offload_ctrl(enic->vdev, OVERLAY_FEATURE_VXLAN,
195 enic->vxlan.patch_level);
196 if (err)
197 goto error;
198
fc9a7def 199 enic->vxlan.vxlan_udp_port_number = ntohs(ti->port);
257e7382 200error:
257e7382 201 spin_unlock_bh(&enic->devcmd_lock);
fc9a7def
JK		 202
203 return err;
257e7382
GV		 204}
205
fc9a7def
JK		 206static int enic_udp_tunnel_unset_port(struct net_device *netdev,
207 unsigned int table, unsigned int entry,
208 struct udp_tunnel_info *ti)
257e7382
GV		 209{
210 struct enic *enic = netdev_priv(netdev);
211 int err;
212
213 spin_lock_bh(&enic->devcmd_lock);
214
257e7382
GV		 215 err = vnic_dev_overlay_offload_ctrl(enic->vdev, OVERLAY_FEATURE_VXLAN,
216 OVERLAY_OFFLOAD_DISABLE);
fc9a7def 217 if (err)
257e7382 218 goto unlock;
257e7382
GV		 219
220 enic->vxlan.vxlan_udp_port_number = 0;
221
257e7382
GV		 222unlock:
223 spin_unlock_bh(&enic->devcmd_lock);
fc9a7def
JK		 224
225 return err;
257e7382
GV		 226}
227
fc9a7def
JK		 228static const struct udp_tunnel_nic_info enic_udp_tunnels = {
229 .set_port = enic_udp_tunnel_set_port,
230 .unset_port = enic_udp_tunnel_unset_port,
231 .tables = {
232 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
233 },
234}, enic_udp_tunnels_v4 = {
235 .set_port = enic_udp_tunnel_set_port,
236 .unset_port = enic_udp_tunnel_unset_port,
237 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
238 .tables = {
239 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
240 },
241};
242
9c744d10
GV		 243static netdev_features_t enic_features_check(struct sk_buff *skb,
244 struct net_device *dev,
245 netdev_features_t features)
246{
247 const struct ethhdr *eth = (struct ethhdr *)skb_inner_mac_header(skb);
248 struct enic *enic = netdev_priv(dev);
249 struct udphdr *udph;
250 u16 port = 0;
d1179094 251 u8 proto;
9c744d10
GV		 252
253 if (!skb->encapsulation)
254 return features;
255
256 features = vxlan_features_check(skb, features);
257
d1179094
GV		 258 switch (vlan_get_protocol(skb)) {
259 case htons(ETH_P_IPV6):
260 if (!(enic->vxlan.flags & ENIC_VXLAN_OUTER_IPV6))
261 goto out;
262 proto = ipv6_hdr(skb)->nexthdr;
263 break;
264 case htons(ETH_P_IP):
265 proto = ip_hdr(skb)->protocol;
266 break;
267 default:
9c744d10 268 goto out;
d1179094 269 }
9c744d10 270
d1179094
GV		 271 switch (eth->h_proto) {
272 case ntohs(ETH_P_IPV6):
273 if (!(enic->vxlan.flags & ENIC_VXLAN_INNER_IPV6))
274 goto out;
df561f66 275 fallthrough;
d1179094
GV		 276 case ntohs(ETH_P_IP):
277 break;
278 default:
9c744d10 279 goto out;
d1179094 280 }
9c744d10 281
9c744d10
GV		 282
283 if (proto == IPPROTO_UDP) {
284 udph = udp_hdr(skb);
285 port = be16_to_cpu(udph->dest);
286 }
287
288 /* HW supports offload of only one UDP port. Remove CSUM and GSO MASK
289 * for other UDP port tunnels
290 */
291 if (port != enic->vxlan.vxlan_udp_port_number)
292 goto out;
293
294 return features;
295
296out:
297 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
298}
299
3f192795 300int enic_is_dynamic(struct enic *enic)
f8bd9091
SF		 301{
302 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
303}
304
8749b427
RP		 305int enic_sriov_enabled(struct enic *enic)
306{
307 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
308}
309
3a4adef5
RP		 310static int enic_is_sriov_vf(struct enic *enic)
311{
312 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
313}
314
889d13f5
RP		 315int enic_is_valid_vf(struct enic *enic, int vf)
316{
317#ifdef CONFIG_PCI_IOV
318 return vf >= 0 && vf < enic->num_vfs;
319#else
320 return 0;
321#endif
322}
323
01f2e4ea
SF		 324static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
325{
326 struct enic *enic = vnic_dev_priv(wq->vdev);
327
328 if (buf->sop)
329 pci_unmap_single(enic->pdev, buf->dma_addr,
330 buf->len, PCI_DMA_TODEVICE);
331 else
332 pci_unmap_page(enic->pdev, buf->dma_addr,
333 buf->len, PCI_DMA_TODEVICE);
334
335 if (buf->os_buf)
336 dev_kfree_skb_any(buf->os_buf);
337}
338
339static void enic_wq_free_buf(struct vnic_wq *wq,
340 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
341{
342 enic_free_wq_buf(wq, buf);
343}
344
345static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
346 u8 type, u16 q_number, u16 completed_index, void *opaque)
347{
348 struct enic *enic = vnic_dev_priv(vdev);
349
350 spin_lock(&enic->wq_lock[q_number]);
351
352 vnic_wq_service(&enic->wq[q_number], cq_desc,
353 completed_index, enic_wq_free_buf,
354 opaque);
355
822473b6 356 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
SF		 357 vnic_wq_desc_avail(&enic->wq[q_number]) >=
358 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 359 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF		 360
361 spin_unlock(&enic->wq_lock[q_number]);
362
363 return 0;
364}
365
cc809237 366static bool enic_log_q_error(struct enic *enic)
01f2e4ea
SF		 367{
368 unsigned int i;
369 u32 error_status;
cc809237 370 bool err = false;
01f2e4ea
SF		 371
372 for (i = 0; i < enic->wq_count; i++) {
373 error_status = vnic_wq_error_status(&enic->wq[i]);
cc809237 374 err |= error_status;
01f2e4ea 375 if (error_status)
a7a79deb
VK		 376 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
377 i, error_status);
01f2e4ea
SF		 378 }
379
380 for (i = 0; i < enic->rq_count; i++) {
381 error_status = vnic_rq_error_status(&enic->rq[i]);
cc809237 382 err |= error_status;
01f2e4ea 383 if (error_status)
a7a79deb
VK		 384 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
385 i, error_status);
01f2e4ea 386 }
cc809237
GV		 387
388 return err;
01f2e4ea
SF		 389}
390
383ab92f 391static void enic_msglvl_check(struct enic *enic)
01f2e4ea 392{
383ab92f 393 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 394
383ab92f 395 if (msg_enable != enic->msg_enable) {
a7a79deb
VK		 396 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
397 enic->msg_enable, msg_enable);
383ab92f 398 enic->msg_enable = msg_enable;
01f2e4ea
SF		 399 }
400}
401
402static void enic_mtu_check(struct enic *enic)
403{
404 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 405 struct net_device *netdev = enic->netdev;
01f2e4ea 406
491598a4 407 if (mtu && mtu != enic->port_mtu) {
7c844599 408 enic->port_mtu = mtu;
7335903c 409 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP		 410 mtu = max_t(int, ENIC_MIN_MTU,
411 min_t(int, ENIC_MAX_MTU, mtu));
412 if (mtu != netdev->mtu)
413 schedule_work(&enic->change_mtu_work);
414 } else {
415 if (mtu < netdev->mtu)
416 netdev_warn(netdev,
417 "interface MTU (%d) set higher "
418 "than switch port MTU (%d)\n",
419 netdev->mtu, mtu);
420 }
01f2e4ea
SF		 421 }
422}
423
383ab92f 424static void enic_link_check(struct enic *enic)
01f2e4ea 425{
383ab92f
VK		 426 int link_status = vnic_dev_link_status(enic->vdev);
427 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 428
383ab92f 429 if (link_status && !carrier_ok) {
a7a79deb 430 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK		 431 netif_carrier_on(enic->netdev);
432 } else if (!link_status && carrier_ok) {
a7a79deb 433 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 434 netif_carrier_off(enic->netdev);
01f2e4ea
SF		 435 }
436}
437
438static void enic_notify_check(struct enic *enic)
439{
440 enic_msglvl_check(enic);
441 enic_mtu_check(enic);
442 enic_link_check(enic);
443}
444
445#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
446
447static irqreturn_t enic_isr_legacy(int irq, void *data)
448{
449 struct net_device *netdev = data;
450 struct enic *enic = netdev_priv(netdev);
717258ba
VK		 451 unsigned int io_intr = enic_legacy_io_intr();
452 unsigned int err_intr = enic_legacy_err_intr();
453 unsigned int notify_intr = enic_legacy_notify_intr();
01f2e4ea
SF		 454 u32 pba;
455
717258ba 456 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
SF		 457
458 pba = vnic_intr_legacy_pba(enic->legacy_pba);
459 if (!pba) {
717258ba 460 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 461 return IRQ_NONE; /* not our interrupt */
462 }
463
717258ba 464 if (ENIC_TEST_INTR(pba, notify_intr)) {
01f2e4ea 465 enic_notify_check(enic);
2b0c2e2d 466 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
ed8af6b2 467 }
01f2e4ea 468
717258ba
VK		 469 if (ENIC_TEST_INTR(pba, err_intr)) {
470 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
SF		 471 enic_log_q_error(enic);
472 /* schedule recovery from WQ/RQ error */
473 schedule_work(&enic->reset);
474 return IRQ_HANDLED;
475 }
476
db40b3f5
GV		 477 if (ENIC_TEST_INTR(pba, io_intr))
478 napi_schedule_irqoff(&enic->napi[0]);
479 else
717258ba 480 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 481
482 return IRQ_HANDLED;
483}
484
485static irqreturn_t enic_isr_msi(int irq, void *data)
486{
487 struct enic *enic = data;
488
489 /* With MSI, there is no sharing of interrupts, so this is
490 * our interrupt and there is no need to ack it. The device
491 * is not providing per-vector masking, so the OS will not
492 * write to PCI config space to mask/unmask the interrupt.
493 * We're using mask_on_assertion for MSI, so the device
494 * automatically masks the interrupt when the interrupt is
495 * generated. Later, when exiting polling, the interrupt
496 * will be unmasked (see enic_poll).
497 *
498 * Also, the device uses the same PCIe Traffic Class (TC)
499 * for Memory Write data and MSI, so there are no ordering
500 * issues; the MSI will always arrive at the Root Complex
501 * _after_ corresponding Memory Writes (i.e. descriptor
502 * writes).
503 */
504
db40b3f5 505 napi_schedule_irqoff(&enic->napi[0]);
01f2e4ea
SF		 506
507 return IRQ_HANDLED;
508}
509
4cfe8785 510static irqreturn_t enic_isr_msix(int irq, void *data)
01f2e4ea 511{
717258ba 512 struct napi_struct *napi = data;
01f2e4ea 513
db40b3f5 514 napi_schedule_irqoff(napi);
01f2e4ea
SF		 515
516 return IRQ_HANDLED;
517}
518
01f2e4ea
SF		 519static irqreturn_t enic_isr_msix_err(int irq, void *data)
520{
521 struct enic *enic = data;
717258ba 522 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 523
717258ba 524 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 525
cc809237
GV		 526 if (enic_log_q_error(enic))
527 /* schedule recovery from WQ/RQ error */
528 schedule_work(&enic->reset);
01f2e4ea
SF		 529
530 return IRQ_HANDLED;
531}
532
533static irqreturn_t enic_isr_msix_notify(int irq, void *data)
534{
535 struct enic *enic = data;
717258ba 536 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea
SF		 537
538 enic_notify_check(enic);
2b0c2e2d 539 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea
SF		 540
541 return IRQ_HANDLED;
542}
543
065df159
GV		 544static int enic_queue_wq_skb_cont(struct enic *enic, struct vnic_wq *wq,
545 struct sk_buff *skb, unsigned int len_left,
546 int loopback)
01f2e4ea 547{
9e903e08 548 const skb_frag_t *frag;
065df159 549 dma_addr_t dma_addr;
01f2e4ea
SF		 550
551 /* Queue additional data fragments */
552 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 553 len_left -= skb_frag_size(frag);
065df159
GV		 554 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 0,
555 skb_frag_size(frag),
556 DMA_TO_DEVICE);
557 if (unlikely(enic_dma_map_check(enic, dma_addr)))
558 return -ENOMEM;
559 enic_queue_wq_desc_cont(wq, skb, dma_addr, skb_frag_size(frag),
560 (len_left == 0), /* EOP? */
561 loopback);
01f2e4ea 562 }
065df159
GV		 563
564 return 0;
01f2e4ea
SF		 565}
566
065df159
GV		 567static int enic_queue_wq_skb_vlan(struct enic *enic, struct vnic_wq *wq,
568 struct sk_buff *skb, int vlan_tag_insert,
569 unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 570{
571 unsigned int head_len = skb_headlen(skb);
572 unsigned int len_left = skb->len - head_len;
573 int eop = (len_left == 0);
065df159
GV		 574 dma_addr_t dma_addr;
575 int err = 0;
576
577 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
578 PCI_DMA_TODEVICE);
579 if (unlikely(enic_dma_map_check(enic, dma_addr)))
580 return -ENOMEM;
01f2e4ea 581
ea0d7d91
SF		 582 /* Queue the main skb fragment. The fragments are no larger
583 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
584 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
585 * per fragment is queued.
586 */
065df159
GV		 587 enic_queue_wq_desc(wq, skb, dma_addr, head_len, vlan_tag_insert,
588 vlan_tag, eop, loopback);
01f2e4ea
SF		 589
590 if (!eop)
065df159
GV		 591 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
592
593 return err;
01f2e4ea
SF		 594}
595
065df159
GV		 596static int enic_queue_wq_skb_csum_l4(struct enic *enic, struct vnic_wq *wq,
597 struct sk_buff *skb, int vlan_tag_insert,
598 unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 599{
600 unsigned int head_len = skb_headlen(skb);
601 unsigned int len_left = skb->len - head_len;
0d0b1672 602 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF		 603 unsigned int csum_offset = hdr_len + skb->csum_offset;
604 int eop = (len_left == 0);
065df159
GV		 605 dma_addr_t dma_addr;
606 int err = 0;
607
608 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
609 PCI_DMA_TODEVICE);
610 if (unlikely(enic_dma_map_check(enic, dma_addr)))
611 return -ENOMEM;
01f2e4ea 612
ea0d7d91
SF		 613 /* Queue the main skb fragment. The fragments are no larger
614 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
615 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
616 * per fragment is queued.
617 */
065df159
GV		 618 enic_queue_wq_desc_csum_l4(wq, skb, dma_addr, head_len, csum_offset,
619 hdr_len, vlan_tag_insert, vlan_tag, eop,
620 loopback);
01f2e4ea
SF		 621
622 if (!eop)
065df159
GV		 623 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
624
625 return err;
01f2e4ea
SF		 626}
627
9c744d10 628static void enic_preload_tcp_csum_encap(struct sk_buff *skb)
01f2e4ea 629{
4a464a2b
GV		 630 const struct ethhdr *eth = (struct ethhdr *)skb_inner_mac_header(skb);
631
632 switch (eth->h_proto) {
633 case ntohs(ETH_P_IP):
9c744d10
GV		 634 inner_ip_hdr(skb)->check = 0;
635 inner_tcp_hdr(skb)->check =
636 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
637 inner_ip_hdr(skb)->daddr, 0,
638 IPPROTO_TCP, 0);
4a464a2b
GV		 639 break;
640 case ntohs(ETH_P_IPV6):
641 inner_tcp_hdr(skb)->check =
642 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
643 &inner_ipv6_hdr(skb)->daddr, 0,
644 IPPROTO_TCP, 0);
645 break;
646 default:
647 WARN_ONCE(1, "Non ipv4/ipv6 inner pkt for encap offload");
648 break;
9c744d10
GV		 649 }
650}
01f2e4ea 651
9c744d10
GV		 652static void enic_preload_tcp_csum(struct sk_buff *skb)
653{
01f2e4ea
SF		 654 /* Preload TCP csum field with IP pseudo hdr calculated
655 * with IP length set to zero. HW will later add in length
656 * to each TCP segment resulting from the TSO.
657 */
658
09640e63 659 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF		 660 ip_hdr(skb)->check = 0;
661 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
662 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 663 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
4c50efba 664 tcp_v6_gso_csum_prep(skb);
01f2e4ea 665 }
9c744d10
GV		 666}
667
668static int enic_queue_wq_skb_tso(struct enic *enic, struct vnic_wq *wq,
669 struct sk_buff *skb, unsigned int mss,
670 int vlan_tag_insert, unsigned int vlan_tag,
671 int loopback)
672{
673 unsigned int frag_len_left = skb_headlen(skb);
674 unsigned int len_left = skb->len - frag_len_left;
675 int eop = (len_left == 0);
676 unsigned int offset = 0;
677 unsigned int hdr_len;
678 dma_addr_t dma_addr;
679 unsigned int len;
680 skb_frag_t *frag;
681
682 if (skb->encapsulation) {
683 hdr_len = skb_inner_transport_header(skb) - skb->data;
684 hdr_len += inner_tcp_hdrlen(skb);
685 enic_preload_tcp_csum_encap(skb);
686 } else {
687 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
688 enic_preload_tcp_csum(skb);
689 }
01f2e4ea 690
ea0d7d91
SF		 691 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
692 * for the main skb fragment
693 */
694 while (frag_len_left) {
695 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
065df159
GV		 696 dma_addr = pci_map_single(enic->pdev, skb->data + offset, len,
697 PCI_DMA_TODEVICE);
698 if (unlikely(enic_dma_map_check(enic, dma_addr)))
699 return -ENOMEM;
700 enic_queue_wq_desc_tso(wq, skb, dma_addr, len, mss, hdr_len,
701 vlan_tag_insert, vlan_tag,
702 eop && (len == frag_len_left), loopback);
ea0d7d91
SF		 703 frag_len_left -= len;
704 offset += len;
705 }
01f2e4ea 706
ea0d7d91 707 if (eop)
065df159 708 return 0;
ea0d7d91
SF		 709
710 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
711 * for additional data fragments
712 */
713 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED		 714 len_left -= skb_frag_size(frag);
715 frag_len_left = skb_frag_size(frag);
4bf5adbf 716 offset = 0;
ea0d7d91
SF		 717
718 while (frag_len_left) {
719 len = min(frag_len_left,
720 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC		 721 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
722 offset, len,
5d6bcdfe 723 DMA_TO_DEVICE);
065df159
GV		 724 if (unlikely(enic_dma_map_check(enic, dma_addr)))
725 return -ENOMEM;
726 enic_queue_wq_desc_cont(wq, skb, dma_addr, len,
727 (len_left == 0) &&
728 (len == frag_len_left),/*EOP*/
729 loopback);
ea0d7d91
SF		 730 frag_len_left -= len;
731 offset += len;
732 }
733 }
065df159
GV		 734
735 return 0;
01f2e4ea
SF		 736}
737
9c744d10
GV		 738static inline int enic_queue_wq_skb_encap(struct enic *enic, struct vnic_wq *wq,
739 struct sk_buff *skb,
740 int vlan_tag_insert,
741 unsigned int vlan_tag, int loopback)
742{
743 unsigned int head_len = skb_headlen(skb);
744 unsigned int len_left = skb->len - head_len;
745 /* Hardware will overwrite the checksum fields, calculating from
746 * scratch and ignoring the value placed by software.
747 * Offload mode = 00
748 * mss[2], mss[1], mss[0] bits are set
749 */
750 unsigned int mss_or_csum = 7;
751 int eop = (len_left == 0);
752 dma_addr_t dma_addr;
753 int err = 0;
754
755 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
756 PCI_DMA_TODEVICE);
757 if (unlikely(enic_dma_map_check(enic, dma_addr)))
758 return -ENOMEM;
759
760 enic_queue_wq_desc_ex(wq, skb, dma_addr, head_len, mss_or_csum, 0,
761 vlan_tag_insert, vlan_tag,
762 WQ_ENET_OFFLOAD_MODE_CSUM, eop, 1 /* SOP */, eop,
763 loopback);
764 if (!eop)
765 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
766
767 return err;
768}
769
01f2e4ea
SF		 770static inline void enic_queue_wq_skb(struct enic *enic,
771 struct vnic_wq *wq, struct sk_buff *skb)
772{
773 unsigned int mss = skb_shinfo(skb)->gso_size;
774 unsigned int vlan_tag = 0;
775 int vlan_tag_insert = 0;
1825aca6 776 int loopback = 0;
065df159 777 int err;
01f2e4ea 778
df8a39de 779 if (skb_vlan_tag_present(skb)) {
01f2e4ea
SF		 780 /* VLAN tag from trunking driver */
781 vlan_tag_insert = 1;
df8a39de 782 vlan_tag = skb_vlan_tag_get(skb);
1825aca6
VK		 783 } else if (enic->loop_enable) {
784 vlan_tag = enic->loop_tag;
785 loopback = 1;
01f2e4ea
SF		 786 }
787
788 if (mss)
065df159
GV		 789 err = enic_queue_wq_skb_tso(enic, wq, skb, mss,
790 vlan_tag_insert, vlan_tag,
791 loopback);
9c744d10
GV		 792 else if (skb->encapsulation)
793 err = enic_queue_wq_skb_encap(enic, wq, skb, vlan_tag_insert,
794 vlan_tag, loopback);
01f2e4ea 795 else if (skb->ip_summed == CHECKSUM_PARTIAL)
065df159
GV		 796 err = enic_queue_wq_skb_csum_l4(enic, wq, skb, vlan_tag_insert,
797 vlan_tag, loopback);
01f2e4ea 798 else
065df159
GV		 799 err = enic_queue_wq_skb_vlan(enic, wq, skb, vlan_tag_insert,
800 vlan_tag, loopback);
801 if (unlikely(err)) {
802 struct vnic_wq_buf *buf;
803
804 buf = wq->to_use->prev;
805 /* while not EOP of previous pkt && queue not empty.
806 * For all non EOP bufs, os_buf is NULL.
807 */
808 while (!buf->os_buf && (buf->next != wq->to_clean)) {
809 enic_free_wq_buf(wq, buf);
810 wq->ring.desc_avail++;
811 buf = buf->prev;
812 }
813 wq->to_use = buf->next;
814 dev_kfree_skb(skb);
815 }
01f2e4ea
SF		 816}
817
ed8af6b2 818/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 819static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 820 struct net_device *netdev)
01f2e4ea
SF		 821{
822 struct enic *enic = netdev_priv(netdev);
822473b6 823 struct vnic_wq *wq;
822473b6 824 unsigned int txq_map;
f8e34d24 825 struct netdev_queue *txq;
01f2e4ea
SF		 826
827 if (skb->len <= 0) {
98d8a65d 828 dev_kfree_skb_any(skb);
01f2e4ea
SF		 829 return NETDEV_TX_OK;
830 }
831
822473b6 832 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
833 wq = &enic->wq[txq_map];
f8e34d24 834 txq = netdev_get_tx_queue(netdev, txq_map);
822473b6 835
01f2e4ea
SF		 836 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
837 * which is very likely. In the off chance it's going to take
838 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
839 */
840
841 if (skb_shinfo(skb)->gso_size == 0 &&
842 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
843 skb_linearize(skb)) {
98d8a65d 844 dev_kfree_skb_any(skb);
01f2e4ea
SF		 845 return NETDEV_TX_OK;
846 }
847
78e2045d 848 spin_lock(&enic->wq_lock[txq_map]);
01f2e4ea 849
ea0d7d91
SF		 850 if (vnic_wq_desc_avail(wq) <
851 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
f8e34d24 852 netif_tx_stop_queue(txq);
01f2e4ea 853 /* This is a hard error, log it */
a7a79deb 854 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
78e2045d 855 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 856 return NETDEV_TX_BUSY;
857 }
858
859 enic_queue_wq_skb(enic, wq, skb);
860
ea0d7d91 861 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
f8e34d24 862 netif_tx_stop_queue(txq);
fb7516d4 863 skb_tx_timestamp(skb);
6b16f9ee 864 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
f8e34d24 865 vnic_wq_doorbell(wq);
01f2e4ea 866
78e2045d 867 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 868
869 return NETDEV_TX_OK;
870}
871
872/* dev_base_lock rwlock held, nominally process context */
bc1f4470 873static void enic_get_stats(struct net_device *netdev,
874 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF		 875{
876 struct enic *enic = netdev_priv(netdev);
877 struct vnic_stats *stats;
19b596bd 878 int err;
01f2e4ea 879
19b596bd
GV		 880 err = enic_dev_stats_dump(enic, &stats);
881 /* return only when pci_zalloc_consistent fails in vnic_dev_stats_dump
882 * For other failures, like devcmd failure, we return previously
883 * recorded stats.
884 */
885 if (err == -ENOMEM)
bc1f4470 886 return;
01f2e4ea 887
25f0a061
SF		 888 net_stats->tx_packets = stats->tx.tx_frames_ok;
889 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
890 net_stats->tx_errors = stats->tx.tx_errors;
891 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 892
25f0a061
SF		 893 net_stats->rx_packets = stats->rx.rx_frames_ok;
894 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
895 net_stats->rx_errors = stats->rx.rx_errors;
896 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 897 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 898 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 899 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea
SF		 900}
901
f009618a
AD		 902static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
903{
904 struct enic *enic = netdev_priv(netdev);
905
906 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
907 unsigned int mc_count = netdev_mc_count(netdev);
908
909 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
910 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
911
912 return -ENOSPC;
913 }
914
915 enic_dev_add_addr(enic, mc_addr);
916 enic->mc_count++;
917
918 return 0;
919}
920
921static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
922{
923 struct enic *enic = netdev_priv(netdev);
924
925 enic_dev_del_addr(enic, mc_addr);
926 enic->mc_count--;
927
928 return 0;
929}
930
931static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
932{
933 struct enic *enic = netdev_priv(netdev);
934
935 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
936 unsigned int uc_count = netdev_uc_count(netdev);
937
938 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
939 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
940
941 return -ENOSPC;
942 }
943
944 enic_dev_add_addr(enic, uc_addr);
945 enic->uc_count++;
946
947 return 0;
948}
949
950static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
951{
952 struct enic *enic = netdev_priv(netdev);
953
954 enic_dev_del_addr(enic, uc_addr);
955 enic->uc_count--;
956
957 return 0;
958}
959
b3abfbd2 960void enic_reset_addr_lists(struct enic *enic)
01f2e4ea 961{
f009618a
AD		 962 struct net_device *netdev = enic->netdev;
963
964 __dev_uc_unsync(netdev, NULL);
965 __dev_mc_unsync(netdev, NULL);
966
01f2e4ea 967 enic->mc_count = 0;
e0afe53f 968 enic->uc_count = 0;
99ef5639 969 enic->flags = 0;
01f2e4ea
SF		 970}
971
972static int enic_set_mac_addr(struct net_device *netdev, char *addr)
973{
f8bd9091
SF		 974 struct enic *enic = netdev_priv(netdev);
975
7335903c 976 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF		 977 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
978 return -EADDRNOTAVAIL;
979 } else {
980 if (!is_valid_ether_addr(addr))
981 return -EADDRNOTAVAIL;
982 }
01f2e4ea
SF		 983
984 memcpy(netdev->dev_addr, addr, netdev->addr_len);
985
986 return 0;
987}
988
f8bd9091
SF		 989static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
990{
991 struct enic *enic = netdev_priv(netdev);
992 struct sockaddr *saddr = p;
993 char *addr = saddr->sa_data;
994 int err;
995
996 if (netif_running(enic->netdev)) {
997 err = enic_dev_del_station_addr(enic);
998 if (err)
999 return err;
1000 }
1001
1002 err = enic_set_mac_addr(netdev, addr);
1003 if (err)
1004 return err;
1005
1006 if (netif_running(enic->netdev)) {
1007 err = enic_dev_add_station_addr(enic);
1008 if (err)
1009 return err;
1010 }
1011
1012 return err;
1013}
1014
1015static int enic_set_mac_address(struct net_device *netdev, void *p)
1016{
294dab25 1017 struct sockaddr *saddr = p;
c76fd32d
VK		 1018 char *addr = saddr->sa_data;
1019 struct enic *enic = netdev_priv(netdev);
1020 int err;
1021
1022 err = enic_dev_del_station_addr(enic);
1023 if (err)
1024 return err;
1025
1026 err = enic_set_mac_addr(netdev, addr);
1027 if (err)
1028 return err;
294dab25 1029
c76fd32d 1030 return enic_dev_add_station_addr(enic);
f8bd9091
SF		 1031}
1032
319d7e84
RP		 1033/* netif_tx_lock held, BHs disabled */
1034static void enic_set_rx_mode(struct net_device *netdev)
1035{
1036 struct enic *enic = netdev_priv(netdev);
1037 int directed = 1;
1038 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
1039 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
1040 int promisc = (netdev->flags & IFF_PROMISC) ||
1041 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
1042 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
1043 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
1044 unsigned int flags = netdev->flags |
1045 (allmulti ? IFF_ALLMULTI : 0) |
1046 (promisc ? IFF_PROMISC : 0);
1047
1048 if (enic->flags != flags) {
1049 enic->flags = flags;
1050 enic_dev_packet_filter(enic, directed,
1051 multicast, broadcast, promisc, allmulti);
1052 }
1053
1054 if (!promisc) {
f009618a 1055 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
319d7e84 1056 if (!allmulti)
f009618a 1057 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
319d7e84
RP		 1058 }
1059}
1060
01f2e4ea 1061/* netif_tx_lock held, BHs disabled */
0290bd29 1062static void enic_tx_timeout(struct net_device *netdev, unsigned int txqueue)
01f2e4ea
SF		 1063{
1064 struct enic *enic = netdev_priv(netdev);
937317c7 1065 schedule_work(&enic->tx_hang_reset);
01f2e4ea
SF		 1066}
1067
0b1c00fc
RP		 1068static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
1069{
1070 struct enic *enic = netdev_priv(netdev);
3f192795
RP		 1071 struct enic_port_profile *pp;
1072 int err;
0b1c00fc 1073
3f192795
RP		 1074 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1075 if (err)
1076 return err;
0b1c00fc 1077
b8622cbd 1078 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP		 1079 if (vf == PORT_SELF_VF) {
1080 memcpy(pp->vf_mac, mac, ETH_ALEN);
1081 return 0;
1082 } else {
1083 /*
1084 * For sriov vf's set the mac in hw
1085 */
1086 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
1087 vnic_dev_set_mac_addr, mac);
1088 return enic_dev_status_to_errno(err);
1089 }
0b1c00fc
RP		 1090 } else
1091 return -EINVAL;
1092}
1093
f8bd9091
SF		 1094static int enic_set_vf_port(struct net_device *netdev, int vf,
1095 struct nlattr *port[])
1096{
1097 struct enic *enic = netdev_priv(netdev);
b3abfbd2 1098 struct enic_port_profile prev_pp;
3f192795 1099 struct enic_port_profile *pp;
b3abfbd2 1100 int err = 0, restore_pp = 1;
08f382eb 1101
3f192795
RP		 1102 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1103 if (err)
1104 return err;
08f382eb 1105
b3abfbd2
RP		 1106 if (!port[IFLA_PORT_REQUEST])
1107 return -EOPNOTSUPP;
1108
3f192795
RP		 1109 memcpy(&prev_pp, pp, sizeof(*enic->pp));
1110 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 1111
3f192795
RP		 1112 pp->set |= ENIC_SET_REQUEST;
1113 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF		 1114
1115 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP		 1116 pp->set |= ENIC_SET_NAME;
1117 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF		 1118 PORT_PROFILE_MAX);
1119 }
1120
1121 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP		 1122 pp->set |= ENIC_SET_INSTANCE;
1123 memcpy(pp->instance_uuid,
08f382eb
SF		 1124 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
1125 }
1126
1127 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP		 1128 pp->set |= ENIC_SET_HOST;
1129 memcpy(pp->host_uuid,
08f382eb
SF		 1130 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
1131 }
f8bd9091 1132
b4765833
RP		 1133 if (vf == PORT_SELF_VF) {
1134 /* Special case handling: mac came from IFLA_VF_MAC */
1135 if (!is_zero_ether_addr(prev_pp.vf_mac))
1136 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 1137
b4765833
RP		 1138 if (is_zero_ether_addr(netdev->dev_addr))
1139 eth_hw_addr_random(netdev);
1140 } else {
1141 /* SR-IOV VF: get mac from adapter */
1142 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
1143 vnic_dev_get_mac_addr, pp->mac_addr);
1144 if (err) {
1145 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
1146 memcpy(pp, &prev_pp, sizeof(*pp));
1147 return enic_dev_status_to_errno(err);
1148 }
1149 }
f8bd9091 1150
3f192795 1151 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP		 1152 if (err) {
1153 if (restore_pp) {
1154 /* Things are still the way they were: Implicit
1155 * DISASSOCIATE failed
1156 */
3f192795 1157 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 1158 } else {
3f192795
RP		 1159 memset(pp, 0, sizeof(*pp));
1160 if (vf == PORT_SELF_VF)
c7bf7169 1161 eth_zero_addr(netdev->dev_addr);
b3abfbd2
RP		 1162 }
1163 } else {
1164 /* Set flag to indicate that the port assoc/disassoc
1165 * request has been sent out to fw
1166 */
3f192795 1167 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP		 1168
1169 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795 1170 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
c7bf7169 1171 eth_zero_addr(pp->mac_addr);
3f192795 1172 if (vf == PORT_SELF_VF)
c7bf7169 1173 eth_zero_addr(netdev->dev_addr);
b3abfbd2
RP		 1174 }
1175 }
29639059 1176
b4765833 1177 if (vf == PORT_SELF_VF)
c7bf7169 1178 eth_zero_addr(pp->vf_mac);
29639059 1179
29639059 1180 return err;
f8bd9091
SF		 1181}
1182
1183static int enic_get_vf_port(struct net_device *netdev, int vf,
1184 struct sk_buff *skb)
1185{
1186 struct enic *enic = netdev_priv(netdev);
f8bd9091 1187 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 1188 struct enic_port_profile *pp;
b3abfbd2 1189 int err;
f8bd9091 1190
3f192795
RP		 1191 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1192 if (err)
1193 return err;
1194
1195 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 1196 return -ENODATA;
f8bd9091 1197
3f192795 1198 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 1199 if (err)
b3abfbd2 1200 return err;
f8bd9091 1201
1a106de6
DM		 1202 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
1203 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
1204 ((pp->set & ENIC_SET_NAME) &&
1205 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
1206 ((pp->set & ENIC_SET_INSTANCE) &&
1207 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
1208 pp->instance_uuid)) ||
1209 ((pp->set & ENIC_SET_HOST) &&
1210 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
1211 goto nla_put_failure;
f8bd9091
SF		 1212 return 0;
1213
1214nla_put_failure:
1215 return -EMSGSIZE;
1216}
1217
01f2e4ea
SF		 1218static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
1219{
1220 struct enic *enic = vnic_dev_priv(rq->vdev);
1221
1222 if (!buf->os_buf)
1223 return;
1224
1225 pci_unmap_single(enic->pdev, buf->dma_addr,
1226 buf->len, PCI_DMA_FROMDEVICE);
1227 dev_kfree_skb_any(buf->os_buf);
a03bb56e 1228 buf->os_buf = NULL;
01f2e4ea
SF		 1229}
1230
01f2e4ea
SF		 1231static int enic_rq_alloc_buf(struct vnic_rq *rq)
1232{
1233 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 1234 struct net_device *netdev = enic->netdev;
01f2e4ea 1235 struct sk_buff *skb;
1825aca6 1236 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF		 1237 unsigned int os_buf_index = 0;
1238 dma_addr_t dma_addr;
a03bb56e
GV		 1239 struct vnic_rq_buf *buf = rq->to_use;
1240
1241 if (buf->os_buf) {
f6b7734b
GV		 1242 enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
1243 buf->len);
01f2e4ea 1244
a03bb56e
GV		 1245 return 0;
1246 }
89d71a66 1247 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF		 1248 if (!skb)
1249 return -ENOMEM;
1250
065df159
GV		 1251 dma_addr = pci_map_single(enic->pdev, skb->data, len,
1252 PCI_DMA_FROMDEVICE);
1253 if (unlikely(enic_dma_map_check(enic, dma_addr))) {
1254 dev_kfree_skb(skb);
1255 return -ENOMEM;
1256 }
01f2e4ea
SF		 1257
1258 enic_queue_rq_desc(rq, skb, os_buf_index,
1259 dma_addr, len);
1260
1261 return 0;
1262}
1263
7c2ce6e6
SS		 1264static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
1265 u32 pkt_len)
1266{
1267 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
1268 pkt_size->large_pkt_bytes_cnt += pkt_len;
1269 else
1270 pkt_size->small_pkt_bytes_cnt += pkt_len;
1271}
1272
a03bb56e
GV		 1273static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
1274 struct vnic_rq_buf *buf, u16 len)
1275{
1276 struct enic *enic = netdev_priv(netdev);
1277 struct sk_buff *new_skb;
1278
1279 if (len > enic->rx_copybreak)
1280 return false;
1281 new_skb = netdev_alloc_skb_ip_align(netdev, len);
1282 if (!new_skb)
1283 return false;
1284 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
1285 DMA_FROM_DEVICE);
1286 memcpy(new_skb->data, (*skb)->data, len);
1287 *skb = new_skb;
1288
1289 return true;
1290}
1291
01f2e4ea
SF		 1292static void enic_rq_indicate_buf(struct vnic_rq *rq,
1293 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
1294 int skipped, void *opaque)
1295{
1296 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 1297 struct net_device *netdev = enic->netdev;
01f2e4ea 1298 struct sk_buff *skb;
7c2ce6e6 1299 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
01f2e4ea
SF		 1300
1301 u8 type, color, eop, sop, ingress_port, vlan_stripped;
1302 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
1303 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
1304 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
1305 u8 packet_error;
f8cac14a 1306 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea 1307 u32 rss_hash;
257e7382 1308 bool outer_csum_ok = true, encap = false;
01f2e4ea
SF		 1309
1310 if (skipped)
1311 return;
1312
1313 skb = buf->os_buf;
01f2e4ea
SF		 1314
1315 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
1316 &type, &color, &q_number, &completed_index,
1317 &ingress_port, &fcoe, &eop, &sop, &rss_type,
1318 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 1319 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF		 1320 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
1321 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
1322 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
1323 &fcs_ok);
1324
1325 if (packet_error) {
1326
350991e1
SF		 1327 if (!fcs_ok) {
1328 if (bytes_written > 0)
1329 enic->rq_bad_fcs++;
1330 else if (bytes_written == 0)
1331 enic->rq_truncated_pkts++;
1332 }
01f2e4ea 1333
44aa91ab
GV		 1334 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1335 PCI_DMA_FROMDEVICE);
01f2e4ea 1336 dev_kfree_skb_any(skb);
44aa91ab 1337 buf->os_buf = NULL;
01f2e4ea
SF		 1338
1339 return;
1340 }
1341
1342 if (eop && bytes_written > 0) {
1343
1344 /* Good receive
1345 */
1346
a03bb56e
GV		 1347 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
1348 buf->os_buf = NULL;
1349 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1350 PCI_DMA_FROMDEVICE);
1351 }
1352 prefetch(skb->data - NET_IP_ALIGN);
1353
01f2e4ea 1354 skb_put(skb, bytes_written);
86ca9db7 1355 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1356 skb_record_rx_queue(skb, q_number);
257e7382
GV		 1357 if ((netdev->features & NETIF_F_RXHASH) && rss_hash &&
1358 (type == 3)) {
17197236
GV		 1359 switch (rss_type) {
1360 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4:
1361 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6:
1362 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX:
1363 skb_set_hash(skb, rss_hash, PKT_HASH_TYPE_L4);
1364 break;
1365 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv4:
1366 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv6:
1367 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX:
1368 skb_set_hash(skb, rss_hash, PKT_HASH_TYPE_L3);
1369 break;
1370 }
bf751ba8 1371 }
257e7382
GV		 1372 if (enic->vxlan.vxlan_udp_port_number) {
1373 switch (enic->vxlan.patch_level) {
1374 case 0:
1375 if (fcoe) {
1376 encap = true;
1377 outer_csum_ok = fcoe_fc_crc_ok;
1378 }
1379 break;
1380 case 2:
1381 if ((type == 7) &&
1382 (rss_hash & BIT(0))) {
1383 encap = true;
1384 outer_csum_ok = (rss_hash & BIT(1)) &&
1385 (rss_hash & BIT(2));
1386 }
1387 break;
1388 }
1389 }
01f2e4ea 1390
17e96834
GV		 1391 /* Hardware does not provide whole packet checksum. It only
1392 * provides pseudo checksum. Since hw validates the packet
1393 * checksum but not provide us the checksum value. use
1394 * CHECSUM_UNNECESSARY.
257e7382
GV		 1395 *
1396 * In case of encap pkt tcp_udp_csum_ok/tcp_udp_csum_ok is
1397 * inner csum_ok. outer_csum_ok is set by hw when outer udp
1398 * csum is correct or is zero.
17e96834 1399 */
257e7382 1400 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc &&
7596175e
GV		 1401 tcp_udp_csum_ok && outer_csum_ok &&
1402 (ipv4_csum_ok || ipv6)) {
17e96834 1403 skb->ip_summed = CHECKSUM_UNNECESSARY;
257e7382
GV		 1404 skb->csum_level = encap;
1405 }
01f2e4ea 1406
6ede746b 1407 if (vlan_stripped)
86a9bad3 1408 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1409
14747cd9 1410 skb_mark_napi_id(skb, &enic->napi[rq->index]);
7a655c63 1411 if (!(netdev->features & NETIF_F_GRO))
6ede746b 1412 netif_receive_skb(skb);
14747cd9
GV		 1413 else
1414 napi_gro_receive(&enic->napi[q_number], skb);
7c2ce6e6
SS		 1415 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1416 enic_intr_update_pkt_size(&cq->pkt_size_counter,
1417 bytes_written);
01f2e4ea
SF		 1418 } else {
1419
1420 /* Buffer overflow
1421 */
1422
44aa91ab
GV		 1423 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1424 PCI_DMA_FROMDEVICE);
01f2e4ea 1425 dev_kfree_skb_any(skb);
44aa91ab 1426 buf->os_buf = NULL;
01f2e4ea
SF		 1427 }
1428}
1429
1430static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1431 u8 type, u16 q_number, u16 completed_index, void *opaque)
1432{
1433 struct enic *enic = vnic_dev_priv(vdev);
1434
1435 vnic_rq_service(&enic->rq[q_number], cq_desc,
1436 completed_index, VNIC_RQ_RETURN_DESC,
1437 enic_rq_indicate_buf, opaque);
1438
1439 return 0;
1440}
1441
fc865d6b
GV		 1442static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
1443{
1444 unsigned int intr = enic_msix_rq_intr(enic, rq->index);
1445 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1446 u32 timer = cq->tobe_rx_coal_timeval;
1447
1448 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
1449 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
1450 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
1451 }
1452}
1453
1454static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
1455{
1456 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1457 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1458 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
1459 int index;
1460 u32 timer;
1461 u32 range_start;
1462 u32 traffic;
1463 u64 delta;
1464 ktime_t now = ktime_get();
1465
1466 delta = ktime_us_delta(now, cq->prev_ts);
1467 if (delta < ENIC_AIC_TS_BREAK)
1468 return;
1469 cq->prev_ts = now;
1470
1471 traffic = pkt_size_counter->large_pkt_bytes_cnt +
1472 pkt_size_counter->small_pkt_bytes_cnt;
1473 /* The table takes Mbps
1474 * traffic *= 8 => bits
1475 * traffic *= (10^6 / delta) => bps
1476 * traffic /= 10^6 => Mbps
1477 *
1478 * Combining, traffic *= (8 / delta)
1479 */
1480
1481 traffic <<= 3;
1482 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
1483
1484 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
1485 if (traffic < mod_table[index].rx_rate)
1486 break;
1487 range_start = (pkt_size_counter->small_pkt_bytes_cnt >
1488 pkt_size_counter->large_pkt_bytes_cnt << 1) ?
1489 rx_coal->small_pkt_range_start :
1490 rx_coal->large_pkt_range_start;
1491 timer = range_start + ((rx_coal->range_end - range_start) *
1492 mod_table[index].range_percent / 100);
1493 /* Damping */
1494 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
1495
1496 pkt_size_counter->large_pkt_bytes_cnt = 0;
1497 pkt_size_counter->small_pkt_bytes_cnt = 0;
1498}
1499
01f2e4ea
SF		 1500static int enic_poll(struct napi_struct *napi, int budget)
1501{
717258ba
VK		 1502 struct net_device *netdev = napi->dev;
1503 struct enic *enic = netdev_priv(netdev);
1504 unsigned int cq_rq = enic_cq_rq(enic, 0);
1505 unsigned int cq_wq = enic_cq_wq(enic, 0);
1506 unsigned int intr = enic_legacy_io_intr();
01f2e4ea 1507 unsigned int rq_work_to_do = budget;
18feb871 1508 unsigned int wq_work_to_do = ENIC_WQ_NAPI_BUDGET;
4c502549 1509 unsigned int work_done, rq_work_done = 0, wq_work_done;
2d6ddced 1510 int err;
01f2e4ea 1511
14747cd9
GV		 1512 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
1513 enic_wq_service, NULL);
1514
4c502549
EB		 1515 if (budget > 0)
1516 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
1517 rq_work_to_do, enic_rq_service, NULL);
01f2e4ea 1518
01f2e4ea
SF		 1519 /* Accumulate intr event credits for this polling
1520 * cycle. An intr event is the completion of a
1521 * a WQ or RQ packet.
1522 */
1523
1524 work_done = rq_work_done + wq_work_done;
1525
1526 if (work_done > 0)
717258ba 1527 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1528 work_done,
1529 0 /* don't unmask intr */,
1530 0 /* don't reset intr timer */);
1531
0eb26022 1532 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1533
2d6ddced
SF		 1534 /* Buffer allocation failed. Stay in polling
1535 * mode so we can try to fill the ring again.
1536 */
01f2e4ea 1537
2d6ddced
SF		 1538 if (err)
1539 rq_work_done = rq_work_to_do;
fc865d6b
GV		 1540 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1541 /* Call the function which refreshes the intr coalescing timer
1542 * value based on the traffic.
1543 */
1544 enic_calc_int_moderation(enic, &enic->rq[0]);
01f2e4ea 1545
9acfd1c0 1546 if ((rq_work_done < budget) && napi_complete_done(napi, rq_work_done)) {
01f2e4ea 1547
2d6ddced 1548 /* Some work done, but not enough to stay in polling,
88132f55 1549 * exit polling
01f2e4ea
SF		 1550 */
1551
fc865d6b
GV		 1552 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1553 enic_set_int_moderation(enic, &enic->rq[0]);
717258ba 1554 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea
SF		 1555 }
1556
1557 return rq_work_done;
1558}
1559
b6e97c13
GV		 1560#ifdef CONFIG_RFS_ACCEL
1561static void enic_free_rx_cpu_rmap(struct enic *enic)
1562{
1563 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
1564 enic->netdev->rx_cpu_rmap = NULL;
1565}
1566
1567static void enic_set_rx_cpu_rmap(struct enic *enic)
1568{
1569 int i, res;
1570
1571 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
1572 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
1573 if (unlikely(!enic->netdev->rx_cpu_rmap))
1574 return;
1575 for (i = 0; i < enic->rq_count; i++) {
1576 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
1577 enic->msix_entry[i].vector);
1578 if (unlikely(res)) {
1579 enic_free_rx_cpu_rmap(enic);
1580 return;
1581 }
1582 }
1583 }
1584}
1585
1586#else
1587
1588static void enic_free_rx_cpu_rmap(struct enic *enic)
1589{
1590}
1591
1592static void enic_set_rx_cpu_rmap(struct enic *enic)
1593{
1594}
1595
1596#endif /* CONFIG_RFS_ACCEL */
1597
4cfe8785
GV		 1598static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
1599{
1600 struct net_device *netdev = napi->dev;
1601 struct enic *enic = netdev_priv(netdev);
1602 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
1603 struct vnic_wq *wq = &enic->wq[wq_index];
1604 unsigned int cq;
1605 unsigned int intr;
18feb871 1606 unsigned int wq_work_to_do = ENIC_WQ_NAPI_BUDGET;
4cfe8785
GV		 1607 unsigned int wq_work_done;
1608 unsigned int wq_irq;
1609
1610 wq_irq = wq->index;
1611 cq = enic_cq_wq(enic, wq_irq);
1612 intr = enic_msix_wq_intr(enic, wq_irq);
1613 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
1614 enic_wq_service, NULL);
1615
1616 vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
1617 0 /* don't unmask intr */,
1618 1 /* reset intr timer */);
1619 if (!wq_work_done) {
1620 napi_complete(napi);
1621 vnic_intr_unmask(&enic->intr[intr]);
f41281d0 1622 return 0;
4cfe8785
GV		 1623 }
1624
f41281d0 1625 return budget;
4cfe8785
GV		 1626}
1627
1628static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
01f2e4ea 1629{
717258ba
VK		 1630 struct net_device *netdev = napi->dev;
1631 struct enic *enic = netdev_priv(netdev);
1632 unsigned int rq = (napi - &enic->napi[0]);
1633 unsigned int cq = enic_cq_rq(enic, rq);
1634 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea 1635 unsigned int work_to_do = budget;
4c502549 1636 unsigned int work_done = 0;
2d6ddced 1637 int err;
01f2e4ea
SF		 1638
1639 /* Service RQ
1640 */
1641
4c502549
EB		 1642 if (budget > 0)
1643 work_done = vnic_cq_service(&enic->cq[cq],
1644 work_to_do, enic_rq_service, NULL);
01f2e4ea 1645
2d6ddced
SF		 1646 /* Return intr event credits for this polling
1647 * cycle. An intr event is the completion of a
1648 * RQ packet.
1649 */
01f2e4ea 1650
2d6ddced 1651 if (work_done > 0)
717258ba 1652 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1653 work_done,
1654 0 /* don't unmask intr */,
1655 0 /* don't reset intr timer */);
01f2e4ea 1656
0eb26022 1657 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF		 1658
1659 /* Buffer allocation failed. Stay in polling mode
1660 * so we can try to fill the ring again.
1661 */
1662
1663 if (err)
1664 work_done = work_to_do;
7c2ce6e6 1665 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
fc865d6b
GV		 1666 /* Call the function which refreshes the intr coalescing timer
1667 * value based on the traffic.
7c2ce6e6
SS		 1668 */
1669 enic_calc_int_moderation(enic, &enic->rq[rq]);
2d6ddced 1670
9acfd1c0 1671 if ((work_done < budget) && napi_complete_done(napi, work_done)) {
2d6ddced
SF		 1672
1673 /* Some work done, but not enough to stay in polling,
88132f55 1674 * exit polling
01f2e4ea
SF		 1675 */
1676
7c2ce6e6
SS		 1677 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1678 enic_set_int_moderation(enic, &enic->rq[rq]);
717258ba 1679 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea
SF		 1680 }
1681
1682 return work_done;
1683}
1684
e99e88a9 1685static void enic_notify_timer(struct timer_list *t)
01f2e4ea 1686{
e99e88a9 1687 struct enic *enic = from_timer(enic, t, notify_timer);
01f2e4ea
SF		 1688
1689 enic_notify_check(enic);
1690
25f0a061
SF		 1691 mod_timer(&enic->notify_timer,
1692 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF		 1693}
1694
1695static void enic_free_intr(struct enic *enic)
1696{
1697 struct net_device *netdev = enic->netdev;
1698 unsigned int i;
1699
b6e97c13 1700 enic_free_rx_cpu_rmap(enic);
01f2e4ea
SF		 1701 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1702 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF		 1703 free_irq(enic->pdev->irq, netdev);
1704 break;
8f4d248c
SF		 1705 case VNIC_DEV_INTR_MODE_MSI:
1706 free_irq(enic->pdev->irq, enic);
1707 break;
01f2e4ea
SF		 1708 case VNIC_DEV_INTR_MODE_MSIX:
1709 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1710 if (enic->msix[i].requested)
1711 free_irq(enic->msix_entry[i].vector,
1712 enic->msix[i].devid);
1713 break;
1714 default:
1715 break;
1716 }
1717}
1718
1719static int enic_request_intr(struct enic *enic)
1720{
1721 struct net_device *netdev = enic->netdev;
717258ba 1722 unsigned int i, intr;
01f2e4ea
SF		 1723 int err = 0;
1724
b6e97c13 1725 enic_set_rx_cpu_rmap(enic);
01f2e4ea
SF		 1726 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1727
1728 case VNIC_DEV_INTR_MODE_INTX:
1729
1730 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1731 IRQF_SHARED, netdev->name, netdev);
1732 break;
1733
1734 case VNIC_DEV_INTR_MODE_MSI:
1735
1736 err = request_irq(enic->pdev->irq, enic_isr_msi,
1737 0, netdev->name, enic);
1738 break;
1739
1740 case VNIC_DEV_INTR_MODE_MSIX:
1741
717258ba
VK		 1742 for (i = 0; i < enic->rq_count; i++) {
1743 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC		 1744 snprintf(enic->msix[intr].devname,
1745 sizeof(enic->msix[intr].devname),
7044f429 1746 "%s-rx-%u", netdev->name, i);
4cfe8785 1747 enic->msix[intr].isr = enic_isr_msix;
717258ba
VK		 1748 enic->msix[intr].devid = &enic->napi[i];
1749 }
01f2e4ea 1750
717258ba 1751 for (i = 0; i < enic->wq_count; i++) {
4cfe8785
GV		 1752 int wq = enic_cq_wq(enic, i);
1753
717258ba 1754 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC		 1755 snprintf(enic->msix[intr].devname,
1756 sizeof(enic->msix[intr].devname),
7044f429 1757 "%s-tx-%u", netdev->name, i);
4cfe8785
GV		 1758 enic->msix[intr].isr = enic_isr_msix;
1759 enic->msix[intr].devid = &enic->napi[wq];
717258ba 1760 }
01f2e4ea 1761
717258ba 1762 intr = enic_msix_err_intr(enic);
4505f40a
DC		 1763 snprintf(enic->msix[intr].devname,
1764 sizeof(enic->msix[intr].devname),
7044f429 1765 "%s-err", netdev->name);
717258ba
VK		 1766 enic->msix[intr].isr = enic_isr_msix_err;
1767 enic->msix[intr].devid = enic;
01f2e4ea 1768
717258ba 1769 intr = enic_msix_notify_intr(enic);
4505f40a
DC		 1770 snprintf(enic->msix[intr].devname,
1771 sizeof(enic->msix[intr].devname),
7044f429 1772 "%s-notify", netdev->name);
717258ba
VK		 1773 enic->msix[intr].isr = enic_isr_msix_notify;
1774 enic->msix[intr].devid = enic;
1775
1776 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1777 enic->msix[i].requested = 0;
01f2e4ea 1778
717258ba 1779 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF		 1780 err = request_irq(enic->msix_entry[i].vector,
1781 enic->msix[i].isr, 0,
1782 enic->msix[i].devname,
1783 enic->msix[i].devid);
1784 if (err) {
1785 enic_free_intr(enic);
1786 break;
1787 }
1788 enic->msix[i].requested = 1;
1789 }
1790
1791 break;
1792
1793 default:
1794 break;
1795 }
1796
1797 return err;
1798}
1799
b3d18d19
SF		 1800static void enic_synchronize_irqs(struct enic *enic)
1801{
1802 unsigned int i;
1803
1804 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1805 case VNIC_DEV_INTR_MODE_INTX:
1806 case VNIC_DEV_INTR_MODE_MSI:
1807 synchronize_irq(enic->pdev->irq);
1808 break;
1809 case VNIC_DEV_INTR_MODE_MSIX:
1810 for (i = 0; i < enic->intr_count; i++)
1811 synchronize_irq(enic->msix_entry[i].vector);
1812 break;
1813 default:
1814 break;
1815 }
1816}
1817
7c2ce6e6
SS		 1818static void enic_set_rx_coal_setting(struct enic *enic)
1819{
1820 unsigned int speed;
1821 int index = -1;
1822 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1823
7c2ce6e6
SS		 1824 /* 1. Read the link speed from fw
1825 * 2. Pick the default range for the speed
1826 * 3. Update it in enic->rx_coalesce_setting
1827 */
1828 speed = vnic_dev_port_speed(enic->vdev);
1829 if (ENIC_LINK_SPEED_10G < speed)
1830 index = ENIC_LINK_40G_INDEX;
1831 else if (ENIC_LINK_SPEED_4G < speed)
1832 index = ENIC_LINK_10G_INDEX;
1833 else
1834 index = ENIC_LINK_4G_INDEX;
1835
1836 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
1837 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
1838 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
1839
1840 /* Start with the value provided by UCSM */
1841 for (index = 0; index < enic->rq_count; index++)
1842 enic->cq[index].cur_rx_coal_timeval =
1843 enic->config.intr_timer_usec;
1844
1845 rx_coal->use_adaptive_rx_coalesce = 1;
1846}
1847
383ab92f 1848static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF		 1849{
1850 int err;
1851
8e091340 1852 spin_lock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1853 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1854 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK		 1855 err = vnic_dev_notify_set(enic->vdev,
1856 enic_legacy_notify_intr());
01f2e4ea
SF		 1857 break;
1858 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1859 err = vnic_dev_notify_set(enic->vdev,
1860 enic_msix_notify_intr(enic));
01f2e4ea
SF		 1861 break;
1862 default:
1863 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1864 break;
1865 }
8e091340 1866 spin_unlock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1867
1868 return err;
1869}
1870
1871static void enic_notify_timer_start(struct enic *enic)
1872{
1873 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1874 case VNIC_DEV_INTR_MODE_MSI:
1875 mod_timer(&enic->notify_timer, jiffies);
1876 break;
1877 default:
1878 /* Using intr for notification for INTx/MSI-X */
1879 break;
6403eab1 1880 }
01f2e4ea
SF		 1881}
1882
1883/* rtnl lock is held, process context */
1884static int enic_open(struct net_device *netdev)
1885{
1886 struct enic *enic = netdev_priv(netdev);
1887 unsigned int i;
56f77227 1888 int err, ret;
01f2e4ea 1889
4b75a442
SF		 1890 err = enic_request_intr(enic);
1891 if (err) {
a7a79deb 1892 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF		 1893 return err;
1894 }
322cf7e3
GV		 1895 enic_init_affinity_hint(enic);
1896 enic_set_affinity_hint(enic);
4b75a442 1897
383ab92f 1898 err = enic_dev_notify_set(enic);
4b75a442 1899 if (err) {
a7a79deb
VK		 1900 netdev_err(netdev,
1901 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF		 1902 goto err_out_free_intr;
1903 }
1904
01f2e4ea 1905 for (i = 0; i < enic->rq_count; i++) {
e8588e26
GV		 1906 /* enable rq before updating rq desc */
1907 vnic_rq_enable(&enic->rq[i]);
0eb26022 1908 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF		 1909 /* Need at least one buffer on ring to get going */
1910 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1911 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1912 err = -ENOMEM;
9dac6232 1913 goto err_out_free_rq;
01f2e4ea
SF		 1914 }
1915 }
1916
1917 for (i = 0; i < enic->wq_count; i++)
1918 vnic_wq_enable(&enic->wq[i]);
01f2e4ea 1919
7335903c 1920 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1921 enic_dev_add_station_addr(enic);
3f192795 1922
319d7e84 1923 enic_set_rx_mode(netdev);
01f2e4ea 1924
822473b6 1925 netif_tx_wake_all_queues(netdev);
717258ba 1926
7a655c63 1927 for (i = 0; i < enic->rq_count; i++)
717258ba 1928 napi_enable(&enic->napi[i]);
7a655c63 1929
4cfe8785
GV		 1930 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1931 for (i = 0; i < enic->wq_count; i++)
1932 napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
383ab92f 1933 enic_dev_enable(enic);
01f2e4ea
SF		 1934
1935 for (i = 0; i < enic->intr_count; i++)
1936 vnic_intr_unmask(&enic->intr[i]);
1937
1938 enic_notify_timer_start(enic);
3256d29f 1939 enic_rfs_timer_start(enic);
01f2e4ea
SF		 1940
1941 return 0;
4b75a442 1942
9dac6232 1943err_out_free_rq:
e8588e26 1944 for (i = 0; i < enic->rq_count; i++) {
56f77227
GV		 1945 ret = vnic_rq_disable(&enic->rq[i]);
1946 if (!ret)
1947 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
e8588e26 1948 }
383ab92f 1949 enic_dev_notify_unset(enic);
4b75a442 1950err_out_free_intr:
322cf7e3 1951 enic_unset_affinity_hint(enic);
4b75a442
SF		 1952 enic_free_intr(enic);
1953
1954 return err;
01f2e4ea
SF		 1955}
1956
1957/* rtnl lock is held, process context */
1958static int enic_stop(struct net_device *netdev)
1959{
1960 struct enic *enic = netdev_priv(netdev);
1961 unsigned int i;
1962 int err;
1963
29046f9b 1964 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 1965 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK		 1966 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
1967 }
b3d18d19
SF		 1968
1969 enic_synchronize_irqs(enic);
1970
01f2e4ea 1971 del_timer_sync(&enic->notify_timer);
a145df23 1972 enic_rfs_flw_tbl_free(enic);
01f2e4ea 1973
383ab92f 1974 enic_dev_disable(enic);
717258ba 1975
7a655c63 1976 for (i = 0; i < enic->rq_count; i++)
717258ba
VK		 1977 napi_disable(&enic->napi[i]);
1978
b3d18d19 1979 netif_carrier_off(netdev);
4cfe8785
GV		 1980 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1981 for (i = 0; i < enic->wq_count; i++)
1982 napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
0f905225 1983 netif_tx_disable(netdev);
3f192795 1984
7335903c 1985 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1986 enic_dev_del_station_addr(enic);
f8bd9091 1987
01f2e4ea
SF		 1988 for (i = 0; i < enic->wq_count; i++) {
1989 err = vnic_wq_disable(&enic->wq[i]);
1990 if (err)
1991 return err;
1992 }
1993 for (i = 0; i < enic->rq_count; i++) {
1994 err = vnic_rq_disable(&enic->rq[i]);
1995 if (err)
1996 return err;
1997 }
1998
383ab92f 1999 enic_dev_notify_unset(enic);
322cf7e3 2000 enic_unset_affinity_hint(enic);
4b75a442
SF		 2001 enic_free_intr(enic);
2002
01f2e4ea
SF		 2003 for (i = 0; i < enic->wq_count; i++)
2004 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
2005 for (i = 0; i < enic->rq_count; i++)
2006 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
2007 for (i = 0; i < enic->cq_count; i++)
2008 vnic_cq_clean(&enic->cq[i]);
2009 for (i = 0; i < enic->intr_count; i++)
2010 vnic_intr_clean(&enic->intr[i]);
2011
2012 return 0;
2013}
2014
ab123fe0
GV		 2015static int _enic_change_mtu(struct net_device *netdev, int new_mtu)
2016{
2017 bool running = netif_running(netdev);
2018 int err = 0;
2019
2020 ASSERT_RTNL();
2021 if (running) {
2022 err = enic_stop(netdev);
2023 if (err)
2024 return err;
2025 }
2026
2027 netdev->mtu = new_mtu;
2028
2029 if (running) {
2030 err = enic_open(netdev);
2031 if (err)
2032 return err;
2033 }
2034
2035 return 0;
2036}
2037
01f2e4ea
SF		 2038static int enic_change_mtu(struct net_device *netdev, int new_mtu)
2039{
2040 struct enic *enic = netdev_priv(netdev);
01f2e4ea 2041
7335903c 2042 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP		 2043 return -EOPNOTSUPP;
2044
01f2e4ea 2045 if (netdev->mtu > enic->port_mtu)
a7a79deb 2046 netdev_warn(netdev,
ab123fe0
GV		 2047 "interface MTU (%d) set higher than port MTU (%d)\n",
2048 netdev->mtu, enic->port_mtu);
01f2e4ea 2049
ab123fe0 2050 return _enic_change_mtu(netdev, new_mtu);
01f2e4ea
SF		 2051}
2052
c97c894d
RP		 2053static void enic_change_mtu_work(struct work_struct *work)
2054{
2055 struct enic *enic = container_of(work, struct enic, change_mtu_work);
2056 struct net_device *netdev = enic->netdev;
2057 int new_mtu = vnic_dev_mtu(enic->vdev);
c97c894d
RP		 2058
2059 rtnl_lock();
ab123fe0 2060 (void)_enic_change_mtu(netdev, new_mtu);
c97c894d
RP		 2061 rtnl_unlock();
2062
2063 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
2064}
2065
01f2e4ea
SF		 2066#ifdef CONFIG_NET_POLL_CONTROLLER
2067static void enic_poll_controller(struct net_device *netdev)
2068{
2069 struct enic *enic = netdev_priv(netdev);
2070 struct vnic_dev *vdev = enic->vdev;
717258ba 2071 unsigned int i, intr;
01f2e4ea
SF		 2072
2073 switch (vnic_dev_get_intr_mode(vdev)) {
2074 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 2075 for (i = 0; i < enic->rq_count; i++) {
2076 intr = enic_msix_rq_intr(enic, i);
4cfe8785
GV		 2077 enic_isr_msix(enic->msix_entry[intr].vector,
2078 &enic->napi[i]);
717258ba 2079 }
b880a954
VK		 2080
2081 for (i = 0; i < enic->wq_count; i++) {
2082 intr = enic_msix_wq_intr(enic, i);
4cfe8785
GV		 2083 enic_isr_msix(enic->msix_entry[intr].vector,
2084 &enic->napi[enic_cq_wq(enic, i)]);
b880a954
VK		 2085 }
2086
01f2e4ea
SF		 2087 break;
2088 case VNIC_DEV_INTR_MODE_MSI:
2089 enic_isr_msi(enic->pdev->irq, enic);
2090 break;
2091 case VNIC_DEV_INTR_MODE_INTX:
2092 enic_isr_legacy(enic->pdev->irq, netdev);
2093 break;
2094 default:
2095 break;
2096 }
2097}
2098#endif
2099
2100static int enic_dev_wait(struct vnic_dev *vdev,
2101 int (*start)(struct vnic_dev *, int),
2102 int (*finished)(struct vnic_dev *, int *),
2103 int arg)
2104{
2105 unsigned long time;
2106 int done;
2107 int err;
2108
2109 BUG_ON(in_interrupt());
2110
2111 err = start(vdev, arg);
2112 if (err)
2113 return err;
2114
2115 /* Wait for func to complete...2 seconds max
2116 */
2117
2118 time = jiffies + (HZ * 2);
2119 do {
2120
2121 err = finished(vdev, &done);
2122 if (err)
2123 return err;
2124
2125 if (done)
2126 return 0;
2127
2128 schedule_timeout_uninterruptible(HZ / 10);
2129
2130 } while (time_after(time, jiffies));
2131
2132 return -ETIMEDOUT;
2133}
2134
2135static int enic_dev_open(struct enic *enic)
2136{
2137 int err;
5de0c022 2138 u32 flags = CMD_OPENF_IG_DESCCACHE;
01f2e4ea
SF		 2139
2140 err = enic_dev_wait(enic->vdev, vnic_dev_open,
5de0c022 2141 vnic_dev_open_done, flags);
01f2e4ea 2142 if (err)
a7a79deb
VK		 2143 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
2144 err);
01f2e4ea
SF		 2145
2146 return err;
2147}
2148
937317c7
GV		 2149static int enic_dev_soft_reset(struct enic *enic)
2150{
2151 int err;
2152
2153 err = enic_dev_wait(enic->vdev, vnic_dev_soft_reset,
2154 vnic_dev_soft_reset_done, 0);
2155 if (err)
2156 netdev_err(enic->netdev, "vNIC soft reset failed, err %d\n",
2157 err);
2158
2159 return err;
2160}
2161
99ef5639 2162static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF		 2163{
2164 int err;
2165
99ef5639
VK		 2166 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
2167 vnic_dev_hang_reset_done, 0);
01f2e4ea 2168 if (err)
a7a79deb
VK		 2169 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
2170 err);
01f2e4ea
SF		 2171
2172 return err;
2173}
2174
4f675eb2 2175int __enic_set_rsskey(struct enic *enic)
717258ba 2176{
c33d23c2 2177 union vnic_rss_key *rss_key_buf_va;
1f4f067f 2178 dma_addr_t rss_key_buf_pa;
c33d23c2 2179 int i, kidx, bidx, err;
717258ba 2180
c33d23c2
ED		 2181 rss_key_buf_va = pci_zalloc_consistent(enic->pdev,
2182 sizeof(union vnic_rss_key),
2183 &rss_key_buf_pa);
717258ba
VK		 2184 if (!rss_key_buf_va)
2185 return -ENOMEM;
2186
c33d23c2
ED		 2187 for (i = 0; i < ENIC_RSS_LEN; i++) {
2188 kidx = i / ENIC_RSS_BYTES_PER_KEY;
2189 bidx = i % ENIC_RSS_BYTES_PER_KEY;
4f675eb2 2190 rss_key_buf_va->key[kidx].b[bidx] = enic->rss_key[i];
c33d23c2 2191 }
8e091340 2192 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 2193 err = enic_set_rss_key(enic,
2194 rss_key_buf_pa,
2195 sizeof(union vnic_rss_key));
8e091340 2196 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 2197
2198 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
2199 rss_key_buf_va, rss_key_buf_pa);
2200
2201 return err;
2202}
2203
4f675eb2
GV		 2204static int enic_set_rsskey(struct enic *enic)
2205{
2206 netdev_rss_key_fill(enic->rss_key, ENIC_RSS_LEN);
2207
2208 return __enic_set_rsskey(enic);
2209}
2210
717258ba
VK		 2211static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
2212{
1f4f067f 2213 dma_addr_t rss_cpu_buf_pa;
717258ba
VK		 2214 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
2215 unsigned int i;
2216 int err;
2217
2218 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
2219 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
2220 if (!rss_cpu_buf_va)
2221 return -ENOMEM;
2222
2223 for (i = 0; i < (1 << rss_hash_bits); i++)
2224 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
2225
8e091340 2226 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 2227 err = enic_set_rss_cpu(enic,
2228 rss_cpu_buf_pa,
2229 sizeof(union vnic_rss_cpu));
8e091340 2230 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 2231
2232 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
2233 rss_cpu_buf_va, rss_cpu_buf_pa);
2234
2235 return err;
2236}
2237
2238static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
2239 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 2240{
68f71708
SF		 2241 const u8 tso_ipid_split_en = 0;
2242 const u8 ig_vlan_strip_en = 1;
383ab92f 2243 int err;
68f71708 2244
717258ba
VK		 2245 /* Enable VLAN tag stripping.
2246 */
68f71708 2247
8e091340 2248 spin_lock_bh(&enic->devcmd_lock);
383ab92f 2249 err = enic_set_nic_cfg(enic,
68f71708
SF		 2250 rss_default_cpu, rss_hash_type,
2251 rss_hash_bits, rss_base_cpu,
2252 rss_enable, tso_ipid_split_en,
2253 ig_vlan_strip_en);
8e091340 2254 spin_unlock_bh(&enic->devcmd_lock);
383ab92f
VK		 2255
2256 return err;
2257}
2258
717258ba
VK		 2259static int enic_set_rss_nic_cfg(struct enic *enic)
2260{
2261 struct device *dev = enic_get_dev(enic);
2262 const u8 rss_default_cpu = 0;
717258ba
VK		 2263 const u8 rss_hash_bits = 7;
2264 const u8 rss_base_cpu = 0;
4016a7f1
GV		 2265 u8 rss_hash_type;
2266 int res;
717258ba
VK		 2267 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
2268
4016a7f1
GV		 2269 spin_lock_bh(&enic->devcmd_lock);
2270 res = vnic_dev_capable_rss_hash_type(enic->vdev, &rss_hash_type);
2271 spin_unlock_bh(&enic->devcmd_lock);
2272 if (res) {
2273 /* defaults for old adapters
2274 */
2275 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
2276 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
2277 NIC_CFG_RSS_HASH_TYPE_IPV6 |
2278 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
2279 }
2280
717258ba
VK		 2281 if (rss_enable) {
2282 if (!enic_set_rsskey(enic)) {
2283 if (enic_set_rsscpu(enic, rss_hash_bits)) {
2284 rss_enable = 0;
2285 dev_warn(dev, "RSS disabled, "
2286 "Failed to set RSS cpu indirection table.");
2287 }
2288 } else {
2289 rss_enable = 0;
2290 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
2291 }
2292 }
2293
2294 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
2295 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK		 2296}
2297
01f2e4ea
SF		 2298static void enic_reset(struct work_struct *work)
2299{
2300 struct enic *enic = container_of(work, struct enic, reset);
2301
2302 if (!netif_running(enic->netdev))
2303 return;
2304
2305 rtnl_lock();
2306
937317c7
GV		 2307 spin_lock(&enic->enic_api_lock);
2308 enic_stop(enic->netdev);
2309 enic_dev_soft_reset(enic);
2310 enic_reset_addr_lists(enic);
2311 enic_init_vnic_resources(enic);
2312 enic_set_rss_nic_cfg(enic);
2313 enic_dev_set_ig_vlan_rewrite_mode(enic);
2314 enic_open(enic->netdev);
2315 spin_unlock(&enic->enic_api_lock);
2316 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
2317
2318 rtnl_unlock();
2319}
2320
2321static void enic_tx_hang_reset(struct work_struct *work)
2322{
2323 struct enic *enic = container_of(work, struct enic, tx_hang_reset);
2324
2325 rtnl_lock();
2326
0b038566 2327 spin_lock(&enic->enic_api_lock);
383ab92f 2328 enic_dev_hang_notify(enic);
01f2e4ea 2329 enic_stop(enic->netdev);
99ef5639 2330 enic_dev_hang_reset(enic);
e0afe53f 2331 enic_reset_addr_lists(enic);
01f2e4ea 2332 enic_init_vnic_resources(enic);
717258ba 2333 enic_set_rss_nic_cfg(enic);
f8cac14a 2334 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 2335 enic_open(enic->netdev);
0b038566 2336 spin_unlock(&enic->enic_api_lock);
d765bb41 2337 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF		 2338
2339 rtnl_unlock();
2340}
2341
2342static int enic_set_intr_mode(struct enic *enic)
2343{
717258ba 2344 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 2345 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF		 2346 unsigned int i;
2347
2348 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 2349 * on system capabilities.
01f2e4ea
SF		 2350 *
2351 * Try MSI-X first
2352 *
2353 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
2354 * (the second to last INTR is used for WQ/RQ errors)
2355 * (the last INTR is used for notifications)
2356 */
2357
2358 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
2359 for (i = 0; i < n + m + 2; i++)
2360 enic->msix_entry[i].entry = i;
2361
717258ba
VK		 2362 /* Use multiple RQs if RSS is enabled
2363 */
2364
2365 if (ENIC_SETTING(enic, RSS) &&
2366 enic->config.intr_mode < 1 &&
01f2e4ea
SF		 2367 enic->rq_count >= n &&
2368 enic->wq_count >= m &&
2369 enic->cq_count >= n + m &&
717258ba 2370 enic->intr_count >= n + m + 2) {
01f2e4ea 2371
abbb6a37
AG		 2372 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2373 n + m + 2, n + m + 2) > 0) {
01f2e4ea 2374
717258ba
VK		 2375 enic->rq_count = n;
2376 enic->wq_count = m;
2377 enic->cq_count = n + m;
2378 enic->intr_count = n + m + 2;
01f2e4ea 2379
717258ba
VK		 2380 vnic_dev_set_intr_mode(enic->vdev,
2381 VNIC_DEV_INTR_MODE_MSIX);
2382
2383 return 0;
2384 }
2385 }
2386
2387 if (enic->config.intr_mode < 1 &&
2388 enic->rq_count >= 1 &&
2389 enic->wq_count >= m &&
2390 enic->cq_count >= 1 + m &&
2391 enic->intr_count >= 1 + m + 2) {
abbb6a37
AG		 2392 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2393 1 + m + 2, 1 + m + 2) > 0) {
717258ba
VK		 2394
2395 enic->rq_count = 1;
2396 enic->wq_count = m;
2397 enic->cq_count = 1 + m;
2398 enic->intr_count = 1 + m + 2;
2399
2400 vnic_dev_set_intr_mode(enic->vdev,
2401 VNIC_DEV_INTR_MODE_MSIX);
2402
2403 return 0;
2404 }
01f2e4ea
SF		 2405 }
2406
2407 /* Next try MSI
2408 *
2409 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
2410 */
2411
2412 if (enic->config.intr_mode < 2 &&
2413 enic->rq_count >= 1 &&
2414 enic->wq_count >= 1 &&
2415 enic->cq_count >= 2 &&
2416 enic->intr_count >= 1 &&
2417 !pci_enable_msi(enic->pdev)) {
2418
2419 enic->rq_count = 1;
2420 enic->wq_count = 1;
2421 enic->cq_count = 2;
2422 enic->intr_count = 1;
2423
2424 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
2425
2426 return 0;
2427 }
2428
2429 /* Next try INTx
2430 *
2431 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
2432 * (the first INTR is used for WQ/RQ)
2433 * (the second INTR is used for WQ/RQ errors)
2434 * (the last INTR is used for notifications)
2435 */
2436
2437 if (enic->config.intr_mode < 3 &&
2438 enic->rq_count >= 1 &&
2439 enic->wq_count >= 1 &&
2440 enic->cq_count >= 2 &&
2441 enic->intr_count >= 3) {
2442
2443 enic->rq_count = 1;
2444 enic->wq_count = 1;
2445 enic->cq_count = 2;
2446 enic->intr_count = 3;
2447
2448 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
2449
2450 return 0;
2451 }
2452
2453 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2454
2455 return -EINVAL;
2456}
2457
2458static void enic_clear_intr_mode(struct enic *enic)
2459{
2460 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2461 case VNIC_DEV_INTR_MODE_MSIX:
2462 pci_disable_msix(enic->pdev);
2463 break;
2464 case VNIC_DEV_INTR_MODE_MSI:
2465 pci_disable_msi(enic->pdev);
2466 break;
2467 default:
2468 break;
2469 }
2470
2471 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2472}
2473
f8bd9091
SF		 2474static const struct net_device_ops enic_netdev_dynamic_ops = {
2475 .ndo_open = enic_open,
2476 .ndo_stop = enic_stop,
2477 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2478 .ndo_get_stats64 = enic_get_stats,
f8bd9091 2479 .ndo_validate_addr = eth_validate_addr,
319d7e84 2480 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF		 2481 .ndo_set_mac_address = enic_set_mac_address_dynamic,
2482 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF		 2483 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2484 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2485 .ndo_tx_timeout = enic_tx_timeout,
2486 .ndo_set_vf_port = enic_set_vf_port,
2487 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 2488 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF		 2489#ifdef CONFIG_NET_POLL_CONTROLLER
2490 .ndo_poll_controller = enic_poll_controller,
2491#endif
a145df23
GV		 2492#ifdef CONFIG_RFS_ACCEL
2493 .ndo_rx_flow_steer = enic_rx_flow_steer,
2494#endif
fc9a7def
JK		 2495 .ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
2496 .ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
9c744d10 2497 .ndo_features_check = enic_features_check,
f8bd9091
SF		 2498};
2499
afe29f7a
SH		 2500static const struct net_device_ops enic_netdev_ops = {
2501 .ndo_open = enic_open,
2502 .ndo_stop = enic_stop,
00829823 2503 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2504 .ndo_get_stats64 = enic_get_stats,
afe29f7a 2505 .ndo_validate_addr = eth_validate_addr,
f8bd9091 2506 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 2507 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 2508 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH		 2509 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2510 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2511 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP		 2512 .ndo_set_vf_port = enic_set_vf_port,
2513 .ndo_get_vf_port = enic_get_vf_port,
2514 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH		 2515#ifdef CONFIG_NET_POLL_CONTROLLER
2516 .ndo_poll_controller = enic_poll_controller,
2517#endif
a145df23
GV		 2518#ifdef CONFIG_RFS_ACCEL
2519 .ndo_rx_flow_steer = enic_rx_flow_steer,
2520#endif
fc9a7def
JK		 2521 .ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
2522 .ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
9c744d10 2523 .ndo_features_check = enic_features_check,
afe29f7a
SH		 2524};
2525
2fdba388 2526static void enic_dev_deinit(struct enic *enic)
6fdfa970 2527{
717258ba
VK		 2528 unsigned int i;
2529
14747cd9
GV		 2530 for (i = 0; i < enic->rq_count; i++) {
2531 napi_hash_del(&enic->napi[i]);
717258ba 2532 netif_napi_del(&enic->napi[i]);
14747cd9 2533 }
4cfe8785
GV		 2534 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2535 for (i = 0; i < enic->wq_count; i++)
2536 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
717258ba 2537
6fdfa970
SF		 2538 enic_free_vnic_resources(enic);
2539 enic_clear_intr_mode(enic);
322cf7e3 2540 enic_free_affinity_hint(enic);
6fdfa970
SF		 2541}
2542
3f255dcc
GV		 2543static void enic_kdump_kernel_config(struct enic *enic)
2544{
2545 if (is_kdump_kernel()) {
2546 dev_info(enic_get_dev(enic), "Running from within kdump kernel. Using minimal resources\n");
2547 enic->rq_count = 1;
2548 enic->wq_count = 1;
2549 enic->config.rq_desc_count = ENIC_MIN_RQ_DESCS;
2550 enic->config.wq_desc_count = ENIC_MIN_WQ_DESCS;
2551 enic->config.mtu = min_t(u16, 1500, enic->config.mtu);
2552 }
2553}
2554
2fdba388 2555static int enic_dev_init(struct enic *enic)
6fdfa970 2556{
a7a79deb 2557 struct device *dev = enic_get_dev(enic);
6fdfa970 2558 struct net_device *netdev = enic->netdev;
717258ba 2559 unsigned int i;
6fdfa970
SF		 2560 int err;
2561
ea7ea65a
VK		 2562 /* Get interrupt coalesce timer info */
2563 err = enic_dev_intr_coal_timer_info(enic);
2564 if (err) {
2565 dev_warn(dev, "Using default conversion factor for "
2566 "interrupt coalesce timer\n");
2567 vnic_dev_intr_coal_timer_info_default(enic->vdev);
2568 }
2569
6fdfa970
SF		 2570 /* Get vNIC configuration
2571 */
2572
2573 err = enic_get_vnic_config(enic);
2574 if (err) {
a7a79deb 2575 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF		 2576 return err;
2577 }
2578
2579 /* Get available resource counts
2580 */
2581
2582 enic_get_res_counts(enic);
2583
3f255dcc
GV		 2584 /* modify resource count if we are in kdump_kernel
2585 */
2586 enic_kdump_kernel_config(enic);
2587
6fdfa970
SF		 2588 /* Set interrupt mode based on resource counts and system
2589 * capabilities
2590 */
2591
2592 err = enic_set_intr_mode(enic);
2593 if (err) {
a7a79deb
VK		 2594 dev_err(dev, "Failed to set intr mode based on resource "
2595 "counts and system capabilities, aborting\n");
6fdfa970
SF		 2596 return err;
2597 }
2598
2599 /* Allocate and configure vNIC resources
2600 */
2601
2602 err = enic_alloc_vnic_resources(enic);
2603 if (err) {
a7a79deb 2604 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF		 2605 goto err_out_free_vnic_resources;
2606 }
2607
2608 enic_init_vnic_resources(enic);
2609
717258ba 2610 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2611 if (err) {
a7a79deb 2612 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF		 2613 goto err_out_free_vnic_resources;
2614 }
2615
2616 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2617 default:
717258ba 2618 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
6fdfa970
SF		 2619 break;
2620 case VNIC_DEV_INTR_MODE_MSIX:
14747cd9 2621 for (i = 0; i < enic->rq_count; i++) {
717258ba 2622 netif_napi_add(netdev, &enic->napi[i],
4cfe8785 2623 enic_poll_msix_rq, NAPI_POLL_WEIGHT);
14747cd9 2624 }
4cfe8785
GV		 2625 for (i = 0; i < enic->wq_count; i++)
2626 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
2627 enic_poll_msix_wq, NAPI_POLL_WEIGHT);
6fdfa970
SF		 2628 break;
2629 }
2630
2631 return 0;
2632
2633err_out_free_vnic_resources:
322cf7e3 2634 enic_free_affinity_hint(enic);
6fdfa970
SF		 2635 enic_clear_intr_mode(enic);
2636 enic_free_vnic_resources(enic);
2637
2638 return err;
2639}
2640
27e6c7d3
SF		 2641static void enic_iounmap(struct enic *enic)
2642{
2643 unsigned int i;
2644
2645 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2646 if (enic->bar[i].vaddr)
2647 iounmap(enic->bar[i].vaddr);
2648}
2649
1dd06ae8 2650static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2651{
a7a79deb 2652 struct device *dev = &pdev->dev;
01f2e4ea
SF		 2653 struct net_device *netdev;
2654 struct enic *enic;
2655 int using_dac = 0;
2656 unsigned int i;
2657 int err;
8749b427
RP		 2658#ifdef CONFIG_PCI_IOV
2659 int pos = 0;
2660#endif
b67f231d 2661 int num_pps = 1;
01f2e4ea 2662
01f2e4ea
SF		 2663 /* Allocate net device structure and initialize. Private
2664 * instance data is initialized to zero.
2665 */
2666
822473b6 2667 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2668 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2669 if (!netdev)
01f2e4ea 2670 return -ENOMEM;
01f2e4ea 2671
01f2e4ea
SF		 2672 pci_set_drvdata(pdev, netdev);
2673
2674 SET_NETDEV_DEV(netdev, &pdev->dev);
2675
2676 enic = netdev_priv(netdev);
2677 enic->netdev = netdev;
2678 enic->pdev = pdev;
2679
2680 /* Setup PCI resources
2681 */
2682
29046f9b 2683 err = pci_enable_device_mem(pdev);
01f2e4ea 2684 if (err) {
a7a79deb 2685 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF		 2686 goto err_out_free_netdev;
2687 }
2688
2689 err = pci_request_regions(pdev, DRV_NAME);
2690 if (err) {
a7a79deb 2691 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF		 2692 goto err_out_disable_device;
2693 }
2694
2695 pci_set_master(pdev);
2696
2697 /* Query PCI controller on system for DMA addressing
322eaa06 2698 * limitation for the device. Try 47-bit first, and
01f2e4ea
SF		 2699 * fail to 32-bit.
2700 */
2701
322eaa06 2702 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(47));
01f2e4ea 2703 if (err) {
284901a9 2704 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2705 if (err) {
a7a79deb 2706 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF		 2707 goto err_out_release_regions;
2708 }
284901a9 2709 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2710 if (err) {
a7a79deb
VK		 2711 dev_err(dev, "Unable to obtain %u-bit DMA "
2712 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF		 2713 goto err_out_release_regions;
2714 }
2715 } else {
322eaa06 2716 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(47));
01f2e4ea 2717 if (err) {
a7a79deb 2718 dev_err(dev, "Unable to obtain %u-bit DMA "
322eaa06 2719 "for consistent allocations, aborting\n", 47);
01f2e4ea
SF		 2720 goto err_out_release_regions;
2721 }
2722 using_dac = 1;
2723 }
2724
27e6c7d3 2725 /* Map vNIC resources from BAR0-5
01f2e4ea
SF		 2726 */
2727
27e6c7d3
SF		 2728 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2729 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2730 continue;
2731 enic->bar[i].len = pci_resource_len(pdev, i);
2732 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2733 if (!enic->bar[i].vaddr) {
a7a79deb 2734 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF		 2735 err = -ENODEV;
2736 goto err_out_iounmap;
2737 }
2738 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF		 2739 }
2740
2741 /* Register vNIC device
2742 */
2743
27e6c7d3
SF		 2744 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2745 ARRAY_SIZE(enic->bar));
01f2e4ea 2746 if (!enic->vdev) {
a7a79deb 2747 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF		 2748 err = -ENODEV;
2749 goto err_out_iounmap;
2750 }
2751
373fb087
GV		 2752 err = vnic_devcmd_init(enic->vdev);
2753
2754 if (err)
2755 goto err_out_vnic_unregister;
2756
8749b427
RP		 2757#ifdef CONFIG_PCI_IOV
2758 /* Get number of subvnics */
2759 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2760 if (pos) {
2761 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2762 &enic->num_vfs);
8749b427
RP		 2763 if (enic->num_vfs) {
2764 err = pci_enable_sriov(pdev, enic->num_vfs);
2765 if (err) {
2766 dev_err(dev, "SRIOV enable failed, aborting."
2767 " pci_enable_sriov() returned %d\n",
2768 err);
2769 goto err_out_vnic_unregister;
2770 }
2771 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2772 num_pps = enic->num_vfs;
8749b427
RP		 2773 }
2774 }
8749b427 2775#endif
ca2b721d 2776
3f192795 2777 /* Allocate structure for port profiles */
a1de2219 2778 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2779 if (!enic->pp) {
3f192795 2780 err = -ENOMEM;
ca2b721d 2781 goto err_out_disable_sriov_pp;
3f192795
RP		 2782 }
2783
01f2e4ea
SF		 2784 /* Issue device open to get device in known state
2785 */
2786
2787 err = enic_dev_open(enic);
2788 if (err) {
a7a79deb 2789 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2790 goto err_out_disable_sriov;
01f2e4ea
SF		 2791 }
2792
69161425
VK		 2793 /* Setup devcmd lock
2794 */
2795
2796 spin_lock_init(&enic->devcmd_lock);
0b038566 2797 spin_lock_init(&enic->enic_api_lock);
69161425
VK		 2798
2799 /*
2800 * Set ingress vlan rewrite mode before vnic initialization
2801 */
2802
2803 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2804 if (err) {
2805 dev_err(dev,
2806 "Failed to set ingress vlan rewrite mode, aborting.\n");
2807 goto err_out_dev_close;
2808 }
2809
01f2e4ea
SF		 2810 /* Issue device init to initialize the vnic-to-switch link.
2811 * We'll start with carrier off and wait for link UP
2812 * notification later to turn on carrier. We don't need
2813 * to wait here for the vnic-to-switch link initialization
2814 * to complete; link UP notification is the indication that
2815 * the process is complete.
2816 */
2817
2818 netif_carrier_off(netdev);
2819
a7a79deb
VK		 2820 /* Do not call dev_init for a dynamic vnic.
2821 * For a dynamic vnic, init_prov_info will be
2822 * called later by an upper layer.
2823 */
2824
2b68c181 2825 if (!enic_is_dynamic(enic)) {
f8bd9091
SF		 2826 err = vnic_dev_init(enic->vdev, 0);
2827 if (err) {
a7a79deb 2828 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF		 2829 goto err_out_dev_close;
2830 }
01f2e4ea
SF		 2831 }
2832
6fdfa970 2833 err = enic_dev_init(enic);
01f2e4ea 2834 if (err) {
a7a79deb 2835 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF		 2836 goto err_out_dev_close;
2837 }
2838
822473b6 2839 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2840 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2841
383ab92f 2842 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF		 2843 */
2844
e99e88a9 2845 timer_setup(&enic->notify_timer, enic_notify_timer, 0);
01f2e4ea 2846
3256d29f 2847 enic_rfs_flw_tbl_init(enic);
7c2ce6e6 2848 enic_set_rx_coal_setting(enic);
01f2e4ea 2849 INIT_WORK(&enic->reset, enic_reset);
937317c7 2850 INIT_WORK(&enic->tx_hang_reset, enic_tx_hang_reset);
c97c894d 2851 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF		 2852
2853 for (i = 0; i < enic->wq_count; i++)
2854 spin_lock_init(&enic->wq_lock[i]);
2855
01f2e4ea
SF		 2856 /* Register net device
2857 */
2858
2859 enic->port_mtu = enic->config.mtu;
01f2e4ea
SF		 2860
2861 err = enic_set_mac_addr(netdev, enic->mac_addr);
2862 if (err) {
a7a79deb 2863 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2864 goto err_out_dev_deinit;
01f2e4ea
SF		 2865 }
2866
7c844599 2867 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
7c2ce6e6
SS		 2868 /* rx coalesce time already got initialized. This gets used
2869 * if adaptive coal is turned off
2870 */
7c844599
SF		 2871 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2872
7335903c 2873 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF		 2874 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2875 else
2876 netdev->netdev_ops = &enic_netdev_ops;
2877
01f2e4ea 2878 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2879 enic_set_ethtool_ops(netdev);
01f2e4ea 2880
f646968f 2881 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2882 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2883 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK		 2884 enic->loop_enable = 1;
2885 enic->loop_tag = enic->config.loop_tag;
2886 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2887 }
01f2e4ea 2888 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2889 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2890 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2891 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2892 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2893 if (ENIC_SETTING(enic, RSS))
2894 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM		 2895 if (ENIC_SETTING(enic, RXCSUM))
2896 netdev->hw_features |= NETIF_F_RXCSUM;
257e7382
GV		 2897 if (ENIC_SETTING(enic, VXLAN)) {
2898 u64 patch_level;
d1179094 2899 u64 a1 = 0;
257e7382
GV		 2900
2901 netdev->hw_enc_features |= NETIF_F_RXCSUM |
2902 NETIF_F_TSO |
d1179094 2903 NETIF_F_TSO6 |
257e7382
GV		 2904 NETIF_F_TSO_ECN |
2905 NETIF_F_GSO_UDP_TUNNEL |
2906 NETIF_F_HW_CSUM |
2907 NETIF_F_GSO_UDP_TUNNEL_CSUM;
2908 netdev->hw_features |= netdev->hw_enc_features;
2909 /* get bit mask from hw about supported offload bit level
2910 * BIT(0) = fw supports patch_level 0
2911 * fcoe bit = encap
2912 * fcoe_fc_crc_ok = outer csum ok
2913 * BIT(1) = always set by fw
2914 * BIT(2) = fw supports patch_level 2
2915 * BIT(0) in rss_hash = encap
2916 * BIT(1,2) in rss_hash = outer_ip_csum_ok/
2917 * outer_tcp_csum_ok
2918 * used in enic_rq_indicate_buf
2919 */
2920 err = vnic_dev_get_supported_feature_ver(enic->vdev,
2921 VIC_FEATURE_VXLAN,
d1179094 2922 &patch_level, &a1);
257e7382
GV		 2923 if (err)
2924 patch_level = 0;
d1179094 2925 enic->vxlan.flags = (u8)a1;
257e7382
GV		 2926 /* mask bits that are supported by driver
2927 */
2928 patch_level &= BIT_ULL(0) | BIT_ULL(2);
2929 patch_level = fls(patch_level);
2930 patch_level = patch_level ? patch_level - 1 : 0;
2931 enic->vxlan.patch_level = patch_level;
fc9a7def
JK		 2932
2933 if (vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ) == 1 ||
2934 enic->vxlan.flags & ENIC_VXLAN_MULTI_WQ) {
2935 netdev->udp_tunnel_nic_info = &enic_udp_tunnels_v4;
2936 if (enic->vxlan.flags & ENIC_VXLAN_OUTER_IPV6)
2937 netdev->udp_tunnel_nic_info = &enic_udp_tunnels;
2938 }
257e7382 2939 }
5ec8f9b8
MM		 2940
2941 netdev->features |= netdev->hw_features;
e7600449 2942 netdev->vlan_features |= netdev->features;
5ec8f9b8 2943
a145df23
GV		 2944#ifdef CONFIG_RFS_ACCEL
2945 netdev->hw_features |= NETIF_F_NTUPLE;
2946#endif
2947
01f2e4ea
SF		 2948 if (using_dac)
2949 netdev->features |= NETIF_F_HIGHDMA;
2950
01789349
JP		 2951 netdev->priv_flags |= IFF_UNICAST_FLT;
2952
44770e11
JW		 2953 /* MTU range: 68 - 9000 */
2954 netdev->min_mtu = ENIC_MIN_MTU;
2955 netdev->max_mtu = ENIC_MAX_MTU;
cb5c6568 2956 netdev->mtu = enic->port_mtu;
44770e11 2957
01f2e4ea
SF		 2958 err = register_netdev(netdev);
2959 if (err) {
a7a79deb 2960 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 2961 goto err_out_dev_deinit;
01f2e4ea 2962 }
a03bb56e 2963 enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
01f2e4ea
SF		 2964
2965 return 0;
2966
6fdfa970
SF		 2967err_out_dev_deinit:
2968 enic_dev_deinit(enic);
01f2e4ea
SF		 2969err_out_dev_close:
2970 vnic_dev_close(enic->vdev);
8749b427 2971err_out_disable_sriov:
ca2b721d
RP		 2972 kfree(enic->pp);
2973err_out_disable_sriov_pp:
8749b427
RP		 2974#ifdef CONFIG_PCI_IOV
2975 if (enic_sriov_enabled(enic)) {
2976 pci_disable_sriov(pdev);
2977 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2978 }
8749b427 2979#endif
1a69205c 2980err_out_vnic_unregister:
35d87e33 2981 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF		 2982err_out_iounmap:
2983 enic_iounmap(enic);
2984err_out_release_regions:
2985 pci_release_regions(pdev);
2986err_out_disable_device:
2987 pci_disable_device(pdev);
2988err_out_free_netdev:
01f2e4ea
SF		 2989 free_netdev(netdev);
2990
2991 return err;
2992}
2993
854de92f 2994static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF		 2995{
2996 struct net_device *netdev = pci_get_drvdata(pdev);
2997
2998 if (netdev) {
2999 struct enic *enic = netdev_priv(netdev);
3000
23f333a2 3001 cancel_work_sync(&enic->reset);
c97c894d 3002 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 3003 unregister_netdev(netdev);
6fdfa970 3004 enic_dev_deinit(enic);
01f2e4ea 3005 vnic_dev_close(enic->vdev);
8749b427
RP		 3006#ifdef CONFIG_PCI_IOV
3007 if (enic_sriov_enabled(enic)) {
3008 pci_disable_sriov(pdev);
3009 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
3010 }
3011#endif
3f192795 3012 kfree(enic->pp);
01f2e4ea
SF		 3013 vnic_dev_unregister(enic->vdev);
3014 enic_iounmap(enic);
3015 pci_release_regions(pdev);
3016 pci_disable_device(pdev);
01f2e4ea
SF		 3017 free_netdev(netdev);
3018 }
3019}
3020
3021static struct pci_driver enic_driver = {
3022 .name = DRV_NAME,
3023 .id_table = enic_id_table,
3024 .probe = enic_probe,
854de92f 3025 .remove = enic_remove,
01f2e4ea
SF		 3026};
3027
3028static int __init enic_init_module(void)
3029{
01f2e4ea
SF		 3030 return pci_register_driver(&enic_driver);
3031}
3032
3033static void __exit enic_cleanup_module(void)
3034{
3035 pci_unregister_driver(&enic_driver);
3036}
3037
3038module_init(enic_init_module);
3039module_exit(enic_cleanup_module);
Linux 6.x block layer and io_uring tree(s)