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mlx4: fix mlx4_en_set_rxfh()
[linux-block.git] / drivers / net / ethernet / cisco / enic / enic_main.c
CommitLineData
01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF		 27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF		 32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF		 34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
7c2ce6e6 41#include <linux/ktime.h>
b6e97c13
GV		 42#ifdef CONFIG_RFS_ACCEL
43#include <linux/cpu_rmap.h>
44#endif
14747cd9
GV		 45#ifdef CONFIG_NET_RX_BUSY_POLL
46#include <net/busy_poll.h>
47#endif
01f2e4ea
SF		 48
49#include "cq_enet_desc.h"
50#include "vnic_dev.h"
51#include "vnic_intr.h"
52#include "vnic_stats.h"
f8bd9091 53#include "vnic_vic.h"
01f2e4ea
SF		 54#include "enic_res.h"
55#include "enic.h"
51987461 56#include "enic_dev.h"
b3abfbd2 57#include "enic_pp.h"
a145df23 58#include "enic_clsf.h"
01f2e4ea
SF		 59
60#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
SF		 61#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
62#define MAX_TSO (1 << 16)
63#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
64
65#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 66#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 67#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea 68
a03bb56e
GV		 69#define RX_COPYBREAK_DEFAULT 256
70
01f2e4ea 71/* Supported devices */
9baa3c34 72static const struct pci_device_id enic_id_table[] = {
ea0d7d91 73 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF		 76 { 0, } /* end of table */
77};
78
79MODULE_DESCRIPTION(DRV_DESCRIPTION);
80MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
81MODULE_LICENSE("GPL");
82MODULE_VERSION(DRV_VERSION);
83MODULE_DEVICE_TABLE(pci, enic_id_table);
84
7c2ce6e6
SS		 85#define ENIC_LARGE_PKT_THRESHOLD 1000
86#define ENIC_MAX_COALESCE_TIMERS 10
87/* Interrupt moderation table, which will be used to decide the
88 * coalescing timer values
89 * {rx_rate in Mbps, mapping percentage of the range}
90 */
91struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
92 {4000, 0},
93 {4400, 10},
94 {5060, 20},
95 {5230, 30},
96 {5540, 40},
97 {5820, 50},
98 {6120, 60},
99 {6435, 70},
100 {6745, 80},
101 {7000, 90},
102 {0xFFFFFFFF, 100}
103};
104
105/* This table helps the driver to pick different ranges for rx coalescing
106 * timer depending on the link speed.
107 */
108struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
109 {0, 0}, /* 0 - 4 Gbps */
110 {0, 3}, /* 4 - 10 Gbps */
111 {3, 6}, /* 10 - 40 Gbps */
112};
113
3f192795 114int enic_is_dynamic(struct enic *enic)
f8bd9091
SF		 115{
116 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
117}
118
8749b427
RP		 119int enic_sriov_enabled(struct enic *enic)
120{
121 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
122}
123
3a4adef5
RP		 124static int enic_is_sriov_vf(struct enic *enic)
125{
126 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
127}
128
889d13f5
RP		 129int enic_is_valid_vf(struct enic *enic, int vf)
130{
131#ifdef CONFIG_PCI_IOV
132 return vf >= 0 && vf < enic->num_vfs;
133#else
134 return 0;
135#endif
136}
137
01f2e4ea
SF		 138static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
139{
140 struct enic *enic = vnic_dev_priv(wq->vdev);
141
142 if (buf->sop)
143 pci_unmap_single(enic->pdev, buf->dma_addr,
144 buf->len, PCI_DMA_TODEVICE);
145 else
146 pci_unmap_page(enic->pdev, buf->dma_addr,
147 buf->len, PCI_DMA_TODEVICE);
148
149 if (buf->os_buf)
150 dev_kfree_skb_any(buf->os_buf);
151}
152
153static void enic_wq_free_buf(struct vnic_wq *wq,
154 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
155{
156 enic_free_wq_buf(wq, buf);
157}
158
159static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
160 u8 type, u16 q_number, u16 completed_index, void *opaque)
161{
162 struct enic *enic = vnic_dev_priv(vdev);
163
164 spin_lock(&enic->wq_lock[q_number]);
165
166 vnic_wq_service(&enic->wq[q_number], cq_desc,
167 completed_index, enic_wq_free_buf,
168 opaque);
169
822473b6 170 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
SF		 171 vnic_wq_desc_avail(&enic->wq[q_number]) >=
172 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 173 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF		 174
175 spin_unlock(&enic->wq_lock[q_number]);
176
177 return 0;
178}
179
180static void enic_log_q_error(struct enic *enic)
181{
182 unsigned int i;
183 u32 error_status;
184
185 for (i = 0; i < enic->wq_count; i++) {
186 error_status = vnic_wq_error_status(&enic->wq[i]);
187 if (error_status)
a7a79deb
VK		 188 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
189 i, error_status);
01f2e4ea
SF		 190 }
191
192 for (i = 0; i < enic->rq_count; i++) {
193 error_status = vnic_rq_error_status(&enic->rq[i]);
194 if (error_status)
a7a79deb
VK		 195 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
196 i, error_status);
01f2e4ea
SF		 197 }
198}
199
383ab92f 200static void enic_msglvl_check(struct enic *enic)
01f2e4ea 201{
383ab92f 202 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 203
383ab92f 204 if (msg_enable != enic->msg_enable) {
a7a79deb
VK		 205 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
206 enic->msg_enable, msg_enable);
383ab92f 207 enic->msg_enable = msg_enable;
01f2e4ea
SF		 208 }
209}
210
211static void enic_mtu_check(struct enic *enic)
212{
213 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 214 struct net_device *netdev = enic->netdev;
01f2e4ea 215
491598a4 216 if (mtu && mtu != enic->port_mtu) {
7c844599 217 enic->port_mtu = mtu;
7335903c 218 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP		 219 mtu = max_t(int, ENIC_MIN_MTU,
220 min_t(int, ENIC_MAX_MTU, mtu));
221 if (mtu != netdev->mtu)
222 schedule_work(&enic->change_mtu_work);
223 } else {
224 if (mtu < netdev->mtu)
225 netdev_warn(netdev,
226 "interface MTU (%d) set higher "
227 "than switch port MTU (%d)\n",
228 netdev->mtu, mtu);
229 }
01f2e4ea
SF		 230 }
231}
232
383ab92f 233static void enic_link_check(struct enic *enic)
01f2e4ea 234{
383ab92f
VK		 235 int link_status = vnic_dev_link_status(enic->vdev);
236 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 237
383ab92f 238 if (link_status && !carrier_ok) {
a7a79deb 239 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK		 240 netif_carrier_on(enic->netdev);
241 } else if (!link_status && carrier_ok) {
a7a79deb 242 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 243 netif_carrier_off(enic->netdev);
01f2e4ea
SF		 244 }
245}
246
247static void enic_notify_check(struct enic *enic)
248{
249 enic_msglvl_check(enic);
250 enic_mtu_check(enic);
251 enic_link_check(enic);
252}
253
254#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
255
256static irqreturn_t enic_isr_legacy(int irq, void *data)
257{
258 struct net_device *netdev = data;
259 struct enic *enic = netdev_priv(netdev);
717258ba
VK		 260 unsigned int io_intr = enic_legacy_io_intr();
261 unsigned int err_intr = enic_legacy_err_intr();
262 unsigned int notify_intr = enic_legacy_notify_intr();
01f2e4ea
SF		 263 u32 pba;
264
717258ba 265 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
SF		 266
267 pba = vnic_intr_legacy_pba(enic->legacy_pba);
268 if (!pba) {
717258ba 269 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 270 return IRQ_NONE; /* not our interrupt */
271 }
272
717258ba
VK		 273 if (ENIC_TEST_INTR(pba, notify_intr)) {
274 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
01f2e4ea 275 enic_notify_check(enic);
ed8af6b2 276 }
01f2e4ea 277
717258ba
VK		 278 if (ENIC_TEST_INTR(pba, err_intr)) {
279 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
SF		 280 enic_log_q_error(enic);
281 /* schedule recovery from WQ/RQ error */
282 schedule_work(&enic->reset);
283 return IRQ_HANDLED;
284 }
285
717258ba
VK		 286 if (ENIC_TEST_INTR(pba, io_intr)) {
287 if (napi_schedule_prep(&enic->napi[0]))
288 __napi_schedule(&enic->napi[0]);
01f2e4ea 289 } else {
717258ba 290 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 291 }
292
293 return IRQ_HANDLED;
294}
295
296static irqreturn_t enic_isr_msi(int irq, void *data)
297{
298 struct enic *enic = data;
299
300 /* With MSI, there is no sharing of interrupts, so this is
301 * our interrupt and there is no need to ack it. The device
302 * is not providing per-vector masking, so the OS will not
303 * write to PCI config space to mask/unmask the interrupt.
304 * We're using mask_on_assertion for MSI, so the device
305 * automatically masks the interrupt when the interrupt is
306 * generated. Later, when exiting polling, the interrupt
307 * will be unmasked (see enic_poll).
308 *
309 * Also, the device uses the same PCIe Traffic Class (TC)
310 * for Memory Write data and MSI, so there are no ordering
311 * issues; the MSI will always arrive at the Root Complex
312 * _after_ corresponding Memory Writes (i.e. descriptor
313 * writes).
314 */
315
717258ba 316 napi_schedule(&enic->napi[0]);
01f2e4ea
SF		 317
318 return IRQ_HANDLED;
319}
320
4cfe8785 321static irqreturn_t enic_isr_msix(int irq, void *data)
01f2e4ea 322{
717258ba 323 struct napi_struct *napi = data;
01f2e4ea 324
717258ba 325 napi_schedule(napi);
01f2e4ea
SF		 326
327 return IRQ_HANDLED;
328}
329
01f2e4ea
SF		 330static irqreturn_t enic_isr_msix_err(int irq, void *data)
331{
332 struct enic *enic = data;
717258ba 333 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 334
717258ba 335 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 336
01f2e4ea
SF		 337 enic_log_q_error(enic);
338
339 /* schedule recovery from WQ/RQ error */
340 schedule_work(&enic->reset);
341
342 return IRQ_HANDLED;
343}
344
345static irqreturn_t enic_isr_msix_notify(int irq, void *data)
346{
347 struct enic *enic = data;
717258ba 348 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea 349
717258ba 350 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea 351 enic_notify_check(enic);
01f2e4ea
SF		 352
353 return IRQ_HANDLED;
354}
355
356static inline void enic_queue_wq_skb_cont(struct enic *enic,
357 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 358 unsigned int len_left, int loopback)
01f2e4ea 359{
9e903e08 360 const skb_frag_t *frag;
01f2e4ea
SF		 361
362 /* Queue additional data fragments */
363 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 364 len_left -= skb_frag_size(frag);
01f2e4ea 365 enic_queue_wq_desc_cont(wq, skb,
4bf5adbf 366 skb_frag_dma_map(&enic->pdev->dev,
9e903e08 367 frag, 0, skb_frag_size(frag),
5d6bcdfe 368 DMA_TO_DEVICE),
9e903e08 369 skb_frag_size(frag),
1825aca6
VK		 370 (len_left == 0), /* EOP? */
371 loopback);
01f2e4ea
SF		 372 }
373}
374
375static inline void enic_queue_wq_skb_vlan(struct enic *enic,
376 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 377 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 378{
379 unsigned int head_len = skb_headlen(skb);
380 unsigned int len_left = skb->len - head_len;
381 int eop = (len_left == 0);
382
ea0d7d91
SF		 383 /* Queue the main skb fragment. The fragments are no larger
384 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
385 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
386 * per fragment is queued.
387 */
01f2e4ea
SF		 388 enic_queue_wq_desc(wq, skb,
389 pci_map_single(enic->pdev, skb->data,
390 head_len, PCI_DMA_TODEVICE),
391 head_len,
392 vlan_tag_insert, vlan_tag,
1825aca6 393 eop, loopback);
01f2e4ea
SF		 394
395 if (!eop)
1825aca6 396 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF		 397}
398
399static inline void enic_queue_wq_skb_csum_l4(struct enic *enic,
400 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 401 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 402{
403 unsigned int head_len = skb_headlen(skb);
404 unsigned int len_left = skb->len - head_len;
0d0b1672 405 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF		 406 unsigned int csum_offset = hdr_len + skb->csum_offset;
407 int eop = (len_left == 0);
408
ea0d7d91
SF		 409 /* Queue the main skb fragment. The fragments are no larger
410 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
411 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
412 * per fragment is queued.
413 */
01f2e4ea
SF		 414 enic_queue_wq_desc_csum_l4(wq, skb,
415 pci_map_single(enic->pdev, skb->data,
416 head_len, PCI_DMA_TODEVICE),
417 head_len,
418 csum_offset,
419 hdr_len,
420 vlan_tag_insert, vlan_tag,
1825aca6 421 eop, loopback);
01f2e4ea
SF		 422
423 if (!eop)
1825aca6 424 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF		 425}
426
427static inline void enic_queue_wq_skb_tso(struct enic *enic,
428 struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss,
1825aca6 429 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea 430{
ea0d7d91
SF		 431 unsigned int frag_len_left = skb_headlen(skb);
432 unsigned int len_left = skb->len - frag_len_left;
01f2e4ea
SF		 433 unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
434 int eop = (len_left == 0);
ea0d7d91
SF		 435 unsigned int len;
436 dma_addr_t dma_addr;
437 unsigned int offset = 0;
438 skb_frag_t *frag;
01f2e4ea
SF		 439
440 /* Preload TCP csum field with IP pseudo hdr calculated
441 * with IP length set to zero. HW will later add in length
442 * to each TCP segment resulting from the TSO.
443 */
444
09640e63 445 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF		 446 ip_hdr(skb)->check = 0;
447 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
448 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 449 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
01f2e4ea
SF		 450 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
451 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
452 }
453
ea0d7d91
SF		 454 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
455 * for the main skb fragment
456 */
457 while (frag_len_left) {
458 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
459 dma_addr = pci_map_single(enic->pdev, skb->data + offset,
460 len, PCI_DMA_TODEVICE);
461 enic_queue_wq_desc_tso(wq, skb,
462 dma_addr,
463 len,
464 mss, hdr_len,
465 vlan_tag_insert, vlan_tag,
1825aca6 466 eop && (len == frag_len_left), loopback);
ea0d7d91
SF		 467 frag_len_left -= len;
468 offset += len;
469 }
01f2e4ea 470
ea0d7d91
SF		 471 if (eop)
472 return;
473
474 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
475 * for additional data fragments
476 */
477 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED		 478 len_left -= skb_frag_size(frag);
479 frag_len_left = skb_frag_size(frag);
4bf5adbf 480 offset = 0;
ea0d7d91
SF		 481
482 while (frag_len_left) {
483 len = min(frag_len_left,
484 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC		 485 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
486 offset, len,
5d6bcdfe 487 DMA_TO_DEVICE);
ea0d7d91
SF		 488 enic_queue_wq_desc_cont(wq, skb,
489 dma_addr,
490 len,
491 (len_left == 0) &&
1825aca6
VK		 492 (len == frag_len_left), /* EOP? */
493 loopback);
ea0d7d91
SF		 494 frag_len_left -= len;
495 offset += len;
496 }
497 }
01f2e4ea
SF		 498}
499
500static inline void enic_queue_wq_skb(struct enic *enic,
501 struct vnic_wq *wq, struct sk_buff *skb)
502{
503 unsigned int mss = skb_shinfo(skb)->gso_size;
504 unsigned int vlan_tag = 0;
505 int vlan_tag_insert = 0;
1825aca6 506 int loopback = 0;
01f2e4ea 507
eab6d18d 508 if (vlan_tx_tag_present(skb)) {
01f2e4ea
SF		 509 /* VLAN tag from trunking driver */
510 vlan_tag_insert = 1;
511 vlan_tag = vlan_tx_tag_get(skb);
1825aca6
VK		 512 } else if (enic->loop_enable) {
513 vlan_tag = enic->loop_tag;
514 loopback = 1;
01f2e4ea
SF		 515 }
516
517 if (mss)
518 enic_queue_wq_skb_tso(enic, wq, skb, mss,
1825aca6 519 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 520 else if (skb->ip_summed == CHECKSUM_PARTIAL)
521 enic_queue_wq_skb_csum_l4(enic, wq, skb,
1825aca6 522 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 523 else
524 enic_queue_wq_skb_vlan(enic, wq, skb,
1825aca6 525 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 526}
527
ed8af6b2 528/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 529static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 530 struct net_device *netdev)
01f2e4ea
SF		 531{
532 struct enic *enic = netdev_priv(netdev);
822473b6 533 struct vnic_wq *wq;
01f2e4ea 534 unsigned long flags;
822473b6 535 unsigned int txq_map;
f8e34d24 536 struct netdev_queue *txq;
01f2e4ea
SF		 537
538 if (skb->len <= 0) {
98d8a65d 539 dev_kfree_skb_any(skb);
01f2e4ea
SF		 540 return NETDEV_TX_OK;
541 }
542
822473b6 543 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
544 wq = &enic->wq[txq_map];
f8e34d24 545 txq = netdev_get_tx_queue(netdev, txq_map);
822473b6 546
01f2e4ea
SF		 547 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
548 * which is very likely. In the off chance it's going to take
549 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
550 */
551
552 if (skb_shinfo(skb)->gso_size == 0 &&
553 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
554 skb_linearize(skb)) {
98d8a65d 555 dev_kfree_skb_any(skb);
01f2e4ea
SF		 556 return NETDEV_TX_OK;
557 }
558
822473b6 559 spin_lock_irqsave(&enic->wq_lock[txq_map], flags);
01f2e4ea 560
ea0d7d91
SF		 561 if (vnic_wq_desc_avail(wq) <
562 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
f8e34d24 563 netif_tx_stop_queue(txq);
01f2e4ea 564 /* This is a hard error, log it */
a7a79deb 565 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
822473b6 566 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
01f2e4ea
SF		 567 return NETDEV_TX_BUSY;
568 }
569
570 enic_queue_wq_skb(enic, wq, skb);
571
ea0d7d91 572 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
f8e34d24
GV		 573 netif_tx_stop_queue(txq);
574 if (!skb->xmit_more || netif_xmit_stopped(txq))
575 vnic_wq_doorbell(wq);
01f2e4ea 576
822473b6 577 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
01f2e4ea
SF		 578
579 return NETDEV_TX_OK;
580}
581
582/* dev_base_lock rwlock held, nominally process context */
f20530bc 583static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev,
584 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF		 585{
586 struct enic *enic = netdev_priv(netdev);
587 struct vnic_stats *stats;
588
383ab92f 589 enic_dev_stats_dump(enic, &stats);
01f2e4ea 590
25f0a061
SF		 591 net_stats->tx_packets = stats->tx.tx_frames_ok;
592 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
593 net_stats->tx_errors = stats->tx.tx_errors;
594 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 595
25f0a061
SF		 596 net_stats->rx_packets = stats->rx.rx_frames_ok;
597 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
598 net_stats->rx_errors = stats->rx.rx_errors;
599 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 600 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 601 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 602 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea 603
25f0a061 604 return net_stats;
01f2e4ea
SF		 605}
606
f009618a
AD		 607static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
608{
609 struct enic *enic = netdev_priv(netdev);
610
611 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
612 unsigned int mc_count = netdev_mc_count(netdev);
613
614 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
615 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
616
617 return -ENOSPC;
618 }
619
620 enic_dev_add_addr(enic, mc_addr);
621 enic->mc_count++;
622
623 return 0;
624}
625
626static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
627{
628 struct enic *enic = netdev_priv(netdev);
629
630 enic_dev_del_addr(enic, mc_addr);
631 enic->mc_count--;
632
633 return 0;
634}
635
636static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
637{
638 struct enic *enic = netdev_priv(netdev);
639
640 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
641 unsigned int uc_count = netdev_uc_count(netdev);
642
643 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
644 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
645
646 return -ENOSPC;
647 }
648
649 enic_dev_add_addr(enic, uc_addr);
650 enic->uc_count++;
651
652 return 0;
653}
654
655static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
656{
657 struct enic *enic = netdev_priv(netdev);
658
659 enic_dev_del_addr(enic, uc_addr);
660 enic->uc_count--;
661
662 return 0;
663}
664
b3abfbd2 665void enic_reset_addr_lists(struct enic *enic)
01f2e4ea 666{
f009618a
AD		 667 struct net_device *netdev = enic->netdev;
668
669 __dev_uc_unsync(netdev, NULL);
670 __dev_mc_unsync(netdev, NULL);
671
01f2e4ea 672 enic->mc_count = 0;
e0afe53f 673 enic->uc_count = 0;
99ef5639 674 enic->flags = 0;
01f2e4ea
SF		 675}
676
677static int enic_set_mac_addr(struct net_device *netdev, char *addr)
678{
f8bd9091
SF		 679 struct enic *enic = netdev_priv(netdev);
680
7335903c 681 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF		 682 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
683 return -EADDRNOTAVAIL;
684 } else {
685 if (!is_valid_ether_addr(addr))
686 return -EADDRNOTAVAIL;
687 }
01f2e4ea
SF		 688
689 memcpy(netdev->dev_addr, addr, netdev->addr_len);
690
691 return 0;
692}
693
f8bd9091
SF		 694static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
695{
696 struct enic *enic = netdev_priv(netdev);
697 struct sockaddr *saddr = p;
698 char *addr = saddr->sa_data;
699 int err;
700
701 if (netif_running(enic->netdev)) {
702 err = enic_dev_del_station_addr(enic);
703 if (err)
704 return err;
705 }
706
707 err = enic_set_mac_addr(netdev, addr);
708 if (err)
709 return err;
710
711 if (netif_running(enic->netdev)) {
712 err = enic_dev_add_station_addr(enic);
713 if (err)
714 return err;
715 }
716
717 return err;
718}
719
720static int enic_set_mac_address(struct net_device *netdev, void *p)
721{
294dab25 722 struct sockaddr *saddr = p;
c76fd32d
VK		 723 char *addr = saddr->sa_data;
724 struct enic *enic = netdev_priv(netdev);
725 int err;
726
727 err = enic_dev_del_station_addr(enic);
728 if (err)
729 return err;
730
731 err = enic_set_mac_addr(netdev, addr);
732 if (err)
733 return err;
294dab25 734
c76fd32d 735 return enic_dev_add_station_addr(enic);
f8bd9091
SF		 736}
737
319d7e84
RP		 738/* netif_tx_lock held, BHs disabled */
739static void enic_set_rx_mode(struct net_device *netdev)
740{
741 struct enic *enic = netdev_priv(netdev);
742 int directed = 1;
743 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
744 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
745 int promisc = (netdev->flags & IFF_PROMISC) ||
746 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
747 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
748 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
749 unsigned int flags = netdev->flags |
750 (allmulti ? IFF_ALLMULTI : 0) |
751 (promisc ? IFF_PROMISC : 0);
752
753 if (enic->flags != flags) {
754 enic->flags = flags;
755 enic_dev_packet_filter(enic, directed,
756 multicast, broadcast, promisc, allmulti);
757 }
758
759 if (!promisc) {
f009618a 760 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
319d7e84 761 if (!allmulti)
f009618a 762 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
319d7e84
RP		 763 }
764}
765
01f2e4ea
SF		 766/* netif_tx_lock held, BHs disabled */
767static void enic_tx_timeout(struct net_device *netdev)
768{
769 struct enic *enic = netdev_priv(netdev);
770 schedule_work(&enic->reset);
771}
772
0b1c00fc
RP		 773static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
774{
775 struct enic *enic = netdev_priv(netdev);
3f192795
RP		 776 struct enic_port_profile *pp;
777 int err;
0b1c00fc 778
3f192795
RP		 779 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
780 if (err)
781 return err;
0b1c00fc 782
b8622cbd 783 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP		 784 if (vf == PORT_SELF_VF) {
785 memcpy(pp->vf_mac, mac, ETH_ALEN);
786 return 0;
787 } else {
788 /*
789 * For sriov vf's set the mac in hw
790 */
791 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
792 vnic_dev_set_mac_addr, mac);
793 return enic_dev_status_to_errno(err);
794 }
0b1c00fc
RP		 795 } else
796 return -EINVAL;
797}
798
f8bd9091
SF		 799static int enic_set_vf_port(struct net_device *netdev, int vf,
800 struct nlattr *port[])
801{
802 struct enic *enic = netdev_priv(netdev);
b3abfbd2 803 struct enic_port_profile prev_pp;
3f192795 804 struct enic_port_profile *pp;
b3abfbd2 805 int err = 0, restore_pp = 1;
08f382eb 806
3f192795
RP		 807 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
808 if (err)
809 return err;
08f382eb 810
b3abfbd2
RP		 811 if (!port[IFLA_PORT_REQUEST])
812 return -EOPNOTSUPP;
813
3f192795
RP		 814 memcpy(&prev_pp, pp, sizeof(*enic->pp));
815 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 816
3f192795
RP		 817 pp->set |= ENIC_SET_REQUEST;
818 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF		 819
820 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP		 821 pp->set |= ENIC_SET_NAME;
822 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF		 823 PORT_PROFILE_MAX);
824 }
825
826 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP		 827 pp->set |= ENIC_SET_INSTANCE;
828 memcpy(pp->instance_uuid,
08f382eb
SF		 829 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
830 }
831
832 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP		 833 pp->set |= ENIC_SET_HOST;
834 memcpy(pp->host_uuid,
08f382eb
SF		 835 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
836 }
f8bd9091 837
b4765833
RP		 838 if (vf == PORT_SELF_VF) {
839 /* Special case handling: mac came from IFLA_VF_MAC */
840 if (!is_zero_ether_addr(prev_pp.vf_mac))
841 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 842
b4765833
RP		 843 if (is_zero_ether_addr(netdev->dev_addr))
844 eth_hw_addr_random(netdev);
845 } else {
846 /* SR-IOV VF: get mac from adapter */
847 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
848 vnic_dev_get_mac_addr, pp->mac_addr);
849 if (err) {
850 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
851 memcpy(pp, &prev_pp, sizeof(*pp));
852 return enic_dev_status_to_errno(err);
853 }
854 }
f8bd9091 855
3f192795 856 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP		 857 if (err) {
858 if (restore_pp) {
859 /* Things are still the way they were: Implicit
860 * DISASSOCIATE failed
861 */
3f192795 862 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 863 } else {
3f192795
RP		 864 memset(pp, 0, sizeof(*pp));
865 if (vf == PORT_SELF_VF)
866 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP		 867 }
868 } else {
869 /* Set flag to indicate that the port assoc/disassoc
870 * request has been sent out to fw
871 */
3f192795 872 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP		 873
874 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795
RP		 875 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
876 memset(pp->mac_addr, 0, ETH_ALEN);
877 if (vf == PORT_SELF_VF)
878 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP		 879 }
880 }
29639059 881
b4765833
RP		 882 if (vf == PORT_SELF_VF)
883 memset(pp->vf_mac, 0, ETH_ALEN);
29639059 884
29639059 885 return err;
f8bd9091
SF		 886}
887
888static int enic_get_vf_port(struct net_device *netdev, int vf,
889 struct sk_buff *skb)
890{
891 struct enic *enic = netdev_priv(netdev);
f8bd9091 892 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 893 struct enic_port_profile *pp;
b3abfbd2 894 int err;
f8bd9091 895
3f192795
RP		 896 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
897 if (err)
898 return err;
899
900 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 901 return -ENODATA;
f8bd9091 902
3f192795 903 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 904 if (err)
b3abfbd2 905 return err;
f8bd9091 906
1a106de6
DM		 907 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
908 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
909 ((pp->set & ENIC_SET_NAME) &&
910 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
911 ((pp->set & ENIC_SET_INSTANCE) &&
912 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
913 pp->instance_uuid)) ||
914 ((pp->set & ENIC_SET_HOST) &&
915 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
916 goto nla_put_failure;
f8bd9091
SF		 917 return 0;
918
919nla_put_failure:
920 return -EMSGSIZE;
921}
922
01f2e4ea
SF		 923static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
924{
925 struct enic *enic = vnic_dev_priv(rq->vdev);
926
927 if (!buf->os_buf)
928 return;
929
930 pci_unmap_single(enic->pdev, buf->dma_addr,
931 buf->len, PCI_DMA_FROMDEVICE);
932 dev_kfree_skb_any(buf->os_buf);
a03bb56e 933 buf->os_buf = NULL;
01f2e4ea
SF		 934}
935
01f2e4ea
SF		 936static int enic_rq_alloc_buf(struct vnic_rq *rq)
937{
938 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 939 struct net_device *netdev = enic->netdev;
01f2e4ea 940 struct sk_buff *skb;
1825aca6 941 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF		 942 unsigned int os_buf_index = 0;
943 dma_addr_t dma_addr;
a03bb56e
GV		 944 struct vnic_rq_buf *buf = rq->to_use;
945
946 if (buf->os_buf) {
f6b7734b
GV		 947 enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
948 buf->len);
01f2e4ea 949
a03bb56e
GV		 950 return 0;
951 }
89d71a66 952 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF		 953 if (!skb)
954 return -ENOMEM;
955
956 dma_addr = pci_map_single(enic->pdev, skb->data,
957 len, PCI_DMA_FROMDEVICE);
958
959 enic_queue_rq_desc(rq, skb, os_buf_index,
960 dma_addr, len);
961
962 return 0;
963}
964
7c2ce6e6
SS		 965static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
966 u32 pkt_len)
967{
968 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
969 pkt_size->large_pkt_bytes_cnt += pkt_len;
970 else
971 pkt_size->small_pkt_bytes_cnt += pkt_len;
972}
973
a03bb56e
GV		 974static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
975 struct vnic_rq_buf *buf, u16 len)
976{
977 struct enic *enic = netdev_priv(netdev);
978 struct sk_buff *new_skb;
979
980 if (len > enic->rx_copybreak)
981 return false;
982 new_skb = netdev_alloc_skb_ip_align(netdev, len);
983 if (!new_skb)
984 return false;
985 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
986 DMA_FROM_DEVICE);
987 memcpy(new_skb->data, (*skb)->data, len);
988 *skb = new_skb;
989
990 return true;
991}
992
01f2e4ea
SF		 993static void enic_rq_indicate_buf(struct vnic_rq *rq,
994 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
995 int skipped, void *opaque)
996{
997 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 998 struct net_device *netdev = enic->netdev;
01f2e4ea 999 struct sk_buff *skb;
7c2ce6e6 1000 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
01f2e4ea
SF		 1001
1002 u8 type, color, eop, sop, ingress_port, vlan_stripped;
1003 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
1004 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
1005 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
1006 u8 packet_error;
f8cac14a 1007 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea
SF		 1008 u32 rss_hash;
1009
1010 if (skipped)
1011 return;
1012
1013 skb = buf->os_buf;
01f2e4ea
SF		 1014
1015 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
1016 &type, &color, &q_number, &completed_index,
1017 &ingress_port, &fcoe, &eop, &sop, &rss_type,
1018 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 1019 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF		 1020 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
1021 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
1022 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
1023 &fcs_ok);
1024
1025 if (packet_error) {
1026
350991e1
SF		 1027 if (!fcs_ok) {
1028 if (bytes_written > 0)
1029 enic->rq_bad_fcs++;
1030 else if (bytes_written == 0)
1031 enic->rq_truncated_pkts++;
1032 }
01f2e4ea 1033
44aa91ab
GV		 1034 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1035 PCI_DMA_FROMDEVICE);
01f2e4ea 1036 dev_kfree_skb_any(skb);
44aa91ab 1037 buf->os_buf = NULL;
01f2e4ea
SF		 1038
1039 return;
1040 }
1041
1042 if (eop && bytes_written > 0) {
1043
1044 /* Good receive
1045 */
1046
a03bb56e
GV		 1047 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
1048 buf->os_buf = NULL;
1049 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1050 PCI_DMA_FROMDEVICE);
1051 }
1052 prefetch(skb->data - NET_IP_ALIGN);
1053
01f2e4ea 1054 skb_put(skb, bytes_written);
86ca9db7 1055 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1056 skb_record_rx_queue(skb, q_number);
1057 if (netdev->features & NETIF_F_RXHASH) {
3739acdd
TH		 1058 skb_set_hash(skb, rss_hash,
1059 (rss_type &
1060 (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX |
1061 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 |
1062 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ?
1063 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
bf751ba8 1064 }
01f2e4ea 1065
5ec8f9b8 1066 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc) {
01f2e4ea
SF		 1067 skb->csum = htons(checksum);
1068 skb->ip_summed = CHECKSUM_COMPLETE;
1069 }
1070
6ede746b 1071 if (vlan_stripped)
86a9bad3 1072 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1073
14747cd9
GV		 1074 skb_mark_napi_id(skb, &enic->napi[rq->index]);
1075 if (enic_poll_busy_polling(rq) ||
1076 !(netdev->features & NETIF_F_GRO))
6ede746b 1077 netif_receive_skb(skb);
14747cd9
GV		 1078 else
1079 napi_gro_receive(&enic->napi[q_number], skb);
7c2ce6e6
SS		 1080 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1081 enic_intr_update_pkt_size(&cq->pkt_size_counter,
1082 bytes_written);
01f2e4ea
SF		 1083 } else {
1084
1085 /* Buffer overflow
1086 */
1087
44aa91ab
GV		 1088 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1089 PCI_DMA_FROMDEVICE);
01f2e4ea 1090 dev_kfree_skb_any(skb);
44aa91ab 1091 buf->os_buf = NULL;
01f2e4ea
SF		 1092 }
1093}
1094
1095static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1096 u8 type, u16 q_number, u16 completed_index, void *opaque)
1097{
1098 struct enic *enic = vnic_dev_priv(vdev);
1099
1100 vnic_rq_service(&enic->rq[q_number], cq_desc,
1101 completed_index, VNIC_RQ_RETURN_DESC,
1102 enic_rq_indicate_buf, opaque);
1103
1104 return 0;
1105}
1106
01f2e4ea
SF		 1107static int enic_poll(struct napi_struct *napi, int budget)
1108{
717258ba
VK		 1109 struct net_device *netdev = napi->dev;
1110 struct enic *enic = netdev_priv(netdev);
1111 unsigned int cq_rq = enic_cq_rq(enic, 0);
1112 unsigned int cq_wq = enic_cq_wq(enic, 0);
1113 unsigned int intr = enic_legacy_io_intr();
01f2e4ea
SF		 1114 unsigned int rq_work_to_do = budget;
1115 unsigned int wq_work_to_do = -1; /* no limit */
4c502549 1116 unsigned int work_done, rq_work_done = 0, wq_work_done;
2d6ddced 1117 int err;
01f2e4ea 1118
14747cd9
GV		 1119 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
1120 enic_wq_service, NULL);
1121
1122 if (!enic_poll_lock_napi(&enic->rq[cq_rq])) {
1123 if (wq_work_done > 0)
1124 vnic_intr_return_credits(&enic->intr[intr],
1125 wq_work_done,
1126 0 /* dont unmask intr */,
1127 0 /* dont reset intr timer */);
1128 return rq_work_done;
1129 }
01f2e4ea 1130
4c502549
EB		 1131 if (budget > 0)
1132 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
1133 rq_work_to_do, enic_rq_service, NULL);
01f2e4ea 1134
01f2e4ea
SF		 1135 /* Accumulate intr event credits for this polling
1136 * cycle. An intr event is the completion of a
1137 * a WQ or RQ packet.
1138 */
1139
1140 work_done = rq_work_done + wq_work_done;
1141
1142 if (work_done > 0)
717258ba 1143 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1144 work_done,
1145 0 /* don't unmask intr */,
1146 0 /* don't reset intr timer */);
1147
0eb26022 1148 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1149
2d6ddced
SF		 1150 /* Buffer allocation failed. Stay in polling
1151 * mode so we can try to fill the ring again.
1152 */
01f2e4ea 1153
2d6ddced
SF		 1154 if (err)
1155 rq_work_done = rq_work_to_do;
01f2e4ea 1156
2d6ddced 1157 if (rq_work_done < rq_work_to_do) {
01f2e4ea 1158
2d6ddced 1159 /* Some work done, but not enough to stay in polling,
88132f55 1160 * exit polling
01f2e4ea
SF		 1161 */
1162
288379f0 1163 napi_complete(napi);
717258ba 1164 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1165 }
14747cd9 1166 enic_poll_unlock_napi(&enic->rq[cq_rq]);
01f2e4ea
SF		 1167
1168 return rq_work_done;
1169}
1170
7c2ce6e6
SS		 1171static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
1172{
1173 unsigned int intr = enic_msix_rq_intr(enic, rq->index);
1174 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1175 u32 timer = cq->tobe_rx_coal_timeval;
1176
1177 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
1178 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
1179 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
1180 }
1181}
1182
1183static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
1184{
1185 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1186 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1187 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
1188 int index;
1189 u32 timer;
1190 u32 range_start;
1191 u32 traffic;
1192 u64 delta;
1193 ktime_t now = ktime_get();
1194
1195 delta = ktime_us_delta(now, cq->prev_ts);
1196 if (delta < ENIC_AIC_TS_BREAK)
1197 return;
1198 cq->prev_ts = now;
1199
1200 traffic = pkt_size_counter->large_pkt_bytes_cnt +
1201 pkt_size_counter->small_pkt_bytes_cnt;
1202 /* The table takes Mbps
1203 * traffic *= 8 => bits
1204 * traffic *= (10^6 / delta) => bps
1205 * traffic /= 10^6 => Mbps
1206 *
1207 * Combining, traffic *= (8 / delta)
1208 */
1209
1210 traffic <<= 3;
958c492c 1211 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
7c2ce6e6
SS		 1212
1213 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
1214 if (traffic < mod_table[index].rx_rate)
1215 break;
1216 range_start = (pkt_size_counter->small_pkt_bytes_cnt >
1217 pkt_size_counter->large_pkt_bytes_cnt << 1) ?
1218 rx_coal->small_pkt_range_start :
1219 rx_coal->large_pkt_range_start;
1220 timer = range_start + ((rx_coal->range_end - range_start) *
1221 mod_table[index].range_percent / 100);
1222 /* Damping */
1223 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
1224
1225 pkt_size_counter->large_pkt_bytes_cnt = 0;
1226 pkt_size_counter->small_pkt_bytes_cnt = 0;
1227}
1228
b6e97c13
GV		 1229#ifdef CONFIG_RFS_ACCEL
1230static void enic_free_rx_cpu_rmap(struct enic *enic)
1231{
1232 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
1233 enic->netdev->rx_cpu_rmap = NULL;
1234}
1235
1236static void enic_set_rx_cpu_rmap(struct enic *enic)
1237{
1238 int i, res;
1239
1240 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
1241 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
1242 if (unlikely(!enic->netdev->rx_cpu_rmap))
1243 return;
1244 for (i = 0; i < enic->rq_count; i++) {
1245 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
1246 enic->msix_entry[i].vector);
1247 if (unlikely(res)) {
1248 enic_free_rx_cpu_rmap(enic);
1249 return;
1250 }
1251 }
1252 }
1253}
1254
1255#else
1256
1257static void enic_free_rx_cpu_rmap(struct enic *enic)
1258{
1259}
1260
1261static void enic_set_rx_cpu_rmap(struct enic *enic)
1262{
1263}
1264
1265#endif /* CONFIG_RFS_ACCEL */
1266
14747cd9
GV		 1267#ifdef CONFIG_NET_RX_BUSY_POLL
1268int enic_busy_poll(struct napi_struct *napi)
1269{
1270 struct net_device *netdev = napi->dev;
1271 struct enic *enic = netdev_priv(netdev);
1272 unsigned int rq = (napi - &enic->napi[0]);
1273 unsigned int cq = enic_cq_rq(enic, rq);
1274 unsigned int intr = enic_msix_rq_intr(enic, rq);
1275 unsigned int work_to_do = -1; /* clean all pkts possible */
1276 unsigned int work_done;
1277
1278 if (!enic_poll_lock_poll(&enic->rq[rq]))
1279 return LL_FLUSH_BUSY;
1280 work_done = vnic_cq_service(&enic->cq[cq], work_to_do,
1281 enic_rq_service, NULL);
1282
1283 if (work_done > 0)
1284 vnic_intr_return_credits(&enic->intr[intr],
1285 work_done, 0, 0);
1286 vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
1287 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1288 enic_calc_int_moderation(enic, &enic->rq[rq]);
1289 enic_poll_unlock_poll(&enic->rq[rq]);
1290
1291 return work_done;
1292}
1293#endif /* CONFIG_NET_RX_BUSY_POLL */
1294
4cfe8785
GV		 1295static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
1296{
1297 struct net_device *netdev = napi->dev;
1298 struct enic *enic = netdev_priv(netdev);
1299 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
1300 struct vnic_wq *wq = &enic->wq[wq_index];
1301 unsigned int cq;
1302 unsigned int intr;
1303 unsigned int wq_work_to_do = -1; /* clean all desc possible */
1304 unsigned int wq_work_done;
1305 unsigned int wq_irq;
1306
1307 wq_irq = wq->index;
1308 cq = enic_cq_wq(enic, wq_irq);
1309 intr = enic_msix_wq_intr(enic, wq_irq);
1310 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
1311 enic_wq_service, NULL);
1312
1313 vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
1314 0 /* don't unmask intr */,
1315 1 /* reset intr timer */);
1316 if (!wq_work_done) {
1317 napi_complete(napi);
1318 vnic_intr_unmask(&enic->intr[intr]);
f41281d0 1319 return 0;
4cfe8785
GV		 1320 }
1321
f41281d0 1322 return budget;
4cfe8785
GV		 1323}
1324
1325static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
01f2e4ea 1326{
717258ba
VK		 1327 struct net_device *netdev = napi->dev;
1328 struct enic *enic = netdev_priv(netdev);
1329 unsigned int rq = (napi - &enic->napi[0]);
1330 unsigned int cq = enic_cq_rq(enic, rq);
1331 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea 1332 unsigned int work_to_do = budget;
4c502549 1333 unsigned int work_done = 0;
2d6ddced 1334 int err;
01f2e4ea 1335
14747cd9
GV		 1336 if (!enic_poll_lock_napi(&enic->rq[rq]))
1337 return work_done;
01f2e4ea
SF		 1338 /* Service RQ
1339 */
1340
4c502549
EB		 1341 if (budget > 0)
1342 work_done = vnic_cq_service(&enic->cq[cq],
1343 work_to_do, enic_rq_service, NULL);
01f2e4ea 1344
2d6ddced
SF		 1345 /* Return intr event credits for this polling
1346 * cycle. An intr event is the completion of a
1347 * RQ packet.
1348 */
01f2e4ea 1349
2d6ddced 1350 if (work_done > 0)
717258ba 1351 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1352 work_done,
1353 0 /* don't unmask intr */,
1354 0 /* don't reset intr timer */);
01f2e4ea 1355
0eb26022 1356 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF		 1357
1358 /* Buffer allocation failed. Stay in polling mode
1359 * so we can try to fill the ring again.
1360 */
1361
1362 if (err)
1363 work_done = work_to_do;
7c2ce6e6
SS		 1364 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1365 /* Call the function which refreshes
1366 * the intr coalescing timer value based on
1367 * the traffic. This is supported only in
1368 * the case of MSI-x mode
1369 */
1370 enic_calc_int_moderation(enic, &enic->rq[rq]);
2d6ddced
SF		 1371
1372 if (work_done < work_to_do) {
1373
1374 /* Some work done, but not enough to stay in polling,
88132f55 1375 * exit polling
01f2e4ea
SF		 1376 */
1377
288379f0 1378 napi_complete(napi);
7c2ce6e6
SS		 1379 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1380 enic_set_int_moderation(enic, &enic->rq[rq]);
717258ba 1381 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1382 }
14747cd9 1383 enic_poll_unlock_napi(&enic->rq[rq]);
01f2e4ea
SF		 1384
1385 return work_done;
1386}
1387
1388static void enic_notify_timer(unsigned long data)
1389{
1390 struct enic *enic = (struct enic *)data;
1391
1392 enic_notify_check(enic);
1393
25f0a061
SF		 1394 mod_timer(&enic->notify_timer,
1395 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF		 1396}
1397
1398static void enic_free_intr(struct enic *enic)
1399{
1400 struct net_device *netdev = enic->netdev;
1401 unsigned int i;
1402
b6e97c13 1403 enic_free_rx_cpu_rmap(enic);
01f2e4ea
SF		 1404 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1405 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF		 1406 free_irq(enic->pdev->irq, netdev);
1407 break;
8f4d248c
SF		 1408 case VNIC_DEV_INTR_MODE_MSI:
1409 free_irq(enic->pdev->irq, enic);
1410 break;
01f2e4ea
SF		 1411 case VNIC_DEV_INTR_MODE_MSIX:
1412 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1413 if (enic->msix[i].requested)
1414 free_irq(enic->msix_entry[i].vector,
1415 enic->msix[i].devid);
1416 break;
1417 default:
1418 break;
1419 }
1420}
1421
1422static int enic_request_intr(struct enic *enic)
1423{
1424 struct net_device *netdev = enic->netdev;
717258ba 1425 unsigned int i, intr;
01f2e4ea
SF		 1426 int err = 0;
1427
b6e97c13 1428 enic_set_rx_cpu_rmap(enic);
01f2e4ea
SF		 1429 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1430
1431 case VNIC_DEV_INTR_MODE_INTX:
1432
1433 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1434 IRQF_SHARED, netdev->name, netdev);
1435 break;
1436
1437 case VNIC_DEV_INTR_MODE_MSI:
1438
1439 err = request_irq(enic->pdev->irq, enic_isr_msi,
1440 0, netdev->name, enic);
1441 break;
1442
1443 case VNIC_DEV_INTR_MODE_MSIX:
1444
717258ba
VK		 1445 for (i = 0; i < enic->rq_count; i++) {
1446 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC		 1447 snprintf(enic->msix[intr].devname,
1448 sizeof(enic->msix[intr].devname),
717258ba 1449 "%.11s-rx-%d", netdev->name, i);
4cfe8785 1450 enic->msix[intr].isr = enic_isr_msix;
717258ba
VK		 1451 enic->msix[intr].devid = &enic->napi[i];
1452 }
01f2e4ea 1453
717258ba 1454 for (i = 0; i < enic->wq_count; i++) {
4cfe8785
GV		 1455 int wq = enic_cq_wq(enic, i);
1456
717258ba 1457 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC		 1458 snprintf(enic->msix[intr].devname,
1459 sizeof(enic->msix[intr].devname),
717258ba 1460 "%.11s-tx-%d", netdev->name, i);
4cfe8785
GV		 1461 enic->msix[intr].isr = enic_isr_msix;
1462 enic->msix[intr].devid = &enic->napi[wq];
717258ba 1463 }
01f2e4ea 1464
717258ba 1465 intr = enic_msix_err_intr(enic);
4505f40a
DC		 1466 snprintf(enic->msix[intr].devname,
1467 sizeof(enic->msix[intr].devname),
01f2e4ea 1468 "%.11s-err", netdev->name);
717258ba
VK		 1469 enic->msix[intr].isr = enic_isr_msix_err;
1470 enic->msix[intr].devid = enic;
01f2e4ea 1471
717258ba 1472 intr = enic_msix_notify_intr(enic);
4505f40a
DC		 1473 snprintf(enic->msix[intr].devname,
1474 sizeof(enic->msix[intr].devname),
01f2e4ea 1475 "%.11s-notify", netdev->name);
717258ba
VK		 1476 enic->msix[intr].isr = enic_isr_msix_notify;
1477 enic->msix[intr].devid = enic;
1478
1479 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1480 enic->msix[i].requested = 0;
01f2e4ea 1481
717258ba 1482 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF		 1483 err = request_irq(enic->msix_entry[i].vector,
1484 enic->msix[i].isr, 0,
1485 enic->msix[i].devname,
1486 enic->msix[i].devid);
1487 if (err) {
1488 enic_free_intr(enic);
1489 break;
1490 }
1491 enic->msix[i].requested = 1;
1492 }
1493
1494 break;
1495
1496 default:
1497 break;
1498 }
1499
1500 return err;
1501}
1502
b3d18d19
SF		 1503static void enic_synchronize_irqs(struct enic *enic)
1504{
1505 unsigned int i;
1506
1507 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1508 case VNIC_DEV_INTR_MODE_INTX:
1509 case VNIC_DEV_INTR_MODE_MSI:
1510 synchronize_irq(enic->pdev->irq);
1511 break;
1512 case VNIC_DEV_INTR_MODE_MSIX:
1513 for (i = 0; i < enic->intr_count; i++)
1514 synchronize_irq(enic->msix_entry[i].vector);
1515 break;
1516 default:
1517 break;
1518 }
1519}
1520
7c2ce6e6
SS		 1521static void enic_set_rx_coal_setting(struct enic *enic)
1522{
1523 unsigned int speed;
1524 int index = -1;
1525 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1526
1527 /* If intr mode is not MSIX, do not do adaptive coalescing */
1528 if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) {
1529 netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing");
1530 return;
1531 }
1532
1533 /* 1. Read the link speed from fw
1534 * 2. Pick the default range for the speed
1535 * 3. Update it in enic->rx_coalesce_setting
1536 */
1537 speed = vnic_dev_port_speed(enic->vdev);
1538 if (ENIC_LINK_SPEED_10G < speed)
1539 index = ENIC_LINK_40G_INDEX;
1540 else if (ENIC_LINK_SPEED_4G < speed)
1541 index = ENIC_LINK_10G_INDEX;
1542 else
1543 index = ENIC_LINK_4G_INDEX;
1544
1545 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
1546 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
1547 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
1548
1549 /* Start with the value provided by UCSM */
1550 for (index = 0; index < enic->rq_count; index++)
1551 enic->cq[index].cur_rx_coal_timeval =
1552 enic->config.intr_timer_usec;
1553
1554 rx_coal->use_adaptive_rx_coalesce = 1;
1555}
1556
383ab92f 1557static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF		 1558{
1559 int err;
1560
8e091340 1561 spin_lock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1562 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1563 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK		 1564 err = vnic_dev_notify_set(enic->vdev,
1565 enic_legacy_notify_intr());
01f2e4ea
SF		 1566 break;
1567 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1568 err = vnic_dev_notify_set(enic->vdev,
1569 enic_msix_notify_intr(enic));
01f2e4ea
SF		 1570 break;
1571 default:
1572 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1573 break;
1574 }
8e091340 1575 spin_unlock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1576
1577 return err;
1578}
1579
1580static void enic_notify_timer_start(struct enic *enic)
1581{
1582 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1583 case VNIC_DEV_INTR_MODE_MSI:
1584 mod_timer(&enic->notify_timer, jiffies);
1585 break;
1586 default:
1587 /* Using intr for notification for INTx/MSI-X */
1588 break;
6403eab1 1589 }
01f2e4ea
SF		 1590}
1591
1592/* rtnl lock is held, process context */
1593static int enic_open(struct net_device *netdev)
1594{
1595 struct enic *enic = netdev_priv(netdev);
1596 unsigned int i;
1597 int err;
1598
4b75a442
SF		 1599 err = enic_request_intr(enic);
1600 if (err) {
a7a79deb 1601 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF		 1602 return err;
1603 }
1604
383ab92f 1605 err = enic_dev_notify_set(enic);
4b75a442 1606 if (err) {
a7a79deb
VK		 1607 netdev_err(netdev,
1608 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF		 1609 goto err_out_free_intr;
1610 }
1611
01f2e4ea 1612 for (i = 0; i < enic->rq_count; i++) {
0eb26022 1613 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF		 1614 /* Need at least one buffer on ring to get going */
1615 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1616 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1617 err = -ENOMEM;
4b75a442 1618 goto err_out_notify_unset;
01f2e4ea
SF		 1619 }
1620 }
1621
1622 for (i = 0; i < enic->wq_count; i++)
1623 vnic_wq_enable(&enic->wq[i]);
1624 for (i = 0; i < enic->rq_count; i++)
1625 vnic_rq_enable(&enic->rq[i]);
1626
7335903c 1627 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1628 enic_dev_add_station_addr(enic);
3f192795 1629
319d7e84 1630 enic_set_rx_mode(netdev);
01f2e4ea 1631
822473b6 1632 netif_tx_wake_all_queues(netdev);
717258ba 1633
14747cd9
GV		 1634 for (i = 0; i < enic->rq_count; i++) {
1635 enic_busy_poll_init_lock(&enic->rq[i]);
717258ba 1636 napi_enable(&enic->napi[i]);
14747cd9 1637 }
4cfe8785
GV		 1638 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1639 for (i = 0; i < enic->wq_count; i++)
1640 napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
383ab92f 1641 enic_dev_enable(enic);
01f2e4ea
SF		 1642
1643 for (i = 0; i < enic->intr_count; i++)
1644 vnic_intr_unmask(&enic->intr[i]);
1645
1646 enic_notify_timer_start(enic);
a145df23 1647 enic_rfs_flw_tbl_init(enic);
01f2e4ea
SF		 1648
1649 return 0;
4b75a442
SF		 1650
1651err_out_notify_unset:
383ab92f 1652 enic_dev_notify_unset(enic);
4b75a442
SF		 1653err_out_free_intr:
1654 enic_free_intr(enic);
1655
1656 return err;
01f2e4ea
SF		 1657}
1658
1659/* rtnl lock is held, process context */
1660static int enic_stop(struct net_device *netdev)
1661{
1662 struct enic *enic = netdev_priv(netdev);
1663 unsigned int i;
1664 int err;
1665
29046f9b 1666 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 1667 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK		 1668 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
1669 }
b3d18d19
SF		 1670
1671 enic_synchronize_irqs(enic);
1672
01f2e4ea 1673 del_timer_sync(&enic->notify_timer);
a145df23 1674 enic_rfs_flw_tbl_free(enic);
01f2e4ea 1675
383ab92f 1676 enic_dev_disable(enic);
717258ba 1677
14747cd9 1678 for (i = 0; i < enic->rq_count; i++) {
717258ba 1679 napi_disable(&enic->napi[i]);
39dc90c1 1680 local_bh_disable();
14747cd9
GV		 1681 while (!enic_poll_lock_napi(&enic->rq[i]))
1682 mdelay(1);
39dc90c1 1683 local_bh_enable();
14747cd9 1684 }
717258ba 1685
b3d18d19
SF		 1686 netif_carrier_off(netdev);
1687 netif_tx_disable(netdev);
4cfe8785
GV		 1688 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1689 for (i = 0; i < enic->wq_count; i++)
1690 napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
3f192795 1691
7335903c 1692 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1693 enic_dev_del_station_addr(enic);
f8bd9091 1694
01f2e4ea
SF		 1695 for (i = 0; i < enic->wq_count; i++) {
1696 err = vnic_wq_disable(&enic->wq[i]);
1697 if (err)
1698 return err;
1699 }
1700 for (i = 0; i < enic->rq_count; i++) {
1701 err = vnic_rq_disable(&enic->rq[i]);
1702 if (err)
1703 return err;
1704 }
1705
383ab92f 1706 enic_dev_notify_unset(enic);
4b75a442
SF		 1707 enic_free_intr(enic);
1708
01f2e4ea
SF		 1709 for (i = 0; i < enic->wq_count; i++)
1710 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
1711 for (i = 0; i < enic->rq_count; i++)
1712 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
1713 for (i = 0; i < enic->cq_count; i++)
1714 vnic_cq_clean(&enic->cq[i]);
1715 for (i = 0; i < enic->intr_count; i++)
1716 vnic_intr_clean(&enic->intr[i]);
1717
1718 return 0;
1719}
1720
1721static int enic_change_mtu(struct net_device *netdev, int new_mtu)
1722{
1723 struct enic *enic = netdev_priv(netdev);
1724 int running = netif_running(netdev);
1725
25f0a061
SF		 1726 if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU)
1727 return -EINVAL;
1728
7335903c 1729 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP		 1730 return -EOPNOTSUPP;
1731
01f2e4ea
SF		 1732 if (running)
1733 enic_stop(netdev);
1734
01f2e4ea
SF		 1735 netdev->mtu = new_mtu;
1736
1737 if (netdev->mtu > enic->port_mtu)
a7a79deb
VK		 1738 netdev_warn(netdev,
1739 "interface MTU (%d) set higher than port MTU (%d)\n",
1740 netdev->mtu, enic->port_mtu);
01f2e4ea
SF		 1741
1742 if (running)
1743 enic_open(netdev);
1744
1745 return 0;
1746}
1747
c97c894d
RP		 1748static void enic_change_mtu_work(struct work_struct *work)
1749{
1750 struct enic *enic = container_of(work, struct enic, change_mtu_work);
1751 struct net_device *netdev = enic->netdev;
1752 int new_mtu = vnic_dev_mtu(enic->vdev);
1753 int err;
1754 unsigned int i;
1755
1756 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
1757
1758 rtnl_lock();
1759
1760 /* Stop RQ */
1761 del_timer_sync(&enic->notify_timer);
1762
1763 for (i = 0; i < enic->rq_count; i++)
1764 napi_disable(&enic->napi[i]);
1765
1766 vnic_intr_mask(&enic->intr[0]);
1767 enic_synchronize_irqs(enic);
1768 err = vnic_rq_disable(&enic->rq[0]);
1769 if (err) {
e057590b 1770 rtnl_unlock();
c97c894d
RP		 1771 netdev_err(netdev, "Unable to disable RQ.\n");
1772 return;
1773 }
1774 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
1775 vnic_cq_clean(&enic->cq[0]);
1776 vnic_intr_clean(&enic->intr[0]);
1777
1778 /* Fill RQ with new_mtu-sized buffers */
1779 netdev->mtu = new_mtu;
1780 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
1781 /* Need at least one buffer on ring to get going */
1782 if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
e057590b 1783 rtnl_unlock();
c97c894d
RP		 1784 netdev_err(netdev, "Unable to alloc receive buffers.\n");
1785 return;
1786 }
1787
1788 /* Start RQ */
1789 vnic_rq_enable(&enic->rq[0]);
1790 napi_enable(&enic->napi[0]);
1791 vnic_intr_unmask(&enic->intr[0]);
1792 enic_notify_timer_start(enic);
1793
1794 rtnl_unlock();
1795
1796 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
1797}
1798
01f2e4ea
SF		 1799#ifdef CONFIG_NET_POLL_CONTROLLER
1800static void enic_poll_controller(struct net_device *netdev)
1801{
1802 struct enic *enic = netdev_priv(netdev);
1803 struct vnic_dev *vdev = enic->vdev;
717258ba 1804 unsigned int i, intr;
01f2e4ea
SF		 1805
1806 switch (vnic_dev_get_intr_mode(vdev)) {
1807 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1808 for (i = 0; i < enic->rq_count; i++) {
1809 intr = enic_msix_rq_intr(enic, i);
4cfe8785
GV		 1810 enic_isr_msix(enic->msix_entry[intr].vector,
1811 &enic->napi[i]);
717258ba 1812 }
b880a954
VK		 1813
1814 for (i = 0; i < enic->wq_count; i++) {
1815 intr = enic_msix_wq_intr(enic, i);
4cfe8785
GV		 1816 enic_isr_msix(enic->msix_entry[intr].vector,
1817 &enic->napi[enic_cq_wq(enic, i)]);
b880a954
VK		 1818 }
1819
01f2e4ea
SF		 1820 break;
1821 case VNIC_DEV_INTR_MODE_MSI:
1822 enic_isr_msi(enic->pdev->irq, enic);
1823 break;
1824 case VNIC_DEV_INTR_MODE_INTX:
1825 enic_isr_legacy(enic->pdev->irq, netdev);
1826 break;
1827 default:
1828 break;
1829 }
1830}
1831#endif
1832
1833static int enic_dev_wait(struct vnic_dev *vdev,
1834 int (*start)(struct vnic_dev *, int),
1835 int (*finished)(struct vnic_dev *, int *),
1836 int arg)
1837{
1838 unsigned long time;
1839 int done;
1840 int err;
1841
1842 BUG_ON(in_interrupt());
1843
1844 err = start(vdev, arg);
1845 if (err)
1846 return err;
1847
1848 /* Wait for func to complete...2 seconds max
1849 */
1850
1851 time = jiffies + (HZ * 2);
1852 do {
1853
1854 err = finished(vdev, &done);
1855 if (err)
1856 return err;
1857
1858 if (done)
1859 return 0;
1860
1861 schedule_timeout_uninterruptible(HZ / 10);
1862
1863 } while (time_after(time, jiffies));
1864
1865 return -ETIMEDOUT;
1866}
1867
1868static int enic_dev_open(struct enic *enic)
1869{
1870 int err;
1871
1872 err = enic_dev_wait(enic->vdev, vnic_dev_open,
1873 vnic_dev_open_done, 0);
1874 if (err)
a7a79deb
VK		 1875 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
1876 err);
01f2e4ea
SF		 1877
1878 return err;
1879}
1880
99ef5639 1881static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF		 1882{
1883 int err;
1884
99ef5639
VK		 1885 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
1886 vnic_dev_hang_reset_done, 0);
01f2e4ea 1887 if (err)
a7a79deb
VK		 1888 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
1889 err);
01f2e4ea
SF		 1890
1891 return err;
1892}
1893
717258ba
VK		 1894static int enic_set_rsskey(struct enic *enic)
1895{
1f4f067f 1896 dma_addr_t rss_key_buf_pa;
717258ba
VK		 1897 union vnic_rss_key *rss_key_buf_va = NULL;
1898 union vnic_rss_key rss_key = {
1899 .key[0].b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101},
1900 .key[1].b = {80, 65, 76, 79, 117, 110, 105, 113, 117, 101},
1901 .key[2].b = {76, 73, 78, 85, 88, 114, 111, 99, 107, 115},
1902 .key[3].b = {69, 78, 73, 67, 105, 115, 99, 111, 111, 108},
1903 };
1904 int err;
1905
1906 rss_key_buf_va = pci_alloc_consistent(enic->pdev,
1907 sizeof(union vnic_rss_key), &rss_key_buf_pa);
1908 if (!rss_key_buf_va)
1909 return -ENOMEM;
1910
1911 memcpy(rss_key_buf_va, &rss_key, sizeof(union vnic_rss_key));
1912
8e091340 1913 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1914 err = enic_set_rss_key(enic,
1915 rss_key_buf_pa,
1916 sizeof(union vnic_rss_key));
8e091340 1917 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1918
1919 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
1920 rss_key_buf_va, rss_key_buf_pa);
1921
1922 return err;
1923}
1924
1925static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
1926{
1f4f067f 1927 dma_addr_t rss_cpu_buf_pa;
717258ba
VK		 1928 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
1929 unsigned int i;
1930 int err;
1931
1932 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
1933 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
1934 if (!rss_cpu_buf_va)
1935 return -ENOMEM;
1936
1937 for (i = 0; i < (1 << rss_hash_bits); i++)
1938 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
1939
8e091340 1940 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1941 err = enic_set_rss_cpu(enic,
1942 rss_cpu_buf_pa,
1943 sizeof(union vnic_rss_cpu));
8e091340 1944 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1945
1946 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
1947 rss_cpu_buf_va, rss_cpu_buf_pa);
1948
1949 return err;
1950}
1951
1952static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
1953 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 1954{
68f71708
SF		 1955 const u8 tso_ipid_split_en = 0;
1956 const u8 ig_vlan_strip_en = 1;
383ab92f 1957 int err;
68f71708 1958
717258ba
VK		 1959 /* Enable VLAN tag stripping.
1960 */
68f71708 1961
8e091340 1962 spin_lock_bh(&enic->devcmd_lock);
383ab92f 1963 err = enic_set_nic_cfg(enic,
68f71708
SF		 1964 rss_default_cpu, rss_hash_type,
1965 rss_hash_bits, rss_base_cpu,
1966 rss_enable, tso_ipid_split_en,
1967 ig_vlan_strip_en);
8e091340 1968 spin_unlock_bh(&enic->devcmd_lock);
383ab92f
VK		 1969
1970 return err;
1971}
1972
717258ba
VK		 1973static int enic_set_rss_nic_cfg(struct enic *enic)
1974{
1975 struct device *dev = enic_get_dev(enic);
1976 const u8 rss_default_cpu = 0;
1977 const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
1978 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
1979 NIC_CFG_RSS_HASH_TYPE_IPV6 |
1980 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
1981 const u8 rss_hash_bits = 7;
1982 const u8 rss_base_cpu = 0;
1983 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
1984
1985 if (rss_enable) {
1986 if (!enic_set_rsskey(enic)) {
1987 if (enic_set_rsscpu(enic, rss_hash_bits)) {
1988 rss_enable = 0;
1989 dev_warn(dev, "RSS disabled, "
1990 "Failed to set RSS cpu indirection table.");
1991 }
1992 } else {
1993 rss_enable = 0;
1994 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
1995 }
1996 }
1997
1998 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
1999 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK		 2000}
2001
01f2e4ea
SF		 2002static void enic_reset(struct work_struct *work)
2003{
2004 struct enic *enic = container_of(work, struct enic, reset);
2005
2006 if (!netif_running(enic->netdev))
2007 return;
2008
2009 rtnl_lock();
2010
0b038566 2011 spin_lock(&enic->enic_api_lock);
383ab92f 2012 enic_dev_hang_notify(enic);
01f2e4ea 2013 enic_stop(enic->netdev);
99ef5639 2014 enic_dev_hang_reset(enic);
e0afe53f 2015 enic_reset_addr_lists(enic);
01f2e4ea 2016 enic_init_vnic_resources(enic);
717258ba 2017 enic_set_rss_nic_cfg(enic);
f8cac14a 2018 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 2019 enic_open(enic->netdev);
0b038566 2020 spin_unlock(&enic->enic_api_lock);
d765bb41 2021 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF		 2022
2023 rtnl_unlock();
2024}
2025
2026static int enic_set_intr_mode(struct enic *enic)
2027{
717258ba 2028 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 2029 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF		 2030 unsigned int i;
2031
2032 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 2033 * on system capabilities.
01f2e4ea
SF		 2034 *
2035 * Try MSI-X first
2036 *
2037 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
2038 * (the second to last INTR is used for WQ/RQ errors)
2039 * (the last INTR is used for notifications)
2040 */
2041
2042 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
2043 for (i = 0; i < n + m + 2; i++)
2044 enic->msix_entry[i].entry = i;
2045
717258ba
VK		 2046 /* Use multiple RQs if RSS is enabled
2047 */
2048
2049 if (ENIC_SETTING(enic, RSS) &&
2050 enic->config.intr_mode < 1 &&
01f2e4ea
SF		 2051 enic->rq_count >= n &&
2052 enic->wq_count >= m &&
2053 enic->cq_count >= n + m &&
717258ba 2054 enic->intr_count >= n + m + 2) {
01f2e4ea 2055
abbb6a37
AG		 2056 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2057 n + m + 2, n + m + 2) > 0) {
01f2e4ea 2058
717258ba
VK		 2059 enic->rq_count = n;
2060 enic->wq_count = m;
2061 enic->cq_count = n + m;
2062 enic->intr_count = n + m + 2;
01f2e4ea 2063
717258ba
VK		 2064 vnic_dev_set_intr_mode(enic->vdev,
2065 VNIC_DEV_INTR_MODE_MSIX);
2066
2067 return 0;
2068 }
2069 }
2070
2071 if (enic->config.intr_mode < 1 &&
2072 enic->rq_count >= 1 &&
2073 enic->wq_count >= m &&
2074 enic->cq_count >= 1 + m &&
2075 enic->intr_count >= 1 + m + 2) {
abbb6a37
AG		 2076 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2077 1 + m + 2, 1 + m + 2) > 0) {
717258ba
VK		 2078
2079 enic->rq_count = 1;
2080 enic->wq_count = m;
2081 enic->cq_count = 1 + m;
2082 enic->intr_count = 1 + m + 2;
2083
2084 vnic_dev_set_intr_mode(enic->vdev,
2085 VNIC_DEV_INTR_MODE_MSIX);
2086
2087 return 0;
2088 }
01f2e4ea
SF		 2089 }
2090
2091 /* Next try MSI
2092 *
2093 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
2094 */
2095
2096 if (enic->config.intr_mode < 2 &&
2097 enic->rq_count >= 1 &&
2098 enic->wq_count >= 1 &&
2099 enic->cq_count >= 2 &&
2100 enic->intr_count >= 1 &&
2101 !pci_enable_msi(enic->pdev)) {
2102
2103 enic->rq_count = 1;
2104 enic->wq_count = 1;
2105 enic->cq_count = 2;
2106 enic->intr_count = 1;
2107
2108 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
2109
2110 return 0;
2111 }
2112
2113 /* Next try INTx
2114 *
2115 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
2116 * (the first INTR is used for WQ/RQ)
2117 * (the second INTR is used for WQ/RQ errors)
2118 * (the last INTR is used for notifications)
2119 */
2120
2121 if (enic->config.intr_mode < 3 &&
2122 enic->rq_count >= 1 &&
2123 enic->wq_count >= 1 &&
2124 enic->cq_count >= 2 &&
2125 enic->intr_count >= 3) {
2126
2127 enic->rq_count = 1;
2128 enic->wq_count = 1;
2129 enic->cq_count = 2;
2130 enic->intr_count = 3;
2131
2132 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
2133
2134 return 0;
2135 }
2136
2137 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2138
2139 return -EINVAL;
2140}
2141
2142static void enic_clear_intr_mode(struct enic *enic)
2143{
2144 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2145 case VNIC_DEV_INTR_MODE_MSIX:
2146 pci_disable_msix(enic->pdev);
2147 break;
2148 case VNIC_DEV_INTR_MODE_MSI:
2149 pci_disable_msi(enic->pdev);
2150 break;
2151 default:
2152 break;
2153 }
2154
2155 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2156}
2157
f8bd9091
SF		 2158static const struct net_device_ops enic_netdev_dynamic_ops = {
2159 .ndo_open = enic_open,
2160 .ndo_stop = enic_stop,
2161 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2162 .ndo_get_stats64 = enic_get_stats,
f8bd9091 2163 .ndo_validate_addr = eth_validate_addr,
319d7e84 2164 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF		 2165 .ndo_set_mac_address = enic_set_mac_address_dynamic,
2166 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF		 2167 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2168 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2169 .ndo_tx_timeout = enic_tx_timeout,
2170 .ndo_set_vf_port = enic_set_vf_port,
2171 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 2172 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF		 2173#ifdef CONFIG_NET_POLL_CONTROLLER
2174 .ndo_poll_controller = enic_poll_controller,
2175#endif
a145df23
GV		 2176#ifdef CONFIG_RFS_ACCEL
2177 .ndo_rx_flow_steer = enic_rx_flow_steer,
2178#endif
14747cd9
GV		 2179#ifdef CONFIG_NET_RX_BUSY_POLL
2180 .ndo_busy_poll = enic_busy_poll,
2181#endif
f8bd9091
SF		 2182};
2183
afe29f7a
SH		 2184static const struct net_device_ops enic_netdev_ops = {
2185 .ndo_open = enic_open,
2186 .ndo_stop = enic_stop,
00829823 2187 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2188 .ndo_get_stats64 = enic_get_stats,
afe29f7a 2189 .ndo_validate_addr = eth_validate_addr,
f8bd9091 2190 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 2191 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 2192 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH		 2193 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2194 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2195 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP		 2196 .ndo_set_vf_port = enic_set_vf_port,
2197 .ndo_get_vf_port = enic_get_vf_port,
2198 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH		 2199#ifdef CONFIG_NET_POLL_CONTROLLER
2200 .ndo_poll_controller = enic_poll_controller,
2201#endif
a145df23
GV		 2202#ifdef CONFIG_RFS_ACCEL
2203 .ndo_rx_flow_steer = enic_rx_flow_steer,
2204#endif
14747cd9
GV		 2205#ifdef CONFIG_NET_RX_BUSY_POLL
2206 .ndo_busy_poll = enic_busy_poll,
2207#endif
afe29f7a
SH		 2208};
2209
2fdba388 2210static void enic_dev_deinit(struct enic *enic)
6fdfa970 2211{
717258ba
VK		 2212 unsigned int i;
2213
14747cd9
GV		 2214 for (i = 0; i < enic->rq_count; i++) {
2215 napi_hash_del(&enic->napi[i]);
717258ba 2216 netif_napi_del(&enic->napi[i]);
14747cd9 2217 }
4cfe8785
GV		 2218 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2219 for (i = 0; i < enic->wq_count; i++)
2220 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
717258ba 2221
6fdfa970
SF		 2222 enic_free_vnic_resources(enic);
2223 enic_clear_intr_mode(enic);
2224}
2225
2fdba388 2226static int enic_dev_init(struct enic *enic)
6fdfa970 2227{
a7a79deb 2228 struct device *dev = enic_get_dev(enic);
6fdfa970 2229 struct net_device *netdev = enic->netdev;
717258ba 2230 unsigned int i;
6fdfa970
SF		 2231 int err;
2232
ea7ea65a
VK		 2233 /* Get interrupt coalesce timer info */
2234 err = enic_dev_intr_coal_timer_info(enic);
2235 if (err) {
2236 dev_warn(dev, "Using default conversion factor for "
2237 "interrupt coalesce timer\n");
2238 vnic_dev_intr_coal_timer_info_default(enic->vdev);
2239 }
2240
6fdfa970
SF		 2241 /* Get vNIC configuration
2242 */
2243
2244 err = enic_get_vnic_config(enic);
2245 if (err) {
a7a79deb 2246 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF		 2247 return err;
2248 }
2249
2250 /* Get available resource counts
2251 */
2252
2253 enic_get_res_counts(enic);
2254
2255 /* Set interrupt mode based on resource counts and system
2256 * capabilities
2257 */
2258
2259 err = enic_set_intr_mode(enic);
2260 if (err) {
a7a79deb
VK		 2261 dev_err(dev, "Failed to set intr mode based on resource "
2262 "counts and system capabilities, aborting\n");
6fdfa970
SF		 2263 return err;
2264 }
2265
2266 /* Allocate and configure vNIC resources
2267 */
2268
2269 err = enic_alloc_vnic_resources(enic);
2270 if (err) {
a7a79deb 2271 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF		 2272 goto err_out_free_vnic_resources;
2273 }
2274
2275 enic_init_vnic_resources(enic);
2276
717258ba 2277 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2278 if (err) {
a7a79deb 2279 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF		 2280 goto err_out_free_vnic_resources;
2281 }
2282
2283 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2284 default:
717258ba 2285 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
14747cd9 2286 napi_hash_add(&enic->napi[0]);
6fdfa970
SF		 2287 break;
2288 case VNIC_DEV_INTR_MODE_MSIX:
14747cd9 2289 for (i = 0; i < enic->rq_count; i++) {
717258ba 2290 netif_napi_add(netdev, &enic->napi[i],
4cfe8785 2291 enic_poll_msix_rq, NAPI_POLL_WEIGHT);
14747cd9
GV		 2292 napi_hash_add(&enic->napi[i]);
2293 }
4cfe8785
GV		 2294 for (i = 0; i < enic->wq_count; i++)
2295 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
2296 enic_poll_msix_wq, NAPI_POLL_WEIGHT);
6fdfa970
SF		 2297 break;
2298 }
2299
2300 return 0;
2301
2302err_out_free_vnic_resources:
2303 enic_clear_intr_mode(enic);
2304 enic_free_vnic_resources(enic);
2305
2306 return err;
2307}
2308
27e6c7d3
SF		 2309static void enic_iounmap(struct enic *enic)
2310{
2311 unsigned int i;
2312
2313 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2314 if (enic->bar[i].vaddr)
2315 iounmap(enic->bar[i].vaddr);
2316}
2317
1dd06ae8 2318static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2319{
a7a79deb 2320 struct device *dev = &pdev->dev;
01f2e4ea
SF		 2321 struct net_device *netdev;
2322 struct enic *enic;
2323 int using_dac = 0;
2324 unsigned int i;
2325 int err;
8749b427
RP		 2326#ifdef CONFIG_PCI_IOV
2327 int pos = 0;
2328#endif
b67f231d 2329 int num_pps = 1;
01f2e4ea 2330
01f2e4ea
SF		 2331 /* Allocate net device structure and initialize. Private
2332 * instance data is initialized to zero.
2333 */
2334
822473b6 2335 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2336 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2337 if (!netdev)
01f2e4ea 2338 return -ENOMEM;
01f2e4ea 2339
01f2e4ea
SF		 2340 pci_set_drvdata(pdev, netdev);
2341
2342 SET_NETDEV_DEV(netdev, &pdev->dev);
2343
2344 enic = netdev_priv(netdev);
2345 enic->netdev = netdev;
2346 enic->pdev = pdev;
2347
2348 /* Setup PCI resources
2349 */
2350
29046f9b 2351 err = pci_enable_device_mem(pdev);
01f2e4ea 2352 if (err) {
a7a79deb 2353 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF		 2354 goto err_out_free_netdev;
2355 }
2356
2357 err = pci_request_regions(pdev, DRV_NAME);
2358 if (err) {
a7a79deb 2359 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF		 2360 goto err_out_disable_device;
2361 }
2362
2363 pci_set_master(pdev);
2364
2365 /* Query PCI controller on system for DMA addressing
624dbf55 2366 * limitation for the device. Try 64-bit first, and
01f2e4ea
SF		 2367 * fail to 32-bit.
2368 */
2369
624dbf55 2370 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2371 if (err) {
284901a9 2372 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2373 if (err) {
a7a79deb 2374 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF		 2375 goto err_out_release_regions;
2376 }
284901a9 2377 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2378 if (err) {
a7a79deb
VK		 2379 dev_err(dev, "Unable to obtain %u-bit DMA "
2380 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF		 2381 goto err_out_release_regions;
2382 }
2383 } else {
624dbf55 2384 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2385 if (err) {
a7a79deb 2386 dev_err(dev, "Unable to obtain %u-bit DMA "
624dbf55 2387 "for consistent allocations, aborting\n", 64);
01f2e4ea
SF		 2388 goto err_out_release_regions;
2389 }
2390 using_dac = 1;
2391 }
2392
27e6c7d3 2393 /* Map vNIC resources from BAR0-5
01f2e4ea
SF		 2394 */
2395
27e6c7d3
SF		 2396 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2397 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2398 continue;
2399 enic->bar[i].len = pci_resource_len(pdev, i);
2400 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2401 if (!enic->bar[i].vaddr) {
a7a79deb 2402 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF		 2403 err = -ENODEV;
2404 goto err_out_iounmap;
2405 }
2406 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF		 2407 }
2408
2409 /* Register vNIC device
2410 */
2411
27e6c7d3
SF		 2412 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2413 ARRAY_SIZE(enic->bar));
01f2e4ea 2414 if (!enic->vdev) {
a7a79deb 2415 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF		 2416 err = -ENODEV;
2417 goto err_out_iounmap;
2418 }
2419
8749b427
RP		 2420#ifdef CONFIG_PCI_IOV
2421 /* Get number of subvnics */
2422 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2423 if (pos) {
2424 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2425 &enic->num_vfs);
8749b427
RP		 2426 if (enic->num_vfs) {
2427 err = pci_enable_sriov(pdev, enic->num_vfs);
2428 if (err) {
2429 dev_err(dev, "SRIOV enable failed, aborting."
2430 " pci_enable_sriov() returned %d\n",
2431 err);
2432 goto err_out_vnic_unregister;
2433 }
2434 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2435 num_pps = enic->num_vfs;
8749b427
RP		 2436 }
2437 }
8749b427 2438#endif
ca2b721d 2439
3f192795 2440 /* Allocate structure for port profiles */
a1de2219 2441 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2442 if (!enic->pp) {
3f192795 2443 err = -ENOMEM;
ca2b721d 2444 goto err_out_disable_sriov_pp;
3f192795
RP		 2445 }
2446
01f2e4ea
SF		 2447 /* Issue device open to get device in known state
2448 */
2449
2450 err = enic_dev_open(enic);
2451 if (err) {
a7a79deb 2452 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2453 goto err_out_disable_sriov;
01f2e4ea
SF		 2454 }
2455
69161425
VK		 2456 /* Setup devcmd lock
2457 */
2458
2459 spin_lock_init(&enic->devcmd_lock);
0b038566 2460 spin_lock_init(&enic->enic_api_lock);
69161425
VK		 2461
2462 /*
2463 * Set ingress vlan rewrite mode before vnic initialization
2464 */
2465
2466 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2467 if (err) {
2468 dev_err(dev,
2469 "Failed to set ingress vlan rewrite mode, aborting.\n");
2470 goto err_out_dev_close;
2471 }
2472
01f2e4ea
SF		 2473 /* Issue device init to initialize the vnic-to-switch link.
2474 * We'll start with carrier off and wait for link UP
2475 * notification later to turn on carrier. We don't need
2476 * to wait here for the vnic-to-switch link initialization
2477 * to complete; link UP notification is the indication that
2478 * the process is complete.
2479 */
2480
2481 netif_carrier_off(netdev);
2482
a7a79deb
VK		 2483 /* Do not call dev_init for a dynamic vnic.
2484 * For a dynamic vnic, init_prov_info will be
2485 * called later by an upper layer.
2486 */
2487
2b68c181 2488 if (!enic_is_dynamic(enic)) {
f8bd9091
SF		 2489 err = vnic_dev_init(enic->vdev, 0);
2490 if (err) {
a7a79deb 2491 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF		 2492 goto err_out_dev_close;
2493 }
01f2e4ea
SF		 2494 }
2495
6fdfa970 2496 err = enic_dev_init(enic);
01f2e4ea 2497 if (err) {
a7a79deb 2498 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF		 2499 goto err_out_dev_close;
2500 }
2501
822473b6 2502 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2503 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2504
383ab92f 2505 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF		 2506 */
2507
2508 init_timer(&enic->notify_timer);
2509 enic->notify_timer.function = enic_notify_timer;
2510 enic->notify_timer.data = (unsigned long)enic;
2511
7c2ce6e6 2512 enic_set_rx_coal_setting(enic);
01f2e4ea 2513 INIT_WORK(&enic->reset, enic_reset);
c97c894d 2514 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF		 2515
2516 for (i = 0; i < enic->wq_count; i++)
2517 spin_lock_init(&enic->wq_lock[i]);
2518
01f2e4ea
SF		 2519 /* Register net device
2520 */
2521
2522 enic->port_mtu = enic->config.mtu;
2523 (void)enic_change_mtu(netdev, enic->port_mtu);
2524
2525 err = enic_set_mac_addr(netdev, enic->mac_addr);
2526 if (err) {
a7a79deb 2527 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2528 goto err_out_dev_deinit;
01f2e4ea
SF		 2529 }
2530
7c844599 2531 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
7c2ce6e6
SS		 2532 /* rx coalesce time already got initialized. This gets used
2533 * if adaptive coal is turned off
2534 */
7c844599
SF		 2535 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2536
7335903c 2537 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF		 2538 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2539 else
2540 netdev->netdev_ops = &enic_netdev_ops;
2541
01f2e4ea 2542 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2543 enic_set_ethtool_ops(netdev);
01f2e4ea 2544
f646968f 2545 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2546 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2547 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK		 2548 enic->loop_enable = 1;
2549 enic->loop_tag = enic->config.loop_tag;
2550 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2551 }
01f2e4ea 2552 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2553 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2554 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2555 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2556 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2557 if (ENIC_SETTING(enic, RSS))
2558 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM		 2559 if (ENIC_SETTING(enic, RXCSUM))
2560 netdev->hw_features |= NETIF_F_RXCSUM;
2561
2562 netdev->features |= netdev->hw_features;
2563
a145df23
GV		 2564#ifdef CONFIG_RFS_ACCEL
2565 netdev->hw_features |= NETIF_F_NTUPLE;
2566#endif
2567
01f2e4ea
SF		 2568 if (using_dac)
2569 netdev->features |= NETIF_F_HIGHDMA;
2570
01789349
JP		 2571 netdev->priv_flags |= IFF_UNICAST_FLT;
2572
01f2e4ea
SF		 2573 err = register_netdev(netdev);
2574 if (err) {
a7a79deb 2575 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 2576 goto err_out_dev_deinit;
01f2e4ea 2577 }
a03bb56e 2578 enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
01f2e4ea
SF		 2579
2580 return 0;
2581
6fdfa970
SF		 2582err_out_dev_deinit:
2583 enic_dev_deinit(enic);
01f2e4ea
SF		 2584err_out_dev_close:
2585 vnic_dev_close(enic->vdev);
8749b427 2586err_out_disable_sriov:
ca2b721d
RP		 2587 kfree(enic->pp);
2588err_out_disable_sriov_pp:
8749b427
RP		 2589#ifdef CONFIG_PCI_IOV
2590 if (enic_sriov_enabled(enic)) {
2591 pci_disable_sriov(pdev);
2592 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2593 }
01f2e4ea 2594err_out_vnic_unregister:
8749b427 2595#endif
35d87e33 2596 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF		 2597err_out_iounmap:
2598 enic_iounmap(enic);
2599err_out_release_regions:
2600 pci_release_regions(pdev);
2601err_out_disable_device:
2602 pci_disable_device(pdev);
2603err_out_free_netdev:
01f2e4ea
SF		 2604 free_netdev(netdev);
2605
2606 return err;
2607}
2608
854de92f 2609static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF		 2610{
2611 struct net_device *netdev = pci_get_drvdata(pdev);
2612
2613 if (netdev) {
2614 struct enic *enic = netdev_priv(netdev);
2615
23f333a2 2616 cancel_work_sync(&enic->reset);
c97c894d 2617 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 2618 unregister_netdev(netdev);
6fdfa970 2619 enic_dev_deinit(enic);
01f2e4ea 2620 vnic_dev_close(enic->vdev);
8749b427
RP		 2621#ifdef CONFIG_PCI_IOV
2622 if (enic_sriov_enabled(enic)) {
2623 pci_disable_sriov(pdev);
2624 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2625 }
2626#endif
3f192795 2627 kfree(enic->pp);
01f2e4ea
SF		 2628 vnic_dev_unregister(enic->vdev);
2629 enic_iounmap(enic);
2630 pci_release_regions(pdev);
2631 pci_disable_device(pdev);
01f2e4ea
SF		 2632 free_netdev(netdev);
2633 }
2634}
2635
2636static struct pci_driver enic_driver = {
2637 .name = DRV_NAME,
2638 .id_table = enic_id_table,
2639 .probe = enic_probe,
854de92f 2640 .remove = enic_remove,
01f2e4ea
SF		 2641};
2642
2643static int __init enic_init_module(void)
2644{
a7a79deb 2645 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
01f2e4ea
SF		 2646
2647 return pci_register_driver(&enic_driver);
2648}
2649
2650static void __exit enic_cleanup_module(void)
2651{
2652 pci_unregister_driver(&enic_driver);
2653}
2654
2655module_init(enic_init_module);
2656module_exit(enic_cleanup_module);
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