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rxrpc: remove redundant initialization of variable 'len'
[linux-block.git] / drivers / net / ethernet / cisco / enic / enic_main.c
CommitLineData
01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF		 27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF		 32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF		 34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
7c2ce6e6 41#include <linux/ktime.h>
322cf7e3 42#include <linux/numa.h>
b6e97c13
GV		 43#ifdef CONFIG_RFS_ACCEL
44#include <linux/cpu_rmap.h>
45#endif
3f255dcc 46#include <linux/crash_dump.h>
7a655c63 47#include <net/busy_poll.h>
257e7382 48#include <net/vxlan.h>
01f2e4ea
SF		 49
50#include "cq_enet_desc.h"
51#include "vnic_dev.h"
52#include "vnic_intr.h"
53#include "vnic_stats.h"
f8bd9091 54#include "vnic_vic.h"
01f2e4ea
SF		 55#include "enic_res.h"
56#include "enic.h"
51987461 57#include "enic_dev.h"
b3abfbd2 58#include "enic_pp.h"
a145df23 59#include "enic_clsf.h"
01f2e4ea
SF		 60
61#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
SF		 62#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
63#define MAX_TSO (1 << 16)
64#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
65
66#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 67#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 68#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea 69
a03bb56e
GV		 70#define RX_COPYBREAK_DEFAULT 256
71
01f2e4ea 72/* Supported devices */
9baa3c34 73static const struct pci_device_id enic_id_table[] = {
ea0d7d91 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 76 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF		 77 { 0, } /* end of table */
78};
79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_VERSION);
84MODULE_DEVICE_TABLE(pci, enic_id_table);
85
7c2ce6e6
SS		 86#define ENIC_LARGE_PKT_THRESHOLD 1000
87#define ENIC_MAX_COALESCE_TIMERS 10
88/* Interrupt moderation table, which will be used to decide the
89 * coalescing timer values
90 * {rx_rate in Mbps, mapping percentage of the range}
91 */
57ae84a0 92static struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
7c2ce6e6
SS		 93 {4000, 0},
94 {4400, 10},
95 {5060, 20},
96 {5230, 30},
97 {5540, 40},
98 {5820, 50},
99 {6120, 60},
100 {6435, 70},
101 {6745, 80},
102 {7000, 90},
103 {0xFFFFFFFF, 100}
104};
105
106/* This table helps the driver to pick different ranges for rx coalescing
107 * timer depending on the link speed.
108 */
57ae84a0 109static struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
7c2ce6e6
SS		 110 {0, 0}, /* 0 - 4 Gbps */
111 {0, 3}, /* 4 - 10 Gbps */
112 {3, 6}, /* 10 - 40 Gbps */
113};
114
322cf7e3
GV		 115static void enic_init_affinity_hint(struct enic *enic)
116{
117 int numa_node = dev_to_node(&enic->pdev->dev);
118 int i;
119
120 for (i = 0; i < enic->intr_count; i++) {
121 if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i) ||
122 (enic->msix[i].affinity_mask &&
123 !cpumask_empty(enic->msix[i].affinity_mask)))
124 continue;
125 if (zalloc_cpumask_var(&enic->msix[i].affinity_mask,
126 GFP_KERNEL))
127 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
128 enic->msix[i].affinity_mask);
129 }
130}
131
132static void enic_free_affinity_hint(struct enic *enic)
133{
134 int i;
135
136 for (i = 0; i < enic->intr_count; i++) {
137 if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i))
138 continue;
139 free_cpumask_var(enic->msix[i].affinity_mask);
140 }
141}
142
143static void enic_set_affinity_hint(struct enic *enic)
144{
145 int i;
146 int err;
147
148 for (i = 0; i < enic->intr_count; i++) {
149 if (enic_is_err_intr(enic, i) ||
150 enic_is_notify_intr(enic, i) ||
151 !enic->msix[i].affinity_mask ||
152 cpumask_empty(enic->msix[i].affinity_mask))
153 continue;
154 err = irq_set_affinity_hint(enic->msix_entry[i].vector,
155 enic->msix[i].affinity_mask);
156 if (err)
157 netdev_warn(enic->netdev, "irq_set_affinity_hint failed, err %d\n",
158 err);
159 }
160
161 for (i = 0; i < enic->wq_count; i++) {
162 int wq_intr = enic_msix_wq_intr(enic, i);
163
164 if (enic->msix[wq_intr].affinity_mask &&
165 !cpumask_empty(enic->msix[wq_intr].affinity_mask))
166 netif_set_xps_queue(enic->netdev,
167 enic->msix[wq_intr].affinity_mask,
168 i);
169 }
170}
171
172static void enic_unset_affinity_hint(struct enic *enic)
173{
174 int i;
175
176 for (i = 0; i < enic->intr_count; i++)
177 irq_set_affinity_hint(enic->msix_entry[i].vector, NULL);
178}
179
257e7382
GV		 180static void enic_udp_tunnel_add(struct net_device *netdev,
181 struct udp_tunnel_info *ti)
182{
183 struct enic *enic = netdev_priv(netdev);
184 __be16 port = ti->port;
185 int err;
186
187 spin_lock_bh(&enic->devcmd_lock);
188
189 if (ti->type != UDP_TUNNEL_TYPE_VXLAN) {
190 netdev_info(netdev, "udp_tnl: only vxlan tunnel offload supported");
191 goto error;
192 }
193
d1179094
GV		 194 switch (ti->sa_family) {
195 case AF_INET6:
196 if (!(enic->vxlan.flags & ENIC_VXLAN_OUTER_IPV6)) {
197 netdev_info(netdev, "vxlan: only IPv4 offload supported");
198 goto error;
199 }
200 /* Fall through */
201 case AF_INET:
202 break;
203 default:
257e7382
GV		 204 goto error;
205 }
206
207 if (enic->vxlan.vxlan_udp_port_number) {
208 if (ntohs(port) == enic->vxlan.vxlan_udp_port_number)
209 netdev_warn(netdev, "vxlan: udp port already offloaded");
210 else
211 netdev_info(netdev, "vxlan: offload supported for only one UDP port");
212
213 goto error;
214 }
7e24c642
GV		 215 if ((vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ) != 1) &&
216 !(enic->vxlan.flags & ENIC_VXLAN_MULTI_WQ)) {
217 netdev_info(netdev, "vxlan: vxlan offload with multi wq not supported on this adapter");
218 goto error;
219 }
257e7382
GV		 220
221 err = vnic_dev_overlay_offload_cfg(enic->vdev,
222 OVERLAY_CFG_VXLAN_PORT_UPDATE,
223 ntohs(port));
224 if (err)
225 goto error;
226
227 err = vnic_dev_overlay_offload_ctrl(enic->vdev, OVERLAY_FEATURE_VXLAN,
228 enic->vxlan.patch_level);
229 if (err)
230 goto error;
231
232 enic->vxlan.vxlan_udp_port_number = ntohs(port);
233
234 netdev_info(netdev, "vxlan fw-vers-%d: offload enabled for udp port: %d, sa_family: %d ",
235 (int)enic->vxlan.patch_level, ntohs(port), ti->sa_family);
236
237 goto unlock;
238
239error:
240 netdev_info(netdev, "failed to offload udp port: %d, sa_family: %d, type: %d",
241 ntohs(port), ti->sa_family, ti->type);
242unlock:
243 spin_unlock_bh(&enic->devcmd_lock);
244}
245
246static void enic_udp_tunnel_del(struct net_device *netdev,
247 struct udp_tunnel_info *ti)
248{
249 struct enic *enic = netdev_priv(netdev);
250 int err;
251
252 spin_lock_bh(&enic->devcmd_lock);
253
254 if ((ti->sa_family != AF_INET) ||
255 ((ntohs(ti->port) != enic->vxlan.vxlan_udp_port_number)) ||
256 (ti->type != UDP_TUNNEL_TYPE_VXLAN)) {
257 netdev_info(netdev, "udp_tnl: port:%d, sa_family: %d, type: %d not offloaded",
258 ntohs(ti->port), ti->sa_family, ti->type);
259 goto unlock;
260 }
261
262 err = vnic_dev_overlay_offload_ctrl(enic->vdev, OVERLAY_FEATURE_VXLAN,
263 OVERLAY_OFFLOAD_DISABLE);
264 if (err) {
265 netdev_err(netdev, "vxlan: del offload udp port: %d failed",
266 ntohs(ti->port));
267 goto unlock;
268 }
269
270 enic->vxlan.vxlan_udp_port_number = 0;
271
272 netdev_info(netdev, "vxlan: del offload udp port %d, family %d\n",
273 ntohs(ti->port), ti->sa_family);
274
275unlock:
276 spin_unlock_bh(&enic->devcmd_lock);
277}
278
9c744d10
GV		 279static netdev_features_t enic_features_check(struct sk_buff *skb,
280 struct net_device *dev,
281 netdev_features_t features)
282{
283 const struct ethhdr *eth = (struct ethhdr *)skb_inner_mac_header(skb);
284 struct enic *enic = netdev_priv(dev);
285 struct udphdr *udph;
286 u16 port = 0;
d1179094 287 u8 proto;
9c744d10
GV		 288
289 if (!skb->encapsulation)
290 return features;
291
292 features = vxlan_features_check(skb, features);
293
d1179094
GV		 294 switch (vlan_get_protocol(skb)) {
295 case htons(ETH_P_IPV6):
296 if (!(enic->vxlan.flags & ENIC_VXLAN_OUTER_IPV6))
297 goto out;
298 proto = ipv6_hdr(skb)->nexthdr;
299 break;
300 case htons(ETH_P_IP):
301 proto = ip_hdr(skb)->protocol;
302 break;
303 default:
9c744d10 304 goto out;
d1179094 305 }
9c744d10 306
d1179094
GV		 307 switch (eth->h_proto) {
308 case ntohs(ETH_P_IPV6):
309 if (!(enic->vxlan.flags & ENIC_VXLAN_INNER_IPV6))
310 goto out;
311 /* Fall through */
312 case ntohs(ETH_P_IP):
313 break;
314 default:
9c744d10 315 goto out;
d1179094 316 }
9c744d10 317
9c744d10
GV		 318
319 if (proto == IPPROTO_UDP) {
320 udph = udp_hdr(skb);
321 port = be16_to_cpu(udph->dest);
322 }
323
324 /* HW supports offload of only one UDP port. Remove CSUM and GSO MASK
325 * for other UDP port tunnels
326 */
327 if (port != enic->vxlan.vxlan_udp_port_number)
328 goto out;
329
330 return features;
331
332out:
333 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
334}
335
3f192795 336int enic_is_dynamic(struct enic *enic)
f8bd9091
SF		 337{
338 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
339}
340
8749b427
RP		 341int enic_sriov_enabled(struct enic *enic)
342{
343 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
344}
345
3a4adef5
RP		 346static int enic_is_sriov_vf(struct enic *enic)
347{
348 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
349}
350
889d13f5
RP		 351int enic_is_valid_vf(struct enic *enic, int vf)
352{
353#ifdef CONFIG_PCI_IOV
354 return vf >= 0 && vf < enic->num_vfs;
355#else
356 return 0;
357#endif
358}
359
01f2e4ea
SF		 360static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
361{
362 struct enic *enic = vnic_dev_priv(wq->vdev);
363
364 if (buf->sop)
365 pci_unmap_single(enic->pdev, buf->dma_addr,
366 buf->len, PCI_DMA_TODEVICE);
367 else
368 pci_unmap_page(enic->pdev, buf->dma_addr,
369 buf->len, PCI_DMA_TODEVICE);
370
371 if (buf->os_buf)
372 dev_kfree_skb_any(buf->os_buf);
373}
374
375static void enic_wq_free_buf(struct vnic_wq *wq,
376 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
377{
378 enic_free_wq_buf(wq, buf);
379}
380
381static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
382 u8 type, u16 q_number, u16 completed_index, void *opaque)
383{
384 struct enic *enic = vnic_dev_priv(vdev);
385
386 spin_lock(&enic->wq_lock[q_number]);
387
388 vnic_wq_service(&enic->wq[q_number], cq_desc,
389 completed_index, enic_wq_free_buf,
390 opaque);
391
822473b6 392 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
SF		 393 vnic_wq_desc_avail(&enic->wq[q_number]) >=
394 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 395 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF		 396
397 spin_unlock(&enic->wq_lock[q_number]);
398
399 return 0;
400}
401
cc809237 402static bool enic_log_q_error(struct enic *enic)
01f2e4ea
SF		 403{
404 unsigned int i;
405 u32 error_status;
cc809237 406 bool err = false;
01f2e4ea
SF		 407
408 for (i = 0; i < enic->wq_count; i++) {
409 error_status = vnic_wq_error_status(&enic->wq[i]);
cc809237 410 err |= error_status;
01f2e4ea 411 if (error_status)
a7a79deb
VK		 412 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
413 i, error_status);
01f2e4ea
SF		 414 }
415
416 for (i = 0; i < enic->rq_count; i++) {
417 error_status = vnic_rq_error_status(&enic->rq[i]);
cc809237 418 err |= error_status;
01f2e4ea 419 if (error_status)
a7a79deb
VK		 420 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
421 i, error_status);
01f2e4ea 422 }
cc809237
GV		 423
424 return err;
01f2e4ea
SF		 425}
426
383ab92f 427static void enic_msglvl_check(struct enic *enic)
01f2e4ea 428{
383ab92f 429 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 430
383ab92f 431 if (msg_enable != enic->msg_enable) {
a7a79deb
VK		 432 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
433 enic->msg_enable, msg_enable);
383ab92f 434 enic->msg_enable = msg_enable;
01f2e4ea
SF		 435 }
436}
437
438static void enic_mtu_check(struct enic *enic)
439{
440 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 441 struct net_device *netdev = enic->netdev;
01f2e4ea 442
491598a4 443 if (mtu && mtu != enic->port_mtu) {
7c844599 444 enic->port_mtu = mtu;
7335903c 445 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP		 446 mtu = max_t(int, ENIC_MIN_MTU,
447 min_t(int, ENIC_MAX_MTU, mtu));
448 if (mtu != netdev->mtu)
449 schedule_work(&enic->change_mtu_work);
450 } else {
451 if (mtu < netdev->mtu)
452 netdev_warn(netdev,
453 "interface MTU (%d) set higher "
454 "than switch port MTU (%d)\n",
455 netdev->mtu, mtu);
456 }
01f2e4ea
SF		 457 }
458}
459
383ab92f 460static void enic_link_check(struct enic *enic)
01f2e4ea 461{
383ab92f
VK		 462 int link_status = vnic_dev_link_status(enic->vdev);
463 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 464
383ab92f 465 if (link_status && !carrier_ok) {
a7a79deb 466 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK		 467 netif_carrier_on(enic->netdev);
468 } else if (!link_status && carrier_ok) {
a7a79deb 469 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 470 netif_carrier_off(enic->netdev);
01f2e4ea
SF		 471 }
472}
473
474static void enic_notify_check(struct enic *enic)
475{
476 enic_msglvl_check(enic);
477 enic_mtu_check(enic);
478 enic_link_check(enic);
479}
480
481#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
482
483static irqreturn_t enic_isr_legacy(int irq, void *data)
484{
485 struct net_device *netdev = data;
486 struct enic *enic = netdev_priv(netdev);
717258ba
VK		 487 unsigned int io_intr = enic_legacy_io_intr();
488 unsigned int err_intr = enic_legacy_err_intr();
489 unsigned int notify_intr = enic_legacy_notify_intr();
01f2e4ea
SF		 490 u32 pba;
491
717258ba 492 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
SF		 493
494 pba = vnic_intr_legacy_pba(enic->legacy_pba);
495 if (!pba) {
717258ba 496 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 497 return IRQ_NONE; /* not our interrupt */
498 }
499
717258ba 500 if (ENIC_TEST_INTR(pba, notify_intr)) {
01f2e4ea 501 enic_notify_check(enic);
2b0c2e2d 502 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
ed8af6b2 503 }
01f2e4ea 504
717258ba
VK		 505 if (ENIC_TEST_INTR(pba, err_intr)) {
506 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
SF		 507 enic_log_q_error(enic);
508 /* schedule recovery from WQ/RQ error */
509 schedule_work(&enic->reset);
510 return IRQ_HANDLED;
511 }
512
db40b3f5
GV		 513 if (ENIC_TEST_INTR(pba, io_intr))
514 napi_schedule_irqoff(&enic->napi[0]);
515 else
717258ba 516 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 517
518 return IRQ_HANDLED;
519}
520
521static irqreturn_t enic_isr_msi(int irq, void *data)
522{
523 struct enic *enic = data;
524
525 /* With MSI, there is no sharing of interrupts, so this is
526 * our interrupt and there is no need to ack it. The device
527 * is not providing per-vector masking, so the OS will not
528 * write to PCI config space to mask/unmask the interrupt.
529 * We're using mask_on_assertion for MSI, so the device
530 * automatically masks the interrupt when the interrupt is
531 * generated. Later, when exiting polling, the interrupt
532 * will be unmasked (see enic_poll).
533 *
534 * Also, the device uses the same PCIe Traffic Class (TC)
535 * for Memory Write data and MSI, so there are no ordering
536 * issues; the MSI will always arrive at the Root Complex
537 * _after_ corresponding Memory Writes (i.e. descriptor
538 * writes).
539 */
540
db40b3f5 541 napi_schedule_irqoff(&enic->napi[0]);
01f2e4ea
SF		 542
543 return IRQ_HANDLED;
544}
545
4cfe8785 546static irqreturn_t enic_isr_msix(int irq, void *data)
01f2e4ea 547{
717258ba 548 struct napi_struct *napi = data;
01f2e4ea 549
db40b3f5 550 napi_schedule_irqoff(napi);
01f2e4ea
SF		 551
552 return IRQ_HANDLED;
553}
554
01f2e4ea
SF		 555static irqreturn_t enic_isr_msix_err(int irq, void *data)
556{
557 struct enic *enic = data;
717258ba 558 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 559
717258ba 560 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 561
cc809237
GV		 562 if (enic_log_q_error(enic))
563 /* schedule recovery from WQ/RQ error */
564 schedule_work(&enic->reset);
01f2e4ea
SF		 565
566 return IRQ_HANDLED;
567}
568
569static irqreturn_t enic_isr_msix_notify(int irq, void *data)
570{
571 struct enic *enic = data;
717258ba 572 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea
SF		 573
574 enic_notify_check(enic);
2b0c2e2d 575 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea
SF		 576
577 return IRQ_HANDLED;
578}
579
065df159
GV		 580static int enic_queue_wq_skb_cont(struct enic *enic, struct vnic_wq *wq,
581 struct sk_buff *skb, unsigned int len_left,
582 int loopback)
01f2e4ea 583{
9e903e08 584 const skb_frag_t *frag;
065df159 585 dma_addr_t dma_addr;
01f2e4ea
SF		 586
587 /* Queue additional data fragments */
588 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 589 len_left -= skb_frag_size(frag);
065df159
GV		 590 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 0,
591 skb_frag_size(frag),
592 DMA_TO_DEVICE);
593 if (unlikely(enic_dma_map_check(enic, dma_addr)))
594 return -ENOMEM;
595 enic_queue_wq_desc_cont(wq, skb, dma_addr, skb_frag_size(frag),
596 (len_left == 0), /* EOP? */
597 loopback);
01f2e4ea 598 }
065df159
GV		 599
600 return 0;
01f2e4ea
SF		 601}
602
065df159
GV		 603static int enic_queue_wq_skb_vlan(struct enic *enic, struct vnic_wq *wq,
604 struct sk_buff *skb, int vlan_tag_insert,
605 unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 606{
607 unsigned int head_len = skb_headlen(skb);
608 unsigned int len_left = skb->len - head_len;
609 int eop = (len_left == 0);
065df159
GV		 610 dma_addr_t dma_addr;
611 int err = 0;
612
613 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
614 PCI_DMA_TODEVICE);
615 if (unlikely(enic_dma_map_check(enic, dma_addr)))
616 return -ENOMEM;
01f2e4ea 617
ea0d7d91
SF		 618 /* Queue the main skb fragment. The fragments are no larger
619 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
620 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
621 * per fragment is queued.
622 */
065df159
GV		 623 enic_queue_wq_desc(wq, skb, dma_addr, head_len, vlan_tag_insert,
624 vlan_tag, eop, loopback);
01f2e4ea
SF		 625
626 if (!eop)
065df159
GV		 627 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
628
629 return err;
01f2e4ea
SF		 630}
631
065df159
GV		 632static int enic_queue_wq_skb_csum_l4(struct enic *enic, struct vnic_wq *wq,
633 struct sk_buff *skb, int vlan_tag_insert,
634 unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 635{
636 unsigned int head_len = skb_headlen(skb);
637 unsigned int len_left = skb->len - head_len;
0d0b1672 638 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF		 639 unsigned int csum_offset = hdr_len + skb->csum_offset;
640 int eop = (len_left == 0);
065df159
GV		 641 dma_addr_t dma_addr;
642 int err = 0;
643
644 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
645 PCI_DMA_TODEVICE);
646 if (unlikely(enic_dma_map_check(enic, dma_addr)))
647 return -ENOMEM;
01f2e4ea 648
ea0d7d91
SF		 649 /* Queue the main skb fragment. The fragments are no larger
650 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
651 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
652 * per fragment is queued.
653 */
065df159
GV		 654 enic_queue_wq_desc_csum_l4(wq, skb, dma_addr, head_len, csum_offset,
655 hdr_len, vlan_tag_insert, vlan_tag, eop,
656 loopback);
01f2e4ea
SF		 657
658 if (!eop)
065df159
GV		 659 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
660
661 return err;
01f2e4ea
SF		 662}
663
9c744d10 664static void enic_preload_tcp_csum_encap(struct sk_buff *skb)
01f2e4ea 665{
4a464a2b
GV		 666 const struct ethhdr *eth = (struct ethhdr *)skb_inner_mac_header(skb);
667
668 switch (eth->h_proto) {
669 case ntohs(ETH_P_IP):
9c744d10
GV		 670 inner_ip_hdr(skb)->check = 0;
671 inner_tcp_hdr(skb)->check =
672 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
673 inner_ip_hdr(skb)->daddr, 0,
674 IPPROTO_TCP, 0);
4a464a2b
GV		 675 break;
676 case ntohs(ETH_P_IPV6):
677 inner_tcp_hdr(skb)->check =
678 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
679 &inner_ipv6_hdr(skb)->daddr, 0,
680 IPPROTO_TCP, 0);
681 break;
682 default:
683 WARN_ONCE(1, "Non ipv4/ipv6 inner pkt for encap offload");
684 break;
9c744d10
GV		 685 }
686}
01f2e4ea 687
9c744d10
GV		 688static void enic_preload_tcp_csum(struct sk_buff *skb)
689{
01f2e4ea
SF		 690 /* Preload TCP csum field with IP pseudo hdr calculated
691 * with IP length set to zero. HW will later add in length
692 * to each TCP segment resulting from the TSO.
693 */
694
09640e63 695 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF		 696 ip_hdr(skb)->check = 0;
697 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
698 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 699 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
01f2e4ea
SF		 700 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
701 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
702 }
9c744d10
GV		 703}
704
705static int enic_queue_wq_skb_tso(struct enic *enic, struct vnic_wq *wq,
706 struct sk_buff *skb, unsigned int mss,
707 int vlan_tag_insert, unsigned int vlan_tag,
708 int loopback)
709{
710 unsigned int frag_len_left = skb_headlen(skb);
711 unsigned int len_left = skb->len - frag_len_left;
712 int eop = (len_left == 0);
713 unsigned int offset = 0;
714 unsigned int hdr_len;
715 dma_addr_t dma_addr;
716 unsigned int len;
717 skb_frag_t *frag;
718
719 if (skb->encapsulation) {
720 hdr_len = skb_inner_transport_header(skb) - skb->data;
721 hdr_len += inner_tcp_hdrlen(skb);
722 enic_preload_tcp_csum_encap(skb);
723 } else {
724 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
725 enic_preload_tcp_csum(skb);
726 }
01f2e4ea 727
ea0d7d91
SF		 728 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
729 * for the main skb fragment
730 */
731 while (frag_len_left) {
732 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
065df159
GV		 733 dma_addr = pci_map_single(enic->pdev, skb->data + offset, len,
734 PCI_DMA_TODEVICE);
735 if (unlikely(enic_dma_map_check(enic, dma_addr)))
736 return -ENOMEM;
737 enic_queue_wq_desc_tso(wq, skb, dma_addr, len, mss, hdr_len,
738 vlan_tag_insert, vlan_tag,
739 eop && (len == frag_len_left), loopback);
ea0d7d91
SF		 740 frag_len_left -= len;
741 offset += len;
742 }
01f2e4ea 743
ea0d7d91 744 if (eop)
065df159 745 return 0;
ea0d7d91
SF		 746
747 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
748 * for additional data fragments
749 */
750 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED		 751 len_left -= skb_frag_size(frag);
752 frag_len_left = skb_frag_size(frag);
4bf5adbf 753 offset = 0;
ea0d7d91
SF		 754
755 while (frag_len_left) {
756 len = min(frag_len_left,
757 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC		 758 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
759 offset, len,
5d6bcdfe 760 DMA_TO_DEVICE);
065df159
GV		 761 if (unlikely(enic_dma_map_check(enic, dma_addr)))
762 return -ENOMEM;
763 enic_queue_wq_desc_cont(wq, skb, dma_addr, len,
764 (len_left == 0) &&
765 (len == frag_len_left),/*EOP*/
766 loopback);
ea0d7d91
SF		 767 frag_len_left -= len;
768 offset += len;
769 }
770 }
065df159
GV		 771
772 return 0;
01f2e4ea
SF		 773}
774
9c744d10
GV		 775static inline int enic_queue_wq_skb_encap(struct enic *enic, struct vnic_wq *wq,
776 struct sk_buff *skb,
777 int vlan_tag_insert,
778 unsigned int vlan_tag, int loopback)
779{
780 unsigned int head_len = skb_headlen(skb);
781 unsigned int len_left = skb->len - head_len;
782 /* Hardware will overwrite the checksum fields, calculating from
783 * scratch and ignoring the value placed by software.
784 * Offload mode = 00
785 * mss[2], mss[1], mss[0] bits are set
786 */
787 unsigned int mss_or_csum = 7;
788 int eop = (len_left == 0);
789 dma_addr_t dma_addr;
790 int err = 0;
791
792 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
793 PCI_DMA_TODEVICE);
794 if (unlikely(enic_dma_map_check(enic, dma_addr)))
795 return -ENOMEM;
796
797 enic_queue_wq_desc_ex(wq, skb, dma_addr, head_len, mss_or_csum, 0,
798 vlan_tag_insert, vlan_tag,
799 WQ_ENET_OFFLOAD_MODE_CSUM, eop, 1 /* SOP */, eop,
800 loopback);
801 if (!eop)
802 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
803
804 return err;
805}
806
01f2e4ea
SF		 807static inline void enic_queue_wq_skb(struct enic *enic,
808 struct vnic_wq *wq, struct sk_buff *skb)
809{
810 unsigned int mss = skb_shinfo(skb)->gso_size;
811 unsigned int vlan_tag = 0;
812 int vlan_tag_insert = 0;
1825aca6 813 int loopback = 0;
065df159 814 int err;
01f2e4ea 815
df8a39de 816 if (skb_vlan_tag_present(skb)) {
01f2e4ea
SF		 817 /* VLAN tag from trunking driver */
818 vlan_tag_insert = 1;
df8a39de 819 vlan_tag = skb_vlan_tag_get(skb);
1825aca6
VK		 820 } else if (enic->loop_enable) {
821 vlan_tag = enic->loop_tag;
822 loopback = 1;
01f2e4ea
SF		 823 }
824
825 if (mss)
065df159
GV		 826 err = enic_queue_wq_skb_tso(enic, wq, skb, mss,
827 vlan_tag_insert, vlan_tag,
828 loopback);
9c744d10
GV		 829 else if (skb->encapsulation)
830 err = enic_queue_wq_skb_encap(enic, wq, skb, vlan_tag_insert,
831 vlan_tag, loopback);
01f2e4ea 832 else if (skb->ip_summed == CHECKSUM_PARTIAL)
065df159
GV		 833 err = enic_queue_wq_skb_csum_l4(enic, wq, skb, vlan_tag_insert,
834 vlan_tag, loopback);
01f2e4ea 835 else
065df159
GV		 836 err = enic_queue_wq_skb_vlan(enic, wq, skb, vlan_tag_insert,
837 vlan_tag, loopback);
838 if (unlikely(err)) {
839 struct vnic_wq_buf *buf;
840
841 buf = wq->to_use->prev;
842 /* while not EOP of previous pkt && queue not empty.
843 * For all non EOP bufs, os_buf is NULL.
844 */
845 while (!buf->os_buf && (buf->next != wq->to_clean)) {
846 enic_free_wq_buf(wq, buf);
847 wq->ring.desc_avail++;
848 buf = buf->prev;
849 }
850 wq->to_use = buf->next;
851 dev_kfree_skb(skb);
852 }
01f2e4ea
SF		 853}
854
ed8af6b2 855/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 856static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 857 struct net_device *netdev)
01f2e4ea
SF		 858{
859 struct enic *enic = netdev_priv(netdev);
822473b6 860 struct vnic_wq *wq;
822473b6 861 unsigned int txq_map;
f8e34d24 862 struct netdev_queue *txq;
01f2e4ea
SF		 863
864 if (skb->len <= 0) {
98d8a65d 865 dev_kfree_skb_any(skb);
01f2e4ea
SF		 866 return NETDEV_TX_OK;
867 }
868
822473b6 869 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
870 wq = &enic->wq[txq_map];
f8e34d24 871 txq = netdev_get_tx_queue(netdev, txq_map);
822473b6 872
01f2e4ea
SF		 873 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
874 * which is very likely. In the off chance it's going to take
875 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
876 */
877
878 if (skb_shinfo(skb)->gso_size == 0 &&
879 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
880 skb_linearize(skb)) {
98d8a65d 881 dev_kfree_skb_any(skb);
01f2e4ea
SF		 882 return NETDEV_TX_OK;
883 }
884
78e2045d 885 spin_lock(&enic->wq_lock[txq_map]);
01f2e4ea 886
ea0d7d91
SF		 887 if (vnic_wq_desc_avail(wq) <
888 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
f8e34d24 889 netif_tx_stop_queue(txq);
01f2e4ea 890 /* This is a hard error, log it */
a7a79deb 891 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
78e2045d 892 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 893 return NETDEV_TX_BUSY;
894 }
895
896 enic_queue_wq_skb(enic, wq, skb);
897
ea0d7d91 898 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
f8e34d24 899 netif_tx_stop_queue(txq);
fb7516d4 900 skb_tx_timestamp(skb);
f8e34d24
GV		 901 if (!skb->xmit_more || netif_xmit_stopped(txq))
902 vnic_wq_doorbell(wq);
01f2e4ea 903
78e2045d 904 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 905
906 return NETDEV_TX_OK;
907}
908
909/* dev_base_lock rwlock held, nominally process context */
bc1f4470 910static void enic_get_stats(struct net_device *netdev,
911 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF		 912{
913 struct enic *enic = netdev_priv(netdev);
914 struct vnic_stats *stats;
19b596bd 915 int err;
01f2e4ea 916
19b596bd
GV		 917 err = enic_dev_stats_dump(enic, &stats);
918 /* return only when pci_zalloc_consistent fails in vnic_dev_stats_dump
919 * For other failures, like devcmd failure, we return previously
920 * recorded stats.
921 */
922 if (err == -ENOMEM)
bc1f4470 923 return;
01f2e4ea 924
25f0a061
SF		 925 net_stats->tx_packets = stats->tx.tx_frames_ok;
926 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
927 net_stats->tx_errors = stats->tx.tx_errors;
928 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 929
25f0a061
SF		 930 net_stats->rx_packets = stats->rx.rx_frames_ok;
931 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
932 net_stats->rx_errors = stats->rx.rx_errors;
933 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 934 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 935 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 936 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea
SF		 937}
938
f009618a
AD		 939static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
940{
941 struct enic *enic = netdev_priv(netdev);
942
943 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
944 unsigned int mc_count = netdev_mc_count(netdev);
945
946 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
947 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
948
949 return -ENOSPC;
950 }
951
952 enic_dev_add_addr(enic, mc_addr);
953 enic->mc_count++;
954
955 return 0;
956}
957
958static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
959{
960 struct enic *enic = netdev_priv(netdev);
961
962 enic_dev_del_addr(enic, mc_addr);
963 enic->mc_count--;
964
965 return 0;
966}
967
968static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
969{
970 struct enic *enic = netdev_priv(netdev);
971
972 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
973 unsigned int uc_count = netdev_uc_count(netdev);
974
975 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
976 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
977
978 return -ENOSPC;
979 }
980
981 enic_dev_add_addr(enic, uc_addr);
982 enic->uc_count++;
983
984 return 0;
985}
986
987static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
988{
989 struct enic *enic = netdev_priv(netdev);
990
991 enic_dev_del_addr(enic, uc_addr);
992 enic->uc_count--;
993
994 return 0;
995}
996
b3abfbd2 997void enic_reset_addr_lists(struct enic *enic)
01f2e4ea 998{
f009618a
AD		 999 struct net_device *netdev = enic->netdev;
1000
1001 __dev_uc_unsync(netdev, NULL);
1002 __dev_mc_unsync(netdev, NULL);
1003
01f2e4ea 1004 enic->mc_count = 0;
e0afe53f 1005 enic->uc_count = 0;
99ef5639 1006 enic->flags = 0;
01f2e4ea
SF		 1007}
1008
1009static int enic_set_mac_addr(struct net_device *netdev, char *addr)
1010{
f8bd9091
SF		 1011 struct enic *enic = netdev_priv(netdev);
1012
7335903c 1013 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF		 1014 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
1015 return -EADDRNOTAVAIL;
1016 } else {
1017 if (!is_valid_ether_addr(addr))
1018 return -EADDRNOTAVAIL;
1019 }
01f2e4ea
SF		 1020
1021 memcpy(netdev->dev_addr, addr, netdev->addr_len);
1022
1023 return 0;
1024}
1025
f8bd9091
SF		 1026static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
1027{
1028 struct enic *enic = netdev_priv(netdev);
1029 struct sockaddr *saddr = p;
1030 char *addr = saddr->sa_data;
1031 int err;
1032
1033 if (netif_running(enic->netdev)) {
1034 err = enic_dev_del_station_addr(enic);
1035 if (err)
1036 return err;
1037 }
1038
1039 err = enic_set_mac_addr(netdev, addr);
1040 if (err)
1041 return err;
1042
1043 if (netif_running(enic->netdev)) {
1044 err = enic_dev_add_station_addr(enic);
1045 if (err)
1046 return err;
1047 }
1048
1049 return err;
1050}
1051
1052static int enic_set_mac_address(struct net_device *netdev, void *p)
1053{
294dab25 1054 struct sockaddr *saddr = p;
c76fd32d
VK		 1055 char *addr = saddr->sa_data;
1056 struct enic *enic = netdev_priv(netdev);
1057 int err;
1058
1059 err = enic_dev_del_station_addr(enic);
1060 if (err)
1061 return err;
1062
1063 err = enic_set_mac_addr(netdev, addr);
1064 if (err)
1065 return err;
294dab25 1066
c76fd32d 1067 return enic_dev_add_station_addr(enic);
f8bd9091
SF		 1068}
1069
319d7e84
RP		 1070/* netif_tx_lock held, BHs disabled */
1071static void enic_set_rx_mode(struct net_device *netdev)
1072{
1073 struct enic *enic = netdev_priv(netdev);
1074 int directed = 1;
1075 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
1076 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
1077 int promisc = (netdev->flags & IFF_PROMISC) ||
1078 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
1079 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
1080 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
1081 unsigned int flags = netdev->flags |
1082 (allmulti ? IFF_ALLMULTI : 0) |
1083 (promisc ? IFF_PROMISC : 0);
1084
1085 if (enic->flags != flags) {
1086 enic->flags = flags;
1087 enic_dev_packet_filter(enic, directed,
1088 multicast, broadcast, promisc, allmulti);
1089 }
1090
1091 if (!promisc) {
f009618a 1092 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
319d7e84 1093 if (!allmulti)
f009618a 1094 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
319d7e84
RP		 1095 }
1096}
1097
01f2e4ea
SF		 1098/* netif_tx_lock held, BHs disabled */
1099static void enic_tx_timeout(struct net_device *netdev)
1100{
1101 struct enic *enic = netdev_priv(netdev);
937317c7 1102 schedule_work(&enic->tx_hang_reset);
01f2e4ea
SF		 1103}
1104
0b1c00fc
RP		 1105static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
1106{
1107 struct enic *enic = netdev_priv(netdev);
3f192795
RP		 1108 struct enic_port_profile *pp;
1109 int err;
0b1c00fc 1110
3f192795
RP		 1111 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1112 if (err)
1113 return err;
0b1c00fc 1114
b8622cbd 1115 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP		 1116 if (vf == PORT_SELF_VF) {
1117 memcpy(pp->vf_mac, mac, ETH_ALEN);
1118 return 0;
1119 } else {
1120 /*
1121 * For sriov vf's set the mac in hw
1122 */
1123 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
1124 vnic_dev_set_mac_addr, mac);
1125 return enic_dev_status_to_errno(err);
1126 }
0b1c00fc
RP		 1127 } else
1128 return -EINVAL;
1129}
1130
f8bd9091
SF		 1131static int enic_set_vf_port(struct net_device *netdev, int vf,
1132 struct nlattr *port[])
1133{
1134 struct enic *enic = netdev_priv(netdev);
b3abfbd2 1135 struct enic_port_profile prev_pp;
3f192795 1136 struct enic_port_profile *pp;
b3abfbd2 1137 int err = 0, restore_pp = 1;
08f382eb 1138
3f192795
RP		 1139 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1140 if (err)
1141 return err;
08f382eb 1142
b3abfbd2
RP		 1143 if (!port[IFLA_PORT_REQUEST])
1144 return -EOPNOTSUPP;
1145
3f192795
RP		 1146 memcpy(&prev_pp, pp, sizeof(*enic->pp));
1147 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 1148
3f192795
RP		 1149 pp->set |= ENIC_SET_REQUEST;
1150 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF		 1151
1152 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP		 1153 pp->set |= ENIC_SET_NAME;
1154 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF		 1155 PORT_PROFILE_MAX);
1156 }
1157
1158 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP		 1159 pp->set |= ENIC_SET_INSTANCE;
1160 memcpy(pp->instance_uuid,
08f382eb
SF		 1161 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
1162 }
1163
1164 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP		 1165 pp->set |= ENIC_SET_HOST;
1166 memcpy(pp->host_uuid,
08f382eb
SF		 1167 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
1168 }
f8bd9091 1169
b4765833
RP		 1170 if (vf == PORT_SELF_VF) {
1171 /* Special case handling: mac came from IFLA_VF_MAC */
1172 if (!is_zero_ether_addr(prev_pp.vf_mac))
1173 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 1174
b4765833
RP		 1175 if (is_zero_ether_addr(netdev->dev_addr))
1176 eth_hw_addr_random(netdev);
1177 } else {
1178 /* SR-IOV VF: get mac from adapter */
1179 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
1180 vnic_dev_get_mac_addr, pp->mac_addr);
1181 if (err) {
1182 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
1183 memcpy(pp, &prev_pp, sizeof(*pp));
1184 return enic_dev_status_to_errno(err);
1185 }
1186 }
f8bd9091 1187
3f192795 1188 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP		 1189 if (err) {
1190 if (restore_pp) {
1191 /* Things are still the way they were: Implicit
1192 * DISASSOCIATE failed
1193 */
3f192795 1194 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 1195 } else {
3f192795
RP		 1196 memset(pp, 0, sizeof(*pp));
1197 if (vf == PORT_SELF_VF)
c7bf7169 1198 eth_zero_addr(netdev->dev_addr);
b3abfbd2
RP		 1199 }
1200 } else {
1201 /* Set flag to indicate that the port assoc/disassoc
1202 * request has been sent out to fw
1203 */
3f192795 1204 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP		 1205
1206 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795 1207 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
c7bf7169 1208 eth_zero_addr(pp->mac_addr);
3f192795 1209 if (vf == PORT_SELF_VF)
c7bf7169 1210 eth_zero_addr(netdev->dev_addr);
b3abfbd2
RP		 1211 }
1212 }
29639059 1213
b4765833 1214 if (vf == PORT_SELF_VF)
c7bf7169 1215 eth_zero_addr(pp->vf_mac);
29639059 1216
29639059 1217 return err;
f8bd9091
SF		 1218}
1219
1220static int enic_get_vf_port(struct net_device *netdev, int vf,
1221 struct sk_buff *skb)
1222{
1223 struct enic *enic = netdev_priv(netdev);
f8bd9091 1224 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 1225 struct enic_port_profile *pp;
b3abfbd2 1226 int err;
f8bd9091 1227
3f192795
RP		 1228 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1229 if (err)
1230 return err;
1231
1232 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 1233 return -ENODATA;
f8bd9091 1234
3f192795 1235 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 1236 if (err)
b3abfbd2 1237 return err;
f8bd9091 1238
1a106de6
DM		 1239 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
1240 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
1241 ((pp->set & ENIC_SET_NAME) &&
1242 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
1243 ((pp->set & ENIC_SET_INSTANCE) &&
1244 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
1245 pp->instance_uuid)) ||
1246 ((pp->set & ENIC_SET_HOST) &&
1247 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
1248 goto nla_put_failure;
f8bd9091
SF		 1249 return 0;
1250
1251nla_put_failure:
1252 return -EMSGSIZE;
1253}
1254
01f2e4ea
SF		 1255static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
1256{
1257 struct enic *enic = vnic_dev_priv(rq->vdev);
1258
1259 if (!buf->os_buf)
1260 return;
1261
1262 pci_unmap_single(enic->pdev, buf->dma_addr,
1263 buf->len, PCI_DMA_FROMDEVICE);
1264 dev_kfree_skb_any(buf->os_buf);
a03bb56e 1265 buf->os_buf = NULL;
01f2e4ea
SF		 1266}
1267
01f2e4ea
SF		 1268static int enic_rq_alloc_buf(struct vnic_rq *rq)
1269{
1270 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 1271 struct net_device *netdev = enic->netdev;
01f2e4ea 1272 struct sk_buff *skb;
1825aca6 1273 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF		 1274 unsigned int os_buf_index = 0;
1275 dma_addr_t dma_addr;
a03bb56e
GV		 1276 struct vnic_rq_buf *buf = rq->to_use;
1277
1278 if (buf->os_buf) {
f6b7734b
GV		 1279 enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
1280 buf->len);
01f2e4ea 1281
a03bb56e
GV		 1282 return 0;
1283 }
89d71a66 1284 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF		 1285 if (!skb)
1286 return -ENOMEM;
1287
065df159
GV		 1288 dma_addr = pci_map_single(enic->pdev, skb->data, len,
1289 PCI_DMA_FROMDEVICE);
1290 if (unlikely(enic_dma_map_check(enic, dma_addr))) {
1291 dev_kfree_skb(skb);
1292 return -ENOMEM;
1293 }
01f2e4ea
SF		 1294
1295 enic_queue_rq_desc(rq, skb, os_buf_index,
1296 dma_addr, len);
1297
1298 return 0;
1299}
1300
7c2ce6e6
SS		 1301static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
1302 u32 pkt_len)
1303{
1304 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
1305 pkt_size->large_pkt_bytes_cnt += pkt_len;
1306 else
1307 pkt_size->small_pkt_bytes_cnt += pkt_len;
1308}
1309
a03bb56e
GV		 1310static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
1311 struct vnic_rq_buf *buf, u16 len)
1312{
1313 struct enic *enic = netdev_priv(netdev);
1314 struct sk_buff *new_skb;
1315
1316 if (len > enic->rx_copybreak)
1317 return false;
1318 new_skb = netdev_alloc_skb_ip_align(netdev, len);
1319 if (!new_skb)
1320 return false;
1321 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
1322 DMA_FROM_DEVICE);
1323 memcpy(new_skb->data, (*skb)->data, len);
1324 *skb = new_skb;
1325
1326 return true;
1327}
1328
01f2e4ea
SF		 1329static void enic_rq_indicate_buf(struct vnic_rq *rq,
1330 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
1331 int skipped, void *opaque)
1332{
1333 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 1334 struct net_device *netdev = enic->netdev;
01f2e4ea 1335 struct sk_buff *skb;
7c2ce6e6 1336 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
01f2e4ea
SF		 1337
1338 u8 type, color, eop, sop, ingress_port, vlan_stripped;
1339 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
1340 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
1341 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
1342 u8 packet_error;
f8cac14a 1343 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea 1344 u32 rss_hash;
257e7382 1345 bool outer_csum_ok = true, encap = false;
01f2e4ea
SF		 1346
1347 if (skipped)
1348 return;
1349
1350 skb = buf->os_buf;
01f2e4ea
SF		 1351
1352 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
1353 &type, &color, &q_number, &completed_index,
1354 &ingress_port, &fcoe, &eop, &sop, &rss_type,
1355 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 1356 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF		 1357 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
1358 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
1359 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
1360 &fcs_ok);
1361
1362 if (packet_error) {
1363
350991e1
SF		 1364 if (!fcs_ok) {
1365 if (bytes_written > 0)
1366 enic->rq_bad_fcs++;
1367 else if (bytes_written == 0)
1368 enic->rq_truncated_pkts++;
1369 }
01f2e4ea 1370
44aa91ab
GV		 1371 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1372 PCI_DMA_FROMDEVICE);
01f2e4ea 1373 dev_kfree_skb_any(skb);
44aa91ab 1374 buf->os_buf = NULL;
01f2e4ea
SF		 1375
1376 return;
1377 }
1378
1379 if (eop && bytes_written > 0) {
1380
1381 /* Good receive
1382 */
1383
a03bb56e
GV		 1384 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
1385 buf->os_buf = NULL;
1386 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1387 PCI_DMA_FROMDEVICE);
1388 }
1389 prefetch(skb->data - NET_IP_ALIGN);
1390
01f2e4ea 1391 skb_put(skb, bytes_written);
86ca9db7 1392 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1393 skb_record_rx_queue(skb, q_number);
257e7382
GV		 1394 if ((netdev->features & NETIF_F_RXHASH) && rss_hash &&
1395 (type == 3)) {
17197236
GV		 1396 switch (rss_type) {
1397 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4:
1398 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6:
1399 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX:
1400 skb_set_hash(skb, rss_hash, PKT_HASH_TYPE_L4);
1401 break;
1402 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv4:
1403 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv6:
1404 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX:
1405 skb_set_hash(skb, rss_hash, PKT_HASH_TYPE_L3);
1406 break;
1407 }
bf751ba8 1408 }
257e7382
GV		 1409 if (enic->vxlan.vxlan_udp_port_number) {
1410 switch (enic->vxlan.patch_level) {
1411 case 0:
1412 if (fcoe) {
1413 encap = true;
1414 outer_csum_ok = fcoe_fc_crc_ok;
1415 }
1416 break;
1417 case 2:
1418 if ((type == 7) &&
1419 (rss_hash & BIT(0))) {
1420 encap = true;
1421 outer_csum_ok = (rss_hash & BIT(1)) &&
1422 (rss_hash & BIT(2));
1423 }
1424 break;
1425 }
1426 }
01f2e4ea 1427
17e96834
GV		 1428 /* Hardware does not provide whole packet checksum. It only
1429 * provides pseudo checksum. Since hw validates the packet
1430 * checksum but not provide us the checksum value. use
1431 * CHECSUM_UNNECESSARY.
257e7382
GV		 1432 *
1433 * In case of encap pkt tcp_udp_csum_ok/tcp_udp_csum_ok is
1434 * inner csum_ok. outer_csum_ok is set by hw when outer udp
1435 * csum is correct or is zero.
17e96834 1436 */
257e7382
GV		 1437 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc &&
1438 tcp_udp_csum_ok && ipv4_csum_ok && outer_csum_ok) {
17e96834 1439 skb->ip_summed = CHECKSUM_UNNECESSARY;
257e7382
GV		 1440 skb->csum_level = encap;
1441 }
01f2e4ea 1442
6ede746b 1443 if (vlan_stripped)
86a9bad3 1444 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1445
14747cd9 1446 skb_mark_napi_id(skb, &enic->napi[rq->index]);
7a655c63 1447 if (!(netdev->features & NETIF_F_GRO))
6ede746b 1448 netif_receive_skb(skb);
14747cd9
GV		 1449 else
1450 napi_gro_receive(&enic->napi[q_number], skb);
7c2ce6e6
SS		 1451 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1452 enic_intr_update_pkt_size(&cq->pkt_size_counter,
1453 bytes_written);
01f2e4ea
SF		 1454 } else {
1455
1456 /* Buffer overflow
1457 */
1458
44aa91ab
GV		 1459 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1460 PCI_DMA_FROMDEVICE);
01f2e4ea 1461 dev_kfree_skb_any(skb);
44aa91ab 1462 buf->os_buf = NULL;
01f2e4ea
SF		 1463 }
1464}
1465
1466static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1467 u8 type, u16 q_number, u16 completed_index, void *opaque)
1468{
1469 struct enic *enic = vnic_dev_priv(vdev);
1470
1471 vnic_rq_service(&enic->rq[q_number], cq_desc,
1472 completed_index, VNIC_RQ_RETURN_DESC,
1473 enic_rq_indicate_buf, opaque);
1474
1475 return 0;
1476}
1477
fc865d6b
GV		 1478static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
1479{
1480 unsigned int intr = enic_msix_rq_intr(enic, rq->index);
1481 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1482 u32 timer = cq->tobe_rx_coal_timeval;
1483
1484 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
1485 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
1486 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
1487 }
1488}
1489
1490static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
1491{
1492 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1493 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1494 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
1495 int index;
1496 u32 timer;
1497 u32 range_start;
1498 u32 traffic;
1499 u64 delta;
1500 ktime_t now = ktime_get();
1501
1502 delta = ktime_us_delta(now, cq->prev_ts);
1503 if (delta < ENIC_AIC_TS_BREAK)
1504 return;
1505 cq->prev_ts = now;
1506
1507 traffic = pkt_size_counter->large_pkt_bytes_cnt +
1508 pkt_size_counter->small_pkt_bytes_cnt;
1509 /* The table takes Mbps
1510 * traffic *= 8 => bits
1511 * traffic *= (10^6 / delta) => bps
1512 * traffic /= 10^6 => Mbps
1513 *
1514 * Combining, traffic *= (8 / delta)
1515 */
1516
1517 traffic <<= 3;
1518 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
1519
1520 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
1521 if (traffic < mod_table[index].rx_rate)
1522 break;
1523 range_start = (pkt_size_counter->small_pkt_bytes_cnt >
1524 pkt_size_counter->large_pkt_bytes_cnt << 1) ?
1525 rx_coal->small_pkt_range_start :
1526 rx_coal->large_pkt_range_start;
1527 timer = range_start + ((rx_coal->range_end - range_start) *
1528 mod_table[index].range_percent / 100);
1529 /* Damping */
1530 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
1531
1532 pkt_size_counter->large_pkt_bytes_cnt = 0;
1533 pkt_size_counter->small_pkt_bytes_cnt = 0;
1534}
1535
01f2e4ea
SF		 1536static int enic_poll(struct napi_struct *napi, int budget)
1537{
717258ba
VK		 1538 struct net_device *netdev = napi->dev;
1539 struct enic *enic = netdev_priv(netdev);
1540 unsigned int cq_rq = enic_cq_rq(enic, 0);
1541 unsigned int cq_wq = enic_cq_wq(enic, 0);
1542 unsigned int intr = enic_legacy_io_intr();
01f2e4ea 1543 unsigned int rq_work_to_do = budget;
18feb871 1544 unsigned int wq_work_to_do = ENIC_WQ_NAPI_BUDGET;
4c502549 1545 unsigned int work_done, rq_work_done = 0, wq_work_done;
2d6ddced 1546 int err;
01f2e4ea 1547
14747cd9
GV		 1548 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
1549 enic_wq_service, NULL);
1550
4c502549
EB		 1551 if (budget > 0)
1552 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
1553 rq_work_to_do, enic_rq_service, NULL);
01f2e4ea 1554
01f2e4ea
SF		 1555 /* Accumulate intr event credits for this polling
1556 * cycle. An intr event is the completion of a
1557 * a WQ or RQ packet.
1558 */
1559
1560 work_done = rq_work_done + wq_work_done;
1561
1562 if (work_done > 0)
717258ba 1563 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1564 work_done,
1565 0 /* don't unmask intr */,
1566 0 /* don't reset intr timer */);
1567
0eb26022 1568 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1569
2d6ddced
SF		 1570 /* Buffer allocation failed. Stay in polling
1571 * mode so we can try to fill the ring again.
1572 */
01f2e4ea 1573
2d6ddced
SF		 1574 if (err)
1575 rq_work_done = rq_work_to_do;
fc865d6b
GV		 1576 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1577 /* Call the function which refreshes the intr coalescing timer
1578 * value based on the traffic.
1579 */
1580 enic_calc_int_moderation(enic, &enic->rq[0]);
01f2e4ea 1581
9acfd1c0 1582 if ((rq_work_done < budget) && napi_complete_done(napi, rq_work_done)) {
01f2e4ea 1583
2d6ddced 1584 /* Some work done, but not enough to stay in polling,
88132f55 1585 * exit polling
01f2e4ea
SF		 1586 */
1587
fc865d6b
GV		 1588 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1589 enic_set_int_moderation(enic, &enic->rq[0]);
717258ba 1590 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea
SF		 1591 }
1592
1593 return rq_work_done;
1594}
1595
b6e97c13
GV		 1596#ifdef CONFIG_RFS_ACCEL
1597static void enic_free_rx_cpu_rmap(struct enic *enic)
1598{
1599 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
1600 enic->netdev->rx_cpu_rmap = NULL;
1601}
1602
1603static void enic_set_rx_cpu_rmap(struct enic *enic)
1604{
1605 int i, res;
1606
1607 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
1608 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
1609 if (unlikely(!enic->netdev->rx_cpu_rmap))
1610 return;
1611 for (i = 0; i < enic->rq_count; i++) {
1612 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
1613 enic->msix_entry[i].vector);
1614 if (unlikely(res)) {
1615 enic_free_rx_cpu_rmap(enic);
1616 return;
1617 }
1618 }
1619 }
1620}
1621
1622#else
1623
1624static void enic_free_rx_cpu_rmap(struct enic *enic)
1625{
1626}
1627
1628static void enic_set_rx_cpu_rmap(struct enic *enic)
1629{
1630}
1631
1632#endif /* CONFIG_RFS_ACCEL */
1633
4cfe8785
GV		 1634static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
1635{
1636 struct net_device *netdev = napi->dev;
1637 struct enic *enic = netdev_priv(netdev);
1638 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
1639 struct vnic_wq *wq = &enic->wq[wq_index];
1640 unsigned int cq;
1641 unsigned int intr;
18feb871 1642 unsigned int wq_work_to_do = ENIC_WQ_NAPI_BUDGET;
4cfe8785
GV		 1643 unsigned int wq_work_done;
1644 unsigned int wq_irq;
1645
1646 wq_irq = wq->index;
1647 cq = enic_cq_wq(enic, wq_irq);
1648 intr = enic_msix_wq_intr(enic, wq_irq);
1649 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
1650 enic_wq_service, NULL);
1651
1652 vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
1653 0 /* don't unmask intr */,
1654 1 /* reset intr timer */);
1655 if (!wq_work_done) {
1656 napi_complete(napi);
1657 vnic_intr_unmask(&enic->intr[intr]);
f41281d0 1658 return 0;
4cfe8785
GV		 1659 }
1660
f41281d0 1661 return budget;
4cfe8785
GV		 1662}
1663
1664static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
01f2e4ea 1665{
717258ba
VK		 1666 struct net_device *netdev = napi->dev;
1667 struct enic *enic = netdev_priv(netdev);
1668 unsigned int rq = (napi - &enic->napi[0]);
1669 unsigned int cq = enic_cq_rq(enic, rq);
1670 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea 1671 unsigned int work_to_do = budget;
4c502549 1672 unsigned int work_done = 0;
2d6ddced 1673 int err;
01f2e4ea
SF		 1674
1675 /* Service RQ
1676 */
1677
4c502549
EB		 1678 if (budget > 0)
1679 work_done = vnic_cq_service(&enic->cq[cq],
1680 work_to_do, enic_rq_service, NULL);
01f2e4ea 1681
2d6ddced
SF		 1682 /* Return intr event credits for this polling
1683 * cycle. An intr event is the completion of a
1684 * RQ packet.
1685 */
01f2e4ea 1686
2d6ddced 1687 if (work_done > 0)
717258ba 1688 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1689 work_done,
1690 0 /* don't unmask intr */,
1691 0 /* don't reset intr timer */);
01f2e4ea 1692
0eb26022 1693 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF		 1694
1695 /* Buffer allocation failed. Stay in polling mode
1696 * so we can try to fill the ring again.
1697 */
1698
1699 if (err)
1700 work_done = work_to_do;
7c2ce6e6 1701 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
fc865d6b
GV		 1702 /* Call the function which refreshes the intr coalescing timer
1703 * value based on the traffic.
7c2ce6e6
SS		 1704 */
1705 enic_calc_int_moderation(enic, &enic->rq[rq]);
2d6ddced 1706
9acfd1c0 1707 if ((work_done < budget) && napi_complete_done(napi, work_done)) {
2d6ddced
SF		 1708
1709 /* Some work done, but not enough to stay in polling,
88132f55 1710 * exit polling
01f2e4ea
SF		 1711 */
1712
7c2ce6e6
SS		 1713 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1714 enic_set_int_moderation(enic, &enic->rq[rq]);
717258ba 1715 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea
SF		 1716 }
1717
1718 return work_done;
1719}
1720
e99e88a9 1721static void enic_notify_timer(struct timer_list *t)
01f2e4ea 1722{
e99e88a9 1723 struct enic *enic = from_timer(enic, t, notify_timer);
01f2e4ea
SF		 1724
1725 enic_notify_check(enic);
1726
25f0a061
SF		 1727 mod_timer(&enic->notify_timer,
1728 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF		 1729}
1730
1731static void enic_free_intr(struct enic *enic)
1732{
1733 struct net_device *netdev = enic->netdev;
1734 unsigned int i;
1735
b6e97c13 1736 enic_free_rx_cpu_rmap(enic);
01f2e4ea
SF		 1737 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1738 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF		 1739 free_irq(enic->pdev->irq, netdev);
1740 break;
8f4d248c
SF		 1741 case VNIC_DEV_INTR_MODE_MSI:
1742 free_irq(enic->pdev->irq, enic);
1743 break;
01f2e4ea
SF		 1744 case VNIC_DEV_INTR_MODE_MSIX:
1745 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1746 if (enic->msix[i].requested)
1747 free_irq(enic->msix_entry[i].vector,
1748 enic->msix[i].devid);
1749 break;
1750 default:
1751 break;
1752 }
1753}
1754
1755static int enic_request_intr(struct enic *enic)
1756{
1757 struct net_device *netdev = enic->netdev;
717258ba 1758 unsigned int i, intr;
01f2e4ea
SF		 1759 int err = 0;
1760
b6e97c13 1761 enic_set_rx_cpu_rmap(enic);
01f2e4ea
SF		 1762 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1763
1764 case VNIC_DEV_INTR_MODE_INTX:
1765
1766 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1767 IRQF_SHARED, netdev->name, netdev);
1768 break;
1769
1770 case VNIC_DEV_INTR_MODE_MSI:
1771
1772 err = request_irq(enic->pdev->irq, enic_isr_msi,
1773 0, netdev->name, enic);
1774 break;
1775
1776 case VNIC_DEV_INTR_MODE_MSIX:
1777
717258ba
VK		 1778 for (i = 0; i < enic->rq_count; i++) {
1779 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC		 1780 snprintf(enic->msix[intr].devname,
1781 sizeof(enic->msix[intr].devname),
7044f429 1782 "%s-rx-%u", netdev->name, i);
4cfe8785 1783 enic->msix[intr].isr = enic_isr_msix;
717258ba
VK		 1784 enic->msix[intr].devid = &enic->napi[i];
1785 }
01f2e4ea 1786
717258ba 1787 for (i = 0; i < enic->wq_count; i++) {
4cfe8785
GV		 1788 int wq = enic_cq_wq(enic, i);
1789
717258ba 1790 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC		 1791 snprintf(enic->msix[intr].devname,
1792 sizeof(enic->msix[intr].devname),
7044f429 1793 "%s-tx-%u", netdev->name, i);
4cfe8785
GV		 1794 enic->msix[intr].isr = enic_isr_msix;
1795 enic->msix[intr].devid = &enic->napi[wq];
717258ba 1796 }
01f2e4ea 1797
717258ba 1798 intr = enic_msix_err_intr(enic);
4505f40a
DC		 1799 snprintf(enic->msix[intr].devname,
1800 sizeof(enic->msix[intr].devname),
7044f429 1801 "%s-err", netdev->name);
717258ba
VK		 1802 enic->msix[intr].isr = enic_isr_msix_err;
1803 enic->msix[intr].devid = enic;
01f2e4ea 1804
717258ba 1805 intr = enic_msix_notify_intr(enic);
4505f40a
DC		 1806 snprintf(enic->msix[intr].devname,
1807 sizeof(enic->msix[intr].devname),
7044f429 1808 "%s-notify", netdev->name);
717258ba
VK		 1809 enic->msix[intr].isr = enic_isr_msix_notify;
1810 enic->msix[intr].devid = enic;
1811
1812 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1813 enic->msix[i].requested = 0;
01f2e4ea 1814
717258ba 1815 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF		 1816 err = request_irq(enic->msix_entry[i].vector,
1817 enic->msix[i].isr, 0,
1818 enic->msix[i].devname,
1819 enic->msix[i].devid);
1820 if (err) {
1821 enic_free_intr(enic);
1822 break;
1823 }
1824 enic->msix[i].requested = 1;
1825 }
1826
1827 break;
1828
1829 default:
1830 break;
1831 }
1832
1833 return err;
1834}
1835
b3d18d19
SF		 1836static void enic_synchronize_irqs(struct enic *enic)
1837{
1838 unsigned int i;
1839
1840 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1841 case VNIC_DEV_INTR_MODE_INTX:
1842 case VNIC_DEV_INTR_MODE_MSI:
1843 synchronize_irq(enic->pdev->irq);
1844 break;
1845 case VNIC_DEV_INTR_MODE_MSIX:
1846 for (i = 0; i < enic->intr_count; i++)
1847 synchronize_irq(enic->msix_entry[i].vector);
1848 break;
1849 default:
1850 break;
1851 }
1852}
1853
7c2ce6e6
SS		 1854static void enic_set_rx_coal_setting(struct enic *enic)
1855{
1856 unsigned int speed;
1857 int index = -1;
1858 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1859
7c2ce6e6
SS		 1860 /* 1. Read the link speed from fw
1861 * 2. Pick the default range for the speed
1862 * 3. Update it in enic->rx_coalesce_setting
1863 */
1864 speed = vnic_dev_port_speed(enic->vdev);
1865 if (ENIC_LINK_SPEED_10G < speed)
1866 index = ENIC_LINK_40G_INDEX;
1867 else if (ENIC_LINK_SPEED_4G < speed)
1868 index = ENIC_LINK_10G_INDEX;
1869 else
1870 index = ENIC_LINK_4G_INDEX;
1871
1872 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
1873 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
1874 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
1875
1876 /* Start with the value provided by UCSM */
1877 for (index = 0; index < enic->rq_count; index++)
1878 enic->cq[index].cur_rx_coal_timeval =
1879 enic->config.intr_timer_usec;
1880
1881 rx_coal->use_adaptive_rx_coalesce = 1;
1882}
1883
383ab92f 1884static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF		 1885{
1886 int err;
1887
8e091340 1888 spin_lock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1889 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1890 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK		 1891 err = vnic_dev_notify_set(enic->vdev,
1892 enic_legacy_notify_intr());
01f2e4ea
SF		 1893 break;
1894 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1895 err = vnic_dev_notify_set(enic->vdev,
1896 enic_msix_notify_intr(enic));
01f2e4ea
SF		 1897 break;
1898 default:
1899 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1900 break;
1901 }
8e091340 1902 spin_unlock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1903
1904 return err;
1905}
1906
1907static void enic_notify_timer_start(struct enic *enic)
1908{
1909 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1910 case VNIC_DEV_INTR_MODE_MSI:
1911 mod_timer(&enic->notify_timer, jiffies);
1912 break;
1913 default:
1914 /* Using intr for notification for INTx/MSI-X */
1915 break;
6403eab1 1916 }
01f2e4ea
SF		 1917}
1918
1919/* rtnl lock is held, process context */
1920static int enic_open(struct net_device *netdev)
1921{
1922 struct enic *enic = netdev_priv(netdev);
1923 unsigned int i;
1924 int err;
1925
4b75a442
SF		 1926 err = enic_request_intr(enic);
1927 if (err) {
a7a79deb 1928 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF		 1929 return err;
1930 }
322cf7e3
GV		 1931 enic_init_affinity_hint(enic);
1932 enic_set_affinity_hint(enic);
4b75a442 1933
383ab92f 1934 err = enic_dev_notify_set(enic);
4b75a442 1935 if (err) {
a7a79deb
VK		 1936 netdev_err(netdev,
1937 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF		 1938 goto err_out_free_intr;
1939 }
1940
01f2e4ea 1941 for (i = 0; i < enic->rq_count; i++) {
e8588e26
GV		 1942 /* enable rq before updating rq desc */
1943 vnic_rq_enable(&enic->rq[i]);
0eb26022 1944 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF		 1945 /* Need at least one buffer on ring to get going */
1946 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1947 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1948 err = -ENOMEM;
9dac6232 1949 goto err_out_free_rq;
01f2e4ea
SF		 1950 }
1951 }
1952
1953 for (i = 0; i < enic->wq_count; i++)
1954 vnic_wq_enable(&enic->wq[i]);
01f2e4ea 1955
7335903c 1956 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1957 enic_dev_add_station_addr(enic);
3f192795 1958
319d7e84 1959 enic_set_rx_mode(netdev);
01f2e4ea 1960
822473b6 1961 netif_tx_wake_all_queues(netdev);
717258ba 1962
7a655c63 1963 for (i = 0; i < enic->rq_count; i++)
717258ba 1964 napi_enable(&enic->napi[i]);
7a655c63 1965
4cfe8785
GV		 1966 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1967 for (i = 0; i < enic->wq_count; i++)
1968 napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
383ab92f 1969 enic_dev_enable(enic);
01f2e4ea
SF		 1970
1971 for (i = 0; i < enic->intr_count; i++)
1972 vnic_intr_unmask(&enic->intr[i]);
1973
1974 enic_notify_timer_start(enic);
a145df23 1975 enic_rfs_flw_tbl_init(enic);
01f2e4ea
SF		 1976
1977 return 0;
4b75a442 1978
9dac6232 1979err_out_free_rq:
e8588e26
GV		 1980 for (i = 0; i < enic->rq_count; i++) {
1981 err = vnic_rq_disable(&enic->rq[i]);
1982 if (err)
1983 return err;
9dac6232 1984 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
e8588e26 1985 }
383ab92f 1986 enic_dev_notify_unset(enic);
4b75a442 1987err_out_free_intr:
322cf7e3 1988 enic_unset_affinity_hint(enic);
4b75a442
SF		 1989 enic_free_intr(enic);
1990
1991 return err;
01f2e4ea
SF		 1992}
1993
1994/* rtnl lock is held, process context */
1995static int enic_stop(struct net_device *netdev)
1996{
1997 struct enic *enic = netdev_priv(netdev);
1998 unsigned int i;
1999 int err;
2000
29046f9b 2001 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 2002 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK		 2003 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
2004 }
b3d18d19
SF		 2005
2006 enic_synchronize_irqs(enic);
2007
01f2e4ea 2008 del_timer_sync(&enic->notify_timer);
a145df23 2009 enic_rfs_flw_tbl_free(enic);
01f2e4ea 2010
383ab92f 2011 enic_dev_disable(enic);
717258ba 2012
7a655c63 2013 for (i = 0; i < enic->rq_count; i++)
717258ba
VK		 2014 napi_disable(&enic->napi[i]);
2015
b3d18d19
SF		 2016 netif_carrier_off(netdev);
2017 netif_tx_disable(netdev);
4cfe8785
GV		 2018 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2019 for (i = 0; i < enic->wq_count; i++)
2020 napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
3f192795 2021
7335903c 2022 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 2023 enic_dev_del_station_addr(enic);
f8bd9091 2024
01f2e4ea
SF		 2025 for (i = 0; i < enic->wq_count; i++) {
2026 err = vnic_wq_disable(&enic->wq[i]);
2027 if (err)
2028 return err;
2029 }
2030 for (i = 0; i < enic->rq_count; i++) {
2031 err = vnic_rq_disable(&enic->rq[i]);
2032 if (err)
2033 return err;
2034 }
2035
383ab92f 2036 enic_dev_notify_unset(enic);
322cf7e3 2037 enic_unset_affinity_hint(enic);
4b75a442
SF		 2038 enic_free_intr(enic);
2039
01f2e4ea
SF		 2040 for (i = 0; i < enic->wq_count; i++)
2041 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
2042 for (i = 0; i < enic->rq_count; i++)
2043 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
2044 for (i = 0; i < enic->cq_count; i++)
2045 vnic_cq_clean(&enic->cq[i]);
2046 for (i = 0; i < enic->intr_count; i++)
2047 vnic_intr_clean(&enic->intr[i]);
2048
2049 return 0;
2050}
2051
2052static int enic_change_mtu(struct net_device *netdev, int new_mtu)
2053{
2054 struct enic *enic = netdev_priv(netdev);
2055 int running = netif_running(netdev);
2056
7335903c 2057 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP		 2058 return -EOPNOTSUPP;
2059
01f2e4ea
SF		 2060 if (running)
2061 enic_stop(netdev);
2062
01f2e4ea
SF		 2063 netdev->mtu = new_mtu;
2064
2065 if (netdev->mtu > enic->port_mtu)
a7a79deb
VK		 2066 netdev_warn(netdev,
2067 "interface MTU (%d) set higher than port MTU (%d)\n",
2068 netdev->mtu, enic->port_mtu);
01f2e4ea
SF		 2069
2070 if (running)
2071 enic_open(netdev);
2072
2073 return 0;
2074}
2075
c97c894d
RP		 2076static void enic_change_mtu_work(struct work_struct *work)
2077{
2078 struct enic *enic = container_of(work, struct enic, change_mtu_work);
2079 struct net_device *netdev = enic->netdev;
2080 int new_mtu = vnic_dev_mtu(enic->vdev);
2081 int err;
2082 unsigned int i;
2083
2084 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
2085
2086 rtnl_lock();
2087
2088 /* Stop RQ */
2089 del_timer_sync(&enic->notify_timer);
2090
2091 for (i = 0; i < enic->rq_count; i++)
2092 napi_disable(&enic->napi[i]);
2093
2094 vnic_intr_mask(&enic->intr[0]);
2095 enic_synchronize_irqs(enic);
2096 err = vnic_rq_disable(&enic->rq[0]);
2097 if (err) {
e057590b 2098 rtnl_unlock();
c97c894d
RP		 2099 netdev_err(netdev, "Unable to disable RQ.\n");
2100 return;
2101 }
2102 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
2103 vnic_cq_clean(&enic->cq[0]);
2104 vnic_intr_clean(&enic->intr[0]);
2105
2106 /* Fill RQ with new_mtu-sized buffers */
2107 netdev->mtu = new_mtu;
2108 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
2109 /* Need at least one buffer on ring to get going */
2110 if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
e057590b 2111 rtnl_unlock();
c97c894d
RP		 2112 netdev_err(netdev, "Unable to alloc receive buffers.\n");
2113 return;
2114 }
2115
2116 /* Start RQ */
2117 vnic_rq_enable(&enic->rq[0]);
2118 napi_enable(&enic->napi[0]);
2119 vnic_intr_unmask(&enic->intr[0]);
2120 enic_notify_timer_start(enic);
2121
2122 rtnl_unlock();
2123
2124 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
2125}
2126
01f2e4ea
SF		 2127#ifdef CONFIG_NET_POLL_CONTROLLER
2128static void enic_poll_controller(struct net_device *netdev)
2129{
2130 struct enic *enic = netdev_priv(netdev);
2131 struct vnic_dev *vdev = enic->vdev;
717258ba 2132 unsigned int i, intr;
01f2e4ea
SF		 2133
2134 switch (vnic_dev_get_intr_mode(vdev)) {
2135 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 2136 for (i = 0; i < enic->rq_count; i++) {
2137 intr = enic_msix_rq_intr(enic, i);
4cfe8785
GV		 2138 enic_isr_msix(enic->msix_entry[intr].vector,
2139 &enic->napi[i]);
717258ba 2140 }
b880a954
VK		 2141
2142 for (i = 0; i < enic->wq_count; i++) {
2143 intr = enic_msix_wq_intr(enic, i);
4cfe8785
GV		 2144 enic_isr_msix(enic->msix_entry[intr].vector,
2145 &enic->napi[enic_cq_wq(enic, i)]);
b880a954
VK		 2146 }
2147
01f2e4ea
SF		 2148 break;
2149 case VNIC_DEV_INTR_MODE_MSI:
2150 enic_isr_msi(enic->pdev->irq, enic);
2151 break;
2152 case VNIC_DEV_INTR_MODE_INTX:
2153 enic_isr_legacy(enic->pdev->irq, netdev);
2154 break;
2155 default:
2156 break;
2157 }
2158}
2159#endif
2160
2161static int enic_dev_wait(struct vnic_dev *vdev,
2162 int (*start)(struct vnic_dev *, int),
2163 int (*finished)(struct vnic_dev *, int *),
2164 int arg)
2165{
2166 unsigned long time;
2167 int done;
2168 int err;
2169
2170 BUG_ON(in_interrupt());
2171
2172 err = start(vdev, arg);
2173 if (err)
2174 return err;
2175
2176 /* Wait for func to complete...2 seconds max
2177 */
2178
2179 time = jiffies + (HZ * 2);
2180 do {
2181
2182 err = finished(vdev, &done);
2183 if (err)
2184 return err;
2185
2186 if (done)
2187 return 0;
2188
2189 schedule_timeout_uninterruptible(HZ / 10);
2190
2191 } while (time_after(time, jiffies));
2192
2193 return -ETIMEDOUT;
2194}
2195
2196static int enic_dev_open(struct enic *enic)
2197{
2198 int err;
5de0c022 2199 u32 flags = CMD_OPENF_IG_DESCCACHE;
01f2e4ea
SF		 2200
2201 err = enic_dev_wait(enic->vdev, vnic_dev_open,
5de0c022 2202 vnic_dev_open_done, flags);
01f2e4ea 2203 if (err)
a7a79deb
VK		 2204 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
2205 err);
01f2e4ea
SF		 2206
2207 return err;
2208}
2209
937317c7
GV		 2210static int enic_dev_soft_reset(struct enic *enic)
2211{
2212 int err;
2213
2214 err = enic_dev_wait(enic->vdev, vnic_dev_soft_reset,
2215 vnic_dev_soft_reset_done, 0);
2216 if (err)
2217 netdev_err(enic->netdev, "vNIC soft reset failed, err %d\n",
2218 err);
2219
2220 return err;
2221}
2222
99ef5639 2223static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF		 2224{
2225 int err;
2226
99ef5639
VK		 2227 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
2228 vnic_dev_hang_reset_done, 0);
01f2e4ea 2229 if (err)
a7a79deb
VK		 2230 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
2231 err);
01f2e4ea
SF		 2232
2233 return err;
2234}
2235
4f675eb2 2236int __enic_set_rsskey(struct enic *enic)
717258ba 2237{
c33d23c2 2238 union vnic_rss_key *rss_key_buf_va;
1f4f067f 2239 dma_addr_t rss_key_buf_pa;
c33d23c2 2240 int i, kidx, bidx, err;
717258ba 2241
c33d23c2
ED		 2242 rss_key_buf_va = pci_zalloc_consistent(enic->pdev,
2243 sizeof(union vnic_rss_key),
2244 &rss_key_buf_pa);
717258ba
VK		 2245 if (!rss_key_buf_va)
2246 return -ENOMEM;
2247
c33d23c2
ED		 2248 for (i = 0; i < ENIC_RSS_LEN; i++) {
2249 kidx = i / ENIC_RSS_BYTES_PER_KEY;
2250 bidx = i % ENIC_RSS_BYTES_PER_KEY;
4f675eb2 2251 rss_key_buf_va->key[kidx].b[bidx] = enic->rss_key[i];
c33d23c2 2252 }
8e091340 2253 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 2254 err = enic_set_rss_key(enic,
2255 rss_key_buf_pa,
2256 sizeof(union vnic_rss_key));
8e091340 2257 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 2258
2259 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
2260 rss_key_buf_va, rss_key_buf_pa);
2261
2262 return err;
2263}
2264
4f675eb2
GV		 2265static int enic_set_rsskey(struct enic *enic)
2266{
2267 netdev_rss_key_fill(enic->rss_key, ENIC_RSS_LEN);
2268
2269 return __enic_set_rsskey(enic);
2270}
2271
717258ba
VK		 2272static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
2273{
1f4f067f 2274 dma_addr_t rss_cpu_buf_pa;
717258ba
VK		 2275 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
2276 unsigned int i;
2277 int err;
2278
2279 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
2280 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
2281 if (!rss_cpu_buf_va)
2282 return -ENOMEM;
2283
2284 for (i = 0; i < (1 << rss_hash_bits); i++)
2285 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
2286
8e091340 2287 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 2288 err = enic_set_rss_cpu(enic,
2289 rss_cpu_buf_pa,
2290 sizeof(union vnic_rss_cpu));
8e091340 2291 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 2292
2293 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
2294 rss_cpu_buf_va, rss_cpu_buf_pa);
2295
2296 return err;
2297}
2298
2299static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
2300 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 2301{
68f71708
SF		 2302 const u8 tso_ipid_split_en = 0;
2303 const u8 ig_vlan_strip_en = 1;
383ab92f 2304 int err;
68f71708 2305
717258ba
VK		 2306 /* Enable VLAN tag stripping.
2307 */
68f71708 2308
8e091340 2309 spin_lock_bh(&enic->devcmd_lock);
383ab92f 2310 err = enic_set_nic_cfg(enic,
68f71708
SF		 2311 rss_default_cpu, rss_hash_type,
2312 rss_hash_bits, rss_base_cpu,
2313 rss_enable, tso_ipid_split_en,
2314 ig_vlan_strip_en);
8e091340 2315 spin_unlock_bh(&enic->devcmd_lock);
383ab92f
VK		 2316
2317 return err;
2318}
2319
717258ba
VK		 2320static int enic_set_rss_nic_cfg(struct enic *enic)
2321{
2322 struct device *dev = enic_get_dev(enic);
2323 const u8 rss_default_cpu = 0;
48398b6e 2324 u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
717258ba
VK		 2325 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
2326 NIC_CFG_RSS_HASH_TYPE_IPV6 |
2327 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
2328 const u8 rss_hash_bits = 7;
2329 const u8 rss_base_cpu = 0;
2330 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
2331
48398b6e
GV		 2332 if (vnic_dev_capable_udp_rss(enic->vdev))
2333 rss_hash_type |= NIC_CFG_RSS_HASH_TYPE_UDP;
717258ba
VK		 2334 if (rss_enable) {
2335 if (!enic_set_rsskey(enic)) {
2336 if (enic_set_rsscpu(enic, rss_hash_bits)) {
2337 rss_enable = 0;
2338 dev_warn(dev, "RSS disabled, "
2339 "Failed to set RSS cpu indirection table.");
2340 }
2341 } else {
2342 rss_enable = 0;
2343 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
2344 }
2345 }
2346
2347 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
2348 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK		 2349}
2350
01f2e4ea
SF		 2351static void enic_reset(struct work_struct *work)
2352{
2353 struct enic *enic = container_of(work, struct enic, reset);
2354
2355 if (!netif_running(enic->netdev))
2356 return;
2357
2358 rtnl_lock();
2359
937317c7
GV		 2360 spin_lock(&enic->enic_api_lock);
2361 enic_stop(enic->netdev);
2362 enic_dev_soft_reset(enic);
2363 enic_reset_addr_lists(enic);
2364 enic_init_vnic_resources(enic);
2365 enic_set_rss_nic_cfg(enic);
2366 enic_dev_set_ig_vlan_rewrite_mode(enic);
2367 enic_open(enic->netdev);
2368 spin_unlock(&enic->enic_api_lock);
2369 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
2370
2371 rtnl_unlock();
2372}
2373
2374static void enic_tx_hang_reset(struct work_struct *work)
2375{
2376 struct enic *enic = container_of(work, struct enic, tx_hang_reset);
2377
2378 rtnl_lock();
2379
0b038566 2380 spin_lock(&enic->enic_api_lock);
383ab92f 2381 enic_dev_hang_notify(enic);
01f2e4ea 2382 enic_stop(enic->netdev);
99ef5639 2383 enic_dev_hang_reset(enic);
e0afe53f 2384 enic_reset_addr_lists(enic);
01f2e4ea 2385 enic_init_vnic_resources(enic);
717258ba 2386 enic_set_rss_nic_cfg(enic);
f8cac14a 2387 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 2388 enic_open(enic->netdev);
0b038566 2389 spin_unlock(&enic->enic_api_lock);
d765bb41 2390 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF		 2391
2392 rtnl_unlock();
2393}
2394
2395static int enic_set_intr_mode(struct enic *enic)
2396{
717258ba 2397 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 2398 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF		 2399 unsigned int i;
2400
2401 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 2402 * on system capabilities.
01f2e4ea
SF		 2403 *
2404 * Try MSI-X first
2405 *
2406 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
2407 * (the second to last INTR is used for WQ/RQ errors)
2408 * (the last INTR is used for notifications)
2409 */
2410
2411 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
2412 for (i = 0; i < n + m + 2; i++)
2413 enic->msix_entry[i].entry = i;
2414
717258ba
VK		 2415 /* Use multiple RQs if RSS is enabled
2416 */
2417
2418 if (ENIC_SETTING(enic, RSS) &&
2419 enic->config.intr_mode < 1 &&
01f2e4ea
SF		 2420 enic->rq_count >= n &&
2421 enic->wq_count >= m &&
2422 enic->cq_count >= n + m &&
717258ba 2423 enic->intr_count >= n + m + 2) {
01f2e4ea 2424
abbb6a37
AG		 2425 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2426 n + m + 2, n + m + 2) > 0) {
01f2e4ea 2427
717258ba
VK		 2428 enic->rq_count = n;
2429 enic->wq_count = m;
2430 enic->cq_count = n + m;
2431 enic->intr_count = n + m + 2;
01f2e4ea 2432
717258ba
VK		 2433 vnic_dev_set_intr_mode(enic->vdev,
2434 VNIC_DEV_INTR_MODE_MSIX);
2435
2436 return 0;
2437 }
2438 }
2439
2440 if (enic->config.intr_mode < 1 &&
2441 enic->rq_count >= 1 &&
2442 enic->wq_count >= m &&
2443 enic->cq_count >= 1 + m &&
2444 enic->intr_count >= 1 + m + 2) {
abbb6a37
AG		 2445 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2446 1 + m + 2, 1 + m + 2) > 0) {
717258ba
VK		 2447
2448 enic->rq_count = 1;
2449 enic->wq_count = m;
2450 enic->cq_count = 1 + m;
2451 enic->intr_count = 1 + m + 2;
2452
2453 vnic_dev_set_intr_mode(enic->vdev,
2454 VNIC_DEV_INTR_MODE_MSIX);
2455
2456 return 0;
2457 }
01f2e4ea
SF		 2458 }
2459
2460 /* Next try MSI
2461 *
2462 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
2463 */
2464
2465 if (enic->config.intr_mode < 2 &&
2466 enic->rq_count >= 1 &&
2467 enic->wq_count >= 1 &&
2468 enic->cq_count >= 2 &&
2469 enic->intr_count >= 1 &&
2470 !pci_enable_msi(enic->pdev)) {
2471
2472 enic->rq_count = 1;
2473 enic->wq_count = 1;
2474 enic->cq_count = 2;
2475 enic->intr_count = 1;
2476
2477 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
2478
2479 return 0;
2480 }
2481
2482 /* Next try INTx
2483 *
2484 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
2485 * (the first INTR is used for WQ/RQ)
2486 * (the second INTR is used for WQ/RQ errors)
2487 * (the last INTR is used for notifications)
2488 */
2489
2490 if (enic->config.intr_mode < 3 &&
2491 enic->rq_count >= 1 &&
2492 enic->wq_count >= 1 &&
2493 enic->cq_count >= 2 &&
2494 enic->intr_count >= 3) {
2495
2496 enic->rq_count = 1;
2497 enic->wq_count = 1;
2498 enic->cq_count = 2;
2499 enic->intr_count = 3;
2500
2501 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
2502
2503 return 0;
2504 }
2505
2506 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2507
2508 return -EINVAL;
2509}
2510
2511static void enic_clear_intr_mode(struct enic *enic)
2512{
2513 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2514 case VNIC_DEV_INTR_MODE_MSIX:
2515 pci_disable_msix(enic->pdev);
2516 break;
2517 case VNIC_DEV_INTR_MODE_MSI:
2518 pci_disable_msi(enic->pdev);
2519 break;
2520 default:
2521 break;
2522 }
2523
2524 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2525}
2526
f8bd9091
SF		 2527static const struct net_device_ops enic_netdev_dynamic_ops = {
2528 .ndo_open = enic_open,
2529 .ndo_stop = enic_stop,
2530 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2531 .ndo_get_stats64 = enic_get_stats,
f8bd9091 2532 .ndo_validate_addr = eth_validate_addr,
319d7e84 2533 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF		 2534 .ndo_set_mac_address = enic_set_mac_address_dynamic,
2535 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF		 2536 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2537 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2538 .ndo_tx_timeout = enic_tx_timeout,
2539 .ndo_set_vf_port = enic_set_vf_port,
2540 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 2541 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF		 2542#ifdef CONFIG_NET_POLL_CONTROLLER
2543 .ndo_poll_controller = enic_poll_controller,
2544#endif
a145df23
GV		 2545#ifdef CONFIG_RFS_ACCEL
2546 .ndo_rx_flow_steer = enic_rx_flow_steer,
2547#endif
257e7382
GV		 2548 .ndo_udp_tunnel_add = enic_udp_tunnel_add,
2549 .ndo_udp_tunnel_del = enic_udp_tunnel_del,
9c744d10 2550 .ndo_features_check = enic_features_check,
f8bd9091
SF		 2551};
2552
afe29f7a
SH		 2553static const struct net_device_ops enic_netdev_ops = {
2554 .ndo_open = enic_open,
2555 .ndo_stop = enic_stop,
00829823 2556 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2557 .ndo_get_stats64 = enic_get_stats,
afe29f7a 2558 .ndo_validate_addr = eth_validate_addr,
f8bd9091 2559 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 2560 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 2561 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH		 2562 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2563 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2564 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP		 2565 .ndo_set_vf_port = enic_set_vf_port,
2566 .ndo_get_vf_port = enic_get_vf_port,
2567 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH		 2568#ifdef CONFIG_NET_POLL_CONTROLLER
2569 .ndo_poll_controller = enic_poll_controller,
2570#endif
a145df23
GV		 2571#ifdef CONFIG_RFS_ACCEL
2572 .ndo_rx_flow_steer = enic_rx_flow_steer,
2573#endif
257e7382
GV		 2574 .ndo_udp_tunnel_add = enic_udp_tunnel_add,
2575 .ndo_udp_tunnel_del = enic_udp_tunnel_del,
9c744d10 2576 .ndo_features_check = enic_features_check,
afe29f7a
SH		 2577};
2578
2fdba388 2579static void enic_dev_deinit(struct enic *enic)
6fdfa970 2580{
717258ba
VK		 2581 unsigned int i;
2582
14747cd9
GV		 2583 for (i = 0; i < enic->rq_count; i++) {
2584 napi_hash_del(&enic->napi[i]);
717258ba 2585 netif_napi_del(&enic->napi[i]);
14747cd9 2586 }
4cfe8785
GV		 2587 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2588 for (i = 0; i < enic->wq_count; i++)
2589 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
717258ba 2590
6fdfa970
SF		 2591 enic_free_vnic_resources(enic);
2592 enic_clear_intr_mode(enic);
322cf7e3 2593 enic_free_affinity_hint(enic);
6fdfa970
SF		 2594}
2595
3f255dcc
GV		 2596static void enic_kdump_kernel_config(struct enic *enic)
2597{
2598 if (is_kdump_kernel()) {
2599 dev_info(enic_get_dev(enic), "Running from within kdump kernel. Using minimal resources\n");
2600 enic->rq_count = 1;
2601 enic->wq_count = 1;
2602 enic->config.rq_desc_count = ENIC_MIN_RQ_DESCS;
2603 enic->config.wq_desc_count = ENIC_MIN_WQ_DESCS;
2604 enic->config.mtu = min_t(u16, 1500, enic->config.mtu);
2605 }
2606}
2607
2fdba388 2608static int enic_dev_init(struct enic *enic)
6fdfa970 2609{
a7a79deb 2610 struct device *dev = enic_get_dev(enic);
6fdfa970 2611 struct net_device *netdev = enic->netdev;
717258ba 2612 unsigned int i;
6fdfa970
SF		 2613 int err;
2614
ea7ea65a
VK		 2615 /* Get interrupt coalesce timer info */
2616 err = enic_dev_intr_coal_timer_info(enic);
2617 if (err) {
2618 dev_warn(dev, "Using default conversion factor for "
2619 "interrupt coalesce timer\n");
2620 vnic_dev_intr_coal_timer_info_default(enic->vdev);
2621 }
2622
6fdfa970
SF		 2623 /* Get vNIC configuration
2624 */
2625
2626 err = enic_get_vnic_config(enic);
2627 if (err) {
a7a79deb 2628 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF		 2629 return err;
2630 }
2631
2632 /* Get available resource counts
2633 */
2634
2635 enic_get_res_counts(enic);
2636
3f255dcc
GV		 2637 /* modify resource count if we are in kdump_kernel
2638 */
2639 enic_kdump_kernel_config(enic);
2640
6fdfa970
SF		 2641 /* Set interrupt mode based on resource counts and system
2642 * capabilities
2643 */
2644
2645 err = enic_set_intr_mode(enic);
2646 if (err) {
a7a79deb
VK		 2647 dev_err(dev, "Failed to set intr mode based on resource "
2648 "counts and system capabilities, aborting\n");
6fdfa970
SF		 2649 return err;
2650 }
2651
2652 /* Allocate and configure vNIC resources
2653 */
2654
2655 err = enic_alloc_vnic_resources(enic);
2656 if (err) {
a7a79deb 2657 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF		 2658 goto err_out_free_vnic_resources;
2659 }
2660
2661 enic_init_vnic_resources(enic);
2662
717258ba 2663 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2664 if (err) {
a7a79deb 2665 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF		 2666 goto err_out_free_vnic_resources;
2667 }
2668
2669 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2670 default:
717258ba 2671 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
6fdfa970
SF		 2672 break;
2673 case VNIC_DEV_INTR_MODE_MSIX:
14747cd9 2674 for (i = 0; i < enic->rq_count; i++) {
717258ba 2675 netif_napi_add(netdev, &enic->napi[i],
4cfe8785 2676 enic_poll_msix_rq, NAPI_POLL_WEIGHT);
14747cd9 2677 }
4cfe8785
GV		 2678 for (i = 0; i < enic->wq_count; i++)
2679 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
2680 enic_poll_msix_wq, NAPI_POLL_WEIGHT);
6fdfa970
SF		 2681 break;
2682 }
2683
2684 return 0;
2685
2686err_out_free_vnic_resources:
322cf7e3 2687 enic_free_affinity_hint(enic);
6fdfa970
SF		 2688 enic_clear_intr_mode(enic);
2689 enic_free_vnic_resources(enic);
2690
2691 return err;
2692}
2693
27e6c7d3
SF		 2694static void enic_iounmap(struct enic *enic)
2695{
2696 unsigned int i;
2697
2698 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2699 if (enic->bar[i].vaddr)
2700 iounmap(enic->bar[i].vaddr);
2701}
2702
1dd06ae8 2703static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2704{
a7a79deb 2705 struct device *dev = &pdev->dev;
01f2e4ea
SF		 2706 struct net_device *netdev;
2707 struct enic *enic;
2708 int using_dac = 0;
2709 unsigned int i;
2710 int err;
8749b427
RP		 2711#ifdef CONFIG_PCI_IOV
2712 int pos = 0;
2713#endif
b67f231d 2714 int num_pps = 1;
01f2e4ea 2715
01f2e4ea
SF		 2716 /* Allocate net device structure and initialize. Private
2717 * instance data is initialized to zero.
2718 */
2719
822473b6 2720 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2721 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2722 if (!netdev)
01f2e4ea 2723 return -ENOMEM;
01f2e4ea 2724
01f2e4ea
SF		 2725 pci_set_drvdata(pdev, netdev);
2726
2727 SET_NETDEV_DEV(netdev, &pdev->dev);
2728
2729 enic = netdev_priv(netdev);
2730 enic->netdev = netdev;
2731 enic->pdev = pdev;
2732
2733 /* Setup PCI resources
2734 */
2735
29046f9b 2736 err = pci_enable_device_mem(pdev);
01f2e4ea 2737 if (err) {
a7a79deb 2738 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF		 2739 goto err_out_free_netdev;
2740 }
2741
2742 err = pci_request_regions(pdev, DRV_NAME);
2743 if (err) {
a7a79deb 2744 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF		 2745 goto err_out_disable_device;
2746 }
2747
2748 pci_set_master(pdev);
2749
2750 /* Query PCI controller on system for DMA addressing
624dbf55 2751 * limitation for the device. Try 64-bit first, and
01f2e4ea
SF		 2752 * fail to 32-bit.
2753 */
2754
624dbf55 2755 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2756 if (err) {
284901a9 2757 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2758 if (err) {
a7a79deb 2759 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF		 2760 goto err_out_release_regions;
2761 }
284901a9 2762 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2763 if (err) {
a7a79deb
VK		 2764 dev_err(dev, "Unable to obtain %u-bit DMA "
2765 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF		 2766 goto err_out_release_regions;
2767 }
2768 } else {
624dbf55 2769 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2770 if (err) {
a7a79deb 2771 dev_err(dev, "Unable to obtain %u-bit DMA "
624dbf55 2772 "for consistent allocations, aborting\n", 64);
01f2e4ea
SF		 2773 goto err_out_release_regions;
2774 }
2775 using_dac = 1;
2776 }
2777
27e6c7d3 2778 /* Map vNIC resources from BAR0-5
01f2e4ea
SF		 2779 */
2780
27e6c7d3
SF		 2781 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2782 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2783 continue;
2784 enic->bar[i].len = pci_resource_len(pdev, i);
2785 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2786 if (!enic->bar[i].vaddr) {
a7a79deb 2787 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF		 2788 err = -ENODEV;
2789 goto err_out_iounmap;
2790 }
2791 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF		 2792 }
2793
2794 /* Register vNIC device
2795 */
2796
27e6c7d3
SF		 2797 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2798 ARRAY_SIZE(enic->bar));
01f2e4ea 2799 if (!enic->vdev) {
a7a79deb 2800 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF		 2801 err = -ENODEV;
2802 goto err_out_iounmap;
2803 }
2804
373fb087
GV		 2805 err = vnic_devcmd_init(enic->vdev);
2806
2807 if (err)
2808 goto err_out_vnic_unregister;
2809
8749b427
RP		 2810#ifdef CONFIG_PCI_IOV
2811 /* Get number of subvnics */
2812 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2813 if (pos) {
2814 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2815 &enic->num_vfs);
8749b427
RP		 2816 if (enic->num_vfs) {
2817 err = pci_enable_sriov(pdev, enic->num_vfs);
2818 if (err) {
2819 dev_err(dev, "SRIOV enable failed, aborting."
2820 " pci_enable_sriov() returned %d\n",
2821 err);
2822 goto err_out_vnic_unregister;
2823 }
2824 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2825 num_pps = enic->num_vfs;
8749b427
RP		 2826 }
2827 }
8749b427 2828#endif
ca2b721d 2829
3f192795 2830 /* Allocate structure for port profiles */
a1de2219 2831 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2832 if (!enic->pp) {
3f192795 2833 err = -ENOMEM;
ca2b721d 2834 goto err_out_disable_sriov_pp;
3f192795
RP		 2835 }
2836
01f2e4ea
SF		 2837 /* Issue device open to get device in known state
2838 */
2839
2840 err = enic_dev_open(enic);
2841 if (err) {
a7a79deb 2842 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2843 goto err_out_disable_sriov;
01f2e4ea
SF		 2844 }
2845
69161425
VK		 2846 /* Setup devcmd lock
2847 */
2848
2849 spin_lock_init(&enic->devcmd_lock);
0b038566 2850 spin_lock_init(&enic->enic_api_lock);
69161425
VK		 2851
2852 /*
2853 * Set ingress vlan rewrite mode before vnic initialization
2854 */
2855
2856 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2857 if (err) {
2858 dev_err(dev,
2859 "Failed to set ingress vlan rewrite mode, aborting.\n");
2860 goto err_out_dev_close;
2861 }
2862
01f2e4ea
SF		 2863 /* Issue device init to initialize the vnic-to-switch link.
2864 * We'll start with carrier off and wait for link UP
2865 * notification later to turn on carrier. We don't need
2866 * to wait here for the vnic-to-switch link initialization
2867 * to complete; link UP notification is the indication that
2868 * the process is complete.
2869 */
2870
2871 netif_carrier_off(netdev);
2872
a7a79deb
VK		 2873 /* Do not call dev_init for a dynamic vnic.
2874 * For a dynamic vnic, init_prov_info will be
2875 * called later by an upper layer.
2876 */
2877
2b68c181 2878 if (!enic_is_dynamic(enic)) {
f8bd9091
SF		 2879 err = vnic_dev_init(enic->vdev, 0);
2880 if (err) {
a7a79deb 2881 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF		 2882 goto err_out_dev_close;
2883 }
01f2e4ea
SF		 2884 }
2885
6fdfa970 2886 err = enic_dev_init(enic);
01f2e4ea 2887 if (err) {
a7a79deb 2888 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF		 2889 goto err_out_dev_close;
2890 }
2891
822473b6 2892 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2893 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2894
383ab92f 2895 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF		 2896 */
2897
e99e88a9 2898 timer_setup(&enic->notify_timer, enic_notify_timer, 0);
01f2e4ea 2899
7c2ce6e6 2900 enic_set_rx_coal_setting(enic);
01f2e4ea 2901 INIT_WORK(&enic->reset, enic_reset);
937317c7 2902 INIT_WORK(&enic->tx_hang_reset, enic_tx_hang_reset);
c97c894d 2903 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF		 2904
2905 for (i = 0; i < enic->wq_count; i++)
2906 spin_lock_init(&enic->wq_lock[i]);
2907
01f2e4ea
SF		 2908 /* Register net device
2909 */
2910
2911 enic->port_mtu = enic->config.mtu;
2912 (void)enic_change_mtu(netdev, enic->port_mtu);
2913
2914 err = enic_set_mac_addr(netdev, enic->mac_addr);
2915 if (err) {
a7a79deb 2916 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2917 goto err_out_dev_deinit;
01f2e4ea
SF		 2918 }
2919
7c844599 2920 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
7c2ce6e6
SS		 2921 /* rx coalesce time already got initialized. This gets used
2922 * if adaptive coal is turned off
2923 */
7c844599
SF		 2924 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2925
7335903c 2926 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF		 2927 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2928 else
2929 netdev->netdev_ops = &enic_netdev_ops;
2930
01f2e4ea 2931 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2932 enic_set_ethtool_ops(netdev);
01f2e4ea 2933
f646968f 2934 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2935 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2936 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK		 2937 enic->loop_enable = 1;
2938 enic->loop_tag = enic->config.loop_tag;
2939 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2940 }
01f2e4ea 2941 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2942 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2943 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2944 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2945 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2946 if (ENIC_SETTING(enic, RSS))
2947 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM		 2948 if (ENIC_SETTING(enic, RXCSUM))
2949 netdev->hw_features |= NETIF_F_RXCSUM;
257e7382
GV		 2950 if (ENIC_SETTING(enic, VXLAN)) {
2951 u64 patch_level;
d1179094 2952 u64 a1 = 0;
257e7382
GV		 2953
2954 netdev->hw_enc_features |= NETIF_F_RXCSUM |
2955 NETIF_F_TSO |
d1179094 2956 NETIF_F_TSO6 |
257e7382
GV		 2957 NETIF_F_TSO_ECN |
2958 NETIF_F_GSO_UDP_TUNNEL |
2959 NETIF_F_HW_CSUM |
2960 NETIF_F_GSO_UDP_TUNNEL_CSUM;
2961 netdev->hw_features |= netdev->hw_enc_features;
2962 /* get bit mask from hw about supported offload bit level
2963 * BIT(0) = fw supports patch_level 0
2964 * fcoe bit = encap
2965 * fcoe_fc_crc_ok = outer csum ok
2966 * BIT(1) = always set by fw
2967 * BIT(2) = fw supports patch_level 2
2968 * BIT(0) in rss_hash = encap
2969 * BIT(1,2) in rss_hash = outer_ip_csum_ok/
2970 * outer_tcp_csum_ok
2971 * used in enic_rq_indicate_buf
2972 */
2973 err = vnic_dev_get_supported_feature_ver(enic->vdev,
2974 VIC_FEATURE_VXLAN,
d1179094 2975 &patch_level, &a1);
257e7382
GV		 2976 if (err)
2977 patch_level = 0;
d1179094 2978 enic->vxlan.flags = (u8)a1;
257e7382
GV		 2979 /* mask bits that are supported by driver
2980 */
2981 patch_level &= BIT_ULL(0) | BIT_ULL(2);
2982 patch_level = fls(patch_level);
2983 patch_level = patch_level ? patch_level - 1 : 0;
2984 enic->vxlan.patch_level = patch_level;
2985 }
5ec8f9b8
MM		 2986
2987 netdev->features |= netdev->hw_features;
e7600449 2988 netdev->vlan_features |= netdev->features;
5ec8f9b8 2989
a145df23
GV		 2990#ifdef CONFIG_RFS_ACCEL
2991 netdev->hw_features |= NETIF_F_NTUPLE;
2992#endif
2993
01f2e4ea
SF		 2994 if (using_dac)
2995 netdev->features |= NETIF_F_HIGHDMA;
2996
01789349
JP		 2997 netdev->priv_flags |= IFF_UNICAST_FLT;
2998
44770e11
JW		 2999 /* MTU range: 68 - 9000 */
3000 netdev->min_mtu = ENIC_MIN_MTU;
3001 netdev->max_mtu = ENIC_MAX_MTU;
3002
01f2e4ea
SF		 3003 err = register_netdev(netdev);
3004 if (err) {
a7a79deb 3005 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 3006 goto err_out_dev_deinit;
01f2e4ea 3007 }
a03bb56e 3008 enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
01f2e4ea
SF		 3009
3010 return 0;
3011
6fdfa970
SF		 3012err_out_dev_deinit:
3013 enic_dev_deinit(enic);
01f2e4ea
SF		 3014err_out_dev_close:
3015 vnic_dev_close(enic->vdev);
8749b427 3016err_out_disable_sriov:
ca2b721d
RP		 3017 kfree(enic->pp);
3018err_out_disable_sriov_pp:
8749b427
RP		 3019#ifdef CONFIG_PCI_IOV
3020 if (enic_sriov_enabled(enic)) {
3021 pci_disable_sriov(pdev);
3022 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
3023 }
8749b427 3024#endif
1a69205c 3025err_out_vnic_unregister:
35d87e33 3026 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF		 3027err_out_iounmap:
3028 enic_iounmap(enic);
3029err_out_release_regions:
3030 pci_release_regions(pdev);
3031err_out_disable_device:
3032 pci_disable_device(pdev);
3033err_out_free_netdev:
01f2e4ea
SF		 3034 free_netdev(netdev);
3035
3036 return err;
3037}
3038
854de92f 3039static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF		 3040{
3041 struct net_device *netdev = pci_get_drvdata(pdev);
3042
3043 if (netdev) {
3044 struct enic *enic = netdev_priv(netdev);
3045
23f333a2 3046 cancel_work_sync(&enic->reset);
c97c894d 3047 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 3048 unregister_netdev(netdev);
6fdfa970 3049 enic_dev_deinit(enic);
01f2e4ea 3050 vnic_dev_close(enic->vdev);
8749b427
RP		 3051#ifdef CONFIG_PCI_IOV
3052 if (enic_sriov_enabled(enic)) {
3053 pci_disable_sriov(pdev);
3054 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
3055 }
3056#endif
3f192795 3057 kfree(enic->pp);
01f2e4ea
SF		 3058 vnic_dev_unregister(enic->vdev);
3059 enic_iounmap(enic);
3060 pci_release_regions(pdev);
3061 pci_disable_device(pdev);
01f2e4ea
SF		 3062 free_netdev(netdev);
3063 }
3064}
3065
3066static struct pci_driver enic_driver = {
3067 .name = DRV_NAME,
3068 .id_table = enic_id_table,
3069 .probe = enic_probe,
854de92f 3070 .remove = enic_remove,
01f2e4ea
SF		 3071};
3072
3073static int __init enic_init_module(void)
3074{
a7a79deb 3075 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
01f2e4ea
SF		 3076
3077 return pci_register_driver(&enic_driver);
3078}
3079
3080static void __exit enic_cleanup_module(void)
3081{
3082 pci_unregister_driver(&enic_driver);
3083}
3084
3085module_init(enic_init_module);
3086module_exit(enic_cleanup_module);
Linux 6.x block layer and io_uring tree(s)