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ipv4: frags: handle possible skb truesize change
[linux-block.git] / drivers / net / ethernet / cisco / enic / enic_main.c
CommitLineData
01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF		 27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF		 32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF		 34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
7c2ce6e6 41#include <linux/ktime.h>
322cf7e3 42#include <linux/numa.h>
b6e97c13
GV		 43#ifdef CONFIG_RFS_ACCEL
44#include <linux/cpu_rmap.h>
45#endif
3f255dcc 46#include <linux/crash_dump.h>
7a655c63 47#include <net/busy_poll.h>
257e7382 48#include <net/vxlan.h>
01f2e4ea
SF		 49
50#include "cq_enet_desc.h"
51#include "vnic_dev.h"
52#include "vnic_intr.h"
53#include "vnic_stats.h"
f8bd9091 54#include "vnic_vic.h"
01f2e4ea
SF		 55#include "enic_res.h"
56#include "enic.h"
51987461 57#include "enic_dev.h"
b3abfbd2 58#include "enic_pp.h"
a145df23 59#include "enic_clsf.h"
01f2e4ea
SF		 60
61#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
SF		 62#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
63#define MAX_TSO (1 << 16)
64#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
65
66#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 67#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 68#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea 69
a03bb56e
GV		 70#define RX_COPYBREAK_DEFAULT 256
71
01f2e4ea 72/* Supported devices */
9baa3c34 73static const struct pci_device_id enic_id_table[] = {
ea0d7d91 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 76 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF		 77 { 0, } /* end of table */
78};
79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_VERSION);
84MODULE_DEVICE_TABLE(pci, enic_id_table);
85
7c2ce6e6
SS		 86#define ENIC_LARGE_PKT_THRESHOLD 1000
87#define ENIC_MAX_COALESCE_TIMERS 10
88/* Interrupt moderation table, which will be used to decide the
89 * coalescing timer values
90 * {rx_rate in Mbps, mapping percentage of the range}
91 */
57ae84a0 92static struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
7c2ce6e6
SS		 93 {4000, 0},
94 {4400, 10},
95 {5060, 20},
96 {5230, 30},
97 {5540, 40},
98 {5820, 50},
99 {6120, 60},
100 {6435, 70},
101 {6745, 80},
102 {7000, 90},
103 {0xFFFFFFFF, 100}
104};
105
106/* This table helps the driver to pick different ranges for rx coalescing
107 * timer depending on the link speed.
108 */
57ae84a0 109static struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
7c2ce6e6
SS		 110 {0, 0}, /* 0 - 4 Gbps */
111 {0, 3}, /* 4 - 10 Gbps */
112 {3, 6}, /* 10 - 40 Gbps */
113};
114
322cf7e3
GV		 115static void enic_init_affinity_hint(struct enic *enic)
116{
117 int numa_node = dev_to_node(&enic->pdev->dev);
118 int i;
119
120 for (i = 0; i < enic->intr_count; i++) {
121 if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i) ||
122 (enic->msix[i].affinity_mask &&
123 !cpumask_empty(enic->msix[i].affinity_mask)))
124 continue;
125 if (zalloc_cpumask_var(&enic->msix[i].affinity_mask,
126 GFP_KERNEL))
127 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
128 enic->msix[i].affinity_mask);
129 }
130}
131
132static void enic_free_affinity_hint(struct enic *enic)
133{
134 int i;
135
136 for (i = 0; i < enic->intr_count; i++) {
137 if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i))
138 continue;
139 free_cpumask_var(enic->msix[i].affinity_mask);
140 }
141}
142
143static void enic_set_affinity_hint(struct enic *enic)
144{
145 int i;
146 int err;
147
148 for (i = 0; i < enic->intr_count; i++) {
149 if (enic_is_err_intr(enic, i) ||
150 enic_is_notify_intr(enic, i) ||
151 !enic->msix[i].affinity_mask ||
152 cpumask_empty(enic->msix[i].affinity_mask))
153 continue;
154 err = irq_set_affinity_hint(enic->msix_entry[i].vector,
155 enic->msix[i].affinity_mask);
156 if (err)
157 netdev_warn(enic->netdev, "irq_set_affinity_hint failed, err %d\n",
158 err);
159 }
160
161 for (i = 0; i < enic->wq_count; i++) {
162 int wq_intr = enic_msix_wq_intr(enic, i);
163
164 if (enic->msix[wq_intr].affinity_mask &&
165 !cpumask_empty(enic->msix[wq_intr].affinity_mask))
166 netif_set_xps_queue(enic->netdev,
167 enic->msix[wq_intr].affinity_mask,
168 i);
169 }
170}
171
172static void enic_unset_affinity_hint(struct enic *enic)
173{
174 int i;
175
176 for (i = 0; i < enic->intr_count; i++)
177 irq_set_affinity_hint(enic->msix_entry[i].vector, NULL);
178}
179
257e7382
GV		 180static void enic_udp_tunnel_add(struct net_device *netdev,
181 struct udp_tunnel_info *ti)
182{
183 struct enic *enic = netdev_priv(netdev);
184 __be16 port = ti->port;
185 int err;
186
187 spin_lock_bh(&enic->devcmd_lock);
188
189 if (ti->type != UDP_TUNNEL_TYPE_VXLAN) {
190 netdev_info(netdev, "udp_tnl: only vxlan tunnel offload supported");
191 goto error;
192 }
193
d1179094
GV		 194 switch (ti->sa_family) {
195 case AF_INET6:
196 if (!(enic->vxlan.flags & ENIC_VXLAN_OUTER_IPV6)) {
197 netdev_info(netdev, "vxlan: only IPv4 offload supported");
198 goto error;
199 }
200 /* Fall through */
201 case AF_INET:
202 break;
203 default:
257e7382
GV		 204 goto error;
205 }
206
207 if (enic->vxlan.vxlan_udp_port_number) {
208 if (ntohs(port) == enic->vxlan.vxlan_udp_port_number)
209 netdev_warn(netdev, "vxlan: udp port already offloaded");
210 else
211 netdev_info(netdev, "vxlan: offload supported for only one UDP port");
212
213 goto error;
214 }
7e24c642
GV		 215 if ((vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ) != 1) &&
216 !(enic->vxlan.flags & ENIC_VXLAN_MULTI_WQ)) {
217 netdev_info(netdev, "vxlan: vxlan offload with multi wq not supported on this adapter");
218 goto error;
219 }
257e7382
GV		 220
221 err = vnic_dev_overlay_offload_cfg(enic->vdev,
222 OVERLAY_CFG_VXLAN_PORT_UPDATE,
223 ntohs(port));
224 if (err)
225 goto error;
226
227 err = vnic_dev_overlay_offload_ctrl(enic->vdev, OVERLAY_FEATURE_VXLAN,
228 enic->vxlan.patch_level);
229 if (err)
230 goto error;
231
232 enic->vxlan.vxlan_udp_port_number = ntohs(port);
233
234 netdev_info(netdev, "vxlan fw-vers-%d: offload enabled for udp port: %d, sa_family: %d ",
235 (int)enic->vxlan.patch_level, ntohs(port), ti->sa_family);
236
237 goto unlock;
238
239error:
240 netdev_info(netdev, "failed to offload udp port: %d, sa_family: %d, type: %d",
241 ntohs(port), ti->sa_family, ti->type);
242unlock:
243 spin_unlock_bh(&enic->devcmd_lock);
244}
245
246static void enic_udp_tunnel_del(struct net_device *netdev,
247 struct udp_tunnel_info *ti)
248{
249 struct enic *enic = netdev_priv(netdev);
250 int err;
251
252 spin_lock_bh(&enic->devcmd_lock);
253
ce3db6aa
GV		 254 if ((ntohs(ti->port) != enic->vxlan.vxlan_udp_port_number) ||
255 ti->type != UDP_TUNNEL_TYPE_VXLAN) {
257e7382
GV		 256 netdev_info(netdev, "udp_tnl: port:%d, sa_family: %d, type: %d not offloaded",
257 ntohs(ti->port), ti->sa_family, ti->type);
258 goto unlock;
259 }
260
261 err = vnic_dev_overlay_offload_ctrl(enic->vdev, OVERLAY_FEATURE_VXLAN,
262 OVERLAY_OFFLOAD_DISABLE);
263 if (err) {
264 netdev_err(netdev, "vxlan: del offload udp port: %d failed",
265 ntohs(ti->port));
266 goto unlock;
267 }
268
269 enic->vxlan.vxlan_udp_port_number = 0;
270
271 netdev_info(netdev, "vxlan: del offload udp port %d, family %d\n",
272 ntohs(ti->port), ti->sa_family);
273
274unlock:
275 spin_unlock_bh(&enic->devcmd_lock);
276}
277
9c744d10
GV		 278static netdev_features_t enic_features_check(struct sk_buff *skb,
279 struct net_device *dev,
280 netdev_features_t features)
281{
282 const struct ethhdr *eth = (struct ethhdr *)skb_inner_mac_header(skb);
283 struct enic *enic = netdev_priv(dev);
284 struct udphdr *udph;
285 u16 port = 0;
d1179094 286 u8 proto;
9c744d10
GV		 287
288 if (!skb->encapsulation)
289 return features;
290
291 features = vxlan_features_check(skb, features);
292
d1179094
GV		 293 switch (vlan_get_protocol(skb)) {
294 case htons(ETH_P_IPV6):
295 if (!(enic->vxlan.flags & ENIC_VXLAN_OUTER_IPV6))
296 goto out;
297 proto = ipv6_hdr(skb)->nexthdr;
298 break;
299 case htons(ETH_P_IP):
300 proto = ip_hdr(skb)->protocol;
301 break;
302 default:
9c744d10 303 goto out;
d1179094 304 }
9c744d10 305
d1179094
GV		 306 switch (eth->h_proto) {
307 case ntohs(ETH_P_IPV6):
308 if (!(enic->vxlan.flags & ENIC_VXLAN_INNER_IPV6))
309 goto out;
310 /* Fall through */
311 case ntohs(ETH_P_IP):
312 break;
313 default:
9c744d10 314 goto out;
d1179094 315 }
9c744d10 316
9c744d10
GV		 317
318 if (proto == IPPROTO_UDP) {
319 udph = udp_hdr(skb);
320 port = be16_to_cpu(udph->dest);
321 }
322
323 /* HW supports offload of only one UDP port. Remove CSUM and GSO MASK
324 * for other UDP port tunnels
325 */
326 if (port != enic->vxlan.vxlan_udp_port_number)
327 goto out;
328
329 return features;
330
331out:
332 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
333}
334
3f192795 335int enic_is_dynamic(struct enic *enic)
f8bd9091
SF		 336{
337 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
338}
339
8749b427
RP		 340int enic_sriov_enabled(struct enic *enic)
341{
342 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
343}
344
3a4adef5
RP		 345static int enic_is_sriov_vf(struct enic *enic)
346{
347 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
348}
349
889d13f5
RP		 350int enic_is_valid_vf(struct enic *enic, int vf)
351{
352#ifdef CONFIG_PCI_IOV
353 return vf >= 0 && vf < enic->num_vfs;
354#else
355 return 0;
356#endif
357}
358
01f2e4ea
SF		 359static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
360{
361 struct enic *enic = vnic_dev_priv(wq->vdev);
362
363 if (buf->sop)
364 pci_unmap_single(enic->pdev, buf->dma_addr,
365 buf->len, PCI_DMA_TODEVICE);
366 else
367 pci_unmap_page(enic->pdev, buf->dma_addr,
368 buf->len, PCI_DMA_TODEVICE);
369
370 if (buf->os_buf)
371 dev_kfree_skb_any(buf->os_buf);
372}
373
374static void enic_wq_free_buf(struct vnic_wq *wq,
375 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
376{
377 enic_free_wq_buf(wq, buf);
378}
379
380static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
381 u8 type, u16 q_number, u16 completed_index, void *opaque)
382{
383 struct enic *enic = vnic_dev_priv(vdev);
384
385 spin_lock(&enic->wq_lock[q_number]);
386
387 vnic_wq_service(&enic->wq[q_number], cq_desc,
388 completed_index, enic_wq_free_buf,
389 opaque);
390
822473b6 391 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
SF		 392 vnic_wq_desc_avail(&enic->wq[q_number]) >=
393 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 394 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF		 395
396 spin_unlock(&enic->wq_lock[q_number]);
397
398 return 0;
399}
400
cc809237 401static bool enic_log_q_error(struct enic *enic)
01f2e4ea
SF		 402{
403 unsigned int i;
404 u32 error_status;
cc809237 405 bool err = false;
01f2e4ea
SF		 406
407 for (i = 0; i < enic->wq_count; i++) {
408 error_status = vnic_wq_error_status(&enic->wq[i]);
cc809237 409 err |= error_status;
01f2e4ea 410 if (error_status)
a7a79deb
VK		 411 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
412 i, error_status);
01f2e4ea
SF		 413 }
414
415 for (i = 0; i < enic->rq_count; i++) {
416 error_status = vnic_rq_error_status(&enic->rq[i]);
cc809237 417 err |= error_status;
01f2e4ea 418 if (error_status)
a7a79deb
VK		 419 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
420 i, error_status);
01f2e4ea 421 }
cc809237
GV		 422
423 return err;
01f2e4ea
SF		 424}
425
383ab92f 426static void enic_msglvl_check(struct enic *enic)
01f2e4ea 427{
383ab92f 428 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 429
383ab92f 430 if (msg_enable != enic->msg_enable) {
a7a79deb
VK		 431 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
432 enic->msg_enable, msg_enable);
383ab92f 433 enic->msg_enable = msg_enable;
01f2e4ea
SF		 434 }
435}
436
437static void enic_mtu_check(struct enic *enic)
438{
439 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 440 struct net_device *netdev = enic->netdev;
01f2e4ea 441
491598a4 442 if (mtu && mtu != enic->port_mtu) {
7c844599 443 enic->port_mtu = mtu;
7335903c 444 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP		 445 mtu = max_t(int, ENIC_MIN_MTU,
446 min_t(int, ENIC_MAX_MTU, mtu));
447 if (mtu != netdev->mtu)
448 schedule_work(&enic->change_mtu_work);
449 } else {
450 if (mtu < netdev->mtu)
451 netdev_warn(netdev,
452 "interface MTU (%d) set higher "
453 "than switch port MTU (%d)\n",
454 netdev->mtu, mtu);
455 }
01f2e4ea
SF		 456 }
457}
458
383ab92f 459static void enic_link_check(struct enic *enic)
01f2e4ea 460{
383ab92f
VK		 461 int link_status = vnic_dev_link_status(enic->vdev);
462 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 463
383ab92f 464 if (link_status && !carrier_ok) {
a7a79deb 465 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK		 466 netif_carrier_on(enic->netdev);
467 } else if (!link_status && carrier_ok) {
a7a79deb 468 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 469 netif_carrier_off(enic->netdev);
01f2e4ea
SF		 470 }
471}
472
473static void enic_notify_check(struct enic *enic)
474{
475 enic_msglvl_check(enic);
476 enic_mtu_check(enic);
477 enic_link_check(enic);
478}
479
480#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
481
482static irqreturn_t enic_isr_legacy(int irq, void *data)
483{
484 struct net_device *netdev = data;
485 struct enic *enic = netdev_priv(netdev);
717258ba
VK		 486 unsigned int io_intr = enic_legacy_io_intr();
487 unsigned int err_intr = enic_legacy_err_intr();
488 unsigned int notify_intr = enic_legacy_notify_intr();
01f2e4ea
SF		 489 u32 pba;
490
717258ba 491 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
SF		 492
493 pba = vnic_intr_legacy_pba(enic->legacy_pba);
494 if (!pba) {
717258ba 495 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 496 return IRQ_NONE; /* not our interrupt */
497 }
498
717258ba 499 if (ENIC_TEST_INTR(pba, notify_intr)) {
01f2e4ea 500 enic_notify_check(enic);
2b0c2e2d 501 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
ed8af6b2 502 }
01f2e4ea 503
717258ba
VK		 504 if (ENIC_TEST_INTR(pba, err_intr)) {
505 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
SF		 506 enic_log_q_error(enic);
507 /* schedule recovery from WQ/RQ error */
508 schedule_work(&enic->reset);
509 return IRQ_HANDLED;
510 }
511
db40b3f5
GV		 512 if (ENIC_TEST_INTR(pba, io_intr))
513 napi_schedule_irqoff(&enic->napi[0]);
514 else
717258ba 515 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 516
517 return IRQ_HANDLED;
518}
519
520static irqreturn_t enic_isr_msi(int irq, void *data)
521{
522 struct enic *enic = data;
523
524 /* With MSI, there is no sharing of interrupts, so this is
525 * our interrupt and there is no need to ack it. The device
526 * is not providing per-vector masking, so the OS will not
527 * write to PCI config space to mask/unmask the interrupt.
528 * We're using mask_on_assertion for MSI, so the device
529 * automatically masks the interrupt when the interrupt is
530 * generated. Later, when exiting polling, the interrupt
531 * will be unmasked (see enic_poll).
532 *
533 * Also, the device uses the same PCIe Traffic Class (TC)
534 * for Memory Write data and MSI, so there are no ordering
535 * issues; the MSI will always arrive at the Root Complex
536 * _after_ corresponding Memory Writes (i.e. descriptor
537 * writes).
538 */
539
db40b3f5 540 napi_schedule_irqoff(&enic->napi[0]);
01f2e4ea
SF		 541
542 return IRQ_HANDLED;
543}
544
4cfe8785 545static irqreturn_t enic_isr_msix(int irq, void *data)
01f2e4ea 546{
717258ba 547 struct napi_struct *napi = data;
01f2e4ea 548
db40b3f5 549 napi_schedule_irqoff(napi);
01f2e4ea
SF		 550
551 return IRQ_HANDLED;
552}
553
01f2e4ea
SF		 554static irqreturn_t enic_isr_msix_err(int irq, void *data)
555{
556 struct enic *enic = data;
717258ba 557 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 558
717258ba 559 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 560
cc809237
GV		 561 if (enic_log_q_error(enic))
562 /* schedule recovery from WQ/RQ error */
563 schedule_work(&enic->reset);
01f2e4ea
SF		 564
565 return IRQ_HANDLED;
566}
567
568static irqreturn_t enic_isr_msix_notify(int irq, void *data)
569{
570 struct enic *enic = data;
717258ba 571 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea
SF		 572
573 enic_notify_check(enic);
2b0c2e2d 574 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea
SF		 575
576 return IRQ_HANDLED;
577}
578
065df159
GV		 579static int enic_queue_wq_skb_cont(struct enic *enic, struct vnic_wq *wq,
580 struct sk_buff *skb, unsigned int len_left,
581 int loopback)
01f2e4ea 582{
9e903e08 583 const skb_frag_t *frag;
065df159 584 dma_addr_t dma_addr;
01f2e4ea
SF		 585
586 /* Queue additional data fragments */
587 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 588 len_left -= skb_frag_size(frag);
065df159
GV		 589 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 0,
590 skb_frag_size(frag),
591 DMA_TO_DEVICE);
592 if (unlikely(enic_dma_map_check(enic, dma_addr)))
593 return -ENOMEM;
594 enic_queue_wq_desc_cont(wq, skb, dma_addr, skb_frag_size(frag),
595 (len_left == 0), /* EOP? */
596 loopback);
01f2e4ea 597 }
065df159
GV		 598
599 return 0;
01f2e4ea
SF		 600}
601
065df159
GV		 602static int enic_queue_wq_skb_vlan(struct enic *enic, struct vnic_wq *wq,
603 struct sk_buff *skb, int vlan_tag_insert,
604 unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 605{
606 unsigned int head_len = skb_headlen(skb);
607 unsigned int len_left = skb->len - head_len;
608 int eop = (len_left == 0);
065df159
GV		 609 dma_addr_t dma_addr;
610 int err = 0;
611
612 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
613 PCI_DMA_TODEVICE);
614 if (unlikely(enic_dma_map_check(enic, dma_addr)))
615 return -ENOMEM;
01f2e4ea 616
ea0d7d91
SF		 617 /* Queue the main skb fragment. The fragments are no larger
618 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
619 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
620 * per fragment is queued.
621 */
065df159
GV		 622 enic_queue_wq_desc(wq, skb, dma_addr, head_len, vlan_tag_insert,
623 vlan_tag, eop, loopback);
01f2e4ea
SF		 624
625 if (!eop)
065df159
GV		 626 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
627
628 return err;
01f2e4ea
SF		 629}
630
065df159
GV		 631static int enic_queue_wq_skb_csum_l4(struct enic *enic, struct vnic_wq *wq,
632 struct sk_buff *skb, int vlan_tag_insert,
633 unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 634{
635 unsigned int head_len = skb_headlen(skb);
636 unsigned int len_left = skb->len - head_len;
0d0b1672 637 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF		 638 unsigned int csum_offset = hdr_len + skb->csum_offset;
639 int eop = (len_left == 0);
065df159
GV		 640 dma_addr_t dma_addr;
641 int err = 0;
642
643 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
644 PCI_DMA_TODEVICE);
645 if (unlikely(enic_dma_map_check(enic, dma_addr)))
646 return -ENOMEM;
01f2e4ea 647
ea0d7d91
SF		 648 /* Queue the main skb fragment. The fragments are no larger
649 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
650 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
651 * per fragment is queued.
652 */
065df159
GV		 653 enic_queue_wq_desc_csum_l4(wq, skb, dma_addr, head_len, csum_offset,
654 hdr_len, vlan_tag_insert, vlan_tag, eop,
655 loopback);
01f2e4ea
SF		 656
657 if (!eop)
065df159
GV		 658 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
659
660 return err;
01f2e4ea
SF		 661}
662
9c744d10 663static void enic_preload_tcp_csum_encap(struct sk_buff *skb)
01f2e4ea 664{
4a464a2b
GV		 665 const struct ethhdr *eth = (struct ethhdr *)skb_inner_mac_header(skb);
666
667 switch (eth->h_proto) {
668 case ntohs(ETH_P_IP):
9c744d10
GV		 669 inner_ip_hdr(skb)->check = 0;
670 inner_tcp_hdr(skb)->check =
671 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
672 inner_ip_hdr(skb)->daddr, 0,
673 IPPROTO_TCP, 0);
4a464a2b
GV		 674 break;
675 case ntohs(ETH_P_IPV6):
676 inner_tcp_hdr(skb)->check =
677 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
678 &inner_ipv6_hdr(skb)->daddr, 0,
679 IPPROTO_TCP, 0);
680 break;
681 default:
682 WARN_ONCE(1, "Non ipv4/ipv6 inner pkt for encap offload");
683 break;
9c744d10
GV		 684 }
685}
01f2e4ea 686
9c744d10
GV		 687static void enic_preload_tcp_csum(struct sk_buff *skb)
688{
01f2e4ea
SF		 689 /* Preload TCP csum field with IP pseudo hdr calculated
690 * with IP length set to zero. HW will later add in length
691 * to each TCP segment resulting from the TSO.
692 */
693
09640e63 694 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF		 695 ip_hdr(skb)->check = 0;
696 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
697 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 698 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
01f2e4ea
SF		 699 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
700 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
701 }
9c744d10
GV		 702}
703
704static int enic_queue_wq_skb_tso(struct enic *enic, struct vnic_wq *wq,
705 struct sk_buff *skb, unsigned int mss,
706 int vlan_tag_insert, unsigned int vlan_tag,
707 int loopback)
708{
709 unsigned int frag_len_left = skb_headlen(skb);
710 unsigned int len_left = skb->len - frag_len_left;
711 int eop = (len_left == 0);
712 unsigned int offset = 0;
713 unsigned int hdr_len;
714 dma_addr_t dma_addr;
715 unsigned int len;
716 skb_frag_t *frag;
717
718 if (skb->encapsulation) {
719 hdr_len = skb_inner_transport_header(skb) - skb->data;
720 hdr_len += inner_tcp_hdrlen(skb);
721 enic_preload_tcp_csum_encap(skb);
722 } else {
723 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
724 enic_preload_tcp_csum(skb);
725 }
01f2e4ea 726
ea0d7d91
SF		 727 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
728 * for the main skb fragment
729 */
730 while (frag_len_left) {
731 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
065df159
GV		 732 dma_addr = pci_map_single(enic->pdev, skb->data + offset, len,
733 PCI_DMA_TODEVICE);
734 if (unlikely(enic_dma_map_check(enic, dma_addr)))
735 return -ENOMEM;
736 enic_queue_wq_desc_tso(wq, skb, dma_addr, len, mss, hdr_len,
737 vlan_tag_insert, vlan_tag,
738 eop && (len == frag_len_left), loopback);
ea0d7d91
SF		 739 frag_len_left -= len;
740 offset += len;
741 }
01f2e4ea 742
ea0d7d91 743 if (eop)
065df159 744 return 0;
ea0d7d91
SF		 745
746 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
747 * for additional data fragments
748 */
749 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED		 750 len_left -= skb_frag_size(frag);
751 frag_len_left = skb_frag_size(frag);
4bf5adbf 752 offset = 0;
ea0d7d91
SF		 753
754 while (frag_len_left) {
755 len = min(frag_len_left,
756 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC		 757 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
758 offset, len,
5d6bcdfe 759 DMA_TO_DEVICE);
065df159
GV		 760 if (unlikely(enic_dma_map_check(enic, dma_addr)))
761 return -ENOMEM;
762 enic_queue_wq_desc_cont(wq, skb, dma_addr, len,
763 (len_left == 0) &&
764 (len == frag_len_left),/*EOP*/
765 loopback);
ea0d7d91
SF		 766 frag_len_left -= len;
767 offset += len;
768 }
769 }
065df159
GV		 770
771 return 0;
01f2e4ea
SF		 772}
773
9c744d10
GV		 774static inline int enic_queue_wq_skb_encap(struct enic *enic, struct vnic_wq *wq,
775 struct sk_buff *skb,
776 int vlan_tag_insert,
777 unsigned int vlan_tag, int loopback)
778{
779 unsigned int head_len = skb_headlen(skb);
780 unsigned int len_left = skb->len - head_len;
781 /* Hardware will overwrite the checksum fields, calculating from
782 * scratch and ignoring the value placed by software.
783 * Offload mode = 00
784 * mss[2], mss[1], mss[0] bits are set
785 */
786 unsigned int mss_or_csum = 7;
787 int eop = (len_left == 0);
788 dma_addr_t dma_addr;
789 int err = 0;
790
791 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
792 PCI_DMA_TODEVICE);
793 if (unlikely(enic_dma_map_check(enic, dma_addr)))
794 return -ENOMEM;
795
796 enic_queue_wq_desc_ex(wq, skb, dma_addr, head_len, mss_or_csum, 0,
797 vlan_tag_insert, vlan_tag,
798 WQ_ENET_OFFLOAD_MODE_CSUM, eop, 1 /* SOP */, eop,
799 loopback);
800 if (!eop)
801 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
802
803 return err;
804}
805
01f2e4ea
SF		 806static inline void enic_queue_wq_skb(struct enic *enic,
807 struct vnic_wq *wq, struct sk_buff *skb)
808{
809 unsigned int mss = skb_shinfo(skb)->gso_size;
810 unsigned int vlan_tag = 0;
811 int vlan_tag_insert = 0;
1825aca6 812 int loopback = 0;
065df159 813 int err;
01f2e4ea 814
df8a39de 815 if (skb_vlan_tag_present(skb)) {
01f2e4ea
SF		 816 /* VLAN tag from trunking driver */
817 vlan_tag_insert = 1;
df8a39de 818 vlan_tag = skb_vlan_tag_get(skb);
1825aca6
VK		 819 } else if (enic->loop_enable) {
820 vlan_tag = enic->loop_tag;
821 loopback = 1;
01f2e4ea
SF		 822 }
823
824 if (mss)
065df159
GV		 825 err = enic_queue_wq_skb_tso(enic, wq, skb, mss,
826 vlan_tag_insert, vlan_tag,
827 loopback);
9c744d10
GV		 828 else if (skb->encapsulation)
829 err = enic_queue_wq_skb_encap(enic, wq, skb, vlan_tag_insert,
830 vlan_tag, loopback);
01f2e4ea 831 else if (skb->ip_summed == CHECKSUM_PARTIAL)
065df159
GV		 832 err = enic_queue_wq_skb_csum_l4(enic, wq, skb, vlan_tag_insert,
833 vlan_tag, loopback);
01f2e4ea 834 else
065df159
GV		 835 err = enic_queue_wq_skb_vlan(enic, wq, skb, vlan_tag_insert,
836 vlan_tag, loopback);
837 if (unlikely(err)) {
838 struct vnic_wq_buf *buf;
839
840 buf = wq->to_use->prev;
841 /* while not EOP of previous pkt && queue not empty.
842 * For all non EOP bufs, os_buf is NULL.
843 */
844 while (!buf->os_buf && (buf->next != wq->to_clean)) {
845 enic_free_wq_buf(wq, buf);
846 wq->ring.desc_avail++;
847 buf = buf->prev;
848 }
849 wq->to_use = buf->next;
850 dev_kfree_skb(skb);
851 }
01f2e4ea
SF		 852}
853
ed8af6b2 854/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 855static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 856 struct net_device *netdev)
01f2e4ea
SF		 857{
858 struct enic *enic = netdev_priv(netdev);
822473b6 859 struct vnic_wq *wq;
822473b6 860 unsigned int txq_map;
f8e34d24 861 struct netdev_queue *txq;
01f2e4ea
SF		 862
863 if (skb->len <= 0) {
98d8a65d 864 dev_kfree_skb_any(skb);
01f2e4ea
SF		 865 return NETDEV_TX_OK;
866 }
867
822473b6 868 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
869 wq = &enic->wq[txq_map];
f8e34d24 870 txq = netdev_get_tx_queue(netdev, txq_map);
822473b6 871
01f2e4ea
SF		 872 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
873 * which is very likely. In the off chance it's going to take
874 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
875 */
876
877 if (skb_shinfo(skb)->gso_size == 0 &&
878 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
879 skb_linearize(skb)) {
98d8a65d 880 dev_kfree_skb_any(skb);
01f2e4ea
SF		 881 return NETDEV_TX_OK;
882 }
883
78e2045d 884 spin_lock(&enic->wq_lock[txq_map]);
01f2e4ea 885
ea0d7d91
SF		 886 if (vnic_wq_desc_avail(wq) <
887 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
f8e34d24 888 netif_tx_stop_queue(txq);
01f2e4ea 889 /* This is a hard error, log it */
a7a79deb 890 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
78e2045d 891 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 892 return NETDEV_TX_BUSY;
893 }
894
895 enic_queue_wq_skb(enic, wq, skb);
896
ea0d7d91 897 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
f8e34d24 898 netif_tx_stop_queue(txq);
fb7516d4 899 skb_tx_timestamp(skb);
f8e34d24
GV		 900 if (!skb->xmit_more || netif_xmit_stopped(txq))
901 vnic_wq_doorbell(wq);
01f2e4ea 902
78e2045d 903 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 904
905 return NETDEV_TX_OK;
906}
907
908/* dev_base_lock rwlock held, nominally process context */
bc1f4470 909static void enic_get_stats(struct net_device *netdev,
910 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF		 911{
912 struct enic *enic = netdev_priv(netdev);
913 struct vnic_stats *stats;
19b596bd 914 int err;
01f2e4ea 915
19b596bd
GV		 916 err = enic_dev_stats_dump(enic, &stats);
917 /* return only when pci_zalloc_consistent fails in vnic_dev_stats_dump
918 * For other failures, like devcmd failure, we return previously
919 * recorded stats.
920 */
921 if (err == -ENOMEM)
bc1f4470 922 return;
01f2e4ea 923
25f0a061
SF		 924 net_stats->tx_packets = stats->tx.tx_frames_ok;
925 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
926 net_stats->tx_errors = stats->tx.tx_errors;
927 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 928
25f0a061
SF		 929 net_stats->rx_packets = stats->rx.rx_frames_ok;
930 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
931 net_stats->rx_errors = stats->rx.rx_errors;
932 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 933 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 934 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 935 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea
SF		 936}
937
f009618a
AD		 938static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
939{
940 struct enic *enic = netdev_priv(netdev);
941
942 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
943 unsigned int mc_count = netdev_mc_count(netdev);
944
945 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
946 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
947
948 return -ENOSPC;
949 }
950
951 enic_dev_add_addr(enic, mc_addr);
952 enic->mc_count++;
953
954 return 0;
955}
956
957static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
958{
959 struct enic *enic = netdev_priv(netdev);
960
961 enic_dev_del_addr(enic, mc_addr);
962 enic->mc_count--;
963
964 return 0;
965}
966
967static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
968{
969 struct enic *enic = netdev_priv(netdev);
970
971 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
972 unsigned int uc_count = netdev_uc_count(netdev);
973
974 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
975 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
976
977 return -ENOSPC;
978 }
979
980 enic_dev_add_addr(enic, uc_addr);
981 enic->uc_count++;
982
983 return 0;
984}
985
986static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
987{
988 struct enic *enic = netdev_priv(netdev);
989
990 enic_dev_del_addr(enic, uc_addr);
991 enic->uc_count--;
992
993 return 0;
994}
995
b3abfbd2 996void enic_reset_addr_lists(struct enic *enic)
01f2e4ea 997{
f009618a
AD		 998 struct net_device *netdev = enic->netdev;
999
1000 __dev_uc_unsync(netdev, NULL);
1001 __dev_mc_unsync(netdev, NULL);
1002
01f2e4ea 1003 enic->mc_count = 0;
e0afe53f 1004 enic->uc_count = 0;
99ef5639 1005 enic->flags = 0;
01f2e4ea
SF		 1006}
1007
1008static int enic_set_mac_addr(struct net_device *netdev, char *addr)
1009{
f8bd9091
SF		 1010 struct enic *enic = netdev_priv(netdev);
1011
7335903c 1012 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF		 1013 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
1014 return -EADDRNOTAVAIL;
1015 } else {
1016 if (!is_valid_ether_addr(addr))
1017 return -EADDRNOTAVAIL;
1018 }
01f2e4ea
SF		 1019
1020 memcpy(netdev->dev_addr, addr, netdev->addr_len);
1021
1022 return 0;
1023}
1024
f8bd9091
SF		 1025static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
1026{
1027 struct enic *enic = netdev_priv(netdev);
1028 struct sockaddr *saddr = p;
1029 char *addr = saddr->sa_data;
1030 int err;
1031
1032 if (netif_running(enic->netdev)) {
1033 err = enic_dev_del_station_addr(enic);
1034 if (err)
1035 return err;
1036 }
1037
1038 err = enic_set_mac_addr(netdev, addr);
1039 if (err)
1040 return err;
1041
1042 if (netif_running(enic->netdev)) {
1043 err = enic_dev_add_station_addr(enic);
1044 if (err)
1045 return err;
1046 }
1047
1048 return err;
1049}
1050
1051static int enic_set_mac_address(struct net_device *netdev, void *p)
1052{
294dab25 1053 struct sockaddr *saddr = p;
c76fd32d
VK		 1054 char *addr = saddr->sa_data;
1055 struct enic *enic = netdev_priv(netdev);
1056 int err;
1057
1058 err = enic_dev_del_station_addr(enic);
1059 if (err)
1060 return err;
1061
1062 err = enic_set_mac_addr(netdev, addr);
1063 if (err)
1064 return err;
294dab25 1065
c76fd32d 1066 return enic_dev_add_station_addr(enic);
f8bd9091
SF		 1067}
1068
319d7e84
RP		 1069/* netif_tx_lock held, BHs disabled */
1070static void enic_set_rx_mode(struct net_device *netdev)
1071{
1072 struct enic *enic = netdev_priv(netdev);
1073 int directed = 1;
1074 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
1075 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
1076 int promisc = (netdev->flags & IFF_PROMISC) ||
1077 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
1078 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
1079 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
1080 unsigned int flags = netdev->flags |
1081 (allmulti ? IFF_ALLMULTI : 0) |
1082 (promisc ? IFF_PROMISC : 0);
1083
1084 if (enic->flags != flags) {
1085 enic->flags = flags;
1086 enic_dev_packet_filter(enic, directed,
1087 multicast, broadcast, promisc, allmulti);
1088 }
1089
1090 if (!promisc) {
f009618a 1091 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
319d7e84 1092 if (!allmulti)
f009618a 1093 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
319d7e84
RP		 1094 }
1095}
1096
01f2e4ea
SF		 1097/* netif_tx_lock held, BHs disabled */
1098static void enic_tx_timeout(struct net_device *netdev)
1099{
1100 struct enic *enic = netdev_priv(netdev);
937317c7 1101 schedule_work(&enic->tx_hang_reset);
01f2e4ea
SF		 1102}
1103
0b1c00fc
RP		 1104static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
1105{
1106 struct enic *enic = netdev_priv(netdev);
3f192795
RP		 1107 struct enic_port_profile *pp;
1108 int err;
0b1c00fc 1109
3f192795
RP		 1110 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1111 if (err)
1112 return err;
0b1c00fc 1113
b8622cbd 1114 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP		 1115 if (vf == PORT_SELF_VF) {
1116 memcpy(pp->vf_mac, mac, ETH_ALEN);
1117 return 0;
1118 } else {
1119 /*
1120 * For sriov vf's set the mac in hw
1121 */
1122 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
1123 vnic_dev_set_mac_addr, mac);
1124 return enic_dev_status_to_errno(err);
1125 }
0b1c00fc
RP		 1126 } else
1127 return -EINVAL;
1128}
1129
f8bd9091
SF		 1130static int enic_set_vf_port(struct net_device *netdev, int vf,
1131 struct nlattr *port[])
1132{
1133 struct enic *enic = netdev_priv(netdev);
b3abfbd2 1134 struct enic_port_profile prev_pp;
3f192795 1135 struct enic_port_profile *pp;
b3abfbd2 1136 int err = 0, restore_pp = 1;
08f382eb 1137
3f192795
RP		 1138 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1139 if (err)
1140 return err;
08f382eb 1141
b3abfbd2
RP		 1142 if (!port[IFLA_PORT_REQUEST])
1143 return -EOPNOTSUPP;
1144
3f192795
RP		 1145 memcpy(&prev_pp, pp, sizeof(*enic->pp));
1146 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 1147
3f192795
RP		 1148 pp->set |= ENIC_SET_REQUEST;
1149 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF		 1150
1151 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP		 1152 pp->set |= ENIC_SET_NAME;
1153 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF		 1154 PORT_PROFILE_MAX);
1155 }
1156
1157 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP		 1158 pp->set |= ENIC_SET_INSTANCE;
1159 memcpy(pp->instance_uuid,
08f382eb
SF		 1160 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
1161 }
1162
1163 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP		 1164 pp->set |= ENIC_SET_HOST;
1165 memcpy(pp->host_uuid,
08f382eb
SF		 1166 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
1167 }
f8bd9091 1168
b4765833
RP		 1169 if (vf == PORT_SELF_VF) {
1170 /* Special case handling: mac came from IFLA_VF_MAC */
1171 if (!is_zero_ether_addr(prev_pp.vf_mac))
1172 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 1173
b4765833
RP		 1174 if (is_zero_ether_addr(netdev->dev_addr))
1175 eth_hw_addr_random(netdev);
1176 } else {
1177 /* SR-IOV VF: get mac from adapter */
1178 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
1179 vnic_dev_get_mac_addr, pp->mac_addr);
1180 if (err) {
1181 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
1182 memcpy(pp, &prev_pp, sizeof(*pp));
1183 return enic_dev_status_to_errno(err);
1184 }
1185 }
f8bd9091 1186
3f192795 1187 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP		 1188 if (err) {
1189 if (restore_pp) {
1190 /* Things are still the way they were: Implicit
1191 * DISASSOCIATE failed
1192 */
3f192795 1193 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 1194 } else {
3f192795
RP		 1195 memset(pp, 0, sizeof(*pp));
1196 if (vf == PORT_SELF_VF)
c7bf7169 1197 eth_zero_addr(netdev->dev_addr);
b3abfbd2
RP		 1198 }
1199 } else {
1200 /* Set flag to indicate that the port assoc/disassoc
1201 * request has been sent out to fw
1202 */
3f192795 1203 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP		 1204
1205 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795 1206 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
c7bf7169 1207 eth_zero_addr(pp->mac_addr);
3f192795 1208 if (vf == PORT_SELF_VF)
c7bf7169 1209 eth_zero_addr(netdev->dev_addr);
b3abfbd2
RP		 1210 }
1211 }
29639059 1212
b4765833 1213 if (vf == PORT_SELF_VF)
c7bf7169 1214 eth_zero_addr(pp->vf_mac);
29639059 1215
29639059 1216 return err;
f8bd9091
SF		 1217}
1218
1219static int enic_get_vf_port(struct net_device *netdev, int vf,
1220 struct sk_buff *skb)
1221{
1222 struct enic *enic = netdev_priv(netdev);
f8bd9091 1223 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 1224 struct enic_port_profile *pp;
b3abfbd2 1225 int err;
f8bd9091 1226
3f192795
RP		 1227 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
1228 if (err)
1229 return err;
1230
1231 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 1232 return -ENODATA;
f8bd9091 1233
3f192795 1234 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 1235 if (err)
b3abfbd2 1236 return err;
f8bd9091 1237
1a106de6
DM		 1238 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
1239 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
1240 ((pp->set & ENIC_SET_NAME) &&
1241 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
1242 ((pp->set & ENIC_SET_INSTANCE) &&
1243 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
1244 pp->instance_uuid)) ||
1245 ((pp->set & ENIC_SET_HOST) &&
1246 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
1247 goto nla_put_failure;
f8bd9091
SF		 1248 return 0;
1249
1250nla_put_failure:
1251 return -EMSGSIZE;
1252}
1253
01f2e4ea
SF		 1254static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
1255{
1256 struct enic *enic = vnic_dev_priv(rq->vdev);
1257
1258 if (!buf->os_buf)
1259 return;
1260
1261 pci_unmap_single(enic->pdev, buf->dma_addr,
1262 buf->len, PCI_DMA_FROMDEVICE);
1263 dev_kfree_skb_any(buf->os_buf);
a03bb56e 1264 buf->os_buf = NULL;
01f2e4ea
SF		 1265}
1266
01f2e4ea
SF		 1267static int enic_rq_alloc_buf(struct vnic_rq *rq)
1268{
1269 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 1270 struct net_device *netdev = enic->netdev;
01f2e4ea 1271 struct sk_buff *skb;
1825aca6 1272 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF		 1273 unsigned int os_buf_index = 0;
1274 dma_addr_t dma_addr;
a03bb56e
GV		 1275 struct vnic_rq_buf *buf = rq->to_use;
1276
1277 if (buf->os_buf) {
f6b7734b
GV		 1278 enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
1279 buf->len);
01f2e4ea 1280
a03bb56e
GV		 1281 return 0;
1282 }
89d71a66 1283 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF		 1284 if (!skb)
1285 return -ENOMEM;
1286
065df159
GV		 1287 dma_addr = pci_map_single(enic->pdev, skb->data, len,
1288 PCI_DMA_FROMDEVICE);
1289 if (unlikely(enic_dma_map_check(enic, dma_addr))) {
1290 dev_kfree_skb(skb);
1291 return -ENOMEM;
1292 }
01f2e4ea
SF		 1293
1294 enic_queue_rq_desc(rq, skb, os_buf_index,
1295 dma_addr, len);
1296
1297 return 0;
1298}
1299
7c2ce6e6
SS		 1300static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
1301 u32 pkt_len)
1302{
1303 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
1304 pkt_size->large_pkt_bytes_cnt += pkt_len;
1305 else
1306 pkt_size->small_pkt_bytes_cnt += pkt_len;
1307}
1308
a03bb56e
GV		 1309static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
1310 struct vnic_rq_buf *buf, u16 len)
1311{
1312 struct enic *enic = netdev_priv(netdev);
1313 struct sk_buff *new_skb;
1314
1315 if (len > enic->rx_copybreak)
1316 return false;
1317 new_skb = netdev_alloc_skb_ip_align(netdev, len);
1318 if (!new_skb)
1319 return false;
1320 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
1321 DMA_FROM_DEVICE);
1322 memcpy(new_skb->data, (*skb)->data, len);
1323 *skb = new_skb;
1324
1325 return true;
1326}
1327
01f2e4ea
SF		 1328static void enic_rq_indicate_buf(struct vnic_rq *rq,
1329 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
1330 int skipped, void *opaque)
1331{
1332 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 1333 struct net_device *netdev = enic->netdev;
01f2e4ea 1334 struct sk_buff *skb;
7c2ce6e6 1335 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
01f2e4ea
SF		 1336
1337 u8 type, color, eop, sop, ingress_port, vlan_stripped;
1338 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
1339 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
1340 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
1341 u8 packet_error;
f8cac14a 1342 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea 1343 u32 rss_hash;
257e7382 1344 bool outer_csum_ok = true, encap = false;
01f2e4ea
SF		 1345
1346 if (skipped)
1347 return;
1348
1349 skb = buf->os_buf;
01f2e4ea
SF		 1350
1351 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
1352 &type, &color, &q_number, &completed_index,
1353 &ingress_port, &fcoe, &eop, &sop, &rss_type,
1354 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 1355 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF		 1356 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
1357 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
1358 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
1359 &fcs_ok);
1360
1361 if (packet_error) {
1362
350991e1
SF		 1363 if (!fcs_ok) {
1364 if (bytes_written > 0)
1365 enic->rq_bad_fcs++;
1366 else if (bytes_written == 0)
1367 enic->rq_truncated_pkts++;
1368 }
01f2e4ea 1369
44aa91ab
GV		 1370 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1371 PCI_DMA_FROMDEVICE);
01f2e4ea 1372 dev_kfree_skb_any(skb);
44aa91ab 1373 buf->os_buf = NULL;
01f2e4ea
SF		 1374
1375 return;
1376 }
1377
1378 if (eop && bytes_written > 0) {
1379
1380 /* Good receive
1381 */
1382
a03bb56e
GV		 1383 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
1384 buf->os_buf = NULL;
1385 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1386 PCI_DMA_FROMDEVICE);
1387 }
1388 prefetch(skb->data - NET_IP_ALIGN);
1389
01f2e4ea 1390 skb_put(skb, bytes_written);
86ca9db7 1391 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1392 skb_record_rx_queue(skb, q_number);
257e7382
GV		 1393 if ((netdev->features & NETIF_F_RXHASH) && rss_hash &&
1394 (type == 3)) {
17197236
GV		 1395 switch (rss_type) {
1396 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4:
1397 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6:
1398 case CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX:
1399 skb_set_hash(skb, rss_hash, PKT_HASH_TYPE_L4);
1400 break;
1401 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv4:
1402 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv6:
1403 case CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX:
1404 skb_set_hash(skb, rss_hash, PKT_HASH_TYPE_L3);
1405 break;
1406 }
bf751ba8 1407 }
257e7382
GV		 1408 if (enic->vxlan.vxlan_udp_port_number) {
1409 switch (enic->vxlan.patch_level) {
1410 case 0:
1411 if (fcoe) {
1412 encap = true;
1413 outer_csum_ok = fcoe_fc_crc_ok;
1414 }
1415 break;
1416 case 2:
1417 if ((type == 7) &&
1418 (rss_hash & BIT(0))) {
1419 encap = true;
1420 outer_csum_ok = (rss_hash & BIT(1)) &&
1421 (rss_hash & BIT(2));
1422 }
1423 break;
1424 }
1425 }
01f2e4ea 1426
17e96834
GV		 1427 /* Hardware does not provide whole packet checksum. It only
1428 * provides pseudo checksum. Since hw validates the packet
1429 * checksum but not provide us the checksum value. use
1430 * CHECSUM_UNNECESSARY.
257e7382
GV		 1431 *
1432 * In case of encap pkt tcp_udp_csum_ok/tcp_udp_csum_ok is
1433 * inner csum_ok. outer_csum_ok is set by hw when outer udp
1434 * csum is correct or is zero.
17e96834 1435 */
257e7382
GV		 1436 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc &&
1437 tcp_udp_csum_ok && ipv4_csum_ok && outer_csum_ok) {
17e96834 1438 skb->ip_summed = CHECKSUM_UNNECESSARY;
257e7382
GV		 1439 skb->csum_level = encap;
1440 }
01f2e4ea 1441
6ede746b 1442 if (vlan_stripped)
86a9bad3 1443 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1444
14747cd9 1445 skb_mark_napi_id(skb, &enic->napi[rq->index]);
7a655c63 1446 if (!(netdev->features & NETIF_F_GRO))
6ede746b 1447 netif_receive_skb(skb);
14747cd9
GV		 1448 else
1449 napi_gro_receive(&enic->napi[q_number], skb);
7c2ce6e6
SS		 1450 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1451 enic_intr_update_pkt_size(&cq->pkt_size_counter,
1452 bytes_written);
01f2e4ea
SF		 1453 } else {
1454
1455 /* Buffer overflow
1456 */
1457
44aa91ab
GV		 1458 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1459 PCI_DMA_FROMDEVICE);
01f2e4ea 1460 dev_kfree_skb_any(skb);
44aa91ab 1461 buf->os_buf = NULL;
01f2e4ea
SF		 1462 }
1463}
1464
1465static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1466 u8 type, u16 q_number, u16 completed_index, void *opaque)
1467{
1468 struct enic *enic = vnic_dev_priv(vdev);
1469
1470 vnic_rq_service(&enic->rq[q_number], cq_desc,
1471 completed_index, VNIC_RQ_RETURN_DESC,
1472 enic_rq_indicate_buf, opaque);
1473
1474 return 0;
1475}
1476
fc865d6b
GV		 1477static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
1478{
1479 unsigned int intr = enic_msix_rq_intr(enic, rq->index);
1480 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1481 u32 timer = cq->tobe_rx_coal_timeval;
1482
1483 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
1484 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
1485 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
1486 }
1487}
1488
1489static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
1490{
1491 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1492 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1493 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
1494 int index;
1495 u32 timer;
1496 u32 range_start;
1497 u32 traffic;
1498 u64 delta;
1499 ktime_t now = ktime_get();
1500
1501 delta = ktime_us_delta(now, cq->prev_ts);
1502 if (delta < ENIC_AIC_TS_BREAK)
1503 return;
1504 cq->prev_ts = now;
1505
1506 traffic = pkt_size_counter->large_pkt_bytes_cnt +
1507 pkt_size_counter->small_pkt_bytes_cnt;
1508 /* The table takes Mbps
1509 * traffic *= 8 => bits
1510 * traffic *= (10^6 / delta) => bps
1511 * traffic /= 10^6 => Mbps
1512 *
1513 * Combining, traffic *= (8 / delta)
1514 */
1515
1516 traffic <<= 3;
1517 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
1518
1519 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
1520 if (traffic < mod_table[index].rx_rate)
1521 break;
1522 range_start = (pkt_size_counter->small_pkt_bytes_cnt >
1523 pkt_size_counter->large_pkt_bytes_cnt << 1) ?
1524 rx_coal->small_pkt_range_start :
1525 rx_coal->large_pkt_range_start;
1526 timer = range_start + ((rx_coal->range_end - range_start) *
1527 mod_table[index].range_percent / 100);
1528 /* Damping */
1529 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
1530
1531 pkt_size_counter->large_pkt_bytes_cnt = 0;
1532 pkt_size_counter->small_pkt_bytes_cnt = 0;
1533}
1534
01f2e4ea
SF		 1535static int enic_poll(struct napi_struct *napi, int budget)
1536{
717258ba
VK		 1537 struct net_device *netdev = napi->dev;
1538 struct enic *enic = netdev_priv(netdev);
1539 unsigned int cq_rq = enic_cq_rq(enic, 0);
1540 unsigned int cq_wq = enic_cq_wq(enic, 0);
1541 unsigned int intr = enic_legacy_io_intr();
01f2e4ea 1542 unsigned int rq_work_to_do = budget;
18feb871 1543 unsigned int wq_work_to_do = ENIC_WQ_NAPI_BUDGET;
4c502549 1544 unsigned int work_done, rq_work_done = 0, wq_work_done;
2d6ddced 1545 int err;
01f2e4ea 1546
14747cd9
GV		 1547 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
1548 enic_wq_service, NULL);
1549
4c502549
EB		 1550 if (budget > 0)
1551 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
1552 rq_work_to_do, enic_rq_service, NULL);
01f2e4ea 1553
01f2e4ea
SF		 1554 /* Accumulate intr event credits for this polling
1555 * cycle. An intr event is the completion of a
1556 * a WQ or RQ packet.
1557 */
1558
1559 work_done = rq_work_done + wq_work_done;
1560
1561 if (work_done > 0)
717258ba 1562 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1563 work_done,
1564 0 /* don't unmask intr */,
1565 0 /* don't reset intr timer */);
1566
0eb26022 1567 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1568
2d6ddced
SF		 1569 /* Buffer allocation failed. Stay in polling
1570 * mode so we can try to fill the ring again.
1571 */
01f2e4ea 1572
2d6ddced
SF		 1573 if (err)
1574 rq_work_done = rq_work_to_do;
fc865d6b
GV		 1575 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1576 /* Call the function which refreshes the intr coalescing timer
1577 * value based on the traffic.
1578 */
1579 enic_calc_int_moderation(enic, &enic->rq[0]);
01f2e4ea 1580
9acfd1c0 1581 if ((rq_work_done < budget) && napi_complete_done(napi, rq_work_done)) {
01f2e4ea 1582
2d6ddced 1583 /* Some work done, but not enough to stay in polling,
88132f55 1584 * exit polling
01f2e4ea
SF		 1585 */
1586
fc865d6b
GV		 1587 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1588 enic_set_int_moderation(enic, &enic->rq[0]);
717258ba 1589 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea
SF		 1590 }
1591
1592 return rq_work_done;
1593}
1594
b6e97c13
GV		 1595#ifdef CONFIG_RFS_ACCEL
1596static void enic_free_rx_cpu_rmap(struct enic *enic)
1597{
1598 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
1599 enic->netdev->rx_cpu_rmap = NULL;
1600}
1601
1602static void enic_set_rx_cpu_rmap(struct enic *enic)
1603{
1604 int i, res;
1605
1606 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
1607 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
1608 if (unlikely(!enic->netdev->rx_cpu_rmap))
1609 return;
1610 for (i = 0; i < enic->rq_count; i++) {
1611 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
1612 enic->msix_entry[i].vector);
1613 if (unlikely(res)) {
1614 enic_free_rx_cpu_rmap(enic);
1615 return;
1616 }
1617 }
1618 }
1619}
1620
1621#else
1622
1623static void enic_free_rx_cpu_rmap(struct enic *enic)
1624{
1625}
1626
1627static void enic_set_rx_cpu_rmap(struct enic *enic)
1628{
1629}
1630
1631#endif /* CONFIG_RFS_ACCEL */
1632
4cfe8785
GV		 1633static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
1634{
1635 struct net_device *netdev = napi->dev;
1636 struct enic *enic = netdev_priv(netdev);
1637 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
1638 struct vnic_wq *wq = &enic->wq[wq_index];
1639 unsigned int cq;
1640 unsigned int intr;
18feb871 1641 unsigned int wq_work_to_do = ENIC_WQ_NAPI_BUDGET;
4cfe8785
GV		 1642 unsigned int wq_work_done;
1643 unsigned int wq_irq;
1644
1645 wq_irq = wq->index;
1646 cq = enic_cq_wq(enic, wq_irq);
1647 intr = enic_msix_wq_intr(enic, wq_irq);
1648 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
1649 enic_wq_service, NULL);
1650
1651 vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
1652 0 /* don't unmask intr */,
1653 1 /* reset intr timer */);
1654 if (!wq_work_done) {
1655 napi_complete(napi);
1656 vnic_intr_unmask(&enic->intr[intr]);
f41281d0 1657 return 0;
4cfe8785
GV		 1658 }
1659
f41281d0 1660 return budget;
4cfe8785
GV		 1661}
1662
1663static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
01f2e4ea 1664{
717258ba
VK		 1665 struct net_device *netdev = napi->dev;
1666 struct enic *enic = netdev_priv(netdev);
1667 unsigned int rq = (napi - &enic->napi[0]);
1668 unsigned int cq = enic_cq_rq(enic, rq);
1669 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea 1670 unsigned int work_to_do = budget;
4c502549 1671 unsigned int work_done = 0;
2d6ddced 1672 int err;
01f2e4ea
SF		 1673
1674 /* Service RQ
1675 */
1676
4c502549
EB		 1677 if (budget > 0)
1678 work_done = vnic_cq_service(&enic->cq[cq],
1679 work_to_do, enic_rq_service, NULL);
01f2e4ea 1680
2d6ddced
SF		 1681 /* Return intr event credits for this polling
1682 * cycle. An intr event is the completion of a
1683 * RQ packet.
1684 */
01f2e4ea 1685
2d6ddced 1686 if (work_done > 0)
717258ba 1687 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1688 work_done,
1689 0 /* don't unmask intr */,
1690 0 /* don't reset intr timer */);
01f2e4ea 1691
0eb26022 1692 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF		 1693
1694 /* Buffer allocation failed. Stay in polling mode
1695 * so we can try to fill the ring again.
1696 */
1697
1698 if (err)
1699 work_done = work_to_do;
7c2ce6e6 1700 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
fc865d6b
GV		 1701 /* Call the function which refreshes the intr coalescing timer
1702 * value based on the traffic.
7c2ce6e6
SS		 1703 */
1704 enic_calc_int_moderation(enic, &enic->rq[rq]);
2d6ddced 1705
9acfd1c0 1706 if ((work_done < budget) && napi_complete_done(napi, work_done)) {
2d6ddced
SF		 1707
1708 /* Some work done, but not enough to stay in polling,
88132f55 1709 * exit polling
01f2e4ea
SF		 1710 */
1711
7c2ce6e6
SS		 1712 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1713 enic_set_int_moderation(enic, &enic->rq[rq]);
717258ba 1714 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea
SF		 1715 }
1716
1717 return work_done;
1718}
1719
e99e88a9 1720static void enic_notify_timer(struct timer_list *t)
01f2e4ea 1721{
e99e88a9 1722 struct enic *enic = from_timer(enic, t, notify_timer);
01f2e4ea
SF		 1723
1724 enic_notify_check(enic);
1725
25f0a061
SF		 1726 mod_timer(&enic->notify_timer,
1727 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF		 1728}
1729
1730static void enic_free_intr(struct enic *enic)
1731{
1732 struct net_device *netdev = enic->netdev;
1733 unsigned int i;
1734
b6e97c13 1735 enic_free_rx_cpu_rmap(enic);
01f2e4ea
SF		 1736 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1737 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF		 1738 free_irq(enic->pdev->irq, netdev);
1739 break;
8f4d248c
SF		 1740 case VNIC_DEV_INTR_MODE_MSI:
1741 free_irq(enic->pdev->irq, enic);
1742 break;
01f2e4ea
SF		 1743 case VNIC_DEV_INTR_MODE_MSIX:
1744 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1745 if (enic->msix[i].requested)
1746 free_irq(enic->msix_entry[i].vector,
1747 enic->msix[i].devid);
1748 break;
1749 default:
1750 break;
1751 }
1752}
1753
1754static int enic_request_intr(struct enic *enic)
1755{
1756 struct net_device *netdev = enic->netdev;
717258ba 1757 unsigned int i, intr;
01f2e4ea
SF		 1758 int err = 0;
1759
b6e97c13 1760 enic_set_rx_cpu_rmap(enic);
01f2e4ea
SF		 1761 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1762
1763 case VNIC_DEV_INTR_MODE_INTX:
1764
1765 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1766 IRQF_SHARED, netdev->name, netdev);
1767 break;
1768
1769 case VNIC_DEV_INTR_MODE_MSI:
1770
1771 err = request_irq(enic->pdev->irq, enic_isr_msi,
1772 0, netdev->name, enic);
1773 break;
1774
1775 case VNIC_DEV_INTR_MODE_MSIX:
1776
717258ba
VK		 1777 for (i = 0; i < enic->rq_count; i++) {
1778 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC		 1779 snprintf(enic->msix[intr].devname,
1780 sizeof(enic->msix[intr].devname),
7044f429 1781 "%s-rx-%u", netdev->name, i);
4cfe8785 1782 enic->msix[intr].isr = enic_isr_msix;
717258ba
VK		 1783 enic->msix[intr].devid = &enic->napi[i];
1784 }
01f2e4ea 1785
717258ba 1786 for (i = 0; i < enic->wq_count; i++) {
4cfe8785
GV		 1787 int wq = enic_cq_wq(enic, i);
1788
717258ba 1789 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC		 1790 snprintf(enic->msix[intr].devname,
1791 sizeof(enic->msix[intr].devname),
7044f429 1792 "%s-tx-%u", netdev->name, i);
4cfe8785
GV		 1793 enic->msix[intr].isr = enic_isr_msix;
1794 enic->msix[intr].devid = &enic->napi[wq];
717258ba 1795 }
01f2e4ea 1796
717258ba 1797 intr = enic_msix_err_intr(enic);
4505f40a
DC		 1798 snprintf(enic->msix[intr].devname,
1799 sizeof(enic->msix[intr].devname),
7044f429 1800 "%s-err", netdev->name);
717258ba
VK		 1801 enic->msix[intr].isr = enic_isr_msix_err;
1802 enic->msix[intr].devid = enic;
01f2e4ea 1803
717258ba 1804 intr = enic_msix_notify_intr(enic);
4505f40a
DC		 1805 snprintf(enic->msix[intr].devname,
1806 sizeof(enic->msix[intr].devname),
7044f429 1807 "%s-notify", netdev->name);
717258ba
VK		 1808 enic->msix[intr].isr = enic_isr_msix_notify;
1809 enic->msix[intr].devid = enic;
1810
1811 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1812 enic->msix[i].requested = 0;
01f2e4ea 1813
717258ba 1814 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF		 1815 err = request_irq(enic->msix_entry[i].vector,
1816 enic->msix[i].isr, 0,
1817 enic->msix[i].devname,
1818 enic->msix[i].devid);
1819 if (err) {
1820 enic_free_intr(enic);
1821 break;
1822 }
1823 enic->msix[i].requested = 1;
1824 }
1825
1826 break;
1827
1828 default:
1829 break;
1830 }
1831
1832 return err;
1833}
1834
b3d18d19
SF		 1835static void enic_synchronize_irqs(struct enic *enic)
1836{
1837 unsigned int i;
1838
1839 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1840 case VNIC_DEV_INTR_MODE_INTX:
1841 case VNIC_DEV_INTR_MODE_MSI:
1842 synchronize_irq(enic->pdev->irq);
1843 break;
1844 case VNIC_DEV_INTR_MODE_MSIX:
1845 for (i = 0; i < enic->intr_count; i++)
1846 synchronize_irq(enic->msix_entry[i].vector);
1847 break;
1848 default:
1849 break;
1850 }
1851}
1852
7c2ce6e6
SS		 1853static void enic_set_rx_coal_setting(struct enic *enic)
1854{
1855 unsigned int speed;
1856 int index = -1;
1857 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1858
7c2ce6e6
SS		 1859 /* 1. Read the link speed from fw
1860 * 2. Pick the default range for the speed
1861 * 3. Update it in enic->rx_coalesce_setting
1862 */
1863 speed = vnic_dev_port_speed(enic->vdev);
1864 if (ENIC_LINK_SPEED_10G < speed)
1865 index = ENIC_LINK_40G_INDEX;
1866 else if (ENIC_LINK_SPEED_4G < speed)
1867 index = ENIC_LINK_10G_INDEX;
1868 else
1869 index = ENIC_LINK_4G_INDEX;
1870
1871 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
1872 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
1873 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
1874
1875 /* Start with the value provided by UCSM */
1876 for (index = 0; index < enic->rq_count; index++)
1877 enic->cq[index].cur_rx_coal_timeval =
1878 enic->config.intr_timer_usec;
1879
1880 rx_coal->use_adaptive_rx_coalesce = 1;
1881}
1882
383ab92f 1883static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF		 1884{
1885 int err;
1886
8e091340 1887 spin_lock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1888 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1889 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK		 1890 err = vnic_dev_notify_set(enic->vdev,
1891 enic_legacy_notify_intr());
01f2e4ea
SF		 1892 break;
1893 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1894 err = vnic_dev_notify_set(enic->vdev,
1895 enic_msix_notify_intr(enic));
01f2e4ea
SF		 1896 break;
1897 default:
1898 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1899 break;
1900 }
8e091340 1901 spin_unlock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1902
1903 return err;
1904}
1905
1906static void enic_notify_timer_start(struct enic *enic)
1907{
1908 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1909 case VNIC_DEV_INTR_MODE_MSI:
1910 mod_timer(&enic->notify_timer, jiffies);
1911 break;
1912 default:
1913 /* Using intr for notification for INTx/MSI-X */
1914 break;
6403eab1 1915 }
01f2e4ea
SF		 1916}
1917
1918/* rtnl lock is held, process context */
1919static int enic_open(struct net_device *netdev)
1920{
1921 struct enic *enic = netdev_priv(netdev);
1922 unsigned int i;
56f77227 1923 int err, ret;
01f2e4ea 1924
4b75a442
SF		 1925 err = enic_request_intr(enic);
1926 if (err) {
a7a79deb 1927 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF		 1928 return err;
1929 }
322cf7e3
GV		 1930 enic_init_affinity_hint(enic);
1931 enic_set_affinity_hint(enic);
4b75a442 1932
383ab92f 1933 err = enic_dev_notify_set(enic);
4b75a442 1934 if (err) {
a7a79deb
VK		 1935 netdev_err(netdev,
1936 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF		 1937 goto err_out_free_intr;
1938 }
1939
01f2e4ea 1940 for (i = 0; i < enic->rq_count; i++) {
e8588e26
GV		 1941 /* enable rq before updating rq desc */
1942 vnic_rq_enable(&enic->rq[i]);
0eb26022 1943 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF		 1944 /* Need at least one buffer on ring to get going */
1945 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1946 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1947 err = -ENOMEM;
9dac6232 1948 goto err_out_free_rq;
01f2e4ea
SF		 1949 }
1950 }
1951
1952 for (i = 0; i < enic->wq_count; i++)
1953 vnic_wq_enable(&enic->wq[i]);
01f2e4ea 1954
7335903c 1955 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1956 enic_dev_add_station_addr(enic);
3f192795 1957
319d7e84 1958 enic_set_rx_mode(netdev);
01f2e4ea 1959
822473b6 1960 netif_tx_wake_all_queues(netdev);
717258ba 1961
7a655c63 1962 for (i = 0; i < enic->rq_count; i++)
717258ba 1963 napi_enable(&enic->napi[i]);
7a655c63 1964
4cfe8785
GV		 1965 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1966 for (i = 0; i < enic->wq_count; i++)
1967 napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
383ab92f 1968 enic_dev_enable(enic);
01f2e4ea
SF		 1969
1970 for (i = 0; i < enic->intr_count; i++)
1971 vnic_intr_unmask(&enic->intr[i]);
1972
1973 enic_notify_timer_start(enic);
3256d29f 1974 enic_rfs_timer_start(enic);
01f2e4ea
SF		 1975
1976 return 0;
4b75a442 1977
9dac6232 1978err_out_free_rq:
e8588e26 1979 for (i = 0; i < enic->rq_count; i++) {
56f77227
GV		 1980 ret = vnic_rq_disable(&enic->rq[i]);
1981 if (!ret)
1982 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
e8588e26 1983 }
383ab92f 1984 enic_dev_notify_unset(enic);
4b75a442 1985err_out_free_intr:
322cf7e3 1986 enic_unset_affinity_hint(enic);
4b75a442
SF		 1987 enic_free_intr(enic);
1988
1989 return err;
01f2e4ea
SF		 1990}
1991
1992/* rtnl lock is held, process context */
1993static int enic_stop(struct net_device *netdev)
1994{
1995 struct enic *enic = netdev_priv(netdev);
1996 unsigned int i;
1997 int err;
1998
29046f9b 1999 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 2000 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK		 2001 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
2002 }
b3d18d19
SF		 2003
2004 enic_synchronize_irqs(enic);
2005
01f2e4ea 2006 del_timer_sync(&enic->notify_timer);
a145df23 2007 enic_rfs_flw_tbl_free(enic);
01f2e4ea 2008
383ab92f 2009 enic_dev_disable(enic);
717258ba 2010
7a655c63 2011 for (i = 0; i < enic->rq_count; i++)
717258ba
VK		 2012 napi_disable(&enic->napi[i]);
2013
b3d18d19
SF		 2014 netif_carrier_off(netdev);
2015 netif_tx_disable(netdev);
4cfe8785
GV		 2016 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2017 for (i = 0; i < enic->wq_count; i++)
2018 napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
3f192795 2019
7335903c 2020 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 2021 enic_dev_del_station_addr(enic);
f8bd9091 2022
01f2e4ea
SF		 2023 for (i = 0; i < enic->wq_count; i++) {
2024 err = vnic_wq_disable(&enic->wq[i]);
2025 if (err)
2026 return err;
2027 }
2028 for (i = 0; i < enic->rq_count; i++) {
2029 err = vnic_rq_disable(&enic->rq[i]);
2030 if (err)
2031 return err;
2032 }
2033
383ab92f 2034 enic_dev_notify_unset(enic);
322cf7e3 2035 enic_unset_affinity_hint(enic);
4b75a442
SF		 2036 enic_free_intr(enic);
2037
01f2e4ea
SF		 2038 for (i = 0; i < enic->wq_count; i++)
2039 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
2040 for (i = 0; i < enic->rq_count; i++)
2041 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
2042 for (i = 0; i < enic->cq_count; i++)
2043 vnic_cq_clean(&enic->cq[i]);
2044 for (i = 0; i < enic->intr_count; i++)
2045 vnic_intr_clean(&enic->intr[i]);
2046
2047 return 0;
2048}
2049
ab123fe0
GV		 2050static int _enic_change_mtu(struct net_device *netdev, int new_mtu)
2051{
2052 bool running = netif_running(netdev);
2053 int err = 0;
2054
2055 ASSERT_RTNL();
2056 if (running) {
2057 err = enic_stop(netdev);
2058 if (err)
2059 return err;
2060 }
2061
2062 netdev->mtu = new_mtu;
2063
2064 if (running) {
2065 err = enic_open(netdev);
2066 if (err)
2067 return err;
2068 }
2069
2070 return 0;
2071}
2072
01f2e4ea
SF		 2073static int enic_change_mtu(struct net_device *netdev, int new_mtu)
2074{
2075 struct enic *enic = netdev_priv(netdev);
01f2e4ea 2076
7335903c 2077 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP		 2078 return -EOPNOTSUPP;
2079
01f2e4ea 2080 if (netdev->mtu > enic->port_mtu)
a7a79deb 2081 netdev_warn(netdev,
ab123fe0
GV		 2082 "interface MTU (%d) set higher than port MTU (%d)\n",
2083 netdev->mtu, enic->port_mtu);
01f2e4ea 2084
ab123fe0 2085 return _enic_change_mtu(netdev, new_mtu);
01f2e4ea
SF		 2086}
2087
c97c894d
RP		 2088static void enic_change_mtu_work(struct work_struct *work)
2089{
2090 struct enic *enic = container_of(work, struct enic, change_mtu_work);
2091 struct net_device *netdev = enic->netdev;
2092 int new_mtu = vnic_dev_mtu(enic->vdev);
c97c894d
RP		 2093
2094 rtnl_lock();
ab123fe0 2095 (void)_enic_change_mtu(netdev, new_mtu);
c97c894d
RP		 2096 rtnl_unlock();
2097
2098 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
2099}
2100
01f2e4ea
SF		 2101#ifdef CONFIG_NET_POLL_CONTROLLER
2102static void enic_poll_controller(struct net_device *netdev)
2103{
2104 struct enic *enic = netdev_priv(netdev);
2105 struct vnic_dev *vdev = enic->vdev;
717258ba 2106 unsigned int i, intr;
01f2e4ea
SF		 2107
2108 switch (vnic_dev_get_intr_mode(vdev)) {
2109 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 2110 for (i = 0; i < enic->rq_count; i++) {
2111 intr = enic_msix_rq_intr(enic, i);
4cfe8785
GV		 2112 enic_isr_msix(enic->msix_entry[intr].vector,
2113 &enic->napi[i]);
717258ba 2114 }
b880a954
VK		 2115
2116 for (i = 0; i < enic->wq_count; i++) {
2117 intr = enic_msix_wq_intr(enic, i);
4cfe8785
GV		 2118 enic_isr_msix(enic->msix_entry[intr].vector,
2119 &enic->napi[enic_cq_wq(enic, i)]);
b880a954
VK		 2120 }
2121
01f2e4ea
SF		 2122 break;
2123 case VNIC_DEV_INTR_MODE_MSI:
2124 enic_isr_msi(enic->pdev->irq, enic);
2125 break;
2126 case VNIC_DEV_INTR_MODE_INTX:
2127 enic_isr_legacy(enic->pdev->irq, netdev);
2128 break;
2129 default:
2130 break;
2131 }
2132}
2133#endif
2134
2135static int enic_dev_wait(struct vnic_dev *vdev,
2136 int (*start)(struct vnic_dev *, int),
2137 int (*finished)(struct vnic_dev *, int *),
2138 int arg)
2139{
2140 unsigned long time;
2141 int done;
2142 int err;
2143
2144 BUG_ON(in_interrupt());
2145
2146 err = start(vdev, arg);
2147 if (err)
2148 return err;
2149
2150 /* Wait for func to complete...2 seconds max
2151 */
2152
2153 time = jiffies + (HZ * 2);
2154 do {
2155
2156 err = finished(vdev, &done);
2157 if (err)
2158 return err;
2159
2160 if (done)
2161 return 0;
2162
2163 schedule_timeout_uninterruptible(HZ / 10);
2164
2165 } while (time_after(time, jiffies));
2166
2167 return -ETIMEDOUT;
2168}
2169
2170static int enic_dev_open(struct enic *enic)
2171{
2172 int err;
5de0c022 2173 u32 flags = CMD_OPENF_IG_DESCCACHE;
01f2e4ea
SF		 2174
2175 err = enic_dev_wait(enic->vdev, vnic_dev_open,
5de0c022 2176 vnic_dev_open_done, flags);
01f2e4ea 2177 if (err)
a7a79deb
VK		 2178 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
2179 err);
01f2e4ea
SF		 2180
2181 return err;
2182}
2183
937317c7
GV		 2184static int enic_dev_soft_reset(struct enic *enic)
2185{
2186 int err;
2187
2188 err = enic_dev_wait(enic->vdev, vnic_dev_soft_reset,
2189 vnic_dev_soft_reset_done, 0);
2190 if (err)
2191 netdev_err(enic->netdev, "vNIC soft reset failed, err %d\n",
2192 err);
2193
2194 return err;
2195}
2196
99ef5639 2197static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF		 2198{
2199 int err;
2200
99ef5639
VK		 2201 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
2202 vnic_dev_hang_reset_done, 0);
01f2e4ea 2203 if (err)
a7a79deb
VK		 2204 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
2205 err);
01f2e4ea
SF		 2206
2207 return err;
2208}
2209
4f675eb2 2210int __enic_set_rsskey(struct enic *enic)
717258ba 2211{
c33d23c2 2212 union vnic_rss_key *rss_key_buf_va;
1f4f067f 2213 dma_addr_t rss_key_buf_pa;
c33d23c2 2214 int i, kidx, bidx, err;
717258ba 2215
c33d23c2
ED		 2216 rss_key_buf_va = pci_zalloc_consistent(enic->pdev,
2217 sizeof(union vnic_rss_key),
2218 &rss_key_buf_pa);
717258ba
VK		 2219 if (!rss_key_buf_va)
2220 return -ENOMEM;
2221
c33d23c2
ED		 2222 for (i = 0; i < ENIC_RSS_LEN; i++) {
2223 kidx = i / ENIC_RSS_BYTES_PER_KEY;
2224 bidx = i % ENIC_RSS_BYTES_PER_KEY;
4f675eb2 2225 rss_key_buf_va->key[kidx].b[bidx] = enic->rss_key[i];
c33d23c2 2226 }
8e091340 2227 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 2228 err = enic_set_rss_key(enic,
2229 rss_key_buf_pa,
2230 sizeof(union vnic_rss_key));
8e091340 2231 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 2232
2233 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
2234 rss_key_buf_va, rss_key_buf_pa);
2235
2236 return err;
2237}
2238
4f675eb2
GV		 2239static int enic_set_rsskey(struct enic *enic)
2240{
2241 netdev_rss_key_fill(enic->rss_key, ENIC_RSS_LEN);
2242
2243 return __enic_set_rsskey(enic);
2244}
2245
717258ba
VK		 2246static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
2247{
1f4f067f 2248 dma_addr_t rss_cpu_buf_pa;
717258ba
VK		 2249 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
2250 unsigned int i;
2251 int err;
2252
2253 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
2254 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
2255 if (!rss_cpu_buf_va)
2256 return -ENOMEM;
2257
2258 for (i = 0; i < (1 << rss_hash_bits); i++)
2259 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
2260
8e091340 2261 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 2262 err = enic_set_rss_cpu(enic,
2263 rss_cpu_buf_pa,
2264 sizeof(union vnic_rss_cpu));
8e091340 2265 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 2266
2267 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
2268 rss_cpu_buf_va, rss_cpu_buf_pa);
2269
2270 return err;
2271}
2272
2273static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
2274 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 2275{
68f71708
SF		 2276 const u8 tso_ipid_split_en = 0;
2277 const u8 ig_vlan_strip_en = 1;
383ab92f 2278 int err;
68f71708 2279
717258ba
VK		 2280 /* Enable VLAN tag stripping.
2281 */
68f71708 2282
8e091340 2283 spin_lock_bh(&enic->devcmd_lock);
383ab92f 2284 err = enic_set_nic_cfg(enic,
68f71708
SF		 2285 rss_default_cpu, rss_hash_type,
2286 rss_hash_bits, rss_base_cpu,
2287 rss_enable, tso_ipid_split_en,
2288 ig_vlan_strip_en);
8e091340 2289 spin_unlock_bh(&enic->devcmd_lock);
383ab92f
VK		 2290
2291 return err;
2292}
2293
717258ba
VK		 2294static int enic_set_rss_nic_cfg(struct enic *enic)
2295{
2296 struct device *dev = enic_get_dev(enic);
2297 const u8 rss_default_cpu = 0;
717258ba
VK		 2298 const u8 rss_hash_bits = 7;
2299 const u8 rss_base_cpu = 0;
4016a7f1
GV		 2300 u8 rss_hash_type;
2301 int res;
717258ba
VK		 2302 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
2303
4016a7f1
GV		 2304 spin_lock_bh(&enic->devcmd_lock);
2305 res = vnic_dev_capable_rss_hash_type(enic->vdev, &rss_hash_type);
2306 spin_unlock_bh(&enic->devcmd_lock);
2307 if (res) {
2308 /* defaults for old adapters
2309 */
2310 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
2311 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
2312 NIC_CFG_RSS_HASH_TYPE_IPV6 |
2313 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
2314 }
2315
717258ba
VK		 2316 if (rss_enable) {
2317 if (!enic_set_rsskey(enic)) {
2318 if (enic_set_rsscpu(enic, rss_hash_bits)) {
2319 rss_enable = 0;
2320 dev_warn(dev, "RSS disabled, "
2321 "Failed to set RSS cpu indirection table.");
2322 }
2323 } else {
2324 rss_enable = 0;
2325 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
2326 }
2327 }
2328
2329 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
2330 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK		 2331}
2332
01f2e4ea
SF		 2333static void enic_reset(struct work_struct *work)
2334{
2335 struct enic *enic = container_of(work, struct enic, reset);
2336
2337 if (!netif_running(enic->netdev))
2338 return;
2339
2340 rtnl_lock();
2341
937317c7
GV		 2342 spin_lock(&enic->enic_api_lock);
2343 enic_stop(enic->netdev);
2344 enic_dev_soft_reset(enic);
2345 enic_reset_addr_lists(enic);
2346 enic_init_vnic_resources(enic);
2347 enic_set_rss_nic_cfg(enic);
2348 enic_dev_set_ig_vlan_rewrite_mode(enic);
2349 enic_open(enic->netdev);
2350 spin_unlock(&enic->enic_api_lock);
2351 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
2352
2353 rtnl_unlock();
2354}
2355
2356static void enic_tx_hang_reset(struct work_struct *work)
2357{
2358 struct enic *enic = container_of(work, struct enic, tx_hang_reset);
2359
2360 rtnl_lock();
2361
0b038566 2362 spin_lock(&enic->enic_api_lock);
383ab92f 2363 enic_dev_hang_notify(enic);
01f2e4ea 2364 enic_stop(enic->netdev);
99ef5639 2365 enic_dev_hang_reset(enic);
e0afe53f 2366 enic_reset_addr_lists(enic);
01f2e4ea 2367 enic_init_vnic_resources(enic);
717258ba 2368 enic_set_rss_nic_cfg(enic);
f8cac14a 2369 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 2370 enic_open(enic->netdev);
0b038566 2371 spin_unlock(&enic->enic_api_lock);
d765bb41 2372 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF		 2373
2374 rtnl_unlock();
2375}
2376
2377static int enic_set_intr_mode(struct enic *enic)
2378{
717258ba 2379 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 2380 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF		 2381 unsigned int i;
2382
2383 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 2384 * on system capabilities.
01f2e4ea
SF		 2385 *
2386 * Try MSI-X first
2387 *
2388 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
2389 * (the second to last INTR is used for WQ/RQ errors)
2390 * (the last INTR is used for notifications)
2391 */
2392
2393 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
2394 for (i = 0; i < n + m + 2; i++)
2395 enic->msix_entry[i].entry = i;
2396
717258ba
VK		 2397 /* Use multiple RQs if RSS is enabled
2398 */
2399
2400 if (ENIC_SETTING(enic, RSS) &&
2401 enic->config.intr_mode < 1 &&
01f2e4ea
SF		 2402 enic->rq_count >= n &&
2403 enic->wq_count >= m &&
2404 enic->cq_count >= n + m &&
717258ba 2405 enic->intr_count >= n + m + 2) {
01f2e4ea 2406
abbb6a37
AG		 2407 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2408 n + m + 2, n + m + 2) > 0) {
01f2e4ea 2409
717258ba
VK		 2410 enic->rq_count = n;
2411 enic->wq_count = m;
2412 enic->cq_count = n + m;
2413 enic->intr_count = n + m + 2;
01f2e4ea 2414
717258ba
VK		 2415 vnic_dev_set_intr_mode(enic->vdev,
2416 VNIC_DEV_INTR_MODE_MSIX);
2417
2418 return 0;
2419 }
2420 }
2421
2422 if (enic->config.intr_mode < 1 &&
2423 enic->rq_count >= 1 &&
2424 enic->wq_count >= m &&
2425 enic->cq_count >= 1 + m &&
2426 enic->intr_count >= 1 + m + 2) {
abbb6a37
AG		 2427 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2428 1 + m + 2, 1 + m + 2) > 0) {
717258ba
VK		 2429
2430 enic->rq_count = 1;
2431 enic->wq_count = m;
2432 enic->cq_count = 1 + m;
2433 enic->intr_count = 1 + m + 2;
2434
2435 vnic_dev_set_intr_mode(enic->vdev,
2436 VNIC_DEV_INTR_MODE_MSIX);
2437
2438 return 0;
2439 }
01f2e4ea
SF		 2440 }
2441
2442 /* Next try MSI
2443 *
2444 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
2445 */
2446
2447 if (enic->config.intr_mode < 2 &&
2448 enic->rq_count >= 1 &&
2449 enic->wq_count >= 1 &&
2450 enic->cq_count >= 2 &&
2451 enic->intr_count >= 1 &&
2452 !pci_enable_msi(enic->pdev)) {
2453
2454 enic->rq_count = 1;
2455 enic->wq_count = 1;
2456 enic->cq_count = 2;
2457 enic->intr_count = 1;
2458
2459 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
2460
2461 return 0;
2462 }
2463
2464 /* Next try INTx
2465 *
2466 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
2467 * (the first INTR is used for WQ/RQ)
2468 * (the second INTR is used for WQ/RQ errors)
2469 * (the last INTR is used for notifications)
2470 */
2471
2472 if (enic->config.intr_mode < 3 &&
2473 enic->rq_count >= 1 &&
2474 enic->wq_count >= 1 &&
2475 enic->cq_count >= 2 &&
2476 enic->intr_count >= 3) {
2477
2478 enic->rq_count = 1;
2479 enic->wq_count = 1;
2480 enic->cq_count = 2;
2481 enic->intr_count = 3;
2482
2483 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
2484
2485 return 0;
2486 }
2487
2488 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2489
2490 return -EINVAL;
2491}
2492
2493static void enic_clear_intr_mode(struct enic *enic)
2494{
2495 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2496 case VNIC_DEV_INTR_MODE_MSIX:
2497 pci_disable_msix(enic->pdev);
2498 break;
2499 case VNIC_DEV_INTR_MODE_MSI:
2500 pci_disable_msi(enic->pdev);
2501 break;
2502 default:
2503 break;
2504 }
2505
2506 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2507}
2508
f8bd9091
SF		 2509static const struct net_device_ops enic_netdev_dynamic_ops = {
2510 .ndo_open = enic_open,
2511 .ndo_stop = enic_stop,
2512 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2513 .ndo_get_stats64 = enic_get_stats,
f8bd9091 2514 .ndo_validate_addr = eth_validate_addr,
319d7e84 2515 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF		 2516 .ndo_set_mac_address = enic_set_mac_address_dynamic,
2517 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF		 2518 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2519 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2520 .ndo_tx_timeout = enic_tx_timeout,
2521 .ndo_set_vf_port = enic_set_vf_port,
2522 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 2523 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF		 2524#ifdef CONFIG_NET_POLL_CONTROLLER
2525 .ndo_poll_controller = enic_poll_controller,
2526#endif
a145df23
GV		 2527#ifdef CONFIG_RFS_ACCEL
2528 .ndo_rx_flow_steer = enic_rx_flow_steer,
2529#endif
257e7382
GV		 2530 .ndo_udp_tunnel_add = enic_udp_tunnel_add,
2531 .ndo_udp_tunnel_del = enic_udp_tunnel_del,
9c744d10 2532 .ndo_features_check = enic_features_check,
f8bd9091
SF		 2533};
2534
afe29f7a
SH		 2535static const struct net_device_ops enic_netdev_ops = {
2536 .ndo_open = enic_open,
2537 .ndo_stop = enic_stop,
00829823 2538 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2539 .ndo_get_stats64 = enic_get_stats,
afe29f7a 2540 .ndo_validate_addr = eth_validate_addr,
f8bd9091 2541 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 2542 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 2543 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH		 2544 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2545 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2546 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP		 2547 .ndo_set_vf_port = enic_set_vf_port,
2548 .ndo_get_vf_port = enic_get_vf_port,
2549 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH		 2550#ifdef CONFIG_NET_POLL_CONTROLLER
2551 .ndo_poll_controller = enic_poll_controller,
2552#endif
a145df23
GV		 2553#ifdef CONFIG_RFS_ACCEL
2554 .ndo_rx_flow_steer = enic_rx_flow_steer,
2555#endif
257e7382
GV		 2556 .ndo_udp_tunnel_add = enic_udp_tunnel_add,
2557 .ndo_udp_tunnel_del = enic_udp_tunnel_del,
9c744d10 2558 .ndo_features_check = enic_features_check,
afe29f7a
SH		 2559};
2560
2fdba388 2561static void enic_dev_deinit(struct enic *enic)
6fdfa970 2562{
717258ba
VK		 2563 unsigned int i;
2564
14747cd9
GV		 2565 for (i = 0; i < enic->rq_count; i++) {
2566 napi_hash_del(&enic->napi[i]);
717258ba 2567 netif_napi_del(&enic->napi[i]);
14747cd9 2568 }
4cfe8785
GV		 2569 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2570 for (i = 0; i < enic->wq_count; i++)
2571 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
717258ba 2572
6fdfa970
SF		 2573 enic_free_vnic_resources(enic);
2574 enic_clear_intr_mode(enic);
322cf7e3 2575 enic_free_affinity_hint(enic);
6fdfa970
SF		 2576}
2577
3f255dcc
GV		 2578static void enic_kdump_kernel_config(struct enic *enic)
2579{
2580 if (is_kdump_kernel()) {
2581 dev_info(enic_get_dev(enic), "Running from within kdump kernel. Using minimal resources\n");
2582 enic->rq_count = 1;
2583 enic->wq_count = 1;
2584 enic->config.rq_desc_count = ENIC_MIN_RQ_DESCS;
2585 enic->config.wq_desc_count = ENIC_MIN_WQ_DESCS;
2586 enic->config.mtu = min_t(u16, 1500, enic->config.mtu);
2587 }
2588}
2589
2fdba388 2590static int enic_dev_init(struct enic *enic)
6fdfa970 2591{
a7a79deb 2592 struct device *dev = enic_get_dev(enic);
6fdfa970 2593 struct net_device *netdev = enic->netdev;
717258ba 2594 unsigned int i;
6fdfa970
SF		 2595 int err;
2596
ea7ea65a
VK		 2597 /* Get interrupt coalesce timer info */
2598 err = enic_dev_intr_coal_timer_info(enic);
2599 if (err) {
2600 dev_warn(dev, "Using default conversion factor for "
2601 "interrupt coalesce timer\n");
2602 vnic_dev_intr_coal_timer_info_default(enic->vdev);
2603 }
2604
6fdfa970
SF		 2605 /* Get vNIC configuration
2606 */
2607
2608 err = enic_get_vnic_config(enic);
2609 if (err) {
a7a79deb 2610 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF		 2611 return err;
2612 }
2613
2614 /* Get available resource counts
2615 */
2616
2617 enic_get_res_counts(enic);
2618
3f255dcc
GV		 2619 /* modify resource count if we are in kdump_kernel
2620 */
2621 enic_kdump_kernel_config(enic);
2622
6fdfa970
SF		 2623 /* Set interrupt mode based on resource counts and system
2624 * capabilities
2625 */
2626
2627 err = enic_set_intr_mode(enic);
2628 if (err) {
a7a79deb
VK		 2629 dev_err(dev, "Failed to set intr mode based on resource "
2630 "counts and system capabilities, aborting\n");
6fdfa970
SF		 2631 return err;
2632 }
2633
2634 /* Allocate and configure vNIC resources
2635 */
2636
2637 err = enic_alloc_vnic_resources(enic);
2638 if (err) {
a7a79deb 2639 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF		 2640 goto err_out_free_vnic_resources;
2641 }
2642
2643 enic_init_vnic_resources(enic);
2644
717258ba 2645 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2646 if (err) {
a7a79deb 2647 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF		 2648 goto err_out_free_vnic_resources;
2649 }
2650
2651 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2652 default:
717258ba 2653 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
6fdfa970
SF		 2654 break;
2655 case VNIC_DEV_INTR_MODE_MSIX:
14747cd9 2656 for (i = 0; i < enic->rq_count; i++) {
717258ba 2657 netif_napi_add(netdev, &enic->napi[i],
4cfe8785 2658 enic_poll_msix_rq, NAPI_POLL_WEIGHT);
14747cd9 2659 }
4cfe8785
GV		 2660 for (i = 0; i < enic->wq_count; i++)
2661 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
2662 enic_poll_msix_wq, NAPI_POLL_WEIGHT);
6fdfa970
SF		 2663 break;
2664 }
2665
2666 return 0;
2667
2668err_out_free_vnic_resources:
322cf7e3 2669 enic_free_affinity_hint(enic);
6fdfa970
SF		 2670 enic_clear_intr_mode(enic);
2671 enic_free_vnic_resources(enic);
2672
2673 return err;
2674}
2675
27e6c7d3
SF		 2676static void enic_iounmap(struct enic *enic)
2677{
2678 unsigned int i;
2679
2680 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2681 if (enic->bar[i].vaddr)
2682 iounmap(enic->bar[i].vaddr);
2683}
2684
1dd06ae8 2685static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2686{
a7a79deb 2687 struct device *dev = &pdev->dev;
01f2e4ea
SF		 2688 struct net_device *netdev;
2689 struct enic *enic;
2690 int using_dac = 0;
2691 unsigned int i;
2692 int err;
8749b427
RP		 2693#ifdef CONFIG_PCI_IOV
2694 int pos = 0;
2695#endif
b67f231d 2696 int num_pps = 1;
01f2e4ea 2697
01f2e4ea
SF		 2698 /* Allocate net device structure and initialize. Private
2699 * instance data is initialized to zero.
2700 */
2701
822473b6 2702 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2703 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2704 if (!netdev)
01f2e4ea 2705 return -ENOMEM;
01f2e4ea 2706
01f2e4ea
SF		 2707 pci_set_drvdata(pdev, netdev);
2708
2709 SET_NETDEV_DEV(netdev, &pdev->dev);
2710
2711 enic = netdev_priv(netdev);
2712 enic->netdev = netdev;
2713 enic->pdev = pdev;
2714
2715 /* Setup PCI resources
2716 */
2717
29046f9b 2718 err = pci_enable_device_mem(pdev);
01f2e4ea 2719 if (err) {
a7a79deb 2720 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF		 2721 goto err_out_free_netdev;
2722 }
2723
2724 err = pci_request_regions(pdev, DRV_NAME);
2725 if (err) {
a7a79deb 2726 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF		 2727 goto err_out_disable_device;
2728 }
2729
2730 pci_set_master(pdev);
2731
2732 /* Query PCI controller on system for DMA addressing
322eaa06 2733 * limitation for the device. Try 47-bit first, and
01f2e4ea
SF		 2734 * fail to 32-bit.
2735 */
2736
322eaa06 2737 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(47));
01f2e4ea 2738 if (err) {
284901a9 2739 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2740 if (err) {
a7a79deb 2741 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF		 2742 goto err_out_release_regions;
2743 }
284901a9 2744 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2745 if (err) {
a7a79deb
VK		 2746 dev_err(dev, "Unable to obtain %u-bit DMA "
2747 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF		 2748 goto err_out_release_regions;
2749 }
2750 } else {
322eaa06 2751 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(47));
01f2e4ea 2752 if (err) {
a7a79deb 2753 dev_err(dev, "Unable to obtain %u-bit DMA "
322eaa06 2754 "for consistent allocations, aborting\n", 47);
01f2e4ea
SF		 2755 goto err_out_release_regions;
2756 }
2757 using_dac = 1;
2758 }
2759
27e6c7d3 2760 /* Map vNIC resources from BAR0-5
01f2e4ea
SF		 2761 */
2762
27e6c7d3
SF		 2763 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2764 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2765 continue;
2766 enic->bar[i].len = pci_resource_len(pdev, i);
2767 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2768 if (!enic->bar[i].vaddr) {
a7a79deb 2769 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF		 2770 err = -ENODEV;
2771 goto err_out_iounmap;
2772 }
2773 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF		 2774 }
2775
2776 /* Register vNIC device
2777 */
2778
27e6c7d3
SF		 2779 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2780 ARRAY_SIZE(enic->bar));
01f2e4ea 2781 if (!enic->vdev) {
a7a79deb 2782 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF		 2783 err = -ENODEV;
2784 goto err_out_iounmap;
2785 }
2786
373fb087
GV		 2787 err = vnic_devcmd_init(enic->vdev);
2788
2789 if (err)
2790 goto err_out_vnic_unregister;
2791
8749b427
RP		 2792#ifdef CONFIG_PCI_IOV
2793 /* Get number of subvnics */
2794 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2795 if (pos) {
2796 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2797 &enic->num_vfs);
8749b427
RP		 2798 if (enic->num_vfs) {
2799 err = pci_enable_sriov(pdev, enic->num_vfs);
2800 if (err) {
2801 dev_err(dev, "SRIOV enable failed, aborting."
2802 " pci_enable_sriov() returned %d\n",
2803 err);
2804 goto err_out_vnic_unregister;
2805 }
2806 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2807 num_pps = enic->num_vfs;
8749b427
RP		 2808 }
2809 }
8749b427 2810#endif
ca2b721d 2811
3f192795 2812 /* Allocate structure for port profiles */
a1de2219 2813 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2814 if (!enic->pp) {
3f192795 2815 err = -ENOMEM;
ca2b721d 2816 goto err_out_disable_sriov_pp;
3f192795
RP		 2817 }
2818
01f2e4ea
SF		 2819 /* Issue device open to get device in known state
2820 */
2821
2822 err = enic_dev_open(enic);
2823 if (err) {
a7a79deb 2824 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2825 goto err_out_disable_sriov;
01f2e4ea
SF		 2826 }
2827
69161425
VK		 2828 /* Setup devcmd lock
2829 */
2830
2831 spin_lock_init(&enic->devcmd_lock);
0b038566 2832 spin_lock_init(&enic->enic_api_lock);
69161425
VK		 2833
2834 /*
2835 * Set ingress vlan rewrite mode before vnic initialization
2836 */
2837
2838 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2839 if (err) {
2840 dev_err(dev,
2841 "Failed to set ingress vlan rewrite mode, aborting.\n");
2842 goto err_out_dev_close;
2843 }
2844
01f2e4ea
SF		 2845 /* Issue device init to initialize the vnic-to-switch link.
2846 * We'll start with carrier off and wait for link UP
2847 * notification later to turn on carrier. We don't need
2848 * to wait here for the vnic-to-switch link initialization
2849 * to complete; link UP notification is the indication that
2850 * the process is complete.
2851 */
2852
2853 netif_carrier_off(netdev);
2854
a7a79deb
VK		 2855 /* Do not call dev_init for a dynamic vnic.
2856 * For a dynamic vnic, init_prov_info will be
2857 * called later by an upper layer.
2858 */
2859
2b68c181 2860 if (!enic_is_dynamic(enic)) {
f8bd9091
SF		 2861 err = vnic_dev_init(enic->vdev, 0);
2862 if (err) {
a7a79deb 2863 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF		 2864 goto err_out_dev_close;
2865 }
01f2e4ea
SF		 2866 }
2867
6fdfa970 2868 err = enic_dev_init(enic);
01f2e4ea 2869 if (err) {
a7a79deb 2870 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF		 2871 goto err_out_dev_close;
2872 }
2873
822473b6 2874 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2875 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2876
383ab92f 2877 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF		 2878 */
2879
e99e88a9 2880 timer_setup(&enic->notify_timer, enic_notify_timer, 0);
01f2e4ea 2881
3256d29f 2882 enic_rfs_flw_tbl_init(enic);
7c2ce6e6 2883 enic_set_rx_coal_setting(enic);
01f2e4ea 2884 INIT_WORK(&enic->reset, enic_reset);
937317c7 2885 INIT_WORK(&enic->tx_hang_reset, enic_tx_hang_reset);
c97c894d 2886 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF		 2887
2888 for (i = 0; i < enic->wq_count; i++)
2889 spin_lock_init(&enic->wq_lock[i]);
2890
01f2e4ea
SF		 2891 /* Register net device
2892 */
2893
2894 enic->port_mtu = enic->config.mtu;
2895 (void)enic_change_mtu(netdev, enic->port_mtu);
2896
2897 err = enic_set_mac_addr(netdev, enic->mac_addr);
2898 if (err) {
a7a79deb 2899 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2900 goto err_out_dev_deinit;
01f2e4ea
SF		 2901 }
2902
7c844599 2903 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
7c2ce6e6
SS		 2904 /* rx coalesce time already got initialized. This gets used
2905 * if adaptive coal is turned off
2906 */
7c844599
SF		 2907 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2908
7335903c 2909 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF		 2910 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2911 else
2912 netdev->netdev_ops = &enic_netdev_ops;
2913
01f2e4ea 2914 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2915 enic_set_ethtool_ops(netdev);
01f2e4ea 2916
f646968f 2917 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2918 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2919 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK		 2920 enic->loop_enable = 1;
2921 enic->loop_tag = enic->config.loop_tag;
2922 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2923 }
01f2e4ea 2924 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2925 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2926 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2927 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2928 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2929 if (ENIC_SETTING(enic, RSS))
2930 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM		 2931 if (ENIC_SETTING(enic, RXCSUM))
2932 netdev->hw_features |= NETIF_F_RXCSUM;
257e7382
GV		 2933 if (ENIC_SETTING(enic, VXLAN)) {
2934 u64 patch_level;
d1179094 2935 u64 a1 = 0;
257e7382
GV		 2936
2937 netdev->hw_enc_features |= NETIF_F_RXCSUM |
2938 NETIF_F_TSO |
d1179094 2939 NETIF_F_TSO6 |
257e7382
GV		 2940 NETIF_F_TSO_ECN |
2941 NETIF_F_GSO_UDP_TUNNEL |
2942 NETIF_F_HW_CSUM |
2943 NETIF_F_GSO_UDP_TUNNEL_CSUM;
2944 netdev->hw_features |= netdev->hw_enc_features;
2945 /* get bit mask from hw about supported offload bit level
2946 * BIT(0) = fw supports patch_level 0
2947 * fcoe bit = encap
2948 * fcoe_fc_crc_ok = outer csum ok
2949 * BIT(1) = always set by fw
2950 * BIT(2) = fw supports patch_level 2
2951 * BIT(0) in rss_hash = encap
2952 * BIT(1,2) in rss_hash = outer_ip_csum_ok/
2953 * outer_tcp_csum_ok
2954 * used in enic_rq_indicate_buf
2955 */
2956 err = vnic_dev_get_supported_feature_ver(enic->vdev,
2957 VIC_FEATURE_VXLAN,
d1179094 2958 &patch_level, &a1);
257e7382
GV		 2959 if (err)
2960 patch_level = 0;
d1179094 2961 enic->vxlan.flags = (u8)a1;
257e7382
GV		 2962 /* mask bits that are supported by driver
2963 */
2964 patch_level &= BIT_ULL(0) | BIT_ULL(2);
2965 patch_level = fls(patch_level);
2966 patch_level = patch_level ? patch_level - 1 : 0;
2967 enic->vxlan.patch_level = patch_level;
2968 }
5ec8f9b8
MM		 2969
2970 netdev->features |= netdev->hw_features;
e7600449 2971 netdev->vlan_features |= netdev->features;
5ec8f9b8 2972
a145df23
GV		 2973#ifdef CONFIG_RFS_ACCEL
2974 netdev->hw_features |= NETIF_F_NTUPLE;
2975#endif
2976
01f2e4ea
SF		 2977 if (using_dac)
2978 netdev->features |= NETIF_F_HIGHDMA;
2979
01789349
JP		 2980 netdev->priv_flags |= IFF_UNICAST_FLT;
2981
44770e11
JW		 2982 /* MTU range: 68 - 9000 */
2983 netdev->min_mtu = ENIC_MIN_MTU;
2984 netdev->max_mtu = ENIC_MAX_MTU;
2985
01f2e4ea
SF		 2986 err = register_netdev(netdev);
2987 if (err) {
a7a79deb 2988 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 2989 goto err_out_dev_deinit;
01f2e4ea 2990 }
a03bb56e 2991 enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
01f2e4ea
SF		 2992
2993 return 0;
2994
6fdfa970
SF		 2995err_out_dev_deinit:
2996 enic_dev_deinit(enic);
01f2e4ea
SF		 2997err_out_dev_close:
2998 vnic_dev_close(enic->vdev);
8749b427 2999err_out_disable_sriov:
ca2b721d
RP		 3000 kfree(enic->pp);
3001err_out_disable_sriov_pp:
8749b427
RP		 3002#ifdef CONFIG_PCI_IOV
3003 if (enic_sriov_enabled(enic)) {
3004 pci_disable_sriov(pdev);
3005 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
3006 }
8749b427 3007#endif
1a69205c 3008err_out_vnic_unregister:
35d87e33 3009 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF		 3010err_out_iounmap:
3011 enic_iounmap(enic);
3012err_out_release_regions:
3013 pci_release_regions(pdev);
3014err_out_disable_device:
3015 pci_disable_device(pdev);
3016err_out_free_netdev:
01f2e4ea
SF		 3017 free_netdev(netdev);
3018
3019 return err;
3020}
3021
854de92f 3022static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF		 3023{
3024 struct net_device *netdev = pci_get_drvdata(pdev);
3025
3026 if (netdev) {
3027 struct enic *enic = netdev_priv(netdev);
3028
23f333a2 3029 cancel_work_sync(&enic->reset);
c97c894d 3030 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 3031 unregister_netdev(netdev);
6fdfa970 3032 enic_dev_deinit(enic);
01f2e4ea 3033 vnic_dev_close(enic->vdev);
8749b427
RP		 3034#ifdef CONFIG_PCI_IOV
3035 if (enic_sriov_enabled(enic)) {
3036 pci_disable_sriov(pdev);
3037 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
3038 }
3039#endif
3f192795 3040 kfree(enic->pp);
01f2e4ea
SF		 3041 vnic_dev_unregister(enic->vdev);
3042 enic_iounmap(enic);
3043 pci_release_regions(pdev);
3044 pci_disable_device(pdev);
01f2e4ea
SF		 3045 free_netdev(netdev);
3046 }
3047}
3048
3049static struct pci_driver enic_driver = {
3050 .name = DRV_NAME,
3051 .id_table = enic_id_table,
3052 .probe = enic_probe,
854de92f 3053 .remove = enic_remove,
01f2e4ea
SF		 3054};
3055
3056static int __init enic_init_module(void)
3057{
a7a79deb 3058 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
01f2e4ea
SF		 3059
3060 return pci_register_driver(&enic_driver);
3061}
3062
3063static void __exit enic_cleanup_module(void)
3064{
3065 pci_unregister_driver(&enic_driver);
3066}
3067
3068module_init(enic_init_module);
3069module_exit(enic_cleanup_module);
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