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01f2e4ea | 1 | /* |
29046f9b | 2 | * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. |
01f2e4ea SF |
3 | * Copyright 2007 Nuova Systems, Inc. All rights reserved. |
4 | * | |
5 | * This program is free software; you may redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
10 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
11 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
12 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
13 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
15 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
16 | * SOFTWARE. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/string.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/init.h> | |
a6b7a407 | 26 | #include <linux/interrupt.h> |
01f2e4ea SF |
27 | #include <linux/workqueue.h> |
28 | #include <linux/pci.h> | |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/etherdevice.h> | |
01789349 | 31 | #include <linux/if.h> |
01f2e4ea SF |
32 | #include <linux/if_ether.h> |
33 | #include <linux/if_vlan.h> | |
01f2e4ea SF |
34 | #include <linux/in.h> |
35 | #include <linux/ip.h> | |
36 | #include <linux/ipv6.h> | |
37 | #include <linux/tcp.h> | |
29046f9b | 38 | #include <linux/rtnetlink.h> |
70c71606 | 39 | #include <linux/prefetch.h> |
b7c6bfb7 | 40 | #include <net/ip6_checksum.h> |
7c2ce6e6 | 41 | #include <linux/ktime.h> |
322cf7e3 | 42 | #include <linux/numa.h> |
b6e97c13 GV |
43 | #ifdef CONFIG_RFS_ACCEL |
44 | #include <linux/cpu_rmap.h> | |
45 | #endif | |
14747cd9 GV |
46 | #ifdef CONFIG_NET_RX_BUSY_POLL |
47 | #include <net/busy_poll.h> | |
48 | #endif | |
3f255dcc | 49 | #include <linux/crash_dump.h> |
01f2e4ea SF |
50 | |
51 | #include "cq_enet_desc.h" | |
52 | #include "vnic_dev.h" | |
53 | #include "vnic_intr.h" | |
54 | #include "vnic_stats.h" | |
f8bd9091 | 55 | #include "vnic_vic.h" |
01f2e4ea SF |
56 | #include "enic_res.h" |
57 | #include "enic.h" | |
51987461 | 58 | #include "enic_dev.h" |
b3abfbd2 | 59 | #include "enic_pp.h" |
a145df23 | 60 | #include "enic_clsf.h" |
01f2e4ea SF |
61 | |
62 | #define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ) | |
ea0d7d91 SF |
63 | #define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS) |
64 | #define MAX_TSO (1 << 16) | |
65 | #define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1) | |
66 | ||
67 | #define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */ | |
f8bd9091 | 68 | #define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */ |
3a4adef5 | 69 | #define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */ |
01f2e4ea | 70 | |
a03bb56e GV |
71 | #define RX_COPYBREAK_DEFAULT 256 |
72 | ||
01f2e4ea | 73 | /* Supported devices */ |
9baa3c34 | 74 | static const struct pci_device_id enic_id_table[] = { |
ea0d7d91 | 75 | { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) }, |
f8bd9091 | 76 | { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) }, |
3a4adef5 | 77 | { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) }, |
01f2e4ea SF |
78 | { 0, } /* end of table */ |
79 | }; | |
80 | ||
81 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
82 | MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>"); | |
83 | MODULE_LICENSE("GPL"); | |
84 | MODULE_VERSION(DRV_VERSION); | |
85 | MODULE_DEVICE_TABLE(pci, enic_id_table); | |
86 | ||
7c2ce6e6 SS |
87 | #define ENIC_LARGE_PKT_THRESHOLD 1000 |
88 | #define ENIC_MAX_COALESCE_TIMERS 10 | |
89 | /* Interrupt moderation table, which will be used to decide the | |
90 | * coalescing timer values | |
91 | * {rx_rate in Mbps, mapping percentage of the range} | |
92 | */ | |
57ae84a0 | 93 | static struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = { |
7c2ce6e6 SS |
94 | {4000, 0}, |
95 | {4400, 10}, | |
96 | {5060, 20}, | |
97 | {5230, 30}, | |
98 | {5540, 40}, | |
99 | {5820, 50}, | |
100 | {6120, 60}, | |
101 | {6435, 70}, | |
102 | {6745, 80}, | |
103 | {7000, 90}, | |
104 | {0xFFFFFFFF, 100} | |
105 | }; | |
106 | ||
107 | /* This table helps the driver to pick different ranges for rx coalescing | |
108 | * timer depending on the link speed. | |
109 | */ | |
57ae84a0 | 110 | static struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = { |
7c2ce6e6 SS |
111 | {0, 0}, /* 0 - 4 Gbps */ |
112 | {0, 3}, /* 4 - 10 Gbps */ | |
113 | {3, 6}, /* 10 - 40 Gbps */ | |
114 | }; | |
115 | ||
322cf7e3 GV |
116 | static void enic_init_affinity_hint(struct enic *enic) |
117 | { | |
118 | int numa_node = dev_to_node(&enic->pdev->dev); | |
119 | int i; | |
120 | ||
121 | for (i = 0; i < enic->intr_count; i++) { | |
122 | if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i) || | |
123 | (enic->msix[i].affinity_mask && | |
124 | !cpumask_empty(enic->msix[i].affinity_mask))) | |
125 | continue; | |
126 | if (zalloc_cpumask_var(&enic->msix[i].affinity_mask, | |
127 | GFP_KERNEL)) | |
128 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), | |
129 | enic->msix[i].affinity_mask); | |
130 | } | |
131 | } | |
132 | ||
133 | static void enic_free_affinity_hint(struct enic *enic) | |
134 | { | |
135 | int i; | |
136 | ||
137 | for (i = 0; i < enic->intr_count; i++) { | |
138 | if (enic_is_err_intr(enic, i) || enic_is_notify_intr(enic, i)) | |
139 | continue; | |
140 | free_cpumask_var(enic->msix[i].affinity_mask); | |
141 | } | |
142 | } | |
143 | ||
144 | static void enic_set_affinity_hint(struct enic *enic) | |
145 | { | |
146 | int i; | |
147 | int err; | |
148 | ||
149 | for (i = 0; i < enic->intr_count; i++) { | |
150 | if (enic_is_err_intr(enic, i) || | |
151 | enic_is_notify_intr(enic, i) || | |
152 | !enic->msix[i].affinity_mask || | |
153 | cpumask_empty(enic->msix[i].affinity_mask)) | |
154 | continue; | |
155 | err = irq_set_affinity_hint(enic->msix_entry[i].vector, | |
156 | enic->msix[i].affinity_mask); | |
157 | if (err) | |
158 | netdev_warn(enic->netdev, "irq_set_affinity_hint failed, err %d\n", | |
159 | err); | |
160 | } | |
161 | ||
162 | for (i = 0; i < enic->wq_count; i++) { | |
163 | int wq_intr = enic_msix_wq_intr(enic, i); | |
164 | ||
165 | if (enic->msix[wq_intr].affinity_mask && | |
166 | !cpumask_empty(enic->msix[wq_intr].affinity_mask)) | |
167 | netif_set_xps_queue(enic->netdev, | |
168 | enic->msix[wq_intr].affinity_mask, | |
169 | i); | |
170 | } | |
171 | } | |
172 | ||
173 | static void enic_unset_affinity_hint(struct enic *enic) | |
174 | { | |
175 | int i; | |
176 | ||
177 | for (i = 0; i < enic->intr_count; i++) | |
178 | irq_set_affinity_hint(enic->msix_entry[i].vector, NULL); | |
179 | } | |
180 | ||
3f192795 | 181 | int enic_is_dynamic(struct enic *enic) |
f8bd9091 SF |
182 | { |
183 | return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN; | |
184 | } | |
185 | ||
8749b427 RP |
186 | int enic_sriov_enabled(struct enic *enic) |
187 | { | |
188 | return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0; | |
189 | } | |
190 | ||
3a4adef5 RP |
191 | static int enic_is_sriov_vf(struct enic *enic) |
192 | { | |
193 | return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF; | |
194 | } | |
195 | ||
889d13f5 RP |
196 | int enic_is_valid_vf(struct enic *enic, int vf) |
197 | { | |
198 | #ifdef CONFIG_PCI_IOV | |
199 | return vf >= 0 && vf < enic->num_vfs; | |
200 | #else | |
201 | return 0; | |
202 | #endif | |
203 | } | |
204 | ||
01f2e4ea SF |
205 | static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf) |
206 | { | |
207 | struct enic *enic = vnic_dev_priv(wq->vdev); | |
208 | ||
209 | if (buf->sop) | |
210 | pci_unmap_single(enic->pdev, buf->dma_addr, | |
211 | buf->len, PCI_DMA_TODEVICE); | |
212 | else | |
213 | pci_unmap_page(enic->pdev, buf->dma_addr, | |
214 | buf->len, PCI_DMA_TODEVICE); | |
215 | ||
216 | if (buf->os_buf) | |
217 | dev_kfree_skb_any(buf->os_buf); | |
218 | } | |
219 | ||
220 | static void enic_wq_free_buf(struct vnic_wq *wq, | |
221 | struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque) | |
222 | { | |
223 | enic_free_wq_buf(wq, buf); | |
224 | } | |
225 | ||
226 | static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc, | |
227 | u8 type, u16 q_number, u16 completed_index, void *opaque) | |
228 | { | |
229 | struct enic *enic = vnic_dev_priv(vdev); | |
230 | ||
231 | spin_lock(&enic->wq_lock[q_number]); | |
232 | ||
233 | vnic_wq_service(&enic->wq[q_number], cq_desc, | |
234 | completed_index, enic_wq_free_buf, | |
235 | opaque); | |
236 | ||
822473b6 | 237 | if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) && |
ea0d7d91 SF |
238 | vnic_wq_desc_avail(&enic->wq[q_number]) >= |
239 | (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)) | |
822473b6 | 240 | netif_wake_subqueue(enic->netdev, q_number); |
01f2e4ea SF |
241 | |
242 | spin_unlock(&enic->wq_lock[q_number]); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
cc809237 | 247 | static bool enic_log_q_error(struct enic *enic) |
01f2e4ea SF |
248 | { |
249 | unsigned int i; | |
250 | u32 error_status; | |
cc809237 | 251 | bool err = false; |
01f2e4ea SF |
252 | |
253 | for (i = 0; i < enic->wq_count; i++) { | |
254 | error_status = vnic_wq_error_status(&enic->wq[i]); | |
cc809237 | 255 | err |= error_status; |
01f2e4ea | 256 | if (error_status) |
a7a79deb VK |
257 | netdev_err(enic->netdev, "WQ[%d] error_status %d\n", |
258 | i, error_status); | |
01f2e4ea SF |
259 | } |
260 | ||
261 | for (i = 0; i < enic->rq_count; i++) { | |
262 | error_status = vnic_rq_error_status(&enic->rq[i]); | |
cc809237 | 263 | err |= error_status; |
01f2e4ea | 264 | if (error_status) |
a7a79deb VK |
265 | netdev_err(enic->netdev, "RQ[%d] error_status %d\n", |
266 | i, error_status); | |
01f2e4ea | 267 | } |
cc809237 GV |
268 | |
269 | return err; | |
01f2e4ea SF |
270 | } |
271 | ||
383ab92f | 272 | static void enic_msglvl_check(struct enic *enic) |
01f2e4ea | 273 | { |
383ab92f | 274 | u32 msg_enable = vnic_dev_msg_lvl(enic->vdev); |
01f2e4ea | 275 | |
383ab92f | 276 | if (msg_enable != enic->msg_enable) { |
a7a79deb VK |
277 | netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n", |
278 | enic->msg_enable, msg_enable); | |
383ab92f | 279 | enic->msg_enable = msg_enable; |
01f2e4ea SF |
280 | } |
281 | } | |
282 | ||
283 | static void enic_mtu_check(struct enic *enic) | |
284 | { | |
285 | u32 mtu = vnic_dev_mtu(enic->vdev); | |
a7a79deb | 286 | struct net_device *netdev = enic->netdev; |
01f2e4ea | 287 | |
491598a4 | 288 | if (mtu && mtu != enic->port_mtu) { |
7c844599 | 289 | enic->port_mtu = mtu; |
7335903c | 290 | if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) { |
c97c894d RP |
291 | mtu = max_t(int, ENIC_MIN_MTU, |
292 | min_t(int, ENIC_MAX_MTU, mtu)); | |
293 | if (mtu != netdev->mtu) | |
294 | schedule_work(&enic->change_mtu_work); | |
295 | } else { | |
296 | if (mtu < netdev->mtu) | |
297 | netdev_warn(netdev, | |
298 | "interface MTU (%d) set higher " | |
299 | "than switch port MTU (%d)\n", | |
300 | netdev->mtu, mtu); | |
301 | } | |
01f2e4ea SF |
302 | } |
303 | } | |
304 | ||
383ab92f | 305 | static void enic_link_check(struct enic *enic) |
01f2e4ea | 306 | { |
383ab92f VK |
307 | int link_status = vnic_dev_link_status(enic->vdev); |
308 | int carrier_ok = netif_carrier_ok(enic->netdev); | |
01f2e4ea | 309 | |
383ab92f | 310 | if (link_status && !carrier_ok) { |
a7a79deb | 311 | netdev_info(enic->netdev, "Link UP\n"); |
383ab92f VK |
312 | netif_carrier_on(enic->netdev); |
313 | } else if (!link_status && carrier_ok) { | |
a7a79deb | 314 | netdev_info(enic->netdev, "Link DOWN\n"); |
383ab92f | 315 | netif_carrier_off(enic->netdev); |
01f2e4ea SF |
316 | } |
317 | } | |
318 | ||
319 | static void enic_notify_check(struct enic *enic) | |
320 | { | |
321 | enic_msglvl_check(enic); | |
322 | enic_mtu_check(enic); | |
323 | enic_link_check(enic); | |
324 | } | |
325 | ||
326 | #define ENIC_TEST_INTR(pba, i) (pba & (1 << i)) | |
327 | ||
328 | static irqreturn_t enic_isr_legacy(int irq, void *data) | |
329 | { | |
330 | struct net_device *netdev = data; | |
331 | struct enic *enic = netdev_priv(netdev); | |
717258ba VK |
332 | unsigned int io_intr = enic_legacy_io_intr(); |
333 | unsigned int err_intr = enic_legacy_err_intr(); | |
334 | unsigned int notify_intr = enic_legacy_notify_intr(); | |
01f2e4ea SF |
335 | u32 pba; |
336 | ||
717258ba | 337 | vnic_intr_mask(&enic->intr[io_intr]); |
01f2e4ea SF |
338 | |
339 | pba = vnic_intr_legacy_pba(enic->legacy_pba); | |
340 | if (!pba) { | |
717258ba | 341 | vnic_intr_unmask(&enic->intr[io_intr]); |
01f2e4ea SF |
342 | return IRQ_NONE; /* not our interrupt */ |
343 | } | |
344 | ||
717258ba | 345 | if (ENIC_TEST_INTR(pba, notify_intr)) { |
01f2e4ea | 346 | enic_notify_check(enic); |
2b0c2e2d | 347 | vnic_intr_return_all_credits(&enic->intr[notify_intr]); |
ed8af6b2 | 348 | } |
01f2e4ea | 349 | |
717258ba VK |
350 | if (ENIC_TEST_INTR(pba, err_intr)) { |
351 | vnic_intr_return_all_credits(&enic->intr[err_intr]); | |
01f2e4ea SF |
352 | enic_log_q_error(enic); |
353 | /* schedule recovery from WQ/RQ error */ | |
354 | schedule_work(&enic->reset); | |
355 | return IRQ_HANDLED; | |
356 | } | |
357 | ||
db40b3f5 GV |
358 | if (ENIC_TEST_INTR(pba, io_intr)) |
359 | napi_schedule_irqoff(&enic->napi[0]); | |
360 | else | |
717258ba | 361 | vnic_intr_unmask(&enic->intr[io_intr]); |
01f2e4ea SF |
362 | |
363 | return IRQ_HANDLED; | |
364 | } | |
365 | ||
366 | static irqreturn_t enic_isr_msi(int irq, void *data) | |
367 | { | |
368 | struct enic *enic = data; | |
369 | ||
370 | /* With MSI, there is no sharing of interrupts, so this is | |
371 | * our interrupt and there is no need to ack it. The device | |
372 | * is not providing per-vector masking, so the OS will not | |
373 | * write to PCI config space to mask/unmask the interrupt. | |
374 | * We're using mask_on_assertion for MSI, so the device | |
375 | * automatically masks the interrupt when the interrupt is | |
376 | * generated. Later, when exiting polling, the interrupt | |
377 | * will be unmasked (see enic_poll). | |
378 | * | |
379 | * Also, the device uses the same PCIe Traffic Class (TC) | |
380 | * for Memory Write data and MSI, so there are no ordering | |
381 | * issues; the MSI will always arrive at the Root Complex | |
382 | * _after_ corresponding Memory Writes (i.e. descriptor | |
383 | * writes). | |
384 | */ | |
385 | ||
db40b3f5 | 386 | napi_schedule_irqoff(&enic->napi[0]); |
01f2e4ea SF |
387 | |
388 | return IRQ_HANDLED; | |
389 | } | |
390 | ||
4cfe8785 | 391 | static irqreturn_t enic_isr_msix(int irq, void *data) |
01f2e4ea | 392 | { |
717258ba | 393 | struct napi_struct *napi = data; |
01f2e4ea | 394 | |
db40b3f5 | 395 | napi_schedule_irqoff(napi); |
01f2e4ea SF |
396 | |
397 | return IRQ_HANDLED; | |
398 | } | |
399 | ||
01f2e4ea SF |
400 | static irqreturn_t enic_isr_msix_err(int irq, void *data) |
401 | { | |
402 | struct enic *enic = data; | |
717258ba | 403 | unsigned int intr = enic_msix_err_intr(enic); |
01f2e4ea | 404 | |
717258ba | 405 | vnic_intr_return_all_credits(&enic->intr[intr]); |
ed8af6b2 | 406 | |
cc809237 GV |
407 | if (enic_log_q_error(enic)) |
408 | /* schedule recovery from WQ/RQ error */ | |
409 | schedule_work(&enic->reset); | |
01f2e4ea SF |
410 | |
411 | return IRQ_HANDLED; | |
412 | } | |
413 | ||
414 | static irqreturn_t enic_isr_msix_notify(int irq, void *data) | |
415 | { | |
416 | struct enic *enic = data; | |
717258ba | 417 | unsigned int intr = enic_msix_notify_intr(enic); |
01f2e4ea SF |
418 | |
419 | enic_notify_check(enic); | |
2b0c2e2d | 420 | vnic_intr_return_all_credits(&enic->intr[intr]); |
01f2e4ea SF |
421 | |
422 | return IRQ_HANDLED; | |
423 | } | |
424 | ||
065df159 GV |
425 | static int enic_queue_wq_skb_cont(struct enic *enic, struct vnic_wq *wq, |
426 | struct sk_buff *skb, unsigned int len_left, | |
427 | int loopback) | |
01f2e4ea | 428 | { |
9e903e08 | 429 | const skb_frag_t *frag; |
065df159 | 430 | dma_addr_t dma_addr; |
01f2e4ea SF |
431 | |
432 | /* Queue additional data fragments */ | |
433 | for (frag = skb_shinfo(skb)->frags; len_left; frag++) { | |
9e903e08 | 434 | len_left -= skb_frag_size(frag); |
065df159 GV |
435 | dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 0, |
436 | skb_frag_size(frag), | |
437 | DMA_TO_DEVICE); | |
438 | if (unlikely(enic_dma_map_check(enic, dma_addr))) | |
439 | return -ENOMEM; | |
440 | enic_queue_wq_desc_cont(wq, skb, dma_addr, skb_frag_size(frag), | |
441 | (len_left == 0), /* EOP? */ | |
442 | loopback); | |
01f2e4ea | 443 | } |
065df159 GV |
444 | |
445 | return 0; | |
01f2e4ea SF |
446 | } |
447 | ||
065df159 GV |
448 | static int enic_queue_wq_skb_vlan(struct enic *enic, struct vnic_wq *wq, |
449 | struct sk_buff *skb, int vlan_tag_insert, | |
450 | unsigned int vlan_tag, int loopback) | |
01f2e4ea SF |
451 | { |
452 | unsigned int head_len = skb_headlen(skb); | |
453 | unsigned int len_left = skb->len - head_len; | |
454 | int eop = (len_left == 0); | |
065df159 GV |
455 | dma_addr_t dma_addr; |
456 | int err = 0; | |
457 | ||
458 | dma_addr = pci_map_single(enic->pdev, skb->data, head_len, | |
459 | PCI_DMA_TODEVICE); | |
460 | if (unlikely(enic_dma_map_check(enic, dma_addr))) | |
461 | return -ENOMEM; | |
01f2e4ea | 462 | |
ea0d7d91 SF |
463 | /* Queue the main skb fragment. The fragments are no larger |
464 | * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less | |
465 | * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor | |
466 | * per fragment is queued. | |
467 | */ | |
065df159 GV |
468 | enic_queue_wq_desc(wq, skb, dma_addr, head_len, vlan_tag_insert, |
469 | vlan_tag, eop, loopback); | |
01f2e4ea SF |
470 | |
471 | if (!eop) | |
065df159 GV |
472 | err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback); |
473 | ||
474 | return err; | |
01f2e4ea SF |
475 | } |
476 | ||
065df159 GV |
477 | static int enic_queue_wq_skb_csum_l4(struct enic *enic, struct vnic_wq *wq, |
478 | struct sk_buff *skb, int vlan_tag_insert, | |
479 | unsigned int vlan_tag, int loopback) | |
01f2e4ea SF |
480 | { |
481 | unsigned int head_len = skb_headlen(skb); | |
482 | unsigned int len_left = skb->len - head_len; | |
0d0b1672 | 483 | unsigned int hdr_len = skb_checksum_start_offset(skb); |
01f2e4ea SF |
484 | unsigned int csum_offset = hdr_len + skb->csum_offset; |
485 | int eop = (len_left == 0); | |
065df159 GV |
486 | dma_addr_t dma_addr; |
487 | int err = 0; | |
488 | ||
489 | dma_addr = pci_map_single(enic->pdev, skb->data, head_len, | |
490 | PCI_DMA_TODEVICE); | |
491 | if (unlikely(enic_dma_map_check(enic, dma_addr))) | |
492 | return -ENOMEM; | |
01f2e4ea | 493 | |
ea0d7d91 SF |
494 | /* Queue the main skb fragment. The fragments are no larger |
495 | * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less | |
496 | * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor | |
497 | * per fragment is queued. | |
498 | */ | |
065df159 GV |
499 | enic_queue_wq_desc_csum_l4(wq, skb, dma_addr, head_len, csum_offset, |
500 | hdr_len, vlan_tag_insert, vlan_tag, eop, | |
501 | loopback); | |
01f2e4ea SF |
502 | |
503 | if (!eop) | |
065df159 GV |
504 | err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback); |
505 | ||
506 | return err; | |
01f2e4ea SF |
507 | } |
508 | ||
065df159 GV |
509 | static int enic_queue_wq_skb_tso(struct enic *enic, struct vnic_wq *wq, |
510 | struct sk_buff *skb, unsigned int mss, | |
511 | int vlan_tag_insert, unsigned int vlan_tag, | |
512 | int loopback) | |
01f2e4ea | 513 | { |
ea0d7d91 SF |
514 | unsigned int frag_len_left = skb_headlen(skb); |
515 | unsigned int len_left = skb->len - frag_len_left; | |
01f2e4ea SF |
516 | unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
517 | int eop = (len_left == 0); | |
ea0d7d91 SF |
518 | unsigned int len; |
519 | dma_addr_t dma_addr; | |
520 | unsigned int offset = 0; | |
521 | skb_frag_t *frag; | |
01f2e4ea SF |
522 | |
523 | /* Preload TCP csum field with IP pseudo hdr calculated | |
524 | * with IP length set to zero. HW will later add in length | |
525 | * to each TCP segment resulting from the TSO. | |
526 | */ | |
527 | ||
09640e63 | 528 | if (skb->protocol == cpu_to_be16(ETH_P_IP)) { |
01f2e4ea SF |
529 | ip_hdr(skb)->check = 0; |
530 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr, | |
531 | ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); | |
09640e63 | 532 | } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { |
01f2e4ea SF |
533 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, |
534 | &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); | |
535 | } | |
536 | ||
ea0d7d91 SF |
537 | /* Queue WQ_ENET_MAX_DESC_LEN length descriptors |
538 | * for the main skb fragment | |
539 | */ | |
540 | while (frag_len_left) { | |
541 | len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN); | |
065df159 GV |
542 | dma_addr = pci_map_single(enic->pdev, skb->data + offset, len, |
543 | PCI_DMA_TODEVICE); | |
544 | if (unlikely(enic_dma_map_check(enic, dma_addr))) | |
545 | return -ENOMEM; | |
546 | enic_queue_wq_desc_tso(wq, skb, dma_addr, len, mss, hdr_len, | |
547 | vlan_tag_insert, vlan_tag, | |
548 | eop && (len == frag_len_left), loopback); | |
ea0d7d91 SF |
549 | frag_len_left -= len; |
550 | offset += len; | |
551 | } | |
01f2e4ea | 552 | |
ea0d7d91 | 553 | if (eop) |
065df159 | 554 | return 0; |
ea0d7d91 SF |
555 | |
556 | /* Queue WQ_ENET_MAX_DESC_LEN length descriptors | |
557 | * for additional data fragments | |
558 | */ | |
559 | for (frag = skb_shinfo(skb)->frags; len_left; frag++) { | |
9e903e08 ED |
560 | len_left -= skb_frag_size(frag); |
561 | frag_len_left = skb_frag_size(frag); | |
4bf5adbf | 562 | offset = 0; |
ea0d7d91 SF |
563 | |
564 | while (frag_len_left) { | |
565 | len = min(frag_len_left, | |
566 | (unsigned int)WQ_ENET_MAX_DESC_LEN); | |
4bf5adbf IC |
567 | dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, |
568 | offset, len, | |
5d6bcdfe | 569 | DMA_TO_DEVICE); |
065df159 GV |
570 | if (unlikely(enic_dma_map_check(enic, dma_addr))) |
571 | return -ENOMEM; | |
572 | enic_queue_wq_desc_cont(wq, skb, dma_addr, len, | |
573 | (len_left == 0) && | |
574 | (len == frag_len_left),/*EOP*/ | |
575 | loopback); | |
ea0d7d91 SF |
576 | frag_len_left -= len; |
577 | offset += len; | |
578 | } | |
579 | } | |
065df159 GV |
580 | |
581 | return 0; | |
01f2e4ea SF |
582 | } |
583 | ||
584 | static inline void enic_queue_wq_skb(struct enic *enic, | |
585 | struct vnic_wq *wq, struct sk_buff *skb) | |
586 | { | |
587 | unsigned int mss = skb_shinfo(skb)->gso_size; | |
588 | unsigned int vlan_tag = 0; | |
589 | int vlan_tag_insert = 0; | |
1825aca6 | 590 | int loopback = 0; |
065df159 | 591 | int err; |
01f2e4ea | 592 | |
df8a39de | 593 | if (skb_vlan_tag_present(skb)) { |
01f2e4ea SF |
594 | /* VLAN tag from trunking driver */ |
595 | vlan_tag_insert = 1; | |
df8a39de | 596 | vlan_tag = skb_vlan_tag_get(skb); |
1825aca6 VK |
597 | } else if (enic->loop_enable) { |
598 | vlan_tag = enic->loop_tag; | |
599 | loopback = 1; | |
01f2e4ea SF |
600 | } |
601 | ||
602 | if (mss) | |
065df159 GV |
603 | err = enic_queue_wq_skb_tso(enic, wq, skb, mss, |
604 | vlan_tag_insert, vlan_tag, | |
605 | loopback); | |
01f2e4ea | 606 | else if (skb->ip_summed == CHECKSUM_PARTIAL) |
065df159 GV |
607 | err = enic_queue_wq_skb_csum_l4(enic, wq, skb, vlan_tag_insert, |
608 | vlan_tag, loopback); | |
01f2e4ea | 609 | else |
065df159 GV |
610 | err = enic_queue_wq_skb_vlan(enic, wq, skb, vlan_tag_insert, |
611 | vlan_tag, loopback); | |
612 | if (unlikely(err)) { | |
613 | struct vnic_wq_buf *buf; | |
614 | ||
615 | buf = wq->to_use->prev; | |
616 | /* while not EOP of previous pkt && queue not empty. | |
617 | * For all non EOP bufs, os_buf is NULL. | |
618 | */ | |
619 | while (!buf->os_buf && (buf->next != wq->to_clean)) { | |
620 | enic_free_wq_buf(wq, buf); | |
621 | wq->ring.desc_avail++; | |
622 | buf = buf->prev; | |
623 | } | |
624 | wq->to_use = buf->next; | |
625 | dev_kfree_skb(skb); | |
626 | } | |
01f2e4ea SF |
627 | } |
628 | ||
ed8af6b2 | 629 | /* netif_tx_lock held, process context with BHs disabled, or BH */ |
61357325 | 630 | static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb, |
d87fd25d | 631 | struct net_device *netdev) |
01f2e4ea SF |
632 | { |
633 | struct enic *enic = netdev_priv(netdev); | |
822473b6 | 634 | struct vnic_wq *wq; |
822473b6 | 635 | unsigned int txq_map; |
f8e34d24 | 636 | struct netdev_queue *txq; |
01f2e4ea SF |
637 | |
638 | if (skb->len <= 0) { | |
98d8a65d | 639 | dev_kfree_skb_any(skb); |
01f2e4ea SF |
640 | return NETDEV_TX_OK; |
641 | } | |
642 | ||
822473b6 | 643 | txq_map = skb_get_queue_mapping(skb) % enic->wq_count; |
644 | wq = &enic->wq[txq_map]; | |
f8e34d24 | 645 | txq = netdev_get_tx_queue(netdev, txq_map); |
822473b6 | 646 | |
01f2e4ea SF |
647 | /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs, |
648 | * which is very likely. In the off chance it's going to take | |
649 | * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb. | |
650 | */ | |
651 | ||
652 | if (skb_shinfo(skb)->gso_size == 0 && | |
653 | skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC && | |
654 | skb_linearize(skb)) { | |
98d8a65d | 655 | dev_kfree_skb_any(skb); |
01f2e4ea SF |
656 | return NETDEV_TX_OK; |
657 | } | |
658 | ||
78e2045d | 659 | spin_lock(&enic->wq_lock[txq_map]); |
01f2e4ea | 660 | |
ea0d7d91 SF |
661 | if (vnic_wq_desc_avail(wq) < |
662 | skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) { | |
f8e34d24 | 663 | netif_tx_stop_queue(txq); |
01f2e4ea | 664 | /* This is a hard error, log it */ |
a7a79deb | 665 | netdev_err(netdev, "BUG! Tx ring full when queue awake!\n"); |
78e2045d | 666 | spin_unlock(&enic->wq_lock[txq_map]); |
01f2e4ea SF |
667 | return NETDEV_TX_BUSY; |
668 | } | |
669 | ||
670 | enic_queue_wq_skb(enic, wq, skb); | |
671 | ||
ea0d7d91 | 672 | if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS) |
f8e34d24 GV |
673 | netif_tx_stop_queue(txq); |
674 | if (!skb->xmit_more || netif_xmit_stopped(txq)) | |
675 | vnic_wq_doorbell(wq); | |
01f2e4ea | 676 | |
78e2045d | 677 | spin_unlock(&enic->wq_lock[txq_map]); |
01f2e4ea SF |
678 | |
679 | return NETDEV_TX_OK; | |
680 | } | |
681 | ||
682 | /* dev_base_lock rwlock held, nominally process context */ | |
f20530bc | 683 | static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev, |
684 | struct rtnl_link_stats64 *net_stats) | |
01f2e4ea SF |
685 | { |
686 | struct enic *enic = netdev_priv(netdev); | |
687 | struct vnic_stats *stats; | |
19b596bd | 688 | int err; |
01f2e4ea | 689 | |
19b596bd GV |
690 | err = enic_dev_stats_dump(enic, &stats); |
691 | /* return only when pci_zalloc_consistent fails in vnic_dev_stats_dump | |
692 | * For other failures, like devcmd failure, we return previously | |
693 | * recorded stats. | |
694 | */ | |
695 | if (err == -ENOMEM) | |
696 | return net_stats; | |
01f2e4ea | 697 | |
25f0a061 SF |
698 | net_stats->tx_packets = stats->tx.tx_frames_ok; |
699 | net_stats->tx_bytes = stats->tx.tx_bytes_ok; | |
700 | net_stats->tx_errors = stats->tx.tx_errors; | |
701 | net_stats->tx_dropped = stats->tx.tx_drops; | |
01f2e4ea | 702 | |
25f0a061 SF |
703 | net_stats->rx_packets = stats->rx.rx_frames_ok; |
704 | net_stats->rx_bytes = stats->rx.rx_bytes_ok; | |
705 | net_stats->rx_errors = stats->rx.rx_errors; | |
706 | net_stats->multicast = stats->rx.rx_multicast_frames_ok; | |
350991e1 | 707 | net_stats->rx_over_errors = enic->rq_truncated_pkts; |
bd9fb1a4 | 708 | net_stats->rx_crc_errors = enic->rq_bad_fcs; |
350991e1 | 709 | net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop; |
01f2e4ea | 710 | |
25f0a061 | 711 | return net_stats; |
01f2e4ea SF |
712 | } |
713 | ||
f009618a AD |
714 | static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr) |
715 | { | |
716 | struct enic *enic = netdev_priv(netdev); | |
717 | ||
718 | if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) { | |
719 | unsigned int mc_count = netdev_mc_count(netdev); | |
720 | ||
721 | netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n", | |
722 | ENIC_MULTICAST_PERFECT_FILTERS, mc_count); | |
723 | ||
724 | return -ENOSPC; | |
725 | } | |
726 | ||
727 | enic_dev_add_addr(enic, mc_addr); | |
728 | enic->mc_count++; | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr) | |
734 | { | |
735 | struct enic *enic = netdev_priv(netdev); | |
736 | ||
737 | enic_dev_del_addr(enic, mc_addr); | |
738 | enic->mc_count--; | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
743 | static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr) | |
744 | { | |
745 | struct enic *enic = netdev_priv(netdev); | |
746 | ||
747 | if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) { | |
748 | unsigned int uc_count = netdev_uc_count(netdev); | |
749 | ||
750 | netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n", | |
751 | ENIC_UNICAST_PERFECT_FILTERS, uc_count); | |
752 | ||
753 | return -ENOSPC; | |
754 | } | |
755 | ||
756 | enic_dev_add_addr(enic, uc_addr); | |
757 | enic->uc_count++; | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
762 | static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr) | |
763 | { | |
764 | struct enic *enic = netdev_priv(netdev); | |
765 | ||
766 | enic_dev_del_addr(enic, uc_addr); | |
767 | enic->uc_count--; | |
768 | ||
769 | return 0; | |
770 | } | |
771 | ||
b3abfbd2 | 772 | void enic_reset_addr_lists(struct enic *enic) |
01f2e4ea | 773 | { |
f009618a AD |
774 | struct net_device *netdev = enic->netdev; |
775 | ||
776 | __dev_uc_unsync(netdev, NULL); | |
777 | __dev_mc_unsync(netdev, NULL); | |
778 | ||
01f2e4ea | 779 | enic->mc_count = 0; |
e0afe53f | 780 | enic->uc_count = 0; |
99ef5639 | 781 | enic->flags = 0; |
01f2e4ea SF |
782 | } |
783 | ||
784 | static int enic_set_mac_addr(struct net_device *netdev, char *addr) | |
785 | { | |
f8bd9091 SF |
786 | struct enic *enic = netdev_priv(netdev); |
787 | ||
7335903c | 788 | if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) { |
f8bd9091 SF |
789 | if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr)) |
790 | return -EADDRNOTAVAIL; | |
791 | } else { | |
792 | if (!is_valid_ether_addr(addr)) | |
793 | return -EADDRNOTAVAIL; | |
794 | } | |
01f2e4ea SF |
795 | |
796 | memcpy(netdev->dev_addr, addr, netdev->addr_len); | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
f8bd9091 SF |
801 | static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p) |
802 | { | |
803 | struct enic *enic = netdev_priv(netdev); | |
804 | struct sockaddr *saddr = p; | |
805 | char *addr = saddr->sa_data; | |
806 | int err; | |
807 | ||
808 | if (netif_running(enic->netdev)) { | |
809 | err = enic_dev_del_station_addr(enic); | |
810 | if (err) | |
811 | return err; | |
812 | } | |
813 | ||
814 | err = enic_set_mac_addr(netdev, addr); | |
815 | if (err) | |
816 | return err; | |
817 | ||
818 | if (netif_running(enic->netdev)) { | |
819 | err = enic_dev_add_station_addr(enic); | |
820 | if (err) | |
821 | return err; | |
822 | } | |
823 | ||
824 | return err; | |
825 | } | |
826 | ||
827 | static int enic_set_mac_address(struct net_device *netdev, void *p) | |
828 | { | |
294dab25 | 829 | struct sockaddr *saddr = p; |
c76fd32d VK |
830 | char *addr = saddr->sa_data; |
831 | struct enic *enic = netdev_priv(netdev); | |
832 | int err; | |
833 | ||
834 | err = enic_dev_del_station_addr(enic); | |
835 | if (err) | |
836 | return err; | |
837 | ||
838 | err = enic_set_mac_addr(netdev, addr); | |
839 | if (err) | |
840 | return err; | |
294dab25 | 841 | |
c76fd32d | 842 | return enic_dev_add_station_addr(enic); |
f8bd9091 SF |
843 | } |
844 | ||
319d7e84 RP |
845 | /* netif_tx_lock held, BHs disabled */ |
846 | static void enic_set_rx_mode(struct net_device *netdev) | |
847 | { | |
848 | struct enic *enic = netdev_priv(netdev); | |
849 | int directed = 1; | |
850 | int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0; | |
851 | int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0; | |
852 | int promisc = (netdev->flags & IFF_PROMISC) || | |
853 | netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS; | |
854 | int allmulti = (netdev->flags & IFF_ALLMULTI) || | |
855 | netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS; | |
856 | unsigned int flags = netdev->flags | | |
857 | (allmulti ? IFF_ALLMULTI : 0) | | |
858 | (promisc ? IFF_PROMISC : 0); | |
859 | ||
860 | if (enic->flags != flags) { | |
861 | enic->flags = flags; | |
862 | enic_dev_packet_filter(enic, directed, | |
863 | multicast, broadcast, promisc, allmulti); | |
864 | } | |
865 | ||
866 | if (!promisc) { | |
f009618a | 867 | __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync); |
319d7e84 | 868 | if (!allmulti) |
f009618a | 869 | __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync); |
319d7e84 RP |
870 | } |
871 | } | |
872 | ||
01f2e4ea SF |
873 | /* netif_tx_lock held, BHs disabled */ |
874 | static void enic_tx_timeout(struct net_device *netdev) | |
875 | { | |
876 | struct enic *enic = netdev_priv(netdev); | |
937317c7 | 877 | schedule_work(&enic->tx_hang_reset); |
01f2e4ea SF |
878 | } |
879 | ||
0b1c00fc RP |
880 | static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
881 | { | |
882 | struct enic *enic = netdev_priv(netdev); | |
3f192795 RP |
883 | struct enic_port_profile *pp; |
884 | int err; | |
0b1c00fc | 885 | |
3f192795 RP |
886 | ENIC_PP_BY_INDEX(enic, vf, pp, &err); |
887 | if (err) | |
888 | return err; | |
0b1c00fc | 889 | |
b8622cbd | 890 | if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) { |
b4765833 RP |
891 | if (vf == PORT_SELF_VF) { |
892 | memcpy(pp->vf_mac, mac, ETH_ALEN); | |
893 | return 0; | |
894 | } else { | |
895 | /* | |
896 | * For sriov vf's set the mac in hw | |
897 | */ | |
898 | ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic, | |
899 | vnic_dev_set_mac_addr, mac); | |
900 | return enic_dev_status_to_errno(err); | |
901 | } | |
0b1c00fc RP |
902 | } else |
903 | return -EINVAL; | |
904 | } | |
905 | ||
f8bd9091 SF |
906 | static int enic_set_vf_port(struct net_device *netdev, int vf, |
907 | struct nlattr *port[]) | |
908 | { | |
909 | struct enic *enic = netdev_priv(netdev); | |
b3abfbd2 | 910 | struct enic_port_profile prev_pp; |
3f192795 | 911 | struct enic_port_profile *pp; |
b3abfbd2 | 912 | int err = 0, restore_pp = 1; |
08f382eb | 913 | |
3f192795 RP |
914 | ENIC_PP_BY_INDEX(enic, vf, pp, &err); |
915 | if (err) | |
916 | return err; | |
08f382eb | 917 | |
b3abfbd2 RP |
918 | if (!port[IFLA_PORT_REQUEST]) |
919 | return -EOPNOTSUPP; | |
920 | ||
3f192795 RP |
921 | memcpy(&prev_pp, pp, sizeof(*enic->pp)); |
922 | memset(pp, 0, sizeof(*enic->pp)); | |
b3abfbd2 | 923 | |
3f192795 RP |
924 | pp->set |= ENIC_SET_REQUEST; |
925 | pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]); | |
08f382eb SF |
926 | |
927 | if (port[IFLA_PORT_PROFILE]) { | |
3f192795 RP |
928 | pp->set |= ENIC_SET_NAME; |
929 | memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]), | |
08f382eb SF |
930 | PORT_PROFILE_MAX); |
931 | } | |
932 | ||
933 | if (port[IFLA_PORT_INSTANCE_UUID]) { | |
3f192795 RP |
934 | pp->set |= ENIC_SET_INSTANCE; |
935 | memcpy(pp->instance_uuid, | |
08f382eb SF |
936 | nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX); |
937 | } | |
938 | ||
939 | if (port[IFLA_PORT_HOST_UUID]) { | |
3f192795 RP |
940 | pp->set |= ENIC_SET_HOST; |
941 | memcpy(pp->host_uuid, | |
08f382eb SF |
942 | nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX); |
943 | } | |
f8bd9091 | 944 | |
b4765833 RP |
945 | if (vf == PORT_SELF_VF) { |
946 | /* Special case handling: mac came from IFLA_VF_MAC */ | |
947 | if (!is_zero_ether_addr(prev_pp.vf_mac)) | |
948 | memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN); | |
418c437d | 949 | |
b4765833 RP |
950 | if (is_zero_ether_addr(netdev->dev_addr)) |
951 | eth_hw_addr_random(netdev); | |
952 | } else { | |
953 | /* SR-IOV VF: get mac from adapter */ | |
954 | ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic, | |
955 | vnic_dev_get_mac_addr, pp->mac_addr); | |
956 | if (err) { | |
957 | netdev_err(netdev, "Error getting mac for vf %d\n", vf); | |
958 | memcpy(pp, &prev_pp, sizeof(*pp)); | |
959 | return enic_dev_status_to_errno(err); | |
960 | } | |
961 | } | |
f8bd9091 | 962 | |
3f192795 | 963 | err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp); |
b3abfbd2 RP |
964 | if (err) { |
965 | if (restore_pp) { | |
966 | /* Things are still the way they were: Implicit | |
967 | * DISASSOCIATE failed | |
968 | */ | |
3f192795 | 969 | memcpy(pp, &prev_pp, sizeof(*pp)); |
b3abfbd2 | 970 | } else { |
3f192795 RP |
971 | memset(pp, 0, sizeof(*pp)); |
972 | if (vf == PORT_SELF_VF) | |
c7bf7169 | 973 | eth_zero_addr(netdev->dev_addr); |
b3abfbd2 RP |
974 | } |
975 | } else { | |
976 | /* Set flag to indicate that the port assoc/disassoc | |
977 | * request has been sent out to fw | |
978 | */ | |
3f192795 | 979 | pp->set |= ENIC_PORT_REQUEST_APPLIED; |
b3abfbd2 RP |
980 | |
981 | /* If DISASSOCIATE, clean up all assigned/saved macaddresses */ | |
3f192795 | 982 | if (pp->request == PORT_REQUEST_DISASSOCIATE) { |
c7bf7169 | 983 | eth_zero_addr(pp->mac_addr); |
3f192795 | 984 | if (vf == PORT_SELF_VF) |
c7bf7169 | 985 | eth_zero_addr(netdev->dev_addr); |
b3abfbd2 RP |
986 | } |
987 | } | |
29639059 | 988 | |
b4765833 | 989 | if (vf == PORT_SELF_VF) |
c7bf7169 | 990 | eth_zero_addr(pp->vf_mac); |
29639059 | 991 | |
29639059 | 992 | return err; |
f8bd9091 SF |
993 | } |
994 | ||
995 | static int enic_get_vf_port(struct net_device *netdev, int vf, | |
996 | struct sk_buff *skb) | |
997 | { | |
998 | struct enic *enic = netdev_priv(netdev); | |
f8bd9091 | 999 | u16 response = PORT_PROFILE_RESPONSE_SUCCESS; |
3f192795 | 1000 | struct enic_port_profile *pp; |
b3abfbd2 | 1001 | int err; |
f8bd9091 | 1002 | |
3f192795 RP |
1003 | ENIC_PP_BY_INDEX(enic, vf, pp, &err); |
1004 | if (err) | |
1005 | return err; | |
1006 | ||
1007 | if (!(pp->set & ENIC_PORT_REQUEST_APPLIED)) | |
08f382eb | 1008 | return -ENODATA; |
f8bd9091 | 1009 | |
3f192795 | 1010 | err = enic_process_get_pp_request(enic, vf, pp->request, &response); |
f8bd9091 | 1011 | if (err) |
b3abfbd2 | 1012 | return err; |
f8bd9091 | 1013 | |
1a106de6 DM |
1014 | if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) || |
1015 | nla_put_u16(skb, IFLA_PORT_RESPONSE, response) || | |
1016 | ((pp->set & ENIC_SET_NAME) && | |
1017 | nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) || | |
1018 | ((pp->set & ENIC_SET_INSTANCE) && | |
1019 | nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX, | |
1020 | pp->instance_uuid)) || | |
1021 | ((pp->set & ENIC_SET_HOST) && | |
1022 | nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid))) | |
1023 | goto nla_put_failure; | |
f8bd9091 SF |
1024 | return 0; |
1025 | ||
1026 | nla_put_failure: | |
1027 | return -EMSGSIZE; | |
1028 | } | |
1029 | ||
01f2e4ea SF |
1030 | static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf) |
1031 | { | |
1032 | struct enic *enic = vnic_dev_priv(rq->vdev); | |
1033 | ||
1034 | if (!buf->os_buf) | |
1035 | return; | |
1036 | ||
1037 | pci_unmap_single(enic->pdev, buf->dma_addr, | |
1038 | buf->len, PCI_DMA_FROMDEVICE); | |
1039 | dev_kfree_skb_any(buf->os_buf); | |
a03bb56e | 1040 | buf->os_buf = NULL; |
01f2e4ea SF |
1041 | } |
1042 | ||
01f2e4ea SF |
1043 | static int enic_rq_alloc_buf(struct vnic_rq *rq) |
1044 | { | |
1045 | struct enic *enic = vnic_dev_priv(rq->vdev); | |
d19e22dc | 1046 | struct net_device *netdev = enic->netdev; |
01f2e4ea | 1047 | struct sk_buff *skb; |
1825aca6 | 1048 | unsigned int len = netdev->mtu + VLAN_ETH_HLEN; |
01f2e4ea SF |
1049 | unsigned int os_buf_index = 0; |
1050 | dma_addr_t dma_addr; | |
a03bb56e GV |
1051 | struct vnic_rq_buf *buf = rq->to_use; |
1052 | ||
1053 | if (buf->os_buf) { | |
f6b7734b GV |
1054 | enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr, |
1055 | buf->len); | |
01f2e4ea | 1056 | |
a03bb56e GV |
1057 | return 0; |
1058 | } | |
89d71a66 | 1059 | skb = netdev_alloc_skb_ip_align(netdev, len); |
01f2e4ea SF |
1060 | if (!skb) |
1061 | return -ENOMEM; | |
1062 | ||
065df159 GV |
1063 | dma_addr = pci_map_single(enic->pdev, skb->data, len, |
1064 | PCI_DMA_FROMDEVICE); | |
1065 | if (unlikely(enic_dma_map_check(enic, dma_addr))) { | |
1066 | dev_kfree_skb(skb); | |
1067 | return -ENOMEM; | |
1068 | } | |
01f2e4ea SF |
1069 | |
1070 | enic_queue_rq_desc(rq, skb, os_buf_index, | |
1071 | dma_addr, len); | |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
7c2ce6e6 SS |
1076 | static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size, |
1077 | u32 pkt_len) | |
1078 | { | |
1079 | if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len) | |
1080 | pkt_size->large_pkt_bytes_cnt += pkt_len; | |
1081 | else | |
1082 | pkt_size->small_pkt_bytes_cnt += pkt_len; | |
1083 | } | |
1084 | ||
a03bb56e GV |
1085 | static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb, |
1086 | struct vnic_rq_buf *buf, u16 len) | |
1087 | { | |
1088 | struct enic *enic = netdev_priv(netdev); | |
1089 | struct sk_buff *new_skb; | |
1090 | ||
1091 | if (len > enic->rx_copybreak) | |
1092 | return false; | |
1093 | new_skb = netdev_alloc_skb_ip_align(netdev, len); | |
1094 | if (!new_skb) | |
1095 | return false; | |
1096 | pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len, | |
1097 | DMA_FROM_DEVICE); | |
1098 | memcpy(new_skb->data, (*skb)->data, len); | |
1099 | *skb = new_skb; | |
1100 | ||
1101 | return true; | |
1102 | } | |
1103 | ||
01f2e4ea SF |
1104 | static void enic_rq_indicate_buf(struct vnic_rq *rq, |
1105 | struct cq_desc *cq_desc, struct vnic_rq_buf *buf, | |
1106 | int skipped, void *opaque) | |
1107 | { | |
1108 | struct enic *enic = vnic_dev_priv(rq->vdev); | |
86ca9db7 | 1109 | struct net_device *netdev = enic->netdev; |
01f2e4ea | 1110 | struct sk_buff *skb; |
7c2ce6e6 | 1111 | struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; |
01f2e4ea SF |
1112 | |
1113 | u8 type, color, eop, sop, ingress_port, vlan_stripped; | |
1114 | u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof; | |
1115 | u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok; | |
1116 | u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc; | |
1117 | u8 packet_error; | |
f8cac14a | 1118 | u16 q_number, completed_index, bytes_written, vlan_tci, checksum; |
01f2e4ea SF |
1119 | u32 rss_hash; |
1120 | ||
1121 | if (skipped) | |
1122 | return; | |
1123 | ||
1124 | skb = buf->os_buf; | |
01f2e4ea SF |
1125 | |
1126 | cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc, | |
1127 | &type, &color, &q_number, &completed_index, | |
1128 | &ingress_port, &fcoe, &eop, &sop, &rss_type, | |
1129 | &csum_not_calc, &rss_hash, &bytes_written, | |
f8cac14a | 1130 | &packet_error, &vlan_stripped, &vlan_tci, &checksum, |
01f2e4ea SF |
1131 | &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error, |
1132 | &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp, | |
1133 | &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment, | |
1134 | &fcs_ok); | |
1135 | ||
1136 | if (packet_error) { | |
1137 | ||
350991e1 SF |
1138 | if (!fcs_ok) { |
1139 | if (bytes_written > 0) | |
1140 | enic->rq_bad_fcs++; | |
1141 | else if (bytes_written == 0) | |
1142 | enic->rq_truncated_pkts++; | |
1143 | } | |
01f2e4ea | 1144 | |
44aa91ab GV |
1145 | pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, |
1146 | PCI_DMA_FROMDEVICE); | |
01f2e4ea | 1147 | dev_kfree_skb_any(skb); |
44aa91ab | 1148 | buf->os_buf = NULL; |
01f2e4ea SF |
1149 | |
1150 | return; | |
1151 | } | |
1152 | ||
1153 | if (eop && bytes_written > 0) { | |
1154 | ||
1155 | /* Good receive | |
1156 | */ | |
1157 | ||
a03bb56e GV |
1158 | if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) { |
1159 | buf->os_buf = NULL; | |
1160 | pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, | |
1161 | PCI_DMA_FROMDEVICE); | |
1162 | } | |
1163 | prefetch(skb->data - NET_IP_ALIGN); | |
1164 | ||
01f2e4ea | 1165 | skb_put(skb, bytes_written); |
86ca9db7 | 1166 | skb->protocol = eth_type_trans(skb, netdev); |
bf751ba8 | 1167 | skb_record_rx_queue(skb, q_number); |
1168 | if (netdev->features & NETIF_F_RXHASH) { | |
3739acdd TH |
1169 | skb_set_hash(skb, rss_hash, |
1170 | (rss_type & | |
1171 | (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX | | |
1172 | NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 | | |
1173 | NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ? | |
1174 | PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); | |
bf751ba8 | 1175 | } |
01f2e4ea | 1176 | |
17e96834 GV |
1177 | /* Hardware does not provide whole packet checksum. It only |
1178 | * provides pseudo checksum. Since hw validates the packet | |
1179 | * checksum but not provide us the checksum value. use | |
1180 | * CHECSUM_UNNECESSARY. | |
1181 | */ | |
1182 | if ((netdev->features & NETIF_F_RXCSUM) && tcp_udp_csum_ok && | |
1183 | ipv4_csum_ok) | |
1184 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
01f2e4ea | 1185 | |
6ede746b | 1186 | if (vlan_stripped) |
86a9bad3 | 1187 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci); |
01f2e4ea | 1188 | |
14747cd9 GV |
1189 | skb_mark_napi_id(skb, &enic->napi[rq->index]); |
1190 | if (enic_poll_busy_polling(rq) || | |
1191 | !(netdev->features & NETIF_F_GRO)) | |
6ede746b | 1192 | netif_receive_skb(skb); |
14747cd9 GV |
1193 | else |
1194 | napi_gro_receive(&enic->napi[q_number], skb); | |
7c2ce6e6 SS |
1195 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) |
1196 | enic_intr_update_pkt_size(&cq->pkt_size_counter, | |
1197 | bytes_written); | |
01f2e4ea SF |
1198 | } else { |
1199 | ||
1200 | /* Buffer overflow | |
1201 | */ | |
1202 | ||
44aa91ab GV |
1203 | pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, |
1204 | PCI_DMA_FROMDEVICE); | |
01f2e4ea | 1205 | dev_kfree_skb_any(skb); |
44aa91ab | 1206 | buf->os_buf = NULL; |
01f2e4ea SF |
1207 | } |
1208 | } | |
1209 | ||
1210 | static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc, | |
1211 | u8 type, u16 q_number, u16 completed_index, void *opaque) | |
1212 | { | |
1213 | struct enic *enic = vnic_dev_priv(vdev); | |
1214 | ||
1215 | vnic_rq_service(&enic->rq[q_number], cq_desc, | |
1216 | completed_index, VNIC_RQ_RETURN_DESC, | |
1217 | enic_rq_indicate_buf, opaque); | |
1218 | ||
1219 | return 0; | |
1220 | } | |
1221 | ||
fc865d6b GV |
1222 | static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq) |
1223 | { | |
1224 | unsigned int intr = enic_msix_rq_intr(enic, rq->index); | |
1225 | struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; | |
1226 | u32 timer = cq->tobe_rx_coal_timeval; | |
1227 | ||
1228 | if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) { | |
1229 | vnic_intr_coalescing_timer_set(&enic->intr[intr], timer); | |
1230 | cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval; | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq) | |
1235 | { | |
1236 | struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting; | |
1237 | struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; | |
1238 | struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter; | |
1239 | int index; | |
1240 | u32 timer; | |
1241 | u32 range_start; | |
1242 | u32 traffic; | |
1243 | u64 delta; | |
1244 | ktime_t now = ktime_get(); | |
1245 | ||
1246 | delta = ktime_us_delta(now, cq->prev_ts); | |
1247 | if (delta < ENIC_AIC_TS_BREAK) | |
1248 | return; | |
1249 | cq->prev_ts = now; | |
1250 | ||
1251 | traffic = pkt_size_counter->large_pkt_bytes_cnt + | |
1252 | pkt_size_counter->small_pkt_bytes_cnt; | |
1253 | /* The table takes Mbps | |
1254 | * traffic *= 8 => bits | |
1255 | * traffic *= (10^6 / delta) => bps | |
1256 | * traffic /= 10^6 => Mbps | |
1257 | * | |
1258 | * Combining, traffic *= (8 / delta) | |
1259 | */ | |
1260 | ||
1261 | traffic <<= 3; | |
1262 | traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta; | |
1263 | ||
1264 | for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++) | |
1265 | if (traffic < mod_table[index].rx_rate) | |
1266 | break; | |
1267 | range_start = (pkt_size_counter->small_pkt_bytes_cnt > | |
1268 | pkt_size_counter->large_pkt_bytes_cnt << 1) ? | |
1269 | rx_coal->small_pkt_range_start : | |
1270 | rx_coal->large_pkt_range_start; | |
1271 | timer = range_start + ((rx_coal->range_end - range_start) * | |
1272 | mod_table[index].range_percent / 100); | |
1273 | /* Damping */ | |
1274 | cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1; | |
1275 | ||
1276 | pkt_size_counter->large_pkt_bytes_cnt = 0; | |
1277 | pkt_size_counter->small_pkt_bytes_cnt = 0; | |
1278 | } | |
1279 | ||
01f2e4ea SF |
1280 | static int enic_poll(struct napi_struct *napi, int budget) |
1281 | { | |
717258ba VK |
1282 | struct net_device *netdev = napi->dev; |
1283 | struct enic *enic = netdev_priv(netdev); | |
1284 | unsigned int cq_rq = enic_cq_rq(enic, 0); | |
1285 | unsigned int cq_wq = enic_cq_wq(enic, 0); | |
1286 | unsigned int intr = enic_legacy_io_intr(); | |
01f2e4ea SF |
1287 | unsigned int rq_work_to_do = budget; |
1288 | unsigned int wq_work_to_do = -1; /* no limit */ | |
4c502549 | 1289 | unsigned int work_done, rq_work_done = 0, wq_work_done; |
2d6ddced | 1290 | int err; |
01f2e4ea | 1291 | |
14747cd9 GV |
1292 | wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do, |
1293 | enic_wq_service, NULL); | |
1294 | ||
1295 | if (!enic_poll_lock_napi(&enic->rq[cq_rq])) { | |
1296 | if (wq_work_done > 0) | |
1297 | vnic_intr_return_credits(&enic->intr[intr], | |
1298 | wq_work_done, | |
1299 | 0 /* dont unmask intr */, | |
1300 | 0 /* dont reset intr timer */); | |
25c14ef8 | 1301 | return budget; |
14747cd9 | 1302 | } |
01f2e4ea | 1303 | |
4c502549 EB |
1304 | if (budget > 0) |
1305 | rq_work_done = vnic_cq_service(&enic->cq[cq_rq], | |
1306 | rq_work_to_do, enic_rq_service, NULL); | |
01f2e4ea | 1307 | |
01f2e4ea SF |
1308 | /* Accumulate intr event credits for this polling |
1309 | * cycle. An intr event is the completion of a | |
1310 | * a WQ or RQ packet. | |
1311 | */ | |
1312 | ||
1313 | work_done = rq_work_done + wq_work_done; | |
1314 | ||
1315 | if (work_done > 0) | |
717258ba | 1316 | vnic_intr_return_credits(&enic->intr[intr], |
01f2e4ea SF |
1317 | work_done, |
1318 | 0 /* don't unmask intr */, | |
1319 | 0 /* don't reset intr timer */); | |
1320 | ||
0eb26022 | 1321 | err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf); |
25c14ef8 | 1322 | enic_poll_unlock_napi(&enic->rq[cq_rq], napi); |
01f2e4ea | 1323 | |
2d6ddced SF |
1324 | /* Buffer allocation failed. Stay in polling |
1325 | * mode so we can try to fill the ring again. | |
1326 | */ | |
01f2e4ea | 1327 | |
2d6ddced SF |
1328 | if (err) |
1329 | rq_work_done = rq_work_to_do; | |
fc865d6b GV |
1330 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) |
1331 | /* Call the function which refreshes the intr coalescing timer | |
1332 | * value based on the traffic. | |
1333 | */ | |
1334 | enic_calc_int_moderation(enic, &enic->rq[0]); | |
01f2e4ea | 1335 | |
2d6ddced | 1336 | if (rq_work_done < rq_work_to_do) { |
01f2e4ea | 1337 | |
2d6ddced | 1338 | /* Some work done, but not enough to stay in polling, |
88132f55 | 1339 | * exit polling |
01f2e4ea SF |
1340 | */ |
1341 | ||
288379f0 | 1342 | napi_complete(napi); |
fc865d6b GV |
1343 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) |
1344 | enic_set_int_moderation(enic, &enic->rq[0]); | |
717258ba | 1345 | vnic_intr_unmask(&enic->intr[intr]); |
01f2e4ea SF |
1346 | } |
1347 | ||
1348 | return rq_work_done; | |
1349 | } | |
1350 | ||
b6e97c13 GV |
1351 | #ifdef CONFIG_RFS_ACCEL |
1352 | static void enic_free_rx_cpu_rmap(struct enic *enic) | |
1353 | { | |
1354 | free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap); | |
1355 | enic->netdev->rx_cpu_rmap = NULL; | |
1356 | } | |
1357 | ||
1358 | static void enic_set_rx_cpu_rmap(struct enic *enic) | |
1359 | { | |
1360 | int i, res; | |
1361 | ||
1362 | if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) { | |
1363 | enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count); | |
1364 | if (unlikely(!enic->netdev->rx_cpu_rmap)) | |
1365 | return; | |
1366 | for (i = 0; i < enic->rq_count; i++) { | |
1367 | res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap, | |
1368 | enic->msix_entry[i].vector); | |
1369 | if (unlikely(res)) { | |
1370 | enic_free_rx_cpu_rmap(enic); | |
1371 | return; | |
1372 | } | |
1373 | } | |
1374 | } | |
1375 | } | |
1376 | ||
1377 | #else | |
1378 | ||
1379 | static void enic_free_rx_cpu_rmap(struct enic *enic) | |
1380 | { | |
1381 | } | |
1382 | ||
1383 | static void enic_set_rx_cpu_rmap(struct enic *enic) | |
1384 | { | |
1385 | } | |
1386 | ||
1387 | #endif /* CONFIG_RFS_ACCEL */ | |
1388 | ||
14747cd9 | 1389 | #ifdef CONFIG_NET_RX_BUSY_POLL |
57ae84a0 | 1390 | static int enic_busy_poll(struct napi_struct *napi) |
14747cd9 GV |
1391 | { |
1392 | struct net_device *netdev = napi->dev; | |
1393 | struct enic *enic = netdev_priv(netdev); | |
1394 | unsigned int rq = (napi - &enic->napi[0]); | |
1395 | unsigned int cq = enic_cq_rq(enic, rq); | |
1396 | unsigned int intr = enic_msix_rq_intr(enic, rq); | |
1397 | unsigned int work_to_do = -1; /* clean all pkts possible */ | |
1398 | unsigned int work_done; | |
1399 | ||
1400 | if (!enic_poll_lock_poll(&enic->rq[rq])) | |
1401 | return LL_FLUSH_BUSY; | |
1402 | work_done = vnic_cq_service(&enic->cq[cq], work_to_do, | |
1403 | enic_rq_service, NULL); | |
1404 | ||
1405 | if (work_done > 0) | |
1406 | vnic_intr_return_credits(&enic->intr[intr], | |
1407 | work_done, 0, 0); | |
1408 | vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf); | |
1409 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) | |
1410 | enic_calc_int_moderation(enic, &enic->rq[rq]); | |
1411 | enic_poll_unlock_poll(&enic->rq[rq]); | |
1412 | ||
1413 | return work_done; | |
1414 | } | |
1415 | #endif /* CONFIG_NET_RX_BUSY_POLL */ | |
1416 | ||
4cfe8785 GV |
1417 | static int enic_poll_msix_wq(struct napi_struct *napi, int budget) |
1418 | { | |
1419 | struct net_device *netdev = napi->dev; | |
1420 | struct enic *enic = netdev_priv(netdev); | |
1421 | unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count; | |
1422 | struct vnic_wq *wq = &enic->wq[wq_index]; | |
1423 | unsigned int cq; | |
1424 | unsigned int intr; | |
1425 | unsigned int wq_work_to_do = -1; /* clean all desc possible */ | |
1426 | unsigned int wq_work_done; | |
1427 | unsigned int wq_irq; | |
1428 | ||
1429 | wq_irq = wq->index; | |
1430 | cq = enic_cq_wq(enic, wq_irq); | |
1431 | intr = enic_msix_wq_intr(enic, wq_irq); | |
1432 | wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do, | |
1433 | enic_wq_service, NULL); | |
1434 | ||
1435 | vnic_intr_return_credits(&enic->intr[intr], wq_work_done, | |
1436 | 0 /* don't unmask intr */, | |
1437 | 1 /* reset intr timer */); | |
1438 | if (!wq_work_done) { | |
1439 | napi_complete(napi); | |
1440 | vnic_intr_unmask(&enic->intr[intr]); | |
f41281d0 | 1441 | return 0; |
4cfe8785 GV |
1442 | } |
1443 | ||
f41281d0 | 1444 | return budget; |
4cfe8785 GV |
1445 | } |
1446 | ||
1447 | static int enic_poll_msix_rq(struct napi_struct *napi, int budget) | |
01f2e4ea | 1448 | { |
717258ba VK |
1449 | struct net_device *netdev = napi->dev; |
1450 | struct enic *enic = netdev_priv(netdev); | |
1451 | unsigned int rq = (napi - &enic->napi[0]); | |
1452 | unsigned int cq = enic_cq_rq(enic, rq); | |
1453 | unsigned int intr = enic_msix_rq_intr(enic, rq); | |
01f2e4ea | 1454 | unsigned int work_to_do = budget; |
4c502549 | 1455 | unsigned int work_done = 0; |
2d6ddced | 1456 | int err; |
01f2e4ea | 1457 | |
14747cd9 | 1458 | if (!enic_poll_lock_napi(&enic->rq[rq])) |
f104fedc | 1459 | return budget; |
01f2e4ea SF |
1460 | /* Service RQ |
1461 | */ | |
1462 | ||
4c502549 EB |
1463 | if (budget > 0) |
1464 | work_done = vnic_cq_service(&enic->cq[cq], | |
1465 | work_to_do, enic_rq_service, NULL); | |
01f2e4ea | 1466 | |
2d6ddced SF |
1467 | /* Return intr event credits for this polling |
1468 | * cycle. An intr event is the completion of a | |
1469 | * RQ packet. | |
1470 | */ | |
01f2e4ea | 1471 | |
2d6ddced | 1472 | if (work_done > 0) |
717258ba | 1473 | vnic_intr_return_credits(&enic->intr[intr], |
01f2e4ea SF |
1474 | work_done, |
1475 | 0 /* don't unmask intr */, | |
1476 | 0 /* don't reset intr timer */); | |
01f2e4ea | 1477 | |
0eb26022 | 1478 | err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf); |
2d6ddced SF |
1479 | |
1480 | /* Buffer allocation failed. Stay in polling mode | |
1481 | * so we can try to fill the ring again. | |
1482 | */ | |
1483 | ||
1484 | if (err) | |
1485 | work_done = work_to_do; | |
7c2ce6e6 | 1486 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) |
fc865d6b GV |
1487 | /* Call the function which refreshes the intr coalescing timer |
1488 | * value based on the traffic. | |
7c2ce6e6 SS |
1489 | */ |
1490 | enic_calc_int_moderation(enic, &enic->rq[rq]); | |
2d6ddced | 1491 | |
f586a336 | 1492 | enic_poll_unlock_napi(&enic->rq[rq], napi); |
2d6ddced SF |
1493 | if (work_done < work_to_do) { |
1494 | ||
1495 | /* Some work done, but not enough to stay in polling, | |
88132f55 | 1496 | * exit polling |
01f2e4ea SF |
1497 | */ |
1498 | ||
288379f0 | 1499 | napi_complete(napi); |
7c2ce6e6 SS |
1500 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) |
1501 | enic_set_int_moderation(enic, &enic->rq[rq]); | |
717258ba | 1502 | vnic_intr_unmask(&enic->intr[intr]); |
01f2e4ea SF |
1503 | } |
1504 | ||
1505 | return work_done; | |
1506 | } | |
1507 | ||
1508 | static void enic_notify_timer(unsigned long data) | |
1509 | { | |
1510 | struct enic *enic = (struct enic *)data; | |
1511 | ||
1512 | enic_notify_check(enic); | |
1513 | ||
25f0a061 SF |
1514 | mod_timer(&enic->notify_timer, |
1515 | round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD)); | |
01f2e4ea SF |
1516 | } |
1517 | ||
1518 | static void enic_free_intr(struct enic *enic) | |
1519 | { | |
1520 | struct net_device *netdev = enic->netdev; | |
1521 | unsigned int i; | |
1522 | ||
b6e97c13 | 1523 | enic_free_rx_cpu_rmap(enic); |
01f2e4ea SF |
1524 | switch (vnic_dev_get_intr_mode(enic->vdev)) { |
1525 | case VNIC_DEV_INTR_MODE_INTX: | |
01f2e4ea SF |
1526 | free_irq(enic->pdev->irq, netdev); |
1527 | break; | |
8f4d248c SF |
1528 | case VNIC_DEV_INTR_MODE_MSI: |
1529 | free_irq(enic->pdev->irq, enic); | |
1530 | break; | |
01f2e4ea SF |
1531 | case VNIC_DEV_INTR_MODE_MSIX: |
1532 | for (i = 0; i < ARRAY_SIZE(enic->msix); i++) | |
1533 | if (enic->msix[i].requested) | |
1534 | free_irq(enic->msix_entry[i].vector, | |
1535 | enic->msix[i].devid); | |
1536 | break; | |
1537 | default: | |
1538 | break; | |
1539 | } | |
1540 | } | |
1541 | ||
1542 | static int enic_request_intr(struct enic *enic) | |
1543 | { | |
1544 | struct net_device *netdev = enic->netdev; | |
717258ba | 1545 | unsigned int i, intr; |
01f2e4ea SF |
1546 | int err = 0; |
1547 | ||
b6e97c13 | 1548 | enic_set_rx_cpu_rmap(enic); |
01f2e4ea SF |
1549 | switch (vnic_dev_get_intr_mode(enic->vdev)) { |
1550 | ||
1551 | case VNIC_DEV_INTR_MODE_INTX: | |
1552 | ||
1553 | err = request_irq(enic->pdev->irq, enic_isr_legacy, | |
1554 | IRQF_SHARED, netdev->name, netdev); | |
1555 | break; | |
1556 | ||
1557 | case VNIC_DEV_INTR_MODE_MSI: | |
1558 | ||
1559 | err = request_irq(enic->pdev->irq, enic_isr_msi, | |
1560 | 0, netdev->name, enic); | |
1561 | break; | |
1562 | ||
1563 | case VNIC_DEV_INTR_MODE_MSIX: | |
1564 | ||
717258ba VK |
1565 | for (i = 0; i < enic->rq_count; i++) { |
1566 | intr = enic_msix_rq_intr(enic, i); | |
4505f40a DC |
1567 | snprintf(enic->msix[intr].devname, |
1568 | sizeof(enic->msix[intr].devname), | |
8d546f58 | 1569 | "%.11s-rx-%u", netdev->name, i); |
4cfe8785 | 1570 | enic->msix[intr].isr = enic_isr_msix; |
717258ba VK |
1571 | enic->msix[intr].devid = &enic->napi[i]; |
1572 | } | |
01f2e4ea | 1573 | |
717258ba | 1574 | for (i = 0; i < enic->wq_count; i++) { |
4cfe8785 GV |
1575 | int wq = enic_cq_wq(enic, i); |
1576 | ||
717258ba | 1577 | intr = enic_msix_wq_intr(enic, i); |
4505f40a DC |
1578 | snprintf(enic->msix[intr].devname, |
1579 | sizeof(enic->msix[intr].devname), | |
8d546f58 | 1580 | "%.11s-tx-%u", netdev->name, i); |
4cfe8785 GV |
1581 | enic->msix[intr].isr = enic_isr_msix; |
1582 | enic->msix[intr].devid = &enic->napi[wq]; | |
717258ba | 1583 | } |
01f2e4ea | 1584 | |
717258ba | 1585 | intr = enic_msix_err_intr(enic); |
4505f40a DC |
1586 | snprintf(enic->msix[intr].devname, |
1587 | sizeof(enic->msix[intr].devname), | |
01f2e4ea | 1588 | "%.11s-err", netdev->name); |
717258ba VK |
1589 | enic->msix[intr].isr = enic_isr_msix_err; |
1590 | enic->msix[intr].devid = enic; | |
01f2e4ea | 1591 | |
717258ba | 1592 | intr = enic_msix_notify_intr(enic); |
4505f40a DC |
1593 | snprintf(enic->msix[intr].devname, |
1594 | sizeof(enic->msix[intr].devname), | |
01f2e4ea | 1595 | "%.11s-notify", netdev->name); |
717258ba VK |
1596 | enic->msix[intr].isr = enic_isr_msix_notify; |
1597 | enic->msix[intr].devid = enic; | |
1598 | ||
1599 | for (i = 0; i < ARRAY_SIZE(enic->msix); i++) | |
1600 | enic->msix[i].requested = 0; | |
01f2e4ea | 1601 | |
717258ba | 1602 | for (i = 0; i < enic->intr_count; i++) { |
01f2e4ea SF |
1603 | err = request_irq(enic->msix_entry[i].vector, |
1604 | enic->msix[i].isr, 0, | |
1605 | enic->msix[i].devname, | |
1606 | enic->msix[i].devid); | |
1607 | if (err) { | |
1608 | enic_free_intr(enic); | |
1609 | break; | |
1610 | } | |
1611 | enic->msix[i].requested = 1; | |
1612 | } | |
1613 | ||
1614 | break; | |
1615 | ||
1616 | default: | |
1617 | break; | |
1618 | } | |
1619 | ||
1620 | return err; | |
1621 | } | |
1622 | ||
b3d18d19 SF |
1623 | static void enic_synchronize_irqs(struct enic *enic) |
1624 | { | |
1625 | unsigned int i; | |
1626 | ||
1627 | switch (vnic_dev_get_intr_mode(enic->vdev)) { | |
1628 | case VNIC_DEV_INTR_MODE_INTX: | |
1629 | case VNIC_DEV_INTR_MODE_MSI: | |
1630 | synchronize_irq(enic->pdev->irq); | |
1631 | break; | |
1632 | case VNIC_DEV_INTR_MODE_MSIX: | |
1633 | for (i = 0; i < enic->intr_count; i++) | |
1634 | synchronize_irq(enic->msix_entry[i].vector); | |
1635 | break; | |
1636 | default: | |
1637 | break; | |
1638 | } | |
1639 | } | |
1640 | ||
7c2ce6e6 SS |
1641 | static void enic_set_rx_coal_setting(struct enic *enic) |
1642 | { | |
1643 | unsigned int speed; | |
1644 | int index = -1; | |
1645 | struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting; | |
1646 | ||
7c2ce6e6 SS |
1647 | /* 1. Read the link speed from fw |
1648 | * 2. Pick the default range for the speed | |
1649 | * 3. Update it in enic->rx_coalesce_setting | |
1650 | */ | |
1651 | speed = vnic_dev_port_speed(enic->vdev); | |
1652 | if (ENIC_LINK_SPEED_10G < speed) | |
1653 | index = ENIC_LINK_40G_INDEX; | |
1654 | else if (ENIC_LINK_SPEED_4G < speed) | |
1655 | index = ENIC_LINK_10G_INDEX; | |
1656 | else | |
1657 | index = ENIC_LINK_4G_INDEX; | |
1658 | ||
1659 | rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start; | |
1660 | rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start; | |
1661 | rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END; | |
1662 | ||
1663 | /* Start with the value provided by UCSM */ | |
1664 | for (index = 0; index < enic->rq_count; index++) | |
1665 | enic->cq[index].cur_rx_coal_timeval = | |
1666 | enic->config.intr_timer_usec; | |
1667 | ||
1668 | rx_coal->use_adaptive_rx_coalesce = 1; | |
1669 | } | |
1670 | ||
383ab92f | 1671 | static int enic_dev_notify_set(struct enic *enic) |
01f2e4ea SF |
1672 | { |
1673 | int err; | |
1674 | ||
8e091340 | 1675 | spin_lock_bh(&enic->devcmd_lock); |
01f2e4ea SF |
1676 | switch (vnic_dev_get_intr_mode(enic->vdev)) { |
1677 | case VNIC_DEV_INTR_MODE_INTX: | |
717258ba VK |
1678 | err = vnic_dev_notify_set(enic->vdev, |
1679 | enic_legacy_notify_intr()); | |
01f2e4ea SF |
1680 | break; |
1681 | case VNIC_DEV_INTR_MODE_MSIX: | |
717258ba VK |
1682 | err = vnic_dev_notify_set(enic->vdev, |
1683 | enic_msix_notify_intr(enic)); | |
01f2e4ea SF |
1684 | break; |
1685 | default: | |
1686 | err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */); | |
1687 | break; | |
1688 | } | |
8e091340 | 1689 | spin_unlock_bh(&enic->devcmd_lock); |
01f2e4ea SF |
1690 | |
1691 | return err; | |
1692 | } | |
1693 | ||
1694 | static void enic_notify_timer_start(struct enic *enic) | |
1695 | { | |
1696 | switch (vnic_dev_get_intr_mode(enic->vdev)) { | |
1697 | case VNIC_DEV_INTR_MODE_MSI: | |
1698 | mod_timer(&enic->notify_timer, jiffies); | |
1699 | break; | |
1700 | default: | |
1701 | /* Using intr for notification for INTx/MSI-X */ | |
1702 | break; | |
6403eab1 | 1703 | } |
01f2e4ea SF |
1704 | } |
1705 | ||
1706 | /* rtnl lock is held, process context */ | |
1707 | static int enic_open(struct net_device *netdev) | |
1708 | { | |
1709 | struct enic *enic = netdev_priv(netdev); | |
1710 | unsigned int i; | |
1711 | int err; | |
1712 | ||
4b75a442 SF |
1713 | err = enic_request_intr(enic); |
1714 | if (err) { | |
a7a79deb | 1715 | netdev_err(netdev, "Unable to request irq.\n"); |
4b75a442 SF |
1716 | return err; |
1717 | } | |
322cf7e3 GV |
1718 | enic_init_affinity_hint(enic); |
1719 | enic_set_affinity_hint(enic); | |
4b75a442 | 1720 | |
383ab92f | 1721 | err = enic_dev_notify_set(enic); |
4b75a442 | 1722 | if (err) { |
a7a79deb VK |
1723 | netdev_err(netdev, |
1724 | "Failed to alloc notify buffer, aborting.\n"); | |
4b75a442 SF |
1725 | goto err_out_free_intr; |
1726 | } | |
1727 | ||
01f2e4ea | 1728 | for (i = 0; i < enic->rq_count; i++) { |
0eb26022 | 1729 | vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf); |
2d6ddced SF |
1730 | /* Need at least one buffer on ring to get going */ |
1731 | if (vnic_rq_desc_used(&enic->rq[i]) == 0) { | |
a7a79deb | 1732 | netdev_err(netdev, "Unable to alloc receive buffers\n"); |
2d6ddced | 1733 | err = -ENOMEM; |
9dac6232 | 1734 | goto err_out_free_rq; |
01f2e4ea SF |
1735 | } |
1736 | } | |
1737 | ||
1738 | for (i = 0; i < enic->wq_count; i++) | |
1739 | vnic_wq_enable(&enic->wq[i]); | |
1740 | for (i = 0; i < enic->rq_count; i++) | |
1741 | vnic_rq_enable(&enic->rq[i]); | |
1742 | ||
7335903c | 1743 | if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic)) |
29639059 | 1744 | enic_dev_add_station_addr(enic); |
3f192795 | 1745 | |
319d7e84 | 1746 | enic_set_rx_mode(netdev); |
01f2e4ea | 1747 | |
822473b6 | 1748 | netif_tx_wake_all_queues(netdev); |
717258ba | 1749 | |
14747cd9 GV |
1750 | for (i = 0; i < enic->rq_count; i++) { |
1751 | enic_busy_poll_init_lock(&enic->rq[i]); | |
717258ba | 1752 | napi_enable(&enic->napi[i]); |
14747cd9 | 1753 | } |
4cfe8785 GV |
1754 | if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) |
1755 | for (i = 0; i < enic->wq_count; i++) | |
1756 | napi_enable(&enic->napi[enic_cq_wq(enic, i)]); | |
383ab92f | 1757 | enic_dev_enable(enic); |
01f2e4ea SF |
1758 | |
1759 | for (i = 0; i < enic->intr_count; i++) | |
1760 | vnic_intr_unmask(&enic->intr[i]); | |
1761 | ||
1762 | enic_notify_timer_start(enic); | |
a145df23 | 1763 | enic_rfs_flw_tbl_init(enic); |
01f2e4ea SF |
1764 | |
1765 | return 0; | |
4b75a442 | 1766 | |
9dac6232 GV |
1767 | err_out_free_rq: |
1768 | for (i = 0; i < enic->rq_count; i++) | |
1769 | vnic_rq_clean(&enic->rq[i], enic_free_rq_buf); | |
383ab92f | 1770 | enic_dev_notify_unset(enic); |
4b75a442 | 1771 | err_out_free_intr: |
322cf7e3 | 1772 | enic_unset_affinity_hint(enic); |
4b75a442 SF |
1773 | enic_free_intr(enic); |
1774 | ||
1775 | return err; | |
01f2e4ea SF |
1776 | } |
1777 | ||
1778 | /* rtnl lock is held, process context */ | |
1779 | static int enic_stop(struct net_device *netdev) | |
1780 | { | |
1781 | struct enic *enic = netdev_priv(netdev); | |
1782 | unsigned int i; | |
1783 | int err; | |
1784 | ||
29046f9b | 1785 | for (i = 0; i < enic->intr_count; i++) { |
b3d18d19 | 1786 | vnic_intr_mask(&enic->intr[i]); |
29046f9b VK |
1787 | (void)vnic_intr_masked(&enic->intr[i]); /* flush write */ |
1788 | } | |
b3d18d19 SF |
1789 | |
1790 | enic_synchronize_irqs(enic); | |
1791 | ||
01f2e4ea | 1792 | del_timer_sync(&enic->notify_timer); |
a145df23 | 1793 | enic_rfs_flw_tbl_free(enic); |
01f2e4ea | 1794 | |
383ab92f | 1795 | enic_dev_disable(enic); |
717258ba | 1796 | |
14747cd9 | 1797 | for (i = 0; i < enic->rq_count; i++) { |
717258ba | 1798 | napi_disable(&enic->napi[i]); |
39dc90c1 | 1799 | local_bh_disable(); |
14747cd9 GV |
1800 | while (!enic_poll_lock_napi(&enic->rq[i])) |
1801 | mdelay(1); | |
39dc90c1 | 1802 | local_bh_enable(); |
14747cd9 | 1803 | } |
717258ba | 1804 | |
b3d18d19 SF |
1805 | netif_carrier_off(netdev); |
1806 | netif_tx_disable(netdev); | |
4cfe8785 GV |
1807 | if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) |
1808 | for (i = 0; i < enic->wq_count; i++) | |
1809 | napi_disable(&enic->napi[enic_cq_wq(enic, i)]); | |
3f192795 | 1810 | |
7335903c | 1811 | if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic)) |
29639059 | 1812 | enic_dev_del_station_addr(enic); |
f8bd9091 | 1813 | |
01f2e4ea SF |
1814 | for (i = 0; i < enic->wq_count; i++) { |
1815 | err = vnic_wq_disable(&enic->wq[i]); | |
1816 | if (err) | |
1817 | return err; | |
1818 | } | |
1819 | for (i = 0; i < enic->rq_count; i++) { | |
1820 | err = vnic_rq_disable(&enic->rq[i]); | |
1821 | if (err) | |
1822 | return err; | |
1823 | } | |
1824 | ||
383ab92f | 1825 | enic_dev_notify_unset(enic); |
322cf7e3 | 1826 | enic_unset_affinity_hint(enic); |
4b75a442 SF |
1827 | enic_free_intr(enic); |
1828 | ||
01f2e4ea SF |
1829 | for (i = 0; i < enic->wq_count; i++) |
1830 | vnic_wq_clean(&enic->wq[i], enic_free_wq_buf); | |
1831 | for (i = 0; i < enic->rq_count; i++) | |
1832 | vnic_rq_clean(&enic->rq[i], enic_free_rq_buf); | |
1833 | for (i = 0; i < enic->cq_count; i++) | |
1834 | vnic_cq_clean(&enic->cq[i]); | |
1835 | for (i = 0; i < enic->intr_count; i++) | |
1836 | vnic_intr_clean(&enic->intr[i]); | |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | ||
1841 | static int enic_change_mtu(struct net_device *netdev, int new_mtu) | |
1842 | { | |
1843 | struct enic *enic = netdev_priv(netdev); | |
1844 | int running = netif_running(netdev); | |
1845 | ||
25f0a061 SF |
1846 | if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU) |
1847 | return -EINVAL; | |
1848 | ||
7335903c | 1849 | if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) |
c97c894d RP |
1850 | return -EOPNOTSUPP; |
1851 | ||
01f2e4ea SF |
1852 | if (running) |
1853 | enic_stop(netdev); | |
1854 | ||
01f2e4ea SF |
1855 | netdev->mtu = new_mtu; |
1856 | ||
1857 | if (netdev->mtu > enic->port_mtu) | |
a7a79deb VK |
1858 | netdev_warn(netdev, |
1859 | "interface MTU (%d) set higher than port MTU (%d)\n", | |
1860 | netdev->mtu, enic->port_mtu); | |
01f2e4ea SF |
1861 | |
1862 | if (running) | |
1863 | enic_open(netdev); | |
1864 | ||
1865 | return 0; | |
1866 | } | |
1867 | ||
c97c894d RP |
1868 | static void enic_change_mtu_work(struct work_struct *work) |
1869 | { | |
1870 | struct enic *enic = container_of(work, struct enic, change_mtu_work); | |
1871 | struct net_device *netdev = enic->netdev; | |
1872 | int new_mtu = vnic_dev_mtu(enic->vdev); | |
1873 | int err; | |
1874 | unsigned int i; | |
1875 | ||
1876 | new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu)); | |
1877 | ||
1878 | rtnl_lock(); | |
1879 | ||
1880 | /* Stop RQ */ | |
1881 | del_timer_sync(&enic->notify_timer); | |
1882 | ||
1883 | for (i = 0; i < enic->rq_count; i++) | |
1884 | napi_disable(&enic->napi[i]); | |
1885 | ||
1886 | vnic_intr_mask(&enic->intr[0]); | |
1887 | enic_synchronize_irqs(enic); | |
1888 | err = vnic_rq_disable(&enic->rq[0]); | |
1889 | if (err) { | |
e057590b | 1890 | rtnl_unlock(); |
c97c894d RP |
1891 | netdev_err(netdev, "Unable to disable RQ.\n"); |
1892 | return; | |
1893 | } | |
1894 | vnic_rq_clean(&enic->rq[0], enic_free_rq_buf); | |
1895 | vnic_cq_clean(&enic->cq[0]); | |
1896 | vnic_intr_clean(&enic->intr[0]); | |
1897 | ||
1898 | /* Fill RQ with new_mtu-sized buffers */ | |
1899 | netdev->mtu = new_mtu; | |
1900 | vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf); | |
1901 | /* Need at least one buffer on ring to get going */ | |
1902 | if (vnic_rq_desc_used(&enic->rq[0]) == 0) { | |
e057590b | 1903 | rtnl_unlock(); |
c97c894d RP |
1904 | netdev_err(netdev, "Unable to alloc receive buffers.\n"); |
1905 | return; | |
1906 | } | |
1907 | ||
1908 | /* Start RQ */ | |
1909 | vnic_rq_enable(&enic->rq[0]); | |
1910 | napi_enable(&enic->napi[0]); | |
1911 | vnic_intr_unmask(&enic->intr[0]); | |
1912 | enic_notify_timer_start(enic); | |
1913 | ||
1914 | rtnl_unlock(); | |
1915 | ||
1916 | netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu); | |
1917 | } | |
1918 | ||
01f2e4ea SF |
1919 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1920 | static void enic_poll_controller(struct net_device *netdev) | |
1921 | { | |
1922 | struct enic *enic = netdev_priv(netdev); | |
1923 | struct vnic_dev *vdev = enic->vdev; | |
717258ba | 1924 | unsigned int i, intr; |
01f2e4ea SF |
1925 | |
1926 | switch (vnic_dev_get_intr_mode(vdev)) { | |
1927 | case VNIC_DEV_INTR_MODE_MSIX: | |
717258ba VK |
1928 | for (i = 0; i < enic->rq_count; i++) { |
1929 | intr = enic_msix_rq_intr(enic, i); | |
4cfe8785 GV |
1930 | enic_isr_msix(enic->msix_entry[intr].vector, |
1931 | &enic->napi[i]); | |
717258ba | 1932 | } |
b880a954 VK |
1933 | |
1934 | for (i = 0; i < enic->wq_count; i++) { | |
1935 | intr = enic_msix_wq_intr(enic, i); | |
4cfe8785 GV |
1936 | enic_isr_msix(enic->msix_entry[intr].vector, |
1937 | &enic->napi[enic_cq_wq(enic, i)]); | |
b880a954 VK |
1938 | } |
1939 | ||
01f2e4ea SF |
1940 | break; |
1941 | case VNIC_DEV_INTR_MODE_MSI: | |
1942 | enic_isr_msi(enic->pdev->irq, enic); | |
1943 | break; | |
1944 | case VNIC_DEV_INTR_MODE_INTX: | |
1945 | enic_isr_legacy(enic->pdev->irq, netdev); | |
1946 | break; | |
1947 | default: | |
1948 | break; | |
1949 | } | |
1950 | } | |
1951 | #endif | |
1952 | ||
1953 | static int enic_dev_wait(struct vnic_dev *vdev, | |
1954 | int (*start)(struct vnic_dev *, int), | |
1955 | int (*finished)(struct vnic_dev *, int *), | |
1956 | int arg) | |
1957 | { | |
1958 | unsigned long time; | |
1959 | int done; | |
1960 | int err; | |
1961 | ||
1962 | BUG_ON(in_interrupt()); | |
1963 | ||
1964 | err = start(vdev, arg); | |
1965 | if (err) | |
1966 | return err; | |
1967 | ||
1968 | /* Wait for func to complete...2 seconds max | |
1969 | */ | |
1970 | ||
1971 | time = jiffies + (HZ * 2); | |
1972 | do { | |
1973 | ||
1974 | err = finished(vdev, &done); | |
1975 | if (err) | |
1976 | return err; | |
1977 | ||
1978 | if (done) | |
1979 | return 0; | |
1980 | ||
1981 | schedule_timeout_uninterruptible(HZ / 10); | |
1982 | ||
1983 | } while (time_after(time, jiffies)); | |
1984 | ||
1985 | return -ETIMEDOUT; | |
1986 | } | |
1987 | ||
1988 | static int enic_dev_open(struct enic *enic) | |
1989 | { | |
1990 | int err; | |
1991 | ||
1992 | err = enic_dev_wait(enic->vdev, vnic_dev_open, | |
1993 | vnic_dev_open_done, 0); | |
1994 | if (err) | |
a7a79deb VK |
1995 | dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n", |
1996 | err); | |
01f2e4ea SF |
1997 | |
1998 | return err; | |
1999 | } | |
2000 | ||
937317c7 GV |
2001 | static int enic_dev_soft_reset(struct enic *enic) |
2002 | { | |
2003 | int err; | |
2004 | ||
2005 | err = enic_dev_wait(enic->vdev, vnic_dev_soft_reset, | |
2006 | vnic_dev_soft_reset_done, 0); | |
2007 | if (err) | |
2008 | netdev_err(enic->netdev, "vNIC soft reset failed, err %d\n", | |
2009 | err); | |
2010 | ||
2011 | return err; | |
2012 | } | |
2013 | ||
99ef5639 | 2014 | static int enic_dev_hang_reset(struct enic *enic) |
01f2e4ea SF |
2015 | { |
2016 | int err; | |
2017 | ||
99ef5639 VK |
2018 | err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset, |
2019 | vnic_dev_hang_reset_done, 0); | |
01f2e4ea | 2020 | if (err) |
a7a79deb VK |
2021 | netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n", |
2022 | err); | |
01f2e4ea SF |
2023 | |
2024 | return err; | |
2025 | } | |
2026 | ||
4f675eb2 | 2027 | int __enic_set_rsskey(struct enic *enic) |
717258ba | 2028 | { |
c33d23c2 | 2029 | union vnic_rss_key *rss_key_buf_va; |
1f4f067f | 2030 | dma_addr_t rss_key_buf_pa; |
c33d23c2 | 2031 | int i, kidx, bidx, err; |
717258ba | 2032 | |
c33d23c2 ED |
2033 | rss_key_buf_va = pci_zalloc_consistent(enic->pdev, |
2034 | sizeof(union vnic_rss_key), | |
2035 | &rss_key_buf_pa); | |
717258ba VK |
2036 | if (!rss_key_buf_va) |
2037 | return -ENOMEM; | |
2038 | ||
c33d23c2 ED |
2039 | for (i = 0; i < ENIC_RSS_LEN; i++) { |
2040 | kidx = i / ENIC_RSS_BYTES_PER_KEY; | |
2041 | bidx = i % ENIC_RSS_BYTES_PER_KEY; | |
4f675eb2 | 2042 | rss_key_buf_va->key[kidx].b[bidx] = enic->rss_key[i]; |
c33d23c2 | 2043 | } |
8e091340 | 2044 | spin_lock_bh(&enic->devcmd_lock); |
717258ba VK |
2045 | err = enic_set_rss_key(enic, |
2046 | rss_key_buf_pa, | |
2047 | sizeof(union vnic_rss_key)); | |
8e091340 | 2048 | spin_unlock_bh(&enic->devcmd_lock); |
717258ba VK |
2049 | |
2050 | pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key), | |
2051 | rss_key_buf_va, rss_key_buf_pa); | |
2052 | ||
2053 | return err; | |
2054 | } | |
2055 | ||
4f675eb2 GV |
2056 | static int enic_set_rsskey(struct enic *enic) |
2057 | { | |
2058 | netdev_rss_key_fill(enic->rss_key, ENIC_RSS_LEN); | |
2059 | ||
2060 | return __enic_set_rsskey(enic); | |
2061 | } | |
2062 | ||
717258ba VK |
2063 | static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits) |
2064 | { | |
1f4f067f | 2065 | dma_addr_t rss_cpu_buf_pa; |
717258ba VK |
2066 | union vnic_rss_cpu *rss_cpu_buf_va = NULL; |
2067 | unsigned int i; | |
2068 | int err; | |
2069 | ||
2070 | rss_cpu_buf_va = pci_alloc_consistent(enic->pdev, | |
2071 | sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa); | |
2072 | if (!rss_cpu_buf_va) | |
2073 | return -ENOMEM; | |
2074 | ||
2075 | for (i = 0; i < (1 << rss_hash_bits); i++) | |
2076 | (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count; | |
2077 | ||
8e091340 | 2078 | spin_lock_bh(&enic->devcmd_lock); |
717258ba VK |
2079 | err = enic_set_rss_cpu(enic, |
2080 | rss_cpu_buf_pa, | |
2081 | sizeof(union vnic_rss_cpu)); | |
8e091340 | 2082 | spin_unlock_bh(&enic->devcmd_lock); |
717258ba VK |
2083 | |
2084 | pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu), | |
2085 | rss_cpu_buf_va, rss_cpu_buf_pa); | |
2086 | ||
2087 | return err; | |
2088 | } | |
2089 | ||
2090 | static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu, | |
2091 | u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable) | |
68f71708 | 2092 | { |
68f71708 SF |
2093 | const u8 tso_ipid_split_en = 0; |
2094 | const u8 ig_vlan_strip_en = 1; | |
383ab92f | 2095 | int err; |
68f71708 | 2096 | |
717258ba VK |
2097 | /* Enable VLAN tag stripping. |
2098 | */ | |
68f71708 | 2099 | |
8e091340 | 2100 | spin_lock_bh(&enic->devcmd_lock); |
383ab92f | 2101 | err = enic_set_nic_cfg(enic, |
68f71708 SF |
2102 | rss_default_cpu, rss_hash_type, |
2103 | rss_hash_bits, rss_base_cpu, | |
2104 | rss_enable, tso_ipid_split_en, | |
2105 | ig_vlan_strip_en); | |
8e091340 | 2106 | spin_unlock_bh(&enic->devcmd_lock); |
383ab92f VK |
2107 | |
2108 | return err; | |
2109 | } | |
2110 | ||
717258ba VK |
2111 | static int enic_set_rss_nic_cfg(struct enic *enic) |
2112 | { | |
2113 | struct device *dev = enic_get_dev(enic); | |
2114 | const u8 rss_default_cpu = 0; | |
2115 | const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 | | |
2116 | NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 | | |
2117 | NIC_CFG_RSS_HASH_TYPE_IPV6 | | |
2118 | NIC_CFG_RSS_HASH_TYPE_TCP_IPV6; | |
2119 | const u8 rss_hash_bits = 7; | |
2120 | const u8 rss_base_cpu = 0; | |
2121 | u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1); | |
2122 | ||
2123 | if (rss_enable) { | |
2124 | if (!enic_set_rsskey(enic)) { | |
2125 | if (enic_set_rsscpu(enic, rss_hash_bits)) { | |
2126 | rss_enable = 0; | |
2127 | dev_warn(dev, "RSS disabled, " | |
2128 | "Failed to set RSS cpu indirection table."); | |
2129 | } | |
2130 | } else { | |
2131 | rss_enable = 0; | |
2132 | dev_warn(dev, "RSS disabled, Failed to set RSS key.\n"); | |
2133 | } | |
2134 | } | |
2135 | ||
2136 | return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type, | |
2137 | rss_hash_bits, rss_base_cpu, rss_enable); | |
f8cac14a VK |
2138 | } |
2139 | ||
01f2e4ea SF |
2140 | static void enic_reset(struct work_struct *work) |
2141 | { | |
2142 | struct enic *enic = container_of(work, struct enic, reset); | |
2143 | ||
2144 | if (!netif_running(enic->netdev)) | |
2145 | return; | |
2146 | ||
2147 | rtnl_lock(); | |
2148 | ||
937317c7 GV |
2149 | spin_lock(&enic->enic_api_lock); |
2150 | enic_stop(enic->netdev); | |
2151 | enic_dev_soft_reset(enic); | |
2152 | enic_reset_addr_lists(enic); | |
2153 | enic_init_vnic_resources(enic); | |
2154 | enic_set_rss_nic_cfg(enic); | |
2155 | enic_dev_set_ig_vlan_rewrite_mode(enic); | |
2156 | enic_open(enic->netdev); | |
2157 | spin_unlock(&enic->enic_api_lock); | |
2158 | call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev); | |
2159 | ||
2160 | rtnl_unlock(); | |
2161 | } | |
2162 | ||
2163 | static void enic_tx_hang_reset(struct work_struct *work) | |
2164 | { | |
2165 | struct enic *enic = container_of(work, struct enic, tx_hang_reset); | |
2166 | ||
2167 | rtnl_lock(); | |
2168 | ||
0b038566 | 2169 | spin_lock(&enic->enic_api_lock); |
383ab92f | 2170 | enic_dev_hang_notify(enic); |
01f2e4ea | 2171 | enic_stop(enic->netdev); |
99ef5639 | 2172 | enic_dev_hang_reset(enic); |
e0afe53f | 2173 | enic_reset_addr_lists(enic); |
01f2e4ea | 2174 | enic_init_vnic_resources(enic); |
717258ba | 2175 | enic_set_rss_nic_cfg(enic); |
f8cac14a | 2176 | enic_dev_set_ig_vlan_rewrite_mode(enic); |
01f2e4ea | 2177 | enic_open(enic->netdev); |
0b038566 | 2178 | spin_unlock(&enic->enic_api_lock); |
d765bb41 | 2179 | call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev); |
01f2e4ea SF |
2180 | |
2181 | rtnl_unlock(); | |
2182 | } | |
2183 | ||
2184 | static int enic_set_intr_mode(struct enic *enic) | |
2185 | { | |
717258ba | 2186 | unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX); |
1cbb1a61 | 2187 | unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX); |
01f2e4ea SF |
2188 | unsigned int i; |
2189 | ||
2190 | /* Set interrupt mode (INTx, MSI, MSI-X) depending | |
717258ba | 2191 | * on system capabilities. |
01f2e4ea SF |
2192 | * |
2193 | * Try MSI-X first | |
2194 | * | |
2195 | * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs | |
2196 | * (the second to last INTR is used for WQ/RQ errors) | |
2197 | * (the last INTR is used for notifications) | |
2198 | */ | |
2199 | ||
2200 | BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2); | |
2201 | for (i = 0; i < n + m + 2; i++) | |
2202 | enic->msix_entry[i].entry = i; | |
2203 | ||
717258ba VK |
2204 | /* Use multiple RQs if RSS is enabled |
2205 | */ | |
2206 | ||
2207 | if (ENIC_SETTING(enic, RSS) && | |
2208 | enic->config.intr_mode < 1 && | |
01f2e4ea SF |
2209 | enic->rq_count >= n && |
2210 | enic->wq_count >= m && | |
2211 | enic->cq_count >= n + m && | |
717258ba | 2212 | enic->intr_count >= n + m + 2) { |
01f2e4ea | 2213 | |
abbb6a37 AG |
2214 | if (pci_enable_msix_range(enic->pdev, enic->msix_entry, |
2215 | n + m + 2, n + m + 2) > 0) { | |
01f2e4ea | 2216 | |
717258ba VK |
2217 | enic->rq_count = n; |
2218 | enic->wq_count = m; | |
2219 | enic->cq_count = n + m; | |
2220 | enic->intr_count = n + m + 2; | |
01f2e4ea | 2221 | |
717258ba VK |
2222 | vnic_dev_set_intr_mode(enic->vdev, |
2223 | VNIC_DEV_INTR_MODE_MSIX); | |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | } | |
2228 | ||
2229 | if (enic->config.intr_mode < 1 && | |
2230 | enic->rq_count >= 1 && | |
2231 | enic->wq_count >= m && | |
2232 | enic->cq_count >= 1 + m && | |
2233 | enic->intr_count >= 1 + m + 2) { | |
abbb6a37 AG |
2234 | if (pci_enable_msix_range(enic->pdev, enic->msix_entry, |
2235 | 1 + m + 2, 1 + m + 2) > 0) { | |
717258ba VK |
2236 | |
2237 | enic->rq_count = 1; | |
2238 | enic->wq_count = m; | |
2239 | enic->cq_count = 1 + m; | |
2240 | enic->intr_count = 1 + m + 2; | |
2241 | ||
2242 | vnic_dev_set_intr_mode(enic->vdev, | |
2243 | VNIC_DEV_INTR_MODE_MSIX); | |
2244 | ||
2245 | return 0; | |
2246 | } | |
01f2e4ea SF |
2247 | } |
2248 | ||
2249 | /* Next try MSI | |
2250 | * | |
2251 | * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR | |
2252 | */ | |
2253 | ||
2254 | if (enic->config.intr_mode < 2 && | |
2255 | enic->rq_count >= 1 && | |
2256 | enic->wq_count >= 1 && | |
2257 | enic->cq_count >= 2 && | |
2258 | enic->intr_count >= 1 && | |
2259 | !pci_enable_msi(enic->pdev)) { | |
2260 | ||
2261 | enic->rq_count = 1; | |
2262 | enic->wq_count = 1; | |
2263 | enic->cq_count = 2; | |
2264 | enic->intr_count = 1; | |
2265 | ||
2266 | vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI); | |
2267 | ||
2268 | return 0; | |
2269 | } | |
2270 | ||
2271 | /* Next try INTx | |
2272 | * | |
2273 | * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs | |
2274 | * (the first INTR is used for WQ/RQ) | |
2275 | * (the second INTR is used for WQ/RQ errors) | |
2276 | * (the last INTR is used for notifications) | |
2277 | */ | |
2278 | ||
2279 | if (enic->config.intr_mode < 3 && | |
2280 | enic->rq_count >= 1 && | |
2281 | enic->wq_count >= 1 && | |
2282 | enic->cq_count >= 2 && | |
2283 | enic->intr_count >= 3) { | |
2284 | ||
2285 | enic->rq_count = 1; | |
2286 | enic->wq_count = 1; | |
2287 | enic->cq_count = 2; | |
2288 | enic->intr_count = 3; | |
2289 | ||
2290 | vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX); | |
2291 | ||
2292 | return 0; | |
2293 | } | |
2294 | ||
2295 | vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN); | |
2296 | ||
2297 | return -EINVAL; | |
2298 | } | |
2299 | ||
2300 | static void enic_clear_intr_mode(struct enic *enic) | |
2301 | { | |
2302 | switch (vnic_dev_get_intr_mode(enic->vdev)) { | |
2303 | case VNIC_DEV_INTR_MODE_MSIX: | |
2304 | pci_disable_msix(enic->pdev); | |
2305 | break; | |
2306 | case VNIC_DEV_INTR_MODE_MSI: | |
2307 | pci_disable_msi(enic->pdev); | |
2308 | break; | |
2309 | default: | |
2310 | break; | |
2311 | } | |
2312 | ||
2313 | vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN); | |
2314 | } | |
2315 | ||
f8bd9091 SF |
2316 | static const struct net_device_ops enic_netdev_dynamic_ops = { |
2317 | .ndo_open = enic_open, | |
2318 | .ndo_stop = enic_stop, | |
2319 | .ndo_start_xmit = enic_hard_start_xmit, | |
f20530bc | 2320 | .ndo_get_stats64 = enic_get_stats, |
f8bd9091 | 2321 | .ndo_validate_addr = eth_validate_addr, |
319d7e84 | 2322 | .ndo_set_rx_mode = enic_set_rx_mode, |
f8bd9091 SF |
2323 | .ndo_set_mac_address = enic_set_mac_address_dynamic, |
2324 | .ndo_change_mtu = enic_change_mtu, | |
f8bd9091 SF |
2325 | .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid, |
2326 | .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid, | |
2327 | .ndo_tx_timeout = enic_tx_timeout, | |
2328 | .ndo_set_vf_port = enic_set_vf_port, | |
2329 | .ndo_get_vf_port = enic_get_vf_port, | |
0b1c00fc | 2330 | .ndo_set_vf_mac = enic_set_vf_mac, |
f8bd9091 SF |
2331 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2332 | .ndo_poll_controller = enic_poll_controller, | |
2333 | #endif | |
a145df23 GV |
2334 | #ifdef CONFIG_RFS_ACCEL |
2335 | .ndo_rx_flow_steer = enic_rx_flow_steer, | |
2336 | #endif | |
14747cd9 GV |
2337 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2338 | .ndo_busy_poll = enic_busy_poll, | |
2339 | #endif | |
f8bd9091 SF |
2340 | }; |
2341 | ||
afe29f7a SH |
2342 | static const struct net_device_ops enic_netdev_ops = { |
2343 | .ndo_open = enic_open, | |
2344 | .ndo_stop = enic_stop, | |
00829823 | 2345 | .ndo_start_xmit = enic_hard_start_xmit, |
f20530bc | 2346 | .ndo_get_stats64 = enic_get_stats, |
afe29f7a | 2347 | .ndo_validate_addr = eth_validate_addr, |
f8bd9091 | 2348 | .ndo_set_mac_address = enic_set_mac_address, |
319d7e84 | 2349 | .ndo_set_rx_mode = enic_set_rx_mode, |
afe29f7a | 2350 | .ndo_change_mtu = enic_change_mtu, |
afe29f7a SH |
2351 | .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid, |
2352 | .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid, | |
2353 | .ndo_tx_timeout = enic_tx_timeout, | |
3f192795 RP |
2354 | .ndo_set_vf_port = enic_set_vf_port, |
2355 | .ndo_get_vf_port = enic_get_vf_port, | |
2356 | .ndo_set_vf_mac = enic_set_vf_mac, | |
afe29f7a SH |
2357 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2358 | .ndo_poll_controller = enic_poll_controller, | |
2359 | #endif | |
a145df23 GV |
2360 | #ifdef CONFIG_RFS_ACCEL |
2361 | .ndo_rx_flow_steer = enic_rx_flow_steer, | |
2362 | #endif | |
14747cd9 GV |
2363 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2364 | .ndo_busy_poll = enic_busy_poll, | |
2365 | #endif | |
afe29f7a SH |
2366 | }; |
2367 | ||
2fdba388 | 2368 | static void enic_dev_deinit(struct enic *enic) |
6fdfa970 | 2369 | { |
717258ba VK |
2370 | unsigned int i; |
2371 | ||
14747cd9 GV |
2372 | for (i = 0; i < enic->rq_count; i++) { |
2373 | napi_hash_del(&enic->napi[i]); | |
717258ba | 2374 | netif_napi_del(&enic->napi[i]); |
14747cd9 | 2375 | } |
4cfe8785 GV |
2376 | if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) |
2377 | for (i = 0; i < enic->wq_count; i++) | |
2378 | netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]); | |
717258ba | 2379 | |
6fdfa970 SF |
2380 | enic_free_vnic_resources(enic); |
2381 | enic_clear_intr_mode(enic); | |
322cf7e3 | 2382 | enic_free_affinity_hint(enic); |
6fdfa970 SF |
2383 | } |
2384 | ||
3f255dcc GV |
2385 | static void enic_kdump_kernel_config(struct enic *enic) |
2386 | { | |
2387 | if (is_kdump_kernel()) { | |
2388 | dev_info(enic_get_dev(enic), "Running from within kdump kernel. Using minimal resources\n"); | |
2389 | enic->rq_count = 1; | |
2390 | enic->wq_count = 1; | |
2391 | enic->config.rq_desc_count = ENIC_MIN_RQ_DESCS; | |
2392 | enic->config.wq_desc_count = ENIC_MIN_WQ_DESCS; | |
2393 | enic->config.mtu = min_t(u16, 1500, enic->config.mtu); | |
2394 | } | |
2395 | } | |
2396 | ||
2fdba388 | 2397 | static int enic_dev_init(struct enic *enic) |
6fdfa970 | 2398 | { |
a7a79deb | 2399 | struct device *dev = enic_get_dev(enic); |
6fdfa970 | 2400 | struct net_device *netdev = enic->netdev; |
717258ba | 2401 | unsigned int i; |
6fdfa970 SF |
2402 | int err; |
2403 | ||
ea7ea65a VK |
2404 | /* Get interrupt coalesce timer info */ |
2405 | err = enic_dev_intr_coal_timer_info(enic); | |
2406 | if (err) { | |
2407 | dev_warn(dev, "Using default conversion factor for " | |
2408 | "interrupt coalesce timer\n"); | |
2409 | vnic_dev_intr_coal_timer_info_default(enic->vdev); | |
2410 | } | |
2411 | ||
6fdfa970 SF |
2412 | /* Get vNIC configuration |
2413 | */ | |
2414 | ||
2415 | err = enic_get_vnic_config(enic); | |
2416 | if (err) { | |
a7a79deb | 2417 | dev_err(dev, "Get vNIC configuration failed, aborting\n"); |
6fdfa970 SF |
2418 | return err; |
2419 | } | |
2420 | ||
2421 | /* Get available resource counts | |
2422 | */ | |
2423 | ||
2424 | enic_get_res_counts(enic); | |
2425 | ||
3f255dcc GV |
2426 | /* modify resource count if we are in kdump_kernel |
2427 | */ | |
2428 | enic_kdump_kernel_config(enic); | |
2429 | ||
6fdfa970 SF |
2430 | /* Set interrupt mode based on resource counts and system |
2431 | * capabilities | |
2432 | */ | |
2433 | ||
2434 | err = enic_set_intr_mode(enic); | |
2435 | if (err) { | |
a7a79deb VK |
2436 | dev_err(dev, "Failed to set intr mode based on resource " |
2437 | "counts and system capabilities, aborting\n"); | |
6fdfa970 SF |
2438 | return err; |
2439 | } | |
2440 | ||
2441 | /* Allocate and configure vNIC resources | |
2442 | */ | |
2443 | ||
2444 | err = enic_alloc_vnic_resources(enic); | |
2445 | if (err) { | |
a7a79deb | 2446 | dev_err(dev, "Failed to alloc vNIC resources, aborting\n"); |
6fdfa970 SF |
2447 | goto err_out_free_vnic_resources; |
2448 | } | |
2449 | ||
2450 | enic_init_vnic_resources(enic); | |
2451 | ||
717258ba | 2452 | err = enic_set_rss_nic_cfg(enic); |
6fdfa970 | 2453 | if (err) { |
a7a79deb | 2454 | dev_err(dev, "Failed to config nic, aborting\n"); |
6fdfa970 SF |
2455 | goto err_out_free_vnic_resources; |
2456 | } | |
2457 | ||
2458 | switch (vnic_dev_get_intr_mode(enic->vdev)) { | |
2459 | default: | |
717258ba | 2460 | netif_napi_add(netdev, &enic->napi[0], enic_poll, 64); |
6fdfa970 SF |
2461 | break; |
2462 | case VNIC_DEV_INTR_MODE_MSIX: | |
14747cd9 | 2463 | for (i = 0; i < enic->rq_count; i++) { |
717258ba | 2464 | netif_napi_add(netdev, &enic->napi[i], |
4cfe8785 | 2465 | enic_poll_msix_rq, NAPI_POLL_WEIGHT); |
14747cd9 | 2466 | } |
4cfe8785 GV |
2467 | for (i = 0; i < enic->wq_count; i++) |
2468 | netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)], | |
2469 | enic_poll_msix_wq, NAPI_POLL_WEIGHT); | |
6fdfa970 SF |
2470 | break; |
2471 | } | |
2472 | ||
2473 | return 0; | |
2474 | ||
2475 | err_out_free_vnic_resources: | |
322cf7e3 | 2476 | enic_free_affinity_hint(enic); |
6fdfa970 SF |
2477 | enic_clear_intr_mode(enic); |
2478 | enic_free_vnic_resources(enic); | |
2479 | ||
2480 | return err; | |
2481 | } | |
2482 | ||
27e6c7d3 SF |
2483 | static void enic_iounmap(struct enic *enic) |
2484 | { | |
2485 | unsigned int i; | |
2486 | ||
2487 | for (i = 0; i < ARRAY_SIZE(enic->bar); i++) | |
2488 | if (enic->bar[i].vaddr) | |
2489 | iounmap(enic->bar[i].vaddr); | |
2490 | } | |
2491 | ||
1dd06ae8 | 2492 | static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
01f2e4ea | 2493 | { |
a7a79deb | 2494 | struct device *dev = &pdev->dev; |
01f2e4ea SF |
2495 | struct net_device *netdev; |
2496 | struct enic *enic; | |
2497 | int using_dac = 0; | |
2498 | unsigned int i; | |
2499 | int err; | |
8749b427 RP |
2500 | #ifdef CONFIG_PCI_IOV |
2501 | int pos = 0; | |
2502 | #endif | |
b67f231d | 2503 | int num_pps = 1; |
01f2e4ea | 2504 | |
01f2e4ea SF |
2505 | /* Allocate net device structure and initialize. Private |
2506 | * instance data is initialized to zero. | |
2507 | */ | |
2508 | ||
822473b6 | 2509 | netdev = alloc_etherdev_mqs(sizeof(struct enic), |
2510 | ENIC_RQ_MAX, ENIC_WQ_MAX); | |
41de8d4c | 2511 | if (!netdev) |
01f2e4ea | 2512 | return -ENOMEM; |
01f2e4ea | 2513 | |
01f2e4ea SF |
2514 | pci_set_drvdata(pdev, netdev); |
2515 | ||
2516 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
2517 | ||
2518 | enic = netdev_priv(netdev); | |
2519 | enic->netdev = netdev; | |
2520 | enic->pdev = pdev; | |
2521 | ||
2522 | /* Setup PCI resources | |
2523 | */ | |
2524 | ||
29046f9b | 2525 | err = pci_enable_device_mem(pdev); |
01f2e4ea | 2526 | if (err) { |
a7a79deb | 2527 | dev_err(dev, "Cannot enable PCI device, aborting\n"); |
01f2e4ea SF |
2528 | goto err_out_free_netdev; |
2529 | } | |
2530 | ||
2531 | err = pci_request_regions(pdev, DRV_NAME); | |
2532 | if (err) { | |
a7a79deb | 2533 | dev_err(dev, "Cannot request PCI regions, aborting\n"); |
01f2e4ea SF |
2534 | goto err_out_disable_device; |
2535 | } | |
2536 | ||
2537 | pci_set_master(pdev); | |
2538 | ||
2539 | /* Query PCI controller on system for DMA addressing | |
624dbf55 | 2540 | * limitation for the device. Try 64-bit first, and |
01f2e4ea SF |
2541 | * fail to 32-bit. |
2542 | */ | |
2543 | ||
624dbf55 | 2544 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
01f2e4ea | 2545 | if (err) { |
284901a9 | 2546 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
01f2e4ea | 2547 | if (err) { |
a7a79deb | 2548 | dev_err(dev, "No usable DMA configuration, aborting\n"); |
01f2e4ea SF |
2549 | goto err_out_release_regions; |
2550 | } | |
284901a9 | 2551 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
01f2e4ea | 2552 | if (err) { |
a7a79deb VK |
2553 | dev_err(dev, "Unable to obtain %u-bit DMA " |
2554 | "for consistent allocations, aborting\n", 32); | |
01f2e4ea SF |
2555 | goto err_out_release_regions; |
2556 | } | |
2557 | } else { | |
624dbf55 | 2558 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
01f2e4ea | 2559 | if (err) { |
a7a79deb | 2560 | dev_err(dev, "Unable to obtain %u-bit DMA " |
624dbf55 | 2561 | "for consistent allocations, aborting\n", 64); |
01f2e4ea SF |
2562 | goto err_out_release_regions; |
2563 | } | |
2564 | using_dac = 1; | |
2565 | } | |
2566 | ||
27e6c7d3 | 2567 | /* Map vNIC resources from BAR0-5 |
01f2e4ea SF |
2568 | */ |
2569 | ||
27e6c7d3 SF |
2570 | for (i = 0; i < ARRAY_SIZE(enic->bar); i++) { |
2571 | if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM)) | |
2572 | continue; | |
2573 | enic->bar[i].len = pci_resource_len(pdev, i); | |
2574 | enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len); | |
2575 | if (!enic->bar[i].vaddr) { | |
a7a79deb | 2576 | dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i); |
27e6c7d3 SF |
2577 | err = -ENODEV; |
2578 | goto err_out_iounmap; | |
2579 | } | |
2580 | enic->bar[i].bus_addr = pci_resource_start(pdev, i); | |
01f2e4ea SF |
2581 | } |
2582 | ||
2583 | /* Register vNIC device | |
2584 | */ | |
2585 | ||
27e6c7d3 SF |
2586 | enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar, |
2587 | ARRAY_SIZE(enic->bar)); | |
01f2e4ea | 2588 | if (!enic->vdev) { |
a7a79deb | 2589 | dev_err(dev, "vNIC registration failed, aborting\n"); |
01f2e4ea SF |
2590 | err = -ENODEV; |
2591 | goto err_out_iounmap; | |
2592 | } | |
2593 | ||
373fb087 GV |
2594 | err = vnic_devcmd_init(enic->vdev); |
2595 | ||
2596 | if (err) | |
2597 | goto err_out_vnic_unregister; | |
2598 | ||
8749b427 RP |
2599 | #ifdef CONFIG_PCI_IOV |
2600 | /* Get number of subvnics */ | |
2601 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); | |
2602 | if (pos) { | |
2603 | pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, | |
413708bb | 2604 | &enic->num_vfs); |
8749b427 RP |
2605 | if (enic->num_vfs) { |
2606 | err = pci_enable_sriov(pdev, enic->num_vfs); | |
2607 | if (err) { | |
2608 | dev_err(dev, "SRIOV enable failed, aborting." | |
2609 | " pci_enable_sriov() returned %d\n", | |
2610 | err); | |
2611 | goto err_out_vnic_unregister; | |
2612 | } | |
2613 | enic->priv_flags |= ENIC_SRIOV_ENABLED; | |
b67f231d | 2614 | num_pps = enic->num_vfs; |
8749b427 RP |
2615 | } |
2616 | } | |
8749b427 | 2617 | #endif |
ca2b721d | 2618 | |
3f192795 | 2619 | /* Allocate structure for port profiles */ |
a1de2219 | 2620 | enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL); |
3f192795 | 2621 | if (!enic->pp) { |
3f192795 | 2622 | err = -ENOMEM; |
ca2b721d | 2623 | goto err_out_disable_sriov_pp; |
3f192795 RP |
2624 | } |
2625 | ||
01f2e4ea SF |
2626 | /* Issue device open to get device in known state |
2627 | */ | |
2628 | ||
2629 | err = enic_dev_open(enic); | |
2630 | if (err) { | |
a7a79deb | 2631 | dev_err(dev, "vNIC dev open failed, aborting\n"); |
ca2b721d | 2632 | goto err_out_disable_sriov; |
01f2e4ea SF |
2633 | } |
2634 | ||
69161425 VK |
2635 | /* Setup devcmd lock |
2636 | */ | |
2637 | ||
2638 | spin_lock_init(&enic->devcmd_lock); | |
0b038566 | 2639 | spin_lock_init(&enic->enic_api_lock); |
69161425 VK |
2640 | |
2641 | /* | |
2642 | * Set ingress vlan rewrite mode before vnic initialization | |
2643 | */ | |
2644 | ||
2645 | err = enic_dev_set_ig_vlan_rewrite_mode(enic); | |
2646 | if (err) { | |
2647 | dev_err(dev, | |
2648 | "Failed to set ingress vlan rewrite mode, aborting.\n"); | |
2649 | goto err_out_dev_close; | |
2650 | } | |
2651 | ||
01f2e4ea SF |
2652 | /* Issue device init to initialize the vnic-to-switch link. |
2653 | * We'll start with carrier off and wait for link UP | |
2654 | * notification later to turn on carrier. We don't need | |
2655 | * to wait here for the vnic-to-switch link initialization | |
2656 | * to complete; link UP notification is the indication that | |
2657 | * the process is complete. | |
2658 | */ | |
2659 | ||
2660 | netif_carrier_off(netdev); | |
2661 | ||
a7a79deb VK |
2662 | /* Do not call dev_init for a dynamic vnic. |
2663 | * For a dynamic vnic, init_prov_info will be | |
2664 | * called later by an upper layer. | |
2665 | */ | |
2666 | ||
2b68c181 | 2667 | if (!enic_is_dynamic(enic)) { |
f8bd9091 SF |
2668 | err = vnic_dev_init(enic->vdev, 0); |
2669 | if (err) { | |
a7a79deb | 2670 | dev_err(dev, "vNIC dev init failed, aborting\n"); |
f8bd9091 SF |
2671 | goto err_out_dev_close; |
2672 | } | |
01f2e4ea SF |
2673 | } |
2674 | ||
6fdfa970 | 2675 | err = enic_dev_init(enic); |
01f2e4ea | 2676 | if (err) { |
a7a79deb | 2677 | dev_err(dev, "Device initialization failed, aborting\n"); |
01f2e4ea SF |
2678 | goto err_out_dev_close; |
2679 | } | |
2680 | ||
822473b6 | 2681 | netif_set_real_num_tx_queues(netdev, enic->wq_count); |
bf751ba8 | 2682 | netif_set_real_num_rx_queues(netdev, enic->rq_count); |
822473b6 | 2683 | |
383ab92f | 2684 | /* Setup notification timer, HW reset task, and wq locks |
01f2e4ea SF |
2685 | */ |
2686 | ||
2687 | init_timer(&enic->notify_timer); | |
2688 | enic->notify_timer.function = enic_notify_timer; | |
2689 | enic->notify_timer.data = (unsigned long)enic; | |
2690 | ||
7c2ce6e6 | 2691 | enic_set_rx_coal_setting(enic); |
01f2e4ea | 2692 | INIT_WORK(&enic->reset, enic_reset); |
937317c7 | 2693 | INIT_WORK(&enic->tx_hang_reset, enic_tx_hang_reset); |
c97c894d | 2694 | INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work); |
01f2e4ea SF |
2695 | |
2696 | for (i = 0; i < enic->wq_count; i++) | |
2697 | spin_lock_init(&enic->wq_lock[i]); | |
2698 | ||
01f2e4ea SF |
2699 | /* Register net device |
2700 | */ | |
2701 | ||
2702 | enic->port_mtu = enic->config.mtu; | |
2703 | (void)enic_change_mtu(netdev, enic->port_mtu); | |
2704 | ||
2705 | err = enic_set_mac_addr(netdev, enic->mac_addr); | |
2706 | if (err) { | |
a7a79deb | 2707 | dev_err(dev, "Invalid MAC address, aborting\n"); |
6fdfa970 | 2708 | goto err_out_dev_deinit; |
01f2e4ea SF |
2709 | } |
2710 | ||
7c844599 | 2711 | enic->tx_coalesce_usecs = enic->config.intr_timer_usec; |
7c2ce6e6 SS |
2712 | /* rx coalesce time already got initialized. This gets used |
2713 | * if adaptive coal is turned off | |
2714 | */ | |
7c844599 SF |
2715 | enic->rx_coalesce_usecs = enic->tx_coalesce_usecs; |
2716 | ||
7335903c | 2717 | if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) |
f8bd9091 SF |
2718 | netdev->netdev_ops = &enic_netdev_dynamic_ops; |
2719 | else | |
2720 | netdev->netdev_ops = &enic_netdev_ops; | |
2721 | ||
01f2e4ea | 2722 | netdev->watchdog_timeo = 2 * HZ; |
f13bbc2f | 2723 | enic_set_ethtool_ops(netdev); |
01f2e4ea | 2724 | |
f646968f | 2725 | netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
1825aca6 | 2726 | if (ENIC_SETTING(enic, LOOP)) { |
f646968f | 2727 | netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
1825aca6 VK |
2728 | enic->loop_enable = 1; |
2729 | enic->loop_tag = enic->config.loop_tag; | |
2730 | dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag); | |
2731 | } | |
01f2e4ea | 2732 | if (ENIC_SETTING(enic, TXCSUM)) |
5ec8f9b8 | 2733 | netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM; |
01f2e4ea | 2734 | if (ENIC_SETTING(enic, TSO)) |
5ec8f9b8 | 2735 | netdev->hw_features |= NETIF_F_TSO | |
01f2e4ea | 2736 | NETIF_F_TSO6 | NETIF_F_TSO_ECN; |
bf751ba8 | 2737 | if (ENIC_SETTING(enic, RSS)) |
2738 | netdev->hw_features |= NETIF_F_RXHASH; | |
5ec8f9b8 MM |
2739 | if (ENIC_SETTING(enic, RXCSUM)) |
2740 | netdev->hw_features |= NETIF_F_RXCSUM; | |
2741 | ||
2742 | netdev->features |= netdev->hw_features; | |
e7600449 | 2743 | netdev->vlan_features |= netdev->features; |
5ec8f9b8 | 2744 | |
a145df23 GV |
2745 | #ifdef CONFIG_RFS_ACCEL |
2746 | netdev->hw_features |= NETIF_F_NTUPLE; | |
2747 | #endif | |
2748 | ||
01f2e4ea SF |
2749 | if (using_dac) |
2750 | netdev->features |= NETIF_F_HIGHDMA; | |
2751 | ||
01789349 JP |
2752 | netdev->priv_flags |= IFF_UNICAST_FLT; |
2753 | ||
01f2e4ea SF |
2754 | err = register_netdev(netdev); |
2755 | if (err) { | |
a7a79deb | 2756 | dev_err(dev, "Cannot register net device, aborting\n"); |
6fdfa970 | 2757 | goto err_out_dev_deinit; |
01f2e4ea | 2758 | } |
a03bb56e | 2759 | enic->rx_copybreak = RX_COPYBREAK_DEFAULT; |
01f2e4ea SF |
2760 | |
2761 | return 0; | |
2762 | ||
6fdfa970 SF |
2763 | err_out_dev_deinit: |
2764 | enic_dev_deinit(enic); | |
01f2e4ea SF |
2765 | err_out_dev_close: |
2766 | vnic_dev_close(enic->vdev); | |
8749b427 | 2767 | err_out_disable_sriov: |
ca2b721d RP |
2768 | kfree(enic->pp); |
2769 | err_out_disable_sriov_pp: | |
8749b427 RP |
2770 | #ifdef CONFIG_PCI_IOV |
2771 | if (enic_sriov_enabled(enic)) { | |
2772 | pci_disable_sriov(pdev); | |
2773 | enic->priv_flags &= ~ENIC_SRIOV_ENABLED; | |
2774 | } | |
8749b427 | 2775 | #endif |
1a69205c | 2776 | err_out_vnic_unregister: |
35d87e33 | 2777 | vnic_dev_unregister(enic->vdev); |
01f2e4ea SF |
2778 | err_out_iounmap: |
2779 | enic_iounmap(enic); | |
2780 | err_out_release_regions: | |
2781 | pci_release_regions(pdev); | |
2782 | err_out_disable_device: | |
2783 | pci_disable_device(pdev); | |
2784 | err_out_free_netdev: | |
01f2e4ea SF |
2785 | free_netdev(netdev); |
2786 | ||
2787 | return err; | |
2788 | } | |
2789 | ||
854de92f | 2790 | static void enic_remove(struct pci_dev *pdev) |
01f2e4ea SF |
2791 | { |
2792 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2793 | ||
2794 | if (netdev) { | |
2795 | struct enic *enic = netdev_priv(netdev); | |
2796 | ||
23f333a2 | 2797 | cancel_work_sync(&enic->reset); |
c97c894d | 2798 | cancel_work_sync(&enic->change_mtu_work); |
01f2e4ea | 2799 | unregister_netdev(netdev); |
6fdfa970 | 2800 | enic_dev_deinit(enic); |
01f2e4ea | 2801 | vnic_dev_close(enic->vdev); |
8749b427 RP |
2802 | #ifdef CONFIG_PCI_IOV |
2803 | if (enic_sriov_enabled(enic)) { | |
2804 | pci_disable_sriov(pdev); | |
2805 | enic->priv_flags &= ~ENIC_SRIOV_ENABLED; | |
2806 | } | |
2807 | #endif | |
3f192795 | 2808 | kfree(enic->pp); |
01f2e4ea SF |
2809 | vnic_dev_unregister(enic->vdev); |
2810 | enic_iounmap(enic); | |
2811 | pci_release_regions(pdev); | |
2812 | pci_disable_device(pdev); | |
01f2e4ea SF |
2813 | free_netdev(netdev); |
2814 | } | |
2815 | } | |
2816 | ||
2817 | static struct pci_driver enic_driver = { | |
2818 | .name = DRV_NAME, | |
2819 | .id_table = enic_id_table, | |
2820 | .probe = enic_probe, | |
854de92f | 2821 | .remove = enic_remove, |
01f2e4ea SF |
2822 | }; |
2823 | ||
2824 | static int __init enic_init_module(void) | |
2825 | { | |
a7a79deb | 2826 | pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION); |
01f2e4ea SF |
2827 | |
2828 | return pci_register_driver(&enic_driver); | |
2829 | } | |
2830 | ||
2831 | static void __exit enic_cleanup_module(void) | |
2832 | { | |
2833 | pci_unregister_driver(&enic_driver); | |
2834 | } | |
2835 | ||
2836 | module_init(enic_init_module); | |
2837 | module_exit(enic_cleanup_module); |