Commit | Line | Data |
---|---|---|
1d22e05d LB |
1 | /* |
2 | * EP93xx ethernet network device driver | |
3 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | |
4 | * Dedicated to Marija Kulikova. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
df2f7ec8 HS |
12 | #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ |
13 | ||
1d22e05d LB |
14 | #include <linux/dma-mapping.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/etherdevice.h> | |
20 | #include <linux/ethtool.h> | |
a6b7a407 | 21 | #include <linux/interrupt.h> |
1d22e05d LB |
22 | #include <linux/moduleparam.h> |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/delay.h> | |
df2f7ec8 | 25 | #include <linux/io.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
df2f7ec8 HS |
27 | |
28 | #include <mach/hardware.h> | |
1d22e05d LB |
29 | |
30 | #define DRV_MODULE_NAME "ep93xx-eth" | |
31 | #define DRV_MODULE_VERSION "0.1" | |
32 | ||
33 | #define RX_QUEUE_ENTRIES 64 | |
34 | #define TX_QUEUE_ENTRIES 8 | |
35 | ||
36 | #define MAX_PKT_SIZE 2044 | |
37 | #define PKT_BUF_SIZE 2048 | |
38 | ||
39 | #define REG_RXCTL 0x0000 | |
40 | #define REG_RXCTL_DEFAULT 0x00073800 | |
41 | #define REG_TXCTL 0x0004 | |
42 | #define REG_TXCTL_ENABLE 0x00000001 | |
43 | #define REG_MIICMD 0x0010 | |
44 | #define REG_MIICMD_READ 0x00008000 | |
45 | #define REG_MIICMD_WRITE 0x00004000 | |
46 | #define REG_MIIDATA 0x0014 | |
47 | #define REG_MIISTS 0x0018 | |
48 | #define REG_MIISTS_BUSY 0x00000001 | |
49 | #define REG_SELFCTL 0x0020 | |
50 | #define REG_SELFCTL_RESET 0x00000001 | |
51 | #define REG_INTEN 0x0024 | |
52 | #define REG_INTEN_TX 0x00000008 | |
53 | #define REG_INTEN_RX 0x00000007 | |
54 | #define REG_INTSTSP 0x0028 | |
55 | #define REG_INTSTS_TX 0x00000008 | |
56 | #define REG_INTSTS_RX 0x00000004 | |
57 | #define REG_INTSTSC 0x002c | |
58 | #define REG_AFP 0x004c | |
59 | #define REG_INDAD0 0x0050 | |
60 | #define REG_INDAD1 0x0051 | |
61 | #define REG_INDAD2 0x0052 | |
62 | #define REG_INDAD3 0x0053 | |
63 | #define REG_INDAD4 0x0054 | |
64 | #define REG_INDAD5 0x0055 | |
65 | #define REG_GIINTMSK 0x0064 | |
66 | #define REG_GIINTMSK_ENABLE 0x00008000 | |
67 | #define REG_BMCTL 0x0080 | |
68 | #define REG_BMCTL_ENABLE_TX 0x00000100 | |
69 | #define REG_BMCTL_ENABLE_RX 0x00000001 | |
70 | #define REG_BMSTS 0x0084 | |
71 | #define REG_BMSTS_RX_ACTIVE 0x00000008 | |
72 | #define REG_RXDQBADD 0x0090 | |
73 | #define REG_RXDQBLEN 0x0094 | |
74 | #define REG_RXDCURADD 0x0098 | |
75 | #define REG_RXDENQ 0x009c | |
76 | #define REG_RXSTSQBADD 0x00a0 | |
77 | #define REG_RXSTSQBLEN 0x00a4 | |
78 | #define REG_RXSTSQCURADD 0x00a8 | |
79 | #define REG_RXSTSENQ 0x00ac | |
80 | #define REG_TXDQBADD 0x00b0 | |
81 | #define REG_TXDQBLEN 0x00b4 | |
82 | #define REG_TXDQCURADD 0x00b8 | |
83 | #define REG_TXDENQ 0x00bc | |
84 | #define REG_TXSTSQBADD 0x00c0 | |
85 | #define REG_TXSTSQBLEN 0x00c4 | |
86 | #define REG_TXSTSQCURADD 0x00c8 | |
87 | #define REG_MAXFRMLEN 0x00e8 | |
88 | ||
89 | struct ep93xx_rdesc | |
90 | { | |
91 | u32 buf_addr; | |
92 | u32 rdesc1; | |
93 | }; | |
94 | ||
95 | #define RDESC1_NSOF 0x80000000 | |
96 | #define RDESC1_BUFFER_INDEX 0x7fff0000 | |
97 | #define RDESC1_BUFFER_LENGTH 0x0000ffff | |
98 | ||
99 | struct ep93xx_rstat | |
100 | { | |
101 | u32 rstat0; | |
102 | u32 rstat1; | |
103 | }; | |
104 | ||
105 | #define RSTAT0_RFP 0x80000000 | |
106 | #define RSTAT0_RWE 0x40000000 | |
107 | #define RSTAT0_EOF 0x20000000 | |
108 | #define RSTAT0_EOB 0x10000000 | |
109 | #define RSTAT0_AM 0x00c00000 | |
110 | #define RSTAT0_RX_ERR 0x00200000 | |
111 | #define RSTAT0_OE 0x00100000 | |
112 | #define RSTAT0_FE 0x00080000 | |
113 | #define RSTAT0_RUNT 0x00040000 | |
114 | #define RSTAT0_EDATA 0x00020000 | |
115 | #define RSTAT0_CRCE 0x00010000 | |
116 | #define RSTAT0_CRCI 0x00008000 | |
117 | #define RSTAT0_HTI 0x00003f00 | |
118 | #define RSTAT1_RFP 0x80000000 | |
119 | #define RSTAT1_BUFFER_INDEX 0x7fff0000 | |
120 | #define RSTAT1_FRAME_LENGTH 0x0000ffff | |
121 | ||
122 | struct ep93xx_tdesc | |
123 | { | |
124 | u32 buf_addr; | |
125 | u32 tdesc1; | |
126 | }; | |
127 | ||
128 | #define TDESC1_EOF 0x80000000 | |
129 | #define TDESC1_BUFFER_INDEX 0x7fff0000 | |
130 | #define TDESC1_BUFFER_ABORT 0x00008000 | |
131 | #define TDESC1_BUFFER_LENGTH 0x00000fff | |
132 | ||
133 | struct ep93xx_tstat | |
134 | { | |
135 | u32 tstat0; | |
136 | }; | |
137 | ||
138 | #define TSTAT0_TXFP 0x80000000 | |
139 | #define TSTAT0_TXWE 0x40000000 | |
140 | #define TSTAT0_FA 0x20000000 | |
141 | #define TSTAT0_LCRS 0x10000000 | |
142 | #define TSTAT0_OW 0x04000000 | |
143 | #define TSTAT0_TXU 0x02000000 | |
144 | #define TSTAT0_ECOLL 0x01000000 | |
145 | #define TSTAT0_NCOLL 0x001f0000 | |
146 | #define TSTAT0_BUFFER_INDEX 0x00007fff | |
147 | ||
148 | struct ep93xx_descs | |
149 | { | |
150 | struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES]; | |
151 | struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES]; | |
152 | struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES]; | |
153 | struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES]; | |
154 | }; | |
155 | ||
156 | struct ep93xx_priv | |
157 | { | |
158 | struct resource *res; | |
5e075cb5 | 159 | void __iomem *base_addr; |
1d22e05d LB |
160 | int irq; |
161 | ||
162 | struct ep93xx_descs *descs; | |
163 | dma_addr_t descs_dma_addr; | |
164 | ||
165 | void *rx_buf[RX_QUEUE_ENTRIES]; | |
166 | void *tx_buf[TX_QUEUE_ENTRIES]; | |
167 | ||
168 | spinlock_t rx_lock; | |
169 | unsigned int rx_pointer; | |
170 | unsigned int tx_clean_pointer; | |
171 | unsigned int tx_pointer; | |
172 | spinlock_t tx_pending_lock; | |
173 | unsigned int tx_pending; | |
174 | ||
bea3348e SH |
175 | struct net_device *dev; |
176 | struct napi_struct napi; | |
177 | ||
1d22e05d LB |
178 | struct mii_if_info mii; |
179 | u8 mdc_divisor; | |
180 | }; | |
181 | ||
182 | #define rdb(ep, off) __raw_readb((ep)->base_addr + (off)) | |
183 | #define rdw(ep, off) __raw_readw((ep)->base_addr + (off)) | |
184 | #define rdl(ep, off) __raw_readl((ep)->base_addr + (off)) | |
185 | #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off)) | |
186 | #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off)) | |
187 | #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off)) | |
188 | ||
df2f7ec8 HS |
189 | static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg) |
190 | { | |
191 | struct ep93xx_priv *ep = netdev_priv(dev); | |
192 | int data; | |
193 | int i; | |
194 | ||
195 | wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg); | |
196 | ||
197 | for (i = 0; i < 10; i++) { | |
198 | if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0) | |
199 | break; | |
200 | msleep(1); | |
201 | } | |
202 | ||
203 | if (i == 10) { | |
204 | pr_info("mdio read timed out\n"); | |
205 | data = 0xffff; | |
206 | } else { | |
207 | data = rdl(ep, REG_MIIDATA); | |
208 | } | |
209 | ||
210 | return data; | |
211 | } | |
212 | ||
213 | static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data) | |
214 | { | |
215 | struct ep93xx_priv *ep = netdev_priv(dev); | |
216 | int i; | |
217 | ||
218 | wrl(ep, REG_MIIDATA, data); | |
219 | wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg); | |
220 | ||
221 | for (i = 0; i < 10; i++) { | |
222 | if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0) | |
223 | break; | |
224 | msleep(1); | |
225 | } | |
226 | ||
227 | if (i == 10) | |
228 | pr_info("mdio write timed out\n"); | |
229 | } | |
1d22e05d | 230 | |
bea3348e | 231 | static int ep93xx_rx(struct net_device *dev, int processed, int budget) |
1d22e05d LB |
232 | { |
233 | struct ep93xx_priv *ep = netdev_priv(dev); | |
1d22e05d | 234 | |
bea3348e | 235 | while (processed < budget) { |
1d22e05d LB |
236 | int entry; |
237 | struct ep93xx_rstat *rstat; | |
238 | u32 rstat0; | |
239 | u32 rstat1; | |
240 | int length; | |
241 | struct sk_buff *skb; | |
242 | ||
243 | entry = ep->rx_pointer; | |
244 | rstat = ep->descs->rstat + entry; | |
2d38caba LB |
245 | |
246 | rstat0 = rstat->rstat0; | |
247 | rstat1 = rstat->rstat1; | |
bea3348e | 248 | if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP)) |
1d22e05d | 249 | break; |
1d22e05d | 250 | |
1d22e05d LB |
251 | rstat->rstat0 = 0; |
252 | rstat->rstat1 = 0; | |
253 | ||
1d22e05d | 254 | if (!(rstat0 & RSTAT0_EOF)) |
df2f7ec8 | 255 | pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1); |
1d22e05d | 256 | if (!(rstat0 & RSTAT0_EOB)) |
df2f7ec8 | 257 | pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1); |
1d22e05d | 258 | if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry) |
df2f7ec8 | 259 | pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1); |
1d22e05d LB |
260 | |
261 | if (!(rstat0 & RSTAT0_RWE)) { | |
5dbfbc40 | 262 | dev->stats.rx_errors++; |
1d22e05d | 263 | if (rstat0 & RSTAT0_OE) |
5dbfbc40 | 264 | dev->stats.rx_fifo_errors++; |
1d22e05d | 265 | if (rstat0 & RSTAT0_FE) |
5dbfbc40 | 266 | dev->stats.rx_frame_errors++; |
1d22e05d | 267 | if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA)) |
5dbfbc40 | 268 | dev->stats.rx_length_errors++; |
1d22e05d | 269 | if (rstat0 & RSTAT0_CRCE) |
5dbfbc40 | 270 | dev->stats.rx_crc_errors++; |
1d22e05d LB |
271 | goto err; |
272 | } | |
273 | ||
274 | length = rstat1 & RSTAT1_FRAME_LENGTH; | |
275 | if (length > MAX_PKT_SIZE) { | |
df2f7ec8 | 276 | pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1); |
1d22e05d LB |
277 | goto err; |
278 | } | |
279 | ||
280 | /* Strip FCS. */ | |
281 | if (rstat0 & RSTAT0_CRCI) | |
282 | length -= 4; | |
283 | ||
21a4e469 | 284 | skb = netdev_alloc_skb(dev, length + 2); |
1d22e05d | 285 | if (likely(skb != NULL)) { |
f1c089e3 | 286 | struct ep93xx_rdesc *rxd = &ep->descs->rdesc[entry]; |
1d22e05d | 287 | skb_reserve(skb, 2); |
f1c089e3 | 288 | dma_sync_single_for_cpu(dev->dev.parent, rxd->buf_addr, |
1d22e05d | 289 | length, DMA_FROM_DEVICE); |
8c7b7faa | 290 | skb_copy_to_linear_data(skb, ep->rx_buf[entry], length); |
f1c089e3 MW |
291 | dma_sync_single_for_device(dev->dev.parent, |
292 | rxd->buf_addr, length, | |
293 | DMA_FROM_DEVICE); | |
1d22e05d LB |
294 | skb_put(skb, length); |
295 | skb->protocol = eth_type_trans(skb, dev); | |
296 | ||
1d22e05d LB |
297 | netif_receive_skb(skb); |
298 | ||
5dbfbc40 TK |
299 | dev->stats.rx_packets++; |
300 | dev->stats.rx_bytes += length; | |
1d22e05d | 301 | } else { |
5dbfbc40 | 302 | dev->stats.rx_dropped++; |
1d22e05d LB |
303 | } |
304 | ||
305 | err: | |
306 | ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1); | |
307 | processed++; | |
1d22e05d LB |
308 | } |
309 | ||
bea3348e | 310 | return processed; |
1d22e05d LB |
311 | } |
312 | ||
313 | static int ep93xx_have_more_rx(struct ep93xx_priv *ep) | |
314 | { | |
2d38caba LB |
315 | struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer; |
316 | return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP)); | |
1d22e05d LB |
317 | } |
318 | ||
bea3348e | 319 | static int ep93xx_poll(struct napi_struct *napi, int budget) |
1d22e05d | 320 | { |
bea3348e SH |
321 | struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi); |
322 | struct net_device *dev = ep->dev; | |
323 | int rx = 0; | |
1d22e05d LB |
324 | |
325 | poll_some_more: | |
bea3348e SH |
326 | rx = ep93xx_rx(dev, rx, budget); |
327 | if (rx < budget) { | |
328 | int more = 0; | |
329 | ||
330 | spin_lock_irq(&ep->rx_lock); | |
288379f0 | 331 | __napi_complete(napi); |
bea3348e SH |
332 | wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX); |
333 | if (ep93xx_have_more_rx(ep)) { | |
334 | wrl(ep, REG_INTEN, REG_INTEN_TX); | |
335 | wrl(ep, REG_INTSTSP, REG_INTSTS_RX); | |
336 | more = 1; | |
337 | } | |
1d22e05d LB |
338 | spin_unlock_irq(&ep->rx_lock); |
339 | ||
288379f0 | 340 | if (more && napi_reschedule(napi)) |
1d22e05d | 341 | goto poll_some_more; |
1d22e05d | 342 | } |
1d22e05d | 343 | |
1827d2e9 DM |
344 | if (rx) { |
345 | wrw(ep, REG_RXDENQ, rx); | |
346 | wrw(ep, REG_RXSTSENQ, rx); | |
347 | } | |
348 | ||
bea3348e | 349 | return rx; |
1d22e05d LB |
350 | } |
351 | ||
352 | static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev) | |
353 | { | |
354 | struct ep93xx_priv *ep = netdev_priv(dev); | |
f1c089e3 | 355 | struct ep93xx_tdesc *txd; |
1d22e05d LB |
356 | int entry; |
357 | ||
79c356f4 | 358 | if (unlikely(skb->len > MAX_PKT_SIZE)) { |
5dbfbc40 | 359 | dev->stats.tx_dropped++; |
1d22e05d LB |
360 | dev_kfree_skb(skb); |
361 | return NETDEV_TX_OK; | |
362 | } | |
363 | ||
364 | entry = ep->tx_pointer; | |
365 | ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1); | |
366 | ||
f1c089e3 MW |
367 | txd = &ep->descs->tdesc[entry]; |
368 | ||
369 | txd->tdesc1 = TDESC1_EOF | (entry << 16) | (skb->len & 0xfff); | |
370 | dma_sync_single_for_cpu(dev->dev.parent, txd->buf_addr, skb->len, | |
371 | DMA_TO_DEVICE); | |
1d22e05d | 372 | skb_copy_and_csum_dev(skb, ep->tx_buf[entry]); |
f1c089e3 MW |
373 | dma_sync_single_for_device(dev->dev.parent, txd->buf_addr, skb->len, |
374 | DMA_TO_DEVICE); | |
1d22e05d LB |
375 | dev_kfree_skb(skb); |
376 | ||
1d22e05d LB |
377 | spin_lock_irq(&ep->tx_pending_lock); |
378 | ep->tx_pending++; | |
379 | if (ep->tx_pending == TX_QUEUE_ENTRIES) | |
380 | netif_stop_queue(dev); | |
381 | spin_unlock_irq(&ep->tx_pending_lock); | |
382 | ||
383 | wrl(ep, REG_TXDENQ, 1); | |
384 | ||
385 | return NETDEV_TX_OK; | |
386 | } | |
387 | ||
388 | static void ep93xx_tx_complete(struct net_device *dev) | |
389 | { | |
390 | struct ep93xx_priv *ep = netdev_priv(dev); | |
1d22e05d LB |
391 | int wake; |
392 | ||
1d22e05d LB |
393 | wake = 0; |
394 | ||
395 | spin_lock(&ep->tx_pending_lock); | |
396 | while (1) { | |
397 | int entry; | |
398 | struct ep93xx_tstat *tstat; | |
399 | u32 tstat0; | |
400 | ||
401 | entry = ep->tx_clean_pointer; | |
402 | tstat = ep->descs->tstat + entry; | |
1d22e05d LB |
403 | |
404 | tstat0 = tstat->tstat0; | |
2d38caba LB |
405 | if (!(tstat0 & TSTAT0_TXFP)) |
406 | break; | |
407 | ||
1d22e05d LB |
408 | tstat->tstat0 = 0; |
409 | ||
1d22e05d | 410 | if (tstat0 & TSTAT0_FA) |
df2f7ec8 | 411 | pr_crit("frame aborted %.8x\n", tstat0); |
1d22e05d | 412 | if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry) |
df2f7ec8 | 413 | pr_crit("entry mismatch %.8x\n", tstat0); |
1d22e05d LB |
414 | |
415 | if (tstat0 & TSTAT0_TXWE) { | |
416 | int length = ep->descs->tdesc[entry].tdesc1 & 0xfff; | |
417 | ||
5dbfbc40 TK |
418 | dev->stats.tx_packets++; |
419 | dev->stats.tx_bytes += length; | |
1d22e05d | 420 | } else { |
5dbfbc40 | 421 | dev->stats.tx_errors++; |
1d22e05d LB |
422 | } |
423 | ||
424 | if (tstat0 & TSTAT0_OW) | |
5dbfbc40 | 425 | dev->stats.tx_window_errors++; |
1d22e05d | 426 | if (tstat0 & TSTAT0_TXU) |
5dbfbc40 TK |
427 | dev->stats.tx_fifo_errors++; |
428 | dev->stats.collisions += (tstat0 >> 16) & 0x1f; | |
1d22e05d LB |
429 | |
430 | ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1); | |
431 | if (ep->tx_pending == TX_QUEUE_ENTRIES) | |
432 | wake = 1; | |
433 | ep->tx_pending--; | |
434 | } | |
435 | spin_unlock(&ep->tx_pending_lock); | |
436 | ||
437 | if (wake) | |
438 | netif_wake_queue(dev); | |
439 | } | |
440 | ||
7d12e780 | 441 | static irqreturn_t ep93xx_irq(int irq, void *dev_id) |
1d22e05d LB |
442 | { |
443 | struct net_device *dev = dev_id; | |
444 | struct ep93xx_priv *ep = netdev_priv(dev); | |
445 | u32 status; | |
446 | ||
447 | status = rdl(ep, REG_INTSTSC); | |
448 | if (status == 0) | |
449 | return IRQ_NONE; | |
450 | ||
451 | if (status & REG_INTSTS_RX) { | |
452 | spin_lock(&ep->rx_lock); | |
288379f0 | 453 | if (likely(napi_schedule_prep(&ep->napi))) { |
1d22e05d | 454 | wrl(ep, REG_INTEN, REG_INTEN_TX); |
288379f0 | 455 | __napi_schedule(&ep->napi); |
1d22e05d LB |
456 | } |
457 | spin_unlock(&ep->rx_lock); | |
458 | } | |
459 | ||
460 | if (status & REG_INTSTS_TX) | |
461 | ep93xx_tx_complete(dev); | |
462 | ||
463 | return IRQ_HANDLED; | |
464 | } | |
465 | ||
466 | static void ep93xx_free_buffers(struct ep93xx_priv *ep) | |
467 | { | |
fc9b4910 | 468 | struct device *dev = ep->dev->dev.parent; |
1d22e05d LB |
469 | int i; |
470 | ||
3247a1fc | 471 | for (i = 0; i < RX_QUEUE_ENTRIES; i++) { |
1d22e05d LB |
472 | dma_addr_t d; |
473 | ||
474 | d = ep->descs->rdesc[i].buf_addr; | |
475 | if (d) | |
3247a1fc | 476 | dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_FROM_DEVICE); |
1d22e05d | 477 | |
7af348be | 478 | kfree(ep->rx_buf[i]); |
1d22e05d LB |
479 | } |
480 | ||
3247a1fc | 481 | for (i = 0; i < TX_QUEUE_ENTRIES; i++) { |
1d22e05d LB |
482 | dma_addr_t d; |
483 | ||
484 | d = ep->descs->tdesc[i].buf_addr; | |
485 | if (d) | |
3247a1fc | 486 | dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_TO_DEVICE); |
1d22e05d | 487 | |
7af348be | 488 | kfree(ep->tx_buf[i]); |
1d22e05d LB |
489 | } |
490 | ||
fc9b4910 | 491 | dma_free_coherent(dev, sizeof(struct ep93xx_descs), ep->descs, |
1d22e05d LB |
492 | ep->descs_dma_addr); |
493 | } | |
494 | ||
1d22e05d LB |
495 | static int ep93xx_alloc_buffers(struct ep93xx_priv *ep) |
496 | { | |
fc9b4910 | 497 | struct device *dev = ep->dev->dev.parent; |
1d22e05d LB |
498 | int i; |
499 | ||
fc9b4910 | 500 | ep->descs = dma_alloc_coherent(dev, sizeof(struct ep93xx_descs), |
1f758a43 | 501 | &ep->descs_dma_addr, GFP_KERNEL); |
1d22e05d LB |
502 | if (ep->descs == NULL) |
503 | return 1; | |
504 | ||
3247a1fc MW |
505 | for (i = 0; i < RX_QUEUE_ENTRIES; i++) { |
506 | void *buf; | |
1d22e05d LB |
507 | dma_addr_t d; |
508 | ||
3247a1fc MW |
509 | buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL); |
510 | if (buf == NULL) | |
1d22e05d LB |
511 | goto err; |
512 | ||
3247a1fc | 513 | d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_FROM_DEVICE); |
fc9b4910 | 514 | if (dma_mapping_error(dev, d)) { |
3247a1fc | 515 | kfree(buf); |
1d22e05d LB |
516 | goto err; |
517 | } | |
518 | ||
3247a1fc | 519 | ep->rx_buf[i] = buf; |
1d22e05d LB |
520 | ep->descs->rdesc[i].buf_addr = d; |
521 | ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE; | |
1d22e05d LB |
522 | } |
523 | ||
3247a1fc MW |
524 | for (i = 0; i < TX_QUEUE_ENTRIES; i++) { |
525 | void *buf; | |
1d22e05d LB |
526 | dma_addr_t d; |
527 | ||
3247a1fc MW |
528 | buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL); |
529 | if (buf == NULL) | |
1d22e05d LB |
530 | goto err; |
531 | ||
3247a1fc | 532 | d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_TO_DEVICE); |
fc9b4910 | 533 | if (dma_mapping_error(dev, d)) { |
3247a1fc | 534 | kfree(buf); |
1d22e05d LB |
535 | goto err; |
536 | } | |
537 | ||
3247a1fc | 538 | ep->tx_buf[i] = buf; |
1d22e05d | 539 | ep->descs->tdesc[i].buf_addr = d; |
1d22e05d LB |
540 | } |
541 | ||
542 | return 0; | |
543 | ||
544 | err: | |
545 | ep93xx_free_buffers(ep); | |
546 | return 1; | |
547 | } | |
548 | ||
549 | static int ep93xx_start_hw(struct net_device *dev) | |
550 | { | |
551 | struct ep93xx_priv *ep = netdev_priv(dev); | |
552 | unsigned long addr; | |
553 | int i; | |
554 | ||
555 | wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET); | |
556 | for (i = 0; i < 10; i++) { | |
557 | if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0) | |
558 | break; | |
559 | msleep(1); | |
560 | } | |
561 | ||
562 | if (i == 10) { | |
df2f7ec8 | 563 | pr_crit("hw failed to reset\n"); |
1d22e05d LB |
564 | return 1; |
565 | } | |
566 | ||
567 | wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9)); | |
568 | ||
569 | /* Does the PHY support preamble suppress? */ | |
570 | if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0) | |
571 | wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8)); | |
572 | ||
573 | /* Receive descriptor ring. */ | |
574 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc); | |
575 | wrl(ep, REG_RXDQBADD, addr); | |
576 | wrl(ep, REG_RXDCURADD, addr); | |
577 | wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc)); | |
578 | ||
579 | /* Receive status ring. */ | |
580 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat); | |
581 | wrl(ep, REG_RXSTSQBADD, addr); | |
582 | wrl(ep, REG_RXSTSQCURADD, addr); | |
583 | wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat)); | |
584 | ||
585 | /* Transmit descriptor ring. */ | |
586 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc); | |
587 | wrl(ep, REG_TXDQBADD, addr); | |
588 | wrl(ep, REG_TXDQCURADD, addr); | |
589 | wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc)); | |
590 | ||
591 | /* Transmit status ring. */ | |
592 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat); | |
593 | wrl(ep, REG_TXSTSQBADD, addr); | |
594 | wrl(ep, REG_TXSTSQCURADD, addr); | |
595 | wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat)); | |
596 | ||
597 | wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX); | |
598 | wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX); | |
599 | wrl(ep, REG_GIINTMSK, 0); | |
600 | ||
601 | for (i = 0; i < 10; i++) { | |
602 | if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0) | |
603 | break; | |
604 | msleep(1); | |
605 | } | |
606 | ||
607 | if (i == 10) { | |
df2f7ec8 | 608 | pr_crit("hw failed to start\n"); |
1d22e05d LB |
609 | return 1; |
610 | } | |
611 | ||
612 | wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES); | |
613 | wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES); | |
614 | ||
615 | wrb(ep, REG_INDAD0, dev->dev_addr[0]); | |
616 | wrb(ep, REG_INDAD1, dev->dev_addr[1]); | |
617 | wrb(ep, REG_INDAD2, dev->dev_addr[2]); | |
618 | wrb(ep, REG_INDAD3, dev->dev_addr[3]); | |
619 | wrb(ep, REG_INDAD4, dev->dev_addr[4]); | |
620 | wrb(ep, REG_INDAD5, dev->dev_addr[5]); | |
621 | wrl(ep, REG_AFP, 0); | |
622 | ||
623 | wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE); | |
624 | ||
625 | wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT); | |
626 | wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE); | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | static void ep93xx_stop_hw(struct net_device *dev) | |
632 | { | |
633 | struct ep93xx_priv *ep = netdev_priv(dev); | |
634 | int i; | |
635 | ||
636 | wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET); | |
637 | for (i = 0; i < 10; i++) { | |
638 | if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0) | |
639 | break; | |
640 | msleep(1); | |
641 | } | |
642 | ||
643 | if (i == 10) | |
df2f7ec8 | 644 | pr_crit("hw failed to reset\n"); |
1d22e05d LB |
645 | } |
646 | ||
647 | static int ep93xx_open(struct net_device *dev) | |
648 | { | |
649 | struct ep93xx_priv *ep = netdev_priv(dev); | |
650 | int err; | |
651 | ||
652 | if (ep93xx_alloc_buffers(ep)) | |
653 | return -ENOMEM; | |
654 | ||
bea3348e SH |
655 | napi_enable(&ep->napi); |
656 | ||
1d22e05d | 657 | if (ep93xx_start_hw(dev)) { |
bea3348e | 658 | napi_disable(&ep->napi); |
1d22e05d LB |
659 | ep93xx_free_buffers(ep); |
660 | return -EIO; | |
661 | } | |
662 | ||
663 | spin_lock_init(&ep->rx_lock); | |
664 | ep->rx_pointer = 0; | |
665 | ep->tx_clean_pointer = 0; | |
666 | ep->tx_pointer = 0; | |
667 | spin_lock_init(&ep->tx_pending_lock); | |
668 | ep->tx_pending = 0; | |
669 | ||
670 | err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev); | |
671 | if (err) { | |
bea3348e | 672 | napi_disable(&ep->napi); |
1d22e05d LB |
673 | ep93xx_stop_hw(dev); |
674 | ep93xx_free_buffers(ep); | |
675 | return err; | |
676 | } | |
677 | ||
678 | wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE); | |
679 | ||
680 | netif_start_queue(dev); | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
685 | static int ep93xx_close(struct net_device *dev) | |
686 | { | |
687 | struct ep93xx_priv *ep = netdev_priv(dev); | |
688 | ||
bea3348e | 689 | napi_disable(&ep->napi); |
1d22e05d LB |
690 | netif_stop_queue(dev); |
691 | ||
692 | wrl(ep, REG_GIINTMSK, 0); | |
693 | free_irq(ep->irq, dev); | |
694 | ep93xx_stop_hw(dev); | |
695 | ep93xx_free_buffers(ep); | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
701 | { | |
702 | struct ep93xx_priv *ep = netdev_priv(dev); | |
703 | struct mii_ioctl_data *data = if_mii(ifr); | |
704 | ||
705 | return generic_mii_ioctl(&ep->mii, data, cmd, NULL); | |
706 | } | |
707 | ||
1d22e05d LB |
708 | static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
709 | { | |
7826d43f JP |
710 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
711 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
1d22e05d LB |
712 | } |
713 | ||
714 | static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
715 | { | |
716 | struct ep93xx_priv *ep = netdev_priv(dev); | |
717 | return mii_ethtool_gset(&ep->mii, cmd); | |
718 | } | |
719 | ||
720 | static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
721 | { | |
722 | struct ep93xx_priv *ep = netdev_priv(dev); | |
723 | return mii_ethtool_sset(&ep->mii, cmd); | |
724 | } | |
725 | ||
726 | static int ep93xx_nway_reset(struct net_device *dev) | |
727 | { | |
728 | struct ep93xx_priv *ep = netdev_priv(dev); | |
729 | return mii_nway_restart(&ep->mii); | |
730 | } | |
731 | ||
732 | static u32 ep93xx_get_link(struct net_device *dev) | |
733 | { | |
734 | struct ep93xx_priv *ep = netdev_priv(dev); | |
735 | return mii_link_ok(&ep->mii); | |
736 | } | |
737 | ||
0fc0b732 | 738 | static const struct ethtool_ops ep93xx_ethtool_ops = { |
1d22e05d LB |
739 | .get_drvinfo = ep93xx_get_drvinfo, |
740 | .get_settings = ep93xx_get_settings, | |
741 | .set_settings = ep93xx_set_settings, | |
742 | .nway_reset = ep93xx_nway_reset, | |
743 | .get_link = ep93xx_get_link, | |
744 | }; | |
745 | ||
9aa7b30c AB |
746 | static const struct net_device_ops ep93xx_netdev_ops = { |
747 | .ndo_open = ep93xx_open, | |
748 | .ndo_stop = ep93xx_close, | |
749 | .ndo_start_xmit = ep93xx_xmit, | |
9aa7b30c AB |
750 | .ndo_do_ioctl = ep93xx_ioctl, |
751 | .ndo_validate_addr = eth_validate_addr, | |
752 | .ndo_change_mtu = eth_change_mtu, | |
753 | .ndo_set_mac_address = eth_mac_addr, | |
754 | }; | |
755 | ||
756 | static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data) | |
1d22e05d LB |
757 | { |
758 | struct net_device *dev; | |
1d22e05d LB |
759 | |
760 | dev = alloc_etherdev(sizeof(struct ep93xx_priv)); | |
761 | if (dev == NULL) | |
762 | return NULL; | |
1d22e05d LB |
763 | |
764 | memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN); | |
765 | ||
1d22e05d | 766 | dev->ethtool_ops = &ep93xx_ethtool_ops; |
9aa7b30c | 767 | dev->netdev_ops = &ep93xx_netdev_ops; |
1d22e05d LB |
768 | |
769 | dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM; | |
1d22e05d LB |
770 | |
771 | return dev; | |
772 | } | |
773 | ||
774 | ||
775 | static int ep93xx_eth_remove(struct platform_device *pdev) | |
776 | { | |
777 | struct net_device *dev; | |
778 | struct ep93xx_priv *ep; | |
779 | ||
780 | dev = platform_get_drvdata(pdev); | |
781 | if (dev == NULL) | |
782 | return 0; | |
1d22e05d LB |
783 | |
784 | ep = netdev_priv(dev); | |
785 | ||
786 | /* @@@ Force down. */ | |
787 | unregister_netdev(dev); | |
788 | ep93xx_free_buffers(ep); | |
789 | ||
790 | if (ep->base_addr != NULL) | |
791 | iounmap(ep->base_addr); | |
792 | ||
793 | if (ep->res != NULL) { | |
794 | release_resource(ep->res); | |
795 | kfree(ep->res); | |
796 | } | |
797 | ||
798 | free_netdev(dev); | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
803 | static int ep93xx_eth_probe(struct platform_device *pdev) | |
804 | { | |
805 | struct ep93xx_eth_data *data; | |
806 | struct net_device *dev; | |
807 | struct ep93xx_priv *ep; | |
df2f7ec8 HS |
808 | struct resource *mem; |
809 | int irq; | |
1d22e05d LB |
810 | int err; |
811 | ||
1d22e05d LB |
812 | if (pdev == NULL) |
813 | return -ENODEV; | |
b96f64dd | 814 | data = dev_get_platdata(&pdev->dev); |
1d22e05d | 815 | |
df2f7ec8 HS |
816 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
817 | irq = platform_get_irq(pdev, 0); | |
818 | if (!mem || irq < 0) | |
819 | return -ENXIO; | |
820 | ||
1d22e05d LB |
821 | dev = ep93xx_dev_alloc(data); |
822 | if (dev == NULL) { | |
823 | err = -ENOMEM; | |
824 | goto err_out; | |
825 | } | |
826 | ep = netdev_priv(dev); | |
bea3348e | 827 | ep->dev = dev; |
fc9b4910 | 828 | SET_NETDEV_DEV(dev, &pdev->dev); |
bea3348e | 829 | netif_napi_add(dev, &ep->napi, ep93xx_poll, 64); |
1d22e05d LB |
830 | |
831 | platform_set_drvdata(pdev, dev); | |
832 | ||
df2f7ec8 HS |
833 | ep->res = request_mem_region(mem->start, resource_size(mem), |
834 | dev_name(&pdev->dev)); | |
1d22e05d LB |
835 | if (ep->res == NULL) { |
836 | dev_err(&pdev->dev, "Could not reserve memory region\n"); | |
837 | err = -ENOMEM; | |
838 | goto err_out; | |
839 | } | |
840 | ||
df2f7ec8 | 841 | ep->base_addr = ioremap(mem->start, resource_size(mem)); |
1d22e05d LB |
842 | if (ep->base_addr == NULL) { |
843 | dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); | |
844 | err = -EIO; | |
845 | goto err_out; | |
846 | } | |
df2f7ec8 | 847 | ep->irq = irq; |
1d22e05d LB |
848 | |
849 | ep->mii.phy_id = data->phy_id; | |
850 | ep->mii.phy_id_mask = 0x1f; | |
851 | ep->mii.reg_num_mask = 0x1f; | |
852 | ep->mii.dev = dev; | |
853 | ep->mii.mdio_read = ep93xx_mdio_read; | |
854 | ep->mii.mdio_write = ep93xx_mdio_write; | |
855 | ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */ | |
856 | ||
3c91c7ae | 857 | if (is_zero_ether_addr(dev->dev_addr)) |
f2cedb63 | 858 | eth_hw_addr_random(dev); |
3c91c7ae | 859 | |
1d22e05d LB |
860 | err = register_netdev(dev); |
861 | if (err) { | |
862 | dev_err(&pdev->dev, "Failed to register netdev\n"); | |
863 | goto err_out; | |
864 | } | |
865 | ||
df2f7ec8 HS |
866 | printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n", |
867 | dev->name, ep->irq, dev->dev_addr); | |
1d22e05d LB |
868 | |
869 | return 0; | |
870 | ||
871 | err_out: | |
872 | ep93xx_eth_remove(pdev); | |
873 | return err; | |
874 | } | |
875 | ||
876 | ||
877 | static struct platform_driver ep93xx_eth_driver = { | |
878 | .probe = ep93xx_eth_probe, | |
879 | .remove = ep93xx_eth_remove, | |
880 | .driver = { | |
881 | .name = "ep93xx-eth", | |
882 | }, | |
883 | }; | |
884 | ||
e827c122 | 885 | module_platform_driver(ep93xx_eth_driver); |
1d22e05d | 886 | |
1d22e05d | 887 | MODULE_LICENSE("GPL"); |
72abb461 | 888 | MODULE_ALIAS("platform:ep93xx-eth"); |