projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| bbc02c7e DM |
1 | /* |
| 2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
| 3 | * | |
| b72a32da | 4 | * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. |
| bbc02c7e DM |
5 | * |
| 6 | * This software is available to you under a choice of one of two | |
| 7 | * licenses. You may choose to be licensed under the terms of the GNU | |
| 8 | * General Public License (GPL) Version 2, available from the file | |
| 9 | * COPYING in the main directory of this source tree, or the | |
| 10 | * OpenIB.org BSD license below: | |
| 11 | * | |
| 12 | * Redistribution and use in source and binary forms, with or | |
| 13 | * without modification, are permitted provided that the following | |
| 14 | * conditions are met: | |
| 15 | * | |
| 16 | * - Redistributions of source code must retain the above | |
| 17 | * copyright notice, this list of conditions and the following | |
| 18 | * disclaimer. | |
| 19 | * | |
| 20 | * - Redistributions in binary form must reproduce the above | |
| 21 | * copyright notice, this list of conditions and the following | |
| 22 | * disclaimer in the documentation and/or other materials | |
| 23 | * provided with the distribution. | |
| 24 | * | |
| 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
| 27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
| 29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
| 30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
| 31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
| 32 | * SOFTWARE. | |
| 33 | */ | |
| 34 | ||
| 35 | #ifndef _T4FW_INTERFACE_H_ | |
| 36 | #define _T4FW_INTERFACE_H_ | |
| 37 | ||
| 5be78ee9 | 38 | enum fw_retval { |
| dbedd44e | 39 | FW_SUCCESS = 0, /* completed successfully */ |
| 5be78ee9 VP |
40 | FW_EPERM = 1, /* operation not permitted */ |
| 41 | FW_ENOENT = 2, /* no such file or directory */ | |
| 42 | FW_EIO = 5, /* input/output error; hw bad */ | |
| 43 | FW_ENOEXEC = 8, /* exec format error; inv microcode */ | |
| 44 | FW_EAGAIN = 11, /* try again */ | |
| 45 | FW_ENOMEM = 12, /* out of memory */ | |
| 46 | FW_EFAULT = 14, /* bad address; fw bad */ | |
| 47 | FW_EBUSY = 16, /* resource busy */ | |
| 48 | FW_EEXIST = 17, /* file exists */ | |
| 989594e2 | 49 | FW_ENODEV = 19, /* no such device */ |
| 5be78ee9 VP |
50 | FW_EINVAL = 22, /* invalid argument */ |
| 51 | FW_ENOSPC = 28, /* no space left on device */ | |
| 52 | FW_ENOSYS = 38, /* functionality not implemented */ | |
| 989594e2 | 53 | FW_ENODATA = 61, /* no data available */ |
| 5be78ee9 VP |
54 | FW_EPROTO = 71, /* protocol error */ |
| 55 | FW_EADDRINUSE = 98, /* address already in use */ | |
| 56 | FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ | |
| 57 | FW_ENETDOWN = 100, /* network is down */ | |
| 58 | FW_ENETUNREACH = 101, /* network is unreachable */ | |
| 59 | FW_ENOBUFS = 105, /* no buffer space available */ | |
| 60 | FW_ETIMEDOUT = 110, /* timeout */ | |
| 61 | FW_EINPROGRESS = 115, /* fw internal */ | |
| 62 | FW_SCSI_ABORT_REQUESTED = 128, /* */ | |
| 63 | FW_SCSI_ABORT_TIMEDOUT = 129, /* */ | |
| 64 | FW_SCSI_ABORTED = 130, /* */ | |
| 65 | FW_SCSI_CLOSE_REQUESTED = 131, /* */ | |
| 66 | FW_ERR_LINK_DOWN = 132, /* */ | |
| 67 | FW_RDEV_NOT_READY = 133, /* */ | |
| 68 | FW_ERR_RDEV_LOST = 134, /* */ | |
| 69 | FW_ERR_RDEV_LOGO = 135, /* */ | |
| 70 | FW_FCOE_NO_XCHG = 136, /* */ | |
| 71 | FW_SCSI_RSP_ERR = 137, /* */ | |
| 72 | FW_ERR_RDEV_IMPL_LOGO = 138, /* */ | |
| 73 | FW_SCSI_UNDER_FLOW_ERR = 139, /* */ | |
| 74 | FW_SCSI_OVER_FLOW_ERR = 140, /* */ | |
| 75 | FW_SCSI_DDP_ERR = 141, /* DDP error*/ | |
| 76 | FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ | |
| f2b7e78d VP |
77 | }; |
| 78 | ||
| bbc02c7e DM |
79 | #define FW_T4VF_SGE_BASE_ADDR 0x0000 |
| 80 | #define FW_T4VF_MPS_BASE_ADDR 0x0100 | |
| 81 | #define FW_T4VF_PL_BASE_ADDR 0x0200 | |
| 82 | #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 | |
| 83 | #define FW_T4VF_CIM_BASE_ADDR 0x0300 | |
| 84 | ||
| 85 | enum fw_wr_opcodes { | |
| 86 | FW_FILTER_WR = 0x02, | |
| 87 | FW_ULPTX_WR = 0x04, | |
| 88 | FW_TP_WR = 0x05, | |
| 89 | FW_ETH_TX_PKT_WR = 0x08, | |
| 5be78ee9 | 90 | FW_OFLD_CONNECTION_WR = 0x2f, |
| bbc02c7e DM |
91 | FW_FLOWC_WR = 0x0a, |
| 92 | FW_OFLD_TX_DATA_WR = 0x0b, | |
| 93 | FW_CMD_WR = 0x10, | |
| 94 | FW_ETH_TX_PKT_VM_WR = 0x11, | |
| 95 | FW_RI_RES_WR = 0x0c, | |
| 96 | FW_RI_INIT_WR = 0x0d, | |
| 97 | FW_RI_RDMA_WRITE_WR = 0x14, | |
| 98 | FW_RI_SEND_WR = 0x15, | |
| 99 | FW_RI_RDMA_READ_WR = 0x16, | |
| 100 | FW_RI_RECV_WR = 0x17, | |
| 101 | FW_RI_BIND_MW_WR = 0x18, | |
| 102 | FW_RI_FR_NSMR_WR = 0x19, | |
| 49b53a93 | 103 | FW_RI_FR_NSMR_TPTE_WR = 0x20, |
| bbc02c7e | 104 | FW_RI_INV_LSTAG_WR = 0x1a, |
| b96c5cbb | 105 | FW_ISCSI_TX_DATA_WR = 0x45, |
| d6657781 | 106 | FW_CRYPTO_LOOKASIDE_WR = 0X6d, |
| 7ef65a42 | 107 | FW_LASTC2E_WR = 0x70 |
| bbc02c7e DM |
108 | }; |
| 109 | ||
| 110 | struct fw_wr_hdr { | |
| 111 | __be32 hi; | |
| 112 | __be32 lo; | |
| 113 | }; | |
| 114 | ||
| e2ac9628 HS |
115 | /* work request opcode (hi) */ |
| 116 | #define FW_WR_OP_S 24 | |
| 117 | #define FW_WR_OP_M 0xff | |
| 118 | #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) | |
| 119 | #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) | |
| 120 | ||
| 121 | /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ | |
| 122 | #define FW_WR_ATOMIC_S 23 | |
| 123 | #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) | |
| 124 | ||
| 125 | /* flush flag (hi) - firmware flushes flushable work request buffered | |
| 126 | * in the flow context. | |
| 127 | */ | |
| 128 | #define FW_WR_FLUSH_S 22 | |
| 129 | #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) | |
| 130 | ||
| 131 | /* completion flag (hi) - firmware generates a cpl_fw6_ack */ | |
| 132 | #define FW_WR_COMPL_S 21 | |
| 133 | #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) | |
| 134 | #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) | |
| 135 | ||
| 136 | /* work request immediate data length (hi) */ | |
| 137 | #define FW_WR_IMMDLEN_S 0 | |
| 138 | #define FW_WR_IMMDLEN_M 0xff | |
| 139 | #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) | |
| 140 | ||
| 141 | /* egress queue status update to associated ingress queue entry (lo) */ | |
| 142 | #define FW_WR_EQUIQ_S 31 | |
| 143 | #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) | |
| 144 | #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) | |
| 145 | ||
| 146 | /* egress queue status update to egress queue status entry (lo) */ | |
| 147 | #define FW_WR_EQUEQ_S 30 | |
| 148 | #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) | |
| 149 | #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) | |
| 150 | ||
| 151 | /* flow context identifier (lo) */ | |
| 152 | #define FW_WR_FLOWID_S 8 | |
| 153 | #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) | |
| 154 | ||
| 155 | /* length in units of 16-bytes (lo) */ | |
| 156 | #define FW_WR_LEN16_S 0 | |
| 157 | #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) | |
| bbc02c7e | 158 | |
| 13ee15d3 | 159 | #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B |
| 5be78ee9 | 160 | #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 |
| 13ee15d3 | 161 | |
| f2b7e78d VP |
162 | /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ |
| 163 | enum fw_filter_wr_cookie { | |
| 164 | FW_FILTER_WR_SUCCESS, | |
| 165 | FW_FILTER_WR_FLT_ADDED, | |
| 166 | FW_FILTER_WR_FLT_DELETED, | |
| 167 | FW_FILTER_WR_SMT_TBL_FULL, | |
| 168 | FW_FILTER_WR_EINVAL, | |
| 169 | }; | |
| 170 | ||
| 171 | struct fw_filter_wr { | |
| 172 | __be32 op_pkd; | |
| 173 | __be32 len16_pkd; | |
| 174 | __be64 r3; | |
| 175 | __be32 tid_to_iq; | |
| 176 | __be32 del_filter_to_l2tix; | |
| 177 | __be16 ethtype; | |
| 178 | __be16 ethtypem; | |
| 179 | __u8 frag_to_ovlan_vldm; | |
| 180 | __u8 smac_sel; | |
| 181 | __be16 rx_chan_rx_rpl_iq; | |
| 182 | __be32 maci_to_matchtypem; | |
| 183 | __u8 ptcl; | |
| 184 | __u8 ptclm; | |
| 185 | __u8 ttyp; | |
| 186 | __u8 ttypm; | |
| 187 | __be16 ivlan; | |
| 188 | __be16 ivlanm; | |
| 189 | __be16 ovlan; | |
| 190 | __be16 ovlanm; | |
| 191 | __u8 lip[16]; | |
| 192 | __u8 lipm[16]; | |
| 193 | __u8 fip[16]; | |
| 194 | __u8 fipm[16]; | |
| 195 | __be16 lp; | |
| 196 | __be16 lpm; | |
| 197 | __be16 fp; | |
| 198 | __be16 fpm; | |
| 199 | __be16 r7; | |
| 200 | __u8 sma[6]; | |
| 201 | }; | |
| 202 | ||
| 77a80e23 HS |
203 | #define FW_FILTER_WR_TID_S 12 |
| 204 | #define FW_FILTER_WR_TID_M 0xfffff | |
| 205 | #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) | |
| 206 | #define FW_FILTER_WR_TID_G(x) \ | |
| 207 | (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) | |
| 208 | ||
| 209 | #define FW_FILTER_WR_RQTYPE_S 11 | |
| 210 | #define FW_FILTER_WR_RQTYPE_M 0x1 | |
| 211 | #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) | |
| 212 | #define FW_FILTER_WR_RQTYPE_G(x) \ | |
| 213 | (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) | |
| 214 | #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) | |
| 215 | ||
| 216 | #define FW_FILTER_WR_NOREPLY_S 10 | |
| 217 | #define FW_FILTER_WR_NOREPLY_M 0x1 | |
| 218 | #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) | |
| 219 | #define FW_FILTER_WR_NOREPLY_G(x) \ | |
| 220 | (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) | |
| 221 | #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) | |
| 222 | ||
| 223 | #define FW_FILTER_WR_IQ_S 0 | |
| 224 | #define FW_FILTER_WR_IQ_M 0x3ff | |
| 225 | #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) | |
| 226 | #define FW_FILTER_WR_IQ_G(x) \ | |
| 227 | (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) | |
| 228 | ||
| 229 | #define FW_FILTER_WR_DEL_FILTER_S 31 | |
| 230 | #define FW_FILTER_WR_DEL_FILTER_M 0x1 | |
| 231 | #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) | |
| 232 | #define FW_FILTER_WR_DEL_FILTER_G(x) \ | |
| 233 | (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) | |
| 234 | #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) | |
| 235 | ||
| 236 | #define FW_FILTER_WR_RPTTID_S 25 | |
| 237 | #define FW_FILTER_WR_RPTTID_M 0x1 | |
| 238 | #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) | |
| 239 | #define FW_FILTER_WR_RPTTID_G(x) \ | |
| 240 | (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) | |
| 241 | #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) | |
| 242 | ||
| 243 | #define FW_FILTER_WR_DROP_S 24 | |
| 244 | #define FW_FILTER_WR_DROP_M 0x1 | |
| 245 | #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) | |
| 246 | #define FW_FILTER_WR_DROP_G(x) \ | |
| 247 | (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) | |
| 248 | #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) | |
| 249 | ||
| 250 | #define FW_FILTER_WR_DIRSTEER_S 23 | |
| 251 | #define FW_FILTER_WR_DIRSTEER_M 0x1 | |
| 252 | #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) | |
| 253 | #define FW_FILTER_WR_DIRSTEER_G(x) \ | |
| 254 | (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) | |
| 255 | #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) | |
| 256 | ||
| 257 | #define FW_FILTER_WR_MASKHASH_S 22 | |
| 258 | #define FW_FILTER_WR_MASKHASH_M 0x1 | |
| 259 | #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) | |
| 260 | #define FW_FILTER_WR_MASKHASH_G(x) \ | |
| 261 | (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) | |
| 262 | #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) | |
| 263 | ||
| 264 | #define FW_FILTER_WR_DIRSTEERHASH_S 21 | |
| 265 | #define FW_FILTER_WR_DIRSTEERHASH_M 0x1 | |
| 266 | #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) | |
| 267 | #define FW_FILTER_WR_DIRSTEERHASH_G(x) \ | |
| 268 | (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) | |
| 269 | #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) | |
| 270 | ||
| 271 | #define FW_FILTER_WR_LPBK_S 20 | |
| 272 | #define FW_FILTER_WR_LPBK_M 0x1 | |
| 273 | #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) | |
| 274 | #define FW_FILTER_WR_LPBK_G(x) \ | |
| 275 | (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) | |
| 276 | #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) | |
| 277 | ||
| 278 | #define FW_FILTER_WR_DMAC_S 19 | |
| 279 | #define FW_FILTER_WR_DMAC_M 0x1 | |
| 280 | #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) | |
| 281 | #define FW_FILTER_WR_DMAC_G(x) \ | |
| 282 | (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) | |
| 283 | #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) | |
| 284 | ||
| 285 | #define FW_FILTER_WR_SMAC_S 18 | |
| 286 | #define FW_FILTER_WR_SMAC_M 0x1 | |
| 287 | #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) | |
| 288 | #define FW_FILTER_WR_SMAC_G(x) \ | |
| 289 | (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) | |
| 290 | #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) | |
| 291 | ||
| 292 | #define FW_FILTER_WR_INSVLAN_S 17 | |
| 293 | #define FW_FILTER_WR_INSVLAN_M 0x1 | |
| 294 | #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) | |
| 295 | #define FW_FILTER_WR_INSVLAN_G(x) \ | |
| 296 | (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) | |
| 297 | #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) | |
| 298 | ||
| 299 | #define FW_FILTER_WR_RMVLAN_S 16 | |
| 300 | #define FW_FILTER_WR_RMVLAN_M 0x1 | |
| 301 | #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) | |
| 302 | #define FW_FILTER_WR_RMVLAN_G(x) \ | |
| 303 | (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) | |
| 304 | #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) | |
| 305 | ||
| 306 | #define FW_FILTER_WR_HITCNTS_S 15 | |
| 307 | #define FW_FILTER_WR_HITCNTS_M 0x1 | |
| 308 | #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) | |
| 309 | #define FW_FILTER_WR_HITCNTS_G(x) \ | |
| 310 | (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) | |
| 311 | #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) | |
| 312 | ||
| 313 | #define FW_FILTER_WR_TXCHAN_S 13 | |
| 314 | #define FW_FILTER_WR_TXCHAN_M 0x3 | |
| 315 | #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) | |
| 316 | #define FW_FILTER_WR_TXCHAN_G(x) \ | |
| 317 | (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) | |
| 318 | ||
| 319 | #define FW_FILTER_WR_PRIO_S 12 | |
| 320 | #define FW_FILTER_WR_PRIO_M 0x1 | |
| 321 | #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) | |
| 322 | #define FW_FILTER_WR_PRIO_G(x) \ | |
| 323 | (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) | |
| 324 | #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) | |
| 325 | ||
| 326 | #define FW_FILTER_WR_L2TIX_S 0 | |
| 327 | #define FW_FILTER_WR_L2TIX_M 0xfff | |
| 328 | #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) | |
| 329 | #define FW_FILTER_WR_L2TIX_G(x) \ | |
| 330 | (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) | |
| 331 | ||
| 332 | #define FW_FILTER_WR_FRAG_S 7 | |
| 333 | #define FW_FILTER_WR_FRAG_M 0x1 | |
| 334 | #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) | |
| 335 | #define FW_FILTER_WR_FRAG_G(x) \ | |
| 336 | (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) | |
| 337 | #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) | |
| 338 | ||
| 339 | #define FW_FILTER_WR_FRAGM_S 6 | |
| 340 | #define FW_FILTER_WR_FRAGM_M 0x1 | |
| 341 | #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) | |
| 342 | #define FW_FILTER_WR_FRAGM_G(x) \ | |
| 343 | (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) | |
| 344 | #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) | |
| 345 | ||
| 346 | #define FW_FILTER_WR_IVLAN_VLD_S 5 | |
| 347 | #define FW_FILTER_WR_IVLAN_VLD_M 0x1 | |
| 348 | #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) | |
| 349 | #define FW_FILTER_WR_IVLAN_VLD_G(x) \ | |
| 350 | (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) | |
| 351 | #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) | |
| 352 | ||
| 353 | #define FW_FILTER_WR_OVLAN_VLD_S 4 | |
| 354 | #define FW_FILTER_WR_OVLAN_VLD_M 0x1 | |
| 355 | #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) | |
| 356 | #define FW_FILTER_WR_OVLAN_VLD_G(x) \ | |
| 357 | (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) | |
| 358 | #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) | |
| 359 | ||
| 360 | #define FW_FILTER_WR_IVLAN_VLDM_S 3 | |
| 361 | #define FW_FILTER_WR_IVLAN_VLDM_M 0x1 | |
| 362 | #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) | |
| 363 | #define FW_FILTER_WR_IVLAN_VLDM_G(x) \ | |
| 364 | (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) | |
| 365 | #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) | |
| 366 | ||
| 367 | #define FW_FILTER_WR_OVLAN_VLDM_S 2 | |
| 368 | #define FW_FILTER_WR_OVLAN_VLDM_M 0x1 | |
| 369 | #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) | |
| 370 | #define FW_FILTER_WR_OVLAN_VLDM_G(x) \ | |
| 371 | (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) | |
| 372 | #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) | |
| 373 | ||
| 374 | #define FW_FILTER_WR_RX_CHAN_S 15 | |
| 375 | #define FW_FILTER_WR_RX_CHAN_M 0x1 | |
| 376 | #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) | |
| 377 | #define FW_FILTER_WR_RX_CHAN_G(x) \ | |
| 378 | (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) | |
| 379 | #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) | |
| 380 | ||
| 381 | #define FW_FILTER_WR_RX_RPL_IQ_S 0 | |
| 382 | #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff | |
| 383 | #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) | |
| 384 | #define FW_FILTER_WR_RX_RPL_IQ_G(x) \ | |
| 385 | (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) | |
| 386 | ||
| 387 | #define FW_FILTER_WR_MACI_S 23 | |
| 388 | #define FW_FILTER_WR_MACI_M 0x1ff | |
| 389 | #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) | |
| 390 | #define FW_FILTER_WR_MACI_G(x) \ | |
| 391 | (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) | |
| 392 | ||
| 393 | #define FW_FILTER_WR_MACIM_S 14 | |
| 394 | #define FW_FILTER_WR_MACIM_M 0x1ff | |
| 395 | #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) | |
| 396 | #define FW_FILTER_WR_MACIM_G(x) \ | |
| 397 | (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) | |
| 398 | ||
| 399 | #define FW_FILTER_WR_FCOE_S 13 | |
| 400 | #define FW_FILTER_WR_FCOE_M 0x1 | |
| 401 | #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) | |
| 402 | #define FW_FILTER_WR_FCOE_G(x) \ | |
| 403 | (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) | |
| 404 | #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) | |
| 405 | ||
| 406 | #define FW_FILTER_WR_FCOEM_S 12 | |
| 407 | #define FW_FILTER_WR_FCOEM_M 0x1 | |
| 408 | #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) | |
| 409 | #define FW_FILTER_WR_FCOEM_G(x) \ | |
| 410 | (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) | |
| 411 | #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) | |
| 412 | ||
| 413 | #define FW_FILTER_WR_PORT_S 9 | |
| 414 | #define FW_FILTER_WR_PORT_M 0x7 | |
| 415 | #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) | |
| 416 | #define FW_FILTER_WR_PORT_G(x) \ | |
| 417 | (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) | |
| 418 | ||
| 419 | #define FW_FILTER_WR_PORTM_S 6 | |
| 420 | #define FW_FILTER_WR_PORTM_M 0x7 | |
| 421 | #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) | |
| 422 | #define FW_FILTER_WR_PORTM_G(x) \ | |
| 423 | (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) | |
| 424 | ||
| 425 | #define FW_FILTER_WR_MATCHTYPE_S 3 | |
| 426 | #define FW_FILTER_WR_MATCHTYPE_M 0x7 | |
| 427 | #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) | |
| 428 | #define FW_FILTER_WR_MATCHTYPE_G(x) \ | |
| 429 | (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) | |
| 430 | ||
| 431 | #define FW_FILTER_WR_MATCHTYPEM_S 0 | |
| 432 | #define FW_FILTER_WR_MATCHTYPEM_M 0x7 | |
| 433 | #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) | |
| 434 | #define FW_FILTER_WR_MATCHTYPEM_G(x) \ | |
| 435 | (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) | |
| f2b7e78d | 436 | |
| bbc02c7e DM |
437 | struct fw_ulptx_wr { |
| 438 | __be32 op_to_compl; | |
| 439 | __be32 flowid_len16; | |
| 440 | u64 cookie; | |
| 441 | }; | |
| 442 | ||
| 443 | struct fw_tp_wr { | |
| 444 | __be32 op_to_immdlen; | |
| 445 | __be32 flowid_len16; | |
| 446 | u64 cookie; | |
| 447 | }; | |
| 448 | ||
| 449 | struct fw_eth_tx_pkt_wr { | |
| 450 | __be32 op_immdlen; | |
| 451 | __be32 equiq_to_len16; | |
| 452 | __be64 r3; | |
| 453 | }; | |
| 454 | ||
| 5be78ee9 VP |
455 | struct fw_ofld_connection_wr { |
| 456 | __be32 op_compl; | |
| 457 | __be32 len16_pkd; | |
| 458 | __u64 cookie; | |
| 459 | __be64 r2; | |
| 460 | __be64 r3; | |
| 461 | struct fw_ofld_connection_le { | |
| 462 | __be32 version_cpl; | |
| 463 | __be32 filter; | |
| 464 | __be32 r1; | |
| 465 | __be16 lport; | |
| 466 | __be16 pport; | |
| 467 | union fw_ofld_connection_leip { | |
| 468 | struct fw_ofld_connection_le_ipv4 { | |
| 469 | __be32 pip; | |
| 470 | __be32 lip; | |
| 471 | __be64 r0; | |
| 472 | __be64 r1; | |
| 473 | __be64 r2; | |
| 474 | } ipv4; | |
| 475 | struct fw_ofld_connection_le_ipv6 { | |
| 476 | __be64 pip_hi; | |
| 477 | __be64 pip_lo; | |
| 478 | __be64 lip_hi; | |
| 479 | __be64 lip_lo; | |
| 480 | } ipv6; | |
| 481 | } u; | |
| 482 | } le; | |
| 483 | struct fw_ofld_connection_tcb { | |
| 484 | __be32 t_state_to_astid; | |
| 485 | __be16 cplrxdataack_cplpassacceptrpl; | |
| 486 | __be16 rcv_adv; | |
| 487 | __be32 rcv_nxt; | |
| 488 | __be32 tx_max; | |
| 489 | __be64 opt0; | |
| 490 | __be32 opt2; | |
| 491 | __be32 r1; | |
| 492 | __be64 r2; | |
| 493 | __be64 r3; | |
| 494 | } tcb; | |
| 495 | }; | |
| 496 | ||
| 77a80e23 HS |
497 | #define FW_OFLD_CONNECTION_WR_VERSION_S 31 |
| 498 | #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 | |
| 499 | #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ | |
| 500 | ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) | |
| 501 | #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ | |
| 502 | (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ | |
| 503 | FW_OFLD_CONNECTION_WR_VERSION_M) | |
| 504 | #define FW_OFLD_CONNECTION_WR_VERSION_F \ | |
| 505 | FW_OFLD_CONNECTION_WR_VERSION_V(1U) | |
| 506 | ||
| 507 | #define FW_OFLD_CONNECTION_WR_CPL_S 30 | |
| 508 | #define FW_OFLD_CONNECTION_WR_CPL_M 0x1 | |
| 509 | #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) | |
| 510 | #define FW_OFLD_CONNECTION_WR_CPL_G(x) \ | |
| 511 | (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) | |
| 512 | #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) | |
| 513 | ||
| 514 | #define FW_OFLD_CONNECTION_WR_T_STATE_S 28 | |
| 515 | #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf | |
| 516 | #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ | |
| 517 | ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) | |
| 518 | #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ | |
| 519 | (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ | |
| 520 | FW_OFLD_CONNECTION_WR_T_STATE_M) | |
| 521 | ||
| 522 | #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 | |
| 523 | #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf | |
| 524 | #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ | |
| 525 | ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) | |
| 526 | #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ | |
| 527 | (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ | |
| 528 | FW_OFLD_CONNECTION_WR_RCV_SCALE_M) | |
| 529 | ||
| 530 | #define FW_OFLD_CONNECTION_WR_ASTID_S 0 | |
| 531 | #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff | |
| 532 | #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ | |
| 533 | ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) | |
| 534 | #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ | |
| 535 | (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) | |
| 536 | ||
| 537 | #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 | |
| 538 | #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 | |
| 539 | #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ | |
| 540 | ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) | |
| 541 | #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ | |
| 542 | (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ | |
| 543 | FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) | |
| 544 | #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ | |
| 545 | FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) | |
| 546 | ||
| 547 | #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 | |
| 548 | #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 | |
| 549 | #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ | |
| 550 | ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) | |
| 551 | #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ | |
| 552 | (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ | |
| 553 | FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) | |
| 554 | #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ | |
| 555 | FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) | |
| 5be78ee9 | 556 | |
| bbc02c7e DM |
557 | enum fw_flowc_mnem { |
| 558 | FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ | |
| 559 | FW_FLOWC_MNEM_CH, | |
| 560 | FW_FLOWC_MNEM_PORT, | |
| 561 | FW_FLOWC_MNEM_IQID, | |
| 562 | FW_FLOWC_MNEM_SNDNXT, | |
| 563 | FW_FLOWC_MNEM_RCVNXT, | |
| 564 | FW_FLOWC_MNEM_SNDBUF, | |
| 565 | FW_FLOWC_MNEM_MSS, | |
| 64bfead8 | 566 | FW_FLOWC_MNEM_TXDATAPLEN_MAX, |
| b96c5cbb VP |
567 | FW_FLOWC_MNEM_TCPSTATE, |
| 568 | FW_FLOWC_MNEM_EOSTATE, | |
| 569 | FW_FLOWC_MNEM_SCHEDCLASS, | |
| 570 | FW_FLOWC_MNEM_DCBPRIO, | |
| 571 | FW_FLOWC_MNEM_SND_SCALE, | |
| 572 | FW_FLOWC_MNEM_RCV_SCALE, | |
| bbc02c7e DM |
573 | }; |
| 574 | ||
| 575 | struct fw_flowc_mnemval { | |
| 576 | u8 mnemonic; | |
| 577 | u8 r4[3]; | |
| 578 | __be32 val; | |
| 579 | }; | |
| 580 | ||
| 581 | struct fw_flowc_wr { | |
| 582 | __be32 op_to_nparams; | |
| bbc02c7e DM |
583 | __be32 flowid_len16; |
| 584 | struct fw_flowc_mnemval mnemval[0]; | |
| 585 | }; | |
| 586 | ||
| e2ac9628 HS |
587 | #define FW_FLOWC_WR_NPARAMS_S 0 |
| 588 | #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) | |
| 589 | ||
| bbc02c7e DM |
590 | struct fw_ofld_tx_data_wr { |
| 591 | __be32 op_to_immdlen; | |
| 592 | __be32 flowid_len16; | |
| 593 | __be32 plen; | |
| 594 | __be32 tunnel_to_proxy; | |
| bbc02c7e DM |
595 | }; |
| 596 | ||
| e2ac9628 HS |
597 | #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 |
| 598 | #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) | |
| 599 | ||
| 600 | #define FW_OFLD_TX_DATA_WR_SAVE_S 18 | |
| 601 | #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) | |
| 602 | ||
| 603 | #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 | |
| 604 | #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) | |
| 605 | #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) | |
| 606 | ||
| 607 | #define FW_OFLD_TX_DATA_WR_URGENT_S 16 | |
| 608 | #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) | |
| 609 | ||
| 610 | #define FW_OFLD_TX_DATA_WR_MORE_S 15 | |
| 611 | #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) | |
| 612 | ||
| 613 | #define FW_OFLD_TX_DATA_WR_SHOVE_S 14 | |
| 614 | #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) | |
| 615 | #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) | |
| 616 | ||
| 617 | #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 | |
| 618 | #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) | |
| 619 | ||
| 620 | #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 | |
| 621 | #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ | |
| 622 | ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) | |
| 623 | ||
| bbc02c7e DM |
624 | struct fw_cmd_wr { |
| 625 | __be32 op_dma; | |
| bbc02c7e DM |
626 | __be32 len16_pkd; |
| 627 | __be64 cookie_daddr; | |
| 628 | }; | |
| 629 | ||
| e2ac9628 HS |
630 | #define FW_CMD_WR_DMA_S 17 |
| 631 | #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) | |
| 632 | ||
| bbc02c7e DM |
633 | struct fw_eth_tx_pkt_vm_wr { |
| 634 | __be32 op_immdlen; | |
| 635 | __be32 equiq_to_len16; | |
| 636 | __be32 r3[2]; | |
| 637 | u8 ethmacdst[6]; | |
| 638 | u8 ethmacsrc[6]; | |
| 639 | __be16 ethtype; | |
| 640 | __be16 vlantci; | |
| 641 | }; | |
| 642 | ||
| 2422d9a3 | 643 | #define FW_CMD_MAX_TIMEOUT 10000 |
| bbc02c7e | 644 | |
| 636f9d37 VP |
645 | /* |
| 646 | * If a host driver does a HELLO and discovers that there's already a MASTER | |
| 647 | * selected, we may have to wait for that MASTER to finish issuing RESET, | |
| 648 | * configuration and INITIALIZE commands. Also, there's a possibility that | |
| 649 | * our own HELLO may get lost if it happens right as the MASTER is issuign a | |
| 650 | * RESET command, so we need to be willing to make a few retries of our HELLO. | |
| 651 | */ | |
| 652 | #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) | |
| 653 | #define FW_CMD_HELLO_RETRIES 3 | |
| 654 | ||
| 655 | ||
| bbc02c7e DM |
656 | enum fw_cmd_opcodes { |
| 657 | FW_LDST_CMD = 0x01, | |
| 658 | FW_RESET_CMD = 0x03, | |
| 659 | FW_HELLO_CMD = 0x04, | |
| 660 | FW_BYE_CMD = 0x05, | |
| 661 | FW_INITIALIZE_CMD = 0x06, | |
| 662 | FW_CAPS_CONFIG_CMD = 0x07, | |
| 663 | FW_PARAMS_CMD = 0x08, | |
| 664 | FW_PFVF_CMD = 0x09, | |
| 665 | FW_IQ_CMD = 0x10, | |
| 666 | FW_EQ_MNGT_CMD = 0x11, | |
| 667 | FW_EQ_ETH_CMD = 0x12, | |
| 668 | FW_EQ_CTRL_CMD = 0x13, | |
| 669 | FW_EQ_OFLD_CMD = 0x21, | |
| 670 | FW_VI_CMD = 0x14, | |
| 671 | FW_VI_MAC_CMD = 0x15, | |
| 672 | FW_VI_RXMODE_CMD = 0x16, | |
| 673 | FW_VI_ENABLE_CMD = 0x17, | |
| 674 | FW_ACL_MAC_CMD = 0x18, | |
| 675 | FW_ACL_VLAN_CMD = 0x19, | |
| 676 | FW_VI_STATS_CMD = 0x1a, | |
| 677 | FW_PORT_CMD = 0x1b, | |
| 678 | FW_PORT_STATS_CMD = 0x1c, | |
| 679 | FW_PORT_LB_STATS_CMD = 0x1d, | |
| 680 | FW_PORT_TRACE_CMD = 0x1e, | |
| 681 | FW_PORT_TRACE_MMAP_CMD = 0x1f, | |
| 682 | FW_RSS_IND_TBL_CMD = 0x20, | |
| 683 | FW_RSS_GLB_CONFIG_CMD = 0x22, | |
| 684 | FW_RSS_VI_CONFIG_CMD = 0x23, | |
| b72a32da | 685 | FW_SCHED_CMD = 0x24, |
| 49aa284f | 686 | FW_DEVLOG_CMD = 0x25, |
| 01bcca68 | 687 | FW_CLIP_CMD = 0x28, |
| bbc02c7e DM |
688 | FW_LASTC2E_CMD = 0x40, |
| 689 | FW_ERROR_CMD = 0x80, | |
| 690 | FW_DEBUG_CMD = 0x81, | |
| 691 | }; | |
| 692 | ||
| 693 | enum fw_cmd_cap { | |
| 694 | FW_CMD_CAP_PF = 0x01, | |
| 695 | FW_CMD_CAP_DMAQ = 0x02, | |
| 696 | FW_CMD_CAP_PORT = 0x04, | |
| 697 | FW_CMD_CAP_PORTPROMISC = 0x08, | |
| 698 | FW_CMD_CAP_PORTSTATS = 0x10, | |
| 699 | FW_CMD_CAP_VF = 0x80, | |
| 700 | }; | |
| 701 | ||
| 702 | /* | |
| 703 | * Generic command header flit0 | |
| 704 | */ | |
| 705 | struct fw_cmd_hdr { | |
| 706 | __be32 hi; | |
| 707 | __be32 lo; | |
| 708 | }; | |
| 709 | ||
| e2ac9628 HS |
710 | #define FW_CMD_OP_S 24 |
| 711 | #define FW_CMD_OP_M 0xff | |
| 712 | #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) | |
| 713 | #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) | |
| 714 | ||
| 715 | #define FW_CMD_REQUEST_S 23 | |
| 716 | #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) | |
| 717 | #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) | |
| 718 | ||
| 719 | #define FW_CMD_READ_S 22 | |
| 720 | #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) | |
| 721 | #define FW_CMD_READ_F FW_CMD_READ_V(1U) | |
| 722 | ||
| 723 | #define FW_CMD_WRITE_S 21 | |
| 724 | #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) | |
| 725 | #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) | |
| 726 | ||
| 727 | #define FW_CMD_EXEC_S 20 | |
| 728 | #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) | |
| 729 | #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) | |
| 730 | ||
| 731 | #define FW_CMD_RAMASK_S 20 | |
| 732 | #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) | |
| 733 | ||
| 734 | #define FW_CMD_RETVAL_S 8 | |
| 735 | #define FW_CMD_RETVAL_M 0xff | |
| 736 | #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) | |
| 737 | #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) | |
| 738 | ||
| 739 | #define FW_CMD_LEN16_S 0 | |
| 740 | #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) | |
| 741 | ||
| 742 | #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) | |
| bbc02c7e DM |
743 | |
| 744 | enum fw_ldst_addrspc { | |
| 745 | FW_LDST_ADDRSPC_FIRMWARE = 0x0001, | |
| 746 | FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, | |
| 747 | FW_LDST_ADDRSPC_SGE_INGC = 0x0009, | |
| 748 | FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, | |
| 749 | FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, | |
| 750 | FW_LDST_ADDRSPC_TP_PIO = 0x0010, | |
| 751 | FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, | |
| 752 | FW_LDST_ADDRSPC_TP_MIB = 0x0012, | |
| 753 | FW_LDST_ADDRSPC_MDIO = 0x0018, | |
| 754 | FW_LDST_ADDRSPC_MPS = 0x0020, | |
| ce91a923 NKI |
755 | FW_LDST_ADDRSPC_FUNC = 0x0028, |
| 756 | FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, | |
| bbc02c7e DM |
757 | }; |
| 758 | ||
| 759 | enum fw_ldst_mps_fid { | |
| 760 | FW_LDST_MPS_ATRB, | |
| 761 | FW_LDST_MPS_RPLC | |
| 762 | }; | |
| 763 | ||
| 764 | enum fw_ldst_func_access_ctl { | |
| 765 | FW_LDST_FUNC_ACC_CTL_VIID, | |
| 766 | FW_LDST_FUNC_ACC_CTL_FID | |
| 767 | }; | |
| 768 | ||
| 769 | enum fw_ldst_func_mod_index { | |
| 770 | FW_LDST_FUNC_MPS | |
| 771 | }; | |
| 772 | ||
| 773 | struct fw_ldst_cmd { | |
| 774 | __be32 op_to_addrspace; | |
| bbc02c7e DM |
775 | __be32 cycles_to_len16; |
| 776 | union fw_ldst { | |
| 777 | struct fw_ldst_addrval { | |
| 778 | __be32 addr; | |
| 779 | __be32 val; | |
| 780 | } addrval; | |
| 781 | struct fw_ldst_idctxt { | |
| 782 | __be32 physid; | |
| 5d700ecb | 783 | __be32 msg_ctxtflush; |
| bbc02c7e DM |
784 | __be32 ctxt_data7; |
| 785 | __be32 ctxt_data6; | |
| 786 | __be32 ctxt_data5; | |
| 787 | __be32 ctxt_data4; | |
| 788 | __be32 ctxt_data3; | |
| 789 | __be32 ctxt_data2; | |
| 790 | __be32 ctxt_data1; | |
| 791 | __be32 ctxt_data0; | |
| 792 | } idctxt; | |
| 793 | struct fw_ldst_mdio { | |
| 794 | __be16 paddr_mmd; | |
| 795 | __be16 raddr; | |
| 796 | __be16 vctl; | |
| 797 | __be16 rval; | |
| 798 | } mdio; | |
| f2be053c HS |
799 | struct fw_ldst_cim_rq { |
| 800 | u8 req_first64[8]; | |
| 801 | u8 req_second64[8]; | |
| 802 | u8 resp_first64[8]; | |
| 803 | u8 resp_second64[8]; | |
| 804 | __be32 r3[2]; | |
| 805 | } cim_rq; | |
| 3ccc6cf7 HS |
806 | union fw_ldst_mps { |
| 807 | struct fw_ldst_mps_rplc { | |
| 808 | __be16 fid_idx; | |
| 809 | __be16 rplcpf_pkd; | |
| 810 | __be32 rplc255_224; | |
| 811 | __be32 rplc223_192; | |
| 812 | __be32 rplc191_160; | |
| 813 | __be32 rplc159_128; | |
| 814 | __be32 rplc127_96; | |
| 815 | __be32 rplc95_64; | |
| 816 | __be32 rplc63_32; | |
| 817 | __be32 rplc31_0; | |
| 818 | } rplc; | |
| 819 | struct fw_ldst_mps_atrb { | |
| 820 | __be16 fid_mpsid; | |
| 821 | __be16 r2[3]; | |
| 822 | __be32 r3[2]; | |
| 823 | __be32 r4; | |
| 824 | __be32 atrb; | |
| 825 | __be16 vlan[16]; | |
| 826 | } atrb; | |
| bbc02c7e DM |
827 | } mps; |
| 828 | struct fw_ldst_func { | |
| 829 | u8 access_ctl; | |
| 830 | u8 mod_index; | |
| 831 | __be16 ctl_id; | |
| 832 | __be32 offset; | |
| 833 | __be64 data0; | |
| 834 | __be64 data1; | |
| 835 | } func; | |
| ce91a923 NKI |
836 | struct fw_ldst_pcie { |
| 837 | u8 ctrl_to_fn; | |
| 838 | u8 bnum; | |
| 839 | u8 r; | |
| 840 | u8 ext_r; | |
| 841 | u8 select_naccess; | |
| 842 | u8 pcie_fn; | |
| 843 | __be16 nset_pkd; | |
| 844 | __be32 data[12]; | |
| 845 | } pcie; | |
| f2be053c HS |
846 | struct fw_ldst_i2c_deprecated { |
| 847 | u8 pid_pkd; | |
| 848 | u8 base; | |
| 849 | u8 boffset; | |
| 850 | u8 data; | |
| 851 | __be32 r9; | |
| 852 | } i2c_deprecated; | |
| 853 | struct fw_ldst_i2c { | |
| 854 | u8 pid; | |
| 855 | u8 did; | |
| 856 | u8 boffset; | |
| 857 | u8 blen; | |
| 858 | __be32 r9; | |
| 859 | __u8 data[48]; | |
| 860 | } i2c; | |
| 861 | struct fw_ldst_le { | |
| 862 | __be32 index; | |
| 863 | __be32 r9; | |
| 864 | u8 val[33]; | |
| 865 | u8 r11[7]; | |
| 866 | } le; | |
| bbc02c7e DM |
867 | } u; |
| 868 | }; | |
| 869 | ||
| f2be053c HS |
870 | #define FW_LDST_CMD_ADDRSPACE_S 0 |
| 871 | #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) | |
| 872 | ||
| 5167865a HS |
873 | #define FW_LDST_CMD_MSG_S 31 |
| 874 | #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) | |
| 875 | ||
| 5d700ecb HS |
876 | #define FW_LDST_CMD_CTXTFLUSH_S 30 |
| 877 | #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) | |
| 878 | #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) | |
| 879 | ||
| 5167865a HS |
880 | #define FW_LDST_CMD_PADDR_S 8 |
| 881 | #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) | |
| 882 | ||
| 883 | #define FW_LDST_CMD_MMD_S 0 | |
| 884 | #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) | |
| 885 | ||
| 886 | #define FW_LDST_CMD_FID_S 15 | |
| 887 | #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) | |
| 888 | ||
| 3ccc6cf7 HS |
889 | #define FW_LDST_CMD_IDX_S 0 |
| 890 | #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) | |
| 5167865a HS |
891 | |
| 892 | #define FW_LDST_CMD_RPLCPF_S 0 | |
| 893 | #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) | |
| 894 | ||
| 895 | #define FW_LDST_CMD_LC_S 4 | |
| 896 | #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) | |
| 897 | #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) | |
| 898 | ||
| 899 | #define FW_LDST_CMD_FN_S 0 | |
| 900 | #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) | |
| 901 | ||
| 902 | #define FW_LDST_CMD_NACCESS_S 0 | |
| 903 | #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) | |
| bbc02c7e DM |
904 | |
| 905 | struct fw_reset_cmd { | |
| 906 | __be32 op_to_write; | |
| 907 | __be32 retval_len16; | |
| 908 | __be32 val; | |
| 26f7cbc0 | 909 | __be32 halt_pkd; |
| bbc02c7e DM |
910 | }; |
| 911 | ||
| 5167865a HS |
912 | #define FW_RESET_CMD_HALT_S 31 |
| 913 | #define FW_RESET_CMD_HALT_M 0x1 | |
| 914 | #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) | |
| 915 | #define FW_RESET_CMD_HALT_G(x) \ | |
| 916 | (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) | |
| 917 | #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) | |
| 26f7cbc0 | 918 | |
| 636f9d37 VP |
919 | enum fw_hellow_cmd { |
| 920 | fw_hello_cmd_stage_os = 0x0 | |
| 921 | }; | |
| 922 | ||
| bbc02c7e DM |
923 | struct fw_hello_cmd { |
| 924 | __be32 op_to_write; | |
| 925 | __be32 retval_len16; | |
| ce91a923 | 926 | __be32 err_to_clearinit; |
| bbc02c7e DM |
927 | __be32 fwrev; |
| 928 | }; | |
| 929 | ||
| 5167865a HS |
930 | #define FW_HELLO_CMD_ERR_S 31 |
| 931 | #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) | |
| 932 | #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) | |
| 933 | ||
| 934 | #define FW_HELLO_CMD_INIT_S 30 | |
| 935 | #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) | |
| 936 | #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) | |
| 937 | ||
| 938 | #define FW_HELLO_CMD_MASTERDIS_S 29 | |
| 939 | #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) | |
| 940 | ||
| 941 | #define FW_HELLO_CMD_MASTERFORCE_S 28 | |
| 942 | #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) | |
| 943 | ||
| 944 | #define FW_HELLO_CMD_MBMASTER_S 24 | |
| 945 | #define FW_HELLO_CMD_MBMASTER_M 0xfU | |
| 946 | #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) | |
| 947 | #define FW_HELLO_CMD_MBMASTER_G(x) \ | |
| 948 | (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) | |
| 949 | ||
| 950 | #define FW_HELLO_CMD_MBASYNCNOTINT_S 23 | |
| 951 | #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) | |
| 952 | ||
| 953 | #define FW_HELLO_CMD_MBASYNCNOT_S 20 | |
| 954 | #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) | |
| 955 | ||
| 956 | #define FW_HELLO_CMD_STAGE_S 17 | |
| 957 | #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) | |
| 958 | ||
| 959 | #define FW_HELLO_CMD_CLEARINIT_S 16 | |
| 960 | #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) | |
| 961 | #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) | |
| 962 | ||
| bbc02c7e DM |
963 | struct fw_bye_cmd { |
| 964 | __be32 op_to_write; | |
| 965 | __be32 retval_len16; | |
| 966 | __be64 r3; | |
| 967 | }; | |
| 968 | ||
| 969 | struct fw_initialize_cmd { | |
| 970 | __be32 op_to_write; | |
| 971 | __be32 retval_len16; | |
| 972 | __be64 r3; | |
| 973 | }; | |
| 974 | ||
| 975 | enum fw_caps_config_hm { | |
| 976 | FW_CAPS_CONFIG_HM_PCIE = 0x00000001, | |
| 977 | FW_CAPS_CONFIG_HM_PL = 0x00000002, | |
| 978 | FW_CAPS_CONFIG_HM_SGE = 0x00000004, | |
| 979 | FW_CAPS_CONFIG_HM_CIM = 0x00000008, | |
| 980 | FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, | |
| 981 | FW_CAPS_CONFIG_HM_TP = 0x00000020, | |
| 982 | FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, | |
| 983 | FW_CAPS_CONFIG_HM_PMRX = 0x00000080, | |
| 984 | FW_CAPS_CONFIG_HM_PMTX = 0x00000100, | |
| 985 | FW_CAPS_CONFIG_HM_MC = 0x00000200, | |
| 986 | FW_CAPS_CONFIG_HM_LE = 0x00000400, | |
| 987 | FW_CAPS_CONFIG_HM_MPS = 0x00000800, | |
| 988 | FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, | |
| 989 | FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, | |
| 990 | FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, | |
| 991 | FW_CAPS_CONFIG_HM_MI = 0x00008000, | |
| 992 | FW_CAPS_CONFIG_HM_I2CM = 0x00010000, | |
| 993 | FW_CAPS_CONFIG_HM_NCSI = 0x00020000, | |
| 994 | FW_CAPS_CONFIG_HM_SMB = 0x00040000, | |
| 995 | FW_CAPS_CONFIG_HM_MA = 0x00080000, | |
| 996 | FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, | |
| 997 | FW_CAPS_CONFIG_HM_PMU = 0x00200000, | |
| 998 | FW_CAPS_CONFIG_HM_UART = 0x00400000, | |
| 999 | FW_CAPS_CONFIG_HM_SF = 0x00800000, | |
| 1000 | }; | |
| 1001 | ||
| 1002 | enum fw_caps_config_nbm { | |
| 1003 | FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, | |
| 1004 | FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, | |
| 1005 | }; | |
| 1006 | ||
| 1007 | enum fw_caps_config_link { | |
| 1008 | FW_CAPS_CONFIG_LINK_PPP = 0x00000001, | |
| 1009 | FW_CAPS_CONFIG_LINK_QFC = 0x00000002, | |
| 1010 | FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, | |
| 1011 | }; | |
| 1012 | ||
| 1013 | enum fw_caps_config_switch { | |
| 1014 | FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, | |
| 1015 | FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, | |
| 1016 | }; | |
| 1017 | ||
| 1018 | enum fw_caps_config_nic { | |
| 1019 | FW_CAPS_CONFIG_NIC = 0x00000001, | |
| 1020 | FW_CAPS_CONFIG_NIC_VM = 0x00000002, | |
| 1021 | }; | |
| 1022 | ||
| 1023 | enum fw_caps_config_ofld { | |
| 1024 | FW_CAPS_CONFIG_OFLD = 0x00000001, | |
| 1025 | }; | |
| 1026 | ||
| 1027 | enum fw_caps_config_rdma { | |
| 1028 | FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, | |
| 1029 | FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, | |
| 1030 | }; | |
| 1031 | ||
| 1032 | enum fw_caps_config_iscsi { | |
| 1033 | FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, | |
| 1034 | FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, | |
| 1035 | FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, | |
| 1036 | FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, | |
| 1037 | }; | |
| 1038 | ||
| 1039 | enum fw_caps_config_fcoe { | |
| 1040 | FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, | |
| 1041 | FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, | |
| ce91a923 | 1042 | FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, |
| bbc02c7e DM |
1043 | }; |
| 1044 | ||
| 52367a76 VP |
1045 | enum fw_memtype_cf { |
| 1046 | FW_MEMTYPE_CF_EDC0 = 0x0, | |
| 1047 | FW_MEMTYPE_CF_EDC1 = 0x1, | |
| 1048 | FW_MEMTYPE_CF_EXTMEM = 0x2, | |
| 1049 | FW_MEMTYPE_CF_FLASH = 0x4, | |
| 1050 | FW_MEMTYPE_CF_INTERNAL = 0x5, | |
| 7ef65a42 | 1051 | FW_MEMTYPE_CF_EXTMEM1 = 0x6, |
| 52367a76 VP |
1052 | }; |
| 1053 | ||
| bbc02c7e DM |
1054 | struct fw_caps_config_cmd { |
| 1055 | __be32 op_to_write; | |
| ce91a923 | 1056 | __be32 cfvalid_to_len16; |
| bbc02c7e DM |
1057 | __be32 r2; |
| 1058 | __be32 hwmbitmap; | |
| 1059 | __be16 nbmcaps; | |
| 1060 | __be16 linkcaps; | |
| 1061 | __be16 switchcaps; | |
| 1062 | __be16 r3; | |
| 1063 | __be16 niccaps; | |
| 1064 | __be16 ofldcaps; | |
| 1065 | __be16 rdmacaps; | |
| 94cdb8bb | 1066 | __be16 cryptocaps; |
| bbc02c7e DM |
1067 | __be16 iscsicaps; |
| 1068 | __be16 fcoecaps; | |
| 52367a76 VP |
1069 | __be32 cfcsum; |
| 1070 | __be32 finiver; | |
| 1071 | __be32 finicsum; | |
| bbc02c7e DM |
1072 | }; |
| 1073 | ||
| 5167865a HS |
1074 | #define FW_CAPS_CONFIG_CMD_CFVALID_S 27 |
| 1075 | #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) | |
| 1076 | #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) | |
| 1077 | ||
| 1078 | #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 | |
| 1079 | #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ | |
| 1080 | ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) | |
| 1081 | ||
| 1082 | #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 | |
| 1083 | #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ | |
| 1084 | ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) | |
| 52367a76 | 1085 | |
| bbc02c7e DM |
1086 | /* |
| 1087 | * params command mnemonics | |
| 1088 | */ | |
| 1089 | enum fw_params_mnem { | |
| 1090 | FW_PARAMS_MNEM_DEV = 1, /* device params */ | |
| 1091 | FW_PARAMS_MNEM_PFVF = 2, /* function params */ | |
| 1092 | FW_PARAMS_MNEM_REG = 3, /* limited register access */ | |
| 1093 | FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ | |
| 7ef65a42 | 1094 | FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ |
| bbc02c7e DM |
1095 | FW_PARAMS_MNEM_LAST |
| 1096 | }; | |
| 1097 | ||
| 1098 | /* | |
| 1099 | * device parameters | |
| 1100 | */ | |
| 1101 | enum fw_params_param_dev { | |
| 1102 | FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ | |
| 1103 | FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ | |
| 1104 | FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs | |
| 1105 | * allocated by the device's | |
| 1106 | * Lookup Engine | |
| 1107 | */ | |
| 1108 | FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, | |
| 1109 | FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, | |
| 1110 | FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, | |
| 1111 | FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, | |
| 1112 | FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, | |
| 1113 | FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, | |
| 1114 | FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, | |
| 81323b74 CL |
1115 | FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, |
| 1116 | FW_PARAMS_PARAM_DEV_FWREV = 0x0B, | |
| 1117 | FW_PARAMS_PARAM_DEV_TPREV = 0x0C, | |
| 52367a76 | 1118 | FW_PARAMS_PARAM_DEV_CF = 0x0D, |
| 01b69614 | 1119 | FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, |
| 70a5f3bb | 1120 | FW_PARAMS_PARAM_DEV_DIAG = 0x11, |
| 4c2c5763 HS |
1121 | FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ |
| 1122 | FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ | |
| 1ac0f095 | 1123 | FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, |
| 49216c1c | 1124 | FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, |
| 086de575 | 1125 | FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, |
| bbc02c7e DM |
1126 | }; |
| 1127 | ||
| 1128 | /* | |
| 1129 | * physical and virtual function parameters | |
| 1130 | */ | |
| 1131 | enum fw_params_param_pfvf { | |
| 1132 | FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, | |
| 1133 | FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, | |
| 1134 | FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, | |
| 1135 | FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, | |
| 1136 | FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, | |
| 1137 | FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, | |
| 1138 | FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, | |
| 1139 | FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, | |
| 1140 | FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, | |
| 1141 | FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, | |
| 1142 | FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, | |
| 1143 | FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, | |
| 1144 | FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, | |
| 1145 | FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, | |
| 1146 | FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, | |
| 1147 | FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, | |
| 1148 | FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, | |
| 1149 | FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, | |
| 1150 | FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, | |
| 1151 | FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, | |
| 1152 | FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, | |
| a0881cab DM |
1153 | FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, |
| 1154 | FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, | |
| 1155 | FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, | |
| 1156 | FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, | |
| bbc02c7e | 1157 | FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, |
| a0881cab DM |
1158 | FW_PARAMS_PARAM_PFVF_VIID = 0x24, |
| 1159 | FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, | |
| 1ae970e0 DM |
1160 | FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, |
| 1161 | FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, | |
| e46dab4d DM |
1162 | FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, |
| 1163 | FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, | |
| 1164 | FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, | |
| 1165 | FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, | |
| 1166 | FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, | |
| 52367a76 | 1167 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, |
| b407a4a9 VP |
1168 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, |
| 1169 | FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, | |
| 72a56ca9 HJ |
1170 | FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, |
| 1171 | FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x32 | |
| bbc02c7e DM |
1172 | }; |
| 1173 | ||
| 1174 | /* | |
| 1175 | * dma queue parameters | |
| 1176 | */ | |
| 1177 | enum fw_params_param_dmaq { | |
| 1178 | FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, | |
| 1179 | FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, | |
| 1180 | FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, | |
| 1181 | FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, | |
| 1182 | FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, | |
| 989594e2 | 1183 | FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, |
| b8b1ae99 | 1184 | FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, |
| bbc02c7e DM |
1185 | }; |
| 1186 | ||
| 01b69614 HS |
1187 | enum fw_params_param_dev_phyfw { |
| 1188 | FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, | |
| 1189 | FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, | |
| 1190 | }; | |
| 1191 | ||
| 70a5f3bb HS |
1192 | enum fw_params_param_dev_diag { |
| 1193 | FW_PARAM_DEV_DIAG_TMP = 0x00, | |
| 1194 | FW_PARAM_DEV_DIAG_VDD = 0x01, | |
| 1195 | }; | |
| 1196 | ||
| 49216c1c HS |
1197 | enum fw_params_param_dev_fwcache { |
| 1198 | FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, | |
| 1199 | FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, | |
| 1200 | }; | |
| 1201 | ||
| 5167865a HS |
1202 | #define FW_PARAMS_MNEM_S 24 |
| 1203 | #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) | |
| 1204 | ||
| 1205 | #define FW_PARAMS_PARAM_X_S 16 | |
| 1206 | #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) | |
| 1207 | ||
| 1208 | #define FW_PARAMS_PARAM_Y_S 8 | |
| 1209 | #define FW_PARAMS_PARAM_Y_M 0xffU | |
| 1210 | #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) | |
| 1211 | #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ | |
| 1212 | FW_PARAMS_PARAM_Y_M) | |
| 1213 | ||
| 1214 | #define FW_PARAMS_PARAM_Z_S 0 | |
| 1215 | #define FW_PARAMS_PARAM_Z_M 0xffu | |
| 1216 | #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) | |
| 1217 | #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ | |
| 1218 | FW_PARAMS_PARAM_Z_M) | |
| 1219 | ||
| 1220 | #define FW_PARAMS_PARAM_XYZ_S 0 | |
| 1221 | #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) | |
| 1222 | ||
| 1223 | #define FW_PARAMS_PARAM_YZ_S 0 | |
| 1224 | #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) | |
| bbc02c7e DM |
1225 | |
| 1226 | struct fw_params_cmd { | |
| 1227 | __be32 op_to_vfn; | |
| 1228 | __be32 retval_len16; | |
| 1229 | struct fw_params_param { | |
| 1230 | __be32 mnem; | |
| 1231 | __be32 val; | |
| 1232 | } param[7]; | |
| 1233 | }; | |
| 1234 | ||
| 5167865a HS |
1235 | #define FW_PARAMS_CMD_PFN_S 8 |
| 1236 | #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) | |
| 1237 | ||
| 1238 | #define FW_PARAMS_CMD_VFN_S 0 | |
| 1239 | #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) | |
| bbc02c7e DM |
1240 | |
| 1241 | struct fw_pfvf_cmd { | |
| 1242 | __be32 op_to_vfn; | |
| 1243 | __be32 retval_len16; | |
| 1244 | __be32 niqflint_niq; | |
| 81323b74 | 1245 | __be32 type_to_neq; |
| bbc02c7e DM |
1246 | __be32 tc_to_nexactf; |
| 1247 | __be32 r_caps_to_nethctrl; | |
| 1248 | __be16 nricq; | |
| 1249 | __be16 nriqp; | |
| 1250 | __be32 r4; | |
| 1251 | }; | |
| 1252 | ||
| 5167865a HS |
1253 | #define FW_PFVF_CMD_PFN_S 8 |
| 1254 | #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) | |
| 1255 | ||
| 1256 | #define FW_PFVF_CMD_VFN_S 0 | |
| 1257 | #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) | |
| 1258 | ||
| 1259 | #define FW_PFVF_CMD_NIQFLINT_S 20 | |
| 1260 | #define FW_PFVF_CMD_NIQFLINT_M 0xfff | |
| 1261 | #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) | |
| 1262 | #define FW_PFVF_CMD_NIQFLINT_G(x) \ | |
| 1263 | (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) | |
| 1264 | ||
| 1265 | #define FW_PFVF_CMD_NIQ_S 0 | |
| 1266 | #define FW_PFVF_CMD_NIQ_M 0xfffff | |
| 1267 | #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) | |
| 1268 | #define FW_PFVF_CMD_NIQ_G(x) \ | |
| 1269 | (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) | |
| 1270 | ||
| 1271 | #define FW_PFVF_CMD_TYPE_S 31 | |
| 1272 | #define FW_PFVF_CMD_TYPE_M 0x1 | |
| 1273 | #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) | |
| 1274 | #define FW_PFVF_CMD_TYPE_G(x) \ | |
| 1275 | (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) | |
| 1276 | #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) | |
| 1277 | ||
| 1278 | #define FW_PFVF_CMD_CMASK_S 24 | |
| 1279 | #define FW_PFVF_CMD_CMASK_M 0xf | |
| 1280 | #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) | |
| 1281 | #define FW_PFVF_CMD_CMASK_G(x) \ | |
| 1282 | (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) | |
| 1283 | ||
| 1284 | #define FW_PFVF_CMD_PMASK_S 20 | |
| 1285 | #define FW_PFVF_CMD_PMASK_M 0xf | |
| 1286 | #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) | |
| 1287 | #define FW_PFVF_CMD_PMASK_G(x) \ | |
| 1288 | (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) | |
| 1289 | ||
| 1290 | #define FW_PFVF_CMD_NEQ_S 0 | |
| 1291 | #define FW_PFVF_CMD_NEQ_M 0xfffff | |
| 1292 | #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) | |
| 1293 | #define FW_PFVF_CMD_NEQ_G(x) \ | |
| 1294 | (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) | |
| 1295 | ||
| 1296 | #define FW_PFVF_CMD_TC_S 24 | |
| 1297 | #define FW_PFVF_CMD_TC_M 0xff | |
| 1298 | #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) | |
| 1299 | #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) | |
| 1300 | ||
| 1301 | #define FW_PFVF_CMD_NVI_S 16 | |
| 1302 | #define FW_PFVF_CMD_NVI_M 0xff | |
| 1303 | #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) | |
| 1304 | #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) | |
| 1305 | ||
| 1306 | #define FW_PFVF_CMD_NEXACTF_S 0 | |
| 1307 | #define FW_PFVF_CMD_NEXACTF_M 0xffff | |
| 1308 | #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) | |
| 1309 | #define FW_PFVF_CMD_NEXACTF_G(x) \ | |
| 1310 | (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) | |
| 1311 | ||
| 1312 | #define FW_PFVF_CMD_R_CAPS_S 24 | |
| 1313 | #define FW_PFVF_CMD_R_CAPS_M 0xff | |
| 1314 | #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) | |
| 1315 | #define FW_PFVF_CMD_R_CAPS_G(x) \ | |
| 1316 | (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) | |
| 1317 | ||
| 1318 | #define FW_PFVF_CMD_WX_CAPS_S 16 | |
| 1319 | #define FW_PFVF_CMD_WX_CAPS_M 0xff | |
| 1320 | #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) | |
| 1321 | #define FW_PFVF_CMD_WX_CAPS_G(x) \ | |
| 1322 | (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) | |
| 1323 | ||
| 1324 | #define FW_PFVF_CMD_NETHCTRL_S 0 | |
| 1325 | #define FW_PFVF_CMD_NETHCTRL_M 0xffff | |
| 1326 | #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) | |
| 1327 | #define FW_PFVF_CMD_NETHCTRL_G(x) \ | |
| 1328 | (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) | |
| bbc02c7e DM |
1329 | |
| 1330 | enum fw_iq_type { | |
| 1331 | FW_IQ_TYPE_FL_INT_CAP, | |
| 1332 | FW_IQ_TYPE_NO_FL_INT_CAP | |
| 1333 | }; | |
| 1334 | ||
| 1335 | struct fw_iq_cmd { | |
| 1336 | __be32 op_to_vfn; | |
| 1337 | __be32 alloc_to_len16; | |
| 1338 | __be16 physiqid; | |
| 1339 | __be16 iqid; | |
| 1340 | __be16 fl0id; | |
| 1341 | __be16 fl1id; | |
| 1342 | __be32 type_to_iqandstindex; | |
| 1343 | __be16 iqdroprss_to_iqesize; | |
| 1344 | __be16 iqsize; | |
| 1345 | __be64 iqaddr; | |
| 1346 | __be32 iqns_to_fl0congen; | |
| 1347 | __be16 fl0dcaen_to_fl0cidxfthresh; | |
| 1348 | __be16 fl0size; | |
| 1349 | __be64 fl0addr; | |
| 1350 | __be32 fl1cngchmap_to_fl1congen; | |
| 1351 | __be16 fl1dcaen_to_fl1cidxfthresh; | |
| 1352 | __be16 fl1size; | |
| 1353 | __be64 fl1addr; | |
| 1354 | }; | |
| 1355 | ||
| 6e4b51a6 HS |
1356 | #define FW_IQ_CMD_PFN_S 8 |
| 1357 | #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) | |
| 1358 | ||
| 1359 | #define FW_IQ_CMD_VFN_S 0 | |
| 1360 | #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) | |
| 1361 | ||
| 1362 | #define FW_IQ_CMD_ALLOC_S 31 | |
| 1363 | #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) | |
| 1364 | #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) | |
| 1365 | ||
| 1366 | #define FW_IQ_CMD_FREE_S 30 | |
| 1367 | #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) | |
| 1368 | #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) | |
| 1369 | ||
| 1370 | #define FW_IQ_CMD_MODIFY_S 29 | |
| 1371 | #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) | |
| 1372 | #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) | |
| 1373 | ||
| 1374 | #define FW_IQ_CMD_IQSTART_S 28 | |
| 1375 | #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) | |
| 1376 | #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) | |
| 1377 | ||
| 1378 | #define FW_IQ_CMD_IQSTOP_S 27 | |
| 1379 | #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) | |
| 1380 | #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) | |
| 1381 | ||
| 1382 | #define FW_IQ_CMD_TYPE_S 29 | |
| 1383 | #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) | |
| 1384 | ||
| 1385 | #define FW_IQ_CMD_IQASYNCH_S 28 | |
| 1386 | #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) | |
| 1387 | ||
| 1388 | #define FW_IQ_CMD_VIID_S 16 | |
| 1389 | #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) | |
| 1390 | ||
| 1391 | #define FW_IQ_CMD_IQANDST_S 15 | |
| 1392 | #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) | |
| 1393 | ||
| 1394 | #define FW_IQ_CMD_IQANUS_S 14 | |
| 1395 | #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) | |
| 1396 | ||
| 1397 | #define FW_IQ_CMD_IQANUD_S 12 | |
| 1398 | #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) | |
| 1399 | ||
| 1400 | #define FW_IQ_CMD_IQANDSTINDEX_S 0 | |
| 1401 | #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) | |
| 1402 | ||
| 1403 | #define FW_IQ_CMD_IQDROPRSS_S 15 | |
| 1404 | #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) | |
| 1405 | #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) | |
| 1406 | ||
| 1407 | #define FW_IQ_CMD_IQGTSMODE_S 14 | |
| 1408 | #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) | |
| 1409 | #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) | |
| 1410 | ||
| 1411 | #define FW_IQ_CMD_IQPCIECH_S 12 | |
| 1412 | #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) | |
| 1413 | ||
| 1414 | #define FW_IQ_CMD_IQDCAEN_S 11 | |
| 1415 | #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) | |
| 1416 | ||
| 1417 | #define FW_IQ_CMD_IQDCACPU_S 6 | |
| 1418 | #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) | |
| 1419 | ||
| 1420 | #define FW_IQ_CMD_IQINTCNTTHRESH_S 4 | |
| 1421 | #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) | |
| 1422 | ||
| 1423 | #define FW_IQ_CMD_IQO_S 3 | |
| 1424 | #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) | |
| 1425 | #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) | |
| 1426 | ||
| 1427 | #define FW_IQ_CMD_IQCPRIO_S 2 | |
| 1428 | #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) | |
| 1429 | ||
| 1430 | #define FW_IQ_CMD_IQESIZE_S 0 | |
| 1431 | #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) | |
| 1432 | ||
| 1433 | #define FW_IQ_CMD_IQNS_S 31 | |
| 1434 | #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) | |
| 1435 | ||
| 1436 | #define FW_IQ_CMD_IQRO_S 30 | |
| 1437 | #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) | |
| 1438 | ||
| 1439 | #define FW_IQ_CMD_IQFLINTIQHSEN_S 28 | |
| 1440 | #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) | |
| 1441 | ||
| 1442 | #define FW_IQ_CMD_IQFLINTCONGEN_S 27 | |
| 1443 | #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) | |
| 145ef8a5 | 1444 | #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) |
| 6e4b51a6 HS |
1445 | |
| 1446 | #define FW_IQ_CMD_IQFLINTISCSIC_S 26 | |
| 1447 | #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) | |
| 1448 | ||
| 1449 | #define FW_IQ_CMD_FL0CNGCHMAP_S 20 | |
| 1450 | #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) | |
| 1451 | ||
| 1452 | #define FW_IQ_CMD_FL0CACHELOCK_S 15 | |
| 1453 | #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) | |
| 1454 | ||
| 1455 | #define FW_IQ_CMD_FL0DBP_S 14 | |
| 1456 | #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) | |
| 1457 | ||
| 1458 | #define FW_IQ_CMD_FL0DATANS_S 13 | |
| 1459 | #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) | |
| 1460 | ||
| 1461 | #define FW_IQ_CMD_FL0DATARO_S 12 | |
| 1462 | #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) | |
| 1463 | #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) | |
| 1464 | ||
| 1465 | #define FW_IQ_CMD_FL0CONGCIF_S 11 | |
| 1466 | #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) | |
| 145ef8a5 | 1467 | #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) |
| 6e4b51a6 HS |
1468 | |
| 1469 | #define FW_IQ_CMD_FL0ONCHIP_S 10 | |
| 1470 | #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) | |
| 1471 | ||
| 1472 | #define FW_IQ_CMD_FL0STATUSPGNS_S 9 | |
| 1473 | #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) | |
| 1474 | ||
| 1475 | #define FW_IQ_CMD_FL0STATUSPGRO_S 8 | |
| 1476 | #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) | |
| 1477 | ||
| 1478 | #define FW_IQ_CMD_FL0FETCHNS_S 7 | |
| 1479 | #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) | |
| 1480 | ||
| 1481 | #define FW_IQ_CMD_FL0FETCHRO_S 6 | |
| 1482 | #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) | |
| 1483 | #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) | |
| 1484 | ||
| 1485 | #define FW_IQ_CMD_FL0HOSTFCMODE_S 4 | |
| 1486 | #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) | |
| 1487 | ||
| 1488 | #define FW_IQ_CMD_FL0CPRIO_S 3 | |
| 1489 | #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) | |
| 1490 | ||
| 1491 | #define FW_IQ_CMD_FL0PADEN_S 2 | |
| 1492 | #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) | |
| 1493 | #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) | |
| 1494 | ||
| 1495 | #define FW_IQ_CMD_FL0PACKEN_S 1 | |
| 1496 | #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) | |
| 1497 | #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) | |
| 1498 | ||
| 1499 | #define FW_IQ_CMD_FL0CONGEN_S 0 | |
| 1500 | #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) | |
| 1501 | #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) | |
| 1502 | ||
| 1503 | #define FW_IQ_CMD_FL0DCAEN_S 15 | |
| 1504 | #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) | |
| 1505 | ||
| 1506 | #define FW_IQ_CMD_FL0DCACPU_S 10 | |
| 1507 | #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) | |
| 1508 | ||
| 1509 | #define FW_IQ_CMD_FL0FBMIN_S 7 | |
| 1510 | #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) | |
| 1511 | ||
| 1512 | #define FW_IQ_CMD_FL0FBMAX_S 4 | |
| 1513 | #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) | |
| 1514 | ||
| 1515 | #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 | |
| 1516 | #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) | |
| 1517 | #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) | |
| 1518 | ||
| 1519 | #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 | |
| 1520 | #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) | |
| 1521 | ||
| 1522 | #define FW_IQ_CMD_FL1CNGCHMAP_S 20 | |
| 1523 | #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) | |
| 1524 | ||
| 1525 | #define FW_IQ_CMD_FL1CACHELOCK_S 15 | |
| 1526 | #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) | |
| 1527 | ||
| 1528 | #define FW_IQ_CMD_FL1DBP_S 14 | |
| 1529 | #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) | |
| 1530 | ||
| 1531 | #define FW_IQ_CMD_FL1DATANS_S 13 | |
| 1532 | #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) | |
| 1533 | ||
| 1534 | #define FW_IQ_CMD_FL1DATARO_S 12 | |
| 1535 | #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) | |
| 1536 | ||
| 1537 | #define FW_IQ_CMD_FL1CONGCIF_S 11 | |
| 1538 | #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) | |
| 1539 | ||
| 1540 | #define FW_IQ_CMD_FL1ONCHIP_S 10 | |
| 1541 | #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) | |
| 1542 | ||
| 1543 | #define FW_IQ_CMD_FL1STATUSPGNS_S 9 | |
| 1544 | #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) | |
| 1545 | ||
| 1546 | #define FW_IQ_CMD_FL1STATUSPGRO_S 8 | |
| 1547 | #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) | |
| 1548 | ||
| 1549 | #define FW_IQ_CMD_FL1FETCHNS_S 7 | |
| 1550 | #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) | |
| 1551 | ||
| 1552 | #define FW_IQ_CMD_FL1FETCHRO_S 6 | |
| 1553 | #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) | |
| 1554 | ||
| 1555 | #define FW_IQ_CMD_FL1HOSTFCMODE_S 4 | |
| 1556 | #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) | |
| 1557 | ||
| 1558 | #define FW_IQ_CMD_FL1CPRIO_S 3 | |
| 1559 | #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) | |
| 1560 | ||
| 1561 | #define FW_IQ_CMD_FL1PADEN_S 2 | |
| 1562 | #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) | |
| 1563 | #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) | |
| 1564 | ||
| 1565 | #define FW_IQ_CMD_FL1PACKEN_S 1 | |
| 1566 | #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) | |
| 1567 | #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) | |
| 1568 | ||
| 1569 | #define FW_IQ_CMD_FL1CONGEN_S 0 | |
| 1570 | #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) | |
| 1571 | #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) | |
| 1572 | ||
| 1573 | #define FW_IQ_CMD_FL1DCAEN_S 15 | |
| 1574 | #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) | |
| 1575 | ||
| 1576 | #define FW_IQ_CMD_FL1DCACPU_S 10 | |
| 1577 | #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) | |
| 1578 | ||
| 1579 | #define FW_IQ_CMD_FL1FBMIN_S 7 | |
| 1580 | #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) | |
| 1581 | ||
| 1582 | #define FW_IQ_CMD_FL1FBMAX_S 4 | |
| 1583 | #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) | |
| 1584 | ||
| 1585 | #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 | |
| 1586 | #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) | |
| 1587 | #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) | |
| 1588 | ||
| 1589 | #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 | |
| 1590 | #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) | |
| bbc02c7e DM |
1591 | |
| 1592 | struct fw_eq_eth_cmd { | |
| 1593 | __be32 op_to_vfn; | |
| 1594 | __be32 alloc_to_len16; | |
| 1595 | __be32 eqid_pkd; | |
| 1596 | __be32 physeqid_pkd; | |
| 1597 | __be32 fetchszm_to_iqid; | |
| 1598 | __be32 dcaen_to_eqsize; | |
| 1599 | __be64 eqaddr; | |
| 1600 | __be32 viid_pkd; | |
| 1601 | __be32 r8_lo; | |
| 1602 | __be64 r9; | |
| 1603 | }; | |
| 1604 | ||
| 6e4b51a6 HS |
1605 | #define FW_EQ_ETH_CMD_PFN_S 8 |
| 1606 | #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) | |
| 1607 | ||
| 1608 | #define FW_EQ_ETH_CMD_VFN_S 0 | |
| 1609 | #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) | |
| 1610 | ||
| 1611 | #define FW_EQ_ETH_CMD_ALLOC_S 31 | |
| 1612 | #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) | |
| 1613 | #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) | |
| 1614 | ||
| 1615 | #define FW_EQ_ETH_CMD_FREE_S 30 | |
| 1616 | #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) | |
| 1617 | #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) | |
| 1618 | ||
| 1619 | #define FW_EQ_ETH_CMD_MODIFY_S 29 | |
| 1620 | #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) | |
| 1621 | #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) | |
| 1622 | ||
| 1623 | #define FW_EQ_ETH_CMD_EQSTART_S 28 | |
| 1624 | #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) | |
| 1625 | #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) | |
| 1626 | ||
| 1627 | #define FW_EQ_ETH_CMD_EQSTOP_S 27 | |
| 1628 | #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) | |
| 1629 | #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) | |
| 1630 | ||
| 1631 | #define FW_EQ_ETH_CMD_EQID_S 0 | |
| 1632 | #define FW_EQ_ETH_CMD_EQID_M 0xfffff | |
| 1633 | #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) | |
| 1634 | #define FW_EQ_ETH_CMD_EQID_G(x) \ | |
| 1635 | (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) | |
| 1636 | ||
| 1637 | #define FW_EQ_ETH_CMD_PHYSEQID_S 0 | |
| 1638 | #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff | |
| 1639 | #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) | |
| 1640 | #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ | |
| 1641 | (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) | |
| 1642 | ||
| 1643 | #define FW_EQ_ETH_CMD_FETCHSZM_S 26 | |
| 1644 | #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) | |
| 1645 | #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) | |
| 1646 | ||
| 1647 | #define FW_EQ_ETH_CMD_STATUSPGNS_S 25 | |
| 1648 | #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) | |
| 1649 | ||
| 1650 | #define FW_EQ_ETH_CMD_STATUSPGRO_S 24 | |
| 1651 | #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) | |
| 1652 | ||
| 1653 | #define FW_EQ_ETH_CMD_FETCHNS_S 23 | |
| 1654 | #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) | |
| 1655 | ||
| 1656 | #define FW_EQ_ETH_CMD_FETCHRO_S 22 | |
| 1657 | #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) | |
| 1ecc7b7a | 1658 | #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) |
| 6e4b51a6 HS |
1659 | |
| 1660 | #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 | |
| 1661 | #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) | |
| 1662 | ||
| 1663 | #define FW_EQ_ETH_CMD_CPRIO_S 19 | |
| 1664 | #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) | |
| 1665 | ||
| 1666 | #define FW_EQ_ETH_CMD_ONCHIP_S 18 | |
| 1667 | #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) | |
| 1668 | ||
| 1669 | #define FW_EQ_ETH_CMD_PCIECHN_S 16 | |
| 1670 | #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) | |
| 1671 | ||
| 1672 | #define FW_EQ_ETH_CMD_IQID_S 0 | |
| 1673 | #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) | |
| 1674 | ||
| 1675 | #define FW_EQ_ETH_CMD_DCAEN_S 31 | |
| 1676 | #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) | |
| 1677 | ||
| 1678 | #define FW_EQ_ETH_CMD_DCACPU_S 26 | |
| 1679 | #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) | |
| 1680 | ||
| 1681 | #define FW_EQ_ETH_CMD_FBMIN_S 23 | |
| 1682 | #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) | |
| 1683 | ||
| 1684 | #define FW_EQ_ETH_CMD_FBMAX_S 20 | |
| 1685 | #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) | |
| 1686 | ||
| 1687 | #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 | |
| 1688 | #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) | |
| 1689 | ||
| 1690 | #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 | |
| 1691 | #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) | |
| 1692 | ||
| 1693 | #define FW_EQ_ETH_CMD_EQSIZE_S 0 | |
| 1694 | #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) | |
| 1695 | ||
| 1696 | #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 | |
| 1697 | #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) | |
| 1698 | #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) | |
| 1699 | ||
| 1700 | #define FW_EQ_ETH_CMD_VIID_S 16 | |
| 1701 | #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) | |
| bbc02c7e DM |
1702 | |
| 1703 | struct fw_eq_ctrl_cmd { | |
| 1704 | __be32 op_to_vfn; | |
| 1705 | __be32 alloc_to_len16; | |
| 1706 | __be32 cmpliqid_eqid; | |
| 1707 | __be32 physeqid_pkd; | |
| 1708 | __be32 fetchszm_to_iqid; | |
| 1709 | __be32 dcaen_to_eqsize; | |
| 1710 | __be64 eqaddr; | |
| 1711 | }; | |
| 1712 | ||
| 6e4b51a6 HS |
1713 | #define FW_EQ_CTRL_CMD_PFN_S 8 |
| 1714 | #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) | |
| 1715 | ||
| 1716 | #define FW_EQ_CTRL_CMD_VFN_S 0 | |
| 1717 | #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) | |
| 1718 | ||
| 1719 | #define FW_EQ_CTRL_CMD_ALLOC_S 31 | |
| 1720 | #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) | |
| 1721 | #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) | |
| 1722 | ||
| 1723 | #define FW_EQ_CTRL_CMD_FREE_S 30 | |
| 1724 | #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) | |
| 1725 | #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) | |
| 1726 | ||
| 1727 | #define FW_EQ_CTRL_CMD_MODIFY_S 29 | |
| 1728 | #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) | |
| 1729 | #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) | |
| 1730 | ||
| 1731 | #define FW_EQ_CTRL_CMD_EQSTART_S 28 | |
| 1732 | #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) | |
| 1733 | #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) | |
| 1734 | ||
| 1735 | #define FW_EQ_CTRL_CMD_EQSTOP_S 27 | |
| 1736 | #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) | |
| 1737 | #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) | |
| 1738 | ||
| 1739 | #define FW_EQ_CTRL_CMD_CMPLIQID_S 20 | |
| 1740 | #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) | |
| 1741 | ||
| 1742 | #define FW_EQ_CTRL_CMD_EQID_S 0 | |
| 1743 | #define FW_EQ_CTRL_CMD_EQID_M 0xfffff | |
| 1744 | #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) | |
| 1745 | #define FW_EQ_CTRL_CMD_EQID_G(x) \ | |
| 1746 | (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) | |
| 1747 | ||
| 1748 | #define FW_EQ_CTRL_CMD_PHYSEQID_S 0 | |
| 1749 | #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff | |
| 1750 | #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ | |
| 1751 | (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) | |
| 1752 | ||
| 1753 | #define FW_EQ_CTRL_CMD_FETCHSZM_S 26 | |
| 1754 | #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) | |
| 1755 | #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) | |
| 1756 | ||
| 1757 | #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 | |
| 1758 | #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) | |
| 1759 | #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) | |
| 1760 | ||
| 1761 | #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 | |
| 1762 | #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) | |
| 1763 | #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) | |
| 1764 | ||
| 1765 | #define FW_EQ_CTRL_CMD_FETCHNS_S 23 | |
| 1766 | #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) | |
| 1767 | #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) | |
| 1768 | ||
| 1769 | #define FW_EQ_CTRL_CMD_FETCHRO_S 22 | |
| 1770 | #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) | |
| 1771 | #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) | |
| 1772 | ||
| 1773 | #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 | |
| 1774 | #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) | |
| 1775 | ||
| 1776 | #define FW_EQ_CTRL_CMD_CPRIO_S 19 | |
| 1777 | #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) | |
| 1778 | ||
| 1779 | #define FW_EQ_CTRL_CMD_ONCHIP_S 18 | |
| 1780 | #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) | |
| 1781 | ||
| 1782 | #define FW_EQ_CTRL_CMD_PCIECHN_S 16 | |
| 1783 | #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) | |
| 1784 | ||
| 1785 | #define FW_EQ_CTRL_CMD_IQID_S 0 | |
| 1786 | #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) | |
| 1787 | ||
| 1788 | #define FW_EQ_CTRL_CMD_DCAEN_S 31 | |
| 1789 | #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) | |
| 1790 | ||
| 1791 | #define FW_EQ_CTRL_CMD_DCACPU_S 26 | |
| 1792 | #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) | |
| 1793 | ||
| 1794 | #define FW_EQ_CTRL_CMD_FBMIN_S 23 | |
| 1795 | #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) | |
| 1796 | ||
| 1797 | #define FW_EQ_CTRL_CMD_FBMAX_S 20 | |
| 1798 | #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) | |
| 1799 | ||
| 1800 | #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 | |
| 1801 | #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ | |
| 1802 | ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) | |
| 1803 | ||
| 1804 | #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 | |
| 1805 | #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) | |
| 1806 | ||
| 1807 | #define FW_EQ_CTRL_CMD_EQSIZE_S 0 | |
| 1808 | #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) | |
| bbc02c7e DM |
1809 | |
| 1810 | struct fw_eq_ofld_cmd { | |
| 1811 | __be32 op_to_vfn; | |
| 1812 | __be32 alloc_to_len16; | |
| 1813 | __be32 eqid_pkd; | |
| 1814 | __be32 physeqid_pkd; | |
| 1815 | __be32 fetchszm_to_iqid; | |
| 1816 | __be32 dcaen_to_eqsize; | |
| 1817 | __be64 eqaddr; | |
| 1818 | }; | |
| 1819 | ||
| 6e4b51a6 HS |
1820 | #define FW_EQ_OFLD_CMD_PFN_S 8 |
| 1821 | #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) | |
| 1822 | ||
| 1823 | #define FW_EQ_OFLD_CMD_VFN_S 0 | |
| 1824 | #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) | |
| 1825 | ||
| 1826 | #define FW_EQ_OFLD_CMD_ALLOC_S 31 | |
| 1827 | #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) | |
| 1828 | #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) | |
| 1829 | ||
| 1830 | #define FW_EQ_OFLD_CMD_FREE_S 30 | |
| 1831 | #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) | |
| 1832 | #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) | |
| 1833 | ||
| 1834 | #define FW_EQ_OFLD_CMD_MODIFY_S 29 | |
| 1835 | #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) | |
| 1836 | #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) | |
| 1837 | ||
| 1838 | #define FW_EQ_OFLD_CMD_EQSTART_S 28 | |
| 1839 | #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) | |
| 1840 | #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) | |
| 1841 | ||
| 1842 | #define FW_EQ_OFLD_CMD_EQSTOP_S 27 | |
| 1843 | #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) | |
| 1844 | #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) | |
| 1845 | ||
| 1846 | #define FW_EQ_OFLD_CMD_EQID_S 0 | |
| 1847 | #define FW_EQ_OFLD_CMD_EQID_M 0xfffff | |
| 1848 | #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) | |
| 1849 | #define FW_EQ_OFLD_CMD_EQID_G(x) \ | |
| 1850 | (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) | |
| 1851 | ||
| 1852 | #define FW_EQ_OFLD_CMD_PHYSEQID_S 0 | |
| 1853 | #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff | |
| 1854 | #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ | |
| 1855 | (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) | |
| 1856 | ||
| 1857 | #define FW_EQ_OFLD_CMD_FETCHSZM_S 26 | |
| 1858 | #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) | |
| 1859 | ||
| 1860 | #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 | |
| 1861 | #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) | |
| 1862 | ||
| 1863 | #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 | |
| 1864 | #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) | |
| 1865 | ||
| 1866 | #define FW_EQ_OFLD_CMD_FETCHNS_S 23 | |
| 1867 | #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) | |
| 1868 | ||
| 1869 | #define FW_EQ_OFLD_CMD_FETCHRO_S 22 | |
| 1870 | #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) | |
| 1871 | #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) | |
| 1872 | ||
| 1873 | #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 | |
| 1874 | #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) | |
| 1875 | ||
| 1876 | #define FW_EQ_OFLD_CMD_CPRIO_S 19 | |
| 1877 | #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) | |
| 1878 | ||
| 1879 | #define FW_EQ_OFLD_CMD_ONCHIP_S 18 | |
| 1880 | #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) | |
| 1881 | ||
| 1882 | #define FW_EQ_OFLD_CMD_PCIECHN_S 16 | |
| 1883 | #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) | |
| 1884 | ||
| 1885 | #define FW_EQ_OFLD_CMD_IQID_S 0 | |
| 1886 | #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) | |
| 1887 | ||
| 1888 | #define FW_EQ_OFLD_CMD_DCAEN_S 31 | |
| 1889 | #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) | |
| 1890 | ||
| 1891 | #define FW_EQ_OFLD_CMD_DCACPU_S 26 | |
| 1892 | #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) | |
| 1893 | ||
| 1894 | #define FW_EQ_OFLD_CMD_FBMIN_S 23 | |
| 1895 | #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) | |
| 1896 | ||
| 1897 | #define FW_EQ_OFLD_CMD_FBMAX_S 20 | |
| 1898 | #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) | |
| 1899 | ||
| 1900 | #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 | |
| 1901 | #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ | |
| 1902 | ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) | |
| 1903 | ||
| 1904 | #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 | |
| 1905 | #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) | |
| 1906 | ||
| 1907 | #define FW_EQ_OFLD_CMD_EQSIZE_S 0 | |
| 1908 | #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) | |
| bbc02c7e DM |
1909 | |
| 1910 | /* | |
| 1911 | * Macros for VIID parsing: | |
| 1912 | * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number | |
| 1913 | */ | |
| d7990b0c AB |
1914 | |
| 1915 | #define FW_VIID_PFN_S 8 | |
| 1916 | #define FW_VIID_PFN_M 0x7 | |
| 1917 | #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) | |
| 1918 | ||
| 2b5fb1f2 HS |
1919 | #define FW_VIID_VIVLD_S 7 |
| 1920 | #define FW_VIID_VIVLD_M 0x1 | |
| 1921 | #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) | |
| 1922 | ||
| 1923 | #define FW_VIID_VIN_S 0 | |
| 1924 | #define FW_VIID_VIN_M 0x7F | |
| 1925 | #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) | |
| bbc02c7e DM |
1926 | |
| 1927 | struct fw_vi_cmd { | |
| 1928 | __be32 op_to_vfn; | |
| 1929 | __be32 alloc_to_len16; | |
| a0881cab | 1930 | __be16 type_viid; |
| bbc02c7e DM |
1931 | u8 mac[6]; |
| 1932 | u8 portid_pkd; | |
| 1933 | u8 nmac; | |
| 1934 | u8 nmac0[6]; | |
| 1935 | __be16 rsssize_pkd; | |
| 1936 | u8 nmac1[6]; | |
| a0881cab | 1937 | __be16 idsiiq_pkd; |
| bbc02c7e | 1938 | u8 nmac2[6]; |
| a0881cab | 1939 | __be16 idseiq_pkd; |
| bbc02c7e DM |
1940 | u8 nmac3[6]; |
| 1941 | __be64 r9; | |
| 1942 | __be64 r10; | |
| 1943 | }; | |
| 1944 | ||
| 2b5fb1f2 HS |
1945 | #define FW_VI_CMD_PFN_S 8 |
| 1946 | #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) | |
| 1947 | ||
| 1948 | #define FW_VI_CMD_VFN_S 0 | |
| 1949 | #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) | |
| 1950 | ||
| 1951 | #define FW_VI_CMD_ALLOC_S 31 | |
| 1952 | #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) | |
| 1953 | #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) | |
| 1954 | ||
| 1955 | #define FW_VI_CMD_FREE_S 30 | |
| 1956 | #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) | |
| 1957 | #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) | |
| 1958 | ||
| 1959 | #define FW_VI_CMD_VIID_S 0 | |
| 1960 | #define FW_VI_CMD_VIID_M 0xfff | |
| 1961 | #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) | |
| 1962 | #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) | |
| 1963 | ||
| 1964 | #define FW_VI_CMD_PORTID_S 4 | |
| 1965 | #define FW_VI_CMD_PORTID_M 0xf | |
| 1966 | #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) | |
| 1967 | #define FW_VI_CMD_PORTID_G(x) \ | |
| 1968 | (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) | |
| 1969 | ||
| 1970 | #define FW_VI_CMD_RSSSIZE_S 0 | |
| 1971 | #define FW_VI_CMD_RSSSIZE_M 0x7ff | |
| 1972 | #define FW_VI_CMD_RSSSIZE_G(x) \ | |
| 1973 | (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) | |
| bbc02c7e DM |
1974 | |
| 1975 | /* Special VI_MAC command index ids */ | |
| 1976 | #define FW_VI_MAC_ADD_MAC 0x3FF | |
| 1977 | #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE | |
| 1978 | #define FW_VI_MAC_MAC_BASED_FREE 0x3FD | |
| 81323b74 | 1979 | #define FW_CLS_TCAM_NUM_ENTRIES 336 |
| bbc02c7e DM |
1980 | |
| 1981 | enum fw_vi_mac_smac { | |
| 1982 | FW_VI_MAC_MPS_TCAM_ENTRY, | |
| 1983 | FW_VI_MAC_MPS_TCAM_ONLY, | |
| 1984 | FW_VI_MAC_SMT_ONLY, | |
| 1985 | FW_VI_MAC_SMT_AND_MPSTCAM | |
| 1986 | }; | |
| 1987 | ||
| 1988 | enum fw_vi_mac_result { | |
| 1989 | FW_VI_MAC_R_SUCCESS, | |
| 1990 | FW_VI_MAC_R_F_NONEXISTENT_NOMEM, | |
| 1991 | FW_VI_MAC_R_SMAC_FAIL, | |
| 1992 | FW_VI_MAC_R_F_ACL_CHECK | |
| 1993 | }; | |
| 1994 | ||
| 1995 | struct fw_vi_mac_cmd { | |
| 1996 | __be32 op_to_viid; | |
| 1997 | __be32 freemacs_to_len16; | |
| 1998 | union fw_vi_mac { | |
| 1999 | struct fw_vi_mac_exact { | |
| 2000 | __be16 valid_to_idx; | |
| 2001 | u8 macaddr[6]; | |
| 2002 | } exact[7]; | |
| 2003 | struct fw_vi_mac_hash { | |
| 2004 | __be64 hashvec; | |
| 2005 | } hash; | |
| 2006 | } u; | |
| 2007 | }; | |
| 2008 | ||
| 2b5fb1f2 HS |
2009 | #define FW_VI_MAC_CMD_VIID_S 0 |
| 2010 | #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) | |
| 2011 | ||
| 2012 | #define FW_VI_MAC_CMD_FREEMACS_S 31 | |
| 2013 | #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) | |
| 2014 | ||
| 2015 | #define FW_VI_MAC_CMD_HASHVECEN_S 23 | |
| 2016 | #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) | |
| 2017 | #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) | |
| 2018 | ||
| 2019 | #define FW_VI_MAC_CMD_HASHUNIEN_S 22 | |
| 2020 | #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) | |
| 2021 | ||
| 2022 | #define FW_VI_MAC_CMD_VALID_S 15 | |
| 2023 | #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) | |
| 2024 | #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) | |
| 2025 | ||
| 2026 | #define FW_VI_MAC_CMD_PRIO_S 12 | |
| 2027 | #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) | |
| 2028 | ||
| 2029 | #define FW_VI_MAC_CMD_SMAC_RESULT_S 10 | |
| 2030 | #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 | |
| 2031 | #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) | |
| 2032 | #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ | |
| 2033 | (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) | |
| 2034 | ||
| 2035 | #define FW_VI_MAC_CMD_IDX_S 0 | |
| 2036 | #define FW_VI_MAC_CMD_IDX_M 0x3ff | |
| 2037 | #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) | |
| 2038 | #define FW_VI_MAC_CMD_IDX_G(x) \ | |
| 2039 | (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) | |
| bbc02c7e DM |
2040 | |
| 2041 | #define FW_RXMODE_MTU_NO_CHG 65535 | |
| 2042 | ||
| 2043 | struct fw_vi_rxmode_cmd { | |
| 2044 | __be32 op_to_viid; | |
| 2045 | __be32 retval_len16; | |
| f8f5aafa | 2046 | __be32 mtu_to_vlanexen; |
| bbc02c7e DM |
2047 | __be32 r4_lo; |
| 2048 | }; | |
| 2049 | ||
| 2b5fb1f2 HS |
2050 | #define FW_VI_RXMODE_CMD_VIID_S 0 |
| 2051 | #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) | |
| 2052 | ||
| 2053 | #define FW_VI_RXMODE_CMD_MTU_S 16 | |
| 2054 | #define FW_VI_RXMODE_CMD_MTU_M 0xffff | |
| 2055 | #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) | |
| 2056 | ||
| 2057 | #define FW_VI_RXMODE_CMD_PROMISCEN_S 14 | |
| 2058 | #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 | |
| 2059 | #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) | |
| 2060 | ||
| 2061 | #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 | |
| 2062 | #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 | |
| 2063 | #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ | |
| 2064 | ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) | |
| 2065 | ||
| 2066 | #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 | |
| 2067 | #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 | |
| 2068 | #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ | |
| 2069 | ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) | |
| 2070 | ||
| 2071 | #define FW_VI_RXMODE_CMD_VLANEXEN_S 8 | |
| 2072 | #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 | |
| 2073 | #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) | |
| bbc02c7e DM |
2074 | |
| 2075 | struct fw_vi_enable_cmd { | |
| 2076 | __be32 op_to_viid; | |
| 2077 | __be32 ien_to_len16; | |
| 2078 | __be16 blinkdur; | |
| 2079 | __be16 r3; | |
| 2080 | __be32 r4; | |
| 2081 | }; | |
| 2082 | ||
| 2b5fb1f2 HS |
2083 | #define FW_VI_ENABLE_CMD_VIID_S 0 |
| 2084 | #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) | |
| 2085 | ||
| 2086 | #define FW_VI_ENABLE_CMD_IEN_S 31 | |
| 2087 | #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) | |
| 2088 | ||
| 2089 | #define FW_VI_ENABLE_CMD_EEN_S 30 | |
| 2090 | #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) | |
| 2091 | ||
| 2092 | #define FW_VI_ENABLE_CMD_LED_S 29 | |
| 2093 | #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) | |
| 2094 | #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) | |
| 2095 | ||
| 2096 | #define FW_VI_ENABLE_CMD_DCB_INFO_S 28 | |
| 2097 | #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) | |
| bbc02c7e DM |
2098 | |
| 2099 | /* VI VF stats offset definitions */ | |
| 2100 | #define VI_VF_NUM_STATS 16 | |
| 2101 | enum fw_vi_stats_vf_index { | |
| 2102 | FW_VI_VF_STAT_TX_BCAST_BYTES_IX, | |
| 2103 | FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, | |
| 2104 | FW_VI_VF_STAT_TX_MCAST_BYTES_IX, | |
| 2105 | FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, | |
| 2106 | FW_VI_VF_STAT_TX_UCAST_BYTES_IX, | |
| 2107 | FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, | |
| 2108 | FW_VI_VF_STAT_TX_DROP_FRAMES_IX, | |
| 2109 | FW_VI_VF_STAT_TX_OFLD_BYTES_IX, | |
| 2110 | FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, | |
| 2111 | FW_VI_VF_STAT_RX_BCAST_BYTES_IX, | |
| 2112 | FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, | |
| 2113 | FW_VI_VF_STAT_RX_MCAST_BYTES_IX, | |
| 2114 | FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, | |
| 2115 | FW_VI_VF_STAT_RX_UCAST_BYTES_IX, | |
| 2116 | FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, | |
| 2117 | FW_VI_VF_STAT_RX_ERR_FRAMES_IX | |
| 2118 | }; | |
| 2119 | ||
| 2120 | /* VI PF stats offset definitions */ | |
| 2121 | #define VI_PF_NUM_STATS 17 | |
| 2122 | enum fw_vi_stats_pf_index { | |
| 2123 | FW_VI_PF_STAT_TX_BCAST_BYTES_IX, | |
| 2124 | FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, | |
| 2125 | FW_VI_PF_STAT_TX_MCAST_BYTES_IX, | |
| 2126 | FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, | |
| 2127 | FW_VI_PF_STAT_TX_UCAST_BYTES_IX, | |
| 2128 | FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, | |
| 2129 | FW_VI_PF_STAT_TX_OFLD_BYTES_IX, | |
| 2130 | FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, | |
| 2131 | FW_VI_PF_STAT_RX_BYTES_IX, | |
| 2132 | FW_VI_PF_STAT_RX_FRAMES_IX, | |
| 2133 | FW_VI_PF_STAT_RX_BCAST_BYTES_IX, | |
| 2134 | FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, | |
| 2135 | FW_VI_PF_STAT_RX_MCAST_BYTES_IX, | |
| 2136 | FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, | |
| 2137 | FW_VI_PF_STAT_RX_UCAST_BYTES_IX, | |
| 2138 | FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, | |
| 2139 | FW_VI_PF_STAT_RX_ERR_FRAMES_IX | |
| 2140 | }; | |
| 2141 | ||
| 2142 | struct fw_vi_stats_cmd { | |
| 2143 | __be32 op_to_viid; | |
| 2144 | __be32 retval_len16; | |
| 2145 | union fw_vi_stats { | |
| 2146 | struct fw_vi_stats_ctl { | |
| 2147 | __be16 nstats_ix; | |
| 2148 | __be16 r6; | |
| 2149 | __be32 r7; | |
| 2150 | __be64 stat0; | |
| 2151 | __be64 stat1; | |
| 2152 | __be64 stat2; | |
| 2153 | __be64 stat3; | |
| 2154 | __be64 stat4; | |
| 2155 | __be64 stat5; | |
| 2156 | } ctl; | |
| 2157 | struct fw_vi_stats_pf { | |
| 2158 | __be64 tx_bcast_bytes; | |
| 2159 | __be64 tx_bcast_frames; | |
| 2160 | __be64 tx_mcast_bytes; | |
| 2161 | __be64 tx_mcast_frames; | |
| 2162 | __be64 tx_ucast_bytes; | |
| 2163 | __be64 tx_ucast_frames; | |
| 2164 | __be64 tx_offload_bytes; | |
| 2165 | __be64 tx_offload_frames; | |
| 2166 | __be64 rx_pf_bytes; | |
| 2167 | __be64 rx_pf_frames; | |
| 2168 | __be64 rx_bcast_bytes; | |
| 2169 | __be64 rx_bcast_frames; | |
| 2170 | __be64 rx_mcast_bytes; | |
| 2171 | __be64 rx_mcast_frames; | |
| 2172 | __be64 rx_ucast_bytes; | |
| 2173 | __be64 rx_ucast_frames; | |
| 2174 | __be64 rx_err_frames; | |
| 2175 | } pf; | |
| 2176 | struct fw_vi_stats_vf { | |
| 2177 | __be64 tx_bcast_bytes; | |
| 2178 | __be64 tx_bcast_frames; | |
| 2179 | __be64 tx_mcast_bytes; | |
| 2180 | __be64 tx_mcast_frames; | |
| 2181 | __be64 tx_ucast_bytes; | |
| 2182 | __be64 tx_ucast_frames; | |
| 2183 | __be64 tx_drop_frames; | |
| 2184 | __be64 tx_offload_bytes; | |
| 2185 | __be64 tx_offload_frames; | |
| 2186 | __be64 rx_bcast_bytes; | |
| 2187 | __be64 rx_bcast_frames; | |
| 2188 | __be64 rx_mcast_bytes; | |
| 2189 | __be64 rx_mcast_frames; | |
| 2190 | __be64 rx_ucast_bytes; | |
| 2191 | __be64 rx_ucast_frames; | |
| 2192 | __be64 rx_err_frames; | |
| 2193 | } vf; | |
| 2194 | } u; | |
| 2195 | }; | |
| 2196 | ||
| 2b5fb1f2 HS |
2197 | #define FW_VI_STATS_CMD_VIID_S 0 |
| 2198 | #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) | |
| 2199 | ||
| 2200 | #define FW_VI_STATS_CMD_NSTATS_S 12 | |
| 2201 | #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) | |
| 2202 | ||
| 2203 | #define FW_VI_STATS_CMD_IX_S 0 | |
| 2204 | #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) | |
| bbc02c7e DM |
2205 | |
| 2206 | struct fw_acl_mac_cmd { | |
| 2207 | __be32 op_to_vfn; | |
| 2208 | __be32 en_to_len16; | |
| 2209 | u8 nmac; | |
| 2210 | u8 r3[7]; | |
| 2211 | __be16 r4; | |
| 2212 | u8 macaddr0[6]; | |
| 2213 | __be16 r5; | |
| 2214 | u8 macaddr1[6]; | |
| 2215 | __be16 r6; | |
| 2216 | u8 macaddr2[6]; | |
| 2217 | __be16 r7; | |
| 2218 | u8 macaddr3[6]; | |
| 2219 | }; | |
| 2220 | ||
| 2b5fb1f2 HS |
2221 | #define FW_ACL_MAC_CMD_PFN_S 8 |
| 2222 | #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) | |
| 2223 | ||
| 2224 | #define FW_ACL_MAC_CMD_VFN_S 0 | |
| 2225 | #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) | |
| 2226 | ||
| 2227 | #define FW_ACL_MAC_CMD_EN_S 31 | |
| 2228 | #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) | |
| bbc02c7e DM |
2229 | |
| 2230 | struct fw_acl_vlan_cmd { | |
| 2231 | __be32 op_to_vfn; | |
| 2232 | __be32 en_to_len16; | |
| 2233 | u8 nvlan; | |
| 2234 | u8 dropnovlan_fm; | |
| 2235 | u8 r3_lo[6]; | |
| 2236 | __be16 vlanid[16]; | |
| 2237 | }; | |
| 2238 | ||
| 2b5fb1f2 HS |
2239 | #define FW_ACL_VLAN_CMD_PFN_S 8 |
| 2240 | #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) | |
| 2241 | ||
| 2242 | #define FW_ACL_VLAN_CMD_VFN_S 0 | |
| 2243 | #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) | |
| 2244 | ||
| 2245 | #define FW_ACL_VLAN_CMD_EN_S 31 | |
| 2246 | #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) | |
| 2247 | ||
| 2248 | #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 | |
| 2249 | #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) | |
| 2250 | ||
| 2251 | #define FW_ACL_VLAN_CMD_FM_S 6 | |
| 2252 | #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) | |
| bbc02c7e DM |
2253 | |
| 2254 | enum fw_port_cap { | |
| 2255 | FW_PORT_CAP_SPEED_100M = 0x0001, | |
| 2256 | FW_PORT_CAP_SPEED_1G = 0x0002, | |
| eb97ad99 | 2257 | FW_PORT_CAP_SPEED_25G = 0x0004, |
| bbc02c7e DM |
2258 | FW_PORT_CAP_SPEED_10G = 0x0008, |
| 2259 | FW_PORT_CAP_SPEED_40G = 0x0010, | |
| 2260 | FW_PORT_CAP_SPEED_100G = 0x0020, | |
| 2261 | FW_PORT_CAP_FC_RX = 0x0040, | |
| 2262 | FW_PORT_CAP_FC_TX = 0x0080, | |
| 2263 | FW_PORT_CAP_ANEG = 0x0100, | |
| eb97ad99 GG |
2264 | FW_PORT_CAP_MDIX = 0x0200, |
| 2265 | FW_PORT_CAP_MDIAUTO = 0x0400, | |
| 3bb4858f GG |
2266 | FW_PORT_CAP_FEC_RS = 0x0800, |
| 2267 | FW_PORT_CAP_FEC_BASER_RS = 0x1000, | |
| 2268 | FW_PORT_CAP_FEC_RESERVED = 0x2000, | |
| eb97ad99 GG |
2269 | FW_PORT_CAP_802_3_PAUSE = 0x4000, |
| 2270 | FW_PORT_CAP_802_3_ASM_DIR = 0x8000, | |
| bbc02c7e DM |
2271 | }; |
| 2272 | ||
| 9b86a8d1 HS |
2273 | #define FW_PORT_CAP_SPEED_S 0 |
| 2274 | #define FW_PORT_CAP_SPEED_M 0x3f | |
| 2275 | #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S) | |
| 2276 | #define FW_PORT_CAP_SPEED_G(x) \ | |
| 2277 | (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M) | |
| 2278 | ||
| bbc02c7e | 2279 | enum fw_port_mdi { |
| 2b5fb1f2 HS |
2280 | FW_PORT_CAP_MDI_UNCHANGED, |
| 2281 | FW_PORT_CAP_MDI_AUTO, | |
| 2282 | FW_PORT_CAP_MDI_F_STRAIGHT, | |
| 2283 | FW_PORT_CAP_MDI_F_CROSSOVER | |
| bbc02c7e DM |
2284 | }; |
| 2285 | ||
| 2b5fb1f2 HS |
2286 | #define FW_PORT_CAP_MDI_S 9 |
| 2287 | #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) | |
| bbc02c7e DM |
2288 | |
| 2289 | enum fw_port_action { | |
| 2290 | FW_PORT_ACTION_L1_CFG = 0x0001, | |
| 2291 | FW_PORT_ACTION_L2_CFG = 0x0002, | |
| 2292 | FW_PORT_ACTION_GET_PORT_INFO = 0x0003, | |
| 2293 | FW_PORT_ACTION_L2_PPP_CFG = 0x0004, | |
| 2294 | FW_PORT_ACTION_L2_DCB_CFG = 0x0005, | |
| 989594e2 AB |
2295 | FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, |
| 2296 | FW_PORT_ACTION_DCB_READ_RECV = 0x0007, | |
| 2297 | FW_PORT_ACTION_DCB_READ_DET = 0x0008, | |
| bbc02c7e DM |
2298 | FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, |
| 2299 | FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, | |
| 2300 | FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, | |
| 2301 | FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, | |
| 2302 | FW_PORT_ACTION_L1_LPBK = 0x0021, | |
| 2303 | FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, | |
| 2304 | FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, | |
| 2305 | FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, | |
| 2306 | FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, | |
| 2307 | FW_PORT_ACTION_PHY_RESET = 0x0040, | |
| 2308 | FW_PORT_ACTION_PMA_RESET = 0x0041, | |
| 2309 | FW_PORT_ACTION_PCS_RESET = 0x0042, | |
| 2310 | FW_PORT_ACTION_PHYXS_RESET = 0x0043, | |
| 2311 | FW_PORT_ACTION_DTEXS_REEST = 0x0044, | |
| 2312 | FW_PORT_ACTION_AN_RESET = 0x0045 | |
| 2313 | }; | |
| 2314 | ||
| 2315 | enum fw_port_l2cfg_ctlbf { | |
| 2316 | FW_PORT_L2_CTLBF_OVLAN0 = 0x01, | |
| 2317 | FW_PORT_L2_CTLBF_OVLAN1 = 0x02, | |
| 2318 | FW_PORT_L2_CTLBF_OVLAN2 = 0x04, | |
| 2319 | FW_PORT_L2_CTLBF_OVLAN3 = 0x08, | |
| 2320 | FW_PORT_L2_CTLBF_IVLAN = 0x10, | |
| 2321 | FW_PORT_L2_CTLBF_TXIPG = 0x20 | |
| 2322 | }; | |
| 2323 | ||
| 10b00466 AB |
2324 | enum fw_port_dcb_versions { |
| 2325 | FW_PORT_DCB_VER_UNKNOWN, | |
| 2326 | FW_PORT_DCB_VER_CEE1D0, | |
| 2327 | FW_PORT_DCB_VER_CEE1D01, | |
| 2328 | FW_PORT_DCB_VER_IEEE, | |
| 2329 | FW_PORT_DCB_VER_AUTO = 7 | |
| 2330 | }; | |
| 2331 | ||
| bbc02c7e DM |
2332 | enum fw_port_dcb_cfg { |
| 2333 | FW_PORT_DCB_CFG_PG = 0x01, | |
| 2334 | FW_PORT_DCB_CFG_PFC = 0x02, | |
| 2335 | FW_PORT_DCB_CFG_APPL = 0x04 | |
| 2336 | }; | |
| 2337 | ||
| 2338 | enum fw_port_dcb_cfg_rc { | |
| 2339 | FW_PORT_DCB_CFG_SUCCESS = 0x0, | |
| 2340 | FW_PORT_DCB_CFG_ERROR = 0x1 | |
| 2341 | }; | |
| 2342 | ||
| ce91a923 NKI |
2343 | enum fw_port_dcb_type { |
| 2344 | FW_PORT_DCB_TYPE_PGID = 0x00, | |
| 2345 | FW_PORT_DCB_TYPE_PGRATE = 0x01, | |
| 2346 | FW_PORT_DCB_TYPE_PRIORATE = 0x02, | |
| 2347 | FW_PORT_DCB_TYPE_PFC = 0x03, | |
| 2348 | FW_PORT_DCB_TYPE_APP_ID = 0x04, | |
| 989594e2 AB |
2349 | FW_PORT_DCB_TYPE_CONTROL = 0x05, |
| 2350 | }; | |
| 2351 | ||
| 2352 | enum fw_port_dcb_feature_state { | |
| 2353 | FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, | |
| 2354 | FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, | |
| 2355 | FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, | |
| 2356 | FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, | |
| ce91a923 NKI |
2357 | }; |
| 2358 | ||
| bbc02c7e DM |
2359 | struct fw_port_cmd { |
| 2360 | __be32 op_to_portid; | |
| 2361 | __be32 action_to_len16; | |
| 2362 | union fw_port { | |
| 2363 | struct fw_port_l1cfg { | |
| 2364 | __be32 rcap; | |
| 2365 | __be32 r; | |
| 2366 | } l1cfg; | |
| 2367 | struct fw_port_l2cfg { | |
| 989594e2 AB |
2368 | __u8 ctlbf; |
| 2369 | __u8 ovlan3_to_ivlan0; | |
| bbc02c7e | 2370 | __be16 ivlantype; |
| 989594e2 AB |
2371 | __be16 txipg_force_pinfo; |
| 2372 | __be16 mtu; | |
| bbc02c7e DM |
2373 | __be16 ovlan0mask; |
| 2374 | __be16 ovlan0type; | |
| 2375 | __be16 ovlan1mask; | |
| 2376 | __be16 ovlan1type; | |
| 2377 | __be16 ovlan2mask; | |
| 2378 | __be16 ovlan2type; | |
| 2379 | __be16 ovlan3mask; | |
| 2380 | __be16 ovlan3type; | |
| 2381 | } l2cfg; | |
| 2382 | struct fw_port_info { | |
| 2383 | __be32 lstatus_to_modtype; | |
| 2384 | __be16 pcap; | |
| 2385 | __be16 acap; | |
| a0881cab DM |
2386 | __be16 mtu; |
| 2387 | __u8 cbllen; | |
| 989594e2 AB |
2388 | __u8 auxlinfo; |
| 2389 | __u8 dcbxdis_pkd; | |
| eb97ad99 GG |
2390 | __u8 r8_lo; |
| 2391 | __be16 lpacap; | |
| 989594e2 | 2392 | __be64 r9; |
| bbc02c7e | 2393 | } info; |
| 989594e2 AB |
2394 | struct fw_port_diags { |
| 2395 | __u8 diagop; | |
| 2396 | __u8 r[3]; | |
| 2397 | __be32 diagval; | |
| 2398 | } diags; | |
| 2399 | union fw_port_dcb { | |
| 2400 | struct fw_port_dcb_pgid { | |
| 2401 | __u8 type; | |
| 2402 | __u8 apply_pkd; | |
| 2403 | __u8 r10_lo[2]; | |
| 2404 | __be32 pgid; | |
| 2405 | __be64 r11; | |
| 2406 | } pgid; | |
| 2407 | struct fw_port_dcb_pgrate { | |
| 2408 | __u8 type; | |
| 2409 | __u8 apply_pkd; | |
| 2410 | __u8 r10_lo[5]; | |
| 2411 | __u8 num_tcs_supported; | |
| 2412 | __u8 pgrate[8]; | |
| 10b00466 | 2413 | __u8 tsa[8]; |
| 989594e2 AB |
2414 | } pgrate; |
| 2415 | struct fw_port_dcb_priorate { | |
| 2416 | __u8 type; | |
| 2417 | __u8 apply_pkd; | |
| 2418 | __u8 r10_lo[6]; | |
| 2419 | __u8 strict_priorate[8]; | |
| 2420 | } priorate; | |
| 2421 | struct fw_port_dcb_pfc { | |
| 2422 | __u8 type; | |
| 2423 | __u8 pfcen; | |
| 2424 | __u8 r10[5]; | |
| 2425 | __u8 max_pfc_tcs; | |
| 2426 | __be64 r11; | |
| 2427 | } pfc; | |
| 2428 | struct fw_port_app_priority { | |
| 2429 | __u8 type; | |
| 2430 | __u8 r10[2]; | |
| 2431 | __u8 idx; | |
| 2432 | __u8 user_prio_map; | |
| 2433 | __u8 sel_field; | |
| 2434 | __be16 protocolid; | |
| 2435 | __be64 r12; | |
| 2436 | } app_priority; | |
| 2437 | struct fw_port_dcb_control { | |
| 2438 | __u8 type; | |
| 2439 | __u8 all_syncd_pkd; | |
| 10b00466 | 2440 | __be16 dcb_version_to_app_state; |
| 989594e2 AB |
2441 | __be32 r11; |
| 2442 | __be64 r12; | |
| 2443 | } control; | |
| bbc02c7e DM |
2444 | } dcb; |
| 2445 | } u; | |
| 2446 | }; | |
| 2447 | ||
| 2b5fb1f2 HS |
2448 | #define FW_PORT_CMD_READ_S 22 |
| 2449 | #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) | |
| 2450 | #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) | |
| 2451 | ||
| 2452 | #define FW_PORT_CMD_PORTID_S 0 | |
| 2453 | #define FW_PORT_CMD_PORTID_M 0xf | |
| 2454 | #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) | |
| 2455 | #define FW_PORT_CMD_PORTID_G(x) \ | |
| 2456 | (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) | |
| 2457 | ||
| 2458 | #define FW_PORT_CMD_ACTION_S 16 | |
| 2459 | #define FW_PORT_CMD_ACTION_M 0xffff | |
| 2460 | #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) | |
| 2461 | #define FW_PORT_CMD_ACTION_G(x) \ | |
| 2462 | (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) | |
| 2463 | ||
| 2464 | #define FW_PORT_CMD_OVLAN3_S 7 | |
| 2465 | #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) | |
| 2466 | ||
| 2467 | #define FW_PORT_CMD_OVLAN2_S 6 | |
| 2468 | #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) | |
| 2469 | ||
| 2470 | #define FW_PORT_CMD_OVLAN1_S 5 | |
| 2471 | #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) | |
| 2472 | ||
| 2473 | #define FW_PORT_CMD_OVLAN0_S 4 | |
| 2474 | #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) | |
| 2475 | ||
| 2476 | #define FW_PORT_CMD_IVLAN0_S 3 | |
| 2477 | #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) | |
| 2478 | ||
| 2479 | #define FW_PORT_CMD_TXIPG_S 3 | |
| 2480 | #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) | |
| 2481 | ||
| 2482 | #define FW_PORT_CMD_LSTATUS_S 31 | |
| 2483 | #define FW_PORT_CMD_LSTATUS_M 0x1 | |
| 2484 | #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) | |
| 2485 | #define FW_PORT_CMD_LSTATUS_G(x) \ | |
| 2486 | (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) | |
| 2487 | #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) | |
| 2488 | ||
| 2489 | #define FW_PORT_CMD_LSPEED_S 24 | |
| 2490 | #define FW_PORT_CMD_LSPEED_M 0x3f | |
| 2491 | #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) | |
| 2492 | #define FW_PORT_CMD_LSPEED_G(x) \ | |
| 2493 | (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) | |
| 2494 | ||
| 2495 | #define FW_PORT_CMD_TXPAUSE_S 23 | |
| 2496 | #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) | |
| 2497 | #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) | |
| 2498 | ||
| 2499 | #define FW_PORT_CMD_RXPAUSE_S 22 | |
| 2500 | #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) | |
| 2501 | #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) | |
| 2502 | ||
| 2503 | #define FW_PORT_CMD_MDIOCAP_S 21 | |
| 2504 | #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) | |
| 2505 | #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) | |
| 2506 | ||
| 2507 | #define FW_PORT_CMD_MDIOADDR_S 16 | |
| 2508 | #define FW_PORT_CMD_MDIOADDR_M 0x1f | |
| 2509 | #define FW_PORT_CMD_MDIOADDR_G(x) \ | |
| 2510 | (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) | |
| 2511 | ||
| 2512 | #define FW_PORT_CMD_LPTXPAUSE_S 15 | |
| 2513 | #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) | |
| 2514 | #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) | |
| 2515 | ||
| 2516 | #define FW_PORT_CMD_LPRXPAUSE_S 14 | |
| 2517 | #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) | |
| 2518 | #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) | |
| 2519 | ||
| 2520 | #define FW_PORT_CMD_PTYPE_S 8 | |
| 2521 | #define FW_PORT_CMD_PTYPE_M 0x1f | |
| 2522 | #define FW_PORT_CMD_PTYPE_G(x) \ | |
| 2523 | (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) | |
| 2524 | ||
| ddc7740d HS |
2525 | #define FW_PORT_CMD_LINKDNRC_S 5 |
| 2526 | #define FW_PORT_CMD_LINKDNRC_M 0x7 | |
| 2527 | #define FW_PORT_CMD_LINKDNRC_G(x) \ | |
| 2528 | (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M) | |
| 2529 | ||
| 2b5fb1f2 HS |
2530 | #define FW_PORT_CMD_MODTYPE_S 0 |
| 2531 | #define FW_PORT_CMD_MODTYPE_M 0x1f | |
| 2532 | #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) | |
| 2533 | #define FW_PORT_CMD_MODTYPE_G(x) \ | |
| 2534 | (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) | |
| 2535 | ||
| 2536 | #define FW_PORT_CMD_DCBXDIS_S 7 | |
| 2537 | #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) | |
| 2538 | #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) | |
| 2539 | ||
| 2540 | #define FW_PORT_CMD_APPLY_S 7 | |
| 2541 | #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) | |
| 2542 | #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) | |
| 2543 | ||
| 2544 | #define FW_PORT_CMD_ALL_SYNCD_S 7 | |
| 2545 | #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) | |
| 2546 | #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) | |
| 2547 | ||
| 2548 | #define FW_PORT_CMD_DCB_VERSION_S 12 | |
| 2549 | #define FW_PORT_CMD_DCB_VERSION_M 0x7 | |
| 2550 | #define FW_PORT_CMD_DCB_VERSION_G(x) \ | |
| 2551 | (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) | |
| bbc02c7e DM |
2552 | |
| 2553 | enum fw_port_type { | |
| a0881cab DM |
2554 | FW_PORT_TYPE_FIBER_XFI, |
| 2555 | FW_PORT_TYPE_FIBER_XAUI, | |
| bbc02c7e | 2556 | FW_PORT_TYPE_BT_SGMII, |
| a0881cab | 2557 | FW_PORT_TYPE_BT_XFI, |
| bbc02c7e | 2558 | FW_PORT_TYPE_BT_XAUI, |
| a0881cab | 2559 | FW_PORT_TYPE_KX4, |
| bbc02c7e | 2560 | FW_PORT_TYPE_CX4, |
| a0881cab DM |
2561 | FW_PORT_TYPE_KX, |
| 2562 | FW_PORT_TYPE_KR, | |
| 2563 | FW_PORT_TYPE_SFP, | |
| 2564 | FW_PORT_TYPE_BP_AP, | |
| 7d5e77aa | 2565 | FW_PORT_TYPE_BP4_AP, |
| 72aca4bf | 2566 | FW_PORT_TYPE_QSFP_10G, |
| 40e9de4b | 2567 | FW_PORT_TYPE_QSA, |
| 5aa80e51 | 2568 | FW_PORT_TYPE_QSFP, |
| 72aca4bf | 2569 | FW_PORT_TYPE_BP40_BA, |
| eb97ad99 GG |
2570 | FW_PORT_TYPE_KR4_100G, |
| 2571 | FW_PORT_TYPE_CR4_QSFP, | |
| 2572 | FW_PORT_TYPE_CR_QSFP, | |
| 2573 | FW_PORT_TYPE_CR2_QSFP, | |
| 2574 | FW_PORT_TYPE_SFP28, | |
| bbc02c7e | 2575 | |
| 2b5fb1f2 | 2576 | FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M |
| bbc02c7e DM |
2577 | }; |
| 2578 | ||
| 2579 | enum fw_port_module_type { | |
| 2580 | FW_PORT_MOD_TYPE_NA, | |
| 2581 | FW_PORT_MOD_TYPE_LR, | |
| 2582 | FW_PORT_MOD_TYPE_SR, | |
| 2583 | FW_PORT_MOD_TYPE_ER, | |
| a0881cab DM |
2584 | FW_PORT_MOD_TYPE_TWINAX_PASSIVE, |
| 2585 | FW_PORT_MOD_TYPE_TWINAX_ACTIVE, | |
| 2586 | FW_PORT_MOD_TYPE_LRM, | |
| 2b5fb1f2 HS |
2587 | FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, |
| 2588 | FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, | |
| 2589 | FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, | |
| bbc02c7e | 2590 | |
| 2b5fb1f2 | 2591 | FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M |
| bbc02c7e DM |
2592 | }; |
| 2593 | ||
| b407a4a9 VP |
2594 | enum fw_port_mod_sub_type { |
| 2595 | FW_PORT_MOD_SUB_TYPE_NA, | |
| 2596 | FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, | |
| 2597 | FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, | |
| 2598 | FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, | |
| 2599 | FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, | |
| 2600 | FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, | |
| 2601 | FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, | |
| 2602 | ||
| 2603 | /* The following will never been in the VPD. They are TWINAX cable | |
| 2604 | * lengths decoded from SFP+ module i2c PROMs. These should | |
| 2605 | * almost certainly go somewhere else ... | |
| 2606 | */ | |
| 2607 | FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, | |
| 2608 | FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, | |
| 2609 | FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, | |
| 2610 | FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, | |
| 2611 | }; | |
| 2612 | ||
| bbc02c7e | 2613 | enum fw_port_stats_tx_index { |
| 3ccc6cf7 | 2614 | FW_STAT_TX_PORT_BYTES_IX = 0, |
| bbc02c7e DM |
2615 | FW_STAT_TX_PORT_FRAMES_IX, |
| 2616 | FW_STAT_TX_PORT_BCAST_IX, | |
| 2617 | FW_STAT_TX_PORT_MCAST_IX, | |
| 2618 | FW_STAT_TX_PORT_UCAST_IX, | |
| 2619 | FW_STAT_TX_PORT_ERROR_IX, | |
| 2620 | FW_STAT_TX_PORT_64B_IX, | |
| 2621 | FW_STAT_TX_PORT_65B_127B_IX, | |
| 2622 | FW_STAT_TX_PORT_128B_255B_IX, | |
| 2623 | FW_STAT_TX_PORT_256B_511B_IX, | |
| 2624 | FW_STAT_TX_PORT_512B_1023B_IX, | |
| 2625 | FW_STAT_TX_PORT_1024B_1518B_IX, | |
| 2626 | FW_STAT_TX_PORT_1519B_MAX_IX, | |
| 2627 | FW_STAT_TX_PORT_DROP_IX, | |
| 2628 | FW_STAT_TX_PORT_PAUSE_IX, | |
| 2629 | FW_STAT_TX_PORT_PPP0_IX, | |
| 2630 | FW_STAT_TX_PORT_PPP1_IX, | |
| 2631 | FW_STAT_TX_PORT_PPP2_IX, | |
| 2632 | FW_STAT_TX_PORT_PPP3_IX, | |
| 2633 | FW_STAT_TX_PORT_PPP4_IX, | |
| 2634 | FW_STAT_TX_PORT_PPP5_IX, | |
| 2635 | FW_STAT_TX_PORT_PPP6_IX, | |
| 3ccc6cf7 HS |
2636 | FW_STAT_TX_PORT_PPP7_IX, |
| 2637 | FW_NUM_PORT_TX_STATS | |
| bbc02c7e DM |
2638 | }; |
| 2639 | ||
| 2640 | enum fw_port_stat_rx_index { | |
| 3ccc6cf7 | 2641 | FW_STAT_RX_PORT_BYTES_IX = 0, |
| bbc02c7e DM |
2642 | FW_STAT_RX_PORT_FRAMES_IX, |
| 2643 | FW_STAT_RX_PORT_BCAST_IX, | |
| 2644 | FW_STAT_RX_PORT_MCAST_IX, | |
| 2645 | FW_STAT_RX_PORT_UCAST_IX, | |
| 2646 | FW_STAT_RX_PORT_MTU_ERROR_IX, | |
| 2647 | FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, | |
| 2648 | FW_STAT_RX_PORT_CRC_ERROR_IX, | |
| 2649 | FW_STAT_RX_PORT_LEN_ERROR_IX, | |
| 2650 | FW_STAT_RX_PORT_SYM_ERROR_IX, | |
| 2651 | FW_STAT_RX_PORT_64B_IX, | |
| 2652 | FW_STAT_RX_PORT_65B_127B_IX, | |
| 2653 | FW_STAT_RX_PORT_128B_255B_IX, | |
| 2654 | FW_STAT_RX_PORT_256B_511B_IX, | |
| 2655 | FW_STAT_RX_PORT_512B_1023B_IX, | |
| 2656 | FW_STAT_RX_PORT_1024B_1518B_IX, | |
| 2657 | FW_STAT_RX_PORT_1519B_MAX_IX, | |
| 2658 | FW_STAT_RX_PORT_PAUSE_IX, | |
| 2659 | FW_STAT_RX_PORT_PPP0_IX, | |
| 2660 | FW_STAT_RX_PORT_PPP1_IX, | |
| 2661 | FW_STAT_RX_PORT_PPP2_IX, | |
| 2662 | FW_STAT_RX_PORT_PPP3_IX, | |
| 2663 | FW_STAT_RX_PORT_PPP4_IX, | |
| 2664 | FW_STAT_RX_PORT_PPP5_IX, | |
| 2665 | FW_STAT_RX_PORT_PPP6_IX, | |
| 2666 | FW_STAT_RX_PORT_PPP7_IX, | |
| 3ccc6cf7 HS |
2667 | FW_STAT_RX_PORT_LESS_64B_IX, |
| 2668 | FW_STAT_RX_PORT_MAC_ERROR_IX, | |
| 2669 | FW_NUM_PORT_RX_STATS | |
| bbc02c7e DM |
2670 | }; |
| 2671 | ||
| 3ccc6cf7 HS |
2672 | /* port stats */ |
| 2673 | #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS) | |
| 2674 | ||
| bbc02c7e DM |
2675 | struct fw_port_stats_cmd { |
| 2676 | __be32 op_to_portid; | |
| 2677 | __be32 retval_len16; | |
| 2678 | union fw_port_stats { | |
| 2679 | struct fw_port_stats_ctl { | |
| 2680 | u8 nstats_bg_bm; | |
| 2681 | u8 tx_ix; | |
| 2682 | __be16 r6; | |
| 2683 | __be32 r7; | |
| 2684 | __be64 stat0; | |
| 2685 | __be64 stat1; | |
| 2686 | __be64 stat2; | |
| 2687 | __be64 stat3; | |
| 2688 | __be64 stat4; | |
| 2689 | __be64 stat5; | |
| 2690 | } ctl; | |
| 2691 | struct fw_port_stats_all { | |
| 2692 | __be64 tx_bytes; | |
| 2693 | __be64 tx_frames; | |
| 2694 | __be64 tx_bcast; | |
| 2695 | __be64 tx_mcast; | |
| 2696 | __be64 tx_ucast; | |
| 2697 | __be64 tx_error; | |
| 2698 | __be64 tx_64b; | |
| 2699 | __be64 tx_65b_127b; | |
| 2700 | __be64 tx_128b_255b; | |
| 2701 | __be64 tx_256b_511b; | |
| 2702 | __be64 tx_512b_1023b; | |
| 2703 | __be64 tx_1024b_1518b; | |
| 2704 | __be64 tx_1519b_max; | |
| 2705 | __be64 tx_drop; | |
| 2706 | __be64 tx_pause; | |
| 2707 | __be64 tx_ppp0; | |
| 2708 | __be64 tx_ppp1; | |
| 2709 | __be64 tx_ppp2; | |
| 2710 | __be64 tx_ppp3; | |
| 2711 | __be64 tx_ppp4; | |
| 2712 | __be64 tx_ppp5; | |
| 2713 | __be64 tx_ppp6; | |
| 2714 | __be64 tx_ppp7; | |
| 2715 | __be64 rx_bytes; | |
| 2716 | __be64 rx_frames; | |
| 2717 | __be64 rx_bcast; | |
| 2718 | __be64 rx_mcast; | |
| 2719 | __be64 rx_ucast; | |
| 2720 | __be64 rx_mtu_error; | |
| 2721 | __be64 rx_mtu_crc_error; | |
| 2722 | __be64 rx_crc_error; | |
| 2723 | __be64 rx_len_error; | |
| 2724 | __be64 rx_sym_error; | |
| 2725 | __be64 rx_64b; | |
| 2726 | __be64 rx_65b_127b; | |
| 2727 | __be64 rx_128b_255b; | |
| 2728 | __be64 rx_256b_511b; | |
| 2729 | __be64 rx_512b_1023b; | |
| 2730 | __be64 rx_1024b_1518b; | |
| 2731 | __be64 rx_1519b_max; | |
| 2732 | __be64 rx_pause; | |
| 2733 | __be64 rx_ppp0; | |
| 2734 | __be64 rx_ppp1; | |
| 2735 | __be64 rx_ppp2; | |
| 2736 | __be64 rx_ppp3; | |
| 2737 | __be64 rx_ppp4; | |
| 2738 | __be64 rx_ppp5; | |
| 2739 | __be64 rx_ppp6; | |
| 2740 | __be64 rx_ppp7; | |
| 2741 | __be64 rx_less_64b; | |
| 2742 | __be64 rx_bg_drop; | |
| 2743 | __be64 rx_bg_trunc; | |
| 2744 | } all; | |
| 2745 | } u; | |
| 2746 | }; | |
| 2747 | ||
| bbc02c7e DM |
2748 | /* port loopback stats */ |
| 2749 | #define FW_NUM_LB_STATS 16 | |
| 2750 | enum fw_port_lb_stats_index { | |
| 2751 | FW_STAT_LB_PORT_BYTES_IX, | |
| 2752 | FW_STAT_LB_PORT_FRAMES_IX, | |
| 2753 | FW_STAT_LB_PORT_BCAST_IX, | |
| 2754 | FW_STAT_LB_PORT_MCAST_IX, | |
| 2755 | FW_STAT_LB_PORT_UCAST_IX, | |
| 2756 | FW_STAT_LB_PORT_ERROR_IX, | |
| 2757 | FW_STAT_LB_PORT_64B_IX, | |
| 2758 | FW_STAT_LB_PORT_65B_127B_IX, | |
| 2759 | FW_STAT_LB_PORT_128B_255B_IX, | |
| 2760 | FW_STAT_LB_PORT_256B_511B_IX, | |
| 2761 | FW_STAT_LB_PORT_512B_1023B_IX, | |
| 2762 | FW_STAT_LB_PORT_1024B_1518B_IX, | |
| 2763 | FW_STAT_LB_PORT_1519B_MAX_IX, | |
| 2764 | FW_STAT_LB_PORT_DROP_FRAMES_IX | |
| 2765 | }; | |
| 2766 | ||
| 2767 | struct fw_port_lb_stats_cmd { | |
| 2768 | __be32 op_to_lbport; | |
| 2769 | __be32 retval_len16; | |
| 2770 | union fw_port_lb_stats { | |
| 2771 | struct fw_port_lb_stats_ctl { | |
| 2772 | u8 nstats_bg_bm; | |
| 2773 | u8 ix_pkd; | |
| 2774 | __be16 r6; | |
| 2775 | __be32 r7; | |
| 2776 | __be64 stat0; | |
| 2777 | __be64 stat1; | |
| 2778 | __be64 stat2; | |
| 2779 | __be64 stat3; | |
| 2780 | __be64 stat4; | |
| 2781 | __be64 stat5; | |
| 2782 | } ctl; | |
| 2783 | struct fw_port_lb_stats_all { | |
| 2784 | __be64 tx_bytes; | |
| 2785 | __be64 tx_frames; | |
| 2786 | __be64 tx_bcast; | |
| 2787 | __be64 tx_mcast; | |
| 2788 | __be64 tx_ucast; | |
| 2789 | __be64 tx_error; | |
| 2790 | __be64 tx_64b; | |
| 2791 | __be64 tx_65b_127b; | |
| 2792 | __be64 tx_128b_255b; | |
| 2793 | __be64 tx_256b_511b; | |
| 2794 | __be64 tx_512b_1023b; | |
| 2795 | __be64 tx_1024b_1518b; | |
| 2796 | __be64 tx_1519b_max; | |
| 2797 | __be64 rx_lb_drop; | |
| 2798 | __be64 rx_lb_trunc; | |
| 2799 | } all; | |
| 2800 | } u; | |
| 2801 | }; | |
| 2802 | ||
| bbc02c7e DM |
2803 | struct fw_rss_ind_tbl_cmd { |
| 2804 | __be32 op_to_viid; | |
| bbc02c7e DM |
2805 | __be32 retval_len16; |
| 2806 | __be16 niqid; | |
| 2807 | __be16 startidx; | |
| 2808 | __be32 r3; | |
| 2809 | __be32 iq0_to_iq2; | |
| bbc02c7e DM |
2810 | __be32 iq3_to_iq5; |
| 2811 | __be32 iq6_to_iq8; | |
| 2812 | __be32 iq9_to_iq11; | |
| 2813 | __be32 iq12_to_iq14; | |
| 2814 | __be32 iq15_to_iq17; | |
| 2815 | __be32 iq18_to_iq20; | |
| 2816 | __be32 iq21_to_iq23; | |
| 2817 | __be32 iq24_to_iq26; | |
| 2818 | __be32 iq27_to_iq29; | |
| 2819 | __be32 iq30_iq31; | |
| 2820 | __be32 r15_lo; | |
| 2821 | }; | |
| 2822 | ||
| b2e1a3f0 HS |
2823 | #define FW_RSS_IND_TBL_CMD_VIID_S 0 |
| 2824 | #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) | |
| 2825 | ||
| 2826 | #define FW_RSS_IND_TBL_CMD_IQ0_S 20 | |
| 2827 | #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) | |
| 2828 | ||
| 2829 | #define FW_RSS_IND_TBL_CMD_IQ1_S 10 | |
| 2830 | #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) | |
| 2831 | ||
| 2832 | #define FW_RSS_IND_TBL_CMD_IQ2_S 0 | |
| 2833 | #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) | |
| 2834 | ||
| bbc02c7e DM |
2835 | struct fw_rss_glb_config_cmd { |
| 2836 | __be32 op_to_write; | |
| 2837 | __be32 retval_len16; | |
| 2838 | union fw_rss_glb_config { | |
| 2839 | struct fw_rss_glb_config_manual { | |
| 2840 | __be32 mode_pkd; | |
| 2841 | __be32 r3; | |
| 2842 | __be64 r4; | |
| 2843 | __be64 r5; | |
| 2844 | } manual; | |
| 2845 | struct fw_rss_glb_config_basicvirtual { | |
| 2846 | __be32 mode_pkd; | |
| 2847 | __be32 synmapen_to_hashtoeplitz; | |
| bbc02c7e DM |
2848 | __be64 r8; |
| 2849 | __be64 r9; | |
| 2850 | } basicvirtual; | |
| 2851 | } u; | |
| 2852 | }; | |
| 2853 | ||
| b2e1a3f0 HS |
2854 | #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 |
| 2855 | #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf | |
| 2856 | #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) | |
| 2857 | #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ | |
| 2858 | (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) | |
| bbc02c7e DM |
2859 | |
| 2860 | #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 | |
| 2861 | #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 | |
| 2862 | ||
| b2e1a3f0 HS |
2863 | #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 |
| 2864 | #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ | |
| 2865 | ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) | |
| 2866 | #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ | |
| 2867 | FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) | |
| 2868 | ||
| 2869 | #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 | |
| 2870 | #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ | |
| 2871 | ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) | |
| 2872 | #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ | |
| 2873 | FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) | |
| 2874 | ||
| 2875 | #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 | |
| 2876 | #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ | |
| 2877 | ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) | |
| 2878 | #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ | |
| 2879 | FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) | |
| 2880 | ||
| 2881 | #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 | |
| 2882 | #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ | |
| 2883 | ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) | |
| 2884 | #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ | |
| 2885 | FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) | |
| 2886 | ||
| 2887 | #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 | |
| 2888 | #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ | |
| 2889 | ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) | |
| 2890 | #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ | |
| 2891 | FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) | |
| 2892 | ||
| 2893 | #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 | |
| 2894 | #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ | |
| 2895 | ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) | |
| 2896 | #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ | |
| 2897 | FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) | |
| 2898 | ||
| 2899 | #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 | |
| 2900 | #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ | |
| 2901 | ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) | |
| 2902 | #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ | |
| 2903 | FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) | |
| 2904 | ||
| 2905 | #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 | |
| 2906 | #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ | |
| 2907 | ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) | |
| 2908 | #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ | |
| 2909 | FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) | |
| 2910 | ||
| 2911 | #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 | |
| 2912 | #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ | |
| 2913 | ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) | |
| 2914 | #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ | |
| 2915 | FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) | |
| 2916 | ||
| bbc02c7e DM |
2917 | struct fw_rss_vi_config_cmd { |
| 2918 | __be32 op_to_viid; | |
| 2919 | #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) | |
| 2920 | __be32 retval_len16; | |
| 2921 | union fw_rss_vi_config { | |
| 2922 | struct fw_rss_vi_config_manual { | |
| 2923 | __be64 r3; | |
| 2924 | __be64 r4; | |
| 2925 | __be64 r5; | |
| 2926 | } manual; | |
| 2927 | struct fw_rss_vi_config_basicvirtual { | |
| 2928 | __be32 r6; | |
| 81323b74 | 2929 | __be32 defaultq_to_udpen; |
| bbc02c7e DM |
2930 | __be64 r9; |
| 2931 | __be64 r10; | |
| 2932 | } basicvirtual; | |
| 2933 | } u; | |
| 2934 | }; | |
| 2935 | ||
| b2e1a3f0 HS |
2936 | #define FW_RSS_VI_CONFIG_CMD_VIID_S 0 |
| 2937 | #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) | |
| 2938 | ||
| 2939 | #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 | |
| 2940 | #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff | |
| 2941 | #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ | |
| 2942 | ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) | |
| 2943 | #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ | |
| 2944 | (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ | |
| 2945 | FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) | |
| 2946 | ||
| 2947 | #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 | |
| 2948 | #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ | |
| 2949 | ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) | |
| 2950 | #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ | |
| 2951 | FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) | |
| 2952 | ||
| 2953 | #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 | |
| 2954 | #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ | |
| 2955 | ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) | |
| 2956 | #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ | |
| 2957 | FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) | |
| 2958 | ||
| 2959 | #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 | |
| 2960 | #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ | |
| 2961 | ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) | |
| 2962 | #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ | |
| 2963 | FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) | |
| 2964 | ||
| 2965 | #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 | |
| 2966 | #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ | |
| 2967 | ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) | |
| 2968 | #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ | |
| 2969 | FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) | |
| 2970 | ||
| 2971 | #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 | |
| 2972 | #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) | |
| 2973 | #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) | |
| 2974 | ||
| b72a32da RL |
2975 | enum fw_sched_sc { |
| 2976 | FW_SCHED_SC_PARAMS = 1, | |
| 2977 | }; | |
| 2978 | ||
| 2979 | struct fw_sched_cmd { | |
| 2980 | __be32 op_to_write; | |
| 2981 | __be32 retval_len16; | |
| 2982 | union fw_sched { | |
| 2983 | struct fw_sched_config { | |
| 2984 | __u8 sc; | |
| 2985 | __u8 type; | |
| 2986 | __u8 minmaxen; | |
| 2987 | __u8 r3[5]; | |
| 2988 | __u8 nclasses[4]; | |
| 2989 | __be32 r4; | |
| 2990 | } config; | |
| 2991 | struct fw_sched_params { | |
| 2992 | __u8 sc; | |
| 2993 | __u8 type; | |
| 2994 | __u8 level; | |
| 2995 | __u8 mode; | |
| 2996 | __u8 unit; | |
| 2997 | __u8 rate; | |
| 2998 | __u8 ch; | |
| 2999 | __u8 cl; | |
| 3000 | __be32 min; | |
| 3001 | __be32 max; | |
| 3002 | __be16 weight; | |
| 3003 | __be16 pktsize; | |
| 3004 | __be16 burstsize; | |
| 3005 | __be16 r4; | |
| 3006 | } params; | |
| 3007 | } u; | |
| 3008 | }; | |
| 3009 | ||
| 01bcca68 VP |
3010 | struct fw_clip_cmd { |
| 3011 | __be32 op_to_write; | |
| 3012 | __be32 alloc_to_len16; | |
| 3013 | __be64 ip_hi; | |
| 3014 | __be64 ip_lo; | |
| 3015 | __be32 r4[2]; | |
| 3016 | }; | |
| 3017 | ||
| b2e1a3f0 HS |
3018 | #define FW_CLIP_CMD_ALLOC_S 31 |
| 3019 | #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) | |
| 3020 | #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) | |
| 01bcca68 | 3021 | |
| b2e1a3f0 HS |
3022 | #define FW_CLIP_CMD_FREE_S 30 |
| 3023 | #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) | |
| 3024 | #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) | |
| 01bcca68 | 3025 | |
| bbc02c7e DM |
3026 | enum fw_error_type { |
| 3027 | FW_ERROR_TYPE_EXCEPTION = 0x0, | |
| 3028 | FW_ERROR_TYPE_HWMODULE = 0x1, | |
| 3029 | FW_ERROR_TYPE_WR = 0x2, | |
| 3030 | FW_ERROR_TYPE_ACL = 0x3, | |
| 3031 | }; | |
| 3032 | ||
| 3033 | struct fw_error_cmd { | |
| 3034 | __be32 op_to_type; | |
| 3035 | __be32 len16_pkd; | |
| 3036 | union fw_error { | |
| 3037 | struct fw_error_exception { | |
| 3038 | __be32 info[6]; | |
| 3039 | } exception; | |
| 3040 | struct fw_error_hwmodule { | |
| 3041 | __be32 regaddr; | |
| 3042 | __be32 regval; | |
| 3043 | } hwmodule; | |
| 3044 | struct fw_error_wr { | |
| 3045 | __be16 cidx; | |
| 3046 | __be16 pfn_vfn; | |
| 3047 | __be32 eqid; | |
| 3048 | u8 wrhdr[16]; | |
| 3049 | } wr; | |
| 3050 | struct fw_error_acl { | |
| 3051 | __be16 cidx; | |
| 3052 | __be16 pfn_vfn; | |
| 3053 | __be32 eqid; | |
| 3054 | __be16 mv_pkd; | |
| 3055 | u8 val[6]; | |
| 3056 | __be64 r4; | |
| 3057 | } acl; | |
| 3058 | } u; | |
| 3059 | }; | |
| 3060 | ||
| 3061 | struct fw_debug_cmd { | |
| 3062 | __be32 op_type; | |
| bbc02c7e DM |
3063 | __be32 len16_pkd; |
| 3064 | union fw_debug { | |
| 3065 | struct fw_debug_assert { | |
| 3066 | __be32 fcid; | |
| 3067 | __be32 line; | |
| 3068 | __be32 x; | |
| 3069 | __be32 y; | |
| 3070 | u8 filename_0_7[8]; | |
| 3071 | u8 filename_8_15[8]; | |
| 3072 | __be64 r3; | |
| 3073 | } assert; | |
| 3074 | struct fw_debug_prt { | |
| 3075 | __be16 dprtstridx; | |
| 3076 | __be16 r3[3]; | |
| 3077 | __be32 dprtstrparam0; | |
| 3078 | __be32 dprtstrparam1; | |
| 3079 | __be32 dprtstrparam2; | |
| 3080 | __be32 dprtstrparam3; | |
| 3081 | } prt; | |
| 3082 | } u; | |
| 3083 | }; | |
| 3084 | ||
| b2e1a3f0 HS |
3085 | #define FW_DEBUG_CMD_TYPE_S 0 |
| 3086 | #define FW_DEBUG_CMD_TYPE_M 0xff | |
| 3087 | #define FW_DEBUG_CMD_TYPE_G(x) \ | |
| 3088 | (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) | |
| 3089 | ||
| 3090 | #define PCIE_FW_ERR_S 31 | |
| 3091 | #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) | |
| 3092 | #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) | |
| 3093 | ||
| 3094 | #define PCIE_FW_INIT_S 30 | |
| 3095 | #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) | |
| 3096 | #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) | |
| 3097 | ||
| 3098 | #define PCIE_FW_HALT_S 29 | |
| 3099 | #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) | |
| 3100 | #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) | |
| 3101 | ||
| 3102 | #define PCIE_FW_EVAL_S 24 | |
| 3103 | #define PCIE_FW_EVAL_M 0x7 | |
| 3104 | #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) | |
| 3105 | ||
| 3106 | #define PCIE_FW_MASTER_VLD_S 15 | |
| 3107 | #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) | |
| 3108 | #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) | |
| 3109 | ||
| 3110 | #define PCIE_FW_MASTER_S 12 | |
| 3111 | #define PCIE_FW_MASTER_M 0x7 | |
| 3112 | #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) | |
| 3113 | #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) | |
| 52367a76 | 3114 | |
| bbc02c7e DM |
3115 | struct fw_hdr { |
| 3116 | u8 ver; | |
| 16e47624 | 3117 | u8 chip; /* terminator chip type */ |
| bbc02c7e DM |
3118 | __be16 len512; /* bin length in units of 512-bytes */ |
| 3119 | __be32 fw_ver; /* firmware version */ | |
| 3120 | __be32 tp_microcode_ver; | |
| 3121 | u8 intfver_nic; | |
| 3122 | u8 intfver_vnic; | |
| 3123 | u8 intfver_ofld; | |
| 3124 | u8 intfver_ri; | |
| 3125 | u8 intfver_iscsipdu; | |
| 3126 | u8 intfver_iscsi; | |
| b407a4a9 | 3127 | u8 intfver_fcoepdu; |
| bbc02c7e | 3128 | u8 intfver_fcoe; |
| b407a4a9 | 3129 | __u32 reserved2; |
| 26f7cbc0 VP |
3130 | __u32 reserved3; |
| 3131 | __u32 reserved4; | |
| 26f7cbc0 VP |
3132 | __be32 flags; |
| 3133 | __be32 reserved6[23]; | |
| bbc02c7e DM |
3134 | }; |
| 3135 | ||
| 16e47624 HS |
3136 | enum fw_hdr_chip { |
| 3137 | FW_HDR_CHIP_T4, | |
| 3ccc6cf7 HS |
3138 | FW_HDR_CHIP_T5, |
| 3139 | FW_HDR_CHIP_T6 | |
| 16e47624 HS |
3140 | }; |
| 3141 | ||
| b2e1a3f0 HS |
3142 | #define FW_HDR_FW_VER_MAJOR_S 24 |
| 3143 | #define FW_HDR_FW_VER_MAJOR_M 0xff | |
| ba3f8cd5 HS |
3144 | #define FW_HDR_FW_VER_MAJOR_V(x) \ |
| 3145 | ((x) << FW_HDR_FW_VER_MAJOR_S) | |
| b2e1a3f0 HS |
3146 | #define FW_HDR_FW_VER_MAJOR_G(x) \ |
| 3147 | (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) | |
| 3148 | ||
| 3149 | #define FW_HDR_FW_VER_MINOR_S 16 | |
| 3150 | #define FW_HDR_FW_VER_MINOR_M 0xff | |
| ba3f8cd5 HS |
3151 | #define FW_HDR_FW_VER_MINOR_V(x) \ |
| 3152 | ((x) << FW_HDR_FW_VER_MINOR_S) | |
| b2e1a3f0 HS |
3153 | #define FW_HDR_FW_VER_MINOR_G(x) \ |
| 3154 | (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) | |
| 3155 | ||
| 3156 | #define FW_HDR_FW_VER_MICRO_S 8 | |
| 3157 | #define FW_HDR_FW_VER_MICRO_M 0xff | |
| ba3f8cd5 HS |
3158 | #define FW_HDR_FW_VER_MICRO_V(x) \ |
| 3159 | ((x) << FW_HDR_FW_VER_MICRO_S) | |
| b2e1a3f0 HS |
3160 | #define FW_HDR_FW_VER_MICRO_G(x) \ |
| 3161 | (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) | |
| 3162 | ||
| 3163 | #define FW_HDR_FW_VER_BUILD_S 0 | |
| 3164 | #define FW_HDR_FW_VER_BUILD_M 0xff | |
| ba3f8cd5 HS |
3165 | #define FW_HDR_FW_VER_BUILD_V(x) \ |
| 3166 | ((x) << FW_HDR_FW_VER_BUILD_S) | |
| b2e1a3f0 HS |
3167 | #define FW_HDR_FW_VER_BUILD_G(x) \ |
| 3168 | (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) | |
| 3069ee9b | 3169 | |
| b407a4a9 VP |
3170 | enum fw_hdr_intfver { |
| 3171 | FW_HDR_INTFVER_NIC = 0x00, | |
| 3172 | FW_HDR_INTFVER_VNIC = 0x00, | |
| 3173 | FW_HDR_INTFVER_OFLD = 0x00, | |
| 3174 | FW_HDR_INTFVER_RI = 0x00, | |
| 3175 | FW_HDR_INTFVER_ISCSIPDU = 0x00, | |
| 3176 | FW_HDR_INTFVER_ISCSI = 0x00, | |
| 3177 | FW_HDR_INTFVER_FCOEPDU = 0x00, | |
| 3178 | FW_HDR_INTFVER_FCOE = 0x00, | |
| 3179 | }; | |
| 3180 | ||
| 26f7cbc0 VP |
3181 | enum fw_hdr_flags { |
| 3182 | FW_HDR_FLAGS_RESET_HALT = 0x00000001, | |
| 3183 | }; | |
| 3184 | ||
| 49aa284f HS |
3185 | /* length of the formatting string */ |
| 3186 | #define FW_DEVLOG_FMT_LEN 192 | |
| 3187 | ||
| 3188 | /* maximum number of the formatting string parameters */ | |
| 3189 | #define FW_DEVLOG_FMT_PARAMS_NUM 8 | |
| 3190 | ||
| 3191 | /* priority levels */ | |
| 3192 | enum fw_devlog_level { | |
| 3193 | FW_DEVLOG_LEVEL_EMERG = 0x0, | |
| 3194 | FW_DEVLOG_LEVEL_CRIT = 0x1, | |
| 3195 | FW_DEVLOG_LEVEL_ERR = 0x2, | |
| 3196 | FW_DEVLOG_LEVEL_NOTICE = 0x3, | |
| 3197 | FW_DEVLOG_LEVEL_INFO = 0x4, | |
| 3198 | FW_DEVLOG_LEVEL_DEBUG = 0x5, | |
| 3199 | FW_DEVLOG_LEVEL_MAX = 0x5, | |
| 3200 | }; | |
| 3201 | ||
| 3202 | /* facilities that may send a log message */ | |
| 3203 | enum fw_devlog_facility { | |
| 3204 | FW_DEVLOG_FACILITY_CORE = 0x00, | |
| 3205 | FW_DEVLOG_FACILITY_CF = 0x01, | |
| 3206 | FW_DEVLOG_FACILITY_SCHED = 0x02, | |
| 3207 | FW_DEVLOG_FACILITY_TIMER = 0x04, | |
| 3208 | FW_DEVLOG_FACILITY_RES = 0x06, | |
| 3209 | FW_DEVLOG_FACILITY_HW = 0x08, | |
| 3210 | FW_DEVLOG_FACILITY_FLR = 0x10, | |
| 3211 | FW_DEVLOG_FACILITY_DMAQ = 0x12, | |
| 3212 | FW_DEVLOG_FACILITY_PHY = 0x14, | |
| 3213 | FW_DEVLOG_FACILITY_MAC = 0x16, | |
| 3214 | FW_DEVLOG_FACILITY_PORT = 0x18, | |
| 3215 | FW_DEVLOG_FACILITY_VI = 0x1A, | |
| 3216 | FW_DEVLOG_FACILITY_FILTER = 0x1C, | |
| 3217 | FW_DEVLOG_FACILITY_ACL = 0x1E, | |
| 3218 | FW_DEVLOG_FACILITY_TM = 0x20, | |
| 3219 | FW_DEVLOG_FACILITY_QFC = 0x22, | |
| 3220 | FW_DEVLOG_FACILITY_DCB = 0x24, | |
| 3221 | FW_DEVLOG_FACILITY_ETH = 0x26, | |
| 3222 | FW_DEVLOG_FACILITY_OFLD = 0x28, | |
| 3223 | FW_DEVLOG_FACILITY_RI = 0x2A, | |
| 3224 | FW_DEVLOG_FACILITY_ISCSI = 0x2C, | |
| 3225 | FW_DEVLOG_FACILITY_FCOE = 0x2E, | |
| 3226 | FW_DEVLOG_FACILITY_FOISCSI = 0x30, | |
| 3227 | FW_DEVLOG_FACILITY_FOFCOE = 0x32, | |
| 7ef65a42 HS |
3228 | FW_DEVLOG_FACILITY_CHNET = 0x34, |
| 3229 | FW_DEVLOG_FACILITY_MAX = 0x34, | |
| 49aa284f HS |
3230 | }; |
| 3231 | ||
| 3232 | /* log message format */ | |
| 3233 | struct fw_devlog_e { | |
| 3234 | __be64 timestamp; | |
| 3235 | __be32 seqno; | |
| 3236 | __be16 reserved1; | |
| 3237 | __u8 level; | |
| 3238 | __u8 facility; | |
| 3239 | __u8 fmt[FW_DEVLOG_FMT_LEN]; | |
| 3240 | __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; | |
| 3241 | __be32 reserved3[4]; | |
| 3242 | }; | |
| 3243 | ||
| 3244 | struct fw_devlog_cmd { | |
| 3245 | __be32 op_to_write; | |
| 3246 | __be32 retval_len16; | |
| 3247 | __u8 level; | |
| 3248 | __u8 r2[7]; | |
| 3249 | __be32 memtype_devlog_memaddr16_devlog; | |
| 3250 | __be32 memsize_devlog; | |
| 3251 | __be32 r3[2]; | |
| 3252 | }; | |
| 3253 | ||
| 3254 | #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 | |
| 3255 | #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf | |
| 3256 | #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ | |
| 3257 | (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ | |
| 3258 | FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) | |
| 3259 | ||
| 3260 | #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 | |
| 3261 | #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff | |
| 3262 | #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ | |
| 3263 | (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ | |
| 3264 | FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) | |
| 3265 | ||
| 7ef65a42 HS |
3266 | /* P C I E F W P F 7 R E G I S T E R */ |
| 3267 | ||
| 3268 | /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to | |
| 3269 | * access the "devlog" which needing to contact firmware. The encoding is | |
| 3270 | * mostly the same as that returned by the DEVLOG command except for the size | |
| 3271 | * which is encoded as the number of entries in multiples-1 of 128 here rather | |
| 3272 | * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 | |
| 3273 | * and 15 means 2048. This of course in turn constrains the allowed values | |
| 3274 | * for the devlog size ... | |
| 3275 | */ | |
| 3276 | #define PCIE_FW_PF_DEVLOG 7 | |
| 3277 | ||
| 3278 | #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 | |
| 3279 | #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf | |
| 3280 | #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ | |
| 3281 | ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) | |
| 3282 | #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ | |
| 3283 | (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ | |
| 3284 | PCIE_FW_PF_DEVLOG_NENTRIES128_M) | |
| 3285 | ||
| 3286 | #define PCIE_FW_PF_DEVLOG_ADDR16_S 4 | |
| 3287 | #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff | |
| 3288 | #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) | |
| 3289 | #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ | |
| 3290 | (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) | |
| 3291 | ||
| 3292 | #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 | |
| 3293 | #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf | |
| 3294 | #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) | |
| 3295 | #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ | |
| 3296 | (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) | |
| 3297 | ||
| d6657781 HS |
3298 | #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr)) |
| 3299 | ||
| 3300 | struct fw_crypto_lookaside_wr { | |
| 3301 | __be32 op_to_cctx_size; | |
| 3302 | __be32 len16_pkd; | |
| 3303 | __be32 session_id; | |
| 3304 | __be32 rx_chid_to_rx_q_id; | |
| 3305 | __be32 key_addr; | |
| 3306 | __be32 pld_size_hash_size; | |
| 3307 | __be64 cookie; | |
| 3308 | }; | |
| 3309 | ||
| 3310 | #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24 | |
| 3311 | #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff | |
| 3312 | #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \ | |
| 3313 | ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) | |
| 3314 | #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \ | |
| 3315 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \ | |
| 3316 | FW_CRYPTO_LOOKASIDE_WR_OPCODE_M) | |
| 3317 | ||
| 3318 | #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23 | |
| 3319 | #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1 | |
| 3320 | #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \ | |
| 3321 | ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S) | |
| 3322 | #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \ | |
| 3323 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \ | |
| 3324 | FW_CRYPTO_LOOKASIDE_WR_COMPL_M) | |
| 3325 | #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U) | |
| 3326 | ||
| 3327 | #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15 | |
| 3328 | #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff | |
| 3329 | #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \ | |
| 3330 | ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) | |
| 3331 | #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \ | |
| 3332 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \ | |
| 3333 | FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M) | |
| 3334 | ||
| 3335 | #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5 | |
| 3336 | #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3 | |
| 3337 | #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \ | |
| 3338 | ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) | |
| 3339 | #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \ | |
| 3340 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \ | |
| 3341 | FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M) | |
| 3342 | ||
| 3343 | #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0 | |
| 3344 | #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f | |
| 3345 | #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \ | |
| 3346 | ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) | |
| 3347 | #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \ | |
| 3348 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \ | |
| 3349 | FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M) | |
| 3350 | ||
| 3351 | #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0 | |
| 3352 | #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff | |
| 3353 | #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \ | |
| 3354 | ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S) | |
| 3355 | #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \ | |
| 3356 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \ | |
| 3357 | FW_CRYPTO_LOOKASIDE_WR_LEN16_M) | |
| 3358 | ||
| 3359 | #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29 | |
| 3360 | #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3 | |
| 3361 | #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \ | |
| 3362 | ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) | |
| 3363 | #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \ | |
| 3364 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \ | |
| 3365 | FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M) | |
| 3366 | ||
| 3367 | #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27 | |
| 3368 | #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3 | |
| 3369 | #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \ | |
| 3370 | ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S) | |
| 3371 | #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \ | |
| 3372 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M) | |
| 3373 | ||
| 3374 | #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25 | |
| 3375 | #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3 | |
| 3376 | #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \ | |
| 3377 | ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S) | |
| 3378 | #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \ | |
| 3379 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \ | |
| 3380 | FW_CRYPTO_LOOKASIDE_WR_PHASH_M) | |
| 3381 | ||
| 3382 | #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23 | |
| 3383 | #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3 | |
| 3384 | #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \ | |
| 3385 | ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S) | |
| 3386 | #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \ | |
| 3387 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M) | |
| 3388 | ||
| 8a13449f HJ |
3389 | #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15 |
| 3390 | #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff | |
| 3391 | #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \ | |
| 3392 | ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) | |
| 3393 | #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \ | |
| 3394 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \ | |
| 3395 | FW_CRYPTO_LOOKASIDE_WR_FQIDX_M) | |
| 3396 | ||
| d6657781 HS |
3397 | #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10 |
| 3398 | #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3 | |
| 3399 | #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \ | |
| 3400 | ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) | |
| 3401 | #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \ | |
| 3402 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \ | |
| 3403 | FW_CRYPTO_LOOKASIDE_WR_TX_CH_M) | |
| 3404 | ||
| 3405 | #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0 | |
| 3406 | #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff | |
| 3407 | #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \ | |
| 3408 | ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) | |
| 3409 | #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \ | |
| 3410 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \ | |
| 3411 | FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M) | |
| 3412 | ||
| 3413 | #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24 | |
| 3414 | #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff | |
| 3415 | #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \ | |
| 3416 | ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) | |
| 3417 | #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \ | |
| 3418 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \ | |
| 3419 | FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M) | |
| 3420 | ||
| 3421 | #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17 | |
| 3422 | #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f | |
| 3423 | #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \ | |
| 3424 | ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) | |
| 3425 | #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \ | |
| 3426 | (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \ | |
| 3427 | FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M) | |
| 3428 | ||
| bbc02c7e | 3429 | #endif /* _T4FW_INTERFACE_H_ */ |