projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| bbc02c7e DM |
1 | /* |
| 2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
| 3 | * | |
| ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
| bbc02c7e DM |
5 | * |
| 6 | * This software is available to you under a choice of one of two | |
| 7 | * licenses. You may choose to be licensed under the terms of the GNU | |
| 8 | * General Public License (GPL) Version 2, available from the file | |
| 9 | * COPYING in the main directory of this source tree, or the | |
| 10 | * OpenIB.org BSD license below: | |
| 11 | * | |
| 12 | * Redistribution and use in source and binary forms, with or | |
| 13 | * without modification, are permitted provided that the following | |
| 14 | * conditions are met: | |
| 15 | * | |
| 16 | * - Redistributions of source code must retain the above | |
| 17 | * copyright notice, this list of conditions and the following | |
| 18 | * disclaimer. | |
| 19 | * | |
| 20 | * - Redistributions in binary form must reproduce the above | |
| 21 | * copyright notice, this list of conditions and the following | |
| 22 | * disclaimer in the documentation and/or other materials | |
| 23 | * provided with the distribution. | |
| 24 | * | |
| 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
| 27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
| 29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
| 30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
| 31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
| 32 | * SOFTWARE. | |
| 33 | */ | |
| 34 | ||
| 35 | #ifndef __T4_REGS_H | |
| 36 | #define __T4_REGS_H | |
| 37 | ||
| 38 | #define MYPF_BASE 0x1b000 | |
| 39 | #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) | |
| 40 | ||
| 41 | #define PF0_BASE 0x1e000 | |
| 42 | #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) | |
| 43 | ||
| 44 | #define PF_STRIDE 0x400 | |
| 45 | #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) | |
| 46 | #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) | |
| 47 | ||
| 48 | #define MYPORT_BASE 0x1c000 | |
| 49 | #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) | |
| 50 | ||
| 51 | #define PORT0_BASE 0x20000 | |
| 52 | #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) | |
| 53 | ||
| 54 | #define PORT_STRIDE 0x2000 | |
| 55 | #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) | |
| 56 | #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) | |
| 57 | ||
| 58 | #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) | |
| 59 | #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) | |
| 60 | ||
| 61 | #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) | |
| 62 | #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) | |
| 63 | #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) | |
| 64 | #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) | |
| 65 | ||
| 66 | #define SGE_PF_KDOORBELL 0x0 | |
| 67 | #define QID_MASK 0xffff8000U | |
| 68 | #define QID_SHIFT 15 | |
| 69 | #define QID(x) ((x) << QID_SHIFT) | |
| ce91a923 | 70 | #define DBPRIO(x) ((x) << 14) |
| b2decadd | 71 | #define DBTYPE(x) ((x) << 13) |
| bbc02c7e DM |
72 | #define PIDX_MASK 0x00003fffU |
| 73 | #define PIDX_SHIFT 0 | |
| 74 | #define PIDX(x) ((x) << PIDX_SHIFT) | |
| b2decadd SR |
75 | #define S_PIDX_T5 0 |
| 76 | #define M_PIDX_T5 0x1fffU | |
| 77 | #define PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5) | |
| 78 | ||
| bbc02c7e DM |
79 | |
| 80 | #define SGE_PF_GTS 0x4 | |
| 81 | #define INGRESSQID_MASK 0xffff0000U | |
| 82 | #define INGRESSQID_SHIFT 16 | |
| 83 | #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) | |
| 84 | #define TIMERREG_MASK 0x0000e000U | |
| 85 | #define TIMERREG_SHIFT 13 | |
| 86 | #define TIMERREG(x) ((x) << TIMERREG_SHIFT) | |
| 87 | #define SEINTARM_MASK 0x00001000U | |
| 88 | #define SEINTARM_SHIFT 12 | |
| 89 | #define SEINTARM(x) ((x) << SEINTARM_SHIFT) | |
| 90 | #define CIDXINC_MASK 0x00000fffU | |
| 91 | #define CIDXINC_SHIFT 0 | |
| 92 | #define CIDXINC(x) ((x) << CIDXINC_SHIFT) | |
| 93 | ||
| 52367a76 VP |
94 | #define X_RXPKTCPLMODE_SPLIT 1 |
| 95 | #define X_INGPADBOUNDARY_SHIFT 5 | |
| 96 | ||
| bbc02c7e DM |
97 | #define SGE_CONTROL 0x1008 |
| 98 | #define DCASYSTYPE 0x00080000U | |
| 52367a76 VP |
99 | #define RXPKTCPLMODE_MASK 0x00040000U |
| 100 | #define RXPKTCPLMODE_SHIFT 18 | |
| 101 | #define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT) | |
| 102 | #define EGRSTATUSPAGESIZE_MASK 0x00020000U | |
| 103 | #define EGRSTATUSPAGESIZE_SHIFT 17 | |
| 104 | #define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT) | |
| bbc02c7e DM |
105 | #define PKTSHIFT_MASK 0x00001c00U |
| 106 | #define PKTSHIFT_SHIFT 10 | |
| 107 | #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT) | |
| 17edf259 | 108 | #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT) |
| bbc02c7e DM |
109 | #define INGPCIEBOUNDARY_MASK 0x00000380U |
| 110 | #define INGPCIEBOUNDARY_SHIFT 7 | |
| 111 | #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT) | |
| 112 | #define INGPADBOUNDARY_MASK 0x00000070U | |
| 113 | #define INGPADBOUNDARY_SHIFT 4 | |
| 114 | #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT) | |
| 17edf259 CL |
115 | #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \ |
| 116 | >> INGPADBOUNDARY_SHIFT) | |
| bbc02c7e DM |
117 | #define EGRPCIEBOUNDARY_MASK 0x0000000eU |
| 118 | #define EGRPCIEBOUNDARY_SHIFT 1 | |
| 119 | #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT) | |
| 120 | #define GLOBALENABLE 0x00000001U | |
| 121 | ||
| 122 | #define SGE_HOST_PAGE_SIZE 0x100c | |
| 636f9d37 VP |
123 | |
| 124 | #define HOSTPAGESIZEPF7_MASK 0x0000000fU | |
| 125 | #define HOSTPAGESIZEPF7_SHIFT 28 | |
| 126 | #define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT) | |
| 127 | ||
| 128 | #define HOSTPAGESIZEPF6_MASK 0x0000000fU | |
| 129 | #define HOSTPAGESIZEPF6_SHIFT 24 | |
| 130 | #define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT) | |
| 131 | ||
| 132 | #define HOSTPAGESIZEPF5_MASK 0x0000000fU | |
| 133 | #define HOSTPAGESIZEPF5_SHIFT 20 | |
| 134 | #define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT) | |
| 135 | ||
| 136 | #define HOSTPAGESIZEPF4_MASK 0x0000000fU | |
| 137 | #define HOSTPAGESIZEPF4_SHIFT 16 | |
| 138 | #define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT) | |
| 139 | ||
| 140 | #define HOSTPAGESIZEPF3_MASK 0x0000000fU | |
| 141 | #define HOSTPAGESIZEPF3_SHIFT 12 | |
| 142 | #define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT) | |
| 143 | ||
| 144 | #define HOSTPAGESIZEPF2_MASK 0x0000000fU | |
| 145 | #define HOSTPAGESIZEPF2_SHIFT 8 | |
| 146 | #define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT) | |
| 147 | ||
| 148 | #define HOSTPAGESIZEPF1_MASK 0x0000000fU | |
| 149 | #define HOSTPAGESIZEPF1_SHIFT 4 | |
| 150 | #define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT) | |
| 151 | ||
| bbc02c7e DM |
152 | #define HOSTPAGESIZEPF0_MASK 0x0000000fU |
| 153 | #define HOSTPAGESIZEPF0_SHIFT 0 | |
| 154 | #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT) | |
| 155 | ||
| 156 | #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 | |
| 157 | #define QUEUESPERPAGEPF0_MASK 0x0000000fU | |
| 158 | #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) | |
| 159 | ||
| b2decadd SR |
160 | #define QUEUESPERPAGEPF1 4 |
| 161 | ||
| bbc02c7e DM |
162 | #define SGE_INT_CAUSE1 0x1024 |
| 163 | #define SGE_INT_CAUSE2 0x1030 | |
| 164 | #define SGE_INT_CAUSE3 0x103c | |
| 165 | #define ERR_FLM_DBP 0x80000000U | |
| 166 | #define ERR_FLM_IDMA1 0x40000000U | |
| 167 | #define ERR_FLM_IDMA0 0x20000000U | |
| 168 | #define ERR_FLM_HINT 0x10000000U | |
| 169 | #define ERR_PCIE_ERROR3 0x08000000U | |
| 170 | #define ERR_PCIE_ERROR2 0x04000000U | |
| 171 | #define ERR_PCIE_ERROR1 0x02000000U | |
| 172 | #define ERR_PCIE_ERROR0 0x01000000U | |
| 173 | #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U | |
| 174 | #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U | |
| 175 | #define ERR_INVALID_CIDX_INC 0x00200000U | |
| 176 | #define ERR_ITP_TIME_PAUSED 0x00100000U | |
| 177 | #define ERR_CPL_OPCODE_0 0x00080000U | |
| 178 | #define ERR_DROPPED_DB 0x00040000U | |
| 179 | #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U | |
| 180 | #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U | |
| 181 | #define ERR_BAD_DB_PIDX3 0x00008000U | |
| 182 | #define ERR_BAD_DB_PIDX2 0x00004000U | |
| 183 | #define ERR_BAD_DB_PIDX1 0x00002000U | |
| 184 | #define ERR_BAD_DB_PIDX0 0x00001000U | |
| 185 | #define ERR_ING_PCIE_CHAN 0x00000800U | |
| 186 | #define ERR_ING_CTXT_PRIO 0x00000400U | |
| 187 | #define ERR_EGR_CTXT_PRIO 0x00000200U | |
| 188 | #define DBFIFO_HP_INT 0x00000100U | |
| 189 | #define DBFIFO_LP_INT 0x00000080U | |
| 190 | #define REG_ADDRESS_ERR 0x00000040U | |
| 191 | #define INGRESS_SIZE_ERR 0x00000020U | |
| 192 | #define EGRESS_SIZE_ERR 0x00000010U | |
| 193 | #define ERR_INV_CTXT3 0x00000008U | |
| 194 | #define ERR_INV_CTXT2 0x00000004U | |
| 195 | #define ERR_INV_CTXT1 0x00000002U | |
| 196 | #define ERR_INV_CTXT0 0x00000001U | |
| 197 | ||
| 198 | #define SGE_INT_ENABLE3 0x1040 | |
| 199 | #define SGE_FL_BUFFER_SIZE0 0x1044 | |
| 200 | #define SGE_FL_BUFFER_SIZE1 0x1048 | |
| 636f9d37 VP |
201 | #define SGE_FL_BUFFER_SIZE2 0x104c |
| 202 | #define SGE_FL_BUFFER_SIZE3 0x1050 | |
| ce91a923 NKI |
203 | #define SGE_FL_BUFFER_SIZE4 0x1054 |
| 204 | #define SGE_FL_BUFFER_SIZE5 0x1058 | |
| 205 | #define SGE_FL_BUFFER_SIZE6 0x105c | |
| 206 | #define SGE_FL_BUFFER_SIZE7 0x1060 | |
| 207 | #define SGE_FL_BUFFER_SIZE8 0x1064 | |
| 208 | ||
| bbc02c7e DM |
209 | #define SGE_INGRESS_RX_THRESHOLD 0x10a0 |
| 210 | #define THRESHOLD_0_MASK 0x3f000000U | |
| 211 | #define THRESHOLD_0_SHIFT 24 | |
| 212 | #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT) | |
| 213 | #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT) | |
| 214 | #define THRESHOLD_1_MASK 0x003f0000U | |
| 215 | #define THRESHOLD_1_SHIFT 16 | |
| 216 | #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT) | |
| 217 | #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT) | |
| 218 | #define THRESHOLD_2_MASK 0x00003f00U | |
| 219 | #define THRESHOLD_2_SHIFT 8 | |
| 220 | #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT) | |
| 221 | #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT) | |
| 222 | #define THRESHOLD_3_MASK 0x0000003fU | |
| 223 | #define THRESHOLD_3_SHIFT 0 | |
| 224 | #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT) | |
| 225 | #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT) | |
| 226 | ||
| 52367a76 VP |
227 | #define SGE_CONM_CTRL 0x1094 |
| 228 | #define EGRTHRESHOLD_MASK 0x00003f00U | |
| 229 | #define EGRTHRESHOLDshift 8 | |
| 230 | #define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift) | |
| 231 | #define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift) | |
| 232 | ||
| c2b955e0 KS |
233 | #define EGRTHRESHOLDPACKING_MASK 0x3fU |
| 234 | #define EGRTHRESHOLDPACKING_SHIFT 14 | |
| 235 | #define EGRTHRESHOLDPACKING(x) ((x) << EGRTHRESHOLDPACKING_SHIFT) | |
| 236 | #define EGRTHRESHOLDPACKING_GET(x) (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \ | |
| 237 | EGRTHRESHOLDPACKING_MASK) | |
| 238 | ||
| ce91a923 NKI |
239 | #define SGE_DBFIFO_STATUS 0x10a4 |
| 240 | #define HP_INT_THRESH_SHIFT 28 | |
| 241 | #define HP_INT_THRESH_MASK 0xfU | |
| 242 | #define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT) | |
| 243 | #define LP_INT_THRESH_SHIFT 12 | |
| 244 | #define LP_INT_THRESH_MASK 0xfU | |
| 245 | #define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT) | |
| 246 | ||
| 247 | #define SGE_DOORBELL_CONTROL 0x10a8 | |
| 248 | #define ENABLE_DROP (1 << 13) | |
| 249 | ||
| 3cbdb928 VP |
250 | #define S_NOCOALESCE 26 |
| 251 | #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE) | |
| 252 | #define F_NOCOALESCE V_NOCOALESCE(1U) | |
| 253 | ||
| 7730b4c7 HS |
254 | #define SGE_TIMESTAMP_LO 0x1098 |
| 255 | #define SGE_TIMESTAMP_HI 0x109c | |
| 256 | #define S_TSVAL 0 | |
| 257 | #define M_TSVAL 0xfffffffU | |
| 258 | #define GET_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL) | |
| 259 | ||
| bbc02c7e DM |
260 | #define SGE_TIMER_VALUE_0_AND_1 0x10b8 |
| 261 | #define TIMERVALUE0_MASK 0xffff0000U | |
| 262 | #define TIMERVALUE0_SHIFT 16 | |
| 263 | #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT) | |
| 264 | #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT) | |
| 265 | #define TIMERVALUE1_MASK 0x0000ffffU | |
| 266 | #define TIMERVALUE1_SHIFT 0 | |
| 267 | #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT) | |
| 268 | #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT) | |
| 269 | ||
| 270 | #define SGE_TIMER_VALUE_2_AND_3 0x10bc | |
| 52367a76 VP |
271 | #define TIMERVALUE2_MASK 0xffff0000U |
| 272 | #define TIMERVALUE2_SHIFT 16 | |
| 273 | #define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT) | |
| 274 | #define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT) | |
| 275 | #define TIMERVALUE3_MASK 0x0000ffffU | |
| 276 | #define TIMERVALUE3_SHIFT 0 | |
| 277 | #define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT) | |
| 278 | #define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT) | |
| 279 | ||
| bbc02c7e | 280 | #define SGE_TIMER_VALUE_4_AND_5 0x10c0 |
| 52367a76 VP |
281 | #define TIMERVALUE4_MASK 0xffff0000U |
| 282 | #define TIMERVALUE4_SHIFT 16 | |
| 283 | #define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT) | |
| 284 | #define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT) | |
| 285 | #define TIMERVALUE5_MASK 0x0000ffffU | |
| 286 | #define TIMERVALUE5_SHIFT 0 | |
| 287 | #define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT) | |
| 288 | #define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT) | |
| 289 | ||
| bbc02c7e DM |
290 | #define SGE_DEBUG_INDEX 0x10cc |
| 291 | #define SGE_DEBUG_DATA_HIGH 0x10d0 | |
| 292 | #define SGE_DEBUG_DATA_LOW 0x10d4 | |
| 68bce192 KS |
293 | #define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8 |
| 294 | #define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc | |
| 295 | #define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8 | |
| bbc02c7e DM |
296 | #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 |
| 297 | ||
| 3069ee9b | 298 | #define S_HP_INT_THRESH 28 |
| 840f3000 | 299 | #define M_HP_INT_THRESH 0xfU |
| 3069ee9b | 300 | #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) |
| b2decadd SR |
301 | #define S_LP_INT_THRESH_T5 18 |
| 302 | #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) | |
| 303 | #define M_LP_COUNT_T5 0x3ffffU | |
| 304 | #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5) | |
| 840f3000 VP |
305 | #define M_HP_COUNT 0x7ffU |
| 306 | #define S_HP_COUNT 16 | |
| 307 | #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) | |
| 308 | #define S_LP_INT_THRESH 12 | |
| 309 | #define M_LP_INT_THRESH 0xfU | |
| b2decadd | 310 | #define M_LP_INT_THRESH_T5 0xfffU |
| 840f3000 VP |
311 | #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) |
| 312 | #define M_LP_COUNT 0x7ffU | |
| 313 | #define S_LP_COUNT 0 | |
| 314 | #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) | |
| 3069ee9b VP |
315 | #define A_SGE_DBFIFO_STATUS 0x10a4 |
| 316 | ||
| b2decadd SR |
317 | #define SGE_STAT_TOTAL 0x10e4 |
| 318 | #define SGE_STAT_MATCH 0x10e8 | |
| 319 | ||
| 320 | #define SGE_STAT_CFG 0x10ec | |
| 321 | #define S_STATSOURCE_T5 9 | |
| 322 | #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) | |
| 323 | ||
| 324 | #define SGE_DBFIFO_STATUS2 0x1118 | |
| 325 | #define M_HP_COUNT_T5 0x3ffU | |
| 326 | #define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5) | |
| 327 | #define S_HP_INT_THRESH_T5 10 | |
| 328 | #define M_HP_INT_THRESH_T5 0xfU | |
| 329 | #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) | |
| 330 | ||
| 3069ee9b VP |
331 | #define S_ENABLE_DROP 13 |
| 332 | #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) | |
| 333 | #define F_ENABLE_DROP V_ENABLE_DROP(1U) | |
| 3069ee9b VP |
334 | #define S_DROPPED_DB 0 |
| 335 | #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB) | |
| 336 | #define F_DROPPED_DB V_DROPPED_DB(1U) | |
| 840f3000 | 337 | #define A_SGE_DOORBELL_CONTROL 0x10a8 |
| 3069ee9b | 338 | |
| 840f3000 VP |
339 | #define A_SGE_CTXT_CMD 0x11fc |
| 340 | #define A_SGE_DBQ_CTXT_BADDR 0x1084 | |
| 3069ee9b | 341 | |
| ce91a923 NKI |
342 | #define PCIE_PF_CFG 0x40 |
| 343 | #define AIVEC(x) ((x) << 4) | |
| 344 | #define AIVEC_MASK 0x3ffU | |
| 345 | ||
| bbc02c7e DM |
346 | #define PCIE_PF_CLI 0x44 |
| 347 | #define PCIE_INT_CAUSE 0x3004 | |
| 348 | #define UNXSPLCPLERR 0x20000000U | |
| 349 | #define PCIEPINT 0x10000000U | |
| 350 | #define PCIESINT 0x08000000U | |
| 351 | #define RPLPERR 0x04000000U | |
| 352 | #define RXWRPERR 0x02000000U | |
| 353 | #define RXCPLPERR 0x01000000U | |
| 354 | #define PIOTAGPERR 0x00800000U | |
| 355 | #define MATAGPERR 0x00400000U | |
| 356 | #define INTXCLRPERR 0x00200000U | |
| 357 | #define FIDPERR 0x00100000U | |
| 358 | #define CFGSNPPERR 0x00080000U | |
| 359 | #define HRSPPERR 0x00040000U | |
| 360 | #define HREQPERR 0x00020000U | |
| 361 | #define HCNTPERR 0x00010000U | |
| 362 | #define DRSPPERR 0x00008000U | |
| 363 | #define DREQPERR 0x00004000U | |
| 364 | #define DCNTPERR 0x00002000U | |
| 365 | #define CRSPPERR 0x00001000U | |
| 366 | #define CREQPERR 0x00000800U | |
| 367 | #define CCNTPERR 0x00000400U | |
| 368 | #define TARTAGPERR 0x00000200U | |
| 369 | #define PIOREQPERR 0x00000100U | |
| 370 | #define PIOCPLPERR 0x00000080U | |
| 371 | #define MSIXDIPERR 0x00000040U | |
| 372 | #define MSIXDATAPERR 0x00000020U | |
| 373 | #define MSIXADDRHPERR 0x00000010U | |
| 374 | #define MSIXADDRLPERR 0x00000008U | |
| 375 | #define MSIDATAPERR 0x00000004U | |
| 376 | #define MSIADDRHPERR 0x00000002U | |
| 377 | #define MSIADDRLPERR 0x00000001U | |
| 378 | ||
| b2decadd SR |
379 | #define READRSPERR 0x20000000U |
| 380 | #define TRGT1GRPPERR 0x10000000U | |
| 381 | #define IPSOTPERR 0x08000000U | |
| 382 | #define IPRXDATAGRPPERR 0x02000000U | |
| 383 | #define IPRXHDRGRPPERR 0x01000000U | |
| 384 | #define MAGRPPERR 0x00400000U | |
| 385 | #define VFIDPERR 0x00200000U | |
| 386 | #define HREQWRPERR 0x00010000U | |
| 387 | #define DREQWRPERR 0x00002000U | |
| 388 | #define MSTTAGQPERR 0x00000400U | |
| 389 | #define PIOREQGRPPERR 0x00000100U | |
| 390 | #define PIOCPLGRPPERR 0x00000080U | |
| 391 | #define MSIXSTIPERR 0x00000004U | |
| 392 | #define MSTTIMEOUTPERR 0x00000002U | |
| 393 | #define MSTGRPPERR 0x00000001U | |
| 394 | ||
| bbc02c7e | 395 | #define PCIE_NONFAT_ERR 0x3010 |
| 0abfd152 HS |
396 | #define PCIE_CFG_SPACE_REQ 0x3060 |
| 397 | #define PCIE_CFG_SPACE_DATA 0x3064 | |
| bbc02c7e | 398 | #define PCIE_MEM_ACCESS_BASE_WIN 0x3068 |
| b2decadd SR |
399 | #define S_PCIEOFST 10 |
| 400 | #define M_PCIEOFST 0x3fffffU | |
| 401 | #define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) | |
| bbc02c7e DM |
402 | #define PCIEOFST_MASK 0xfffffc00U |
| 403 | #define BIR_MASK 0x00000300U | |
| 404 | #define BIR_SHIFT 8 | |
| 405 | #define BIR(x) ((x) << BIR_SHIFT) | |
| 406 | #define WINDOW_MASK 0x000000ffU | |
| 407 | #define WINDOW_SHIFT 0 | |
| 408 | #define WINDOW(x) ((x) << WINDOW_SHIFT) | |
| fc5ab020 | 409 | #define GET_WINDOW(x) (((x) >> WINDOW_SHIFT) & WINDOW_MASK) |
| 1ae970e0 | 410 | #define PCIE_MEM_ACCESS_OFFSET 0x306c |
| 0abfd152 HS |
411 | #define ENABLE (1U << 30) |
| 412 | #define FUNCTION(x) ((x) << 12) | |
| 413 | #define F_LOCALCFG (1U << 28) | |
| bbc02c7e | 414 | |
| b2decadd SR |
415 | #define S_PFNUM 0 |
| 416 | #define V_PFNUM(x) ((x) << S_PFNUM) | |
| 417 | ||
| 26f7cbc0 | 418 | #define PCIE_FW 0x30b8 |
| ce91a923 NKI |
419 | #define PCIE_FW_ERR 0x80000000U |
| 420 | #define PCIE_FW_INIT 0x40000000U | |
| 421 | #define PCIE_FW_HALT 0x20000000U | |
| 422 | #define PCIE_FW_MASTER_VLD 0x00008000U | |
| 423 | #define PCIE_FW_MASTER(x) ((x) << 12) | |
| 424 | #define PCIE_FW_MASTER_MASK 0x7 | |
| 425 | #define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK) | |
| 26f7cbc0 | 426 | |
| bbc02c7e DM |
427 | #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 |
| 428 | #define RNPP 0x80000000U | |
| 429 | #define RPCP 0x20000000U | |
| 430 | #define RCIP 0x08000000U | |
| 431 | #define RCCP 0x04000000U | |
| 432 | #define RFTP 0x00800000U | |
| 433 | #define PTRP 0x00100000U | |
| 434 | ||
| 435 | #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 | |
| 436 | #define TPCP 0x40000000U | |
| 437 | #define TNPP 0x20000000U | |
| 438 | #define TFTP 0x10000000U | |
| 439 | #define TCAP 0x08000000U | |
| 440 | #define TCIP 0x04000000U | |
| 441 | #define RCAP 0x02000000U | |
| 442 | #define PLUP 0x00800000U | |
| 443 | #define PLDN 0x00400000U | |
| 444 | #define OTDD 0x00200000U | |
| 445 | #define GTRP 0x00100000U | |
| 446 | #define RDPE 0x00040000U | |
| 447 | #define TDCE 0x00020000U | |
| 448 | #define TDUE 0x00010000U | |
| 449 | ||
| 450 | #define MC_INT_CAUSE 0x7518 | |
| 822dd8a8 | 451 | #define MC_P_INT_CAUSE 0x41318 |
| bbc02c7e DM |
452 | #define ECC_UE_INT_CAUSE 0x00000004U |
| 453 | #define ECC_CE_INT_CAUSE 0x00000002U | |
| 454 | #define PERR_INT_CAUSE 0x00000001U | |
| 455 | ||
| 456 | #define MC_ECC_STATUS 0x751c | |
| 822dd8a8 | 457 | #define MC_P_ECC_STATUS 0x4131c |
| bbc02c7e DM |
458 | #define ECC_CECNT_MASK 0xffff0000U |
| 459 | #define ECC_CECNT_SHIFT 16 | |
| 460 | #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT) | |
| 461 | #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT) | |
| 462 | #define ECC_UECNT_MASK 0x0000ffffU | |
| 463 | #define ECC_UECNT_SHIFT 0 | |
| 464 | #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT) | |
| 465 | #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT) | |
| 466 | ||
| 467 | #define MC_BIST_CMD 0x7600 | |
| 468 | #define START_BIST 0x80000000U | |
| 469 | #define BIST_CMD_GAP_MASK 0x0000ff00U | |
| 470 | #define BIST_CMD_GAP_SHIFT 8 | |
| 471 | #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT) | |
| 472 | #define BIST_OPCODE_MASK 0x00000003U | |
| 473 | #define BIST_OPCODE_SHIFT 0 | |
| 474 | #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT) | |
| 475 | ||
| 476 | #define MC_BIST_CMD_ADDR 0x7604 | |
| 477 | #define MC_BIST_CMD_LEN 0x7608 | |
| 478 | #define MC_BIST_DATA_PATTERN 0x760c | |
| 479 | #define BIST_DATA_TYPE_MASK 0x0000000fU | |
| 480 | #define BIST_DATA_TYPE_SHIFT 0 | |
| 481 | #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT) | |
| 482 | ||
| 483 | #define MC_BIST_STATUS_RDATA 0x7688 | |
| 484 | ||
| b2decadd SR |
485 | #define MA_EDRAM0_BAR 0x77c0 |
| 486 | #define MA_EDRAM1_BAR 0x77c4 | |
| 487 | #define EDRAM_SIZE_MASK 0xfffU | |
| 488 | #define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK) | |
| 489 | ||
| bbc02c7e DM |
490 | #define MA_EXT_MEMORY_BAR 0x77c8 |
| 491 | #define EXT_MEM_SIZE_MASK 0x00000fffU | |
| 492 | #define EXT_MEM_SIZE_SHIFT 0 | |
| 493 | #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) | |
| 494 | ||
| 495 | #define MA_TARGET_MEM_ENABLE 0x77d8 | |
| b2decadd | 496 | #define EXT_MEM1_ENABLE 0x00000010U |
| bbc02c7e DM |
497 | #define EXT_MEM_ENABLE 0x00000004U |
| 498 | #define EDRAM1_ENABLE 0x00000002U | |
| 499 | #define EDRAM0_ENABLE 0x00000001U | |
| 500 | ||
| 501 | #define MA_INT_CAUSE 0x77e0 | |
| 502 | #define MEM_PERR_INT_CAUSE 0x00000002U | |
| 503 | #define MEM_WRAP_INT_CAUSE 0x00000001U | |
| 504 | ||
| 505 | #define MA_INT_WRAP_STATUS 0x77e4 | |
| 506 | #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U | |
| 507 | #define MEM_WRAP_ADDRESS_SHIFT 4 | |
| 508 | #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT) | |
| 509 | #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU | |
| 510 | #define MEM_WRAP_CLIENT_NUM_SHIFT 0 | |
| 511 | #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) | |
| 636f9d37 | 512 | #define MA_PCIE_FW 0x30b8 |
| bbc02c7e | 513 | #define MA_PARITY_ERROR_STATUS 0x77f4 |
| 9bb59b96 | 514 | #define MA_PARITY_ERROR_STATUS2 0x7804 |
| bbc02c7e | 515 | |
| b2decadd | 516 | #define MA_EXT_MEMORY1_BAR 0x7808 |
| bbc02c7e DM |
517 | #define EDC_0_BASE_ADDR 0x7900 |
| 518 | ||
| 519 | #define EDC_BIST_CMD 0x7904 | |
| 520 | #define EDC_BIST_CMD_ADDR 0x7908 | |
| 521 | #define EDC_BIST_CMD_LEN 0x790c | |
| 522 | #define EDC_BIST_DATA_PATTERN 0x7910 | |
| 523 | #define EDC_BIST_STATUS_RDATA 0x7928 | |
| 524 | #define EDC_INT_CAUSE 0x7978 | |
| 525 | #define ECC_UE_PAR 0x00000020U | |
| 526 | #define ECC_CE_PAR 0x00000010U | |
| 527 | #define PERR_PAR_CAUSE 0x00000008U | |
| 528 | ||
| 529 | #define EDC_ECC_STATUS 0x797c | |
| 530 | ||
| 531 | #define EDC_1_BASE_ADDR 0x7980 | |
| 532 | ||
| 900a6596 DM |
533 | #define CIM_BOOT_CFG 0x7b00 |
| 534 | #define BOOTADDR_MASK 0xffffff00U | |
| 26f7cbc0 | 535 | #define UPCRST 0x1U |
| 900a6596 | 536 | |
| bbc02c7e DM |
537 | #define CIM_PF_MAILBOX_DATA 0x240 |
| 538 | #define CIM_PF_MAILBOX_CTRL 0x280 | |
| 539 | #define MBMSGVALID 0x00000008U | |
| 540 | #define MBINTREQ 0x00000004U | |
| 541 | #define MBOWNER_MASK 0x00000003U | |
| 542 | #define MBOWNER_SHIFT 0 | |
| 543 | #define MBOWNER(x) ((x) << MBOWNER_SHIFT) | |
| 544 | #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT) | |
| 545 | ||
| ce91a923 NKI |
546 | #define CIM_PF_HOST_INT_ENABLE 0x288 |
| 547 | #define MBMSGRDYINTEN(x) ((x) << 19) | |
| 548 | ||
| bbc02c7e DM |
549 | #define CIM_PF_HOST_INT_CAUSE 0x28c |
| 550 | #define MBMSGRDYINT 0x00080000U | |
| 551 | ||
| 552 | #define CIM_HOST_INT_CAUSE 0x7b2c | |
| 553 | #define TIEQOUTPARERRINT 0x00100000U | |
| 554 | #define TIEQINPARERRINT 0x00080000U | |
| 555 | #define MBHOSTPARERR 0x00040000U | |
| 556 | #define MBUPPARERR 0x00020000U | |
| 557 | #define IBQPARERR 0x0001f800U | |
| 558 | #define IBQTP0PARERR 0x00010000U | |
| 559 | #define IBQTP1PARERR 0x00008000U | |
| 560 | #define IBQULPPARERR 0x00004000U | |
| 561 | #define IBQSGELOPARERR 0x00002000U | |
| 562 | #define IBQSGEHIPARERR 0x00001000U | |
| 563 | #define IBQNCSIPARERR 0x00000800U | |
| 564 | #define OBQPARERR 0x000007e0U | |
| 565 | #define OBQULP0PARERR 0x00000400U | |
| 566 | #define OBQULP1PARERR 0x00000200U | |
| 567 | #define OBQULP2PARERR 0x00000100U | |
| 568 | #define OBQULP3PARERR 0x00000080U | |
| 569 | #define OBQSGEPARERR 0x00000040U | |
| 570 | #define OBQNCSIPARERR 0x00000020U | |
| 571 | #define PREFDROPINT 0x00000002U | |
| 572 | #define UPACCNONZERO 0x00000001U | |
| 573 | ||
| 574 | #define CIM_HOST_UPACC_INT_CAUSE 0x7b34 | |
| 575 | #define EEPROMWRINT 0x40000000U | |
| 576 | #define TIMEOUTMAINT 0x20000000U | |
| 577 | #define TIMEOUTINT 0x10000000U | |
| 578 | #define RSPOVRLOOKUPINT 0x08000000U | |
| 579 | #define REQOVRLOOKUPINT 0x04000000U | |
| 580 | #define BLKWRPLINT 0x02000000U | |
| 581 | #define BLKRDPLINT 0x01000000U | |
| 582 | #define SGLWRPLINT 0x00800000U | |
| 583 | #define SGLRDPLINT 0x00400000U | |
| 584 | #define BLKWRCTLINT 0x00200000U | |
| 585 | #define BLKRDCTLINT 0x00100000U | |
| 586 | #define SGLWRCTLINT 0x00080000U | |
| 587 | #define SGLRDCTLINT 0x00040000U | |
| 588 | #define BLKWREEPROMINT 0x00020000U | |
| 589 | #define BLKRDEEPROMINT 0x00010000U | |
| 590 | #define SGLWREEPROMINT 0x00008000U | |
| 591 | #define SGLRDEEPROMINT 0x00004000U | |
| 592 | #define BLKWRFLASHINT 0x00002000U | |
| 593 | #define BLKRDFLASHINT 0x00001000U | |
| 594 | #define SGLWRFLASHINT 0x00000800U | |
| 595 | #define SGLRDFLASHINT 0x00000400U | |
| 596 | #define BLKWRBOOTINT 0x00000200U | |
| 597 | #define BLKRDBOOTINT 0x00000100U | |
| 598 | #define SGLWRBOOTINT 0x00000080U | |
| 599 | #define SGLRDBOOTINT 0x00000040U | |
| 600 | #define ILLWRBEINT 0x00000020U | |
| 601 | #define ILLRDBEINT 0x00000010U | |
| 602 | #define ILLRDINT 0x00000008U | |
| 603 | #define ILLWRINT 0x00000004U | |
| 604 | #define ILLTRANSINT 0x00000002U | |
| 605 | #define RSVDSPACEINT 0x00000001U | |
| 606 | ||
| 607 | #define TP_OUT_CONFIG 0x7d04 | |
| 608 | #define VLANEXTENABLE_MASK 0x0000f000U | |
| 609 | #define VLANEXTENABLE_SHIFT 12 | |
| 610 | ||
| 13ee15d3 VP |
611 | #define TP_GLOBAL_CONFIG 0x7d08 |
| 612 | #define FIVETUPLELOOKUP_SHIFT 17 | |
| 613 | #define FIVETUPLELOOKUP_MASK 0x00060000U | |
| 614 | #define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT) | |
| 615 | #define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \ | |
| 616 | FIVETUPLELOOKUP_SHIFT) | |
| 617 | ||
| bbc02c7e DM |
618 | #define TP_PARA_REG2 0x7d68 |
| 619 | #define MAXRXDATA_MASK 0xffff0000U | |
| 620 | #define MAXRXDATA_SHIFT 16 | |
| 621 | #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) | |
| 622 | ||
| 623 | #define TP_TIMER_RESOLUTION 0x7d90 | |
| 624 | #define TIMERRESOLUTION_MASK 0x00ff0000U | |
| 625 | #define TIMERRESOLUTION_SHIFT 16 | |
| 626 | #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) | |
| 636f9d37 VP |
627 | #define DELAYEDACKRESOLUTION_MASK 0x000000ffU |
| 628 | #define DELAYEDACKRESOLUTION_SHIFT 0 | |
| 629 | #define DELAYEDACKRESOLUTION_GET(x) \ | |
| 630 | (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT) | |
| bbc02c7e DM |
631 | |
| 632 | #define TP_SHIFT_CNT 0x7dc0 | |
| 13ee15d3 VP |
633 | #define SYNSHIFTMAX_SHIFT 24 |
| 634 | #define SYNSHIFTMAX_MASK 0xff000000U | |
| 635 | #define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT) | |
| 636 | #define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \ | |
| 637 | SYNSHIFTMAX_SHIFT) | |
| 638 | #define RXTSHIFTMAXR1_SHIFT 20 | |
| 639 | #define RXTSHIFTMAXR1_MASK 0x00f00000U | |
| 640 | #define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT) | |
| 641 | #define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \ | |
| 642 | RXTSHIFTMAXR1_SHIFT) | |
| 643 | #define RXTSHIFTMAXR2_SHIFT 16 | |
| 644 | #define RXTSHIFTMAXR2_MASK 0x000f0000U | |
| 645 | #define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT) | |
| 646 | #define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \ | |
| 647 | RXTSHIFTMAXR2_SHIFT) | |
| 648 | #define PERSHIFTBACKOFFMAX_SHIFT 12 | |
| 649 | #define PERSHIFTBACKOFFMAX_MASK 0x0000f000U | |
| 650 | #define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT) | |
| 651 | #define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \ | |
| 652 | PERSHIFTBACKOFFMAX_SHIFT) | |
| 653 | #define PERSHIFTMAX_SHIFT 8 | |
| 654 | #define PERSHIFTMAX_MASK 0x00000f00U | |
| 655 | #define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT) | |
| 656 | #define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \ | |
| 657 | PERSHIFTMAX_SHIFT) | |
| 658 | #define KEEPALIVEMAXR1_SHIFT 4 | |
| 659 | #define KEEPALIVEMAXR1_MASK 0x000000f0U | |
| 660 | #define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT) | |
| 661 | #define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \ | |
| 662 | KEEPALIVEMAXR1_SHIFT) | |
| 663 | #define KEEPALIVEMAXR2_SHIFT 0 | |
| 664 | #define KEEPALIVEMAXR2_MASK 0x0000000fU | |
| 665 | #define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT) | |
| 666 | #define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \ | |
| 667 | KEEPALIVEMAXR2_SHIFT) | |
| bbc02c7e DM |
668 | |
| 669 | #define TP_CCTRL_TABLE 0x7ddc | |
| 670 | #define TP_MTU_TABLE 0x7de4 | |
| 671 | #define MTUINDEX_MASK 0xff000000U | |
| 672 | #define MTUINDEX_SHIFT 24 | |
| 673 | #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) | |
| 674 | #define MTUWIDTH_MASK 0x000f0000U | |
| 675 | #define MTUWIDTH_SHIFT 16 | |
| 676 | #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) | |
| 677 | #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) | |
| 678 | #define MTUVALUE_MASK 0x00003fffU | |
| 679 | #define MTUVALUE_SHIFT 0 | |
| 680 | #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) | |
| 681 | #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) | |
| 682 | ||
| 683 | #define TP_RSS_LKP_TABLE 0x7dec | |
| 684 | #define LKPTBLROWVLD 0x80000000U | |
| 685 | #define LKPTBLQUEUE1_MASK 0x000ffc00U | |
| 686 | #define LKPTBLQUEUE1_SHIFT 10 | |
| 687 | #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) | |
| 688 | #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) | |
| 689 | #define LKPTBLQUEUE0_MASK 0x000003ffU | |
| 690 | #define LKPTBLQUEUE0_SHIFT 0 | |
| 691 | #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) | |
| 692 | #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) | |
| 693 | ||
| 694 | #define TP_PIO_ADDR 0x7e40 | |
| 695 | #define TP_PIO_DATA 0x7e44 | |
| 696 | #define TP_MIB_INDEX 0x7e50 | |
| 697 | #define TP_MIB_DATA 0x7e54 | |
| 698 | #define TP_INT_CAUSE 0x7e74 | |
| 699 | #define FLMTXFLSTEMPTY 0x40000000U | |
| 700 | ||
| 13ee15d3 VP |
701 | #define TP_VLAN_PRI_MAP 0x140 |
| 702 | #define FRAGMENTATION_SHIFT 9 | |
| 703 | #define FRAGMENTATION_MASK 0x00000200U | |
| 704 | #define MPSHITTYPE_MASK 0x00000100U | |
| 705 | #define MACMATCH_MASK 0x00000080U | |
| 706 | #define ETHERTYPE_MASK 0x00000040U | |
| 707 | #define PROTOCOL_MASK 0x00000020U | |
| 708 | #define TOS_MASK 0x00000010U | |
| 709 | #define VLAN_MASK 0x00000008U | |
| 710 | #define VNIC_ID_MASK 0x00000004U | |
| 711 | #define PORT_MASK 0x00000002U | |
| 712 | #define FCOE_SHIFT 0 | |
| 713 | #define FCOE_MASK 0x00000001U | |
| 714 | ||
| bbc02c7e DM |
715 | #define TP_INGRESS_CONFIG 0x141 |
| 716 | #define VNIC 0x00000800U | |
| 717 | #define CSUM_HAS_PSEUDO_HDR 0x00000400U | |
| 718 | #define RM_OVLAN 0x00000200U | |
| 719 | #define LOOKUPEVERYPKT 0x00000100U | |
| 720 | ||
| 721 | #define TP_MIB_MAC_IN_ERR_0 0x0 | |
| 722 | #define TP_MIB_TCP_OUT_RST 0xc | |
| 723 | #define TP_MIB_TCP_IN_SEG_HI 0x10 | |
| 724 | #define TP_MIB_TCP_IN_SEG_LO 0x11 | |
| 725 | #define TP_MIB_TCP_OUT_SEG_HI 0x12 | |
| 726 | #define TP_MIB_TCP_OUT_SEG_LO 0x13 | |
| 727 | #define TP_MIB_TCP_RXT_SEG_HI 0x14 | |
| 728 | #define TP_MIB_TCP_RXT_SEG_LO 0x15 | |
| 729 | #define TP_MIB_TNL_CNG_DROP_0 0x18 | |
| 730 | #define TP_MIB_TCP_V6IN_ERR_0 0x28 | |
| 731 | #define TP_MIB_TCP_V6OUT_RST 0x2c | |
| 732 | #define TP_MIB_OFD_ARP_DROP 0x36 | |
| 733 | #define TP_MIB_TNL_DROP_0 0x44 | |
| 734 | #define TP_MIB_OFD_VLN_DROP_0 0x58 | |
| 735 | ||
| 736 | #define ULP_TX_INT_CAUSE 0x8dcc | |
| 737 | #define PBL_BOUND_ERR_CH3 0x80000000U | |
| 738 | #define PBL_BOUND_ERR_CH2 0x40000000U | |
| 739 | #define PBL_BOUND_ERR_CH1 0x20000000U | |
| 740 | #define PBL_BOUND_ERR_CH0 0x10000000U | |
| 741 | ||
| 742 | #define PM_RX_INT_CAUSE 0x8fdc | |
| 743 | #define ZERO_E_CMD_ERROR 0x00400000U | |
| 744 | #define PMRX_FRAMING_ERROR 0x003ffff0U | |
| 745 | #define OCSPI_PAR_ERROR 0x00000008U | |
| 746 | #define DB_OPTIONS_PAR_ERROR 0x00000004U | |
| 747 | #define IESPI_PAR_ERROR 0x00000002U | |
| 748 | #define E_PCMD_PAR_ERROR 0x00000001U | |
| 749 | ||
| 750 | #define PM_TX_INT_CAUSE 0x8ffc | |
| 751 | #define PCMD_LEN_OVFL0 0x80000000U | |
| 752 | #define PCMD_LEN_OVFL1 0x40000000U | |
| 753 | #define PCMD_LEN_OVFL2 0x20000000U | |
| 754 | #define ZERO_C_CMD_ERROR 0x10000000U | |
| 755 | #define PMTX_FRAMING_ERROR 0x0ffffff0U | |
| 756 | #define OESPI_PAR_ERROR 0x00000008U | |
| 757 | #define ICSPI_PAR_ERROR 0x00000002U | |
| 758 | #define C_PCMD_PAR_ERROR 0x00000001U | |
| 759 | ||
| 760 | #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 | |
| 761 | #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 | |
| 762 | #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 | |
| 763 | #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c | |
| 764 | #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 | |
| 765 | #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 | |
| 766 | #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 | |
| 767 | #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c | |
| 768 | #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 | |
| 769 | #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 | |
| 770 | #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 | |
| 771 | #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c | |
| 772 | #define MPS_PORT_STAT_TX_PORT_64B_L 0x430 | |
| 773 | #define MPS_PORT_STAT_TX_PORT_64B_H 0x434 | |
| 774 | #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 | |
| 775 | #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c | |
| 776 | #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 | |
| 777 | #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 | |
| 778 | #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 | |
| 779 | #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c | |
| 780 | #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 | |
| 781 | #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 | |
| 782 | #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 | |
| 783 | #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c | |
| 784 | #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 | |
| 785 | #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 | |
| 786 | #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 | |
| 787 | #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c | |
| 788 | #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 | |
| 789 | #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 | |
| 790 | #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 | |
| 791 | #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c | |
| 792 | #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 | |
| 793 | #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 | |
| 794 | #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 | |
| 795 | #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c | |
| 796 | #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 | |
| 797 | #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 | |
| 798 | #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 | |
| 799 | #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c | |
| 800 | #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 | |
| 801 | #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 | |
| 802 | #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 | |
| 803 | #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac | |
| 804 | #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 | |
| 805 | #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 | |
| 806 | #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 | |
| 807 | #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 | |
| 808 | #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 | |
| 809 | #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc | |
| 810 | #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 | |
| 811 | #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 | |
| 812 | #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 | |
| 813 | #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc | |
| 814 | #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 | |
| 815 | #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 | |
| 816 | #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 | |
| 817 | #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec | |
| 818 | #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 | |
| 819 | #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 | |
| 820 | #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 | |
| 821 | #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc | |
| 822 | #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 | |
| 823 | #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 | |
| 824 | #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 | |
| 825 | #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c | |
| 826 | #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 | |
| 827 | #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 | |
| 828 | #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 | |
| 829 | #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c | |
| 830 | #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 | |
| 831 | #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 | |
| 832 | #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 | |
| 833 | #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 | |
| 834 | #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 | |
| 835 | #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 | |
| 836 | #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c | |
| 837 | #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 | |
| 838 | #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 | |
| 839 | #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 | |
| 840 | #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c | |
| 841 | #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 | |
| 842 | #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 | |
| 843 | #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 | |
| 844 | #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c | |
| 845 | #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 | |
| 846 | #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 | |
| 847 | #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 | |
| 848 | #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c | |
| 849 | #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 | |
| 850 | #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 | |
| 851 | #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 | |
| 852 | #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c | |
| 853 | #define MPS_PORT_STAT_RX_PORT_64B_L 0x590 | |
| 854 | #define MPS_PORT_STAT_RX_PORT_64B_H 0x594 | |
| 855 | #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 | |
| 856 | #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c | |
| 857 | #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 | |
| 858 | #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 | |
| 859 | #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 | |
| 860 | #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac | |
| 861 | #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 | |
| 862 | #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 | |
| 863 | #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 | |
| 864 | #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc | |
| 865 | #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 | |
| 866 | #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 | |
| 867 | #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 | |
| 868 | #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc | |
| 869 | #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 | |
| 870 | #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 | |
| 871 | #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 | |
| 872 | #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc | |
| 873 | #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 | |
| 874 | #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 | |
| 875 | #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 | |
| 876 | #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec | |
| 877 | #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 | |
| 878 | #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 | |
| 879 | #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 | |
| 880 | #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc | |
| 881 | #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 | |
| 882 | #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 | |
| 883 | #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 | |
| 884 | #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c | |
| 885 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 | |
| 886 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 | |
| b2decadd SR |
887 | #define MAC_PORT_CFG2 0x818 |
| 888 | #define MAC_PORT_MAGIC_MACID_LO 0x824 | |
| 889 | #define MAC_PORT_MAGIC_MACID_HI 0x828 | |
| 890 | #define MAC_PORT_EPIO_DATA0 0x8c0 | |
| 891 | #define MAC_PORT_EPIO_DATA1 0x8c4 | |
| 892 | #define MAC_PORT_EPIO_DATA2 0x8c8 | |
| 893 | #define MAC_PORT_EPIO_DATA3 0x8cc | |
| 894 | #define MAC_PORT_EPIO_OP 0x8d0 | |
| 895 | ||
| bbc02c7e DM |
896 | #define MPS_CMN_CTL 0x9000 |
| 897 | #define NUMPORTS_MASK 0x00000003U | |
| 898 | #define NUMPORTS_SHIFT 0 | |
| 899 | #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) | |
| 900 | ||
| 901 | #define MPS_INT_CAUSE 0x9008 | |
| 902 | #define STATINT 0x00000020U | |
| 903 | #define TXINT 0x00000010U | |
| 904 | #define RXINT 0x00000008U | |
| 905 | #define TRCINT 0x00000004U | |
| 906 | #define CLSINT 0x00000002U | |
| 907 | #define PLINT 0x00000001U | |
| 908 | ||
| 909 | #define MPS_TX_INT_CAUSE 0x9408 | |
| 910 | #define PORTERR 0x00010000U | |
| 911 | #define FRMERR 0x00008000U | |
| 912 | #define SECNTERR 0x00004000U | |
| 913 | #define BUBBLE 0x00002000U | |
| 914 | #define TXDESCFIFO 0x00001e00U | |
| 915 | #define TXDATAFIFO 0x000001e0U | |
| 916 | #define NCSIFIFO 0x00000010U | |
| 917 | #define TPFIFO 0x0000000fU | |
| 918 | ||
| 919 | #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 | |
| 920 | #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 | |
| 921 | #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c | |
| 922 | ||
| 923 | #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 | |
| 924 | #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 | |
| 925 | #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 | |
| 926 | #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c | |
| 927 | #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 | |
| 928 | #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 | |
| 929 | #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 | |
| 930 | #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c | |
| 931 | #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 | |
| 932 | #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 | |
| 933 | #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 | |
| 934 | #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c | |
| 935 | #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 | |
| 936 | #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 | |
| 937 | #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 | |
| 938 | #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c | |
| 939 | #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 | |
| 940 | #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 | |
| 941 | #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 | |
| 942 | #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c | |
| 943 | #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 | |
| 944 | #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 | |
| 945 | #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 | |
| 946 | #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c | |
| 947 | #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 | |
| 948 | #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 | |
| 949 | #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 | |
| 950 | #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac | |
| 951 | #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 | |
| 952 | #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 | |
| 953 | #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 | |
| 954 | #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc | |
| 955 | #define MPS_TRC_CFG 0x9800 | |
| 956 | #define TRCFIFOEMPTY 0x00000010U | |
| 957 | #define TRCIGNOREDROPINPUT 0x00000008U | |
| 958 | #define TRCKEEPDUPLICATES 0x00000004U | |
| 959 | #define TRCEN 0x00000002U | |
| 960 | #define TRCMULTIFILTER 0x00000001U | |
| 961 | ||
| 962 | #define MPS_TRC_RSS_CONTROL 0x9808 | |
| 9bb59b96 | 963 | #define MPS_T5_TRC_RSS_CONTROL 0xa00c |
| bbc02c7e DM |
964 | #define RSSCONTROL_MASK 0x00ff0000U |
| 965 | #define RSSCONTROL_SHIFT 16 | |
| 966 | #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) | |
| 967 | #define QUEUENUMBER_MASK 0x0000ffffU | |
| 968 | #define QUEUENUMBER_SHIFT 0 | |
| 969 | #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) | |
| 970 | ||
| 971 | #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 | |
| 972 | #define TFINVERTMATCH 0x01000000U | |
| 973 | #define TFPKTTOOLARGE 0x00800000U | |
| 974 | #define TFEN 0x00400000U | |
| 975 | #define TFPORT_MASK 0x003c0000U | |
| 976 | #define TFPORT_SHIFT 18 | |
| 977 | #define TFPORT(x) ((x) << TFPORT_SHIFT) | |
| 978 | #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) | |
| 979 | #define TFDROP 0x00020000U | |
| 980 | #define TFSOPEOPERR 0x00010000U | |
| 981 | #define TFLENGTH_MASK 0x00001f00U | |
| 982 | #define TFLENGTH_SHIFT 8 | |
| 983 | #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) | |
| 984 | #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) | |
| 985 | #define TFOFFSET_MASK 0x0000001fU | |
| 986 | #define TFOFFSET_SHIFT 0 | |
| 987 | #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) | |
| 988 | #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) | |
| 989 | ||
| 990 | #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 | |
| 991 | #define TFMINPKTSIZE_MASK 0x01ff0000U | |
| 992 | #define TFMINPKTSIZE_SHIFT 16 | |
| 993 | #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) | |
| 994 | #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) | |
| 995 | #define TFCAPTUREMAX_MASK 0x00003fffU | |
| 996 | #define TFCAPTUREMAX_SHIFT 0 | |
| 997 | #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) | |
| 998 | #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) | |
| 999 | ||
| 1000 | #define MPS_TRC_INT_CAUSE 0x985c | |
| 1001 | #define MISCPERR 0x00000100U | |
| 1002 | #define PKTFIFO 0x000000f0U | |
| 1003 | #define FILTMEM 0x0000000fU | |
| 1004 | ||
| 1005 | #define MPS_TRC_FILTER0_MATCH 0x9c00 | |
| 1006 | #define MPS_TRC_FILTER0_DONT_CARE 0x9c80 | |
| 1007 | #define MPS_TRC_FILTER1_MATCH 0x9d00 | |
| 1008 | #define MPS_CLS_INT_CAUSE 0xd028 | |
| 1009 | #define PLERRENB 0x00000008U | |
| 1010 | #define HASHSRAM 0x00000004U | |
| 1011 | #define MATCHTCAM 0x00000002U | |
| 1012 | #define MATCHSRAM 0x00000001U | |
| 1013 | ||
| 1014 | #define MPS_RX_PERR_INT_CAUSE 0x11074 | |
| 1015 | ||
| 1016 | #define CPL_INTR_CAUSE 0x19054 | |
| 1017 | #define CIM_OP_MAP_PERR 0x00000020U | |
| 1018 | #define CIM_OVFL_ERROR 0x00000010U | |
| 1019 | #define TP_FRAMING_ERROR 0x00000008U | |
| 1020 | #define SGE_FRAMING_ERROR 0x00000004U | |
| 1021 | #define CIM_FRAMING_ERROR 0x00000002U | |
| 1022 | #define ZERO_SWITCH_ERROR 0x00000001U | |
| 1023 | ||
| 1024 | #define SMB_INT_CAUSE 0x19090 | |
| 1025 | #define MSTTXFIFOPARINT 0x00200000U | |
| 1026 | #define MSTRXFIFOPARINT 0x00100000U | |
| 1027 | #define SLVFIFOPARINT 0x00080000U | |
| 1028 | ||
| 1029 | #define ULP_RX_INT_CAUSE 0x19158 | |
| 1030 | #define ULP_RX_ISCSI_TAGMASK 0x19164 | |
| 1031 | #define ULP_RX_ISCSI_PSZ 0x19168 | |
| 1032 | #define HPZ3_MASK 0x0f000000U | |
| 1033 | #define HPZ3_SHIFT 24 | |
| 1034 | #define HPZ3(x) ((x) << HPZ3_SHIFT) | |
| 1035 | #define HPZ2_MASK 0x000f0000U | |
| 1036 | #define HPZ2_SHIFT 16 | |
| 1037 | #define HPZ2(x) ((x) << HPZ2_SHIFT) | |
| 1038 | #define HPZ1_MASK 0x00000f00U | |
| 1039 | #define HPZ1_SHIFT 8 | |
| 1040 | #define HPZ1(x) ((x) << HPZ1_SHIFT) | |
| 1041 | #define HPZ0_MASK 0x0000000fU | |
| 1042 | #define HPZ0_SHIFT 0 | |
| 1043 | #define HPZ0(x) ((x) << HPZ0_SHIFT) | |
| 1044 | ||
| 1045 | #define ULP_RX_TDDP_PSZ 0x19178 | |
| 1046 | ||
| 1047 | #define SF_DATA 0x193f8 | |
| 1048 | #define SF_OP 0x193fc | |
| ce91a923 | 1049 | #define SF_BUSY 0x80000000U |
| bbc02c7e DM |
1050 | #define SF_LOCK 0x00000010U |
| 1051 | #define SF_CONT 0x00000008U | |
| 1052 | #define BYTECNT_MASK 0x00000006U | |
| 1053 | #define BYTECNT_SHIFT 1 | |
| 1054 | #define BYTECNT(x) ((x) << BYTECNT_SHIFT) | |
| 1055 | #define OP_WR 0x00000001U | |
| 1056 | ||
| 1057 | #define PL_PF_INT_CAUSE 0x3c0 | |
| 1058 | #define PFSW 0x00000008U | |
| 1059 | #define PFSGE 0x00000004U | |
| 1060 | #define PFCIM 0x00000002U | |
| 1061 | #define PFMPS 0x00000001U | |
| 1062 | ||
| 1063 | #define PL_PF_INT_ENABLE 0x3c4 | |
| 1064 | #define PL_PF_CTL 0x3c8 | |
| 1065 | #define SWINT 0x00000001U | |
| 1066 | ||
| 1067 | #define PL_WHOAMI 0x19400 | |
| 1068 | #define SOURCEPF_MASK 0x00000700U | |
| 1069 | #define SOURCEPF_SHIFT 8 | |
| 1070 | #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT) | |
| 1071 | #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT) | |
| 1072 | #define ISVF 0x00000080U | |
| 1073 | #define VFID_MASK 0x0000007fU | |
| 1074 | #define VFID_SHIFT 0 | |
| 1075 | #define VFID(x) ((x) << VFID_SHIFT) | |
| 1076 | #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT) | |
| 1077 | ||
| 1078 | #define PL_INT_CAUSE 0x1940c | |
| 1079 | #define ULP_TX 0x08000000U | |
| 1080 | #define SGE 0x04000000U | |
| 1081 | #define HMA 0x02000000U | |
| 1082 | #define CPL_SWITCH 0x01000000U | |
| 1083 | #define ULP_RX 0x00800000U | |
| 1084 | #define PM_RX 0x00400000U | |
| 1085 | #define PM_TX 0x00200000U | |
| 1086 | #define MA 0x00100000U | |
| 1087 | #define TP 0x00080000U | |
| 1088 | #define LE 0x00040000U | |
| 1089 | #define EDC1 0x00020000U | |
| 1090 | #define EDC0 0x00010000U | |
| 1091 | #define MC 0x00008000U | |
| 1092 | #define PCIE 0x00004000U | |
| 1093 | #define PMU 0x00002000U | |
| 1094 | #define XGMAC_KR1 0x00001000U | |
| 1095 | #define XGMAC_KR0 0x00000800U | |
| 1096 | #define XGMAC1 0x00000400U | |
| 1097 | #define XGMAC0 0x00000200U | |
| 1098 | #define SMB 0x00000100U | |
| 1099 | #define SF 0x00000080U | |
| 1100 | #define PL 0x00000040U | |
| 1101 | #define NCSI 0x00000020U | |
| 1102 | #define MPS 0x00000010U | |
| 1103 | #define MI 0x00000008U | |
| 1104 | #define DBG 0x00000004U | |
| 1105 | #define I2CM 0x00000002U | |
| 1106 | #define CIM 0x00000001U | |
| 1107 | ||
| 822dd8a8 | 1108 | #define MC1 0x31 |
| ce91a923 | 1109 | #define PL_INT_ENABLE 0x19410 |
| bbc02c7e DM |
1110 | #define PL_INT_MAP0 0x19414 |
| 1111 | #define PL_RST 0x19428 | |
| 1112 | #define PIORST 0x00000002U | |
| 1113 | #define PIORSTMODE 0x00000001U | |
| 1114 | ||
| 1115 | #define PL_PL_INT_CAUSE 0x19430 | |
| 1116 | #define FATALPERR 0x00000010U | |
| 1117 | #define PERRVFID 0x00000001U | |
| 1118 | ||
| 1119 | #define PL_REV 0x1943c | |
| 1120 | ||
| d14807dd HS |
1121 | #define S_REV 0 |
| 1122 | #define M_REV 0xfU | |
| 1123 | #define V_REV(x) ((x) << S_REV) | |
| 1124 | #define G_REV(x) (((x) >> S_REV) & M_REV) | |
| 1125 | ||
| bbc02c7e DM |
1126 | #define LE_DB_CONFIG 0x19c04 |
| 1127 | #define HASHEN 0x00100000U | |
| 1128 | ||
| 1129 | #define LE_DB_SERVER_INDEX 0x19c18 | |
| 1130 | #define LE_DB_ACT_CNT_IPV4 0x19c20 | |
| 1131 | #define LE_DB_ACT_CNT_IPV6 0x19c24 | |
| 1132 | ||
| 1133 | #define LE_DB_INT_CAUSE 0x19c3c | |
| 1134 | #define REQQPARERR 0x00010000U | |
| 1135 | #define UNKNOWNCMD 0x00008000U | |
| 1136 | #define PARITYERR 0x00000040U | |
| 1137 | #define LIPMISS 0x00000020U | |
| 1138 | #define LIP0 0x00000010U | |
| 1139 | ||
| 1140 | #define LE_DB_TID_HASHBASE 0x19df8 | |
| 1141 | ||
| 1142 | #define NCSI_INT_CAUSE 0x1a0d8 | |
| 1143 | #define CIM_DM_PRTY_ERR 0x00000100U | |
| 1144 | #define MPS_DM_PRTY_ERR 0x00000080U | |
| 1145 | #define TXFIFO_PRTY_ERR 0x00000002U | |
| 1146 | #define RXFIFO_PRTY_ERR 0x00000001U | |
| 1147 | ||
| 1148 | #define XGMAC_PORT_CFG2 0x1018 | |
| 1149 | #define PATEN 0x00040000U | |
| 1150 | #define MAGICEN 0x00020000U | |
| 1151 | ||
| 1152 | #define XGMAC_PORT_MAGIC_MACID_LO 0x1024 | |
| 1153 | #define XGMAC_PORT_MAGIC_MACID_HI 0x1028 | |
| 1154 | ||
| 1155 | #define XGMAC_PORT_EPIO_DATA0 0x10c0 | |
| 1156 | #define XGMAC_PORT_EPIO_DATA1 0x10c4 | |
| 1157 | #define XGMAC_PORT_EPIO_DATA2 0x10c8 | |
| 1158 | #define XGMAC_PORT_EPIO_DATA3 0x10cc | |
| 1159 | #define XGMAC_PORT_EPIO_OP 0x10d0 | |
| 1160 | #define EPIOWR 0x00000100U | |
| 1161 | #define ADDRESS_MASK 0x000000ffU | |
| 1162 | #define ADDRESS_SHIFT 0 | |
| 1163 | #define ADDRESS(x) ((x) << ADDRESS_SHIFT) | |
| 1164 | ||
| b2decadd | 1165 | #define MAC_PORT_INT_CAUSE 0x8dc |
| bbc02c7e | 1166 | #define XGMAC_PORT_INT_CAUSE 0x10dc |
| dca4faeb VP |
1167 | |
| 1168 | #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 | |
| 1169 | ||
| 1170 | #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34 | |
| 1171 | ||
| 1172 | #define S_TX_MOD_QUEUE_REQ_MAP 0 | |
| 1173 | #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU | |
| 1174 | #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) | |
| 1175 | ||
| 1176 | #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30 | |
| 1177 | ||
| 1178 | #define S_TX_MODQ_WEIGHT3 24 | |
| 1179 | #define M_TX_MODQ_WEIGHT3 0xffU | |
| 1180 | #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3) | |
| 1181 | ||
| 1182 | #define S_TX_MODQ_WEIGHT2 16 | |
| 1183 | #define M_TX_MODQ_WEIGHT2 0xffU | |
| 1184 | #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2) | |
| 1185 | ||
| 1186 | #define S_TX_MODQ_WEIGHT1 8 | |
| 1187 | #define M_TX_MODQ_WEIGHT1 0xffU | |
| 1188 | #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1) | |
| 1189 | ||
| 1190 | #define S_TX_MODQ_WEIGHT0 0 | |
| 1191 | #define M_TX_MODQ_WEIGHT0 0xffU | |
| 1192 | #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0) | |
| 1193 | ||
| 1194 | #define A_TP_TX_SCHED_HDR 0x23 | |
| 1195 | ||
| 1196 | #define A_TP_TX_SCHED_FIFO 0x24 | |
| 1197 | ||
| 1198 | #define A_TP_TX_SCHED_PCMD 0x25 | |
| 1199 | ||
| dcf7b6f5 KS |
1200 | #define S_VNIC 11 |
| 1201 | #define V_VNIC(x) ((x) << S_VNIC) | |
| 1202 | #define F_VNIC V_VNIC(1U) | |
| 1203 | ||
| 1204 | #define S_FRAGMENTATION 9 | |
| 1205 | #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION) | |
| 1206 | #define F_FRAGMENTATION V_FRAGMENTATION(1U) | |
| 1207 | ||
| 1208 | #define S_MPSHITTYPE 8 | |
| 1209 | #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE) | |
| 1210 | #define F_MPSHITTYPE V_MPSHITTYPE(1U) | |
| 1211 | ||
| 1212 | #define S_MACMATCH 7 | |
| 1213 | #define V_MACMATCH(x) ((x) << S_MACMATCH) | |
| 1214 | #define F_MACMATCH V_MACMATCH(1U) | |
| 1215 | ||
| 1216 | #define S_ETHERTYPE 6 | |
| 1217 | #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE) | |
| 1218 | #define F_ETHERTYPE V_ETHERTYPE(1U) | |
| 1219 | ||
| 7c89e555 KS |
1220 | #define S_PROTOCOL 5 |
| 1221 | #define V_PROTOCOL(x) ((x) << S_PROTOCOL) | |
| 1222 | #define F_PROTOCOL V_PROTOCOL(1U) | |
| 1223 | ||
| dcf7b6f5 KS |
1224 | #define S_TOS 4 |
| 1225 | #define V_TOS(x) ((x) << S_TOS) | |
| 1226 | #define F_TOS V_TOS(1U) | |
| 1227 | ||
| 1228 | #define S_VLAN 3 | |
| 1229 | #define V_VLAN(x) ((x) << S_VLAN) | |
| 1230 | #define F_VLAN V_VLAN(1U) | |
| 1231 | ||
| 1232 | #define S_VNIC_ID 2 | |
| 1233 | #define V_VNIC_ID(x) ((x) << S_VNIC_ID) | |
| 1234 | #define F_VNIC_ID V_VNIC_ID(1U) | |
| 1235 | ||
| 5be78ee9 | 1236 | #define S_PORT 1 |
| 793dad94 VP |
1237 | #define V_PORT(x) ((x) << S_PORT) |
| 1238 | #define F_PORT V_PORT(1U) | |
| 5be78ee9 | 1239 | |
| dcf7b6f5 KS |
1240 | #define S_FCOE 0 |
| 1241 | #define V_FCOE(x) ((x) << S_FCOE) | |
| 1242 | #define F_FCOE V_FCOE(1U) | |
| 1243 | ||
| b2decadd SR |
1244 | #define NUM_MPS_CLS_SRAM_L_INSTANCES 336 |
| 1245 | #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 | |
| 1246 | ||
| 1247 | #define T5_PORT0_BASE 0x30000 | |
| 1248 | #define T5_PORT_STRIDE 0x4000 | |
| 1249 | #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) | |
| 1250 | #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) | |
| 1251 | ||
| 1252 | #define MC_0_BASE_ADDR 0x40000 | |
| 1253 | #define MC_1_BASE_ADDR 0x48000 | |
| 1254 | #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) | |
| 1255 | #define MC_REG(reg, idx) (reg + MC_STRIDE * idx) | |
| 1256 | ||
| 1257 | #define MC_P_BIST_CMD 0x41400 | |
| 1258 | #define MC_P_BIST_CMD_ADDR 0x41404 | |
| 1259 | #define MC_P_BIST_CMD_LEN 0x41408 | |
| 1260 | #define MC_P_BIST_DATA_PATTERN 0x4140c | |
| 1261 | #define MC_P_BIST_STATUS_RDATA 0x41488 | |
| 1262 | #define EDC_T50_BASE_ADDR 0x50000 | |
| 1263 | #define EDC_H_BIST_CMD 0x50004 | |
| 1264 | #define EDC_H_BIST_CMD_ADDR 0x50008 | |
| 1265 | #define EDC_H_BIST_CMD_LEN 0x5000c | |
| 1266 | #define EDC_H_BIST_DATA_PATTERN 0x50010 | |
| 1267 | #define EDC_H_BIST_STATUS_RDATA 0x50028 | |
| 1268 | ||
| 1269 | #define EDC_T51_BASE_ADDR 0x50800 | |
| 1270 | #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) | |
| 1271 | #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) | |
| 1272 | ||
| 70ee3666 HS |
1273 | #define A_PL_VF_REV 0x4 |
| 1274 | #define A_PL_VF_WHOAMI 0x0 | |
| 1275 | #define A_PL_VF_REVISION 0x8 | |
| 1276 | ||
| 1277 | #define S_CHIPID 4 | |
| 1278 | #define M_CHIPID 0xfU | |
| 1279 | #define V_CHIPID(x) ((x) << S_CHIPID) | |
| 1280 | #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID) | |
| 1281 | ||
| dcf7b6f5 KS |
1282 | /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the |
| 1283 | * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP | |
| 1284 | * selects for a particular field being present. These fields, when present | |
| 1285 | * in the Compressed Filter Tuple, have the following widths in bits. | |
| 1286 | */ | |
| 1287 | #define W_FT_FCOE 1 | |
| 1288 | #define W_FT_PORT 3 | |
| 1289 | #define W_FT_VNIC_ID 17 | |
| 1290 | #define W_FT_VLAN 17 | |
| 1291 | #define W_FT_TOS 8 | |
| 1292 | #define W_FT_PROTOCOL 8 | |
| 1293 | #define W_FT_ETHERTYPE 16 | |
| 1294 | #define W_FT_MACMATCH 9 | |
| 1295 | #define W_FT_MPSHITTYPE 3 | |
| 1296 | #define W_FT_FRAGMENTATION 1 | |
| 1297 | ||
| 1298 | /* Some of the Compressed Filter Tuple fields have internal structure. These | |
| 1299 | * bit shifts/masks describe those structures. All shifts are relative to the | |
| 1300 | * base position of the fields within the Compressed Filter Tuple | |
| 1301 | */ | |
| 1302 | #define S_FT_VLAN_VLD 16 | |
| 1303 | #define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD) | |
| 1304 | #define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U) | |
| 1305 | ||
| 1306 | #define S_FT_VNID_ID_VF 0 | |
| 1307 | #define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF) | |
| 1308 | ||
| 1309 | #define S_FT_VNID_ID_PF 7 | |
| 1310 | #define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) | |
| 1311 | ||
| 1312 | #define S_FT_VNID_ID_VLD 16 | |
| 1313 | #define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) | |
| 1314 | ||
| bbc02c7e | 1315 | #endif /* __T4_REGS_H */ |