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56d36be4 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
4 | * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/init.h> | |
36 | #include <linux/delay.h> | |
37 | #include "cxgb4.h" | |
38 | #include "t4_regs.h" | |
39 | #include "t4fw_api.h" | |
40 | ||
41 | /** | |
42 | * t4_wait_op_done_val - wait until an operation is completed | |
43 | * @adapter: the adapter performing the operation | |
44 | * @reg: the register to check for completion | |
45 | * @mask: a single-bit field within @reg that indicates completion | |
46 | * @polarity: the value of the field when the operation is completed | |
47 | * @attempts: number of check iterations | |
48 | * @delay: delay in usecs between iterations | |
49 | * @valp: where to store the value of the register at completion time | |
50 | * | |
51 | * Wait until an operation is completed by checking a bit in a register | |
52 | * up to @attempts times. If @valp is not NULL the value of the register | |
53 | * at the time it indicated completion is stored there. Returns 0 if the | |
54 | * operation completes and -EAGAIN otherwise. | |
55 | */ | |
de498c89 RD |
56 | static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, |
57 | int polarity, int attempts, int delay, u32 *valp) | |
56d36be4 DM |
58 | { |
59 | while (1) { | |
60 | u32 val = t4_read_reg(adapter, reg); | |
61 | ||
62 | if (!!(val & mask) == polarity) { | |
63 | if (valp) | |
64 | *valp = val; | |
65 | return 0; | |
66 | } | |
67 | if (--attempts == 0) | |
68 | return -EAGAIN; | |
69 | if (delay) | |
70 | udelay(delay); | |
71 | } | |
72 | } | |
73 | ||
74 | static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, | |
75 | int polarity, int attempts, int delay) | |
76 | { | |
77 | return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, | |
78 | delay, NULL); | |
79 | } | |
80 | ||
81 | /** | |
82 | * t4_set_reg_field - set a register field to a value | |
83 | * @adapter: the adapter to program | |
84 | * @addr: the register address | |
85 | * @mask: specifies the portion of the register to modify | |
86 | * @val: the new value for the register field | |
87 | * | |
88 | * Sets a register field specified by the supplied mask to the | |
89 | * given value. | |
90 | */ | |
91 | void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, | |
92 | u32 val) | |
93 | { | |
94 | u32 v = t4_read_reg(adapter, addr) & ~mask; | |
95 | ||
96 | t4_write_reg(adapter, addr, v | val); | |
97 | (void) t4_read_reg(adapter, addr); /* flush */ | |
98 | } | |
99 | ||
100 | /** | |
101 | * t4_read_indirect - read indirectly addressed registers | |
102 | * @adap: the adapter | |
103 | * @addr_reg: register holding the indirect address | |
104 | * @data_reg: register holding the value of the indirect register | |
105 | * @vals: where the read register values are stored | |
106 | * @nregs: how many indirect registers to read | |
107 | * @start_idx: index of first indirect register to read | |
108 | * | |
109 | * Reads registers that are accessed indirectly through an address/data | |
110 | * register pair. | |
111 | */ | |
de498c89 RD |
112 | static void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, |
113 | unsigned int data_reg, u32 *vals, | |
114 | unsigned int nregs, unsigned int start_idx) | |
56d36be4 DM |
115 | { |
116 | while (nregs--) { | |
117 | t4_write_reg(adap, addr_reg, start_idx); | |
118 | *vals++ = t4_read_reg(adap, data_reg); | |
119 | start_idx++; | |
120 | } | |
121 | } | |
122 | ||
56d36be4 DM |
123 | /* |
124 | * Get the reply to a mailbox command and store it in @rpl in big-endian order. | |
125 | */ | |
126 | static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, | |
127 | u32 mbox_addr) | |
128 | { | |
129 | for ( ; nflit; nflit--, mbox_addr += 8) | |
130 | *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); | |
131 | } | |
132 | ||
133 | /* | |
134 | * Handle a FW assertion reported in a mailbox. | |
135 | */ | |
136 | static void fw_asrt(struct adapter *adap, u32 mbox_addr) | |
137 | { | |
138 | struct fw_debug_cmd asrt; | |
139 | ||
140 | get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); | |
141 | dev_alert(adap->pdev_dev, | |
142 | "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", | |
143 | asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line), | |
144 | ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y)); | |
145 | } | |
146 | ||
147 | static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg) | |
148 | { | |
149 | dev_err(adap->pdev_dev, | |
150 | "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, | |
151 | (unsigned long long)t4_read_reg64(adap, data_reg), | |
152 | (unsigned long long)t4_read_reg64(adap, data_reg + 8), | |
153 | (unsigned long long)t4_read_reg64(adap, data_reg + 16), | |
154 | (unsigned long long)t4_read_reg64(adap, data_reg + 24), | |
155 | (unsigned long long)t4_read_reg64(adap, data_reg + 32), | |
156 | (unsigned long long)t4_read_reg64(adap, data_reg + 40), | |
157 | (unsigned long long)t4_read_reg64(adap, data_reg + 48), | |
158 | (unsigned long long)t4_read_reg64(adap, data_reg + 56)); | |
159 | } | |
160 | ||
161 | /** | |
162 | * t4_wr_mbox_meat - send a command to FW through the given mailbox | |
163 | * @adap: the adapter | |
164 | * @mbox: index of the mailbox to use | |
165 | * @cmd: the command to write | |
166 | * @size: command length in bytes | |
167 | * @rpl: where to optionally store the reply | |
168 | * @sleep_ok: if true we may sleep while awaiting command completion | |
169 | * | |
170 | * Sends the given command to FW through the selected mailbox and waits | |
171 | * for the FW to execute the command. If @rpl is not %NULL it is used to | |
172 | * store the FW's reply to the command. The command and its optional | |
173 | * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms | |
174 | * to respond. @sleep_ok determines whether we may sleep while awaiting | |
175 | * the response. If sleeping is allowed we use progressive backoff | |
176 | * otherwise we spin. | |
177 | * | |
178 | * The return value is 0 on success or a negative errno on failure. A | |
179 | * failure can happen either because we are not able to execute the | |
180 | * command or FW executes it but signals an error. In the latter case | |
181 | * the return value is the error code indicated by FW (negated). | |
182 | */ | |
183 | int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, | |
184 | void *rpl, bool sleep_ok) | |
185 | { | |
005b5717 | 186 | static const int delay[] = { |
56d36be4 DM |
187 | 1, 1, 3, 5, 10, 10, 20, 50, 100, 200 |
188 | }; | |
189 | ||
190 | u32 v; | |
191 | u64 res; | |
192 | int i, ms, delay_idx; | |
193 | const __be64 *p = cmd; | |
194 | u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA); | |
195 | u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL); | |
196 | ||
197 | if ((size & 15) || size > MBOX_LEN) | |
198 | return -EINVAL; | |
199 | ||
204dc3c0 DM |
200 | /* |
201 | * If the device is off-line, as in EEH, commands will time out. | |
202 | * Fail them early so we don't waste time waiting. | |
203 | */ | |
204 | if (adap->pdev->error_state != pci_channel_io_normal) | |
205 | return -EIO; | |
206 | ||
56d36be4 DM |
207 | v = MBOWNER_GET(t4_read_reg(adap, ctl_reg)); |
208 | for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++) | |
209 | v = MBOWNER_GET(t4_read_reg(adap, ctl_reg)); | |
210 | ||
211 | if (v != MBOX_OWNER_DRV) | |
212 | return v ? -EBUSY : -ETIMEDOUT; | |
213 | ||
214 | for (i = 0; i < size; i += 8) | |
215 | t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); | |
216 | ||
217 | t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW)); | |
218 | t4_read_reg(adap, ctl_reg); /* flush write */ | |
219 | ||
220 | delay_idx = 0; | |
221 | ms = delay[0]; | |
222 | ||
223 | for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) { | |
224 | if (sleep_ok) { | |
225 | ms = delay[delay_idx]; /* last element may repeat */ | |
226 | if (delay_idx < ARRAY_SIZE(delay) - 1) | |
227 | delay_idx++; | |
228 | msleep(ms); | |
229 | } else | |
230 | mdelay(ms); | |
231 | ||
232 | v = t4_read_reg(adap, ctl_reg); | |
233 | if (MBOWNER_GET(v) == MBOX_OWNER_DRV) { | |
234 | if (!(v & MBMSGVALID)) { | |
235 | t4_write_reg(adap, ctl_reg, 0); | |
236 | continue; | |
237 | } | |
238 | ||
239 | res = t4_read_reg64(adap, data_reg); | |
240 | if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) { | |
241 | fw_asrt(adap, data_reg); | |
242 | res = FW_CMD_RETVAL(EIO); | |
243 | } else if (rpl) | |
244 | get_mbox_rpl(adap, rpl, size / 8, data_reg); | |
245 | ||
246 | if (FW_CMD_RETVAL_GET((int)res)) | |
247 | dump_mbox(adap, mbox, data_reg); | |
248 | t4_write_reg(adap, ctl_reg, 0); | |
249 | return -FW_CMD_RETVAL_GET((int)res); | |
250 | } | |
251 | } | |
252 | ||
253 | dump_mbox(adap, mbox, data_reg); | |
254 | dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", | |
255 | *(const u8 *)cmd, mbox); | |
256 | return -ETIMEDOUT; | |
257 | } | |
258 | ||
259 | /** | |
260 | * t4_mc_read - read from MC through backdoor accesses | |
261 | * @adap: the adapter | |
262 | * @addr: address of first byte requested | |
263 | * @data: 64 bytes of data containing the requested address | |
264 | * @ecc: where to store the corresponding 64-bit ECC word | |
265 | * | |
266 | * Read 64 bytes of data from MC starting at a 64-byte-aligned address | |
267 | * that covers the requested address @addr. If @parity is not %NULL it | |
268 | * is assigned the 64-bit ECC word for the read data. | |
269 | */ | |
270 | int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc) | |
271 | { | |
272 | int i; | |
273 | ||
274 | if (t4_read_reg(adap, MC_BIST_CMD) & START_BIST) | |
275 | return -EBUSY; | |
276 | t4_write_reg(adap, MC_BIST_CMD_ADDR, addr & ~0x3fU); | |
277 | t4_write_reg(adap, MC_BIST_CMD_LEN, 64); | |
278 | t4_write_reg(adap, MC_BIST_DATA_PATTERN, 0xc); | |
279 | t4_write_reg(adap, MC_BIST_CMD, BIST_OPCODE(1) | START_BIST | | |
280 | BIST_CMD_GAP(1)); | |
281 | i = t4_wait_op_done(adap, MC_BIST_CMD, START_BIST, 0, 10, 1); | |
282 | if (i) | |
283 | return i; | |
284 | ||
285 | #define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i) | |
286 | ||
287 | for (i = 15; i >= 0; i--) | |
288 | *data++ = htonl(t4_read_reg(adap, MC_DATA(i))); | |
289 | if (ecc) | |
290 | *ecc = t4_read_reg64(adap, MC_DATA(16)); | |
291 | #undef MC_DATA | |
292 | return 0; | |
293 | } | |
294 | ||
295 | /** | |
296 | * t4_edc_read - read from EDC through backdoor accesses | |
297 | * @adap: the adapter | |
298 | * @idx: which EDC to access | |
299 | * @addr: address of first byte requested | |
300 | * @data: 64 bytes of data containing the requested address | |
301 | * @ecc: where to store the corresponding 64-bit ECC word | |
302 | * | |
303 | * Read 64 bytes of data from EDC starting at a 64-byte-aligned address | |
304 | * that covers the requested address @addr. If @parity is not %NULL it | |
305 | * is assigned the 64-bit ECC word for the read data. | |
306 | */ | |
307 | int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) | |
308 | { | |
309 | int i; | |
310 | ||
311 | idx *= EDC_STRIDE; | |
312 | if (t4_read_reg(adap, EDC_BIST_CMD + idx) & START_BIST) | |
313 | return -EBUSY; | |
314 | t4_write_reg(adap, EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU); | |
315 | t4_write_reg(adap, EDC_BIST_CMD_LEN + idx, 64); | |
316 | t4_write_reg(adap, EDC_BIST_DATA_PATTERN + idx, 0xc); | |
317 | t4_write_reg(adap, EDC_BIST_CMD + idx, | |
318 | BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST); | |
319 | i = t4_wait_op_done(adap, EDC_BIST_CMD + idx, START_BIST, 0, 10, 1); | |
320 | if (i) | |
321 | return i; | |
322 | ||
323 | #define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx) | |
324 | ||
325 | for (i = 15; i >= 0; i--) | |
326 | *data++ = htonl(t4_read_reg(adap, EDC_DATA(i))); | |
327 | if (ecc) | |
328 | *ecc = t4_read_reg64(adap, EDC_DATA(16)); | |
329 | #undef EDC_DATA | |
330 | return 0; | |
331 | } | |
332 | ||
5afc8b84 VP |
333 | /* |
334 | * t4_mem_win_rw - read/write memory through PCIE memory window | |
335 | * @adap: the adapter | |
336 | * @addr: address of first byte requested | |
337 | * @data: MEMWIN0_APERTURE bytes of data containing the requested address | |
338 | * @dir: direction of transfer 1 => read, 0 => write | |
339 | * | |
340 | * Read/write MEMWIN0_APERTURE bytes of data from MC starting at a | |
341 | * MEMWIN0_APERTURE-byte-aligned address that covers the requested | |
342 | * address @addr. | |
343 | */ | |
344 | static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir) | |
345 | { | |
346 | int i; | |
347 | ||
348 | /* | |
349 | * Setup offset into PCIE memory window. Address must be a | |
350 | * MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to | |
351 | * ensure that changes propagate before we attempt to use the new | |
352 | * values.) | |
353 | */ | |
354 | t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, | |
355 | addr & ~(MEMWIN0_APERTURE - 1)); | |
356 | t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET); | |
357 | ||
358 | /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */ | |
359 | for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) { | |
360 | if (dir) | |
361 | *data++ = t4_read_reg(adap, (MEMWIN0_BASE + i)); | |
362 | else | |
363 | t4_write_reg(adap, (MEMWIN0_BASE + i), *data++); | |
364 | } | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
369 | /** | |
370 | * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window | |
371 | * @adap: the adapter | |
372 | * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC | |
373 | * @addr: address within indicated memory type | |
374 | * @len: amount of memory to transfer | |
375 | * @buf: host memory buffer | |
376 | * @dir: direction of transfer 1 => read, 0 => write | |
377 | * | |
378 | * Reads/writes an [almost] arbitrary memory region in the firmware: the | |
379 | * firmware memory address, length and host buffer must be aligned on | |
380 | * 32-bit boudaries. The memory is transferred as a raw byte sequence | |
381 | * from/to the firmware's memory. If this memory contains data | |
382 | * structures which contain multi-byte integers, it's the callers | |
383 | * responsibility to perform appropriate byte order conversions. | |
384 | */ | |
385 | static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len, | |
386 | __be32 *buf, int dir) | |
387 | { | |
388 | u32 pos, start, end, offset, memoffset; | |
389 | int ret; | |
390 | ||
391 | /* | |
392 | * Argument sanity checks ... | |
393 | */ | |
394 | if ((addr & 0x3) || (len & 0x3)) | |
395 | return -EINVAL; | |
396 | ||
397 | /* | |
398 | * Offset into the region of memory which is being accessed | |
399 | * MEM_EDC0 = 0 | |
400 | * MEM_EDC1 = 1 | |
401 | * MEM_MC = 2 | |
402 | */ | |
403 | memoffset = (mtype * (5 * 1024 * 1024)); | |
404 | ||
405 | /* Determine the PCIE_MEM_ACCESS_OFFSET */ | |
406 | addr = addr + memoffset; | |
407 | ||
408 | /* | |
409 | * The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes | |
410 | * at a time so we need to round down the start and round up the end. | |
411 | * We'll start copying out of the first line at (addr - start) a word | |
412 | * at a time. | |
413 | */ | |
414 | start = addr & ~(MEMWIN0_APERTURE-1); | |
415 | end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1); | |
416 | offset = (addr - start)/sizeof(__be32); | |
417 | ||
418 | for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) { | |
419 | __be32 data[MEMWIN0_APERTURE/sizeof(__be32)]; | |
420 | ||
421 | /* | |
422 | * If we're writing, copy the data from the caller's memory | |
423 | * buffer | |
424 | */ | |
425 | if (!dir) { | |
426 | /* | |
427 | * If we're doing a partial write, then we need to do | |
428 | * a read-modify-write ... | |
429 | */ | |
430 | if (offset || len < MEMWIN0_APERTURE) { | |
431 | ret = t4_mem_win_rw(adap, pos, data, 1); | |
432 | if (ret) | |
433 | return ret; | |
434 | } | |
435 | while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) && | |
436 | len > 0) { | |
437 | data[offset++] = *buf++; | |
438 | len -= sizeof(__be32); | |
439 | } | |
440 | } | |
441 | ||
442 | /* | |
443 | * Transfer a block of memory and bail if there's an error. | |
444 | */ | |
445 | ret = t4_mem_win_rw(adap, pos, data, dir); | |
446 | if (ret) | |
447 | return ret; | |
448 | ||
449 | /* | |
450 | * If we're reading, copy the data into the caller's memory | |
451 | * buffer. | |
452 | */ | |
453 | if (dir) | |
454 | while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) && | |
455 | len > 0) { | |
456 | *buf++ = data[offset++]; | |
457 | len -= sizeof(__be32); | |
458 | } | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len, | |
465 | __be32 *buf) | |
466 | { | |
467 | return t4_memory_rw(adap, mtype, addr, len, buf, 0); | |
468 | } | |
469 | ||
56d36be4 DM |
470 | #define EEPROM_STAT_ADDR 0x7bfc |
471 | #define VPD_BASE 0 | |
226ec5fd | 472 | #define VPD_LEN 512 |
56d36be4 DM |
473 | |
474 | /** | |
475 | * t4_seeprom_wp - enable/disable EEPROM write protection | |
476 | * @adapter: the adapter | |
477 | * @enable: whether to enable or disable write protection | |
478 | * | |
479 | * Enables or disables write protection on the serial EEPROM. | |
480 | */ | |
481 | int t4_seeprom_wp(struct adapter *adapter, bool enable) | |
482 | { | |
483 | unsigned int v = enable ? 0xc : 0; | |
484 | int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v); | |
485 | return ret < 0 ? ret : 0; | |
486 | } | |
487 | ||
488 | /** | |
489 | * get_vpd_params - read VPD parameters from VPD EEPROM | |
490 | * @adapter: adapter to read | |
491 | * @p: where to store the parameters | |
492 | * | |
493 | * Reads card parameters stored in VPD EEPROM. | |
494 | */ | |
495 | static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) | |
496 | { | |
226ec5fd | 497 | int i, ret; |
ec164008 | 498 | int ec, sn; |
226ec5fd | 499 | u8 vpd[VPD_LEN], csum; |
23d88e1d | 500 | unsigned int vpdr_len, kw_offset, id_len; |
56d36be4 | 501 | |
226ec5fd | 502 | ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(vpd), vpd); |
56d36be4 DM |
503 | if (ret < 0) |
504 | return ret; | |
505 | ||
23d88e1d DM |
506 | if (vpd[0] != PCI_VPD_LRDT_ID_STRING) { |
507 | dev_err(adapter->pdev_dev, "missing VPD ID string\n"); | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
511 | id_len = pci_vpd_lrdt_size(vpd); | |
512 | if (id_len > ID_LEN) | |
513 | id_len = ID_LEN; | |
514 | ||
515 | i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA); | |
516 | if (i < 0) { | |
517 | dev_err(adapter->pdev_dev, "missing VPD-R section\n"); | |
518 | return -EINVAL; | |
519 | } | |
520 | ||
521 | vpdr_len = pci_vpd_lrdt_size(&vpd[i]); | |
522 | kw_offset = i + PCI_VPD_LRDT_TAG_SIZE; | |
523 | if (vpdr_len + kw_offset > VPD_LEN) { | |
226ec5fd DM |
524 | dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len); |
525 | return -EINVAL; | |
526 | } | |
527 | ||
528 | #define FIND_VPD_KW(var, name) do { \ | |
23d88e1d | 529 | var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \ |
226ec5fd DM |
530 | if (var < 0) { \ |
531 | dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \ | |
532 | return -EINVAL; \ | |
533 | } \ | |
534 | var += PCI_VPD_INFO_FLD_HDR_SIZE; \ | |
535 | } while (0) | |
536 | ||
537 | FIND_VPD_KW(i, "RV"); | |
538 | for (csum = 0; i >= 0; i--) | |
539 | csum += vpd[i]; | |
56d36be4 DM |
540 | |
541 | if (csum) { | |
542 | dev_err(adapter->pdev_dev, | |
543 | "corrupted VPD EEPROM, actual csum %u\n", csum); | |
544 | return -EINVAL; | |
545 | } | |
546 | ||
226ec5fd DM |
547 | FIND_VPD_KW(ec, "EC"); |
548 | FIND_VPD_KW(sn, "SN"); | |
226ec5fd DM |
549 | #undef FIND_VPD_KW |
550 | ||
23d88e1d | 551 | memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len); |
56d36be4 | 552 | strim(p->id); |
226ec5fd | 553 | memcpy(p->ec, vpd + ec, EC_LEN); |
56d36be4 | 554 | strim(p->ec); |
226ec5fd DM |
555 | i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE); |
556 | memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); | |
56d36be4 DM |
557 | strim(p->sn); |
558 | return 0; | |
559 | } | |
560 | ||
561 | /* serial flash and firmware constants */ | |
562 | enum { | |
563 | SF_ATTEMPTS = 10, /* max retries for SF operations */ | |
564 | ||
565 | /* flash command opcodes */ | |
566 | SF_PROG_PAGE = 2, /* program page */ | |
567 | SF_WR_DISABLE = 4, /* disable writes */ | |
568 | SF_RD_STATUS = 5, /* read status register */ | |
569 | SF_WR_ENABLE = 6, /* enable writes */ | |
570 | SF_RD_DATA_FAST = 0xb, /* read flash */ | |
900a6596 | 571 | SF_RD_ID = 0x9f, /* read ID */ |
56d36be4 DM |
572 | SF_ERASE_SECTOR = 0xd8, /* erase sector */ |
573 | ||
900a6596 | 574 | FW_MAX_SIZE = 512 * 1024, |
56d36be4 DM |
575 | }; |
576 | ||
577 | /** | |
578 | * sf1_read - read data from the serial flash | |
579 | * @adapter: the adapter | |
580 | * @byte_cnt: number of bytes to read | |
581 | * @cont: whether another operation will be chained | |
582 | * @lock: whether to lock SF for PL access only | |
583 | * @valp: where to store the read data | |
584 | * | |
585 | * Reads up to 4 bytes of data from the serial flash. The location of | |
586 | * the read needs to be specified prior to calling this by issuing the | |
587 | * appropriate commands to the serial flash. | |
588 | */ | |
589 | static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, | |
590 | int lock, u32 *valp) | |
591 | { | |
592 | int ret; | |
593 | ||
594 | if (!byte_cnt || byte_cnt > 4) | |
595 | return -EINVAL; | |
596 | if (t4_read_reg(adapter, SF_OP) & BUSY) | |
597 | return -EBUSY; | |
598 | cont = cont ? SF_CONT : 0; | |
599 | lock = lock ? SF_LOCK : 0; | |
600 | t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1)); | |
601 | ret = t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5); | |
602 | if (!ret) | |
603 | *valp = t4_read_reg(adapter, SF_DATA); | |
604 | return ret; | |
605 | } | |
606 | ||
607 | /** | |
608 | * sf1_write - write data to the serial flash | |
609 | * @adapter: the adapter | |
610 | * @byte_cnt: number of bytes to write | |
611 | * @cont: whether another operation will be chained | |
612 | * @lock: whether to lock SF for PL access only | |
613 | * @val: value to write | |
614 | * | |
615 | * Writes up to 4 bytes of data to the serial flash. The location of | |
616 | * the write needs to be specified prior to calling this by issuing the | |
617 | * appropriate commands to the serial flash. | |
618 | */ | |
619 | static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, | |
620 | int lock, u32 val) | |
621 | { | |
622 | if (!byte_cnt || byte_cnt > 4) | |
623 | return -EINVAL; | |
624 | if (t4_read_reg(adapter, SF_OP) & BUSY) | |
625 | return -EBUSY; | |
626 | cont = cont ? SF_CONT : 0; | |
627 | lock = lock ? SF_LOCK : 0; | |
628 | t4_write_reg(adapter, SF_DATA, val); | |
629 | t4_write_reg(adapter, SF_OP, lock | | |
630 | cont | BYTECNT(byte_cnt - 1) | OP_WR); | |
631 | return t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5); | |
632 | } | |
633 | ||
634 | /** | |
635 | * flash_wait_op - wait for a flash operation to complete | |
636 | * @adapter: the adapter | |
637 | * @attempts: max number of polls of the status register | |
638 | * @delay: delay between polls in ms | |
639 | * | |
640 | * Wait for a flash operation to complete by polling the status register. | |
641 | */ | |
642 | static int flash_wait_op(struct adapter *adapter, int attempts, int delay) | |
643 | { | |
644 | int ret; | |
645 | u32 status; | |
646 | ||
647 | while (1) { | |
648 | if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || | |
649 | (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) | |
650 | return ret; | |
651 | if (!(status & 1)) | |
652 | return 0; | |
653 | if (--attempts == 0) | |
654 | return -EAGAIN; | |
655 | if (delay) | |
656 | msleep(delay); | |
657 | } | |
658 | } | |
659 | ||
660 | /** | |
661 | * t4_read_flash - read words from serial flash | |
662 | * @adapter: the adapter | |
663 | * @addr: the start address for the read | |
664 | * @nwords: how many 32-bit words to read | |
665 | * @data: where to store the read data | |
666 | * @byte_oriented: whether to store data as bytes or as words | |
667 | * | |
668 | * Read the specified number of 32-bit words from the serial flash. | |
669 | * If @byte_oriented is set the read data is stored as a byte array | |
670 | * (i.e., big-endian), otherwise as 32-bit words in the platform's | |
671 | * natural endianess. | |
672 | */ | |
de498c89 RD |
673 | static int t4_read_flash(struct adapter *adapter, unsigned int addr, |
674 | unsigned int nwords, u32 *data, int byte_oriented) | |
56d36be4 DM |
675 | { |
676 | int ret; | |
677 | ||
900a6596 | 678 | if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) |
56d36be4 DM |
679 | return -EINVAL; |
680 | ||
681 | addr = swab32(addr) | SF_RD_DATA_FAST; | |
682 | ||
683 | if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || | |
684 | (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) | |
685 | return ret; | |
686 | ||
687 | for ( ; nwords; nwords--, data++) { | |
688 | ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); | |
689 | if (nwords == 1) | |
690 | t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ | |
691 | if (ret) | |
692 | return ret; | |
693 | if (byte_oriented) | |
694 | *data = htonl(*data); | |
695 | } | |
696 | return 0; | |
697 | } | |
698 | ||
699 | /** | |
700 | * t4_write_flash - write up to a page of data to the serial flash | |
701 | * @adapter: the adapter | |
702 | * @addr: the start address to write | |
703 | * @n: length of data to write in bytes | |
704 | * @data: the data to write | |
705 | * | |
706 | * Writes up to a page of data (256 bytes) to the serial flash starting | |
707 | * at the given address. All the data must be written to the same page. | |
708 | */ | |
709 | static int t4_write_flash(struct adapter *adapter, unsigned int addr, | |
710 | unsigned int n, const u8 *data) | |
711 | { | |
712 | int ret; | |
713 | u32 buf[64]; | |
714 | unsigned int i, c, left, val, offset = addr & 0xff; | |
715 | ||
900a6596 | 716 | if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) |
56d36be4 DM |
717 | return -EINVAL; |
718 | ||
719 | val = swab32(addr) | SF_PROG_PAGE; | |
720 | ||
721 | if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || | |
722 | (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) | |
723 | goto unlock; | |
724 | ||
725 | for (left = n; left; left -= c) { | |
726 | c = min(left, 4U); | |
727 | for (val = 0, i = 0; i < c; ++i) | |
728 | val = (val << 8) + *data++; | |
729 | ||
730 | ret = sf1_write(adapter, c, c != left, 1, val); | |
731 | if (ret) | |
732 | goto unlock; | |
733 | } | |
900a6596 | 734 | ret = flash_wait_op(adapter, 8, 1); |
56d36be4 DM |
735 | if (ret) |
736 | goto unlock; | |
737 | ||
738 | t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ | |
739 | ||
740 | /* Read the page to verify the write succeeded */ | |
741 | ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); | |
742 | if (ret) | |
743 | return ret; | |
744 | ||
745 | if (memcmp(data - n, (u8 *)buf + offset, n)) { | |
746 | dev_err(adapter->pdev_dev, | |
747 | "failed to correctly write the flash page at %#x\n", | |
748 | addr); | |
749 | return -EIO; | |
750 | } | |
751 | return 0; | |
752 | ||
753 | unlock: | |
754 | t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ | |
755 | return ret; | |
756 | } | |
757 | ||
758 | /** | |
759 | * get_fw_version - read the firmware version | |
760 | * @adapter: the adapter | |
761 | * @vers: where to place the version | |
762 | * | |
763 | * Reads the FW version from flash. | |
764 | */ | |
765 | static int get_fw_version(struct adapter *adapter, u32 *vers) | |
766 | { | |
900a6596 DM |
767 | return t4_read_flash(adapter, adapter->params.sf_fw_start + |
768 | offsetof(struct fw_hdr, fw_ver), 1, vers, 0); | |
56d36be4 DM |
769 | } |
770 | ||
771 | /** | |
772 | * get_tp_version - read the TP microcode version | |
773 | * @adapter: the adapter | |
774 | * @vers: where to place the version | |
775 | * | |
776 | * Reads the TP microcode version from flash. | |
777 | */ | |
778 | static int get_tp_version(struct adapter *adapter, u32 *vers) | |
779 | { | |
900a6596 DM |
780 | return t4_read_flash(adapter, adapter->params.sf_fw_start + |
781 | offsetof(struct fw_hdr, tp_microcode_ver), | |
56d36be4 DM |
782 | 1, vers, 0); |
783 | } | |
784 | ||
785 | /** | |
786 | * t4_check_fw_version - check if the FW is compatible with this driver | |
787 | * @adapter: the adapter | |
788 | * | |
789 | * Checks if an adapter's FW is compatible with the driver. Returns 0 | |
790 | * if there's exact match, a negative error if the version could not be | |
791 | * read or there's a major version mismatch, and a positive value if the | |
792 | * expected major version is found but there's a minor version mismatch. | |
793 | */ | |
794 | int t4_check_fw_version(struct adapter *adapter) | |
795 | { | |
796 | u32 api_vers[2]; | |
797 | int ret, major, minor, micro; | |
798 | ||
799 | ret = get_fw_version(adapter, &adapter->params.fw_vers); | |
800 | if (!ret) | |
801 | ret = get_tp_version(adapter, &adapter->params.tp_vers); | |
802 | if (!ret) | |
900a6596 DM |
803 | ret = t4_read_flash(adapter, adapter->params.sf_fw_start + |
804 | offsetof(struct fw_hdr, intfver_nic), | |
805 | 2, api_vers, 1); | |
56d36be4 DM |
806 | if (ret) |
807 | return ret; | |
808 | ||
809 | major = FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers); | |
810 | minor = FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers); | |
811 | micro = FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers); | |
812 | memcpy(adapter->params.api_vers, api_vers, | |
813 | sizeof(adapter->params.api_vers)); | |
814 | ||
815 | if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */ | |
816 | dev_err(adapter->pdev_dev, | |
817 | "card FW has major version %u, driver wants %u\n", | |
818 | major, FW_VERSION_MAJOR); | |
819 | return -EINVAL; | |
820 | } | |
821 | ||
822 | if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO) | |
823 | return 0; /* perfect match */ | |
824 | ||
825 | /* Minor/micro version mismatch. Report it but often it's OK. */ | |
826 | return 1; | |
827 | } | |
828 | ||
829 | /** | |
830 | * t4_flash_erase_sectors - erase a range of flash sectors | |
831 | * @adapter: the adapter | |
832 | * @start: the first sector to erase | |
833 | * @end: the last sector to erase | |
834 | * | |
835 | * Erases the sectors in the given inclusive range. | |
836 | */ | |
837 | static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) | |
838 | { | |
839 | int ret = 0; | |
840 | ||
841 | while (start <= end) { | |
842 | if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || | |
843 | (ret = sf1_write(adapter, 4, 0, 1, | |
844 | SF_ERASE_SECTOR | (start << 8))) != 0 || | |
900a6596 | 845 | (ret = flash_wait_op(adapter, 14, 500)) != 0) { |
56d36be4 DM |
846 | dev_err(adapter->pdev_dev, |
847 | "erase of flash sector %d failed, error %d\n", | |
848 | start, ret); | |
849 | break; | |
850 | } | |
851 | start++; | |
852 | } | |
853 | t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ | |
854 | return ret; | |
855 | } | |
856 | ||
857 | /** | |
858 | * t4_load_fw - download firmware | |
859 | * @adap: the adapter | |
860 | * @fw_data: the firmware image to write | |
861 | * @size: image size | |
862 | * | |
863 | * Write the supplied firmware image to the card's serial flash. | |
864 | */ | |
865 | int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) | |
866 | { | |
867 | u32 csum; | |
868 | int ret, addr; | |
869 | unsigned int i; | |
870 | u8 first_page[SF_PAGE_SIZE]; | |
871 | const u32 *p = (const u32 *)fw_data; | |
872 | const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; | |
900a6596 DM |
873 | unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; |
874 | unsigned int fw_img_start = adap->params.sf_fw_start; | |
875 | unsigned int fw_start_sec = fw_img_start / sf_sec_size; | |
56d36be4 DM |
876 | |
877 | if (!size) { | |
878 | dev_err(adap->pdev_dev, "FW image has no data\n"); | |
879 | return -EINVAL; | |
880 | } | |
881 | if (size & 511) { | |
882 | dev_err(adap->pdev_dev, | |
883 | "FW image size not multiple of 512 bytes\n"); | |
884 | return -EINVAL; | |
885 | } | |
886 | if (ntohs(hdr->len512) * 512 != size) { | |
887 | dev_err(adap->pdev_dev, | |
888 | "FW image size differs from size in FW header\n"); | |
889 | return -EINVAL; | |
890 | } | |
891 | if (size > FW_MAX_SIZE) { | |
892 | dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", | |
893 | FW_MAX_SIZE); | |
894 | return -EFBIG; | |
895 | } | |
896 | ||
897 | for (csum = 0, i = 0; i < size / sizeof(csum); i++) | |
898 | csum += ntohl(p[i]); | |
899 | ||
900 | if (csum != 0xffffffff) { | |
901 | dev_err(adap->pdev_dev, | |
902 | "corrupted firmware image, checksum %#x\n", csum); | |
903 | return -EINVAL; | |
904 | } | |
905 | ||
900a6596 DM |
906 | i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ |
907 | ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); | |
56d36be4 DM |
908 | if (ret) |
909 | goto out; | |
910 | ||
911 | /* | |
912 | * We write the correct version at the end so the driver can see a bad | |
913 | * version if the FW write fails. Start by writing a copy of the | |
914 | * first page with a bad version. | |
915 | */ | |
916 | memcpy(first_page, fw_data, SF_PAGE_SIZE); | |
917 | ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); | |
900a6596 | 918 | ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page); |
56d36be4 DM |
919 | if (ret) |
920 | goto out; | |
921 | ||
900a6596 | 922 | addr = fw_img_start; |
56d36be4 DM |
923 | for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { |
924 | addr += SF_PAGE_SIZE; | |
925 | fw_data += SF_PAGE_SIZE; | |
926 | ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); | |
927 | if (ret) | |
928 | goto out; | |
929 | } | |
930 | ||
931 | ret = t4_write_flash(adap, | |
900a6596 | 932 | fw_img_start + offsetof(struct fw_hdr, fw_ver), |
56d36be4 DM |
933 | sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver); |
934 | out: | |
935 | if (ret) | |
936 | dev_err(adap->pdev_dev, "firmware download failed, error %d\n", | |
937 | ret); | |
938 | return ret; | |
939 | } | |
940 | ||
941 | #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ | |
942 | FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG) | |
943 | ||
944 | /** | |
945 | * t4_link_start - apply link configuration to MAC/PHY | |
946 | * @phy: the PHY to setup | |
947 | * @mac: the MAC to setup | |
948 | * @lc: the requested link configuration | |
949 | * | |
950 | * Set up a port's MAC and PHY according to a desired link configuration. | |
951 | * - If the PHY can auto-negotiate first decide what to advertise, then | |
952 | * enable/disable auto-negotiation as desired, and reset. | |
953 | * - If the PHY does not auto-negotiate just reset it. | |
954 | * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, | |
955 | * otherwise do it later based on the outcome of auto-negotiation. | |
956 | */ | |
957 | int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, | |
958 | struct link_config *lc) | |
959 | { | |
960 | struct fw_port_cmd c; | |
961 | unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO); | |
962 | ||
963 | lc->link_ok = 0; | |
964 | if (lc->requested_fc & PAUSE_RX) | |
965 | fc |= FW_PORT_CAP_FC_RX; | |
966 | if (lc->requested_fc & PAUSE_TX) | |
967 | fc |= FW_PORT_CAP_FC_TX; | |
968 | ||
969 | memset(&c, 0, sizeof(c)); | |
970 | c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST | | |
971 | FW_CMD_EXEC | FW_PORT_CMD_PORTID(port)); | |
972 | c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | | |
973 | FW_LEN16(c)); | |
974 | ||
975 | if (!(lc->supported & FW_PORT_CAP_ANEG)) { | |
976 | c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc); | |
977 | lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); | |
978 | } else if (lc->autoneg == AUTONEG_DISABLE) { | |
979 | c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi); | |
980 | lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); | |
981 | } else | |
982 | c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi); | |
983 | ||
984 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
985 | } | |
986 | ||
987 | /** | |
988 | * t4_restart_aneg - restart autonegotiation | |
989 | * @adap: the adapter | |
990 | * @mbox: mbox to use for the FW command | |
991 | * @port: the port id | |
992 | * | |
993 | * Restarts autonegotiation for the selected port. | |
994 | */ | |
995 | int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) | |
996 | { | |
997 | struct fw_port_cmd c; | |
998 | ||
999 | memset(&c, 0, sizeof(c)); | |
1000 | c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST | | |
1001 | FW_CMD_EXEC | FW_PORT_CMD_PORTID(port)); | |
1002 | c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | | |
1003 | FW_LEN16(c)); | |
1004 | c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG); | |
1005 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
1006 | } | |
1007 | ||
8caa1e84 VP |
1008 | typedef void (*int_handler_t)(struct adapter *adap); |
1009 | ||
56d36be4 DM |
1010 | struct intr_info { |
1011 | unsigned int mask; /* bits to check in interrupt status */ | |
1012 | const char *msg; /* message to print or NULL */ | |
1013 | short stat_idx; /* stat counter to increment or -1 */ | |
1014 | unsigned short fatal; /* whether the condition reported is fatal */ | |
8caa1e84 | 1015 | int_handler_t int_handler; /* platform-specific int handler */ |
56d36be4 DM |
1016 | }; |
1017 | ||
1018 | /** | |
1019 | * t4_handle_intr_status - table driven interrupt handler | |
1020 | * @adapter: the adapter that generated the interrupt | |
1021 | * @reg: the interrupt status register to process | |
1022 | * @acts: table of interrupt actions | |
1023 | * | |
1024 | * A table driven interrupt handler that applies a set of masks to an | |
1025 | * interrupt status word and performs the corresponding actions if the | |
25985edc | 1026 | * interrupts described by the mask have occurred. The actions include |
56d36be4 DM |
1027 | * optionally emitting a warning or alert message. The table is terminated |
1028 | * by an entry specifying mask 0. Returns the number of fatal interrupt | |
1029 | * conditions. | |
1030 | */ | |
1031 | static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, | |
1032 | const struct intr_info *acts) | |
1033 | { | |
1034 | int fatal = 0; | |
1035 | unsigned int mask = 0; | |
1036 | unsigned int status = t4_read_reg(adapter, reg); | |
1037 | ||
1038 | for ( ; acts->mask; ++acts) { | |
1039 | if (!(status & acts->mask)) | |
1040 | continue; | |
1041 | if (acts->fatal) { | |
1042 | fatal++; | |
1043 | dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, | |
1044 | status & acts->mask); | |
1045 | } else if (acts->msg && printk_ratelimit()) | |
1046 | dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, | |
1047 | status & acts->mask); | |
8caa1e84 VP |
1048 | if (acts->int_handler) |
1049 | acts->int_handler(adapter); | |
56d36be4 DM |
1050 | mask |= acts->mask; |
1051 | } | |
1052 | status &= mask; | |
1053 | if (status) /* clear processed interrupts */ | |
1054 | t4_write_reg(adapter, reg, status); | |
1055 | return fatal; | |
1056 | } | |
1057 | ||
1058 | /* | |
1059 | * Interrupt handler for the PCIE module. | |
1060 | */ | |
1061 | static void pcie_intr_handler(struct adapter *adapter) | |
1062 | { | |
005b5717 | 1063 | static const struct intr_info sysbus_intr_info[] = { |
56d36be4 DM |
1064 | { RNPP, "RXNP array parity error", -1, 1 }, |
1065 | { RPCP, "RXPC array parity error", -1, 1 }, | |
1066 | { RCIP, "RXCIF array parity error", -1, 1 }, | |
1067 | { RCCP, "Rx completions control array parity error", -1, 1 }, | |
1068 | { RFTP, "RXFT array parity error", -1, 1 }, | |
1069 | { 0 } | |
1070 | }; | |
005b5717 | 1071 | static const struct intr_info pcie_port_intr_info[] = { |
56d36be4 DM |
1072 | { TPCP, "TXPC array parity error", -1, 1 }, |
1073 | { TNPP, "TXNP array parity error", -1, 1 }, | |
1074 | { TFTP, "TXFT array parity error", -1, 1 }, | |
1075 | { TCAP, "TXCA array parity error", -1, 1 }, | |
1076 | { TCIP, "TXCIF array parity error", -1, 1 }, | |
1077 | { RCAP, "RXCA array parity error", -1, 1 }, | |
1078 | { OTDD, "outbound request TLP discarded", -1, 1 }, | |
1079 | { RDPE, "Rx data parity error", -1, 1 }, | |
1080 | { TDUE, "Tx uncorrectable data error", -1, 1 }, | |
1081 | { 0 } | |
1082 | }; | |
005b5717 | 1083 | static const struct intr_info pcie_intr_info[] = { |
56d36be4 DM |
1084 | { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, |
1085 | { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, | |
1086 | { MSIDATAPERR, "MSI data parity error", -1, 1 }, | |
1087 | { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, | |
1088 | { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, | |
1089 | { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, | |
1090 | { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, | |
1091 | { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, | |
1092 | { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, | |
1093 | { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, | |
1094 | { CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, | |
1095 | { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, | |
1096 | { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, | |
1097 | { DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, | |
1098 | { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, | |
1099 | { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, | |
1100 | { HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, | |
1101 | { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, | |
1102 | { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, | |
1103 | { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, | |
1104 | { FIDPERR, "PCI FID parity error", -1, 1 }, | |
1105 | { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, | |
1106 | { MATAGPERR, "PCI MA tag parity error", -1, 1 }, | |
1107 | { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, | |
1108 | { RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, | |
1109 | { RXWRPERR, "PCI Rx write parity error", -1, 1 }, | |
1110 | { RPLPERR, "PCI replay buffer parity error", -1, 1 }, | |
1111 | { PCIESINT, "PCI core secondary fault", -1, 1 }, | |
1112 | { PCIEPINT, "PCI core primary fault", -1, 1 }, | |
1113 | { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 }, | |
1114 | { 0 } | |
1115 | }; | |
1116 | ||
1117 | int fat; | |
1118 | ||
1119 | fat = t4_handle_intr_status(adapter, | |
1120 | PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, | |
1121 | sysbus_intr_info) + | |
1122 | t4_handle_intr_status(adapter, | |
1123 | PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, | |
1124 | pcie_port_intr_info) + | |
1125 | t4_handle_intr_status(adapter, PCIE_INT_CAUSE, pcie_intr_info); | |
1126 | if (fat) | |
1127 | t4_fatal_err(adapter); | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * TP interrupt handler. | |
1132 | */ | |
1133 | static void tp_intr_handler(struct adapter *adapter) | |
1134 | { | |
005b5717 | 1135 | static const struct intr_info tp_intr_info[] = { |
56d36be4 DM |
1136 | { 0x3fffffff, "TP parity error", -1, 1 }, |
1137 | { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, | |
1138 | { 0 } | |
1139 | }; | |
1140 | ||
1141 | if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info)) | |
1142 | t4_fatal_err(adapter); | |
1143 | } | |
1144 | ||
1145 | /* | |
1146 | * SGE interrupt handler. | |
1147 | */ | |
1148 | static void sge_intr_handler(struct adapter *adapter) | |
1149 | { | |
1150 | u64 v; | |
1151 | ||
005b5717 | 1152 | static const struct intr_info sge_intr_info[] = { |
56d36be4 DM |
1153 | { ERR_CPL_EXCEED_IQE_SIZE, |
1154 | "SGE received CPL exceeding IQE size", -1, 1 }, | |
1155 | { ERR_INVALID_CIDX_INC, | |
1156 | "SGE GTS CIDX increment too large", -1, 0 }, | |
1157 | { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, | |
840f3000 VP |
1158 | { DBFIFO_LP_INT, NULL, -1, 0, t4_db_full }, |
1159 | { DBFIFO_HP_INT, NULL, -1, 0, t4_db_full }, | |
1160 | { ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped }, | |
56d36be4 DM |
1161 | { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0, |
1162 | "SGE IQID > 1023 received CPL for FL", -1, 0 }, | |
1163 | { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, | |
1164 | 0 }, | |
1165 | { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, | |
1166 | 0 }, | |
1167 | { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, | |
1168 | 0 }, | |
1169 | { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, | |
1170 | 0 }, | |
1171 | { ERR_ING_CTXT_PRIO, | |
1172 | "SGE too many priority ingress contexts", -1, 0 }, | |
1173 | { ERR_EGR_CTXT_PRIO, | |
1174 | "SGE too many priority egress contexts", -1, 0 }, | |
1175 | { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, | |
1176 | { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, | |
1177 | { 0 } | |
1178 | }; | |
1179 | ||
1180 | v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) | | |
8caa1e84 | 1181 | ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32); |
56d36be4 DM |
1182 | if (v) { |
1183 | dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n", | |
8caa1e84 | 1184 | (unsigned long long)v); |
56d36be4 DM |
1185 | t4_write_reg(adapter, SGE_INT_CAUSE1, v); |
1186 | t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32); | |
1187 | } | |
1188 | ||
1189 | if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) || | |
1190 | v != 0) | |
1191 | t4_fatal_err(adapter); | |
1192 | } | |
1193 | ||
1194 | /* | |
1195 | * CIM interrupt handler. | |
1196 | */ | |
1197 | static void cim_intr_handler(struct adapter *adapter) | |
1198 | { | |
005b5717 | 1199 | static const struct intr_info cim_intr_info[] = { |
56d36be4 DM |
1200 | { PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, |
1201 | { OBQPARERR, "CIM OBQ parity error", -1, 1 }, | |
1202 | { IBQPARERR, "CIM IBQ parity error", -1, 1 }, | |
1203 | { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, | |
1204 | { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, | |
1205 | { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, | |
1206 | { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, | |
1207 | { 0 } | |
1208 | }; | |
005b5717 | 1209 | static const struct intr_info cim_upintr_info[] = { |
56d36be4 DM |
1210 | { RSVDSPACEINT, "CIM reserved space access", -1, 1 }, |
1211 | { ILLTRANSINT, "CIM illegal transaction", -1, 1 }, | |
1212 | { ILLWRINT, "CIM illegal write", -1, 1 }, | |
1213 | { ILLRDINT, "CIM illegal read", -1, 1 }, | |
1214 | { ILLRDBEINT, "CIM illegal read BE", -1, 1 }, | |
1215 | { ILLWRBEINT, "CIM illegal write BE", -1, 1 }, | |
1216 | { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, | |
1217 | { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, | |
1218 | { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, | |
1219 | { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, | |
1220 | { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, | |
1221 | { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, | |
1222 | { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, | |
1223 | { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, | |
1224 | { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, | |
1225 | { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, | |
1226 | { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, | |
1227 | { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, | |
1228 | { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, | |
1229 | { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, | |
1230 | { SGLRDPLINT , "CIM single read from PL space", -1, 1 }, | |
1231 | { SGLWRPLINT , "CIM single write to PL space", -1, 1 }, | |
1232 | { BLKRDPLINT , "CIM block read from PL space", -1, 1 }, | |
1233 | { BLKWRPLINT , "CIM block write to PL space", -1, 1 }, | |
1234 | { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, | |
1235 | { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, | |
1236 | { TIMEOUTINT , "CIM PIF timeout", -1, 1 }, | |
1237 | { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, | |
1238 | { 0 } | |
1239 | }; | |
1240 | ||
1241 | int fat; | |
1242 | ||
1243 | fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE, | |
1244 | cim_intr_info) + | |
1245 | t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE, | |
1246 | cim_upintr_info); | |
1247 | if (fat) | |
1248 | t4_fatal_err(adapter); | |
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * ULP RX interrupt handler. | |
1253 | */ | |
1254 | static void ulprx_intr_handler(struct adapter *adapter) | |
1255 | { | |
005b5717 | 1256 | static const struct intr_info ulprx_intr_info[] = { |
91e9a1ec | 1257 | { 0x1800000, "ULPRX context error", -1, 1 }, |
56d36be4 DM |
1258 | { 0x7fffff, "ULPRX parity error", -1, 1 }, |
1259 | { 0 } | |
1260 | }; | |
1261 | ||
1262 | if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info)) | |
1263 | t4_fatal_err(adapter); | |
1264 | } | |
1265 | ||
1266 | /* | |
1267 | * ULP TX interrupt handler. | |
1268 | */ | |
1269 | static void ulptx_intr_handler(struct adapter *adapter) | |
1270 | { | |
005b5717 | 1271 | static const struct intr_info ulptx_intr_info[] = { |
56d36be4 DM |
1272 | { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, |
1273 | 0 }, | |
1274 | { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, | |
1275 | 0 }, | |
1276 | { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, | |
1277 | 0 }, | |
1278 | { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, | |
1279 | 0 }, | |
1280 | { 0xfffffff, "ULPTX parity error", -1, 1 }, | |
1281 | { 0 } | |
1282 | }; | |
1283 | ||
1284 | if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info)) | |
1285 | t4_fatal_err(adapter); | |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * PM TX interrupt handler. | |
1290 | */ | |
1291 | static void pmtx_intr_handler(struct adapter *adapter) | |
1292 | { | |
005b5717 | 1293 | static const struct intr_info pmtx_intr_info[] = { |
56d36be4 DM |
1294 | { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, |
1295 | { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, | |
1296 | { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, | |
1297 | { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, | |
1298 | { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 }, | |
1299 | { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, | |
1300 | { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 }, | |
1301 | { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, | |
1302 | { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, | |
1303 | { 0 } | |
1304 | }; | |
1305 | ||
1306 | if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info)) | |
1307 | t4_fatal_err(adapter); | |
1308 | } | |
1309 | ||
1310 | /* | |
1311 | * PM RX interrupt handler. | |
1312 | */ | |
1313 | static void pmrx_intr_handler(struct adapter *adapter) | |
1314 | { | |
005b5717 | 1315 | static const struct intr_info pmrx_intr_info[] = { |
56d36be4 DM |
1316 | { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, |
1317 | { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 }, | |
1318 | { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, | |
1319 | { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 }, | |
1320 | { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, | |
1321 | { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, | |
1322 | { 0 } | |
1323 | }; | |
1324 | ||
1325 | if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info)) | |
1326 | t4_fatal_err(adapter); | |
1327 | } | |
1328 | ||
1329 | /* | |
1330 | * CPL switch interrupt handler. | |
1331 | */ | |
1332 | static void cplsw_intr_handler(struct adapter *adapter) | |
1333 | { | |
005b5717 | 1334 | static const struct intr_info cplsw_intr_info[] = { |
56d36be4 DM |
1335 | { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, |
1336 | { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, | |
1337 | { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, | |
1338 | { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, | |
1339 | { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, | |
1340 | { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, | |
1341 | { 0 } | |
1342 | }; | |
1343 | ||
1344 | if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info)) | |
1345 | t4_fatal_err(adapter); | |
1346 | } | |
1347 | ||
1348 | /* | |
1349 | * LE interrupt handler. | |
1350 | */ | |
1351 | static void le_intr_handler(struct adapter *adap) | |
1352 | { | |
005b5717 | 1353 | static const struct intr_info le_intr_info[] = { |
56d36be4 DM |
1354 | { LIPMISS, "LE LIP miss", -1, 0 }, |
1355 | { LIP0, "LE 0 LIP error", -1, 0 }, | |
1356 | { PARITYERR, "LE parity error", -1, 1 }, | |
1357 | { UNKNOWNCMD, "LE unknown command", -1, 1 }, | |
1358 | { REQQPARERR, "LE request queue parity error", -1, 1 }, | |
1359 | { 0 } | |
1360 | }; | |
1361 | ||
1362 | if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info)) | |
1363 | t4_fatal_err(adap); | |
1364 | } | |
1365 | ||
1366 | /* | |
1367 | * MPS interrupt handler. | |
1368 | */ | |
1369 | static void mps_intr_handler(struct adapter *adapter) | |
1370 | { | |
005b5717 | 1371 | static const struct intr_info mps_rx_intr_info[] = { |
56d36be4 DM |
1372 | { 0xffffff, "MPS Rx parity error", -1, 1 }, |
1373 | { 0 } | |
1374 | }; | |
005b5717 | 1375 | static const struct intr_info mps_tx_intr_info[] = { |
56d36be4 DM |
1376 | { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 }, |
1377 | { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, | |
1378 | { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 }, | |
1379 | { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 }, | |
1380 | { BUBBLE, "MPS Tx underflow", -1, 1 }, | |
1381 | { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, | |
1382 | { FRMERR, "MPS Tx framing error", -1, 1 }, | |
1383 | { 0 } | |
1384 | }; | |
005b5717 | 1385 | static const struct intr_info mps_trc_intr_info[] = { |
56d36be4 DM |
1386 | { FILTMEM, "MPS TRC filter parity error", -1, 1 }, |
1387 | { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 }, | |
1388 | { MISCPERR, "MPS TRC misc parity error", -1, 1 }, | |
1389 | { 0 } | |
1390 | }; | |
005b5717 | 1391 | static const struct intr_info mps_stat_sram_intr_info[] = { |
56d36be4 DM |
1392 | { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, |
1393 | { 0 } | |
1394 | }; | |
005b5717 | 1395 | static const struct intr_info mps_stat_tx_intr_info[] = { |
56d36be4 DM |
1396 | { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, |
1397 | { 0 } | |
1398 | }; | |
005b5717 | 1399 | static const struct intr_info mps_stat_rx_intr_info[] = { |
56d36be4 DM |
1400 | { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, |
1401 | { 0 } | |
1402 | }; | |
005b5717 | 1403 | static const struct intr_info mps_cls_intr_info[] = { |
56d36be4 DM |
1404 | { MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, |
1405 | { MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, | |
1406 | { HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, | |
1407 | { 0 } | |
1408 | }; | |
1409 | ||
1410 | int fat; | |
1411 | ||
1412 | fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE, | |
1413 | mps_rx_intr_info) + | |
1414 | t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE, | |
1415 | mps_tx_intr_info) + | |
1416 | t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE, | |
1417 | mps_trc_intr_info) + | |
1418 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM, | |
1419 | mps_stat_sram_intr_info) + | |
1420 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO, | |
1421 | mps_stat_tx_intr_info) + | |
1422 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO, | |
1423 | mps_stat_rx_intr_info) + | |
1424 | t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE, | |
1425 | mps_cls_intr_info); | |
1426 | ||
1427 | t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT | | |
1428 | RXINT | TXINT | STATINT); | |
1429 | t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */ | |
1430 | if (fat) | |
1431 | t4_fatal_err(adapter); | |
1432 | } | |
1433 | ||
1434 | #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE) | |
1435 | ||
1436 | /* | |
1437 | * EDC/MC interrupt handler. | |
1438 | */ | |
1439 | static void mem_intr_handler(struct adapter *adapter, int idx) | |
1440 | { | |
1441 | static const char name[3][5] = { "EDC0", "EDC1", "MC" }; | |
1442 | ||
1443 | unsigned int addr, cnt_addr, v; | |
1444 | ||
1445 | if (idx <= MEM_EDC1) { | |
1446 | addr = EDC_REG(EDC_INT_CAUSE, idx); | |
1447 | cnt_addr = EDC_REG(EDC_ECC_STATUS, idx); | |
1448 | } else { | |
1449 | addr = MC_INT_CAUSE; | |
1450 | cnt_addr = MC_ECC_STATUS; | |
1451 | } | |
1452 | ||
1453 | v = t4_read_reg(adapter, addr) & MEM_INT_MASK; | |
1454 | if (v & PERR_INT_CAUSE) | |
1455 | dev_alert(adapter->pdev_dev, "%s FIFO parity error\n", | |
1456 | name[idx]); | |
1457 | if (v & ECC_CE_INT_CAUSE) { | |
1458 | u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr)); | |
1459 | ||
1460 | t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK); | |
1461 | if (printk_ratelimit()) | |
1462 | dev_warn(adapter->pdev_dev, | |
1463 | "%u %s correctable ECC data error%s\n", | |
1464 | cnt, name[idx], cnt > 1 ? "s" : ""); | |
1465 | } | |
1466 | if (v & ECC_UE_INT_CAUSE) | |
1467 | dev_alert(adapter->pdev_dev, | |
1468 | "%s uncorrectable ECC data error\n", name[idx]); | |
1469 | ||
1470 | t4_write_reg(adapter, addr, v); | |
1471 | if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE)) | |
1472 | t4_fatal_err(adapter); | |
1473 | } | |
1474 | ||
1475 | /* | |
1476 | * MA interrupt handler. | |
1477 | */ | |
1478 | static void ma_intr_handler(struct adapter *adap) | |
1479 | { | |
1480 | u32 v, status = t4_read_reg(adap, MA_INT_CAUSE); | |
1481 | ||
1482 | if (status & MEM_PERR_INT_CAUSE) | |
1483 | dev_alert(adap->pdev_dev, | |
1484 | "MA parity error, parity status %#x\n", | |
1485 | t4_read_reg(adap, MA_PARITY_ERROR_STATUS)); | |
1486 | if (status & MEM_WRAP_INT_CAUSE) { | |
1487 | v = t4_read_reg(adap, MA_INT_WRAP_STATUS); | |
1488 | dev_alert(adap->pdev_dev, "MA address wrap-around error by " | |
1489 | "client %u to address %#x\n", | |
1490 | MEM_WRAP_CLIENT_NUM_GET(v), | |
1491 | MEM_WRAP_ADDRESS_GET(v) << 4); | |
1492 | } | |
1493 | t4_write_reg(adap, MA_INT_CAUSE, status); | |
1494 | t4_fatal_err(adap); | |
1495 | } | |
1496 | ||
1497 | /* | |
1498 | * SMB interrupt handler. | |
1499 | */ | |
1500 | static void smb_intr_handler(struct adapter *adap) | |
1501 | { | |
005b5717 | 1502 | static const struct intr_info smb_intr_info[] = { |
56d36be4 DM |
1503 | { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, |
1504 | { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, | |
1505 | { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, | |
1506 | { 0 } | |
1507 | }; | |
1508 | ||
1509 | if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info)) | |
1510 | t4_fatal_err(adap); | |
1511 | } | |
1512 | ||
1513 | /* | |
1514 | * NC-SI interrupt handler. | |
1515 | */ | |
1516 | static void ncsi_intr_handler(struct adapter *adap) | |
1517 | { | |
005b5717 | 1518 | static const struct intr_info ncsi_intr_info[] = { |
56d36be4 DM |
1519 | { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, |
1520 | { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, | |
1521 | { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, | |
1522 | { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, | |
1523 | { 0 } | |
1524 | }; | |
1525 | ||
1526 | if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info)) | |
1527 | t4_fatal_err(adap); | |
1528 | } | |
1529 | ||
1530 | /* | |
1531 | * XGMAC interrupt handler. | |
1532 | */ | |
1533 | static void xgmac_intr_handler(struct adapter *adap, int port) | |
1534 | { | |
1535 | u32 v = t4_read_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE)); | |
1536 | ||
1537 | v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR; | |
1538 | if (!v) | |
1539 | return; | |
1540 | ||
1541 | if (v & TXFIFO_PRTY_ERR) | |
1542 | dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", | |
1543 | port); | |
1544 | if (v & RXFIFO_PRTY_ERR) | |
1545 | dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", | |
1546 | port); | |
1547 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v); | |
1548 | t4_fatal_err(adap); | |
1549 | } | |
1550 | ||
1551 | /* | |
1552 | * PL interrupt handler. | |
1553 | */ | |
1554 | static void pl_intr_handler(struct adapter *adap) | |
1555 | { | |
005b5717 | 1556 | static const struct intr_info pl_intr_info[] = { |
56d36be4 DM |
1557 | { FATALPERR, "T4 fatal parity error", -1, 1 }, |
1558 | { PERRVFID, "PL VFID_MAP parity error", -1, 1 }, | |
1559 | { 0 } | |
1560 | }; | |
1561 | ||
1562 | if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info)) | |
1563 | t4_fatal_err(adap); | |
1564 | } | |
1565 | ||
63bcceec | 1566 | #define PF_INTR_MASK (PFSW) |
56d36be4 DM |
1567 | #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \ |
1568 | EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \ | |
1569 | CPL_SWITCH | SGE | ULP_TX) | |
1570 | ||
1571 | /** | |
1572 | * t4_slow_intr_handler - control path interrupt handler | |
1573 | * @adapter: the adapter | |
1574 | * | |
1575 | * T4 interrupt handler for non-data global interrupt events, e.g., errors. | |
1576 | * The designation 'slow' is because it involves register reads, while | |
1577 | * data interrupts typically don't involve any MMIOs. | |
1578 | */ | |
1579 | int t4_slow_intr_handler(struct adapter *adapter) | |
1580 | { | |
1581 | u32 cause = t4_read_reg(adapter, PL_INT_CAUSE); | |
1582 | ||
1583 | if (!(cause & GLBL_INTR_MASK)) | |
1584 | return 0; | |
1585 | if (cause & CIM) | |
1586 | cim_intr_handler(adapter); | |
1587 | if (cause & MPS) | |
1588 | mps_intr_handler(adapter); | |
1589 | if (cause & NCSI) | |
1590 | ncsi_intr_handler(adapter); | |
1591 | if (cause & PL) | |
1592 | pl_intr_handler(adapter); | |
1593 | if (cause & SMB) | |
1594 | smb_intr_handler(adapter); | |
1595 | if (cause & XGMAC0) | |
1596 | xgmac_intr_handler(adapter, 0); | |
1597 | if (cause & XGMAC1) | |
1598 | xgmac_intr_handler(adapter, 1); | |
1599 | if (cause & XGMAC_KR0) | |
1600 | xgmac_intr_handler(adapter, 2); | |
1601 | if (cause & XGMAC_KR1) | |
1602 | xgmac_intr_handler(adapter, 3); | |
1603 | if (cause & PCIE) | |
1604 | pcie_intr_handler(adapter); | |
1605 | if (cause & MC) | |
1606 | mem_intr_handler(adapter, MEM_MC); | |
1607 | if (cause & EDC0) | |
1608 | mem_intr_handler(adapter, MEM_EDC0); | |
1609 | if (cause & EDC1) | |
1610 | mem_intr_handler(adapter, MEM_EDC1); | |
1611 | if (cause & LE) | |
1612 | le_intr_handler(adapter); | |
1613 | if (cause & TP) | |
1614 | tp_intr_handler(adapter); | |
1615 | if (cause & MA) | |
1616 | ma_intr_handler(adapter); | |
1617 | if (cause & PM_TX) | |
1618 | pmtx_intr_handler(adapter); | |
1619 | if (cause & PM_RX) | |
1620 | pmrx_intr_handler(adapter); | |
1621 | if (cause & ULP_RX) | |
1622 | ulprx_intr_handler(adapter); | |
1623 | if (cause & CPL_SWITCH) | |
1624 | cplsw_intr_handler(adapter); | |
1625 | if (cause & SGE) | |
1626 | sge_intr_handler(adapter); | |
1627 | if (cause & ULP_TX) | |
1628 | ulptx_intr_handler(adapter); | |
1629 | ||
1630 | /* Clear the interrupts just processed for which we are the master. */ | |
1631 | t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK); | |
1632 | (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */ | |
1633 | return 1; | |
1634 | } | |
1635 | ||
1636 | /** | |
1637 | * t4_intr_enable - enable interrupts | |
1638 | * @adapter: the adapter whose interrupts should be enabled | |
1639 | * | |
1640 | * Enable PF-specific interrupts for the calling function and the top-level | |
1641 | * interrupt concentrator for global interrupts. Interrupts are already | |
1642 | * enabled at each module, here we just enable the roots of the interrupt | |
1643 | * hierarchies. | |
1644 | * | |
1645 | * Note: this function should be called only when the driver manages | |
1646 | * non PF-specific interrupts from the various HW modules. Only one PCI | |
1647 | * function at a time should be doing this. | |
1648 | */ | |
1649 | void t4_intr_enable(struct adapter *adapter) | |
1650 | { | |
1651 | u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI)); | |
1652 | ||
1653 | t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE | | |
1654 | ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 | | |
1655 | ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 | | |
1656 | ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 | | |
1657 | ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 | | |
1658 | ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO | | |
1659 | ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR | | |
840f3000 | 1660 | DBFIFO_HP_INT | DBFIFO_LP_INT | |
56d36be4 DM |
1661 | EGRESS_SIZE_ERR); |
1662 | t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK); | |
1663 | t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf); | |
1664 | } | |
1665 | ||
1666 | /** | |
1667 | * t4_intr_disable - disable interrupts | |
1668 | * @adapter: the adapter whose interrupts should be disabled | |
1669 | * | |
1670 | * Disable interrupts. We only disable the top-level interrupt | |
1671 | * concentrators. The caller must be a PCI function managing global | |
1672 | * interrupts. | |
1673 | */ | |
1674 | void t4_intr_disable(struct adapter *adapter) | |
1675 | { | |
1676 | u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI)); | |
1677 | ||
1678 | t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0); | |
1679 | t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0); | |
1680 | } | |
1681 | ||
56d36be4 DM |
1682 | /** |
1683 | * hash_mac_addr - return the hash value of a MAC address | |
1684 | * @addr: the 48-bit Ethernet MAC address | |
1685 | * | |
1686 | * Hashes a MAC address according to the hash function used by HW inexact | |
1687 | * (hash) address matching. | |
1688 | */ | |
1689 | static int hash_mac_addr(const u8 *addr) | |
1690 | { | |
1691 | u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; | |
1692 | u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; | |
1693 | a ^= b; | |
1694 | a ^= (a >> 12); | |
1695 | a ^= (a >> 6); | |
1696 | return a & 0x3f; | |
1697 | } | |
1698 | ||
1699 | /** | |
1700 | * t4_config_rss_range - configure a portion of the RSS mapping table | |
1701 | * @adapter: the adapter | |
1702 | * @mbox: mbox to use for the FW command | |
1703 | * @viid: virtual interface whose RSS subtable is to be written | |
1704 | * @start: start entry in the table to write | |
1705 | * @n: how many table entries to write | |
1706 | * @rspq: values for the response queue lookup table | |
1707 | * @nrspq: number of values in @rspq | |
1708 | * | |
1709 | * Programs the selected part of the VI's RSS mapping table with the | |
1710 | * provided values. If @nrspq < @n the supplied values are used repeatedly | |
1711 | * until the full table range is populated. | |
1712 | * | |
1713 | * The caller must ensure the values in @rspq are in the range allowed for | |
1714 | * @viid. | |
1715 | */ | |
1716 | int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, | |
1717 | int start, int n, const u16 *rspq, unsigned int nrspq) | |
1718 | { | |
1719 | int ret; | |
1720 | const u16 *rsp = rspq; | |
1721 | const u16 *rsp_end = rspq + nrspq; | |
1722 | struct fw_rss_ind_tbl_cmd cmd; | |
1723 | ||
1724 | memset(&cmd, 0, sizeof(cmd)); | |
1725 | cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) | | |
1726 | FW_CMD_REQUEST | FW_CMD_WRITE | | |
1727 | FW_RSS_IND_TBL_CMD_VIID(viid)); | |
1728 | cmd.retval_len16 = htonl(FW_LEN16(cmd)); | |
1729 | ||
1730 | /* each fw_rss_ind_tbl_cmd takes up to 32 entries */ | |
1731 | while (n > 0) { | |
1732 | int nq = min(n, 32); | |
1733 | __be32 *qp = &cmd.iq0_to_iq2; | |
1734 | ||
1735 | cmd.niqid = htons(nq); | |
1736 | cmd.startidx = htons(start); | |
1737 | ||
1738 | start += nq; | |
1739 | n -= nq; | |
1740 | ||
1741 | while (nq > 0) { | |
1742 | unsigned int v; | |
1743 | ||
1744 | v = FW_RSS_IND_TBL_CMD_IQ0(*rsp); | |
1745 | if (++rsp >= rsp_end) | |
1746 | rsp = rspq; | |
1747 | v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp); | |
1748 | if (++rsp >= rsp_end) | |
1749 | rsp = rspq; | |
1750 | v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp); | |
1751 | if (++rsp >= rsp_end) | |
1752 | rsp = rspq; | |
1753 | ||
1754 | *qp++ = htonl(v); | |
1755 | nq -= 3; | |
1756 | } | |
1757 | ||
1758 | ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); | |
1759 | if (ret) | |
1760 | return ret; | |
1761 | } | |
1762 | return 0; | |
1763 | } | |
1764 | ||
1765 | /** | |
1766 | * t4_config_glbl_rss - configure the global RSS mode | |
1767 | * @adapter: the adapter | |
1768 | * @mbox: mbox to use for the FW command | |
1769 | * @mode: global RSS mode | |
1770 | * @flags: mode-specific flags | |
1771 | * | |
1772 | * Sets the global RSS mode. | |
1773 | */ | |
1774 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, | |
1775 | unsigned int flags) | |
1776 | { | |
1777 | struct fw_rss_glb_config_cmd c; | |
1778 | ||
1779 | memset(&c, 0, sizeof(c)); | |
1780 | c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | | |
1781 | FW_CMD_REQUEST | FW_CMD_WRITE); | |
1782 | c.retval_len16 = htonl(FW_LEN16(c)); | |
1783 | if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { | |
1784 | c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode)); | |
1785 | } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { | |
1786 | c.u.basicvirtual.mode_pkd = | |
1787 | htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode)); | |
1788 | c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags); | |
1789 | } else | |
1790 | return -EINVAL; | |
1791 | return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); | |
1792 | } | |
1793 | ||
56d36be4 DM |
1794 | /** |
1795 | * t4_tp_get_tcp_stats - read TP's TCP MIB counters | |
1796 | * @adap: the adapter | |
1797 | * @v4: holds the TCP/IP counter values | |
1798 | * @v6: holds the TCP/IPv6 counter values | |
1799 | * | |
1800 | * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. | |
1801 | * Either @v4 or @v6 may be %NULL to skip the corresponding stats. | |
1802 | */ | |
1803 | void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, | |
1804 | struct tp_tcp_stats *v6) | |
1805 | { | |
1806 | u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1]; | |
1807 | ||
1808 | #define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST) | |
1809 | #define STAT(x) val[STAT_IDX(x)] | |
1810 | #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) | |
1811 | ||
1812 | if (v4) { | |
1813 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val, | |
1814 | ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST); | |
1815 | v4->tcpOutRsts = STAT(OUT_RST); | |
1816 | v4->tcpInSegs = STAT64(IN_SEG); | |
1817 | v4->tcpOutSegs = STAT64(OUT_SEG); | |
1818 | v4->tcpRetransSegs = STAT64(RXT_SEG); | |
1819 | } | |
1820 | if (v6) { | |
1821 | t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val, | |
1822 | ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST); | |
1823 | v6->tcpOutRsts = STAT(OUT_RST); | |
1824 | v6->tcpInSegs = STAT64(IN_SEG); | |
1825 | v6->tcpOutSegs = STAT64(OUT_SEG); | |
1826 | v6->tcpRetransSegs = STAT64(RXT_SEG); | |
1827 | } | |
1828 | #undef STAT64 | |
1829 | #undef STAT | |
1830 | #undef STAT_IDX | |
1831 | } | |
1832 | ||
56d36be4 DM |
1833 | /** |
1834 | * t4_read_mtu_tbl - returns the values in the HW path MTU table | |
1835 | * @adap: the adapter | |
1836 | * @mtus: where to store the MTU values | |
1837 | * @mtu_log: where to store the MTU base-2 log (may be %NULL) | |
1838 | * | |
1839 | * Reads the HW path MTU table. | |
1840 | */ | |
1841 | void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) | |
1842 | { | |
1843 | u32 v; | |
1844 | int i; | |
1845 | ||
1846 | for (i = 0; i < NMTUS; ++i) { | |
1847 | t4_write_reg(adap, TP_MTU_TABLE, | |
1848 | MTUINDEX(0xff) | MTUVALUE(i)); | |
1849 | v = t4_read_reg(adap, TP_MTU_TABLE); | |
1850 | mtus[i] = MTUVALUE_GET(v); | |
1851 | if (mtu_log) | |
1852 | mtu_log[i] = MTUWIDTH_GET(v); | |
1853 | } | |
1854 | } | |
1855 | ||
1856 | /** | |
1857 | * init_cong_ctrl - initialize congestion control parameters | |
1858 | * @a: the alpha values for congestion control | |
1859 | * @b: the beta values for congestion control | |
1860 | * | |
1861 | * Initialize the congestion control parameters. | |
1862 | */ | |
1863 | static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b) | |
1864 | { | |
1865 | a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; | |
1866 | a[9] = 2; | |
1867 | a[10] = 3; | |
1868 | a[11] = 4; | |
1869 | a[12] = 5; | |
1870 | a[13] = 6; | |
1871 | a[14] = 7; | |
1872 | a[15] = 8; | |
1873 | a[16] = 9; | |
1874 | a[17] = 10; | |
1875 | a[18] = 14; | |
1876 | a[19] = 17; | |
1877 | a[20] = 21; | |
1878 | a[21] = 25; | |
1879 | a[22] = 30; | |
1880 | a[23] = 35; | |
1881 | a[24] = 45; | |
1882 | a[25] = 60; | |
1883 | a[26] = 80; | |
1884 | a[27] = 100; | |
1885 | a[28] = 200; | |
1886 | a[29] = 300; | |
1887 | a[30] = 400; | |
1888 | a[31] = 500; | |
1889 | ||
1890 | b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; | |
1891 | b[9] = b[10] = 1; | |
1892 | b[11] = b[12] = 2; | |
1893 | b[13] = b[14] = b[15] = b[16] = 3; | |
1894 | b[17] = b[18] = b[19] = b[20] = b[21] = 4; | |
1895 | b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; | |
1896 | b[28] = b[29] = 6; | |
1897 | b[30] = b[31] = 7; | |
1898 | } | |
1899 | ||
1900 | /* The minimum additive increment value for the congestion control table */ | |
1901 | #define CC_MIN_INCR 2U | |
1902 | ||
1903 | /** | |
1904 | * t4_load_mtus - write the MTU and congestion control HW tables | |
1905 | * @adap: the adapter | |
1906 | * @mtus: the values for the MTU table | |
1907 | * @alpha: the values for the congestion control alpha parameter | |
1908 | * @beta: the values for the congestion control beta parameter | |
1909 | * | |
1910 | * Write the HW MTU table with the supplied MTUs and the high-speed | |
1911 | * congestion control table with the supplied alpha, beta, and MTUs. | |
1912 | * We write the two tables together because the additive increments | |
1913 | * depend on the MTUs. | |
1914 | */ | |
1915 | void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, | |
1916 | const unsigned short *alpha, const unsigned short *beta) | |
1917 | { | |
1918 | static const unsigned int avg_pkts[NCCTRL_WIN] = { | |
1919 | 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, | |
1920 | 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, | |
1921 | 28672, 40960, 57344, 81920, 114688, 163840, 229376 | |
1922 | }; | |
1923 | ||
1924 | unsigned int i, w; | |
1925 | ||
1926 | for (i = 0; i < NMTUS; ++i) { | |
1927 | unsigned int mtu = mtus[i]; | |
1928 | unsigned int log2 = fls(mtu); | |
1929 | ||
1930 | if (!(mtu & ((1 << log2) >> 2))) /* round */ | |
1931 | log2--; | |
1932 | t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) | | |
1933 | MTUWIDTH(log2) | MTUVALUE(mtu)); | |
1934 | ||
1935 | for (w = 0; w < NCCTRL_WIN; ++w) { | |
1936 | unsigned int inc; | |
1937 | ||
1938 | inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], | |
1939 | CC_MIN_INCR); | |
1940 | ||
1941 | t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) | | |
1942 | (w << 16) | (beta[w] << 13) | inc); | |
1943 | } | |
1944 | } | |
1945 | } | |
1946 | ||
56d36be4 DM |
1947 | /** |
1948 | * get_mps_bg_map - return the buffer groups associated with a port | |
1949 | * @adap: the adapter | |
1950 | * @idx: the port index | |
1951 | * | |
1952 | * Returns a bitmap indicating which MPS buffer groups are associated | |
1953 | * with the given port. Bit i is set if buffer group i is used by the | |
1954 | * port. | |
1955 | */ | |
1956 | static unsigned int get_mps_bg_map(struct adapter *adap, int idx) | |
1957 | { | |
1958 | u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL)); | |
1959 | ||
1960 | if (n == 0) | |
1961 | return idx == 0 ? 0xf : 0; | |
1962 | if (n == 1) | |
1963 | return idx < 2 ? (3 << (2 * idx)) : 0; | |
1964 | return 1 << idx; | |
1965 | } | |
1966 | ||
1967 | /** | |
1968 | * t4_get_port_stats - collect port statistics | |
1969 | * @adap: the adapter | |
1970 | * @idx: the port index | |
1971 | * @p: the stats structure to fill | |
1972 | * | |
1973 | * Collect statistics related to the given port from HW. | |
1974 | */ | |
1975 | void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) | |
1976 | { | |
1977 | u32 bgmap = get_mps_bg_map(adap, idx); | |
1978 | ||
1979 | #define GET_STAT(name) \ | |
1980 | t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_##name##_L)) | |
1981 | #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) | |
1982 | ||
1983 | p->tx_octets = GET_STAT(TX_PORT_BYTES); | |
1984 | p->tx_frames = GET_STAT(TX_PORT_FRAMES); | |
1985 | p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); | |
1986 | p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); | |
1987 | p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); | |
1988 | p->tx_error_frames = GET_STAT(TX_PORT_ERROR); | |
1989 | p->tx_frames_64 = GET_STAT(TX_PORT_64B); | |
1990 | p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); | |
1991 | p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); | |
1992 | p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); | |
1993 | p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); | |
1994 | p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); | |
1995 | p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); | |
1996 | p->tx_drop = GET_STAT(TX_PORT_DROP); | |
1997 | p->tx_pause = GET_STAT(TX_PORT_PAUSE); | |
1998 | p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); | |
1999 | p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); | |
2000 | p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); | |
2001 | p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); | |
2002 | p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); | |
2003 | p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); | |
2004 | p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); | |
2005 | p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); | |
2006 | ||
2007 | p->rx_octets = GET_STAT(RX_PORT_BYTES); | |
2008 | p->rx_frames = GET_STAT(RX_PORT_FRAMES); | |
2009 | p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); | |
2010 | p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); | |
2011 | p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); | |
2012 | p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); | |
2013 | p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); | |
2014 | p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); | |
2015 | p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); | |
2016 | p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); | |
2017 | p->rx_runt = GET_STAT(RX_PORT_LESS_64B); | |
2018 | p->rx_frames_64 = GET_STAT(RX_PORT_64B); | |
2019 | p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); | |
2020 | p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); | |
2021 | p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); | |
2022 | p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); | |
2023 | p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); | |
2024 | p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); | |
2025 | p->rx_pause = GET_STAT(RX_PORT_PAUSE); | |
2026 | p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); | |
2027 | p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); | |
2028 | p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); | |
2029 | p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); | |
2030 | p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); | |
2031 | p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); | |
2032 | p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); | |
2033 | p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); | |
2034 | ||
2035 | p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; | |
2036 | p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; | |
2037 | p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; | |
2038 | p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; | |
2039 | p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; | |
2040 | p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; | |
2041 | p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; | |
2042 | p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; | |
2043 | ||
2044 | #undef GET_STAT | |
2045 | #undef GET_STAT_COM | |
2046 | } | |
2047 | ||
56d36be4 DM |
2048 | /** |
2049 | * t4_wol_magic_enable - enable/disable magic packet WoL | |
2050 | * @adap: the adapter | |
2051 | * @port: the physical port index | |
2052 | * @addr: MAC address expected in magic packets, %NULL to disable | |
2053 | * | |
2054 | * Enables/disables magic packet wake-on-LAN for the selected port. | |
2055 | */ | |
2056 | void t4_wol_magic_enable(struct adapter *adap, unsigned int port, | |
2057 | const u8 *addr) | |
2058 | { | |
2059 | if (addr) { | |
2060 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO), | |
2061 | (addr[2] << 24) | (addr[3] << 16) | | |
2062 | (addr[4] << 8) | addr[5]); | |
2063 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI), | |
2064 | (addr[0] << 8) | addr[1]); | |
2065 | } | |
2066 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), MAGICEN, | |
2067 | addr ? MAGICEN : 0); | |
2068 | } | |
2069 | ||
2070 | /** | |
2071 | * t4_wol_pat_enable - enable/disable pattern-based WoL | |
2072 | * @adap: the adapter | |
2073 | * @port: the physical port index | |
2074 | * @map: bitmap of which HW pattern filters to set | |
2075 | * @mask0: byte mask for bytes 0-63 of a packet | |
2076 | * @mask1: byte mask for bytes 64-127 of a packet | |
2077 | * @crc: Ethernet CRC for selected bytes | |
2078 | * @enable: enable/disable switch | |
2079 | * | |
2080 | * Sets the pattern filters indicated in @map to mask out the bytes | |
2081 | * specified in @mask0/@mask1 in received packets and compare the CRC of | |
2082 | * the resulting packet against @crc. If @enable is %true pattern-based | |
2083 | * WoL is enabled, otherwise disabled. | |
2084 | */ | |
2085 | int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, | |
2086 | u64 mask0, u64 mask1, unsigned int crc, bool enable) | |
2087 | { | |
2088 | int i; | |
2089 | ||
2090 | if (!enable) { | |
2091 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), | |
2092 | PATEN, 0); | |
2093 | return 0; | |
2094 | } | |
2095 | if (map > 0xff) | |
2096 | return -EINVAL; | |
2097 | ||
2098 | #define EPIO_REG(name) PORT_REG(port, XGMAC_PORT_EPIO_##name) | |
2099 | ||
2100 | t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); | |
2101 | t4_write_reg(adap, EPIO_REG(DATA2), mask1); | |
2102 | t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); | |
2103 | ||
2104 | for (i = 0; i < NWOL_PAT; i++, map >>= 1) { | |
2105 | if (!(map & 1)) | |
2106 | continue; | |
2107 | ||
2108 | /* write byte masks */ | |
2109 | t4_write_reg(adap, EPIO_REG(DATA0), mask0); | |
2110 | t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR); | |
2111 | t4_read_reg(adap, EPIO_REG(OP)); /* flush */ | |
2112 | if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY) | |
2113 | return -ETIMEDOUT; | |
2114 | ||
2115 | /* write CRC */ | |
2116 | t4_write_reg(adap, EPIO_REG(DATA0), crc); | |
2117 | t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR); | |
2118 | t4_read_reg(adap, EPIO_REG(OP)); /* flush */ | |
2119 | if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY) | |
2120 | return -ETIMEDOUT; | |
2121 | } | |
2122 | #undef EPIO_REG | |
2123 | ||
2124 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN); | |
2125 | return 0; | |
2126 | } | |
2127 | ||
2128 | #define INIT_CMD(var, cmd, rd_wr) do { \ | |
2129 | (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \ | |
2130 | FW_CMD_REQUEST | FW_CMD_##rd_wr); \ | |
2131 | (var).retval_len16 = htonl(FW_LEN16(var)); \ | |
2132 | } while (0) | |
2133 | ||
8caa1e84 VP |
2134 | int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, |
2135 | u32 addr, u32 val) | |
2136 | { | |
2137 | struct fw_ldst_cmd c; | |
2138 | ||
2139 | memset(&c, 0, sizeof(c)); | |
2140 | c.op_to_addrspace = htonl(V_FW_CMD_OP(FW_LDST_CMD) | F_FW_CMD_REQUEST | | |
2141 | F_FW_CMD_WRITE | | |
2142 | V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE)); | |
2143 | c.cycles_to_len16 = htonl(FW_LEN16(c)); | |
2144 | c.u.addrval.addr = htonl(addr); | |
2145 | c.u.addrval.val = htonl(val); | |
2146 | ||
2147 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2148 | } | |
2149 | ||
49ce9c2c | 2150 | /** |
8caa1e84 VP |
2151 | * t4_mem_win_read_len - read memory through PCIE memory window |
2152 | * @adap: the adapter | |
2153 | * @addr: address of first byte requested aligned on 32b. | |
2154 | * @data: len bytes to hold the data read | |
2155 | * @len: amount of data to read from window. Must be <= | |
2156 | * MEMWIN0_APERATURE after adjusting for 16B alignment | |
2157 | * requirements of the the memory window. | |
2158 | * | |
2159 | * Read len bytes of data from MC starting at @addr. | |
2160 | */ | |
2161 | int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len) | |
2162 | { | |
2163 | int i; | |
2164 | int off; | |
2165 | ||
2166 | /* | |
2167 | * Align on a 16B boundary. | |
2168 | */ | |
2169 | off = addr & 15; | |
2170 | if ((addr & 3) || (len + off) > MEMWIN0_APERTURE) | |
2171 | return -EINVAL; | |
2172 | ||
840f3000 VP |
2173 | t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, addr & ~15); |
2174 | t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET); | |
8caa1e84 VP |
2175 | |
2176 | for (i = 0; i < len; i += 4) | |
2177 | *data++ = t4_read_reg(adap, (MEMWIN0_BASE + off + i)); | |
2178 | ||
2179 | return 0; | |
2180 | } | |
2181 | ||
56d36be4 DM |
2182 | /** |
2183 | * t4_mdio_rd - read a PHY register through MDIO | |
2184 | * @adap: the adapter | |
2185 | * @mbox: mailbox to use for the FW command | |
2186 | * @phy_addr: the PHY address | |
2187 | * @mmd: the PHY MMD to access (0 for clause 22 PHYs) | |
2188 | * @reg: the register to read | |
2189 | * @valp: where to store the value | |
2190 | * | |
2191 | * Issues a FW command through the given mailbox to read a PHY register. | |
2192 | */ | |
2193 | int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
2194 | unsigned int mmd, unsigned int reg, u16 *valp) | |
2195 | { | |
2196 | int ret; | |
2197 | struct fw_ldst_cmd c; | |
2198 | ||
2199 | memset(&c, 0, sizeof(c)); | |
2200 | c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST | | |
2201 | FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO)); | |
2202 | c.cycles_to_len16 = htonl(FW_LEN16(c)); | |
2203 | c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) | | |
2204 | FW_LDST_CMD_MMD(mmd)); | |
2205 | c.u.mdio.raddr = htons(reg); | |
2206 | ||
2207 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
2208 | if (ret == 0) | |
2209 | *valp = ntohs(c.u.mdio.rval); | |
2210 | return ret; | |
2211 | } | |
2212 | ||
2213 | /** | |
2214 | * t4_mdio_wr - write a PHY register through MDIO | |
2215 | * @adap: the adapter | |
2216 | * @mbox: mailbox to use for the FW command | |
2217 | * @phy_addr: the PHY address | |
2218 | * @mmd: the PHY MMD to access (0 for clause 22 PHYs) | |
2219 | * @reg: the register to write | |
2220 | * @valp: value to write | |
2221 | * | |
2222 | * Issues a FW command through the given mailbox to write a PHY register. | |
2223 | */ | |
2224 | int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
2225 | unsigned int mmd, unsigned int reg, u16 val) | |
2226 | { | |
2227 | struct fw_ldst_cmd c; | |
2228 | ||
2229 | memset(&c, 0, sizeof(c)); | |
2230 | c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST | | |
2231 | FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO)); | |
2232 | c.cycles_to_len16 = htonl(FW_LEN16(c)); | |
2233 | c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) | | |
2234 | FW_LDST_CMD_MMD(mmd)); | |
2235 | c.u.mdio.raddr = htons(reg); | |
2236 | c.u.mdio.rval = htons(val); | |
2237 | ||
2238 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2239 | } | |
2240 | ||
2241 | /** | |
2242 | * t4_fw_hello - establish communication with FW | |
2243 | * @adap: the adapter | |
2244 | * @mbox: mailbox to use for the FW command | |
2245 | * @evt_mbox: mailbox to receive async FW events | |
2246 | * @master: specifies the caller's willingness to be the device master | |
2247 | * @state: returns the current device state | |
2248 | * | |
2249 | * Issues a command to establish communication with FW. | |
2250 | */ | |
2251 | int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, | |
2252 | enum dev_master master, enum dev_state *state) | |
2253 | { | |
2254 | int ret; | |
2255 | struct fw_hello_cmd c; | |
2256 | ||
2257 | INIT_CMD(c, HELLO, WRITE); | |
2258 | c.err_to_mbasyncnot = htonl( | |
2259 | FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | | |
2260 | FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | | |
2261 | FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox : 0xff) | | |
2262 | FW_HELLO_CMD_MBASYNCNOT(evt_mbox)); | |
2263 | ||
2264 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
2265 | if (ret == 0 && state) { | |
2266 | u32 v = ntohl(c.err_to_mbasyncnot); | |
2267 | if (v & FW_HELLO_CMD_INIT) | |
2268 | *state = DEV_STATE_INIT; | |
2269 | else if (v & FW_HELLO_CMD_ERR) | |
2270 | *state = DEV_STATE_ERR; | |
2271 | else | |
2272 | *state = DEV_STATE_UNINIT; | |
2273 | } | |
2274 | return ret; | |
2275 | } | |
2276 | ||
2277 | /** | |
2278 | * t4_fw_bye - end communication with FW | |
2279 | * @adap: the adapter | |
2280 | * @mbox: mailbox to use for the FW command | |
2281 | * | |
2282 | * Issues a command to terminate communication with FW. | |
2283 | */ | |
2284 | int t4_fw_bye(struct adapter *adap, unsigned int mbox) | |
2285 | { | |
2286 | struct fw_bye_cmd c; | |
2287 | ||
2288 | INIT_CMD(c, BYE, WRITE); | |
2289 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2290 | } | |
2291 | ||
2292 | /** | |
2293 | * t4_init_cmd - ask FW to initialize the device | |
2294 | * @adap: the adapter | |
2295 | * @mbox: mailbox to use for the FW command | |
2296 | * | |
2297 | * Issues a command to FW to partially initialize the device. This | |
2298 | * performs initialization that generally doesn't depend on user input. | |
2299 | */ | |
2300 | int t4_early_init(struct adapter *adap, unsigned int mbox) | |
2301 | { | |
2302 | struct fw_initialize_cmd c; | |
2303 | ||
2304 | INIT_CMD(c, INITIALIZE, WRITE); | |
2305 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2306 | } | |
2307 | ||
2308 | /** | |
2309 | * t4_fw_reset - issue a reset to FW | |
2310 | * @adap: the adapter | |
2311 | * @mbox: mailbox to use for the FW command | |
2312 | * @reset: specifies the type of reset to perform | |
2313 | * | |
2314 | * Issues a reset command of the specified type to FW. | |
2315 | */ | |
2316 | int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) | |
2317 | { | |
2318 | struct fw_reset_cmd c; | |
2319 | ||
2320 | INIT_CMD(c, RESET, WRITE); | |
2321 | c.val = htonl(reset); | |
2322 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2323 | } | |
2324 | ||
2325 | /** | |
2326 | * t4_query_params - query FW or device parameters | |
2327 | * @adap: the adapter | |
2328 | * @mbox: mailbox to use for the FW command | |
2329 | * @pf: the PF | |
2330 | * @vf: the VF | |
2331 | * @nparams: the number of parameters | |
2332 | * @params: the parameter names | |
2333 | * @val: the parameter values | |
2334 | * | |
2335 | * Reads the value of FW or device parameters. Up to 7 parameters can be | |
2336 | * queried at once. | |
2337 | */ | |
2338 | int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
2339 | unsigned int vf, unsigned int nparams, const u32 *params, | |
2340 | u32 *val) | |
2341 | { | |
2342 | int i, ret; | |
2343 | struct fw_params_cmd c; | |
2344 | __be32 *p = &c.param[0].mnem; | |
2345 | ||
2346 | if (nparams > 7) | |
2347 | return -EINVAL; | |
2348 | ||
2349 | memset(&c, 0, sizeof(c)); | |
2350 | c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST | | |
2351 | FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) | | |
2352 | FW_PARAMS_CMD_VFN(vf)); | |
2353 | c.retval_len16 = htonl(FW_LEN16(c)); | |
2354 | for (i = 0; i < nparams; i++, p += 2) | |
2355 | *p = htonl(*params++); | |
2356 | ||
2357 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
2358 | if (ret == 0) | |
2359 | for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) | |
2360 | *val++ = ntohl(*p); | |
2361 | return ret; | |
2362 | } | |
2363 | ||
2364 | /** | |
2365 | * t4_set_params - sets FW or device parameters | |
2366 | * @adap: the adapter | |
2367 | * @mbox: mailbox to use for the FW command | |
2368 | * @pf: the PF | |
2369 | * @vf: the VF | |
2370 | * @nparams: the number of parameters | |
2371 | * @params: the parameter names | |
2372 | * @val: the parameter values | |
2373 | * | |
2374 | * Sets the value of FW or device parameters. Up to 7 parameters can be | |
2375 | * specified at once. | |
2376 | */ | |
2377 | int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
2378 | unsigned int vf, unsigned int nparams, const u32 *params, | |
2379 | const u32 *val) | |
2380 | { | |
2381 | struct fw_params_cmd c; | |
2382 | __be32 *p = &c.param[0].mnem; | |
2383 | ||
2384 | if (nparams > 7) | |
2385 | return -EINVAL; | |
2386 | ||
2387 | memset(&c, 0, sizeof(c)); | |
2388 | c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST | | |
2389 | FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) | | |
2390 | FW_PARAMS_CMD_VFN(vf)); | |
2391 | c.retval_len16 = htonl(FW_LEN16(c)); | |
2392 | while (nparams--) { | |
2393 | *p++ = htonl(*params++); | |
2394 | *p++ = htonl(*val++); | |
2395 | } | |
2396 | ||
2397 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2398 | } | |
2399 | ||
2400 | /** | |
2401 | * t4_cfg_pfvf - configure PF/VF resource limits | |
2402 | * @adap: the adapter | |
2403 | * @mbox: mailbox to use for the FW command | |
2404 | * @pf: the PF being configured | |
2405 | * @vf: the VF being configured | |
2406 | * @txq: the max number of egress queues | |
2407 | * @txq_eth_ctrl: the max number of egress Ethernet or control queues | |
2408 | * @rxqi: the max number of interrupt-capable ingress queues | |
2409 | * @rxq: the max number of interruptless ingress queues | |
2410 | * @tc: the PCI traffic class | |
2411 | * @vi: the max number of virtual interfaces | |
2412 | * @cmask: the channel access rights mask for the PF/VF | |
2413 | * @pmask: the port access rights mask for the PF/VF | |
2414 | * @nexact: the maximum number of exact MPS filters | |
2415 | * @rcaps: read capabilities | |
2416 | * @wxcaps: write/execute capabilities | |
2417 | * | |
2418 | * Configures resource limits and capabilities for a physical or virtual | |
2419 | * function. | |
2420 | */ | |
2421 | int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
2422 | unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, | |
2423 | unsigned int rxqi, unsigned int rxq, unsigned int tc, | |
2424 | unsigned int vi, unsigned int cmask, unsigned int pmask, | |
2425 | unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) | |
2426 | { | |
2427 | struct fw_pfvf_cmd c; | |
2428 | ||
2429 | memset(&c, 0, sizeof(c)); | |
2430 | c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST | | |
2431 | FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) | | |
2432 | FW_PFVF_CMD_VFN(vf)); | |
2433 | c.retval_len16 = htonl(FW_LEN16(c)); | |
2434 | c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) | | |
2435 | FW_PFVF_CMD_NIQ(rxq)); | |
81323b74 | 2436 | c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) | |
56d36be4 DM |
2437 | FW_PFVF_CMD_PMASK(pmask) | |
2438 | FW_PFVF_CMD_NEQ(txq)); | |
2439 | c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) | | |
2440 | FW_PFVF_CMD_NEXACTF(nexact)); | |
2441 | c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) | | |
2442 | FW_PFVF_CMD_WX_CAPS(wxcaps) | | |
2443 | FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); | |
2444 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2445 | } | |
2446 | ||
2447 | /** | |
2448 | * t4_alloc_vi - allocate a virtual interface | |
2449 | * @adap: the adapter | |
2450 | * @mbox: mailbox to use for the FW command | |
2451 | * @port: physical port associated with the VI | |
2452 | * @pf: the PF owning the VI | |
2453 | * @vf: the VF owning the VI | |
2454 | * @nmac: number of MAC addresses needed (1 to 5) | |
2455 | * @mac: the MAC addresses of the VI | |
2456 | * @rss_size: size of RSS table slice associated with this VI | |
2457 | * | |
2458 | * Allocates a virtual interface for the given physical port. If @mac is | |
2459 | * not %NULL it contains the MAC addresses of the VI as assigned by FW. | |
2460 | * @mac should be large enough to hold @nmac Ethernet addresses, they are | |
2461 | * stored consecutively so the space needed is @nmac * 6 bytes. | |
2462 | * Returns a negative error number or the non-negative VI id. | |
2463 | */ | |
2464 | int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, | |
2465 | unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, | |
2466 | unsigned int *rss_size) | |
2467 | { | |
2468 | int ret; | |
2469 | struct fw_vi_cmd c; | |
2470 | ||
2471 | memset(&c, 0, sizeof(c)); | |
2472 | c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST | | |
2473 | FW_CMD_WRITE | FW_CMD_EXEC | | |
2474 | FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf)); | |
2475 | c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c)); | |
2476 | c.portid_pkd = FW_VI_CMD_PORTID(port); | |
2477 | c.nmac = nmac - 1; | |
2478 | ||
2479 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
2480 | if (ret) | |
2481 | return ret; | |
2482 | ||
2483 | if (mac) { | |
2484 | memcpy(mac, c.mac, sizeof(c.mac)); | |
2485 | switch (nmac) { | |
2486 | case 5: | |
2487 | memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); | |
2488 | case 4: | |
2489 | memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); | |
2490 | case 3: | |
2491 | memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); | |
2492 | case 2: | |
2493 | memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); | |
2494 | } | |
2495 | } | |
2496 | if (rss_size) | |
2497 | *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd)); | |
a0881cab | 2498 | return FW_VI_CMD_VIID_GET(ntohs(c.type_viid)); |
56d36be4 DM |
2499 | } |
2500 | ||
56d36be4 DM |
2501 | /** |
2502 | * t4_set_rxmode - set Rx properties of a virtual interface | |
2503 | * @adap: the adapter | |
2504 | * @mbox: mailbox to use for the FW command | |
2505 | * @viid: the VI id | |
2506 | * @mtu: the new MTU or -1 | |
2507 | * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change | |
2508 | * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change | |
2509 | * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change | |
f8f5aafa | 2510 | * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change |
56d36be4 DM |
2511 | * @sleep_ok: if true we may sleep while awaiting command completion |
2512 | * | |
2513 | * Sets Rx properties of a virtual interface. | |
2514 | */ | |
2515 | int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
f8f5aafa DM |
2516 | int mtu, int promisc, int all_multi, int bcast, int vlanex, |
2517 | bool sleep_ok) | |
56d36be4 DM |
2518 | { |
2519 | struct fw_vi_rxmode_cmd c; | |
2520 | ||
2521 | /* convert to FW values */ | |
2522 | if (mtu < 0) | |
2523 | mtu = FW_RXMODE_MTU_NO_CHG; | |
2524 | if (promisc < 0) | |
2525 | promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK; | |
2526 | if (all_multi < 0) | |
2527 | all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK; | |
2528 | if (bcast < 0) | |
2529 | bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK; | |
f8f5aafa DM |
2530 | if (vlanex < 0) |
2531 | vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK; | |
56d36be4 DM |
2532 | |
2533 | memset(&c, 0, sizeof(c)); | |
2534 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST | | |
2535 | FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid)); | |
2536 | c.retval_len16 = htonl(FW_LEN16(c)); | |
f8f5aafa DM |
2537 | c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU(mtu) | |
2538 | FW_VI_RXMODE_CMD_PROMISCEN(promisc) | | |
2539 | FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | | |
2540 | FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | | |
2541 | FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); | |
56d36be4 DM |
2542 | return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); |
2543 | } | |
2544 | ||
2545 | /** | |
2546 | * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses | |
2547 | * @adap: the adapter | |
2548 | * @mbox: mailbox to use for the FW command | |
2549 | * @viid: the VI id | |
2550 | * @free: if true any existing filters for this VI id are first removed | |
2551 | * @naddr: the number of MAC addresses to allocate filters for (up to 7) | |
2552 | * @addr: the MAC address(es) | |
2553 | * @idx: where to store the index of each allocated filter | |
2554 | * @hash: pointer to hash address filter bitmap | |
2555 | * @sleep_ok: call is allowed to sleep | |
2556 | * | |
2557 | * Allocates an exact-match filter for each of the supplied addresses and | |
2558 | * sets it to the corresponding address. If @idx is not %NULL it should | |
2559 | * have at least @naddr entries, each of which will be set to the index of | |
2560 | * the filter allocated for the corresponding MAC address. If a filter | |
2561 | * could not be allocated for an address its index is set to 0xffff. | |
2562 | * If @hash is not %NULL addresses that fail to allocate an exact filter | |
2563 | * are hashed and update the hash filter bitmap pointed at by @hash. | |
2564 | * | |
2565 | * Returns a negative error number or the number of filters allocated. | |
2566 | */ | |
2567 | int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, | |
2568 | unsigned int viid, bool free, unsigned int naddr, | |
2569 | const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) | |
2570 | { | |
2571 | int i, ret; | |
2572 | struct fw_vi_mac_cmd c; | |
2573 | struct fw_vi_mac_exact *p; | |
2574 | ||
2575 | if (naddr > 7) | |
2576 | return -EINVAL; | |
2577 | ||
2578 | memset(&c, 0, sizeof(c)); | |
2579 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST | | |
2580 | FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) | | |
2581 | FW_VI_MAC_CMD_VIID(viid)); | |
2582 | c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) | | |
2583 | FW_CMD_LEN16((naddr + 2) / 2)); | |
2584 | ||
2585 | for (i = 0, p = c.u.exact; i < naddr; i++, p++) { | |
2586 | p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID | | |
2587 | FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); | |
2588 | memcpy(p->macaddr, addr[i], sizeof(p->macaddr)); | |
2589 | } | |
2590 | ||
2591 | ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); | |
2592 | if (ret) | |
2593 | return ret; | |
2594 | ||
2595 | for (i = 0, p = c.u.exact; i < naddr; i++, p++) { | |
2596 | u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx)); | |
2597 | ||
2598 | if (idx) | |
2599 | idx[i] = index >= NEXACT_MAC ? 0xffff : index; | |
2600 | if (index < NEXACT_MAC) | |
2601 | ret++; | |
2602 | else if (hash) | |
ce9aeb58 | 2603 | *hash |= (1ULL << hash_mac_addr(addr[i])); |
56d36be4 DM |
2604 | } |
2605 | return ret; | |
2606 | } | |
2607 | ||
2608 | /** | |
2609 | * t4_change_mac - modifies the exact-match filter for a MAC address | |
2610 | * @adap: the adapter | |
2611 | * @mbox: mailbox to use for the FW command | |
2612 | * @viid: the VI id | |
2613 | * @idx: index of existing filter for old value of MAC address, or -1 | |
2614 | * @addr: the new MAC address value | |
2615 | * @persist: whether a new MAC allocation should be persistent | |
2616 | * @add_smt: if true also add the address to the HW SMT | |
2617 | * | |
2618 | * Modifies an exact-match filter and sets it to the new MAC address. | |
2619 | * Note that in general it is not possible to modify the value of a given | |
2620 | * filter so the generic way to modify an address filter is to free the one | |
2621 | * being used by the old address value and allocate a new filter for the | |
2622 | * new address value. @idx can be -1 if the address is a new addition. | |
2623 | * | |
2624 | * Returns a negative error number or the index of the filter with the new | |
2625 | * MAC value. | |
2626 | */ | |
2627 | int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
2628 | int idx, const u8 *addr, bool persist, bool add_smt) | |
2629 | { | |
2630 | int ret, mode; | |
2631 | struct fw_vi_mac_cmd c; | |
2632 | struct fw_vi_mac_exact *p = c.u.exact; | |
2633 | ||
2634 | if (idx < 0) /* new allocation */ | |
2635 | idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; | |
2636 | mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; | |
2637 | ||
2638 | memset(&c, 0, sizeof(c)); | |
2639 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST | | |
2640 | FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid)); | |
2641 | c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1)); | |
2642 | p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID | | |
2643 | FW_VI_MAC_CMD_SMAC_RESULT(mode) | | |
2644 | FW_VI_MAC_CMD_IDX(idx)); | |
2645 | memcpy(p->macaddr, addr, sizeof(p->macaddr)); | |
2646 | ||
2647 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
2648 | if (ret == 0) { | |
2649 | ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx)); | |
2650 | if (ret >= NEXACT_MAC) | |
2651 | ret = -ENOMEM; | |
2652 | } | |
2653 | return ret; | |
2654 | } | |
2655 | ||
2656 | /** | |
2657 | * t4_set_addr_hash - program the MAC inexact-match hash filter | |
2658 | * @adap: the adapter | |
2659 | * @mbox: mailbox to use for the FW command | |
2660 | * @viid: the VI id | |
2661 | * @ucast: whether the hash filter should also match unicast addresses | |
2662 | * @vec: the value to be written to the hash filter | |
2663 | * @sleep_ok: call is allowed to sleep | |
2664 | * | |
2665 | * Sets the 64-bit inexact-match hash filter for a virtual interface. | |
2666 | */ | |
2667 | int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
2668 | bool ucast, u64 vec, bool sleep_ok) | |
2669 | { | |
2670 | struct fw_vi_mac_cmd c; | |
2671 | ||
2672 | memset(&c, 0, sizeof(c)); | |
2673 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST | | |
2674 | FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid)); | |
2675 | c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN | | |
2676 | FW_VI_MAC_CMD_HASHUNIEN(ucast) | | |
2677 | FW_CMD_LEN16(1)); | |
2678 | c.u.hash.hashvec = cpu_to_be64(vec); | |
2679 | return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); | |
2680 | } | |
2681 | ||
2682 | /** | |
2683 | * t4_enable_vi - enable/disable a virtual interface | |
2684 | * @adap: the adapter | |
2685 | * @mbox: mailbox to use for the FW command | |
2686 | * @viid: the VI id | |
2687 | * @rx_en: 1=enable Rx, 0=disable Rx | |
2688 | * @tx_en: 1=enable Tx, 0=disable Tx | |
2689 | * | |
2690 | * Enables/disables a virtual interface. | |
2691 | */ | |
2692 | int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
2693 | bool rx_en, bool tx_en) | |
2694 | { | |
2695 | struct fw_vi_enable_cmd c; | |
2696 | ||
2697 | memset(&c, 0, sizeof(c)); | |
2698 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST | | |
2699 | FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid)); | |
2700 | c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) | | |
2701 | FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c)); | |
2702 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2703 | } | |
2704 | ||
2705 | /** | |
2706 | * t4_identify_port - identify a VI's port by blinking its LED | |
2707 | * @adap: the adapter | |
2708 | * @mbox: mailbox to use for the FW command | |
2709 | * @viid: the VI id | |
2710 | * @nblinks: how many times to blink LED at 2.5 Hz | |
2711 | * | |
2712 | * Identifies a VI's port by blinking its LED. | |
2713 | */ | |
2714 | int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
2715 | unsigned int nblinks) | |
2716 | { | |
2717 | struct fw_vi_enable_cmd c; | |
2718 | ||
2719 | c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST | | |
2720 | FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid)); | |
2721 | c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); | |
2722 | c.blinkdur = htons(nblinks); | |
2723 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
56d36be4 DM |
2724 | } |
2725 | ||
2726 | /** | |
2727 | * t4_iq_free - free an ingress queue and its FLs | |
2728 | * @adap: the adapter | |
2729 | * @mbox: mailbox to use for the FW command | |
2730 | * @pf: the PF owning the queues | |
2731 | * @vf: the VF owning the queues | |
2732 | * @iqtype: the ingress queue type | |
2733 | * @iqid: ingress queue id | |
2734 | * @fl0id: FL0 queue id or 0xffff if no attached FL0 | |
2735 | * @fl1id: FL1 queue id or 0xffff if no attached FL1 | |
2736 | * | |
2737 | * Frees an ingress queue and its associated FLs, if any. | |
2738 | */ | |
2739 | int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
2740 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | |
2741 | unsigned int fl0id, unsigned int fl1id) | |
2742 | { | |
2743 | struct fw_iq_cmd c; | |
2744 | ||
2745 | memset(&c, 0, sizeof(c)); | |
2746 | c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST | | |
2747 | FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) | | |
2748 | FW_IQ_CMD_VFN(vf)); | |
2749 | c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c)); | |
2750 | c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype)); | |
2751 | c.iqid = htons(iqid); | |
2752 | c.fl0id = htons(fl0id); | |
2753 | c.fl1id = htons(fl1id); | |
2754 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2755 | } | |
2756 | ||
2757 | /** | |
2758 | * t4_eth_eq_free - free an Ethernet egress queue | |
2759 | * @adap: the adapter | |
2760 | * @mbox: mailbox to use for the FW command | |
2761 | * @pf: the PF owning the queue | |
2762 | * @vf: the VF owning the queue | |
2763 | * @eqid: egress queue id | |
2764 | * | |
2765 | * Frees an Ethernet egress queue. | |
2766 | */ | |
2767 | int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
2768 | unsigned int vf, unsigned int eqid) | |
2769 | { | |
2770 | struct fw_eq_eth_cmd c; | |
2771 | ||
2772 | memset(&c, 0, sizeof(c)); | |
2773 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST | | |
2774 | FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) | | |
2775 | FW_EQ_ETH_CMD_VFN(vf)); | |
2776 | c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); | |
2777 | c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid)); | |
2778 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2779 | } | |
2780 | ||
2781 | /** | |
2782 | * t4_ctrl_eq_free - free a control egress queue | |
2783 | * @adap: the adapter | |
2784 | * @mbox: mailbox to use for the FW command | |
2785 | * @pf: the PF owning the queue | |
2786 | * @vf: the VF owning the queue | |
2787 | * @eqid: egress queue id | |
2788 | * | |
2789 | * Frees a control egress queue. | |
2790 | */ | |
2791 | int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
2792 | unsigned int vf, unsigned int eqid) | |
2793 | { | |
2794 | struct fw_eq_ctrl_cmd c; | |
2795 | ||
2796 | memset(&c, 0, sizeof(c)); | |
2797 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST | | |
2798 | FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) | | |
2799 | FW_EQ_CTRL_CMD_VFN(vf)); | |
2800 | c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); | |
2801 | c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid)); | |
2802 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2803 | } | |
2804 | ||
2805 | /** | |
2806 | * t4_ofld_eq_free - free an offload egress queue | |
2807 | * @adap: the adapter | |
2808 | * @mbox: mailbox to use for the FW command | |
2809 | * @pf: the PF owning the queue | |
2810 | * @vf: the VF owning the queue | |
2811 | * @eqid: egress queue id | |
2812 | * | |
2813 | * Frees a control egress queue. | |
2814 | */ | |
2815 | int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
2816 | unsigned int vf, unsigned int eqid) | |
2817 | { | |
2818 | struct fw_eq_ofld_cmd c; | |
2819 | ||
2820 | memset(&c, 0, sizeof(c)); | |
2821 | c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST | | |
2822 | FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) | | |
2823 | FW_EQ_OFLD_CMD_VFN(vf)); | |
2824 | c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); | |
2825 | c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid)); | |
2826 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2827 | } | |
2828 | ||
2829 | /** | |
2830 | * t4_handle_fw_rpl - process a FW reply message | |
2831 | * @adap: the adapter | |
2832 | * @rpl: start of the FW message | |
2833 | * | |
2834 | * Processes a FW message, such as link state change messages. | |
2835 | */ | |
2836 | int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) | |
2837 | { | |
2838 | u8 opcode = *(const u8 *)rpl; | |
2839 | ||
2840 | if (opcode == FW_PORT_CMD) { /* link/module state change message */ | |
2841 | int speed = 0, fc = 0; | |
2842 | const struct fw_port_cmd *p = (void *)rpl; | |
2843 | int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid)); | |
2844 | int port = adap->chan_map[chan]; | |
2845 | struct port_info *pi = adap2pinfo(adap, port); | |
2846 | struct link_config *lc = &pi->link_cfg; | |
2847 | u32 stat = ntohl(p->u.info.lstatus_to_modtype); | |
2848 | int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0; | |
2849 | u32 mod = FW_PORT_CMD_MODTYPE_GET(stat); | |
2850 | ||
2851 | if (stat & FW_PORT_CMD_RXPAUSE) | |
2852 | fc |= PAUSE_RX; | |
2853 | if (stat & FW_PORT_CMD_TXPAUSE) | |
2854 | fc |= PAUSE_TX; | |
2855 | if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) | |
2856 | speed = SPEED_100; | |
2857 | else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) | |
2858 | speed = SPEED_1000; | |
2859 | else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) | |
2860 | speed = SPEED_10000; | |
2861 | ||
2862 | if (link_ok != lc->link_ok || speed != lc->speed || | |
2863 | fc != lc->fc) { /* something changed */ | |
2864 | lc->link_ok = link_ok; | |
2865 | lc->speed = speed; | |
2866 | lc->fc = fc; | |
2867 | t4_os_link_changed(adap, port, link_ok); | |
2868 | } | |
2869 | if (mod != pi->mod_type) { | |
2870 | pi->mod_type = mod; | |
2871 | t4_os_portmod_changed(adap, port); | |
2872 | } | |
2873 | } | |
2874 | return 0; | |
2875 | } | |
2876 | ||
2877 | static void __devinit get_pci_mode(struct adapter *adapter, | |
2878 | struct pci_params *p) | |
2879 | { | |
2880 | u16 val; | |
2881 | u32 pcie_cap = pci_pcie_cap(adapter->pdev); | |
2882 | ||
2883 | if (pcie_cap) { | |
2884 | pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, | |
2885 | &val); | |
2886 | p->speed = val & PCI_EXP_LNKSTA_CLS; | |
2887 | p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; | |
2888 | } | |
2889 | } | |
2890 | ||
2891 | /** | |
2892 | * init_link_config - initialize a link's SW state | |
2893 | * @lc: structure holding the link state | |
2894 | * @caps: link capabilities | |
2895 | * | |
2896 | * Initializes the SW state maintained for each link, including the link's | |
2897 | * capabilities and default speed/flow-control/autonegotiation settings. | |
2898 | */ | |
2899 | static void __devinit init_link_config(struct link_config *lc, | |
2900 | unsigned int caps) | |
2901 | { | |
2902 | lc->supported = caps; | |
2903 | lc->requested_speed = 0; | |
2904 | lc->speed = 0; | |
2905 | lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; | |
2906 | if (lc->supported & FW_PORT_CAP_ANEG) { | |
2907 | lc->advertising = lc->supported & ADVERT_MASK; | |
2908 | lc->autoneg = AUTONEG_ENABLE; | |
2909 | lc->requested_fc |= PAUSE_AUTONEG; | |
2910 | } else { | |
2911 | lc->advertising = 0; | |
2912 | lc->autoneg = AUTONEG_DISABLE; | |
2913 | } | |
2914 | } | |
2915 | ||
204dc3c0 | 2916 | int t4_wait_dev_ready(struct adapter *adap) |
56d36be4 DM |
2917 | { |
2918 | if (t4_read_reg(adap, PL_WHOAMI) != 0xffffffff) | |
2919 | return 0; | |
2920 | msleep(500); | |
2921 | return t4_read_reg(adap, PL_WHOAMI) != 0xffffffff ? 0 : -EIO; | |
2922 | } | |
2923 | ||
900a6596 DM |
2924 | static int __devinit get_flash_params(struct adapter *adap) |
2925 | { | |
2926 | int ret; | |
2927 | u32 info; | |
2928 | ||
2929 | ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); | |
2930 | if (!ret) | |
2931 | ret = sf1_read(adap, 3, 0, 1, &info); | |
2932 | t4_write_reg(adap, SF_OP, 0); /* unlock SF */ | |
2933 | if (ret) | |
2934 | return ret; | |
2935 | ||
2936 | if ((info & 0xff) != 0x20) /* not a Numonix flash */ | |
2937 | return -EINVAL; | |
2938 | info >>= 16; /* log2 of size */ | |
2939 | if (info >= 0x14 && info < 0x18) | |
2940 | adap->params.sf_nsec = 1 << (info - 16); | |
2941 | else if (info == 0x18) | |
2942 | adap->params.sf_nsec = 64; | |
2943 | else | |
2944 | return -EINVAL; | |
2945 | adap->params.sf_size = 1 << info; | |
2946 | adap->params.sf_fw_start = | |
2947 | t4_read_reg(adap, CIM_BOOT_CFG) & BOOTADDR_MASK; | |
2948 | return 0; | |
2949 | } | |
2950 | ||
56d36be4 DM |
2951 | /** |
2952 | * t4_prep_adapter - prepare SW and HW for operation | |
2953 | * @adapter: the adapter | |
2954 | * @reset: if true perform a HW reset | |
2955 | * | |
2956 | * Initialize adapter SW state for the various HW modules, set initial | |
2957 | * values for some adapter tunables, take PHYs out of reset, and | |
2958 | * initialize the MDIO interface. | |
2959 | */ | |
2960 | int __devinit t4_prep_adapter(struct adapter *adapter) | |
2961 | { | |
2962 | int ret; | |
2963 | ||
204dc3c0 | 2964 | ret = t4_wait_dev_ready(adapter); |
56d36be4 DM |
2965 | if (ret < 0) |
2966 | return ret; | |
2967 | ||
2968 | get_pci_mode(adapter, &adapter->params.pci); | |
2969 | adapter->params.rev = t4_read_reg(adapter, PL_REV); | |
2970 | ||
900a6596 DM |
2971 | ret = get_flash_params(adapter); |
2972 | if (ret < 0) { | |
2973 | dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret); | |
2974 | return ret; | |
2975 | } | |
2976 | ||
56d36be4 DM |
2977 | ret = get_vpd_params(adapter, &adapter->params.vpd); |
2978 | if (ret < 0) | |
2979 | return ret; | |
2980 | ||
2981 | init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); | |
2982 | ||
2983 | /* | |
2984 | * Default port for debugging in case we can't reach FW. | |
2985 | */ | |
2986 | adapter->params.nports = 1; | |
2987 | adapter->params.portvec = 1; | |
2988 | return 0; | |
2989 | } | |
2990 | ||
2991 | int __devinit t4_port_init(struct adapter *adap, int mbox, int pf, int vf) | |
2992 | { | |
2993 | u8 addr[6]; | |
2994 | int ret, i, j = 0; | |
2995 | struct fw_port_cmd c; | |
f796564a | 2996 | struct fw_rss_vi_config_cmd rvc; |
56d36be4 DM |
2997 | |
2998 | memset(&c, 0, sizeof(c)); | |
f796564a | 2999 | memset(&rvc, 0, sizeof(rvc)); |
56d36be4 DM |
3000 | |
3001 | for_each_port(adap, i) { | |
3002 | unsigned int rss_size; | |
3003 | struct port_info *p = adap2pinfo(adap, i); | |
3004 | ||
3005 | while ((adap->params.portvec & (1 << j)) == 0) | |
3006 | j++; | |
3007 | ||
3008 | c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | | |
3009 | FW_CMD_REQUEST | FW_CMD_READ | | |
3010 | FW_PORT_CMD_PORTID(j)); | |
3011 | c.action_to_len16 = htonl( | |
3012 | FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) | | |
3013 | FW_LEN16(c)); | |
3014 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
3015 | if (ret) | |
3016 | return ret; | |
3017 | ||
3018 | ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); | |
3019 | if (ret < 0) | |
3020 | return ret; | |
3021 | ||
3022 | p->viid = ret; | |
3023 | p->tx_chan = j; | |
3024 | p->lport = j; | |
3025 | p->rss_size = rss_size; | |
3026 | memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); | |
3027 | memcpy(adap->port[i]->perm_addr, addr, ETH_ALEN); | |
f21ce1c3 | 3028 | adap->port[i]->dev_id = j; |
56d36be4 DM |
3029 | |
3030 | ret = ntohl(c.u.info.lstatus_to_modtype); | |
3031 | p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ? | |
3032 | FW_PORT_CMD_MDIOADDR_GET(ret) : -1; | |
3033 | p->port_type = FW_PORT_CMD_PTYPE_GET(ret); | |
a0881cab | 3034 | p->mod_type = FW_PORT_MOD_TYPE_NA; |
56d36be4 | 3035 | |
f796564a DM |
3036 | rvc.op_to_viid = htonl(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | |
3037 | FW_CMD_REQUEST | FW_CMD_READ | | |
3038 | FW_RSS_VI_CONFIG_CMD_VIID(p->viid)); | |
3039 | rvc.retval_len16 = htonl(FW_LEN16(rvc)); | |
3040 | ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); | |
3041 | if (ret) | |
3042 | return ret; | |
3043 | p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen); | |
3044 | ||
56d36be4 DM |
3045 | init_link_config(&p->link_cfg, ntohs(c.u.info.pcap)); |
3046 | j++; | |
3047 | } | |
3048 | return 0; | |
3049 | } |