[linux-2.6-block.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_uld.h

/*
 * This file is part of the Chelsio T4 Ethernet driver for Linux.
 *
 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __CXGB4_ULD_H
#define __CXGB4_ULD_H

#include <linux/cache.h>
#include <linux/spinlock.h>
#include <linux/skbuff.h>
#include <linux/inetdevice.h>
#include <linux/atomic.h>
#include "cxgb4.h"

#define MAX_ULD_QSETS 16

/* CPL message priority levels */
enum {
	CPL_PRIORITY_DATA     = 0,  /* data messages */
	CPL_PRIORITY_SETUP    = 1,  /* connection setup messages */
	CPL_PRIORITY_TEARDOWN = 0,  /* connection teardown messages */
	CPL_PRIORITY_LISTEN   = 1,  /* listen start/stop messages */
	CPL_PRIORITY_ACK      = 1,  /* RX ACK messages */
	CPL_PRIORITY_CONTROL  = 1   /* control messages */
};

#define INIT_TP_WR(w, tid) do { \
	(w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_TP_WR) | \
			      FW_WR_IMMDLEN_V(sizeof(*w) - sizeof(w->wr))); \
	(w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*w), 16)) | \
			       FW_WR_FLOWID_V(tid)); \
	(w)->wr.wr_lo = cpu_to_be64(0); \
} while (0)

#define INIT_TP_WR_CPL(w, cpl, tid) do { \
	INIT_TP_WR(w, tid); \
	OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \
} while (0)

#define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
	(w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) | \
			      FW_WR_ATOMIC_V(atomic)); \
	(w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(wrlen, 16)) | \
			       FW_WR_FLOWID_V(tid)); \
	(w)->wr.wr_lo = cpu_to_be64(0); \
} while (0)

/* Special asynchronous notification message */
#define CXGB4_MSG_AN ((void *)1)
#define TX_ULD(uld)(((uld) != CXGB4_ULD_CRYPTO) ? CXGB4_TX_OFLD :\
		      CXGB4_TX_CRYPTO)

struct serv_entry {
	void *data;
};

union aopen_entry {
	void *data;
	union aopen_entry *next;
};

/*
 * Holds the size, base address, free list start, etc of the TID, server TID,
 * and active-open TID tables.  The tables themselves are allocated dynamically.
 */
struct tid_info {
	void **tid_tab;
	unsigned int ntids;

	struct serv_entry *stid_tab;
	unsigned long *stid_bmap;
	unsigned int nstids;
	unsigned int stid_base;
	unsigned int hash_base;

	union aopen_entry *atid_tab;
	unsigned int natids;
	unsigned int atid_base;

	struct filter_entry *ftid_tab;
	unsigned long *ftid_bmap;
	unsigned int nftids;
	unsigned int ftid_base;
	unsigned int aftid_base;
	unsigned int aftid_end;
	/* Server filter region */
	unsigned int sftid_base;
	unsigned int nsftids;

	spinlock_t atid_lock ____cacheline_aligned_in_smp;
	union aopen_entry *afree;
	unsigned int atids_in_use;

	spinlock_t stid_lock;
	unsigned int stids_in_use;
	unsigned int v6_stids_in_use;
	unsigned int sftids_in_use;

	/* TIDs in the TCAM */
	atomic_t tids_in_use;
	/* TIDs in the HASH */
	atomic_t hash_tids_in_use;
	atomic_t conns_in_use;
	/* lock for setting/clearing filter bitmap */
	spinlock_t ftid_lock;
};

static inline void *lookup_tid(const struct tid_info *t, unsigned int tid)
{
	return tid < t->ntids ? t->tid_tab[tid] : NULL;
}

static inline void *lookup_atid(const struct tid_info *t, unsigned int atid)
{
	return atid < t->natids ? t->atid_tab[atid].data : NULL;
}

static inline void *lookup_stid(const struct tid_info *t, unsigned int stid)
{
	/* Is it a server filter TID? */
	if (t->nsftids && (stid >= t->sftid_base)) {
		stid -= t->sftid_base;
		stid += t->nstids;
	} else {
		stid -= t->stid_base;
	}

	return stid < (t->nstids + t->nsftids) ? t->stid_tab[stid].data : NULL;
}

static inline void cxgb4_insert_tid(struct tid_info *t, void *data,
				    unsigned int tid, unsigned short family)
{
	t->tid_tab[tid] = data;
	if (t->hash_base && (tid >= t->hash_base)) {
		if (family == AF_INET6)
			atomic_add(2, &t->hash_tids_in_use);
		else
			atomic_inc(&t->hash_tids_in_use);
	} else {
		if (family == AF_INET6)
			atomic_add(2, &t->tids_in_use);
		else
			atomic_inc(&t->tids_in_use);
	}
	atomic_inc(&t->conns_in_use);
}

int cxgb4_alloc_atid(struct tid_info *t, void *data);
int cxgb4_alloc_stid(struct tid_info *t, int family, void *data);
int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data);
void cxgb4_free_atid(struct tid_info *t, unsigned int atid);
void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family);
void cxgb4_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid,
		      unsigned short family);
struct in6_addr;

int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
			__be32 sip, __be16 sport, __be16 vlan,
			unsigned int queue);
int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
			 const struct in6_addr *sip, __be16 sport,
			 unsigned int queue);
int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
			unsigned int queue, bool ipv6);
int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
			       __be32 sip, __be16 sport, __be16 vlan,
			       unsigned int queue,
			       unsigned char port, unsigned char mask);
int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
			       unsigned int queue, bool ipv6);

/* Filter operation context to allow callers of cxgb4_set_filter() and
 * cxgb4_del_filter() to wait for an asynchronous completion.
 */
struct filter_ctx {
	struct completion completion;	/* completion rendezvous */
	void *closure;			/* caller's opaque information */
	int result;			/* result of operation */
	u32 tid;			/* to store tid */
};

struct ch_filter_specification;

int cxgb4_get_free_ftid(struct net_device *dev, int family);
int __cxgb4_set_filter(struct net_device *dev, int filter_id,
		       struct ch_filter_specification *fs,
		       struct filter_ctx *ctx);
int __cxgb4_del_filter(struct net_device *dev, int filter_id,
		       struct ch_filter_specification *fs,
		       struct filter_ctx *ctx);
int cxgb4_set_filter(struct net_device *dev, int filter_id,
		     struct ch_filter_specification *fs);
int cxgb4_del_filter(struct net_device *dev, int filter_id,
		     struct ch_filter_specification *fs);
int cxgb4_get_filter_counters(struct net_device *dev, unsigned int fidx,
			      u64 *hitcnt, u64 *bytecnt, bool hash);

static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue)
{
	skb_set_queue_mapping(skb, (queue << 1) | prio);
}

enum cxgb4_uld {
	CXGB4_ULD_INIT,
	CXGB4_ULD_RDMA,
	CXGB4_ULD_ISCSI,
	CXGB4_ULD_ISCSIT,
	CXGB4_ULD_CRYPTO,
	CXGB4_ULD_TLS,
	CXGB4_ULD_MAX
};

enum cxgb4_tx_uld {
	CXGB4_TX_OFLD,
	CXGB4_TX_CRYPTO,
	CXGB4_TX_MAX
};

enum cxgb4_txq_type {
	CXGB4_TXQ_ETH,
	CXGB4_TXQ_ULD,
	CXGB4_TXQ_CTRL,
	CXGB4_TXQ_MAX
};

enum cxgb4_state {
	CXGB4_STATE_UP,
	CXGB4_STATE_START_RECOVERY,
	CXGB4_STATE_DOWN,
	CXGB4_STATE_DETACH,
	CXGB4_STATE_FATAL_ERROR
};

enum cxgb4_control {
	CXGB4_CONTROL_DB_FULL,
	CXGB4_CONTROL_DB_EMPTY,
	CXGB4_CONTROL_DB_DROP,
};

struct pci_dev;
struct l2t_data;
struct net_device;
struct pkt_gl;
struct tp_tcp_stats;
struct t4_lro_mgr;

struct cxgb4_range {
	unsigned int start;
	unsigned int size;
};

struct cxgb4_virt_res {                      /* virtualized HW resources */
	struct cxgb4_range ddp;
	struct cxgb4_range iscsi;
	struct cxgb4_range stag;
	struct cxgb4_range rq;
	struct cxgb4_range srq;
	struct cxgb4_range pbl;
	struct cxgb4_range qp;
	struct cxgb4_range cq;
	struct cxgb4_range ocq;
	struct cxgb4_range key;
	unsigned int ncrypto_fc;
};

struct chcr_stats_debug {
	atomic_t cipher_rqst;
	atomic_t digest_rqst;
	atomic_t aead_rqst;
	atomic_t complete;
	atomic_t error;
	atomic_t fallback;
	atomic_t ipsec_cnt;
	atomic_t tls_pdu_tx;
	atomic_t tls_pdu_rx;
	atomic_t tls_key;
};

#define OCQ_WIN_OFFSET(pdev, vres) \
	(pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size))

/*
 * Block of information the LLD provides to ULDs attaching to a device.
 */
struct cxgb4_lld_info {
	struct pci_dev *pdev;                /* associated PCI device */
	struct l2t_data *l2t;                /* L2 table */
	struct tid_info *tids;               /* TID table */
	struct net_device **ports;           /* device ports */
	const struct cxgb4_virt_res *vr;     /* assorted HW resources */
	const unsigned short *mtus;          /* MTU table */
	const unsigned short *rxq_ids;       /* the ULD's Rx queue ids */
	const unsigned short *ciq_ids;       /* the ULD's concentrator IQ ids */
	unsigned short nrxq;                 /* # of Rx queues */
	unsigned short ntxq;                 /* # of Tx queues */
	unsigned short nciq;		     /* # of concentrator IQ */
	unsigned char nchan:4;               /* # of channels */
	unsigned char nports:4;              /* # of ports */
	unsigned char wr_cred;               /* WR 16-byte credits */
	unsigned char adapter_type;          /* type of adapter */
	unsigned char fw_api_ver;            /* FW API version */
	unsigned char crypto;                /* crypto support */
	unsigned int fw_vers;                /* FW version */
	unsigned int iscsi_iolen;            /* iSCSI max I/O length */
	unsigned int cclk_ps;                /* Core clock period in psec */
	unsigned short udb_density;          /* # of user DB/page */
	unsigned short ucq_density;          /* # of user CQs/page */
	unsigned int sge_host_page_size;     /* SGE host page size */
	unsigned short filt_mode;            /* filter optional components */
	unsigned short tx_modq[NCHAN];       /* maps each tx channel to a */
					     /* scheduler queue */
	void __iomem *gts_reg;               /* address of GTS register */
	void __iomem *db_reg;                /* address of kernel doorbell */
	int dbfifo_int_thresh;		     /* doorbell fifo int threshold */
	unsigned int sge_ingpadboundary;     /* SGE ingress padding boundary */
	unsigned int sge_egrstatuspagesize;  /* SGE egress status page size */
	unsigned int sge_pktshift;           /* Padding between CPL and */
					     /*	packet data */
	unsigned int pf;		     /* Physical Function we're using */
	bool enable_fw_ofld_conn;            /* Enable connection through fw */
					     /* WR */
	unsigned int max_ordird_qp;          /* Max ORD/IRD depth per RDMA QP */
	unsigned int max_ird_adapter;        /* Max IRD memory per adapter */
	bool ulptx_memwrite_dsgl;            /* use of T5 DSGL allowed */
	unsigned int iscsi_tagmask;	     /* iscsi ddp tag mask */
	unsigned int iscsi_pgsz_order;	     /* iscsi ddp page size orders */
	unsigned int iscsi_llimit;	     /* chip's iscsi region llimit */
	unsigned int ulp_crypto;             /* crypto lookaside support */
	void **iscsi_ppm;		     /* iscsi page pod manager */
	int nodeid;			     /* device numa node id */
	bool fr_nsmr_tpte_wr_support;	     /* FW supports FR_NSMR_TPTE_WR */
	bool write_w_imm_support;         /* FW supports WRITE_WITH_IMMEDIATE */
	bool write_cmpl_support;             /* FW supports WRITE_CMPL WR */
};

struct cxgb4_uld_info {
	char name[IFNAMSIZ];
	void *handle;
	unsigned int nrxq;
	unsigned int rxq_size;
	unsigned int ntxq;
	bool ciq;
	bool lro;
	void *(*add)(const struct cxgb4_lld_info *p);
	int (*rx_handler)(void *handle, const __be64 *rsp,
			  const struct pkt_gl *gl);
	int (*state_change)(void *handle, enum cxgb4_state new_state);
	int (*control)(void *handle, enum cxgb4_control control, ...);
	int (*lro_rx_handler)(void *handle, const __be64 *rsp,
			      const struct pkt_gl *gl,
			      struct t4_lro_mgr *lro_mgr,
			      struct napi_struct *napi);
	void (*lro_flush)(struct t4_lro_mgr *);
	int (*tx_handler)(struct sk_buff *skb, struct net_device *dev);
};

void cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p);
int cxgb4_unregister_uld(enum cxgb4_uld type);
int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb);
int cxgb4_immdata_send(struct net_device *dev, unsigned int idx,
		       const void *src, unsigned int len);
int cxgb4_crypto_send(struct net_device *dev, struct sk_buff *skb);
unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo);
unsigned int cxgb4_port_chan(const struct net_device *dev);
unsigned int cxgb4_port_viid(const struct net_device *dev);
unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid);
unsigned int cxgb4_port_idx(const struct net_device *dev);
unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
			    unsigned int *idx);
unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
				    unsigned short header_size,
				    unsigned short data_size_max,
				    unsigned short data_size_align,
				    unsigned int *mtu_idxp);
void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
			 struct tp_tcp_stats *v6);
void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
		      const unsigned int *pgsz_order);
struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
				   unsigned int skb_len, unsigned int pull_len);
int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size);
int cxgb4_flush_eq_cache(struct net_device *dev);
int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte);
u64 cxgb4_read_sge_timestamp(struct net_device *dev);

enum cxgb4_bar2_qtype { CXGB4_BAR2_QTYPE_EGRESS, CXGB4_BAR2_QTYPE_INGRESS };
int cxgb4_bar2_sge_qregs(struct net_device *dev,
			 unsigned int qid,
			 enum cxgb4_bar2_qtype qtype,
			 int user,
			 u64 *pbar2_qoffset,
			 unsigned int *pbar2_qid);

#endif  /* !__CXGB4_ULD_H */
Commit	Line	Data
625ba2c2 DM	1	/*
	2	* This file is part of the Chelsio T4 Ethernet driver for Linux.
	3	*
578b46b9	4	* Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
625ba2c2 DM	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* COPYING in the main directory of this source tree, or the
	10	* OpenIB.org BSD license below:
	11	*
	12	* Redistribution and use in source and binary forms, with or
	13	* without modification, are permitted provided that the following
	14	* conditions are met:
	15	*
	16	* - Redistributions of source code must retain the above
	17	* copyright notice, this list of conditions and the following
	18	* disclaimer.
	19	*
	20	* - Redistributions in binary form must reproduce the above
	21	* copyright notice, this list of conditions and the following
	22	* disclaimer in the documentation and/or other materials
	23	* provided with the distribution.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	26	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	27	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	28	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	29	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	30	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	31	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	32	* SOFTWARE.
	33	*/
	34
94cdb8bb HS	35	#ifndef __CXGB4_ULD_H
94cdb8bb HS	36	#define __CXGB4_ULD_H
625ba2c2 DM	37
	38	#include <linux/cache.h>
	39	#include <linux/spinlock.h>
	40	#include <linux/skbuff.h>
793dad94	41	#include <linux/inetdevice.h>
60063497	42	#include <linux/atomic.h>
27999805	43	#include "cxgb4.h"
625ba2c2	44
0fbc81b3 HS	45	#define MAX_ULD_QSETS 16
0fbc81b3 HS	46
625ba2c2 DM	47	/* CPL message priority levels */
	48	enum {
	49	CPL_PRIORITY_DATA = 0, /* data messages */
	50	CPL_PRIORITY_SETUP = 1, /* connection setup messages */
	51	CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */
	52	CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */
	53	CPL_PRIORITY_ACK = 1, /* RX ACK messages */
	54	CPL_PRIORITY_CONTROL = 1 /* control messages */
	55	};
	56
	57	#define INIT_TP_WR(w, tid) do { \
e2ac9628 HS	58	(w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_TP_WR) \| \
	59	FW_WR_IMMDLEN_V(sizeof(*w) - sizeof(w->wr))); \
	60	(w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*w), 16)) \| \
	61	FW_WR_FLOWID_V(tid)); \
625ba2c2 DM	62	(w)->wr.wr_lo = cpu_to_be64(0); \
	63	} while (0)
	64
	65	#define INIT_TP_WR_CPL(w, cpl, tid) do { \
	66	INIT_TP_WR(w, tid); \
	67	OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \
	68	} while (0)
	69
	70	#define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
e2ac9628 HS	71	(w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) \| \
	72	FW_WR_ATOMIC_V(atomic)); \
	73	(w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(wrlen, 16)) \| \
	74	FW_WR_FLOWID_V(tid)); \
625ba2c2 DM	75	(w)->wr.wr_lo = cpu_to_be64(0); \
	76	} while (0)
	77
	78	/* Special asynchronous notification message */
	79	#define CXGB4_MSG_AN ((void *)1)
ab677ff4 HS	80	#define TX_ULD(uld)(((uld) != CXGB4_ULD_CRYPTO) ? CXGB4_TX_OFLD :\
ab677ff4 HS	81	CXGB4_TX_CRYPTO)
625ba2c2 DM	82
	83	struct serv_entry {
	84	void *data;
	85	};
	86
	87	union aopen_entry {
	88	void *data;
	89	union aopen_entry *next;
	90	};
	91
	92	/*
	93	* Holds the size, base address, free list start, etc of the TID, server TID,
	94	* and active-open TID tables. The tables themselves are allocated dynamically.
	95	*/
	96	struct tid_info {
	97	void **tid_tab;
	98	unsigned int ntids;
	99
	100	struct serv_entry *stid_tab;
	101	unsigned long *stid_bmap;
	102	unsigned int nstids;
	103	unsigned int stid_base;
9a1bb9f6	104	unsigned int hash_base;
625ba2c2 DM	105
	106	union aopen_entry *atid_tab;
	107	unsigned int natids;
f2b7e78d	108	unsigned int atid_base;
625ba2c2	109
f2b7e78d	110	struct filter_entry *ftid_tab;
578b46b9	111	unsigned long *ftid_bmap;
625ba2c2 DM	112	unsigned int nftids;
625ba2c2 DM	113	unsigned int ftid_base;
636f9d37 VP	114	unsigned int aftid_base;
636f9d37 VP	115	unsigned int aftid_end;
9a4da2cd VP	116	/* Server filter region */
	117	unsigned int sftid_base;
	118	unsigned int nsftids;
625ba2c2 DM	119
	120	spinlock_t atid_lock ____cacheline_aligned_in_smp;
	121	union aopen_entry *afree;
	122	unsigned int atids_in_use;
	123
	124	spinlock_t stid_lock;
	125	unsigned int stids_in_use;
1dec4cec	126	unsigned int v6_stids_in_use;
2248b293	127	unsigned int sftids_in_use;
625ba2c2	128
9a1bb9f6	129	/* TIDs in the TCAM */
625ba2c2	130	atomic_t tids_in_use;
9a1bb9f6 HS	131	/* TIDs in the HASH */
9a1bb9f6 HS	132	atomic_t hash_tids_in_use;
1dec4cec	133	atomic_t conns_in_use;
578b46b9 RL	134	/* lock for setting/clearing filter bitmap */
578b46b9 RL	135	spinlock_t ftid_lock;
625ba2c2 DM	136	};
	137
	138	static inline void lookup_tid(const struct tid_info t, unsigned int tid)
	139	{
	140	return tid < t->ntids ? t->tid_tab[tid] : NULL;
	141	}
	142
	143	static inline void lookup_atid(const struct tid_info t, unsigned int atid)
	144	{
	145	return atid < t->natids ? t->atid_tab[atid].data : NULL;
	146	}
	147
	148	static inline void lookup_stid(const struct tid_info t, unsigned int stid)
	149	{
470c60c4 KS	150	/* Is it a server filter TID? */
	151	if (t->nsftids && (stid >= t->sftid_base)) {
	152	stid -= t->sftid_base;
	153	stid += t->nstids;
	154	} else {
	155	stid -= t->stid_base;
	156	}
	157
dca4faeb	158	return stid < (t->nstids + t->nsftids) ? t->stid_tab[stid].data : NULL;
625ba2c2 DM	159	}
	160
	161	static inline void cxgb4_insert_tid(struct tid_info t, void data,
1dec4cec	162	unsigned int tid, unsigned short family)
625ba2c2 DM	163	{
625ba2c2 DM	164	t->tid_tab[tid] = data;
1dec4cec GG	165	if (t->hash_base && (tid >= t->hash_base)) {
	166	if (family == AF_INET6)
	167	atomic_add(2, &t->hash_tids_in_use);
	168	else
	169	atomic_inc(&t->hash_tids_in_use);
	170	} else {
	171	if (family == AF_INET6)
	172	atomic_add(2, &t->tids_in_use);
	173	else
	174	atomic_inc(&t->tids_in_use);
	175	}
	176	atomic_inc(&t->conns_in_use);
625ba2c2 DM	177	}
	178
	179	int cxgb4_alloc_atid(struct tid_info t, void data);
	180	int cxgb4_alloc_stid(struct tid_info t, int family, void data);
dca4faeb	181	int cxgb4_alloc_sftid(struct tid_info t, int family, void data);
625ba2c2 DM	182	void cxgb4_free_atid(struct tid_info *t, unsigned int atid);
625ba2c2 DM	183	void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family);
1dec4cec GG	184	void cxgb4_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid,
1dec4cec GG	185	unsigned short family);
625ba2c2 DM	186	struct in6_addr;
	187
	188	int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94 VP	189	__be32 sip, __be16 sport, __be16 vlan,
793dad94 VP	190	unsigned int queue);
80f40c1f VP	191	int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
	192	const struct in6_addr *sip, __be16 sport,
	193	unsigned int queue);
	194	int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
	195	unsigned int queue, bool ipv6);
dca4faeb	196	int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94 VP	197	__be32 sip, __be16 sport, __be16 vlan,
	198	unsigned int queue,
	199	unsigned char port, unsigned char mask);
dca4faeb VP	200	int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
dca4faeb VP	201	unsigned int queue, bool ipv6);
a3e3b285	202
578b46b9 RL	203	/* Filter operation context to allow callers of cxgb4_set_filter() and
	204	* cxgb4_del_filter() to wait for an asynchronous completion.
	205	*/
	206	struct filter_ctx {
	207	struct completion completion; /* completion rendezvous */
	208	void closure; / caller's opaque information */
	209	int result; /* result of operation */
	210	u32 tid; /* to store tid */
	211	};
	212
	213	struct ch_filter_specification;
	214
62488e4b	215	int cxgb4_get_free_ftid(struct net_device *dev, int family);
578b46b9 RL	216	int __cxgb4_set_filter(struct net_device *dev, int filter_id,
	217	struct ch_filter_specification *fs,
	218	struct filter_ctx *ctx);
	219	int __cxgb4_del_filter(struct net_device *dev, int filter_id,
3b0b3bee	220	struct ch_filter_specification *fs,
578b46b9 RL	221	struct filter_ctx *ctx);
	222	int cxgb4_set_filter(struct net_device *dev, int filter_id,
	223	struct ch_filter_specification *fs);
3b0b3bee KS	224	int cxgb4_del_filter(struct net_device *dev, int filter_id,
3b0b3bee KS	225	struct ch_filter_specification *fs);
e0f911c8	226	int cxgb4_get_filter_counters(struct net_device *dev, unsigned int fidx,
9d922d4b	227	u64 hitcnt, u64 bytecnt, bool hash);
578b46b9	228
625ba2c2 DM	229	static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue)
	230	{
	231	skb_set_queue_mapping(skb, (queue << 1) \| prio);
	232	}
	233
	234	enum cxgb4_uld {
0fbc81b3	235	CXGB4_ULD_INIT,
625ba2c2 DM	236	CXGB4_ULD_RDMA,
625ba2c2 DM	237	CXGB4_ULD_ISCSI,
2fddfb81	238	CXGB4_ULD_ISCSIT,
0fbc81b3	239	CXGB4_ULD_CRYPTO,
e383f248	240	CXGB4_ULD_TLS,
625ba2c2 DM	241	CXGB4_ULD_MAX
	242	};
	243
ab677ff4 HS	244	enum cxgb4_tx_uld {
	245	CXGB4_TX_OFLD,
	246	CXGB4_TX_CRYPTO,
	247	CXGB4_TX_MAX
	248	};
	249
	250	enum cxgb4_txq_type {
	251	CXGB4_TXQ_ETH,
	252	CXGB4_TXQ_ULD,
	253	CXGB4_TXQ_CTRL,
	254	CXGB4_TXQ_MAX
	255	};
	256
625ba2c2 DM	257	enum cxgb4_state {
	258	CXGB4_STATE_UP,
	259	CXGB4_STATE_START_RECOVERY,
	260	CXGB4_STATE_DOWN,
8b7372c1 GG	261	CXGB4_STATE_DETACH,
8b7372c1 GG	262	CXGB4_STATE_FATAL_ERROR
625ba2c2 DM	263	};
625ba2c2 DM	264
881806bc VP	265	enum cxgb4_control {
	266	CXGB4_CONTROL_DB_FULL,
	267	CXGB4_CONTROL_DB_EMPTY,
	268	CXGB4_CONTROL_DB_DROP,
	269	};
	270
625ba2c2 DM	271	struct pci_dev;
	272	struct l2t_data;
	273	struct net_device;
	274	struct pkt_gl;
	275	struct tp_tcp_stats;
2337ba42	276	struct t4_lro_mgr;
625ba2c2 DM	277
	278	struct cxgb4_range {
	279	unsigned int start;
	280	unsigned int size;
	281	};
	282
	283	struct cxgb4_virt_res { /* virtualized HW resources */
	284	struct cxgb4_range ddp;
	285	struct cxgb4_range iscsi;
	286	struct cxgb4_range stag;
	287	struct cxgb4_range rq;
c68644ef	288	struct cxgb4_range srq;
625ba2c2	289	struct cxgb4_range pbl;
a0881cab DM	290	struct cxgb4_range qp;
a0881cab DM	291	struct cxgb4_range cq;
1ae970e0	292	struct cxgb4_range ocq;
e383f248	293	struct cxgb4_range key;
72a56ca9	294	unsigned int ncrypto_fc;
625ba2c2 DM	295	};
625ba2c2 DM	296
ee0863ba HJ	297	struct chcr_stats_debug {
	298	atomic_t cipher_rqst;
	299	atomic_t digest_rqst;
	300	atomic_t aead_rqst;
	301	atomic_t complete;
	302	atomic_t error;
	303	atomic_t fallback;
a6ec572b	304	atomic_t ipsec_cnt;
e383f248 AG	305	atomic_t tls_pdu_tx;
	306	atomic_t tls_pdu_rx;
	307	atomic_t tls_key;
ee0863ba HJ	308	};
ee0863ba HJ	309
1ae970e0 DM	310	#define OCQ_WIN_OFFSET(pdev, vres) \
	311	(pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size))
	312
625ba2c2 DM	313	/*
	314	* Block of information the LLD provides to ULDs attaching to a device.
	315	*/
	316	struct cxgb4_lld_info {
	317	struct pci_dev pdev; / associated PCI device */
	318	struct l2t_data l2t; / L2 table */
	319	struct tid_info tids; / TID table */
	320	struct net_device *ports; / device ports */
	321	const struct cxgb4_virt_res vr; / assorted HW resources */
	322	const unsigned short mtus; / MTU table */
	323	const unsigned short rxq_ids; / the ULD's Rx queue ids */
cf38be6d	324	const unsigned short ciq_ids; / the ULD's concentrator IQ ids */
625ba2c2 DM	325	unsigned short nrxq; /* # of Rx queues */
625ba2c2 DM	326	unsigned short ntxq; /* # of Tx queues */
cf38be6d	327	unsigned short nciq; /* # of concentrator IQ */
625ba2c2 DM	328	unsigned char nchan:4; /* # of channels */
	329	unsigned char nports:4; /* # of ports */
	330	unsigned char wr_cred; /* WR 16-byte credits */
	331	unsigned char adapter_type; /* type of adapter */
	332	unsigned char fw_api_ver; /* FW API version */
a6ec572b	333	unsigned char crypto; /* crypto support */
625ba2c2 DM	334	unsigned int fw_vers; /* FW version */
625ba2c2 DM	335	unsigned int iscsi_iolen; /* iSCSI max I/O length */
7730b4c7	336	unsigned int cclk_ps; /* Core clock period in psec */
625ba2c2 DM	337	unsigned short udb_density; /* # of user DB/page */
625ba2c2 DM	338	unsigned short ucq_density; /* # of user CQs/page */
fc4144e7	339	unsigned int sge_host_page_size; /* SGE host page size */
dca4faeb VP	340	unsigned short filt_mode; /* filter optional components */
	341	unsigned short tx_modq[NCHAN]; /* maps each tx channel to a */
	342	/* scheduler queue */
625ba2c2 DM	343	void __iomem gts_reg; / address of GTS register */
625ba2c2 DM	344	void __iomem db_reg; / address of kernel doorbell */
3069ee9b	345	int dbfifo_int_thresh; /* doorbell fifo int threshold */
04e10e21 HS	346	unsigned int sge_ingpadboundary; /* SGE ingress padding boundary */
04e10e21 HS	347	unsigned int sge_egrstatuspagesize; /* SGE egress status page size */
dca4faeb VP	348	unsigned int sge_pktshift; /* Padding between CPL and */
dca4faeb VP	349	/* packet data */
35b1de55	350	unsigned int pf; /* Physical Function we're using */
dca4faeb VP	351	bool enable_fw_ofld_conn; /* Enable connection through fw */
dca4faeb VP	352	/* WR */
4c2c5763 HS	353	unsigned int max_ordird_qp; /* Max ORD/IRD depth per RDMA QP */
4c2c5763 HS	354	unsigned int max_ird_adapter; /* Max IRD memory per adapter */
1ac0f095	355	bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
7714cb9e VP	356	unsigned int iscsi_tagmask; /* iscsi ddp tag mask */
	357	unsigned int iscsi_pgsz_order; /* iscsi ddp page size orders */
	358	unsigned int iscsi_llimit; /* chip's iscsi region llimit */
14c19b17	359	unsigned int ulp_crypto; /* crypto lookaside support */
7714cb9e	360	void *iscsi_ppm; / iscsi page pod manager */
982b81eb	361	int nodeid; /* device numa node id */
086de575	362	bool fr_nsmr_tpte_wr_support; /* FW supports FR_NSMR_TPTE_WR */
43db9296	363	bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
f3910c62	364	bool write_cmpl_support; /* FW supports WRITE_CMPL WR */
625ba2c2 DM	365	};
	366
	367	struct cxgb4_uld_info {
1a91649f	368	char name[IFNAMSIZ];
94cdb8bb HS	369	void *handle;
94cdb8bb HS	370	unsigned int nrxq;
94cdb8bb	371	unsigned int rxq_size;
ab677ff4	372	unsigned int ntxq;
0fbc81b3 HS	373	bool ciq;
0fbc81b3 HS	374	bool lro;
94cdb8bb HS	375	void (add)(const struct cxgb4_lld_info *p);
	376	int (rx_handler)(void handle, const __be64 *rsp,
	377	const struct pkt_gl *gl);
	378	int (state_change)(void handle, enum cxgb4_state new_state);
	379	int (control)(void handle, enum cxgb4_control control, ...);
	380	int (lro_rx_handler)(void handle, const __be64 *rsp,
	381	const struct pkt_gl *gl,
	382	struct t4_lro_mgr *lro_mgr,
	383	struct napi_struct *napi);
	384	void (lro_flush)(struct t4_lro_mgr );
a6ec572b	385	int (tx_handler)(struct sk_buff skb, struct net_device *dev);
94cdb8bb HS	386	};
94cdb8bb HS	387
40b06553	388	void cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p);
625ba2c2 DM	389	int cxgb4_unregister_uld(enum cxgb4_uld type);
625ba2c2 DM	390	int cxgb4_ofld_send(struct net_device dev, struct sk_buff skb);
e383f248 AG	391	int cxgb4_immdata_send(struct net_device *dev, unsigned int idx,
e383f248 AG	392	const void *src, unsigned int len);
ab677ff4	393	int cxgb4_crypto_send(struct net_device dev, struct sk_buff skb);
881806bc	394	unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo);
625ba2c2 DM	395	unsigned int cxgb4_port_chan(const struct net_device *dev);
625ba2c2 DM	396	unsigned int cxgb4_port_viid(const struct net_device *dev);
27999805	397	unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid);
625ba2c2	398	unsigned int cxgb4_port_idx(const struct net_device *dev);
625ba2c2 DM	399	unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
625ba2c2 DM	400	unsigned int *idx);
92e7ae71 HS	401	unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
	402	unsigned short header_size,
	403	unsigned short data_size_max,
	404	unsigned short data_size_align,
	405	unsigned int *mtu_idxp);
625ba2c2 DM	406	void cxgb4_get_tcp_stats(struct pci_dev pdev, struct tp_tcp_stats v4,
	407	struct tp_tcp_stats *v6);
	408	void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
	409	const unsigned int *pgsz_order);
	410	struct sk_buff cxgb4_pktgl_to_skb(const struct pkt_gl gl,
	411	unsigned int skb_len, unsigned int pull_len);
3069ee9b VP	412	int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size);
3069ee9b VP	413	int cxgb4_flush_eq_cache(struct net_device *dev);
031cf476	414	int cxgb4_read_tpte(struct net_device dev, u32 stag, __be32 tpte);
7730b4c7	415	u64 cxgb4_read_sge_timestamp(struct net_device *dev);
3cbdb928	416
df64e4d3 HS	417	enum cxgb4_bar2_qtype { CXGB4_BAR2_QTYPE_EGRESS, CXGB4_BAR2_QTYPE_INGRESS };
	418	int cxgb4_bar2_sge_qregs(struct net_device *dev,
	419	unsigned int qid,
	420	enum cxgb4_bar2_qtype qtype,
66cf188e	421	int user,
df64e4d3 HS	422	u64 *pbar2_qoffset,
	423	unsigned int *pbar2_qid);
	424
94cdb8bb	425	#endif /* !__CXGB4_ULD_H */